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int64 1
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int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
JosiCoder/CtLab
|
FPGA/SPI Interface/Source/SPI_SlaveReceiver.vhd
| 1 | 5,036 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides an SPI slave receiver consisting of an address decoder, an address
-- buffer, a receiver deserializer and several receiver buffers each having its
-- own enable signal. The data width is fixed (see data_width constant value in
-- the Globals package).
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
-- Note: It's not possible to use generics for both the data width and the number
-- of buffers to be generated. This would need a signal that is an array of
-- unconstrained arrays which is not yet supported by VHDL. Thus, the data width
-- is fixed (see Globals package).
entity SPI_SlaveReceiver is
generic
(
-- The width of the address.
address_width: positive
);
port
(
-- The system clock.
clk: in std_logic;
-- Controls when the received data are passed to the output (triggered
-- on the rising edge, synchronous to CLK).
buffer_enable: in std_logic;
-- The clock controlling the serial data transmission.
sclk: in std_logic;
-- The (active low) address slave select.
ss_address: in std_logic;
-- The serial input.
mosi: in std_logic;
-- The parallel output providing the address received most recently
-- (this might be used by the transmitter).
address: out unsigned(address_width-1 downto 0) := (others => '0');
-- The parallel outputs providing the data received.
data_x: out data_buffer_vector((2**address_width)-1 downto 0);
-- Indicates for each buffer whether the received data are stable.
ready_x: out std_logic_vector((2**address_width)-1 downto 0)
);
end entity;
architecture stdarch of SPI_SlaveReceiver is
constant number_of_data_buffers: positive := 2**address_width;
signal address_int: unsigned(address_width-1 downto 0) := (others => '0');
signal receiver_data: data_buffer;
-- Signals for n data buffers.
signal buffer_enable_x_int: std_logic_vector(number_of_data_buffers-1 downto 0);
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
-- Internal connections.
address <= address_int;
-- The address decoder.
address_decoder: entity work.SPI_SlaveAddressDecoder
generic map
(
address_width => address_width
)
port map
(
buffer_enable => buffer_enable,
address => address_int,
buffer_enable_x => buffer_enable_x_int
);
-- The shared slave receiver deserializer.
deserializer: entity work.SPI_SlaveReceiverDeserializer
generic map
(
width => data_width
)
port map
(
sclk => sclk,
mosi => mosi,
data => receiver_data
);
-- The output data buffer (sensitive to the rising edge of the enable signal;
-- synchronous to clk).
data_buffers: for i in 0 to number_of_data_buffers-1 generate
data_buffer: entity work.SPI_SlaveDataBuffer
generic map
(
width => data_width,
edge_triggered => true
)
port map
(
clk => clk,
buffer_enable => buffer_enable_x_int(i),
data => receiver_data,
buffered_data => data_x(i),
ready => ready_x(i)
);
end generate;
--------------------------------------------------------------------------------
-- Address register.
--------------------------------------------------------------------------------
address_register: process is
begin
wait until rising_edge(ss_address);
address_int <= unsigned(receiver_data(address_width-1 downto 0));
end process;
end architecture;
|
gpl-3.0
|
befbe71b27868718e4d7b8585d4bdd95
| 0.545075 | 4.903603 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
pid_table_ram.vhd
| 1 | 11,378 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: pid_table_ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pid_table_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END pid_table_ram;
ARCHITECTURE SYN OF pid_table_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_b : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(7 DOWNTO 0);
q_b <= sub_wire1(0 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
intended_device_family => "Cyclone IV GX",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 2048,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
read_during_write_mode_mixed_ports => "DONT_CARE",
read_during_write_mode_port_a => "OLD_DATA",
read_during_write_mode_port_b => "OLD_DATA",
widthad_a => 8,
widthad_b => 11,
width_a => 8,
width_b => 1,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
clock0 => clock,
wren_a => wren_a,
address_b => address_b,
data_b => data_b,
wren_b => wren_b,
address_a => address_a,
data_a => data_a,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
-- Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
-- Retrieval info: USED_PORT: data_b 0 0 1 0 INPUT NODEFVAL "data_b[0..0]"
-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
-- Retrieval info: USED_PORT: q_b 0 0 1 0 OUTPUT NODEFVAL "q_b[0..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
-- Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
-- Retrieval info: CONNECT: @data_b 0 0 1 0 data_b 0 0 1 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: q_b 0 0 1 0 @q_b 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pid_table_ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pid_table_ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pid_table_ram.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pid_table_ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pid_table_ram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-3.0
|
3abe5344ed83c9684ac31e37e72e770c
| 0.678327 | 3.252716 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/ipcore_dir/multiplier.vhd
| 1 | 5,880 |
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- Generated from component ID: xilinx.com:ip:cmpy:3.1
-- You must compile the wrapper file multiplier.vhd when simulating
-- the core, multiplier. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY multiplier IS
port (
ar: in std_logic_vector(17 downto 0);
ai: in std_logic_vector(17 downto 0);
br: in std_logic_vector(17 downto 0);
bi: in std_logic_vector(17 downto 0);
clk: in std_logic;
pr: out std_logic_vector(21 downto 0);
pi: out std_logic_vector(21 downto 0));
END multiplier;
ARCHITECTURE multiplier_a OF multiplier IS
-- synthesis translate_off
component wrapped_multiplier
port (
ar: in std_logic_vector(17 downto 0);
ai: in std_logic_vector(17 downto 0);
br: in std_logic_vector(17 downto 0);
bi: in std_logic_vector(17 downto 0);
clk: in std_logic;
pr: out std_logic_vector(21 downto 0);
pi: out std_logic_vector(21 downto 0));
end component;
-- Configuration specification
for all : wrapped_multiplier use entity XilinxCoreLib.cmpy_v3_1(behavioral)
generic map(
c_a_width => 18,
c_ce_overrides_sclr => 0,
has_negate => 0,
c_has_sclr => 0,
c_out_high => 36,
c_verbosity => 0,
c_mult_type => 1,
c_latency => 4,
c_xdevice => "xc6slx9",
c_has_ce => 0,
single_output => 0,
round => 0,
use_dsp_cascades => 1,
c_optimize_goal => 1,
c_xdevicefamily => "spartan6",
c_out_low => 15,
c_b_width => 18);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_multiplier
port map (
ar => ar,
ai => ai,
br => br,
bi => bi,
clk => clk,
pr => pr,
pi => pi);
-- synthesis translate_on
END multiplier_a;
|
gpl-3.0
|
b4ec103ec65bbcd78ccee6a3bb0b9a5c
| 0.529762 | 4.600939 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
testbench/dvb_source.vhd
| 1 | 1,916 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dvb_source is
generic (
CLOCK_RATE_MHZ : natural := 11;
INTERPACKET_GAP : natural := 0;
INTEROCTET_GAP : natural := 0
);
port (
ts_clk : out std_logic;
ts_strt : out std_logic;
ts_dval : out std_logic;
ts_data : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of dvb_source is
constant t_clk_h : natural := 1000 / CLOCK_RATE_MHZ;
constant t_clk_l : natural := t_clk_h;
signal clk : std_logic := '0';
begin
ts_clk <= clk;
process
begin
wait for t_clk_l * 1 ns;
clk <= '1';
wait for t_clk_h * 1 ns;
clk <= '0';
end process;
process
variable octet : unsigned(7 downto 0);
begin
octet := (others => '0');
loop
wait until falling_edge(clk);
ts_strt <= '1';
ts_dval <= '1';
ts_data <= X"47";
for i in 1 to INTEROCTET_GAP loop
wait until falling_edge(clk);
ts_dval <= '0';
end loop;
--
wait until falling_edge(clk);
ts_strt <= '0';
ts_dval <= '1';
ts_data <= X"1F";
for i in 1 to INTEROCTET_GAP loop
wait until falling_edge(clk);
ts_dval <= '0';
end loop;
--
wait until falling_edge(clk);
ts_dval <= '1';
ts_data <= X"FF";
for i in 1 to INTEROCTET_GAP loop
wait until falling_edge(clk);
ts_dval <= '0';
end loop;
--
for j in 3 to 187 loop
wait until falling_edge(clk);
ts_dval <= '1';
ts_data <= std_logic_vector(octet);
octet := octet + 1;
for i in 1 to INTEROCTET_GAP loop
wait until falling_edge(clk);
ts_dval <= '0';
end loop;
end loop;
--
for i in 1 to INTERPACKET_GAP loop
wait until falling_edge(clk);
ts_dval <= '0';
ts_data <= (others => '0');
end loop;
end loop;
end process;
end;
|
gpl-3.0
|
be09bbb1791f55e2d841019f7e28cbcb
| 0.590292 | 2.65374 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_auto_cc_0/bd_auto_cc_0_sim_netlist.vhdl
| 1 | 741,103 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Apr 14 18:39:27 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top bd_auto_cc_0 -prefix
-- bd_auto_cc_0_ bd_auto_cc_0_sim_netlist.vhdl
-- Design : bd_auto_cc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_dmem is
port (
dout_i : out STD_LOGIC_VECTOR ( 64 downto 0 );
s_aclk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
DI : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
end bd_auto_cc_0_dmem;
architecture STRUCTURE of bd_auto_cc_0_dmem is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_3 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_4 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_5 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_0 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_1 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_2 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_3 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_64 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(1 downto 0),
DIB(1 downto 0) => DI(3 downto 2),
DIC(1 downto 0) => DI(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(13 downto 12),
DIB(1 downto 0) => DI(15 downto 14),
DIC(1 downto 0) => DI(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(19 downto 18),
DIB(1 downto 0) => DI(21 downto 20),
DIC(1 downto 0) => DI(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(25 downto 24),
DIB(1 downto 0) => DI(27 downto 26),
DIC(1 downto 0) => DI(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(31 downto 30),
DIB(1 downto 0) => DI(33 downto 32),
DIC(1 downto 0) => DI(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(37 downto 36),
DIB(1 downto 0) => DI(39 downto 38),
DIC(1 downto 0) => DI(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(43 downto 42),
DIB(1 downto 0) => DI(45 downto 44),
DIC(1 downto 0) => DI(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(49 downto 48),
DIB(1 downto 0) => DI(51 downto 50),
DIC(1 downto 0) => DI(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(55 downto 54),
DIB(1 downto 0) => DI(57 downto 56),
DIC(1 downto 0) => DI(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_59_n_0,
DOA(0) => RAM_reg_0_15_54_59_n_1,
DOB(1) => RAM_reg_0_15_54_59_n_2,
DOB(0) => RAM_reg_0_15_54_59_n_3,
DOC(1) => RAM_reg_0_15_54_59_n_4,
DOC(0) => RAM_reg_0_15_54_59_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_60_64: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(61 downto 60),
DIB(1 downto 0) => DI(63 downto 62),
DIC(1) => '0',
DIC(0) => DI(64),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_60_64_n_0,
DOA(0) => RAM_reg_0_15_60_64_n_1,
DOB(1) => RAM_reg_0_15_60_64_n_2,
DOB(0) => RAM_reg_0_15_60_64_n_3,
DOC(1) => NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED(1),
DOC(0) => RAM_reg_0_15_60_64_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(7 downto 6),
DIB(1 downto 0) => DI(9 downto 8),
DIC(1 downto 0) => DI(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => dout_i(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => dout_i(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => dout_i(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => dout_i(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => dout_i(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => dout_i(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => dout_i(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => dout_i(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => dout_i(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => dout_i(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => dout_i(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => dout_i(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => dout_i(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => dout_i(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => dout_i(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => dout_i(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => dout_i(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => dout_i(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => dout_i(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => dout_i(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => dout_i(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => dout_i(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => dout_i(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => dout_i(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => dout_i(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => dout_i(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => dout_i(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => dout_i(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => dout_i(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => dout_i(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => dout_i(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => dout_i(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => dout_i(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => dout_i(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => dout_i(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => dout_i(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => dout_i(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => dout_i(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => dout_i(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => dout_i(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => dout_i(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => dout_i(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => dout_i(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => dout_i(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => dout_i(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => dout_i(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => dout_i(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => dout_i(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => dout_i(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_1,
Q => dout_i(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_0,
Q => dout_i(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_3,
Q => dout_i(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_2,
Q => dout_i(57),
R => '0'
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_5,
Q => dout_i(58),
R => '0'
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_4,
Q => dout_i(59),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => dout_i(5),
R => '0'
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_1,
Q => dout_i(60),
R => '0'
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_0,
Q => dout_i(61),
R => '0'
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_3,
Q => dout_i(62),
R => '0'
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_2,
Q => dout_i(63),
R => '0'
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_5,
Q => dout_i(64),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => dout_i(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => dout_i(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => dout_i(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => dout_i(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_dmem_81 is
port (
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_dmem_81 : entity is "dmem";
end bd_auto_cc_0_dmem_81;
architecture STRUCTURE of bd_auto_cc_0_dmem_81 is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_3 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_4 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_5 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_0 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_1 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_2 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_3 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_64 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(1 downto 0),
DIB(1 downto 0) => I123(3 downto 2),
DIC(1 downto 0) => I123(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(13 downto 12),
DIB(1 downto 0) => I123(15 downto 14),
DIC(1 downto 0) => I123(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(19 downto 18),
DIB(1 downto 0) => I123(21 downto 20),
DIC(1 downto 0) => I123(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(25 downto 24),
DIB(1 downto 0) => I123(27 downto 26),
DIC(1 downto 0) => I123(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(31 downto 30),
DIB(1 downto 0) => I123(33 downto 32),
DIC(1 downto 0) => I123(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(37 downto 36),
DIB(1 downto 0) => I123(39 downto 38),
DIC(1 downto 0) => I123(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(43 downto 42),
DIB(1 downto 0) => I123(45 downto 44),
DIC(1 downto 0) => I123(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(49 downto 48),
DIB(1 downto 0) => I123(51 downto 50),
DIC(1 downto 0) => I123(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(55 downto 54),
DIB(1 downto 0) => I123(57 downto 56),
DIC(1 downto 0) => I123(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_59_n_0,
DOA(0) => RAM_reg_0_15_54_59_n_1,
DOB(1) => RAM_reg_0_15_54_59_n_2,
DOB(0) => RAM_reg_0_15_54_59_n_3,
DOC(1) => RAM_reg_0_15_54_59_n_4,
DOC(0) => RAM_reg_0_15_54_59_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_60_64: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(61 downto 60),
DIB(1 downto 0) => I123(63 downto 62),
DIC(1) => '0',
DIC(0) => I123(64),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_60_64_n_0,
DOA(0) => RAM_reg_0_15_60_64_n_1,
DOB(1) => RAM_reg_0_15_60_64_n_2,
DOB(0) => RAM_reg_0_15_60_64_n_3,
DOC(1) => NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED(1),
DOC(0) => RAM_reg_0_15_60_64_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(7 downto 6),
DIB(1 downto 0) => I123(9 downto 8),
DIC(1 downto 0) => I123(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => Q(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => Q(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => Q(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => Q(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => Q(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => Q(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => Q(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => Q(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => Q(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => Q(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => Q(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => Q(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => Q(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => Q(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => Q(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_1,
Q => Q(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_0,
Q => Q(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_3,
Q => Q(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_2,
Q => Q(57),
R => '0'
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_5,
Q => Q(58),
R => '0'
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_4,
Q => Q(59),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_1,
Q => Q(60),
R => '0'
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_0,
Q => Q(61),
R => '0'
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_3,
Q => Q(62),
R => '0'
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_2,
Q => Q(63),
R => '0'
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_5,
Q => Q(64),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_dmem__parameterized0\ is
port (
Q : out STD_LOGIC_VECTOR ( 36 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_dmem__parameterized0\ : entity is "dmem";
end \bd_auto_cc_0_dmem__parameterized0\;
architecture STRUCTURE of \bd_auto_cc_0_dmem__parameterized0\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_36_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_36_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_36_36_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_36_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_36_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_36 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(1 downto 0),
DIB(1 downto 0) => I115(3 downto 2),
DIC(1 downto 0) => I115(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(13 downto 12),
DIB(1 downto 0) => I115(15 downto 14),
DIC(1 downto 0) => I115(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(19 downto 18),
DIB(1 downto 0) => I115(21 downto 20),
DIC(1 downto 0) => I115(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(25 downto 24),
DIB(1 downto 0) => I115(27 downto 26),
DIC(1 downto 0) => I115(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(31 downto 30),
DIB(1 downto 0) => I115(33 downto 32),
DIC(1 downto 0) => I115(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_36_36: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1) => '0',
DIA(0) => I115(36),
DIB(1 downto 0) => B"00",
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => NLW_RAM_reg_0_15_36_36_DOA_UNCONNECTED(1),
DOA(0) => RAM_reg_0_15_36_36_n_1,
DOB(1 downto 0) => NLW_RAM_reg_0_15_36_36_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_15_36_36_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_36_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(7 downto 6),
DIB(1 downto 0) => I115(9 downto 8),
DIC(1 downto 0) => I115(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_36_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_dmem__parameterized1\ is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_dmem__parameterized1\ : entity is "dmem";
end \bd_auto_cc_0_dmem__parameterized1\;
architecture STRUCTURE of \bd_auto_cc_0_dmem__parameterized1\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => m_axi_bresp(1 downto 0),
DIB(1 downto 0) => m_axi_bid(1 downto 0),
DIC(1 downto 0) => m_axi_bid(3 downto 2),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_dmem__parameterized2\ is
port (
Q : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_dmem__parameterized2\ : entity is "dmem";
end \bd_auto_cc_0_dmem__parameterized2\;
architecture STRUCTURE of \bd_auto_cc_0_dmem__parameterized2\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_38_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_38_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_38_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_38_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_36_38_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_38_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_38 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(1 downto 0),
DIB(1 downto 0) => I127(3 downto 2),
DIC(1 downto 0) => I127(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(13 downto 12),
DIB(1 downto 0) => I127(15 downto 14),
DIC(1 downto 0) => I127(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(19 downto 18),
DIB(1 downto 0) => I127(21 downto 20),
DIC(1 downto 0) => I127(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(25 downto 24),
DIB(1 downto 0) => I127(27 downto 26),
DIC(1 downto 0) => I127(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(31 downto 30),
DIB(1 downto 0) => I127(33 downto 32),
DIC(1 downto 0) => I127(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_36_38: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(37 downto 36),
DIB(1) => '0',
DIB(0) => I127(38),
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_38_n_0,
DOA(0) => RAM_reg_0_15_36_38_n_1,
DOB(1) => NLW_RAM_reg_0_15_36_38_DOB_UNCONNECTED(1),
DOB(0) => RAM_reg_0_15_36_38_n_3,
DOC(1 downto 0) => NLW_RAM_reg_0_15_36_38_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_38_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(7 downto 6),
DIB(1 downto 0) => I127(9 downto 8),
DIC(1 downto 0) => I127(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_38_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_38_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_38_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_rd_bin_cntr;
architecture STRUCTURE of bd_auto_cc_0_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__6\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__2_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__2\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__2\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__2\ : label is "soft_lutpair27";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__6\(0)
);
\gc0.count[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__6\(1)
);
\gc0.count[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__6\(2)
);
\gc0.count[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__6\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__6\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__6\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__6\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__6\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__2_n_0\,
I1 => \ram_empty_i_i_3__2_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__2_n_0\
);
\ram_empty_i_i_3__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_bin_cntr_20 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_bin_cntr_20 : entity is "rd_bin_cntr";
end bd_auto_cc_0_rd_bin_cntr_20;
architecture STRUCTURE of bd_auto_cc_0_rd_bin_cntr_20 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__0\ : label is "soft_lutpair21";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__0\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__0_n_0\,
I1 => \ram_empty_i_i_3__0_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__0_n_0\
);
\ram_empty_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_bin_cntr_41 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_bin_cntr_41 : entity is "rd_bin_cntr";
end bd_auto_cc_0_rd_bin_cntr_41;
architecture STRUCTURE of bd_auto_cc_0_rd_bin_cntr_41 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_i_i_3_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of ram_empty_i_i_2 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of ram_empty_i_i_3 : label is "soft_lutpair15";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => plusOp(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => ram_empty_i_i_2_n_0,
I1 => ram_empty_i_i_3_n_0,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
ram_empty_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => ram_empty_i_i_2_n_0
);
ram_empty_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => ram_empty_i_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_bin_cntr_62 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_bin_cntr_62 : entity is "rd_bin_cntr";
end bd_auto_cc_0_rd_bin_cntr_62;
architecture STRUCTURE of bd_auto_cc_0_rd_bin_cntr_62 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__3_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__3\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__3\ : label is "soft_lutpair9";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__8\(0)
);
\gc0.count[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__8\(1)
);
\gc0.count[2]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__8\(2)
);
\gc0.count[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__8\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__8\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__3_n_0\,
I1 => \ram_empty_i_i_3__3_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__3_n_0\
);
\ram_empty_i_i_3__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_bin_cntr_86 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_bin_cntr_86 : entity is "rd_bin_cntr";
end bd_auto_cc_0_rd_bin_cntr_86;
architecture STRUCTURE of bd_auto_cc_0_rd_bin_cntr_86 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__1_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__1\ : label is "soft_lutpair3";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__2\(0)
);
\gc0.count[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__2\(1)
);
\gc0.count[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__2\(2)
);
\gc0.count[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__2\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__2\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__1_n_0\,
I1 => \ram_empty_i_i_3__1_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__1_n_0\
);
\ram_empty_i_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_fwft is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_rd_fwft;
architecture STRUCTURE of bd_auto_cc_0_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => \goreg_dm.dout_i_reg[5]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => s_axi_bready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
\ram_empty_i_i_5__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
s_axi_bvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_fwft_18 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[36]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_fwft_18 : entity is "rd_fwft";
end bd_auto_cc_0_rd_fwft_18;
architecture STRUCTURE of bd_auto_cc_0_rd_fwft_18 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[36]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => \goreg_dm.dout_i_reg[36]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_wready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_wvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_wvalid
);
\ram_empty_i_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_fwft_39 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_fwft_39 : entity is "rd_fwft";
end bd_auto_cc_0_rd_fwft_39;
architecture STRUCTURE of bd_auto_cc_0_rd_fwft_39 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[64]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => \goreg_dm.dout_i_reg[64]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_awready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_awvalid
);
ram_empty_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_fwft_60 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[38]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_fwft_60 : entity is "rd_fwft";
end bd_auto_cc_0_rd_fwft_60;
architecture STRUCTURE of bd_auto_cc_0_rd_fwft_60 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[38]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => \goreg_dm.dout_i_reg[38]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => s_axi_rready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
\ram_empty_i_i_5__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_fwft_84 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_fwft_84 : entity is "rd_fwft";
end bd_auto_cc_0_rd_fwft_84;
architecture STRUCTURE of bd_auto_cc_0_rd_fwft_84 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[64]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => \goreg_dm.dout_i_reg[64]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_arready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_arvalid
);
\ram_empty_i_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_status_flags_as is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_rd_status_flags_as;
architecture STRUCTURE of bd_auto_cc_0_rd_status_flags_as is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_status_flags_as_19 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_status_flags_as_19 : entity is "rd_status_flags_as";
end bd_auto_cc_0_rd_status_flags_as_19;
architecture STRUCTURE of bd_auto_cc_0_rd_status_flags_as_19 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_status_flags_as_40 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_status_flags_as_40 : entity is "rd_status_flags_as";
end bd_auto_cc_0_rd_status_flags_as_40;
architecture STRUCTURE of bd_auto_cc_0_rd_status_flags_as_40 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_status_flags_as_61 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_status_flags_as_61 : entity is "rd_status_flags_as";
end bd_auto_cc_0_rd_status_flags_as_61;
architecture STRUCTURE of bd_auto_cc_0_rd_status_flags_as_61 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_status_flags_as_85 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_status_flags_as_85 : entity is "rd_status_flags_as";
end bd_auto_cc_0_rd_status_flags_as_85;
architecture STRUCTURE of bd_auto_cc_0_rd_status_flags_as_85 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
end bd_auto_cc_0_synchronizer_ff;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_1 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_1 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_1;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_10 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_10 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_10;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_10 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_11 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_11 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_11;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_11 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_12 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_12 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_12;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_12 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_13 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_13 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_13;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_13 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_14 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_14 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_14;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_14 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_15 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_15 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_15;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_15 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_2 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_2 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_2;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_3 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_3 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_3;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_31 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_31 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_31;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_31 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_32 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_32 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_32;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_32 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_33 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_33 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_33;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_33 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_34 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_34 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_34;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_34 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_35 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_35 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_35;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_35 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_36 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_36 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_36;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_36 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_4 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_4 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_4;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_5 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_5 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_5;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_52 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_52 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_52;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_52 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_53 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_53 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_53;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_53 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_54 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_54 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_54;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_54 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_55 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_55 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_55;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_55 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_56 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_56 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_56;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_56 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_57 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_57 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_57;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_57 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_75 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_75 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_75;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_75 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_76 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_76 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_76;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_76 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_77 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_77 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_77;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_77 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_78 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_78 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_78;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_78 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_79 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_79 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_79;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_79 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_80 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_80 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_80;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_80 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized0_21\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized0_21\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized0_21\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized0_21\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized0_42\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized0_42\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized0_42\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized0_42\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized0_63\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized0_63\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized0_63\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized0_63\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized0_87\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized0_87\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized0_87\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized0_87\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized1_22\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized1_22\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized1_22\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized1_22\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized1_43\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized1_43\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized1_43\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized1_43\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized1_64\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized1_64\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized1_64\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized1_64\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized1_88\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized1_88\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized1_88\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized1_88\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized2\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized2_23\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized2_23\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized2_23\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized2_23\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized2_44\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized2_44\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized2_44\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized2_44\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized2_65\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized2_65\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized2_65\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized2_65\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized2_89\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized2_89\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized2_89\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized2_89\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized3\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized3_24\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized3_24\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized3_24\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized3_24\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized3_45\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized3_45\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized3_45\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized3_45\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized3_66\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized3_66\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized3_66\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized3_66\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized3_90\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized3_90\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized3_90\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized3_90\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized4\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized4\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized4\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized4\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized4_25\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized4_25\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized4_25\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized4_25\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized4_46\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized4_46\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized4_46\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized4_46\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized4_67\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized4_67\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized4_67\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized4_67\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized4_91\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized4_91\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized4_91\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized4_91\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized5\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized5\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized5\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized5\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized5_26\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized5_26\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized5_26\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized5_26\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized5_47\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized5_47\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized5_47\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized5_47\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized5_68\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized5_68\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized5_68\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized5_68\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized5_92\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized5_92\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized5_92\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized5_92\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_wr_bin_cntr;
architecture STRUCTURE of bd_auto_cc_0_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair29";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_bin_cntr_17 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_bin_cntr_17 : entity is "wr_bin_cntr";
end bd_auto_cc_0_wr_bin_cntr_17;
architecture STRUCTURE of bd_auto_cc_0_wr_bin_cntr_17 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__2\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__2\ : label is "soft_lutpair23";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__5\(0)
);
\gic0.gc0.count[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__5\(1)
);
\gic0.gc0.count[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__5\(2)
);
\gic0.gc0.count[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__5\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__5\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_bin_cntr_38 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_bin_cntr_38 : entity is "wr_bin_cntr";
end bd_auto_cc_0_wr_bin_cntr_38;
architecture STRUCTURE of bd_auto_cc_0_wr_bin_cntr_38 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__1\ : label is "soft_lutpair17";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__4\(0)
);
\gic0.gc0.count[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__4\(1)
);
\gic0.gc0.count[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__4\(2)
);
\gic0.gc0.count[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__4\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__4\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_bin_cntr_59 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_bin_cntr_59 : entity is "wr_bin_cntr";
end bd_auto_cc_0_wr_bin_cntr_59;
architecture STRUCTURE of bd_auto_cc_0_wr_bin_cntr_59 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__0\ : label is "soft_lutpair11";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__3\(0)
);
\gic0.gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__3\(1)
);
\gic0.gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__3\(2)
);
\gic0.gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__3\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__3\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_bin_cntr_83 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_bin_cntr_83 : entity is "wr_bin_cntr";
end bd_auto_cc_0_wr_bin_cntr_83;
architecture STRUCTURE of bd_auto_cc_0_wr_bin_cntr_83 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__3\ : label is "soft_lutpair5";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__7\(0)
);
\gic0.gc0.count[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__7\(1)
);
\gic0.gc0.count[2]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__7\(2)
);
\gic0.gc0.count[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__7\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__7\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_status_flags_as is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_wr_status_flags_as;
architecture STRUCTURE of bd_auto_cc_0_wr_status_flags_as is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_bvalid,
I1 => ram_full_fb_i,
O => E(0)
);
m_axi_bready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => m_axi_bready
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => m_axi_bvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_status_flags_as_16 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_status_flags_as_16 : entity is "wr_status_flags_as";
end bd_auto_cc_0_wr_status_flags_as_16;
architecture STRUCTURE of bd_auto_cc_0_wr_status_flags_as_16 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_wvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_wready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_wready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_status_flags_as_37 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_status_flags_as_37 : entity is "wr_status_flags_as";
end bd_auto_cc_0_wr_status_flags_as_37;
architecture STRUCTURE of bd_auto_cc_0_wr_status_flags_as_37 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_awvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_awready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_awready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_status_flags_as_58 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_status_flags_as_58 : entity is "wr_status_flags_as";
end bd_auto_cc_0_wr_status_flags_as_58;
architecture STRUCTURE of bd_auto_cc_0_wr_status_flags_as_58 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_rvalid,
I1 => ram_full_fb_i,
O => E(0)
);
m_axi_rready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => m_axi_rready
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => m_axi_rvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_status_flags_as_82 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_status_flags_as_82 : entity is "wr_status_flags_as";
end bd_auto_cc_0_wr_status_flags_as_82;
architecture STRUCTURE of bd_auto_cc_0_wr_status_flags_as_82 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_arvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_arvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_arready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_clk_x_pntrs is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_clk_x_pntrs;
architecture STRUCTURE of bd_auto_cc_0_clk_x_pntrs is
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair25";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized0\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized2\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized4\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized5\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
m_aclk => m_aclk,
\out\(3 downto 0) => p_8_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^ram_empty_i_reg_0\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^ram_empty_i_reg_0\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^ram_empty_i_reg_0\(0),
O => ram_empty_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => ram_full_i_i_2_n_0,
I1 => ram_full_fb_i_reg_1,
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => ram_full_i_i_4_n_0,
O => ram_full_fb_i_reg
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => ram_full_i_i_2_n_0
);
ram_full_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => Q(2),
I2 => p_23_out(1),
I3 => Q(1),
I4 => Q(0),
I5 => p_23_out(0),
O => ram_full_i_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_clk_x_pntrs_27 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_clk_x_pntrs_27 : entity is "clk_x_pntrs";
end bd_auto_cc_0_clk_x_pntrs_27;
architecture STRUCTURE of bd_auto_cc_0_clk_x_pntrs_27 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_23_out_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__1_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__1_n_0\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair13";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => gray2bin(1)
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized0_42\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3 downto 0) => wr_pntr_gc(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized1_43\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3 downto 0) => rd_pntr_gc(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized2_44\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized3_45\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized4_46\
port map (
D(0) => p_0_out,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized5_47\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out_1(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out_1(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out_1(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(0),
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(1),
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(2),
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => wr_pntr_gc(3)
);
ram_empty_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__1_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__1_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out_1(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out_1(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out_1(0),
O => \ram_full_i_i_2__1_n_0\
);
\ram_full_i_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out_1(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out_1(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out_1(0),
O => \ram_full_i_i_4__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_clk_x_pntrs_48 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_clk_x_pntrs_48 : entity is "clk_x_pntrs";
end bd_auto_cc_0_clk_x_pntrs_48;
architecture STRUCTURE of bd_auto_cc_0_clk_x_pntrs_48 is
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair7";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized0_63\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized1_64\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized2_65\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized3_66\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized4_67\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized5_68\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
m_aclk => m_aclk,
\out\(3 downto 0) => p_8_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^ram_empty_i_reg_0\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^ram_empty_i_reg_0\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^ram_empty_i_reg_0\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__0_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__0_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__0_n_0\
);
\ram_full_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => Q(2),
I2 => p_23_out(1),
I3 => Q(1),
I4 => Q(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_clk_x_pntrs_6 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_clk_x_pntrs_6 : entity is "clk_x_pntrs";
end bd_auto_cc_0_clk_x_pntrs_6;
architecture STRUCTURE of bd_auto_cc_0_clk_x_pntrs_6 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__2_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair19";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized0_21\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized1_22\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized2_23\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized3_24\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized4_25\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized5_26\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__2_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__2_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__2_n_0\
);
\ram_full_i_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_clk_x_pntrs_70 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_clk_x_pntrs_70 : entity is "clk_x_pntrs";
end bd_auto_cc_0_clk_x_pntrs_70;
architecture STRUCTURE of bd_auto_cc_0_clk_x_pntrs_70 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__3_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized0_87\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized1_88\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized2_89\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized3_90\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized4_91\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized5_92\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__3_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__3_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__3_n_0\
);
\ram_full_i_i_4__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_memory is
port (
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
DI : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_memory;
architecture STRUCTURE of bd_auto_cc_0_memory is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_58\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_59\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_60\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_61\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_62\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_63\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_64\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.bd_auto_cc_0_dmem
port map (
DI(64 downto 0) => DI(64 downto 0),
dout_i(64) => \gdm.dm_gen.dm_n_0\,
dout_i(63) => \gdm.dm_gen.dm_n_1\,
dout_i(62) => \gdm.dm_gen.dm_n_2\,
dout_i(61) => \gdm.dm_gen.dm_n_3\,
dout_i(60) => \gdm.dm_gen.dm_n_4\,
dout_i(59) => \gdm.dm_gen.dm_n_5\,
dout_i(58) => \gdm.dm_gen.dm_n_6\,
dout_i(57) => \gdm.dm_gen.dm_n_7\,
dout_i(56) => \gdm.dm_gen.dm_n_8\,
dout_i(55) => \gdm.dm_gen.dm_n_9\,
dout_i(54) => \gdm.dm_gen.dm_n_10\,
dout_i(53) => \gdm.dm_gen.dm_n_11\,
dout_i(52) => \gdm.dm_gen.dm_n_12\,
dout_i(51) => \gdm.dm_gen.dm_n_13\,
dout_i(50) => \gdm.dm_gen.dm_n_14\,
dout_i(49) => \gdm.dm_gen.dm_n_15\,
dout_i(48) => \gdm.dm_gen.dm_n_16\,
dout_i(47) => \gdm.dm_gen.dm_n_17\,
dout_i(46) => \gdm.dm_gen.dm_n_18\,
dout_i(45) => \gdm.dm_gen.dm_n_19\,
dout_i(44) => \gdm.dm_gen.dm_n_20\,
dout_i(43) => \gdm.dm_gen.dm_n_21\,
dout_i(42) => \gdm.dm_gen.dm_n_22\,
dout_i(41) => \gdm.dm_gen.dm_n_23\,
dout_i(40) => \gdm.dm_gen.dm_n_24\,
dout_i(39) => \gdm.dm_gen.dm_n_25\,
dout_i(38) => \gdm.dm_gen.dm_n_26\,
dout_i(37) => \gdm.dm_gen.dm_n_27\,
dout_i(36) => \gdm.dm_gen.dm_n_28\,
dout_i(35) => \gdm.dm_gen.dm_n_29\,
dout_i(34) => \gdm.dm_gen.dm_n_30\,
dout_i(33) => \gdm.dm_gen.dm_n_31\,
dout_i(32) => \gdm.dm_gen.dm_n_32\,
dout_i(31) => \gdm.dm_gen.dm_n_33\,
dout_i(30) => \gdm.dm_gen.dm_n_34\,
dout_i(29) => \gdm.dm_gen.dm_n_35\,
dout_i(28) => \gdm.dm_gen.dm_n_36\,
dout_i(27) => \gdm.dm_gen.dm_n_37\,
dout_i(26) => \gdm.dm_gen.dm_n_38\,
dout_i(25) => \gdm.dm_gen.dm_n_39\,
dout_i(24) => \gdm.dm_gen.dm_n_40\,
dout_i(23) => \gdm.dm_gen.dm_n_41\,
dout_i(22) => \gdm.dm_gen.dm_n_42\,
dout_i(21) => \gdm.dm_gen.dm_n_43\,
dout_i(20) => \gdm.dm_gen.dm_n_44\,
dout_i(19) => \gdm.dm_gen.dm_n_45\,
dout_i(18) => \gdm.dm_gen.dm_n_46\,
dout_i(17) => \gdm.dm_gen.dm_n_47\,
dout_i(16) => \gdm.dm_gen.dm_n_48\,
dout_i(15) => \gdm.dm_gen.dm_n_49\,
dout_i(14) => \gdm.dm_gen.dm_n_50\,
dout_i(13) => \gdm.dm_gen.dm_n_51\,
dout_i(12) => \gdm.dm_gen.dm_n_52\,
dout_i(11) => \gdm.dm_gen.dm_n_53\,
dout_i(10) => \gdm.dm_gen.dm_n_54\,
dout_i(9) => \gdm.dm_gen.dm_n_55\,
dout_i(8) => \gdm.dm_gen.dm_n_56\,
dout_i(7) => \gdm.dm_gen.dm_n_57\,
dout_i(6) => \gdm.dm_gen.dm_n_58\,
dout_i(5) => \gdm.dm_gen.dm_n_59\,
dout_i(4) => \gdm.dm_gen.dm_n_60\,
dout_i(3) => \gdm.dm_gen.dm_n_61\,
dout_i(2) => \gdm.dm_gen.dm_n_62\,
dout_i(1) => \gdm.dm_gen.dm_n_63\,
dout_i(0) => \gdm.dm_gen.dm_n_64\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_64\,
Q => Q(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_54\,
Q => Q(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_53\,
Q => Q(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_52\,
Q => Q(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_51\,
Q => Q(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_50\,
Q => Q(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_49\,
Q => Q(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_48\,
Q => Q(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_47\,
Q => Q(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_46\,
Q => Q(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_45\,
Q => Q(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_63\,
Q => Q(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_44\,
Q => Q(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_43\,
Q => Q(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_42\,
Q => Q(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_41\,
Q => Q(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_40\,
Q => Q(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_39\,
Q => Q(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_38\,
Q => Q(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_37\,
Q => Q(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_36\,
Q => Q(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_35\,
Q => Q(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_62\,
Q => Q(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_34\,
Q => Q(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_33\,
Q => Q(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_32\,
Q => Q(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_31\,
Q => Q(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_30\,
Q => Q(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_29\,
Q => Q(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_28\,
Q => Q(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_27\,
Q => Q(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_26\,
Q => Q(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_25\,
Q => Q(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_61\,
Q => Q(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_24\,
Q => Q(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_23\,
Q => Q(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_22\,
Q => Q(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_21\,
Q => Q(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_20\,
Q => Q(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_19\,
Q => Q(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_18\,
Q => Q(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_17\,
Q => Q(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_16\,
Q => Q(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_15\,
Q => Q(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_60\,
Q => Q(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_14\,
Q => Q(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_13\,
Q => Q(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_12\,
Q => Q(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_11\,
Q => Q(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_10\,
Q => Q(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_9\,
Q => Q(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_8\,
Q => Q(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_7\,
Q => Q(57),
R => '0'
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_6\,
Q => Q(58),
R => '0'
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_5\,
Q => Q(59),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_59\,
Q => Q(5),
R => '0'
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_4\,
Q => Q(60),
R => '0'
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_3\,
Q => Q(61),
R => '0'
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_2\,
Q => Q(62),
R => '0'
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_1\,
Q => Q(63),
R => '0'
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_0\,
Q => Q(64),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_58\,
Q => Q(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_57\,
Q => Q(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_56\,
Q => Q(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_55\,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_memory_73 is
port (
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_memory_73 : entity is "memory";
end bd_auto_cc_0_memory_73;
architecture STRUCTURE of bd_auto_cc_0_memory_73 is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_58\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_59\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_60\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_61\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_62\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_63\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_64\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.bd_auto_cc_0_dmem_81
port map (
E(0) => E(0),
I123(64 downto 0) => I123(64 downto 0),
Q(64) => \gdm.dm_gen.dm_n_0\,
Q(63) => \gdm.dm_gen.dm_n_1\,
Q(62) => \gdm.dm_gen.dm_n_2\,
Q(61) => \gdm.dm_gen.dm_n_3\,
Q(60) => \gdm.dm_gen.dm_n_4\,
Q(59) => \gdm.dm_gen.dm_n_5\,
Q(58) => \gdm.dm_gen.dm_n_6\,
Q(57) => \gdm.dm_gen.dm_n_7\,
Q(56) => \gdm.dm_gen.dm_n_8\,
Q(55) => \gdm.dm_gen.dm_n_9\,
Q(54) => \gdm.dm_gen.dm_n_10\,
Q(53) => \gdm.dm_gen.dm_n_11\,
Q(52) => \gdm.dm_gen.dm_n_12\,
Q(51) => \gdm.dm_gen.dm_n_13\,
Q(50) => \gdm.dm_gen.dm_n_14\,
Q(49) => \gdm.dm_gen.dm_n_15\,
Q(48) => \gdm.dm_gen.dm_n_16\,
Q(47) => \gdm.dm_gen.dm_n_17\,
Q(46) => \gdm.dm_gen.dm_n_18\,
Q(45) => \gdm.dm_gen.dm_n_19\,
Q(44) => \gdm.dm_gen.dm_n_20\,
Q(43) => \gdm.dm_gen.dm_n_21\,
Q(42) => \gdm.dm_gen.dm_n_22\,
Q(41) => \gdm.dm_gen.dm_n_23\,
Q(40) => \gdm.dm_gen.dm_n_24\,
Q(39) => \gdm.dm_gen.dm_n_25\,
Q(38) => \gdm.dm_gen.dm_n_26\,
Q(37) => \gdm.dm_gen.dm_n_27\,
Q(36) => \gdm.dm_gen.dm_n_28\,
Q(35) => \gdm.dm_gen.dm_n_29\,
Q(34) => \gdm.dm_gen.dm_n_30\,
Q(33) => \gdm.dm_gen.dm_n_31\,
Q(32) => \gdm.dm_gen.dm_n_32\,
Q(31) => \gdm.dm_gen.dm_n_33\,
Q(30) => \gdm.dm_gen.dm_n_34\,
Q(29) => \gdm.dm_gen.dm_n_35\,
Q(28) => \gdm.dm_gen.dm_n_36\,
Q(27) => \gdm.dm_gen.dm_n_37\,
Q(26) => \gdm.dm_gen.dm_n_38\,
Q(25) => \gdm.dm_gen.dm_n_39\,
Q(24) => \gdm.dm_gen.dm_n_40\,
Q(23) => \gdm.dm_gen.dm_n_41\,
Q(22) => \gdm.dm_gen.dm_n_42\,
Q(21) => \gdm.dm_gen.dm_n_43\,
Q(20) => \gdm.dm_gen.dm_n_44\,
Q(19) => \gdm.dm_gen.dm_n_45\,
Q(18) => \gdm.dm_gen.dm_n_46\,
Q(17) => \gdm.dm_gen.dm_n_47\,
Q(16) => \gdm.dm_gen.dm_n_48\,
Q(15) => \gdm.dm_gen.dm_n_49\,
Q(14) => \gdm.dm_gen.dm_n_50\,
Q(13) => \gdm.dm_gen.dm_n_51\,
Q(12) => \gdm.dm_gen.dm_n_52\,
Q(11) => \gdm.dm_gen.dm_n_53\,
Q(10) => \gdm.dm_gen.dm_n_54\,
Q(9) => \gdm.dm_gen.dm_n_55\,
Q(8) => \gdm.dm_gen.dm_n_56\,
Q(7) => \gdm.dm_gen.dm_n_57\,
Q(6) => \gdm.dm_gen.dm_n_58\,
Q(5) => \gdm.dm_gen.dm_n_59\,
Q(4) => \gdm.dm_gen.dm_n_60\,
Q(3) => \gdm.dm_gen.dm_n_61\,
Q(2) => \gdm.dm_gen.dm_n_62\,
Q(1) => \gdm.dm_gen.dm_n_63\,
Q(0) => \gdm.dm_gen.dm_n_64\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_64\,
Q => \m_axi_arid[3]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_54\,
Q => \m_axi_arid[3]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_53\,
Q => \m_axi_arid[3]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_52\,
Q => \m_axi_arid[3]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_51\,
Q => \m_axi_arid[3]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_50\,
Q => \m_axi_arid[3]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_49\,
Q => \m_axi_arid[3]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_48\,
Q => \m_axi_arid[3]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_47\,
Q => \m_axi_arid[3]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_46\,
Q => \m_axi_arid[3]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_45\,
Q => \m_axi_arid[3]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_63\,
Q => \m_axi_arid[3]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_44\,
Q => \m_axi_arid[3]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_43\,
Q => \m_axi_arid[3]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_42\,
Q => \m_axi_arid[3]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_41\,
Q => \m_axi_arid[3]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_40\,
Q => \m_axi_arid[3]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_39\,
Q => \m_axi_arid[3]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \m_axi_arid[3]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \m_axi_arid[3]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \m_axi_arid[3]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \m_axi_arid[3]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_62\,
Q => \m_axi_arid[3]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \m_axi_arid[3]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \m_axi_arid[3]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \m_axi_arid[3]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \m_axi_arid[3]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \m_axi_arid[3]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \m_axi_arid[3]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \m_axi_arid[3]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \m_axi_arid[3]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \m_axi_arid[3]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \m_axi_arid[3]\(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_61\,
Q => \m_axi_arid[3]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \m_axi_arid[3]\(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \m_axi_arid[3]\(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \m_axi_arid[3]\(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \m_axi_arid[3]\(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \m_axi_arid[3]\(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \m_axi_arid[3]\(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \m_axi_arid[3]\(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \m_axi_arid[3]\(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \m_axi_arid[3]\(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \m_axi_arid[3]\(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_60\,
Q => \m_axi_arid[3]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \m_axi_arid[3]\(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \m_axi_arid[3]\(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \m_axi_arid[3]\(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \m_axi_arid[3]\(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \m_axi_arid[3]\(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \m_axi_arid[3]\(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \m_axi_arid[3]\(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \m_axi_arid[3]\(57),
R => '0'
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \m_axi_arid[3]\(58),
R => '0'
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \m_axi_arid[3]\(59),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_59\,
Q => \m_axi_arid[3]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \m_axi_arid[3]\(60),
R => '0'
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \m_axi_arid[3]\(61),
R => '0'
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \m_axi_arid[3]\(62),
R => '0'
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \m_axi_arid[3]\(63),
R => '0'
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \m_axi_arid[3]\(64),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_58\,
Q => \m_axi_arid[3]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_57\,
Q => \m_axi_arid[3]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_56\,
Q => \m_axi_arid[3]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_55\,
Q => \m_axi_arid[3]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_memory__parameterized0\ is
port (
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_memory__parameterized0\ : entity is "memory";
end \bd_auto_cc_0_memory__parameterized0\;
architecture STRUCTURE of \bd_auto_cc_0_memory__parameterized0\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\bd_auto_cc_0_dmem__parameterized0\
port map (
E(0) => E(0),
I115(36 downto 0) => I115(36 downto 0),
Q(36) => \gdm.dm_gen.dm_n_0\,
Q(35) => \gdm.dm_gen.dm_n_1\,
Q(34) => \gdm.dm_gen.dm_n_2\,
Q(33) => \gdm.dm_gen.dm_n_3\,
Q(32) => \gdm.dm_gen.dm_n_4\,
Q(31) => \gdm.dm_gen.dm_n_5\,
Q(30) => \gdm.dm_gen.dm_n_6\,
Q(29) => \gdm.dm_gen.dm_n_7\,
Q(28) => \gdm.dm_gen.dm_n_8\,
Q(27) => \gdm.dm_gen.dm_n_9\,
Q(26) => \gdm.dm_gen.dm_n_10\,
Q(25) => \gdm.dm_gen.dm_n_11\,
Q(24) => \gdm.dm_gen.dm_n_12\,
Q(23) => \gdm.dm_gen.dm_n_13\,
Q(22) => \gdm.dm_gen.dm_n_14\,
Q(21) => \gdm.dm_gen.dm_n_15\,
Q(20) => \gdm.dm_gen.dm_n_16\,
Q(19) => \gdm.dm_gen.dm_n_17\,
Q(18) => \gdm.dm_gen.dm_n_18\,
Q(17) => \gdm.dm_gen.dm_n_19\,
Q(16) => \gdm.dm_gen.dm_n_20\,
Q(15) => \gdm.dm_gen.dm_n_21\,
Q(14) => \gdm.dm_gen.dm_n_22\,
Q(13) => \gdm.dm_gen.dm_n_23\,
Q(12) => \gdm.dm_gen.dm_n_24\,
Q(11) => \gdm.dm_gen.dm_n_25\,
Q(10) => \gdm.dm_gen.dm_n_26\,
Q(9) => \gdm.dm_gen.dm_n_27\,
Q(8) => \gdm.dm_gen.dm_n_28\,
Q(7) => \gdm.dm_gen.dm_n_29\,
Q(6) => \gdm.dm_gen.dm_n_30\,
Q(5) => \gdm.dm_gen.dm_n_31\,
Q(4) => \gdm.dm_gen.dm_n_32\,
Q(3) => \gdm.dm_gen.dm_n_33\,
Q(2) => \gdm.dm_gen.dm_n_34\,
Q(1) => \gdm.dm_gen.dm_n_35\,
Q(0) => \gdm.dm_gen.dm_n_36\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \m_axi_wdata[31]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \m_axi_wdata[31]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \m_axi_wdata[31]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \m_axi_wdata[31]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \m_axi_wdata[31]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \m_axi_wdata[31]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \m_axi_wdata[31]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \m_axi_wdata[31]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \m_axi_wdata[31]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \m_axi_wdata[31]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \m_axi_wdata[31]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \m_axi_wdata[31]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \m_axi_wdata[31]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \m_axi_wdata[31]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \m_axi_wdata[31]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \m_axi_wdata[31]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \m_axi_wdata[31]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \m_axi_wdata[31]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \m_axi_wdata[31]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \m_axi_wdata[31]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \m_axi_wdata[31]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \m_axi_wdata[31]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \m_axi_wdata[31]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \m_axi_wdata[31]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \m_axi_wdata[31]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \m_axi_wdata[31]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \m_axi_wdata[31]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \m_axi_wdata[31]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \m_axi_wdata[31]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \m_axi_wdata[31]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \m_axi_wdata[31]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \m_axi_wdata[31]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \m_axi_wdata[31]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \m_axi_wdata[31]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \m_axi_wdata[31]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \m_axi_wdata[31]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \m_axi_wdata[31]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_memory__parameterized1\ is
port (
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_memory__parameterized1\ : entity is "memory";
end \bd_auto_cc_0_memory__parameterized1\;
architecture STRUCTURE of \bd_auto_cc_0_memory__parameterized1\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\bd_auto_cc_0_dmem__parameterized1\
port map (
E(0) => E(0),
Q(5) => \gdm.dm_gen.dm_n_0\,
Q(4) => \gdm.dm_gen.dm_n_1\,
Q(3) => \gdm.dm_gen.dm_n_2\,
Q(2) => \gdm.dm_gen.dm_n_3\,
Q(1) => \gdm.dm_gen.dm_n_4\,
Q(0) => \gdm.dm_gen.dm_n_5\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \s_axi_bid[3]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \s_axi_bid[3]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \s_axi_bid[3]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \s_axi_bid[3]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \s_axi_bid[3]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \s_axi_bid[3]\(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_memory__parameterized2\ is
port (
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_memory__parameterized2\ : entity is "memory";
end \bd_auto_cc_0_memory__parameterized2\;
architecture STRUCTURE of \bd_auto_cc_0_memory__parameterized2\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\bd_auto_cc_0_dmem__parameterized2\
port map (
E(0) => E(0),
I127(38 downto 0) => I127(38 downto 0),
Q(38) => \gdm.dm_gen.dm_n_0\,
Q(37) => \gdm.dm_gen.dm_n_1\,
Q(36) => \gdm.dm_gen.dm_n_2\,
Q(35) => \gdm.dm_gen.dm_n_3\,
Q(34) => \gdm.dm_gen.dm_n_4\,
Q(33) => \gdm.dm_gen.dm_n_5\,
Q(32) => \gdm.dm_gen.dm_n_6\,
Q(31) => \gdm.dm_gen.dm_n_7\,
Q(30) => \gdm.dm_gen.dm_n_8\,
Q(29) => \gdm.dm_gen.dm_n_9\,
Q(28) => \gdm.dm_gen.dm_n_10\,
Q(27) => \gdm.dm_gen.dm_n_11\,
Q(26) => \gdm.dm_gen.dm_n_12\,
Q(25) => \gdm.dm_gen.dm_n_13\,
Q(24) => \gdm.dm_gen.dm_n_14\,
Q(23) => \gdm.dm_gen.dm_n_15\,
Q(22) => \gdm.dm_gen.dm_n_16\,
Q(21) => \gdm.dm_gen.dm_n_17\,
Q(20) => \gdm.dm_gen.dm_n_18\,
Q(19) => \gdm.dm_gen.dm_n_19\,
Q(18) => \gdm.dm_gen.dm_n_20\,
Q(17) => \gdm.dm_gen.dm_n_21\,
Q(16) => \gdm.dm_gen.dm_n_22\,
Q(15) => \gdm.dm_gen.dm_n_23\,
Q(14) => \gdm.dm_gen.dm_n_24\,
Q(13) => \gdm.dm_gen.dm_n_25\,
Q(12) => \gdm.dm_gen.dm_n_26\,
Q(11) => \gdm.dm_gen.dm_n_27\,
Q(10) => \gdm.dm_gen.dm_n_28\,
Q(9) => \gdm.dm_gen.dm_n_29\,
Q(8) => \gdm.dm_gen.dm_n_30\,
Q(7) => \gdm.dm_gen.dm_n_31\,
Q(6) => \gdm.dm_gen.dm_n_32\,
Q(5) => \gdm.dm_gen.dm_n_33\,
Q(4) => \gdm.dm_gen.dm_n_34\,
Q(3) => \gdm.dm_gen.dm_n_35\,
Q(2) => \gdm.dm_gen.dm_n_36\,
Q(1) => \gdm.dm_gen.dm_n_37\,
Q(0) => \gdm.dm_gen.dm_n_38\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \s_axi_rid[3]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \s_axi_rid[3]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \s_axi_rid[3]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \s_axi_rid[3]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \s_axi_rid[3]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \s_axi_rid[3]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \s_axi_rid[3]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \s_axi_rid[3]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \s_axi_rid[3]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \s_axi_rid[3]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \s_axi_rid[3]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \s_axi_rid[3]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \s_axi_rid[3]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \s_axi_rid[3]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \s_axi_rid[3]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \s_axi_rid[3]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \s_axi_rid[3]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \s_axi_rid[3]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \s_axi_rid[3]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \s_axi_rid[3]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \s_axi_rid[3]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \s_axi_rid[3]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \s_axi_rid[3]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \s_axi_rid[3]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \s_axi_rid[3]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \s_axi_rid[3]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \s_axi_rid[3]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \s_axi_rid[3]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \s_axi_rid[3]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \s_axi_rid[3]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \s_axi_rid[3]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \s_axi_rid[3]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \s_axi_rid[3]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \s_axi_rid[3]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \s_axi_rid[3]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \s_axi_rid[3]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \s_axi_rid[3]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \s_axi_rid[3]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \s_axi_rid[3]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_logic is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end bd_auto_cc_0_rd_logic;
architecture STRUCTURE of bd_auto_cc_0_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.bd_auto_cc_0_rd_fwft
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[5]\(0) => \goreg_dm.dout_i_reg[5]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\,
s_aclk => s_aclk,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
\gras.rsts\: entity work.bd_auto_cc_0_rd_status_flags_as
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
s_aclk => s_aclk
);
rpntr: entity work.bd_auto_cc_0_rd_bin_cntr
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_logic_28 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_logic_28 : entity is "rd_logic";
end bd_auto_cc_0_rd_logic_28;
architecture STRUCTURE of bd_auto_cc_0_rd_logic_28 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.bd_auto_cc_0_rd_fwft_39
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[64]\(0) => \goreg_dm.dout_i_reg[64]\(0),
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.bd_auto_cc_0_rd_status_flags_as_40
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.bd_auto_cc_0_rd_bin_cntr_41
port map (
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_logic_49 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[38]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_logic_49 : entity is "rd_logic";
end bd_auto_cc_0_rd_logic_49;
architecture STRUCTURE of bd_auto_cc_0_rd_logic_49 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.bd_auto_cc_0_rd_fwft_60
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[38]\(0) => \goreg_dm.dout_i_reg[38]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\,
s_aclk => s_aclk,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gras.rsts\: entity work.bd_auto_cc_0_rd_status_flags_as_61
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
s_aclk => s_aclk
);
rpntr: entity work.bd_auto_cc_0_rd_bin_cntr_62
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_logic_7 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[36]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_logic_7 : entity is "rd_logic";
end bd_auto_cc_0_rd_logic_7;
architecture STRUCTURE of bd_auto_cc_0_rd_logic_7 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.bd_auto_cc_0_rd_fwft_18
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[36]\(0) => \goreg_dm.dout_i_reg[36]\(0),
m_aclk => m_aclk,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.bd_auto_cc_0_rd_status_flags_as_19
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.bd_auto_cc_0_rd_bin_cntr_20
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_logic_71 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_logic_71 : entity is "rd_logic";
end bd_auto_cc_0_rd_logic_71;
architecture STRUCTURE of bd_auto_cc_0_rd_logic_71 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.bd_auto_cc_0_rd_fwft_84
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[64]\(0) => \goreg_dm.dout_i_reg[64]\(0),
m_aclk => m_aclk,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.bd_auto_cc_0_rd_status_flags_as_85
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.bd_auto_cc_0_rd_bin_cntr_86
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
end bd_auto_cc_0_reset_blk_ramfifo;
architecture STRUCTURE of bd_auto_cc_0_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_1
port map (
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_3
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_4
port map (
\Q_reg_reg[0]_0\ => p_7_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_5
port map (
\Q_reg_reg[0]_0\ => p_8_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_reset_blk_ramfifo_30 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_reset_blk_ramfifo_30 : entity is "reset_blk_ramfifo";
end bd_auto_cc_0_reset_blk_ramfifo_30;
architecture STRUCTURE of bd_auto_cc_0_reset_blk_ramfifo_30 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_31
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_32
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_33
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_34
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_35
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_36
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_reset_blk_ramfifo_51 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ : out STD_LOGIC;
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_reset_blk_ramfifo_51 : entity is "reset_blk_ramfifo";
end bd_auto_cc_0_reset_blk_ramfifo_51;
architecture STRUCTURE of bd_auto_cc_0_reset_blk_ramfifo_51 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ <= \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_52
port map (
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_53
port map (
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_54
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_55
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_56
port map (
\Q_reg_reg[0]_0\ => p_7_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_57
port map (
\Q_reg_reg[0]_0\ => p_8_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_reset_blk_ramfifo_74 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_reset_blk_ramfifo_74 : entity is "reset_blk_ramfifo";
end bd_auto_cc_0_reset_blk_ramfifo_74;
architecture STRUCTURE of bd_auto_cc_0_reset_blk_ramfifo_74 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_75
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_76
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_77
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_78
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_79
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_80
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_reset_blk_ramfifo_9 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_reset_blk_ramfifo_9 : entity is "reset_blk_ramfifo";
end bd_auto_cc_0_reset_blk_ramfifo_9;
architecture STRUCTURE of bd_auto_cc_0_reset_blk_ramfifo_9 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_10
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_11
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_12
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_13
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_14
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_15
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_logic is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_wr_logic;
architecture STRUCTURE of bd_auto_cc_0_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.bd_auto_cc_0_wr_status_flags_as
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
m_aclk => m_aclk,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.bd_auto_cc_0_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
m_aclk => m_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_logic_29 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_logic_29 : entity is "wr_logic";
end bd_auto_cc_0_wr_logic_29;
architecture STRUCTURE of bd_auto_cc_0_wr_logic_29 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.bd_auto_cc_0_wr_status_flags_as_37
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
wpntr: entity work.bd_auto_cc_0_wr_bin_cntr_38
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_logic_50 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_logic_50 : entity is "wr_logic";
end bd_auto_cc_0_wr_logic_50;
architecture STRUCTURE of bd_auto_cc_0_wr_logic_50 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.bd_auto_cc_0_wr_status_flags_as_58
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.bd_auto_cc_0_wr_bin_cntr_59
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
m_aclk => m_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_logic_72 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_logic_72 : entity is "wr_logic";
end bd_auto_cc_0_wr_logic_72;
architecture STRUCTURE of bd_auto_cc_0_wr_logic_72 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.bd_auto_cc_0_wr_status_flags_as_82
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
wpntr: entity work.bd_auto_cc_0_wr_bin_cntr_83
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_logic_8 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_logic_8 : entity is "wr_logic";
end bd_auto_cc_0_wr_logic_8;
architecture STRUCTURE of bd_auto_cc_0_wr_logic_8 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.bd_auto_cc_0_wr_status_flags_as_16
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
wpntr: entity work.bd_auto_cc_0_wr_bin_cntr_17
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_ramfifo is
port (
s_axi_awready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end bd_auto_cc_0_fifo_generator_ramfifo;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out_0 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC;
signal p_23_out_1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.bd_auto_cc_0_clk_x_pntrs_27
port map (
AR(0) => wr_rst_i(0),
D(0) => gray2bin(0),
Q(3 downto 0) => p_22_out(3 downto 0),
\gc0.count_d1_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gc0.count_d1_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gc0.count_d1_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gc0.count_d1_reg[3]\(0) => p_0_out_0(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => p_23_out,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out_1(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => gray2bin(0)
);
\gntv_or_sync_fifo.gl0.rd\: entity work.bd_auto_cc_0_rd_logic_28
port map (
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[64]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.bd_auto_cc_0_wr_logic_29
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out_1(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
\gntv_or_sync_fifo.mem\: entity work.bd_auto_cc_0_memory
port map (
DI(64 downto 0) => DI(64 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
Q(64 downto 0) => Q(64 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
ram_full_fb_i_reg(0) => p_18_out,
s_aclk => s_aclk
);
rstblk: entity work.bd_auto_cc_0_reset_blk_ramfifo_30
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => p_23_out,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_ramfifo_69 is
port (
s_axi_arready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_fifo_generator_ramfifo_69 : entity is "fifo_generator_ramfifo";
end bd_auto_cc_0_fifo_generator_ramfifo_69;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_ramfifo_69 is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_rach : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.bd_auto_cc_0_clk_x_pntrs_70
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_22_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rach,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.bd_auto_cc_0_rd_logic_71
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[64]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.bd_auto_cc_0_wr_logic_72
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
\gntv_or_sync_fifo.mem\: entity work.bd_auto_cc_0_memory_73
port map (
E(0) => p_18_out,
I123(64 downto 0) => I123(64 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 0) => \m_axi_arid[3]\(64 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk
);
rstblk: entity work.bd_auto_cc_0_reset_blk_ramfifo_74
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_rach,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_ramfifo__parameterized0\ is
port (
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized0\ : entity is "fifo_generator_ramfifo";
end \bd_auto_cc_0_fifo_generator_ramfifo__parameterized0\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized0\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.bd_auto_cc_0_clk_x_pntrs_6
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_22_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => p_15_out,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.bd_auto_cc_0_rd_logic_7
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[36]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.bd_auto_cc_0_wr_logic_8
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
\gntv_or_sync_fifo.mem\: entity work.\bd_auto_cc_0_memory__parameterized0\
port map (
E(0) => p_18_out,
I115(36 downto 0) => I115(36 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\m_axi_wdata[31]\(36 downto 0) => \m_axi_wdata[31]\(36 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk
);
rstblk: entity work.bd_auto_cc_0_reset_blk_ramfifo_9
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => p_15_out,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_ramfifo__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized1\ : entity is "fifo_generator_ramfifo";
end \bd_auto_cc_0_fifo_generator_ramfifo__parameterized1\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized1\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_wrch : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.bd_auto_cc_0_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_13_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_wrch,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_6\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.bd_auto_cc_0_rd_logic
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[5]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
s_aclk => s_aclk,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.bd_auto_cc_0_wr_logic
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
m_aclk => m_aclk,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.\bd_auto_cc_0_memory__parameterized1\
port map (
E(0) => p_18_out,
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk,
\s_axi_bid[3]\(5 downto 0) => \s_axi_bid[3]\(5 downto 0)
);
rstblk: entity work.bd_auto_cc_0_reset_blk_ramfifo
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_wrch,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_ramfifo__parameterized2\ is
port (
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized2\ : entity is "fifo_generator_ramfifo";
end \bd_auto_cc_0_fifo_generator_ramfifo__parameterized2\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized2\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_rdch : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.bd_auto_cc_0_clk_x_pntrs_48
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_13_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rdch,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_6\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.bd_auto_cc_0_rd_logic_49
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[38]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
s_aclk => s_aclk,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.bd_auto_cc_0_wr_logic_50
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.\bd_auto_cc_0_memory__parameterized2\
port map (
E(0) => p_18_out,
I127(38 downto 0) => I127(38 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk,
\s_axi_rid[3]\(38 downto 0) => \s_axi_rid[3]\(38 downto 0)
);
rstblk: entity work.bd_auto_cc_0_reset_blk_ramfifo_51
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ => \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_rdch,
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_top is
port (
s_axi_arready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end bd_auto_cc_0_fifo_generator_top;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_top is
begin
\grf.rf\: entity work.bd_auto_cc_0_fifo_generator_ramfifo_69
port map (
I123(64 downto 0) => I123(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 0) => \m_axi_arid[3]\(64 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_top_0 is
port (
s_axi_awready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_fifo_generator_top_0 : entity is "fifo_generator_top";
end bd_auto_cc_0_fifo_generator_top_0;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_top_0 is
begin
\grf.rf\: entity work.bd_auto_cc_0_fifo_generator_ramfifo
port map (
DI(64 downto 0) => DI(64 downto 0),
Q(64 downto 0) => Q(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_top__parameterized0\ is
port (
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_top__parameterized0\ : entity is "fifo_generator_top";
end \bd_auto_cc_0_fifo_generator_top__parameterized0\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_top__parameterized0\ is
begin
\grf.rf\: entity work.\bd_auto_cc_0_fifo_generator_ramfifo__parameterized0\
port map (
I115(36 downto 0) => I115(36 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_wdata[31]\(36 downto 0) => \m_axi_wdata[31]\(36 downto 0),
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_top__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_top__parameterized1\ : entity is "fifo_generator_top";
end \bd_auto_cc_0_fifo_generator_top__parameterized1\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_top__parameterized1\ is
begin
\grf.rf\: entity work.\bd_auto_cc_0_fifo_generator_ramfifo__parameterized1\
port map (
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_aclk => s_aclk,
\s_axi_bid[3]\(5 downto 0) => \s_axi_bid[3]\(5 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_top__parameterized2\ is
port (
inverted_reset : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_top__parameterized2\ : entity is "fifo_generator_top";
end \bd_auto_cc_0_fifo_generator_top__parameterized2\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_top__parameterized2\ is
begin
\grf.rf\: entity work.\bd_auto_cc_0_fifo_generator_ramfifo__parameterized2\
port map (
I127(38 downto 0) => I127(38 downto 0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ => inverted_reset,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
\s_axi_rid[3]\(38 downto 0) => \s_axi_rid[3]\(38 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_v13_1_3_synth is
port (
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_awready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 );
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 );
DI : in STD_LOGIC_VECTOR ( 64 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
end bd_auto_cc_0_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_v13_1_3_synth is
signal inverted_reset : STD_LOGIC;
begin
\gaxi_full_lite.gread_ch.grach2.axi_rach\: entity work.bd_auto_cc_0_fifo_generator_top
port map (
I123(64 downto 0) => I123(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 0) => \m_axi_arid[3]\(64 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
\gaxi_full_lite.gread_ch.grdch2.axi_rdch\: entity work.\bd_auto_cc_0_fifo_generator_top__parameterized2\
port map (
I127(38 downto 0) => I127(38 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
\s_axi_rid[3]\(38 downto 0) => \s_axi_rid[3]\(38 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gaxi_full_lite.gwrite_ch.gwach2.axi_wach\: entity work.bd_auto_cc_0_fifo_generator_top_0
port map (
DI(64 downto 0) => DI(64 downto 0),
Q(64 downto 0) => Q(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch\: entity work.\bd_auto_cc_0_fifo_generator_top__parameterized0\
port map (
I115(36 downto 0) => I115(36 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_wdata[31]\(36 downto 0) => \m_axi_wdata[31]\(36 downto 0),
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch\: entity work.\bd_auto_cc_0_fifo_generator_top__parameterized1\
port map (
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_aclk => s_aclk,
\s_axi_bid[3]\(5 downto 0) => \s_axi_bid[3]\(5 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 17 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 17 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 18;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 65;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 39;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 65;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 37;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 6;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 18;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 2;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "4kx4";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
end bd_auto_cc_0_fifo_generator_v13_1_3;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const0>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const0>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const0>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const0>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const0>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const0>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
dout(17) <= \<const0>\;
dout(16) <= \<const0>\;
dout(15) <= \<const0>\;
dout(14) <= \<const0>\;
dout(13) <= \<const0>\;
dout(12) <= \<const0>\;
dout(11) <= \<const0>\;
dout(10) <= \<const0>\;
dout(9) <= \<const0>\;
dout(8) <= \<const0>\;
dout(7) <= \<const0>\;
dout(6) <= \<const0>\;
dout(5) <= \<const0>\;
dout(4) <= \<const0>\;
dout(3) <= \<const0>\;
dout(2) <= \<const0>\;
dout(1) <= \<const0>\;
dout(0) <= \<const0>\;
empty <= \<const0>\;
full <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_fifo_gen: entity work.bd_auto_cc_0_fifo_generator_v13_1_3_synth
port map (
DI(64 downto 61) => s_axi_awid(3 downto 0),
DI(60 downto 29) => s_axi_awaddr(31 downto 0),
DI(28 downto 21) => s_axi_awlen(7 downto 0),
DI(20 downto 18) => s_axi_awsize(2 downto 0),
DI(17 downto 16) => s_axi_awburst(1 downto 0),
DI(15) => s_axi_awlock(0),
DI(14 downto 11) => s_axi_awcache(3 downto 0),
DI(10 downto 8) => s_axi_awprot(2 downto 0),
DI(7 downto 4) => s_axi_awqos(3 downto 0),
DI(3 downto 0) => s_axi_awregion(3 downto 0),
I115(36 downto 5) => s_axi_wdata(31 downto 0),
I115(4 downto 1) => s_axi_wstrb(3 downto 0),
I115(0) => s_axi_wlast,
I123(64 downto 61) => s_axi_arid(3 downto 0),
I123(60 downto 29) => s_axi_araddr(31 downto 0),
I123(28 downto 21) => s_axi_arlen(7 downto 0),
I123(20 downto 18) => s_axi_arsize(2 downto 0),
I123(17 downto 16) => s_axi_arburst(1 downto 0),
I123(15) => s_axi_arlock(0),
I123(14 downto 11) => s_axi_arcache(3 downto 0),
I123(10 downto 8) => s_axi_arprot(2 downto 0),
I123(7 downto 4) => s_axi_arqos(3 downto 0),
I123(3 downto 0) => s_axi_arregion(3 downto 0),
I127(38 downto 35) => m_axi_rid(3 downto 0),
I127(34 downto 3) => m_axi_rdata(31 downto 0),
I127(2 downto 1) => m_axi_rresp(1 downto 0),
I127(0) => m_axi_rlast,
Q(64 downto 61) => m_axi_awid(3 downto 0),
Q(60 downto 29) => m_axi_awaddr(31 downto 0),
Q(28 downto 21) => m_axi_awlen(7 downto 0),
Q(20 downto 18) => m_axi_awsize(2 downto 0),
Q(17 downto 16) => m_axi_awburst(1 downto 0),
Q(15) => m_axi_awlock(0),
Q(14 downto 11) => m_axi_awcache(3 downto 0),
Q(10 downto 8) => m_axi_awprot(2 downto 0),
Q(7 downto 4) => m_axi_awqos(3 downto 0),
Q(3 downto 0) => m_axi_awregion(3 downto 0),
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 61) => m_axi_arid(3 downto 0),
\m_axi_arid[3]\(60 downto 29) => m_axi_araddr(31 downto 0),
\m_axi_arid[3]\(28 downto 21) => m_axi_arlen(7 downto 0),
\m_axi_arid[3]\(20 downto 18) => m_axi_arsize(2 downto 0),
\m_axi_arid[3]\(17 downto 16) => m_axi_arburst(1 downto 0),
\m_axi_arid[3]\(15) => m_axi_arlock(0),
\m_axi_arid[3]\(14 downto 11) => m_axi_arcache(3 downto 0),
\m_axi_arid[3]\(10 downto 8) => m_axi_arprot(2 downto 0),
\m_axi_arid[3]\(7 downto 4) => m_axi_arqos(3 downto 0),
\m_axi_arid[3]\(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\m_axi_wdata[31]\(36 downto 5) => m_axi_wdata(31 downto 0),
\m_axi_wdata[31]\(4 downto 1) => m_axi_wstrb(3 downto 0),
\m_axi_wdata[31]\(0) => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[3]\(5 downto 2) => s_axi_bid(3 downto 0),
\s_axi_bid[3]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[3]\(38 downto 35) => s_axi_rid(3 downto 0),
\s_axi_rid[3]\(34 downto 3) => s_axi_rdata(31 downto 0),
\s_axi_rid[3]\(2 downto 1) => s_axi_rresp(1 downto 0),
\s_axi_rid[3]\(0) => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 29;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 61;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 21;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 15;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 18;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 29;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 61;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 21;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 15;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 18;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 6;
attribute C_FAMILY : string;
attribute C_FAMILY of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 6;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 39;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 37;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 35;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 39;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 5;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 37;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 37;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "yes";
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "1'b1";
end bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter;
architecture STRUCTURE of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter is
signal \<const0>\ : STD_LOGIC;
signal async_conv_reset_n : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_AXI_ADDR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 32;
attribute C_AXI_ARUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_AWUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_BUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_DATA_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 32;
attribute C_AXI_ID_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_RUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_WUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 18;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 65;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 39;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 65;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 37;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 6;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 18;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_FAMILY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 2;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "4kx4";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1021;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_SYNCHRONIZER_STAGE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
begin
m_axi_aruser(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_clock_conv.gen_async_conv.asyncfifo_axi\: entity work.bd_auto_cc_0_fifo_generator_v13_1_3
port map (
almost_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED\,
almost_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED\,
axi_ar_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED\(4 downto 0),
axi_ar_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED\,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED\,
axi_ar_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED\,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED\,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED\(4 downto 0),
axi_ar_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED\,
axi_ar_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED\,
axi_ar_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED\(4 downto 0),
axi_aw_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED\(4 downto 0),
axi_aw_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED\,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED\,
axi_aw_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED\,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED\,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED\(4 downto 0),
axi_aw_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED\,
axi_aw_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED\,
axi_aw_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED\(4 downto 0),
axi_b_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED\(4 downto 0),
axi_b_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED\,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED\,
axi_b_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED\,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED\,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED\(4 downto 0),
axi_b_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED\,
axi_b_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED\,
axi_b_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED\(4 downto 0),
axi_r_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED\(4 downto 0),
axi_r_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED\,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED\,
axi_r_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED\,
axi_r_prog_empty_thresh(3 downto 0) => B"0000",
axi_r_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED\,
axi_r_prog_full_thresh(3 downto 0) => B"0000",
axi_r_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED\(4 downto 0),
axi_r_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED\,
axi_r_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED\,
axi_r_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED\(4 downto 0),
axi_w_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED\(4 downto 0),
axi_w_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED\,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED\,
axi_w_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED\,
axi_w_prog_empty_thresh(3 downto 0) => B"0000",
axi_w_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED\,
axi_w_prog_full_thresh(3 downto 0) => B"0000",
axi_w_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED\(4 downto 0),
axi_w_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED\,
axi_w_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED\,
axi_w_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED\(4 downto 0),
axis_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED\(10 downto 0),
axis_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED\,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED\,
axis_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED\,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED\,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED\(10 downto 0),
axis_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED\,
axis_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED\,
axis_wr_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED\(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED\(9 downto 0),
dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED\,
din(17 downto 0) => B"000000000000000000",
dout(17 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED\(17 downto 0),
empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED\,
full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED\,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => m_axi_aclk,
m_aclk_en => '1',
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(3 downto 0) => m_axi_arid(3 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED\(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(3 downto 0) => m_axi_awid(3 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED\(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(3 downto 0) => m_axi_rid(3 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(3 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED\(3 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED\(0),
m_axi_wvalid => m_axi_wvalid,
m_axis_tdata(7 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED\(7 downto 0),
m_axis_tdest(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED\(0),
m_axis_tid(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED\(0),
m_axis_tkeep(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED\(0),
m_axis_tlast => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED\,
m_axis_tready => '0',
m_axis_tstrb(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED\(0),
m_axis_tuser(3 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED\(3 downto 0),
m_axis_tvalid => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED\,
overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED\,
prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED\,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED\,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED\(9 downto 0),
rd_en => '0',
rd_rst => '0',
rd_rst_busy => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED\,
rst => '0',
s_aclk => s_axi_aclk,
s_aclk_en => '1',
s_aresetn => async_conv_reset_n,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(3 downto 0) => s_axi_arid(3 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(3 downto 0) => s_axi_awid(3 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(3 downto 0) => s_axi_bid(3 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED\(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(3 downto 0) => s_axi_rid(3 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED\(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid,
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED\,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED\,
sleep => '0',
srst => '0',
underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED\,
valid => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED\,
wr_ack => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED\,
wr_clk => '0',
wr_data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED\(9 downto 0),
wr_en => '0',
wr_rst => '0',
wr_rst_busy => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED\
);
\gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_aresetn,
I1 => m_axi_aresetn,
O => async_conv_reset_n
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bd_auto_cc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bd_auto_cc_0 : entity is "bd_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of bd_auto_cc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of bd_auto_cc_0 : entity is "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4";
end bd_auto_cc_0;
architecture STRUCTURE of bd_auto_cc_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of inst : label is 29;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of inst : label is 32;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of inst : label is 16;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of inst : label is 2;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of inst : label is 11;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of inst : label is 4;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of inst : label is 61;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of inst : label is 4;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of inst : label is 21;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of inst : label is 8;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of inst : label is 15;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of inst : label is 1;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of inst : label is 8;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of inst : label is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of inst : label is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of inst : label is 4;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of inst : label is 4;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of inst : label is 4;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of inst : label is 18;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of inst : label is 3;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of inst : label is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of inst : label is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of inst : label is 65;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of inst : label is 29;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of inst : label is 32;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of inst : label is 16;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of inst : label is 2;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of inst : label is 11;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of inst : label is 4;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of inst : label is 61;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of inst : label is 4;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of inst : label is 21;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of inst : label is 8;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of inst : label is 15;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of inst : label is 1;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of inst : label is 8;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of inst : label is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of inst : label is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of inst : label is 4;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of inst : label is 4;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of inst : label is 4;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of inst : label is 18;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of inst : label is 3;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of inst : label is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of inst : label is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of inst : label is 65;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 4;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of inst : label is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of inst : label is 4;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of inst : label is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of inst : label is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of inst : label is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of inst : label is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of inst : label is 6;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of inst : label is 65;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of inst : label is 65;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of inst : label is 6;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of inst : label is 39;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of inst : label is 37;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of inst : label is 3;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of inst : label is 32;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of inst : label is 35;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of inst : label is 4;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of inst : label is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of inst : label is 1;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of inst : label is 1;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of inst : label is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of inst : label is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of inst : label is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of inst : label is 39;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of inst : label is 5;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of inst : label is 32;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of inst : label is 37;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of inst : label is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of inst : label is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of inst : label is 1;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of inst : label is 1;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of inst : label is 4;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of inst : label is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of inst : label is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of inst : label is 37;
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of inst : label is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of inst : label is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of inst : label is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of inst : label is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of inst : label is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of inst : label is "1'b1";
attribute downgradeipidentifiedwarnings of inst : label is "yes";
begin
inst: entity work.bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter
port map (
m_axi_aclk => m_axi_aclk,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => m_axi_aresetn,
m_axi_arid(3 downto 0) => m_axi_arid(3 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(3 downto 0) => m_axi_awid(3 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(3 downto 0) => m_axi_rid(3 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(3 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(3 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(3 downto 0) => s_axi_arid(3 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(3 downto 0) => s_axi_awid(3 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(3 downto 0) => s_axi_bid(3 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(3 downto 0) => s_axi_rid(3 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
mit
|
3ed1f0207389d702be6117217d76568b
| 0.577881 | 2.714683 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/tb_iteration.vhd
| 1 | 4,355 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY tb_iteration IS
END tb_iteration;
ARCHITECTURE behavior OF tb_iteration IS
COMPONENT mandelbrot_iteration
PORT(
clk : IN std_logic;
ov_in : IN std_logic;
x : IN std_logic_vector(17 downto 0);
y : IN std_logic_vector(17 downto 0);
x0 : IN std_logic_vector(17 downto 0);
y0 : IN std_logic_vector(17 downto 0);
x_out : OUT std_logic_vector(17 downto 0);
y_out : OUT std_logic_vector(17 downto 0);
ov : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal ov_in : std_logic := '0';
signal x : std_logic_vector(17 downto 0) := (others => '0');
signal y : std_logic_vector(17 downto 0) := (others => '0');
signal x0 : std_logic_vector(17 downto 0) := (others => '0');
signal y0 : std_logic_vector(17 downto 0) := (others => '0');
--Outputs
signal x_out : std_logic_vector(17 downto 0);
signal y_out : std_logic_vector(17 downto 0);
signal ov : std_logic;
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mandelbrot_iteration PORT MAP (
clk => clk,
ov_in => ov_in,
x => x,
y => y,
x0 => x0,
y0 => y0,
x_out => x_out,
y_out => y_out,
ov => ov
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*20.5;
-- insert stimulus here
-- x0<= std_logic_vector(to_signed(+1*(2**15),18));
-- y0<= std_logic_vector(to_signed(+1*(2**15),18));
--
-- x <= std_logic_vector(to_signed(+1*(2**15),18));
-- y <= std_logic_vector(to_signed(+0*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(-1*(2**15),18));
-- y <= std_logic_vector(to_signed(+0*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(+0*(2**15),18));
-- y <= std_logic_vector(to_signed(+1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(+0*(2**15),18));
-- y <= std_logic_vector(to_signed(-1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(+1*(2**15),18));
-- y <= std_logic_vector(to_signed(+1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(-1*(2**15),18));
-- y <= std_logic_vector(to_signed(-1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(+1*(2**15),18));
-- y <= std_logic_vector(to_signed(-1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(-1*(2**15),18));
-- y <= std_logic_vector(to_signed(1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(2*(2**15),18));
-- y <= std_logic_vector(to_signed(1*(2**15),18));
-- wait for clk_period*20;
--
-- x <= std_logic_vector(to_signed(2*(2**15),18));
-- y <= std_logic_vector(to_signed(2*(2**15),18));
-- wait for clk_period*20;
wait for clk_period*100;
x <= std_logic_vector(to_signed(2*(2**15),18));
y <= std_logic_vector(to_signed(2*(2**15),18));
wait for clk_period*1;
x <= std_logic_vector(to_signed(+1*(2**15),18));
y <= std_logic_vector(to_signed(+1*(2**15),18));
wait for clk_period*1;
x <= std_logic_vector(to_signed(+0*(2**15),18));
y <= std_logic_vector(to_signed(+0*(2**15),18));
wait for clk_period*1;
x <= std_logic_vector(to_signed(+1*(2**15),18));
y <= std_logic_vector(to_signed(+1*(2**15),18));
x0 <= std_logic_vector(to_signed(-1*(2**15),18));
y0 <= std_logic_vector(to_signed(+1*(2**15),18));
wait for clk_period*1;
x <= std_logic_vector(to_signed(+0*(2**15),18));
y <= std_logic_vector(to_signed(+0*(2**15),18));
x0 <= std_logic_vector(to_signed(-0*(2**15),18));
y0 <= std_logic_vector(to_signed(+0*(2**15),18));
wait for clk_period*1;
ov_in <= '1';
wait for clk_period*1;
ov_in <= '0';
wait for clk_period*100;
wait;
end process;
END;
|
gpl-3.0
|
1e7978db75406493425ae6a50d50a816
| 0.553157 | 2.689932 | false | false | false | false |
Daverball/reconos
|
pcores/reconos_memif_arbiter_v1_00_a/hdl/vhdl/reconos_memif_arbiter.vhd
| 2 | 10,631 |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF Arbiter
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The arbiter connects the different HWTs
-- to the memory system of ReconOS. It acts as an
-- arbiter and controls the the memory access. For
-- further details on how the memory system in ReconOS
-- works take a look into the documentation (memory.txt)
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity reconos_memif_arbiter is
generic (
C_NUM_HWTS : integer := 1;
C_MEMIF_FIFO_WIDTH : integer := 32;
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24
);
port (
-- Input ports from HWTs
-- ## BEGIN GENERATE LOOP ##
MEMIF_FIFO_In_Hwt2Mem_Data_#i# : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_In_Hwt2Mem_Fill_#i# : in std_logic_vector(15 downto 0);
MEMIF_FIFO_In_Hwt2Mem_Empty_#i# : in std_logic;
MEMIF_FIFO_In_Hwt2Mem_RE_#i# : out std_logic;
MEMIF_FIFO_In_Mem2Hwt_Data_#i# : out std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_In_Mem2Hwt_Rem_#i# : in std_logic_vector(15 downto 0);
MEMIF_FIFO_In_Mem2Hwt_Full_#i# : in std_logic;
MEMIF_FIFO_In_Mem2Hwt_WE_#i# : out std_logic;
-- ## END GENERATE LOOP ##
-- Multiplexed output ports
MEMIF_FIFO_Out_Hwt2Mem_Data : out std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Out_Hwt2Mem_Fill : out std_logic_vector(15 downto 0);
MEMIF_FIFO_Out_Hwt2Mem_Empty : out std_logic;
MEMIF_FIFO_Out_Hwt2Mem_RE : in std_logic;
MEMIF_FIFO_Out_Mem2Hwt_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Out_Mem2Hwt_Rem : out std_logic_vector(15 downto 0);
MEMIF_FIFO_Out_Mem2Hwt_Full : out std_logic;
MEMIF_FIFO_Out_Mem2Hwt_WE : in std_logic;
-- Control FIFO for memory subsystem
-- REMARK: This is not a master interface of a FIFO.
-- We emulate the FIFO directly to avoid delays.
CTRL_FIFO_Out_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Out_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Out_Empty : out std_logic;
CTRL_FIFO_Out_RE : in std_logic;
-- Transaction control ports
TCTRL_Clk : in std_logic;
TCTRL_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of TCTRL_Clk : signal is "Clk";
attribute SIGIS of TCTRL_Rst : signal is "Rst";
end entity reconos_memif_arbiter;
architecture implementation of reconos_memif_arbiter is
-- Definition of MEMIF datatypes for easier handling of the FIFOs
type memif_fifo_t is record
hw2mem_data : std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
hw2mem_fill : std_logic_vector(15 downto 0);
hw2mem_empty : std_logic;
hw2mem_re : std_logic;
mem2hw_data : std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
mem2hw_rem : std_logic_vector(15 downto 0);
mem2hw_full : std_logic;
mem2hw_we : std_logic;
end record;
-- Signals to control HWT-MEMIF from this control unit
signal hw2mem_data : std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
signal hw2mem_fill : std_logic_vector(15 downto 0);
signal hw2mem_empty : std_logic;
signal hw2mem_re : std_logic;
signal mem2hw_data : std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
signal mem2hw_rem : std_logic_vector(15 downto 0);
signal mem2hw_full : std_logic;
signal mem2hw_we : std_logic;
-- Array which contains all connected MEMIFs for easier handling
type memif_t is array(0 to C_NUM_HWTS - 1) of memif_fifo_t;
signal memif : memif_t;
signal memif_select : integer range 0 to C_NUM_HWTS - 1;
signal memif_empty : std_logic_vector(0 to C_NUM_HWTS - 1);
-- Transaction control signals
type STATE_TYPE is (WAIT_REQUEST, READ_CMD, READ_ADDR, SERV_REQUEST);
signal state : STATE_TYPE;
signal ctrl_cmd : std_logic_vector(C_MEMIF_FIFO_WIDTH - C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_length : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_addr : std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
signal tctrl_bytes_rem : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
begin
-- This process multiplexes the MEMIFs to the right output
-- dependend on the current state
mux_proc : process(state,memif,memif_select,
hw2mem_re,hw2mem_data,
mem2hw_we,mem2hw_data,
CTRL_FIFO_Out_RE,
-- sensitivity list for MEMIF-FIFOs
-- ## BEGIN GENERATE LOOP ##
MEMIF_FIFO_In_Hwt2Mem_Data_#i#,MEMIF_FIFO_In_Hwt2Mem_Fill_#i#,MEMIF_FIFO_In_Hwt2Mem_Empty_#i#,
MEMIF_FIFO_In_Mem2Hwt_Rem_#i#,MEMIF_FIFO_In_Mem2Hwt_Full_#i#,
-- ## END GENERATE LOOP ##
MEMIF_FIFO_Out_Hwt2Mem_RE, MEMIF_FIFO_Out_Mem2Hwt_Data, MEMIF_FIFO_Out_Mem2Hwt_WE
) is
begin
-- Assign MEMIF_FIFOs to array
-- this could be done outside this process but because
-- of the behaviour of VHDL-record we can not drive different
-- components of a record in different processes
-- ## BEGIN GENERATE LOOP ##
memif(#i#).hw2mem_data <= MEMIF_FIFO_In_Hwt2Mem_Data_#i#;
memif(#i#).hw2mem_fill <= MEMIF_FIFO_In_Hwt2Mem_Fill_#i#;
memif(#i#).hw2mem_empty <= MEMIF_FIFO_In_Hwt2Mem_Empty_#i#;
MEMIF_FIFO_In_Hwt2Mem_RE_#i# <= memif(#i#).hw2mem_re;
MEMIF_FIFO_In_Mem2Hwt_Data_#i# <= memif(#i#).mem2hw_data;
memif(#i#).mem2hw_rem <= MEMIF_FIFO_In_Mem2Hwt_Rem_#i#;
memif(#i#).mem2hw_full <= MEMIF_FIFO_In_Mem2Hwt_Full_#i#;
MEMIF_FIFO_In_Mem2Hwt_WE_#i# <= memif(#i#).mem2hw_we;
memif_empty(#i#) <= not MEMIF_FIFO_In_Hwt2Mem_Empty_#i#;
-- ## END GENERATE LOOP ##
-- default values for not connected ports
-- later assignments will override this defaults
for i in 0 to C_NUM_HWTS - 1 loop
memif(i).hw2mem_re <= '0';
memif(i).mem2hw_we <= '0';
memif(i).mem2hw_data <= (others => '0');
end loop;
MEMIF_FIFO_Out_Hwt2Mem_Empty <= '1';
MEMIF_FIFO_Out_Hwt2Mem_Fill <= (others => '0');
MEMIF_FIFO_Out_Hwt2Mem_Data <= (others => '0');
MEMIF_FIFO_Out_Mem2Hwt_Full <= '1';
MEMIF_FIFO_Out_Mem2Hwt_Rem <= (others => '0');
CTRL_FIFO_Out_Empty <= '1';
CTRL_FIFO_Out_Fill <= (others => '0');
CTRL_FIFO_Out_Data <= (others => '0');
hw2mem_data <= (others => '0');
case state is
when WAIT_REQUEST =>
-- Connect MEMIF-FIFO to this control unit
hw2mem_data <= memif(memif_select).hw2mem_data;
hw2mem_fill <= memif(memif_select).hw2mem_fill;
hw2mem_empty <= memif(memif_select).hw2mem_empty;
memif(memif_select).hw2mem_re <= hw2mem_re;
memif(memif_select).mem2hw_data <= mem2hw_data;
mem2hw_rem <= memif(memif_select).mem2hw_rem;
mem2hw_full <= memif(memif_select).mem2hw_full;
memif(memif_select).mem2hw_we <= mem2hw_we;
when READ_CMD | READ_ADDR =>
-- Connecting hw2mem that the memory subsystem can read the command
CTRL_FIFO_Out_Data <= memif(memif_select).hw2mem_data;
CTRL_FIFO_Out_Fill <= memif(memif_select).hw2mem_fill;
CTRL_FIFO_Out_Empty <= memif(memif_select).hw2mem_empty;
memif(memif_select).hw2mem_re <= CTRL_FIFO_Out_RE;
hw2mem_data <= memif(memif_select).hw2mem_data;
when others =>
-- Connecting selected MEMIF-FIFO to output
MEMIF_FIFO_Out_Hwt2Mem_Data <= memif(memif_select).hw2mem_data;
MEMIF_FIFO_Out_Hwt2Mem_Fill <= memif(memif_select).hw2mem_fill;
MEMIF_FIFO_Out_Hwt2Mem_Empty <= memif(memif_select).hw2mem_empty;
memif(memif_select).hw2mem_re <= MEMIF_FIFO_Out_Hwt2Mem_RE;
memif(memif_select).mem2hw_data <= MEMIF_FIFO_Out_Mem2Hwt_Data;
MEMIF_FIFO_Out_Mem2Hwt_Rem <= memif(memif_select).mem2hw_rem;
MEMIF_FIFO_Out_Mem2Hwt_Full <= memif(memif_select).mem2hw_full;
memif(memif_select).mem2hw_we <= MEMIF_FIFO_Out_Mem2Hwt_WE;
end case;
end process mux_proc;
schedule_proc : process(TCTRL_Clk,TCTRL_Rst) is
variable pos : integer;
begin
if TCTRL_Rst = '1' then
state <= WAIT_REQUEST;
memif_select <= 0;
hw2mem_re <= '0';
mem2hw_we <= '0';
mem2hw_data <= (others => '0');
elsif rising_edge(TCTRL_Clk) then
case state is
when WAIT_REQUEST =>
hw2mem_re <= '0';
mem2hw_we <= '0';
-- a request is present, if a FIFO is not empty
if or_reduce(memif_empty) = '1' then
-- find out the next request to server with a simple schedule
-- start to look at FIFOs after the last position and find the first
-- one which is not empty
for i in 1 to C_NUM_HWTS loop
pos := (memif_select + i) mod C_NUM_HWTS;
if memif_empty(pos) = '1' then
memif_select <= pos;
exit;
end if;
end loop;
state <= READ_CMD;
end if;
when READ_CMD =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_cmd <= hw2mem_data(31 downto C_MEMIF_LENGTH_WIDTH);
ctrl_length <= hw2mem_data(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
state <= READ_ADDR;
end if;
when READ_ADDR =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_addr <= hw2mem_data;
tctrl_bytes_rem <= ctrl_length(C_MEMIF_LENGTH_WIDTH - 1 downto 2) & "00";
state <= SERV_REQUEST;
end if;
when SERV_REQUEST =>
-- count number of written/read words to find end of transaction
if MEMIF_FIFO_Out_Hwt2Mem_RE = '1' or MEMIF_FIFO_Out_Mem2Hwt_WE = '1' then
tctrl_bytes_rem <= tctrl_bytes_rem - 4;
if or_reduce(tctrl_bytes_rem - 4) = '0' then
state <= WAIT_REQUEST;
end if;
end if;
end case;
end if;
end process schedule_proc;
end architecture implementation;
|
gpl-2.0
|
394f6e18a1545dd35896ee268891d6ff
| 0.599153 | 3.024182 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/VGA1/ipcore_dir/v_timer.vhd
| 1 | 4,041 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file v_timer.vhd when simulating
-- the core, v_timer. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY v_timer IS
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END v_timer;
ARCHITECTURE v_timer_a OF v_timer IS
-- synthesis translate_off
COMPONENT wrapped_v_timer
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_v_timer USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1000001100",
c_fb_latency => 0,
c_has_ce => 0,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 1,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 10,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_v_timer
PORT MAP (
clk => clk,
q => q
);
-- synthesis translate_on
END v_timer_a;
|
gpl-3.0
|
8b38a8a6128d5c95c2c3ec2d7ca9bc9b
| 0.532541 | 4.677083 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
pcie_compiler_0.vhd
| 1 | 85,947 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- megafunction wizard: %IP Compiler for PCI Express v11.1%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- ============================================================
--Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--$Revision: #1
--Phy type: Cyclone IV GX Hard IP
--Number of Lanes: 1
--Ref Clk Freq: 100Mhz
--Number of VCs: 1
--Transaction Layer runs at 62.5Mhz
entity pcie_compiler_0 is
port (
-- inputs:
signal AvlClk_i : IN STD_LOGIC;
signal CraAddress_i : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal CraByteEnable_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal CraChipSelect_i : IN STD_LOGIC;
signal CraRead : IN STD_LOGIC;
signal CraWrite : IN STD_LOGIC;
signal CraWriteData_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal RxmIrqNum_i : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal RxmIrq_i : IN STD_LOGIC;
signal RxmReadDataValid_i : IN STD_LOGIC;
signal RxmReadData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal RxmWaitRequest_i : IN STD_LOGIC;
signal TxsAddress_i : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
signal TxsBurstCount_i : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal TxsByteEnable_i : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal TxsChipSelect_i : IN STD_LOGIC;
signal TxsRead_i : IN STD_LOGIC;
signal TxsWriteData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal TxsWrite_i : IN STD_LOGIC;
signal busy_altgxb_reconfig : IN STD_LOGIC;
signal cal_blk_clk : IN STD_LOGIC;
signal fixedclk_serdes : IN STD_LOGIC;
signal gxb_powerdown : IN STD_LOGIC;
signal pcie_rstn : IN STD_LOGIC;
signal phystatus_ext : IN STD_LOGIC;
signal pipe_mode : IN STD_LOGIC;
signal pll_powerdown : IN STD_LOGIC;
signal reconfig_clk : IN STD_LOGIC;
signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal rx_in0 : IN STD_LOGIC;
signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext : IN STD_LOGIC;
signal rxelecidle0_ext : IN STD_LOGIC;
signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
-- outputs:
signal CraIrq_o : OUT STD_LOGIC;
signal CraReadData_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal CraWaitRequest_o : OUT STD_LOGIC;
signal RxmAddress_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal RxmBurstCount_o : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal RxmByteEnable_o : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal RxmRead_o : OUT STD_LOGIC;
signal RxmResetRequest_o : OUT STD_LOGIC;
signal RxmWriteData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal RxmWrite_o : OUT STD_LOGIC;
signal TxsReadDataValid_o : OUT STD_LOGIC;
signal TxsReadData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal TxsWaitRequest_o : OUT STD_LOGIC;
signal clk125_out : OUT STD_LOGIC;
signal clk250_out : OUT STD_LOGIC;
signal clk500_out : OUT STD_LOGIC;
signal lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal pcie_core_clk : OUT STD_LOGIC;
signal powerdown_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rate_ext : OUT STD_LOGIC;
signal rc_pll_locked : OUT STD_LOGIC;
signal rc_rx_digitalreset : OUT STD_LOGIC;
signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reset_status : OUT STD_LOGIC;
signal rxpolarity0_ext : OUT STD_LOGIC;
signal suc_spd_neg : OUT STD_LOGIC;
signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal tl_cfg_ctl_wr : OUT STD_LOGIC;
signal tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
signal tl_cfg_sts_wr : OUT STD_LOGIC;
signal tx_out0 : OUT STD_LOGIC;
signal txcompl0_ext : OUT STD_LOGIC;
signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext : OUT STD_LOGIC;
signal txdetectrx_ext : OUT STD_LOGIC;
signal txelecidle0_ext : OUT STD_LOGIC
);
end entity pcie_compiler_0;
architecture europa of pcie_compiler_0 is
component pcie_compiler_0_serdes is
PORT (
signal rx_dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal pipeelecidle : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal pipedatavalid : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal pipestatus : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rx_ctrldetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal hip_tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal pipephydonestatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal tx_forceelecidle : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
signal pipe8b10binvpolarity : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
signal tx_forcedispcompliance : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
signal tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
signal rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
signal fixedclk : IN STD_LOGIC;
signal rx_elecidleinfersel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal cal_blk_clk : IN STD_LOGIC;
signal rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
signal powerdn : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal reconfig_clk : IN STD_LOGIC;
signal tx_ctrlenable : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
signal gxb_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
signal rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
signal pll_inclk : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
signal tx_datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pll_areset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
signal tx_detectrxloop : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
end component pcie_compiler_0_serdes;
component altpcie_rs_serdes is
PORT (
signal rxanalogreset : OUT STD_LOGIC;
signal txdigitalreset : OUT STD_LOGIC;
signal rxdigitalreset : OUT STD_LOGIC;
signal rx_pll_locked : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pll_locked : IN STD_LOGIC;
signal ltssm : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal npor : IN STD_LOGIC;
signal use_c4gx_serdes : IN STD_LOGIC;
signal rc_inclk_eq_125mhz : IN STD_LOGIC;
signal rx_signaldetect : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_err : IN STD_LOGIC;
signal detect_mask_rxdrst : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal pld_clk : IN STD_LOGIC;
signal busy_altgxb_reconfig : IN STD_LOGIC;
signal rx_freqlocked : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component altpcie_rs_serdes;
component pcie_compiler_0_core is
PORT (
signal RxmWrite_o : OUT STD_LOGIC;
signal rc_gxb_powerdown : OUT STD_LOGIC;
signal tx_fifo_full0 : OUT STD_LOGIC;
signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal TxsWaitRequest_o : OUT STD_LOGIC;
signal tl_cfg_sts_wr : OUT STD_LOGIC;
signal tl_cfg_ctl_wr : OUT STD_LOGIC;
signal l2_exit : OUT STD_LOGIC;
signal app_msi_ack : OUT STD_LOGIC;
signal tx_margin : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
signal tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
signal rc_rx_digitalreset : OUT STD_LOGIC;
signal CraWaitRequest_o : OUT STD_LOGIC;
signal TxsReadDataValid_o : OUT STD_LOGIC;
signal txelecidle0_ext : OUT STD_LOGIC;
signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rx_fifo_empty0 : OUT STD_LOGIC;
signal test_out : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal rx_st_err0 : OUT STD_LOGIC;
signal suc_spd_neg : OUT STD_LOGIC;
signal rc_rx_analogreset : OUT STD_LOGIC;
signal hip_extraclkout : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rxpolarity0_ext : OUT STD_LOGIC;
signal CraIrq_o : OUT STD_LOGIC;
signal rx_fifo_full0 : OUT STD_LOGIC;
signal RxmRead_o : OUT STD_LOGIC;
signal dl_ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal rx_st_eop0 : OUT STD_LOGIC;
signal txdetectrx0_ext : OUT STD_LOGIC;
signal lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal rate_ext : OUT STD_LOGIC;
signal rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_valid0 : OUT STD_LOGIC;
signal tx_st_ready0 : OUT STD_LOGIC;
signal rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal core_clk_out : OUT STD_LOGIC;
signal hotrst_exit : OUT STD_LOGIC;
signal tx_fifo_empty0 : OUT STD_LOGIC;
signal eidle_infer_sel : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_sop0 : OUT STD_LOGIC;
signal powerdown0_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal TxsReadData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pme_to_sr : OUT STD_LOGIC;
signal CraReadData_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal RxmByteEnable_o : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal RxmWriteData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal RxmBurstCount_o : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal dlup_exit : OUT STD_LOGIC;
signal reset_status : OUT STD_LOGIC;
signal txdatak0_ext : OUT STD_LOGIC;
signal txcompl0_ext : OUT STD_LOGIC;
signal app_int_ack : OUT STD_LOGIC;
signal RxmAddress_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rc_tx_digitalreset : OUT STD_LOGIC;
signal tx_deemph : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal CraWriteData_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal lmi_rden : IN STD_LOGIC;
signal CraRead : IN STD_LOGIC;
signal app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal core_clk_in : IN STD_LOGIC;
signal TxsChipSelect_i : IN STD_LOGIC;
signal tx_st_sop0 : IN STD_LOGIC;
signal pclk_central : IN STD_LOGIC;
signal pm_event : IN STD_LOGIC;
signal rc_inclk_eq_125mhz : IN STD_LOGIC;
signal pclk_ch0 : IN STD_LOGIC;
signal RxmIrq_i : IN STD_LOGIC;
signal tx_st_sop0_p1 : IN STD_LOGIC;
signal app_msi_req : IN STD_LOGIC;
signal app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rx_st_ready0 : IN STD_LOGIC;
signal rxelecidle0_ext : IN STD_LOGIC;
signal pld_clk : IN STD_LOGIC;
signal TxsWrite_i : IN STD_LOGIC;
signal pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal rc_areset : IN STD_LOGIC;
signal phystatus0_ext : IN STD_LOGIC;
signal tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_st_data0_p1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal TxsRead_i : IN STD_LOGIC;
signal rxdatak0_ext : IN STD_LOGIC;
signal rx_st_mask0 : IN STD_LOGIC;
signal CraAddress_i : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal CraWrite : IN STD_LOGIC;
signal hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal TxsByteEnable_i : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal RxmIrqNum_i : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal crst : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal RxmReadDataValid_i : IN STD_LOGIC;
signal cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal TxsWriteData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_st_eop0 : IN STD_LOGIC;
signal aer_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal RxmReadData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal TxsAddress_i : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
signal lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal lmi_wren : IN STD_LOGIC;
signal Rstn_i : IN STD_LOGIC;
signal TxsBurstCount_i : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pme_to_cr : IN STD_LOGIC;
signal tx_st_err0 : IN STD_LOGIC;
signal AvlClk_i : IN STD_LOGIC;
signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal RxmWaitRequest_i : IN STD_LOGIC;
signal tx_st_valid0 : IN STD_LOGIC;
signal rc_pll_locked : IN STD_LOGIC;
signal tx_st_eop0_p1 : IN STD_LOGIC;
signal npor : IN STD_LOGIC;
signal pm_auxpwr : IN STD_LOGIC;
signal srst : IN STD_LOGIC;
signal app_int_sts : IN STD_LOGIC;
signal CraChipSelect_i : IN STD_LOGIC;
signal CraByteEnable_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pll_fixed_clk : IN STD_LOGIC;
signal rxvalid0_ext : IN STD_LOGIC;
signal rc_rx_pll_locked_one : IN STD_LOGIC;
signal lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal cpl_pending : IN STD_LOGIC
);
end component pcie_compiler_0_core;
--synthesis translate_off
component altpcie_pll_100_250 is
PORT (
signal c0 : OUT STD_LOGIC;
signal areset : IN STD_LOGIC;
signal inclk0 : IN STD_LOGIC
);
end component altpcie_pll_100_250;
component altpcie_pll_125_250 is
PORT (
signal c0 : OUT STD_LOGIC;
signal areset : IN STD_LOGIC;
signal inclk0 : IN STD_LOGIC
);
end component altpcie_pll_125_250;
--synthesis translate_on
signal RxmByteEnable_int : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal RxmReadData_int : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal RxmWriteData_int : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal app_clk : STD_LOGIC;
signal core_clk_in : STD_LOGIC;
signal core_clk_out : STD_LOGIC;
signal crst : STD_LOGIC;
signal detect_mask_rxdrst : STD_LOGIC;
signal dlup_exit : STD_LOGIC;
signal eidle_infer_sel : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal fifo_err : STD_LOGIC;
signal gnd_app_int_sts : STD_LOGIC;
signal gnd_app_msi_num : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal gnd_app_msi_req : STD_LOGIC;
signal gnd_app_msi_tc : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal gnd_cpl_err : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal gnd_cpl_pending : STD_LOGIC;
signal gnd_pex_msi_num : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal gnd_pme_to_cr : STD_LOGIC;
signal gnd_rx_st_mask0 : STD_LOGIC;
signal gnd_rx_st_ready0 : STD_LOGIC;
signal gnd_tx_st_data0 : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal gnd_tx_st_eop0 : STD_LOGIC;
signal gnd_tx_st_err0 : STD_LOGIC;
signal gnd_tx_st_sop0 : STD_LOGIC;
signal gnd_tx_st_valid0 : STD_LOGIC;
signal gxb_powerdown_int : STD_LOGIC;
signal hip_extraclkout : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal hotrst_exit : STD_LOGIC;
signal internal_CraIrq_o : STD_LOGIC;
signal internal_CraReadData_o : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_CraWaitRequest_o : STD_LOGIC;
signal internal_RxmAddress_o : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_RxmBurstCount_o : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal internal_RxmRead_o : STD_LOGIC;
signal internal_RxmWrite_o : STD_LOGIC;
signal internal_TxsReadDataValid_o : STD_LOGIC;
signal internal_TxsReadData_o : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal internal_TxsWaitRequest_o : STD_LOGIC;
signal internal_clk250_out : STD_LOGIC;
signal internal_clk500_out : STD_LOGIC;
signal internal_lane_act : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_ltssm : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal internal_rate_ext : STD_LOGIC;
signal internal_rc_pll_locked : STD_LOGIC;
signal internal_rc_rx_digitalreset : STD_LOGIC;
signal internal_reconfig_fromgxb : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal internal_reset_status : STD_LOGIC;
signal internal_suc_spd_neg : STD_LOGIC;
signal internal_tl_cfg_add : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_tl_cfg_ctl : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_tl_cfg_ctl_wr : STD_LOGIC;
signal internal_tl_cfg_sts : STD_LOGIC_VECTOR (52 DOWNTO 0);
signal internal_tl_cfg_sts_wr : STD_LOGIC;
signal l2_exit : STD_LOGIC;
signal npor : STD_LOGIC;
signal npor_r : STD_LOGIC;
signal npor_rr : STD_LOGIC;
signal open_app_int_ack : STD_LOGIC;
signal open_app_msi_ack : STD_LOGIC;
signal open_gxb_powerdown : STD_LOGIC;
signal open_pme_to_sr : STD_LOGIC;
signal open_rc_rx_analogreset : STD_LOGIC;
signal open_rc_tx_digitalreset : STD_LOGIC;
signal open_rx_fifo_empty0 : STD_LOGIC;
signal open_rx_fifo_full0 : STD_LOGIC;
signal open_rx_st_bardec0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal open_rx_st_be0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal open_rx_st_data0 : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal open_rx_st_eop0 : STD_LOGIC;
signal open_rx_st_err0 : STD_LOGIC;
signal open_rx_st_sop0 : STD_LOGIC;
signal open_rx_st_valid0 : STD_LOGIC;
signal open_tx_fifo_empty0 : STD_LOGIC;
signal open_tx_fifo_full0 : STD_LOGIC;
signal open_tx_fifo_rdptr0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal open_tx_fifo_wrptr0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal open_tx_st_ready0 : STD_LOGIC;
signal pclk_central : STD_LOGIC;
signal pclk_central_serdes : STD_LOGIC;
signal pclk_ch0 : STD_LOGIC;
signal pclk_ch0_serdes : STD_LOGIC;
signal pclk_in : STD_LOGIC;
signal phystatus : STD_LOGIC;
signal phystatus_pcs : STD_LOGIC;
signal pipe_mode_int : STD_LOGIC;
signal pld_clk : STD_LOGIC;
signal pll_fixed_clk : STD_LOGIC;
signal pll_fixed_clk_serdes : STD_LOGIC;
signal pll_locked : STD_LOGIC;
signal pll_powerdown_int : STD_LOGIC;
signal powerdown : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal powerdown0_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal powerdown0_int : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rate_int : STD_LOGIC;
signal rateswitch : STD_LOGIC;
signal rateswitchbaseclock : STD_LOGIC;
signal rc_areset : STD_LOGIC;
signal rc_inclk_eq_125mhz : STD_LOGIC;
signal rc_rx_analogreset : STD_LOGIC;
signal rc_rx_pll_locked_one : STD_LOGIC;
signal rc_tx_digitalreset : STD_LOGIC;
signal reset_n_r : STD_LOGIC;
signal reset_n_rr : STD_LOGIC;
signal rsnt_cntn : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal rx_cruclk : STD_LOGIC;
signal rx_digitalreset_serdes : STD_LOGIC;
signal rx_freqlocked : STD_LOGIC;
signal rx_freqlocked_byte : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_in : STD_LOGIC;
signal rx_pll_locked : STD_LOGIC;
signal rx_pll_locked_byte : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_signaldetect_byte : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata_pcs : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak : STD_LOGIC;
signal rxdatak_pcs : STD_LOGIC;
signal rxelecidle : STD_LOGIC;
signal rxelecidle_pcs : STD_LOGIC;
signal rxpolarity : STD_LOGIC;
signal rxpolarity0_int : STD_LOGIC;
signal rxstatus : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus_pcs : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid : STD_LOGIC;
signal rxvalid_pcs : STD_LOGIC;
signal srst : STD_LOGIC;
signal test_out_int : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_deemph : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal tx_margin : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal tx_out : STD_LOGIC;
signal txcompl : STD_LOGIC;
signal txcompl0_int : STD_LOGIC;
signal txdata : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata0_int : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak : STD_LOGIC;
signal txdatak0_int : STD_LOGIC;
signal txdetectrx : STD_LOGIC;
signal txdetectrx0_ext : STD_LOGIC;
signal txdetectrx0_int : STD_LOGIC;
signal txelecidle : STD_LOGIC;
signal txelecidle0_int : STD_LOGIC;
signal use_c4gx_serdes : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of npor_r : signal is "SUPPRESS_DA_RULE_INTERNAL=R102";
attribute ALTERA_ATTRIBUTE of npor_rr : signal is "SUPPRESS_DA_RULE_INTERNAL=R102";
attribute ALTERA_ATTRIBUTE of reset_n_r : signal is "SUPPRESS_DA_RULE_INTERNAL=R105";
attribute ALTERA_ATTRIBUTE of reset_n_rr : signal is "SUPPRESS_DA_RULE_INTERNAL=R105";
begin
clk125_out <= core_clk_out;
pld_clk <= core_clk_out;
pcie_core_clk <= app_clk;
app_clk <= core_clk_out;
txdetectrx_ext <= txdetectrx0_ext;
powerdown_ext <= powerdown0_ext;
rxdata(7 DOWNTO 0) <= A_WE_StdLogicVector((std_logic'(pipe_mode_int) = '1'), rxdata0_ext, rxdata_pcs(7 DOWNTO 0));
phystatus <= A_WE_StdLogic((std_logic'(pipe_mode_int) = '1'), phystatus_ext, phystatus_pcs);
rxelecidle <= A_WE_StdLogic((std_logic'(pipe_mode_int) = '1'), rxelecidle0_ext, rxelecidle_pcs);
rxvalid <= A_WE_StdLogic((std_logic'(pipe_mode_int) = '1'), rxvalid0_ext, rxvalid_pcs);
txdata(7 DOWNTO 0) <= txdata0_int;
rxdatak <= A_WE_StdLogic((std_logic'(pipe_mode_int) = '1'), rxdatak0_ext, rxdatak_pcs);
rxstatus(2 DOWNTO 0) <= A_WE_StdLogicVector((std_logic'(pipe_mode_int) = '1'), rxstatus0_ext, rxstatus_pcs(2 DOWNTO 0));
powerdown(1 DOWNTO 0) <= powerdown0_int;
rxpolarity <= rxpolarity0_int;
txcompl <= txcompl0_int;
txdatak <= txdatak0_int;
txdetectrx <= txdetectrx0_int;
txelecidle <= txelecidle0_int;
txdata0_ext <= A_EXT (A_WE_StdLogicVector((std_logic'(pipe_mode_int) = '1'), (std_logic_vector'("000000000000000000000000") & (txdata0_int)), std_logic_vector'("00000000000000000000000000000000")), 8);
txdatak0_ext <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(pipe_mode_int) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(txdatak0_int))), std_logic_vector'("00000000000000000000000000000000")));
txdetectrx0_ext <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(pipe_mode_int) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(txdetectrx0_int))), std_logic_vector'("00000000000000000000000000000000")));
txelecidle0_ext <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(pipe_mode_int) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(txelecidle0_int))), std_logic_vector'("00000000000000000000000000000000")));
txcompl0_ext <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(pipe_mode_int) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(txcompl0_int))), std_logic_vector'("00000000000000000000000000000000")));
rxpolarity0_ext <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(pipe_mode_int) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rxpolarity0_int))), std_logic_vector'("00000000000000000000000000000000")));
powerdown0_ext <= A_EXT (A_WE_StdLogicVector((std_logic'(pipe_mode_int) = '1'), (std_logic_vector'("000000000000000000000000000000") & (powerdown0_int)), std_logic_vector'("00000000000000000000000000000000")), 2);
RxmWriteData_o <= RxmWriteData_int;
RxmReadData_int <= RxmReadData_i;
RxmByteEnable_o <= RxmByteEnable_int;
gnd_cpl_pending <= std_logic'('0');
gnd_cpl_err <= std_logic_vector'("0000000");
gnd_pme_to_cr <= std_logic'('0');
gnd_app_int_sts <= std_logic'('0');
gnd_app_msi_req <= std_logic'('0');
gnd_app_msi_tc <= std_logic_vector'("000");
gnd_app_msi_num <= std_logic_vector'("00000");
gnd_pex_msi_num <= std_logic_vector'("00000");
npor <= pcie_rstn;
--reset Synchronizer to PCIe clock
process (pld_clk, npor)
begin
if npor = '0' then
npor_r <= std_logic'('0');
npor_rr <= std_logic'('0');
elsif pld_clk'event and pld_clk = '1' then
npor_r <= std_logic'('1');
npor_rr <= npor_r;
end if;
end process;
--generate system reset request
process (pld_clk)
begin
if pld_clk'event and pld_clk = '1' then
if std_logic'(reset_n_rr) = std_logic'(std_logic'('0')) then
RxmResetRequest_o <= std_logic'('0');
elsif (((((std_logic'(npor_rr) = std_logic'(std_logic'('0')))) OR ((std_logic'(l2_exit) = std_logic'(std_logic'('0'))))) OR ((std_logic'(hotrst_exit) = std_logic'(std_logic'('0'))))) OR ((std_logic'(dlup_exit) = std_logic'(std_logic'('0'))))) OR ((internal_ltssm = std_logic_vector'("10000"))) then
RxmResetRequest_o <= std_logic'('1');
end if;
end if;
end process;
--reset Synchronizer to PCIe clock
process (pld_clk, reset_n)
begin
if reset_n = '0' then
reset_n_r <= std_logic'('0');
reset_n_rr <= std_logic'('0');
elsif pld_clk'event and pld_clk = '1' then
reset_n_r <= std_logic'('1');
reset_n_rr <= reset_n_r;
end if;
end process;
--reset counter
process (pld_clk, reset_n_rr)
begin
if reset_n_rr = '0' then
rsnt_cntn <= std_logic_vector'("00000000000");
elsif pld_clk'event and pld_clk = '1' then
if rsnt_cntn /= std_logic_vector'("00000001111") then
rsnt_cntn <= A_EXT (((std_logic_vector'("0000000000000000000000") & (rsnt_cntn)) + std_logic_vector'("000000000000000000000000000000001")), 11);
end if;
end if;
end process;
--sync and config reset
process (pld_clk, reset_n_rr)
begin
if reset_n_rr = '0' then
srst <= std_logic'('1');
crst <= std_logic'('1');
elsif pld_clk'event and pld_clk = '1' then
if rsnt_cntn = std_logic_vector'("00000001111") then
srst <= std_logic'('0');
crst <= std_logic'('0');
end if;
end if;
end process;
rx_in <= rx_in0;
tx_out0 <= tx_out;
rc_inclk_eq_125mhz <= std_logic'('1');
pclk_central_serdes <= std_logic'('0');
pll_fixed_clk_serdes <= rateswitchbaseclock;
rateswitchbaseclock <= pclk_ch0_serdes;
internal_rc_pll_locked <= A_WE_StdLogic(((std_logic'(pipe_mode_int) = std_logic'(std_logic'('1')))), std_logic'('1'), pll_locked);
gxb_powerdown_int <= A_WE_StdLogic(((std_logic'(pipe_mode_int) = std_logic'(std_logic'('1')))), std_logic'('1'), gxb_powerdown);
pll_powerdown_int <= A_WE_StdLogic(((std_logic'(pipe_mode_int) = std_logic'(std_logic'('1')))), std_logic'('1'), pll_powerdown);
rx_pll_locked <= std_logic'('1');
rx_cruclk <= refclk;
rc_areset <= (pipe_mode_int OR NOT npor) OR busy_altgxb_reconfig;
pclk_central <= A_WE_StdLogic(((std_logic'(pipe_mode_int) = std_logic'(std_logic'('1')))), pclk_in, pclk_central_serdes);
pclk_ch0 <= A_WE_StdLogic(((std_logic'(pipe_mode_int) = std_logic'(std_logic'('1')))), pclk_in, pclk_ch0_serdes);
rateswitch <= rate_int;
internal_rate_ext <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(pipe_mode_int) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rate_int))), std_logic_vector'("00000000000000000000000000000000")));
pll_fixed_clk <= A_WE_StdLogic(((std_logic'(pipe_mode_int) = std_logic'(std_logic'('1')))), internal_clk250_out, pll_fixed_clk_serdes);
pclk_in <= A_WE_StdLogic(((std_logic'(internal_rate_ext) = std_logic'(std_logic'('1')))), internal_clk500_out, internal_clk250_out);
rc_rx_pll_locked_one <= rx_pll_locked OR rx_freqlocked;
use_c4gx_serdes <= std_logic'('1');
fifo_err <= std_logic'('0');
rx_freqlocked_byte(0) <= rx_freqlocked;
rx_freqlocked_byte(7 DOWNTO 1) <= std_logic_vector'("1111111");
rx_pll_locked_byte(0) <= rx_pll_locked;
rx_pll_locked_byte(7 DOWNTO 1) <= std_logic_vector'("1111111");
rx_signaldetect_byte(7 DOWNTO 0) <= std_logic_vector'("11111111");
detect_mask_rxdrst <= std_logic'('0');
core_clk_in <= std_logic'('0');
gnd_rx_st_ready0 <= std_logic'('0');
gnd_rx_st_mask0 <= std_logic'('0');
gnd_tx_st_sop0 <= std_logic'('0');
gnd_tx_st_eop0 <= std_logic'('0');
gnd_tx_st_err0 <= std_logic'('0');
gnd_tx_st_valid0 <= std_logic'('0');
gnd_tx_st_data0 <= std_logic_vector'("000000000000000000000000000000000000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('0')));
serdes : pcie_compiler_0_serdes
port map(
cal_blk_clk => cal_blk_clk,
fixedclk => fixedclk_serdes,
gxb_powerdown => A_TOSTDLOGICVECTOR(gxb_powerdown_int),
hip_tx_clkout(0) => pclk_ch0_serdes,
pipe8b10binvpolarity => A_TOSTDLOGICVECTOR(rxpolarity),
pipedatavalid(0) => rxvalid_pcs,
pipeelecidle(0) => rxelecidle_pcs,
pipephydonestatus(0) => phystatus_pcs,
pipestatus => rxstatus_pcs,
pll_areset => A_TOSTDLOGICVECTOR(pll_powerdown_int),
pll_inclk => A_TOSTDLOGICVECTOR(refclk),
pll_locked(0) => pll_locked,
powerdn => powerdown,
reconfig_clk => reconfig_clk,
reconfig_fromgxb => internal_reconfig_fromgxb,
reconfig_togxb => reconfig_togxb,
rx_analogreset => A_TOSTDLOGICVECTOR(rc_rx_analogreset),
rx_ctrldetect(0) => rxdatak_pcs,
rx_datain => A_TOSTDLOGICVECTOR(rx_in),
rx_dataout => rxdata_pcs,
rx_digitalreset => A_TOSTDLOGICVECTOR(rx_digitalreset_serdes),
rx_elecidleinfersel => eidle_infer_sel(2 DOWNTO 0),
rx_freqlocked(0) => rx_freqlocked,
tx_ctrlenable => A_TOSTDLOGICVECTOR(txdatak),
tx_datain => txdata,
tx_dataout(0) => tx_out,
tx_detectrxloop => A_TOSTDLOGICVECTOR(txdetectrx),
tx_digitalreset => A_TOSTDLOGICVECTOR(rc_tx_digitalreset),
tx_forcedispcompliance => A_TOSTDLOGICVECTOR(txcompl),
tx_forceelecidle => A_TOSTDLOGICVECTOR(txelecidle)
);
rs_serdes : altpcie_rs_serdes
port map(
busy_altgxb_reconfig => busy_altgxb_reconfig,
detect_mask_rxdrst => detect_mask_rxdrst,
fifo_err => fifo_err,
ltssm => internal_ltssm,
npor => npor,
pld_clk => pld_clk,
pll_locked => internal_rc_pll_locked,
rc_inclk_eq_125mhz => rc_inclk_eq_125mhz,
rx_freqlocked => rx_freqlocked_byte,
rx_pll_locked => rx_pll_locked_byte,
rx_signaldetect => rx_signaldetect_byte,
rxanalogreset => rc_rx_analogreset,
rxdigitalreset => rx_digitalreset_serdes,
test_in => test_in,
txdigitalreset => rc_tx_digitalreset,
use_c4gx_serdes => use_c4gx_serdes
);
wrapper : pcie_compiler_0_core
port map(
AvlClk_i => AvlClk_i,
CraAddress_i => CraAddress_i,
CraByteEnable_i => CraByteEnable_i,
CraChipSelect_i => CraChipSelect_i,
CraIrq_o => internal_CraIrq_o,
CraRead => CraRead,
CraReadData_o => internal_CraReadData_o,
CraWaitRequest_o => internal_CraWaitRequest_o,
CraWrite => CraWrite,
CraWriteData_i => CraWriteData_i,
Rstn_i => reset_n,
RxmAddress_o => internal_RxmAddress_o,
RxmBurstCount_o => internal_RxmBurstCount_o,
RxmByteEnable_o => RxmByteEnable_int,
RxmIrqNum_i => RxmIrqNum_i,
RxmIrq_i => RxmIrq_i,
RxmReadDataValid_i => RxmReadDataValid_i,
RxmReadData_i => RxmReadData_int,
RxmRead_o => internal_RxmRead_o,
RxmWaitRequest_i => RxmWaitRequest_i,
RxmWriteData_o => RxmWriteData_int,
RxmWrite_o => internal_RxmWrite_o,
TxsAddress_i => TxsAddress_i,
TxsBurstCount_i => TxsBurstCount_i,
TxsByteEnable_i => TxsByteEnable_i,
TxsChipSelect_i => TxsChipSelect_i,
TxsReadDataValid_o => internal_TxsReadDataValid_o,
TxsReadData_o => internal_TxsReadData_o,
TxsRead_i => TxsRead_i,
TxsWaitRequest_o => internal_TxsWaitRequest_o,
TxsWriteData_i => TxsWriteData_i,
TxsWrite_i => TxsWrite_i,
aer_msi_num => std_logic_vector'("00000"),
app_int_ack => open_app_int_ack,
app_int_sts => gnd_app_int_sts,
app_msi_ack => open_app_msi_ack,
app_msi_num => gnd_app_msi_num,
app_msi_req => gnd_app_msi_req,
app_msi_tc => gnd_app_msi_tc,
core_clk_in => core_clk_in,
core_clk_out => core_clk_out,
cpl_err => gnd_cpl_err,
cpl_pending => gnd_cpl_pending,
crst => crst,
dl_ltssm => internal_ltssm,
dlup_exit => dlup_exit,
eidle_infer_sel => eidle_infer_sel,
hip_extraclkout => hip_extraclkout,
hotrst_exit => hotrst_exit,
hpg_ctrler => std_logic_vector'("00000"),
l2_exit => l2_exit,
lane_act => internal_lane_act,
lmi_addr => std_logic_vector'("000000000000"),
lmi_din => std_logic_vector'("00000000000000000000000000000000"),
lmi_rden => std_logic'('0'),
lmi_wren => std_logic'('0'),
npor => npor,
pclk_central => pclk_central,
pclk_ch0 => pclk_ch0,
pex_msi_num => gnd_pex_msi_num,
phystatus0_ext => phystatus,
pld_clk => pld_clk,
pll_fixed_clk => pll_fixed_clk,
pm_auxpwr => std_logic'('0'),
pm_data => std_logic_vector'("0000000000"),
pm_event => std_logic'('0'),
pme_to_cr => gnd_pme_to_cr,
pme_to_sr => open_pme_to_sr,
powerdown0_ext => powerdown0_int,
rate_ext => rate_int,
rc_areset => rc_areset,
rc_gxb_powerdown => open_gxb_powerdown,
rc_inclk_eq_125mhz => rc_inclk_eq_125mhz,
rc_pll_locked => internal_rc_pll_locked,
rc_rx_analogreset => open_rc_rx_analogreset,
rc_rx_digitalreset => internal_rc_rx_digitalreset,
rc_rx_pll_locked_one => rc_rx_pll_locked_one,
rc_tx_digitalreset => open_rc_tx_digitalreset,
reset_status => internal_reset_status,
rx_fifo_empty0 => open_rx_fifo_empty0,
rx_fifo_full0 => open_rx_fifo_full0,
rx_st_bardec0 => open_rx_st_bardec0,
rx_st_be0 => open_rx_st_be0,
rx_st_data0 => open_rx_st_data0,
rx_st_eop0 => open_rx_st_eop0,
rx_st_err0 => open_rx_st_err0,
rx_st_mask0 => gnd_rx_st_mask0,
rx_st_ready0 => gnd_rx_st_ready0,
rx_st_sop0 => open_rx_st_sop0,
rx_st_valid0 => open_rx_st_valid0,
rxdata0_ext => rxdata(7 DOWNTO 0),
rxdatak0_ext => rxdatak,
rxelecidle0_ext => rxelecidle,
rxpolarity0_ext => rxpolarity0_int,
rxstatus0_ext => rxstatus(2 DOWNTO 0),
rxvalid0_ext => rxvalid,
srst => srst,
suc_spd_neg => internal_suc_spd_neg,
test_in => test_in,
test_out => test_out_int,
tl_cfg_add => internal_tl_cfg_add,
tl_cfg_ctl => internal_tl_cfg_ctl,
tl_cfg_ctl_wr => internal_tl_cfg_ctl_wr,
tl_cfg_sts => internal_tl_cfg_sts,
tl_cfg_sts_wr => internal_tl_cfg_sts_wr,
tx_deemph => tx_deemph,
tx_fifo_empty0 => open_tx_fifo_empty0,
tx_fifo_full0 => open_tx_fifo_full0,
tx_fifo_rdptr0 => open_tx_fifo_rdptr0,
tx_fifo_wrptr0 => open_tx_fifo_wrptr0,
tx_margin => tx_margin,
tx_st_data0 => gnd_tx_st_data0,
tx_st_data0_p1 => std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000"),
tx_st_eop0 => gnd_tx_st_eop0,
tx_st_eop0_p1 => std_logic'('0'),
tx_st_err0 => gnd_tx_st_err0,
tx_st_ready0 => open_tx_st_ready0,
tx_st_sop0 => gnd_tx_st_sop0,
tx_st_sop0_p1 => std_logic'('0'),
tx_st_valid0 => gnd_tx_st_valid0,
txcompl0_ext => txcompl0_int,
txdata0_ext => txdata0_int,
txdatak0_ext => txdatak0_int,
txdetectrx0_ext => txdetectrx0_int,
txelecidle0_ext => txelecidle0_int
);
--vhdl renameroo for output signals
CraIrq_o <= internal_CraIrq_o;
--vhdl renameroo for output signals
CraReadData_o <= internal_CraReadData_o;
--vhdl renameroo for output signals
CraWaitRequest_o <= internal_CraWaitRequest_o;
--vhdl renameroo for output signals
RxmAddress_o <= internal_RxmAddress_o;
--vhdl renameroo for output signals
RxmBurstCount_o <= internal_RxmBurstCount_o;
--vhdl renameroo for output signals
RxmRead_o <= internal_RxmRead_o;
--vhdl renameroo for output signals
RxmWrite_o <= internal_RxmWrite_o;
--vhdl renameroo for output signals
TxsReadDataValid_o <= internal_TxsReadDataValid_o;
--vhdl renameroo for output signals
TxsReadData_o <= internal_TxsReadData_o;
--vhdl renameroo for output signals
TxsWaitRequest_o <= internal_TxsWaitRequest_o;
--vhdl renameroo for output signals
clk250_out <= internal_clk250_out;
--vhdl renameroo for output signals
clk500_out <= internal_clk500_out;
--vhdl renameroo for output signals
lane_act <= internal_lane_act;
--vhdl renameroo for output signals
ltssm <= internal_ltssm;
--vhdl renameroo for output signals
rate_ext <= internal_rate_ext;
--vhdl renameroo for output signals
rc_pll_locked <= internal_rc_pll_locked;
--vhdl renameroo for output signals
rc_rx_digitalreset <= internal_rc_rx_digitalreset;
--vhdl renameroo for output signals
reconfig_fromgxb <= internal_reconfig_fromgxb;
--vhdl renameroo for output signals
reset_status <= internal_reset_status;
--vhdl renameroo for output signals
suc_spd_neg <= internal_suc_spd_neg;
--vhdl renameroo for output signals
tl_cfg_add <= internal_tl_cfg_add;
--vhdl renameroo for output signals
tl_cfg_ctl <= internal_tl_cfg_ctl;
--vhdl renameroo for output signals
tl_cfg_ctl_wr <= internal_tl_cfg_ctl_wr;
--vhdl renameroo for output signals
tl_cfg_sts <= internal_tl_cfg_sts;
--vhdl renameroo for output signals
tl_cfg_sts_wr <= internal_tl_cfg_sts_wr;
--synthesis translate_off
pipe_mode_int <= pipe_mode;
refclk_to_250mhz : altpcie_pll_100_250
port map(
areset => std_logic'('0'),
c0 => internal_clk250_out,
inclk0 => refclk
);
pll_250mhz_to_500mhz : altpcie_pll_125_250
port map(
areset => std_logic'('0'),
c0 => internal_clk500_out,
inclk0 => internal_clk250_out
);
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- pipe_mode_int <= std_logic'('0');
--synthesis read_comments_as_HDL off
end europa;
-- =========================================================
-- IP Compiler for PCI Express Wizard Data
-- ===============================
-- DO NOT EDIT FOLLOWING DATA
-- @Altera, IP Toolbench@
-- Warning: If you modify this section, IP Compiler for PCI Express Wizard may not be able to reproduce your chosen configuration.
--
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <MEGACORE title="IP Compiler for PCI Express" version="11.1" build="259" iptb_version="1.3.0 Build 259" format_version="120" >
-- Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.MVCModel" active_core="altpcie_hip_pipen1b" >
-- Retrieval info: <STATIC_SECTION>
-- Retrieval info: <PRIVATES>
-- Retrieval info: <NAMESPACE name = "parameterization">
-- Retrieval info: <PRIVATE name = "p_pcie_phy" value="Cyclone IV GX" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_port_type" value="Native Endpoint" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_tag_supported" value="32" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_msi_message_requested" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_low_priority_virtual_channels" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_retry_fifo_depth" value="64" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nfts_common_clock" value="255" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nfts_separate_clock" value="255" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_exp_rom_bar_used" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_link_common_clock" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_advanced_error_reporting" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_ecrc_check" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_ecrc_generation" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_power_indicator" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_attention_indicator" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_attention_button" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_msi_message_64bits_address_capable" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_auto_configure_retry_buffer" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_implement_data_register" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_device_init_required" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_L1_aspm" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_rate_match_fifo" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_fast_recovery" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "SOPCSystemName" value="unici_core" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR0AvalonAddress" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR0Size" value="15" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR1AvalonAddress" value="262144" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR1Size" value="18" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR2AvalonAddress" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR2Size" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR3AvalonAddress" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR3Size" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR4AvalonAddress" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR4Size" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR5AvalonAddress" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR5Size" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "allowedDeviceFamilies" value="[Stratix III, Stratix II, HardCopy II, Stratix II GX, Stratix, Stratix GX, Cyclone III LS, Cyclone V, Cyclone IV E, Cyclone IV GX, Cyclone III, Cyclone II, Cyclone, MAX II, MAX V, Arria GX, Stratix IV, Stratix V, Arria II GX, HardCopy III, HardCopy IV, Arria II GZ, Arria V, Unknown, None]" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "altgx_generated" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "clockSource" value="pcie_core_clk" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "contextState" value="SOPCContext" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "deviceFamily" value="Cyclone IV GX" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ordering_code" value="IP-PCIE/4" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hardwired_address_map" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_00" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_00_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_01" value="0x0000000080000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_01_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_02" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_02_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_03" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_03_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_04" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_04_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_05" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_05_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_06" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_06_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_07" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_07_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_08" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_08_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_09" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_09_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_10" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_10_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_11" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_11_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_12" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_12_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_13" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_13_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_14" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_14_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_15" value="0x0000000000000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_hw_pci_address_15_type" value="Memory32Bit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_pane_count" value="2" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_avalon_pane_size" value="30" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_enable_pcie_hip_dprio" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_64bit_bar" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_64bit_bus" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_66mhz" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_allow_param_readback" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_altera_arbiter" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_arbited_devices" value="2" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_arbiter" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_0_auto_avalon_address" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_0_auto_sized" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_0_avalon_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_0_hardwired" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_0_pci_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_0_prefetchable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_1_auto_avalon_address" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_1_auto_sized" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_1_avalon_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_1_hardwired" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_1_pci_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_1_prefetchable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_2_auto_avalon_address" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_2_auto_sized" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_2_avalon_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_2_hardwired" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_2_pci_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_2_prefetchable" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_3_auto_avalon_address" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_3_auto_sized" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_3_avalon_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_3_hardwired" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_3_pci_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_3_prefetchable" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_4_auto_avalon_address" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_4_auto_sized" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_4_avalon_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_4_hardwired" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_4_pci_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_4_prefetchable" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_5_auto_avalon_address" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_5_auto_sized" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_5_avalon_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_5_hardwired" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_5_pci_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_5_prefetchable" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bus_access_address_width" value="28" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_global_reset" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_host_bridge" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_impl_cra_av_slave_port" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_master" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_master_bursts" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_master_concurrent_reads" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_master_data_width" value="64" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_maximum_burst_size" value="128" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_maximum_burst_size_a2p" value="128" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_maximum_pending_read_transactions_a2p" value="8" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_non_pref_av_master_port" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_not_target_only_port" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_pref_av_master_port" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_reqn_gntn_pins" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_single_clock" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_target_bursts" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_target_concurrent_reads" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_user_specified_bars" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_L1_exit_latency_common_clock" value=">64 us" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_L1_exit_latency_separate_clock" value=">64 us" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_advanced_error_int_num" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_alt2gxb" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_altgx_keyParameters_used" value="{p_pcie_enable_hip=1, p_pcie_number_of_lanes=x1, p_pcie_phy=Cyclone IV GX, p_pcie_rate=Gen1 (2.5 Gbps), p_pcie_txrx_clock=100 MHz}" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_app_signal_interface" value="AvalonMM" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_avalon_mm_lite" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_0" value="32 KBytes - 15 bits" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_1" value="256 KBytes - 18 bits" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_2" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_3" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_4" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_5" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_0" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_1" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_2" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_3" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_4" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_5" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_0" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_1" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_2" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_3" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_4" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_5" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_channel_number" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_chk_io" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_class_code" value="0x048000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_data_credit_vc0" value="256" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_data_credit_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_data_credit_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_data_credit_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_data_used_space_vc0" value="4096" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_data_used_space_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_data_used_space_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_data_used_space_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_header_credit_vc0" value="48" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_header_credit_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_header_credit_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_header_credit_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_header_used_space_vc0" value="768" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_header_used_space_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_header_used_space_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_header_used_space_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_timeout" value="NONE" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_custom_phy_x8" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_custom_rx_buffer_xml" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_device_id" value="0x18F6" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_disable_L0s" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_dll_active_report_support" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_eie_b4_nfts_count" value="4" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_completion_timeout_disable" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_function_msix_support" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_hip" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_hip_core_clk" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_pcie_gen2_x8_es" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_pcie_gen2_x8_s5gx" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_root_port_endpoint_mode" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_simple_dma" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_slot_capability" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_enable_tl_bypass_mode" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_endpoint_L0s_acceptable_latency" value="<64 ns" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_endpoint_L1_acceptable_latency" value="<1 us" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_exp_rom_bar_size" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_gen2_nfts_diff_clock" value="255" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_gen2_nfts_same_clock" value="255" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_initiator_performance_preset" value="High" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_internal_clock" value="62.5 MHz" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_io_base_and_limit_register" value="IODisable" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_lanerev" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_link_port_number" value="0x01" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_max_payload_size" value="256 Bytes" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_mem_base_and_limit_register" value="MemDisable" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_msix_pba_bir" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_msix_pba_offset" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_msix_table_bir" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_msix_table_offset" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_msix_table_size" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_data_credit_vc0" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_data_credit_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_data_credit_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_data_credit_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_data_used_space_vc0" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_data_used_space_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_data_used_space_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_data_used_space_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_header_credit_vc0" value="30" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_header_credit_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_header_credit_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_header_credit_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_header_used_space_vc0" value="480" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_header_used_space_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_header_used_space_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nonposted_header_used_space_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_number_of_lanes" value="x1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_phy_interface" value="Serial" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_pme_pending" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_pme_reg_id" value="0x0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_data_credit_vc0" value="198" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_data_credit_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_data_credit_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_data_credit_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_data_used_space_vc0" value="3168" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_data_used_space_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_data_used_space_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_data_used_space_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_header_credit_vc0" value="28" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_header_credit_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_header_credit_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_header_credit_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_header_used_space_vc0" value="448" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_header_used_space_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_header_used_space_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_posted_header_used_space_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_rate" value="Gen1 (2.5 Gbps)" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_retry_buffer_size" value="2 KBytes" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_revision_id" value="0x02" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_rx_buffer_preset" value="Default" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_rx_buffer_size_string_vc0" value="8960 Bytes" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_rx_buffer_size_string_vc1" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_rx_buffer_size_string_vc2" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_rx_buffer_size_string_vc3" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_rx_buffer_size_vc0" value="8960" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_rx_buffer_size_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_rx_buffer_size_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_rx_buffer_size_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_slot_capabilities" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_special_phy_gl" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_special_phy_px" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_subsystem_device_id" value="0x18F6" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_subsystem_vendor_id" value="0x1B55" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_surprise_down_error_support" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_target_performance_preset" value="Maximum" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_test_out_width" value="None" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_threshold_for_L0s_entry" value="8192 ns" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_total_header_credit_vc0" value="106" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_total_header_credit_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_total_header_credit_vc2" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_total_header_credit_vc3" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_txrx_clock" value="100 MHz" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_underSOPCBuilder" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_use_crc_forwarding" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_use_parity" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_variation_name" value="pcie_compiler_0_core" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_vendor_id" value="0x1B55" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_version" value="1.1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_virutal_channels" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "pref_nonp_independent" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "translationTableSizeInfo" value="The bridge reserves a contiguous Avalon address range to access
-- Retrieval info: PCIe devices. This Avalon address range is segmented into one or
-- Retrieval info: more equal-sized pages that are individually mapped to PCIe
-- Retrieval info: addresses. Select the number and size of the address pages." type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress0" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress1" value="0x80000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress10" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress11" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress12" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress13" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress14" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress15" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress2" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress3" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress4" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress5" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress6" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress7" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress8" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWAddress9" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress0" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress1" value="0x80000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress10" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress11" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress12" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress13" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress14" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress15" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress2" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress3" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress4" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress5" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress6" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress7" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress8" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress9" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonTranslationTable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar0PCIAddress" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar0Prefetchable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar1PCIAddress" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar1Prefetchable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar2PCIAddress" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar2Prefetchable" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar3PCIAddress" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar3Prefetchable" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar4PCIAddress" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar4Prefetchable" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar5PCIAddress" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar5Prefetchable" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiCRAInfoPanel" value="dynamicTable" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiExpROMType" value="Select to Enable" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiFixedTable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar0Type" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar1Type" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar2Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar3Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar4Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar5Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBarTable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBusArbiter" value="external" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIDeviceMode" value="masterTarget" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIMasterPerformance" value="burstSinglePending" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCITargetPerformance" value="burstSinglePending" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPaneCount" value="2" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPaneSize" value="30" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ui_pcie_msix_pba_bir" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ui_pcie_msix_table_bir" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_tx_cdc_full_value" value="12" type="INTEGER" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen_enable">
-- Retrieval info: <PRIVATE name = "language" value="VHDL" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "greybox">
-- Retrieval info: <PRIVATE name = "gb_enabled" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filename" value="pcie_compiler_0_syn.v" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "testbench">
-- Retrieval info: <PRIVATE name = "plugin_worker" value="1" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen">
-- Retrieval info: <PRIVATE name = "filename" value="pcie_compiler_0_core.vhd" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "serializer"/>
-- Retrieval info: </PRIVATES>
-- Retrieval info: <FILES/>
-- Retrieval info: <PORTS/>
-- Retrieval info: <LIBRARIES/>
-- Retrieval info: </STATIC_SECTION>
-- Retrieval info: </NETLIST_SECTION>
-- Retrieval info: </MEGACORE>
-- =========================================================
|
gpl-3.0
|
226335ff2d0a5b0dc3bb75044980b560
| 0.620347 | 3.380679 | false | false | false | false |
maijohnson/comp3601_blue_15s2
|
AudioController/memory_controller.vhd
| 1 | 8,747 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : sch2hdl
-- / / Filename : DemoWithMemCfg.vhf
-- /___/ /\ Timestamp : 09/05/2015 14:10:23
-- \ \ / \
-- \___\/\___\
--
--Command: D:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\sch2hdl.exe -intstyle ise -family spartan3 -flat -suppress -vhdl DemoWithMemCfg.vhf -w C:/Comp3601/N/Nexys_BIST/DemoWithMemCfg.sch
--Design Name: DemoWithMemCfg
--Device: spartan3
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesized and simulated, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity memory_controller is
port ( clk : in std_logic;
EppAstb : in std_logic;
EppDstb : in std_logic;
EppWr : in std_logic;
FlashStSts : in std_logic;
RamWait : in std_logic;
EppWait : out std_logic;
FlashCS : out std_logic;
FlashRp : out std_logic;
MemAdr : out std_logic_vector (23 downto 1);
MemOe : out std_logic;
MemWr : out std_logic;
RamAdv : out std_logic;
RamClk : out std_logic;
RamCre : out std_logic;
RamCS : out std_logic;
RamLB : out std_logic;
RamUB : out std_logic;
EppDB : inout std_logic_vector (7 downto 0);
MemDB : inout std_logic_vector (15 downto 0);
BTN : in std_logic;
dataout : inout std_logic_vector (15 downto 0);
Reset : in std_logic
);
end memory_controller;
architecture BEHAVIORAL of memory_controller is
attribute BOX_TYPE : string ;
signal XLXN_1 : std_logic_vector (7 downto 0);
signal XLXN_6 : std_logic;
signal XLXN_7 : std_logic;
signal XLXN_8 : std_logic;
signal XLXN_10 : std_logic;
signal XLXN_38 : std_logic;
signal XLXN_108 : std_logic_vector (7 downto 0);
signal XLXN_187 : std_logic_vector (7 downto 0);
signal XLXN_190 : std_logic;
signal XLXN_279 : std_logic;
signal XLXN_280 : std_logic_vector (7 downto 0);
component EppCtrl
port ( HandShakeReqIn : in std_logic;
ctlEppDoneIn : in std_logic;
busEppIn : in std_logic_vector (7 downto 0);
ctlEppRdCycleOut : inout std_logic;
regEppAdrOut : inout std_logic_vector (7 downto 0);
ctlEppDwrOut : out std_logic;
ctlEppStartOut : out std_logic;
busEppOut : out std_logic_vector (7 downto 0);
clk : in std_logic;
EppAstb : in std_logic;
EppDstb : in std_logic;
EppWr : in std_logic;
EppRst : in std_logic;
EppDB : inout std_logic_vector (7 downto 0);
EppWait : out std_logic);
end component;
component CompSel
port ( regEppAdrIn : in std_logic_vector (7 downto 0);
CS80_9F : out std_logic;
CS0_7 : out std_logic;
CS8_F : out std_logic);
end component;
component PhoenixOnBoardMemCtrl
port ( clk : in std_logic;
ctlMsmStartIn : in std_logic;
ctlMsmDwrIn : in std_logic;
ctlEppRdCycleIn : in std_logic;
ComponentSelect : in std_logic;
RamWait : in std_logic;
FlashStSts : in std_logic;
EppWrDataIn : in std_logic_vector (7 downto 0);
regEppAdrIn : in std_logic_vector (7 downto 0);
MemDB : inout std_logic_vector (15 downto 0);
HandShakeReqOut : out std_logic;
ctlMsmDoneOut : out std_logic;
FlashByte : out std_logic;
RamCS : out std_logic;
FlashCS : out std_logic;
MemWR : out std_logic;
MemOE : out std_logic;
RamUB : out std_logic;
RamLB : out std_logic;
RamCre : out std_logic;
RamAdv : out std_logic;
RamClk : out std_logic;
FlashRp : out std_logic;
MemCtrlEnabled : out std_logic;
EppRdDataOut : out std_logic_vector (7 downto 0);
MemAdr : out std_logic_vector (23 downto 1);
ReadReq: in std_logic;
DataRdy: out std_logic;
DataOut :out std_logic_vector(7 downto 0);
DataAck: in std_logic;
Reset : in std_logic
);
end component;
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
signal data : std_logic_vector(7 downto 0);
signal dataHigh : std_logic_vector(7 downto 0);
signal test_count : integer range 0 to 21 := 0;
signal stage : integer range 0 to 10 := 0;
signal memRead : std_logic;
signal Datardy : std_logic;
signal DataAck : std_logic;
signal lock: std_logic := '0';
begin
process (BTN, clk) -- Do a double read cycle
Begin
if (BTN'event and BTN = '1' and stage = 0) then
stage <= 1;
memRead <= '1';
end if;
if (clk'event and clk = '1' AND stage /= 0) then
test_count <= test_count + 1;
end if;
if (test_count = 4 ) then
memRead <= '0';
stage <= 1;
elsif (test_count = 20) And stage = 2 then
memRead <= '0';
stage <= 0;
elsif (test_count = 15) and stage = 1 then
memRead <= '1';
stage <= 2;
end if;
end process;
process (DataRdy)
Begin
if DataRdy = '1' then
DataAck <= '1';
else
DataAck <= '0';
end if;
end process;
process (Data)
Begin
if (stage = 1) then
DataHigh <= data(7 downto 0);
else
DataOut <= DataHigh & data(7 downto 0);
end if;
end process;
XLXI_1 : EppCtrl
port map (busEppIn(7 downto 0)=>XLXN_187(7 downto 0),
clk=>clk,
ctlEppDoneIn=>XLXN_8,
EppAstb=>EppAstb,
EppDstb=>EppDstb,
EppRst=>XLXN_38,
EppWr=>EppWr,
HandShakeReqIn=>XLXN_6,
busEppOut(7 downto 0)=>XLXN_1(7 downto 0),
ctlEppDwrOut=>XLXN_279,
ctlEppStartOut=>XLXN_7,
EppWait=>EppWait,
ctlEppRdCycleOut=>XLXN_190,
EppDB(7 downto 0)=>EppDB(7 downto 0),
regEppAdrOut(7 downto 0)=>XLXN_280(7 downto 0));
XLXI_4 : CompSel
port map (regEppAdrIn(7 downto 0)=>XLXN_280(7 downto 0),
CS0_7=>XLXN_10,
CS8_F=>open,
CS80_9F=>open);
XLXI_6 : PhoenixOnBoardMemCtrl
port map (clk=>clk,
ComponentSelect=>XLXN_10,
ctlEppRdCycleIn=>XLXN_190,
ctlMsmDwrIn=>XLXN_279,
ctlMsmStartIn=>XLXN_7,
EppWrDataIn(7 downto 0)=>XLXN_1(7 downto 0),
FlashStSts=>FlashStSts,
RamWait=>RamWait,
regEppAdrIn(7 downto 0)=>XLXN_280(7 downto 0),
ctlMsmDoneOut=>XLXN_8,
EppRdDataOut(7 downto 0)=>XLXN_187(7 downto 0),
FlashByte=>open,
FlashCS=>FlashCS,
FlashRp=>FlashRp,
HandShakeReqOut=>XLXN_6,
MemAdr(23 downto 1)=>MemAdr(23 downto 1),
MemCtrlEnabled=>open,
MemOE=>MemOe,
MemWR=>MemWr,
RamAdv=>RamAdv,
RamClk=>RamClk,
RamCre=>RamCre,
RamCS=>RamCS,
RamLB=>RamLB,
RamUB=>RamUB,
MemDB(15 downto 0)=>MemDB(15 downto 0),
ReadReq => MemRead,
DataRdy => DataRdy,
DataOut => data,
DataAck=> DataAck,
Reset => Reset
);
XLXI_7 : VCC
port map (P=>XLXN_38);
end BEHAVIORAL;
|
mit
|
dfc72f16ea76fbffdf826d8c4fd5625a
| 0.488853 | 3.880657 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/Common/Source/EdgeDetector.vhd
| 1 | 2,579 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Detects rising and/or a falling clock edges of a signal and provides a one-
-- clock-cycle tick on every edge.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity EdgeDetector is
generic
(
detect_rising_edges: boolean := true;
detect_falling_edges: boolean := false
);
port
(
-- The system clock.
clk: in std_logic;
-- The signal to detect edges from.
sigin: in std_logic;
-- Indicates whether an edge has been detected in the current clock cycle.
edge: out std_logic
);
end entity;
architecture stdarch of EdgeDetector is
signal reg_sigin: std_logic := '0';
begin
-------------------------------------
-- State register.
-------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
reg_sigin <= sigin;
end process;
-------------------------------------
-- Output logic (Mealy).
-------------------------------------
detect_rising_edge: if (detect_rising_edges and (not detect_falling_edges)) generate
edge <= (not reg_sigin) and sigin;
end generate;
detect_falling_edge: if ((not detect_rising_edges) and detect_falling_edges) generate
edge <= reg_sigin and (not sigin);
end generate;
detect_both_edges: if (detect_rising_edges and detect_falling_edges) generate
edge <= reg_sigin xor sigin;
end generate;
end architecture;
|
gpl-3.0
|
ffa2f9d9b02b1f6ded7651e5388ce202
| 0.528499 | 4.838649 | false | false | false | false |
wyvernSemi/vproc
|
test.vhd
| 1 | 7,646 |
-- =============================================================
--
-- Top level demonstration test environment for VProc
--
-- Copyright (c) 2021 Simon Southwell. Confidential
--
-- This file is part of VProc.
--
-- VProc is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- VProc is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with VProc. If not, see <http://www.gnu.org/licenses/>.
--
-- $Id: test.vhd,v 1.1 2021/05/04 15:59:07 simon Exp $
-- $Source: /home/simon/CVS/src/HDL/VProc/test.vhd,v $
--
-- =============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.env.all;
entity test is
end entity;
architecture sim of test is
---------------------------------------------
-- Declarations
---------------------------------------------
type array_t is array (natural range <>) of std_logic_vector;
constant FREQ : real := 100.0e6;
constant ClkPeriod : time := 1 sec / FREQ;
constant StopCount : integer := 100;
signal Clk : std_logic := '1';
signal Count : integer := 0;
signal Interrupt0, Interrupt1 : std_logic_vector(2 downto 0) := "000";
signal notReset_H : std_logic := '0';
signal UpdateResponse : std_logic_vector(1 downto 0) := "11";
signal VPAddr0, VPDataOut0 : std_logic_vector(31 downto 0) := 32x"0";
signal VPAddr1, VPDataOut1 : std_logic_vector(31 downto 0) := 32x"0";
signal VPDataIn0, VPDataIn1 : std_logic_vector(31 downto 0) := 32x"0";
signal VPWE0, VPWE1 : std_logic;
signal VPRD0, VPRD1 : std_logic;
signal Update : std_logic_vector(1 downto 0);
signal notReset : std_logic;
signal ResetInt : std_logic := '0';
signal CS1 : std_logic;
signal Mem : array_t (0 to 1023)(31 downto 0) := (others => 32x"0");
begin
---------------------------------------------
-- Combinatorial logic
---------------------------------------------
notReset <= '1' when (Count > 5) else '0';
CS1 <= '1' when VPAddr1(31 downto 28) = 4x"a" else '0';
---------------------------------------------
-- VProc 0
---------------------------------------------
vp0 : entity work.VProc
port map (
Clk => Clk,
Addr => VPAddr0,
WE => VPWE0,
RD => VPRD0,
DataOut => VPDataOut0,
DataIn => VPDataIn0,
WRAck => VPWE0,
RDAck => VPRD0,
Interrupt => ResetInt & Interrupt0(1 downto 0),
Update => Update(0),
UpdateResponse => UpdateResponse(0),
Node => 4x"0"
);
---------------------------------------------
-- VProc 1
---------------------------------------------
vp1 : entity work.VProc
port map (
Clk => Clk,
Addr => VPAddr1,
WE => VPWE1,
RD => VPRD1,
DataOut => VPDataOut1,
DataIn => VPDataIn1,
WRAck => VPWE1,
RDAck => VPRD1,
Interrupt => Interrupt1,
Update => Update(1),
UpdateResponse => UpdateResponse(1),
Node => 4x"1"
);
---------------------------------------------
-- Response processes
---------------------------------------------
P_UPDT0 : process(Update(0))
begin
UpdateResponse(0) <= not UpdateResponse(0);
end process;
P_UPDT1 : process(Update(1))
begin
UpdateResponse(1) <= not UpdateResponse(1);
end process;
---------------------------------------------
-- Clock generation
---------------------------------------------
P_CLKGEN : process
begin
-- Generate a clock cycle
loop
Clk <= '1';
wait for ClkPeriod/2.0;
Clk <= '0';
wait for ClkPeriod/2.0;
end loop;
end process;
---------------------------------------------
-- Data generation
---------------------------------------------
P_GENDATA : process (Clk)
variable Seed1 : natural := 16#250864#;
variable Seed2 : natural := 16#468025#;
variable RandNumR : real;
variable RandNumI0 : natural;
variable RandNumI1 : natural;
begin
if Clk'event and Clk = '1' then
ResetInt <= notReset and not notReset_H;
if Count = StopCount then
stop(0);
end if;
notReset_H <= notReset;
Count <= Count + 1;
uniform(Seed1, Seed2, RandNumR);
RandNumI0 := natural(65536.0 * RandNumR);
uniform(Seed1, Seed2, RandNumR);
RandNumI1 := natural(65536.0 * RandNumR);
VPDataIn0 <= std_logic_vector(to_unsigned(RandNumI0, 16)) &
std_logic_vector(to_unsigned(RandNumI1, 16)) ;
uniform(Seed1, Seed2, RandNumR);
RandNumI0 := natural(16.0 * RandNumR);
if RandNumI0 = 0 then
Interrupt0 <= "001";
else
Interrupt0 <= "000";
end if;
uniform(Seed1, Seed2, RandNumR);
RandNumI0 := natural(16.0 * RandNumR);
if RandNumI0 = 0 then
Interrupt1 <= "001";
else
Interrupt1 <= "000";
end if;
end if;
end process;
---------------------------------------------
-- Memory model
---------------------------------------------
P_MEM : process (Clk, VPAddr1)
begin
-- Read memory
VPDataIn1 <= Mem(to_integer(unsigned(VPAddr1(9 downto 0))));
-- Write memory
if Clk'event and Clk = '1' then
if VPWE1 = '1' and CS1 = '1' then
Mem(to_integer(unsigned(VPAddr1(9 downto 0)))) <= VPDataOut1;
end if;
end if;
end process;
end sim;
|
gpl-3.0
|
8c41d4de010897cf3a47f39a282a7c89
| 0.396678 | 4.885623 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/7/projetos/projeto1/projeto_2.vhd
| 1 | 860 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity projeto_2 is
port (
entrada : in std_logic_vector (2 downto 0) := "000";
reset : in std_logic := '0';
enable : in std_logic := '1';
clk : in std_logic;
saida : out std_logic_vector (2 downto 0)
);
end projeto_2;
architecture Behavioral of projeto_2 is
signal auxEntrada : std_logic_vector (2 downto 0);
begin
process (clk, reset)
begin
if (reset = '1') then
auxEntrada <= "000";
elsif (rising_edge(clk)) then
if (enable = '1') then
if (entrada = "000") then
auxEntrada <= "010";
elsif (entrada = "010") then
auxEntrada <= "101";
elsif (entrada = "101") then
auxEntrada <= "110";
else
auxEntrada <= "000";
end if;
end if;
saida <= auxEntrada;
end if;
end process;
end Behavioral;
|
mit
|
691059efb9669d6216abad51376f5e53
| 0.601163 | 2.975779 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/audioDac/ipcore_dir/counter16.vhd
| 2 | 4,054 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file counter16.vhd when simulating
-- the core, counter16. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY counter16 IS
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END counter16;
ARCHITECTURE counter16_a OF counter16 IS
-- synthesis translate_off
COMPONENT wrapped_counter16
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_counter16 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 0,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 16,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_counter16
PORT MAP (
clk => clk,
q => q
);
-- synthesis translate_on
END counter16_a;
|
gpl-3.0
|
cc6f6fa5e5f96285a9a7896869a43080
| 0.536507 | 4.747073 | false | false | false | false |
Krabby127/ADC
|
accelb.vhd
| 1 | 8,336 |
-------------------------------------------------------
-- Design Name : accelb
-- File Name : accelb.vhd
-- Function : 2wire i/f for accelerometer
-- Author : J Rigg
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity accelb is
port (
reset :in std_logic;
clk :in std_logic;
clrb :in std_logic;
scl :out std_logic;
sdai :in std_logic;
sdao :out std_logic;
sda_oe :out std_logic;
bump :out std_logic;
st :out std_logic_vector (7 downto 0);
xd :out std_logic_vector (11 downto 0);
yd :out std_logic_vector (11 downto 0);
zd :out std_logic_vector (11 downto 0)
);
end entity;
architecture rtl of accelb is
signal datao :std_logic_vector (7 downto 0);
signal datai :std_logic_vector (7 downto 0);
signal amux :std_logic_vector (7 downto 0);
signal dmux :std_logic_vector (7 downto 0);
signal xdi :std_logic_vector (11 downto 0);
signal ydi :std_logic_vector (11 downto 0);
signal zdi :std_logic_vector (11 downto 0);
signal lastx :std_logic_vector (11 downto 0);
signal lasty :std_logic_vector (11 downto 0);
signal lastz :std_logic_vector (11 downto 0);
signal bx :std_logic_vector (12 downto 0);
signal by :std_logic_vector (12 downto 0);
signal bz :std_logic_vector (12 downto 0);
signal count :std_logic_vector (6 downto 0);
signal bit_cnt :std_logic_vector (6 downto 0);
signal init_cnt :std_logic_vector (2 downto 0);
signal state :std_logic_vector (3 downto 0);
signal upd_cnt :std_logic_vector (10 downto 0);
signal bumpi :std_logic;
signal bumpx :std_logic;
signal bumpy :std_logic;
signal bumpz :std_logic;
signal count_half:std_logic;
signal count_end :std_logic;
signal sdao_i :std_logic;
signal upd_i :std_logic;
begin
sdao<=sdao_i;
xd<=xdi;
yd<=ydi;
zd<=zdi;
bump<=bumpi;
count_proc: process (clk, reset)
begin
if reset = '1' then
count <= "0000000";
count_end<='0';
count_half<='0';
bit_cnt <= "0000000";
init_cnt <= "000";
sda_oe<='0';
elsif clk'event and clk='1' then
count <= count+'1';
if count="0111110" then
count_half<='1';
else
count_half<='0';
end if;
if count="1111110" then
count_end<='1';
else
count_end<='0';
end if;
if state="0101" and count_end='1' then
if init_cnt="110" then
init_cnt<="000";
else
init_cnt<=init_cnt+'1';
end if;
end if;
if state(1 downto 0)="01" then
bit_cnt<="0000000";
elsif state(1 downto 0)="11" and count_end='1' then
bit_cnt<=bit_cnt+'1';
end if;
if count_half='1' then
if state="1100" and bit_cnt="1011010" then
sdao_i<='1'; --NAK
elsif bit_cnt="1011010" then
sdao_i<=sdao_i; --NAK
elsif state(2 downto 0)="000" then
sdao_i<='1';
elsif state(2 downto 0)="101" then
sdao_i<='1';
elsif state="1100" and bit_cnt="0010010" then
sdao_i<='1';
elsif state="1011" and bit_cnt="0010010" then
sdao_i<='0';
elsif bit_cnt="0010010" then
sdao_i<=sdao_i;
else
sdao_i<=datao(7);
end if;
end if;
if count_half='1' then
if bit_cnt="0001000" or bit_cnt="0010001" or (state(3)='0' and bit_cnt="0011010") then
--(state(3)='1' and bit_cnt="011011") then
sda_oe<='0';
elsif state(3)='1' and bit_cnt>"0011010" and bit_cnt/="0100100" and bit_cnt/="0101101" and bit_cnt/="0110110" and bit_cnt/="0111111" and bit_cnt/="1001000" and bit_cnt/="1010001" and bit_cnt/="1011010" then
sda_oe<='0';
else
sda_oe<='1';
end if;
end if;
if state(2 downto 0)="010" or state(2 downto 0)="100" then
scl<='0';
else
scl<='1';
end if;
end if;
end process;
state_proc: process (clk, reset)
begin
if reset = '1' then
state <= (others=>'0');
elsif clk'event and clk='1' then
if count_end='1' then
if state(3 downto 2)= "00" then
state <= state+'1';
elsif state = "0100" then
if bit_cnt="0011011" then
state <= "0101";
else
state <= "0011";
end if;
elsif state = "0101" then
if init_cnt="110" then
state <= "1000";
else
state <= "0001";
end if;
elsif (state = "1000" and upd_i='1') or
(state(3 downto 2)="10" and state(1 downto 0)/="00") then
state <= state+'1';
elsif state = "1100" then
if bit_cnt="1011010" then
state <= "1101";
else
state <= "1011";
end if;
elsif state = "1101" then
state <= "1000";
end if;
end if;
end if;
end process;
mux_p:process(init_cnt)
begin
case init_cnt is
when "000" => amux<="00101010"; -- 2A
dmux<="00000100"; -- 04 low noise, disable
when "001" => amux<="00101101"; -- 2D
dmux<="00000100"; -- 04
when "010" => amux<="00101110"; -- 2e
dmux<="00000100"; -- 04
when "011" => amux<="00010111"; -- 17
dmux<="00010000"; -- 10
when "100" => amux<="00011000"; -- 18
dmux<="00000001"; -- 01
when "101" => amux<="00010101"; -- 15
dmux<="11111000"; -- f8
when "110" => amux<="00101010"; -- 2A
dmux<="00000101"; -- 05 enable
when others => amux<="00101010"; -- 2A
dmux<="00000100"; -- 04 disable
end case;
end process;
dio_proc: process
begin
wait until clk'event and clk='1';
if state="1011" and count_half='1' then
datai<=datai(6 downto 0) & sdai;
end if;
if state(2 downto 0)="001" then
datao<="00111000"; --chip address, write
elsif state="0100" and count_half='1' and bit_cnt="0001001" then
datao<=amux;
elsif state="0100" and count_half='1' and bit_cnt="0010010" then
datao<=dmux;
--elsif state="1100" and count_half='1' and bit_cnt="001001" then
elsif state="1100" and count_half='1' and bit_cnt="0010011" then
datao<="00111001"; -- chip address, read
elsif state(2 downto 0)="011" and count_half='1' then
datao<=datao(6 downto 0) & '0';
end if;
if reset='1' or clrb='1' then
upd_cnt <= (others=>'0');
elsif state="1000" and count_end='1' and upd_i='0' then
upd_cnt<=upd_cnt+'1';
end if;
if upd_cnt="11111111111" and count_end='1' then
upd_i <= '1';
elsif count_end='1' then
upd_i <= '0';
end if;
end process;
bx<=('0'&lastx)-('0'&xdi);
by<=('0'&lasty)-('0'&ydi);
bz<=('0'&lastz)-('0'&zdi);
bumpx<='1' when (bx(12)='0' and bx(11 downto 4)/="00000000") or (bx(12)='1' and bx(11 downto 4)/="11111111") else '0';
bumpy<='1' when (by(12)='0' and by(11 downto 4)/="00000000") or (by(12)='1' and by(11 downto 4)/="11111111") else '0';
bumpz<='1' when (bz(12)='0' and bz(11 downto 4)/="00000000") or (bz(12)='1' and bz(11 downto 4)/="11111111") else '0';
reg_proc: process
begin
wait until clk'event and clk='1';
if state="1011" and bit_cnt="0100011" and count_end='1' then
st <= datai;
end if;
if state="1011" and bit_cnt="0101100" and count_end='1' then
xdi(11 downto 4) <= datai;
lastx<=xdi;
end if;
if state="1011" and bit_cnt="0110101" and count_end='1' then
xdi(3 downto 0) <= datai(7 downto 4);
end if;
if state="1011" and bit_cnt="0111110" and count_end='1' then
ydi(11 downto 4) <= datai;
lasty<=ydi;
end if;
if state="1011" and bit_cnt="1000111" and count_end='1' then
ydi(3 downto 0) <= datai(7 downto 4);
end if;
if state="1011" and bit_cnt="1010000" and count_end='1' then
zdi(11 downto 4) <= datai;
lastz<=zdi;
end if;
if state="1011" and bit_cnt="1011001" and count_end='1' then
zdi(3 downto 0) <= datai(7 downto 4);
end if;
if reset='1' or clrb='1' then
bumpi<='0';
elsif state="1100" and bit_cnt="1011010" then
bumpi<= bumpx or bumpy or bumpz or bumpi;
end if;
end process;
end architecture;
|
apache-2.0
|
64d7a974a6aacd1fa312ba0710a02753
| 0.545825 | 3.315831 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/flashyLights/ipcore_dir/memmory/simulation/memmory_synth.vhd
| 1 | 6,819 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: memmory_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY memmory_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE memmory_synth_ARCH OF memmory_synth IS
COMPONENT memmory_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: memmory_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
gpl-3.0
|
d8e119d91b05b58a5ad35cd626ca1625
| 0.58029 | 3.818029 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/clock24h_bcd.vhd
| 2 | 2,276 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:36:47 02/19/2016
-- Design Name:
-- Module Name: clock24h_bcd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock24h_bcd is
Port ( clk_1ms : in STD_LOGIC;
hour_bcd : out STD_LOGIC_VECTOR (7 downto 0);
minute_bcd : out STD_LOGIC_VECTOR (7 downto 0);
clk_1s : out STD_LOGIC);
end clock24h_bcd;
architecture Behavioral of clock24h_bcd is
signal half_Sec : STD_LOGIC := '0';
signal mili : STD_LOGIC_VECTOR (8 downto 0) := (others =>'0');
signal sec : STD_LOGIC_VECTOR (5 downto 0) := (others =>'0');
signal min_uni : STD_LOGIC_VECTOR (3 downto 0) := (others =>'0');
signal min_dec : STD_LOGIC_VECTOR (3 downto 0) := (others =>'0');
signal hour_uni : STD_LOGIC_VECTOR (3 downto 0) := (others =>'0');
signal hour_dec : STD_LOGIC_VECTOR (3 downto 0) := (others =>'0');
begin
clk_1s <= half_sec;
minute_bcd <= min_dec & min_uni;
hour_bcd <= hour_dec & hour_uni;
mili_process: process(clk_1ms) begin
if rising_edge(clk_1ms) then
if mili = 500-1 then
mili <= (others =>'0');
half_sec <= not half_sec;
else
mili <= mili +1;
end if;
end if;
end process;
sec_process: process(half_sec) begin
if rising_edge(half_sec) then
if sec = 59 then
sec <= (others =>'0');
if min_uni = 9 then
min_uni <= (others =>'0');
if min_dec = 5 then
min_dec <= (others =>'0');
if hour_uni = 9 OR (hour_dec = 2 AND hour_uni = 3) then
hour_uni <= (others =>'0');
if hour_dec = 2 then
hour_dec <= (others =>'0');
else
hour_dec <= hour_dec +1;
end if;
else
hour_uni <= hour_uni +1;
end if;
else
min_dec <= min_dec +1;
end if;
else
min_uni <= min_uni +1;
end if;
else
sec <= sec +1;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
a48c55bd93bf3c545fe5b34259c71be1
| 0.529877 | 3.038718 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/plasoc_interconnect_crossbar_wrap.vhd
| 1 | 64,649 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.plasoc_crossbar_pack.plasoc_crossbar;
use work.plasoc_interconnect_crossbar_wrap_pack.all;
entity plasoc_interconnect_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 7;
axi_slave_amount : integer := 3;
axi_master_base_address : std_logic_vector := X"20000000200400002003000020020000200100001000000000000000";
axi_master_high_address : std_logic_vector := X"2000ffff2004ffff2003ffff2002ffff2001ffff1fffffff0000ffff"
);
port
(
cpu_0_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_0_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_0_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_0_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_0_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_0_s_axi_awlock : in std_logic;
cpu_0_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_0_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_0_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_0_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_0_s_axi_awvalid : in std_logic;
cpu_0_s_axi_awready : out std_logic;
cpu_0_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_0_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_0_s_axi_wlast : in std_logic;
cpu_0_s_axi_wvalid : in std_logic;
cpu_0_s_axi_wready : out std_logic;
cpu_0_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_0_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_0_s_axi_bvalid : out std_logic;
cpu_0_s_axi_bready : in std_logic;
cpu_0_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_0_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_0_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_0_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_0_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_0_s_axi_arlock : in std_logic;
cpu_0_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_0_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_0_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_0_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_0_s_axi_arvalid : in std_logic;
cpu_0_s_axi_arready : out std_logic;
cpu_0_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_0_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_0_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_0_s_axi_rlast : out std_logic;
cpu_0_s_axi_rvalid : out std_logic;
cpu_0_s_axi_rready : in std_logic;
cpu_1_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_1_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_1_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_1_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_1_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_1_s_axi_awlock : in std_logic;
cpu_1_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_1_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_1_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_1_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_1_s_axi_awvalid : in std_logic;
cpu_1_s_axi_awready : out std_logic;
cpu_1_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_1_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_1_s_axi_wlast : in std_logic;
cpu_1_s_axi_wvalid : in std_logic;
cpu_1_s_axi_wready : out std_logic;
cpu_1_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_1_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_1_s_axi_bvalid : out std_logic;
cpu_1_s_axi_bready : in std_logic;
cpu_1_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_1_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_1_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_1_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_1_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_1_s_axi_arlock : in std_logic;
cpu_1_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_1_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_1_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_1_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_1_s_axi_arvalid : in std_logic;
cpu_1_s_axi_arready : out std_logic;
cpu_1_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_1_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_1_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_1_s_axi_rlast : out std_logic;
cpu_1_s_axi_rvalid : out std_logic;
cpu_1_s_axi_rready : in std_logic;
cpu_2_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_2_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_2_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_2_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_2_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_2_s_axi_awlock : in std_logic;
cpu_2_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_2_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_2_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_2_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_2_s_axi_awvalid : in std_logic;
cpu_2_s_axi_awready : out std_logic;
cpu_2_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_2_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_2_s_axi_wlast : in std_logic;
cpu_2_s_axi_wvalid : in std_logic;
cpu_2_s_axi_wready : out std_logic;
cpu_2_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_2_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_2_s_axi_bvalid : out std_logic;
cpu_2_s_axi_bready : in std_logic;
cpu_2_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_2_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_2_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_2_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_2_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_2_s_axi_arlock : in std_logic;
cpu_2_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_2_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_2_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_2_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_2_s_axi_arvalid : in std_logic;
cpu_2_s_axi_arready : out std_logic;
cpu_2_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_2_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_2_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_2_s_axi_rlast : out std_logic;
cpu_2_s_axi_rvalid : out std_logic;
cpu_2_s_axi_rready : in std_logic;
boot_bram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
boot_bram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
boot_bram_m_axi_awlen : out std_logic_vector(7 downto 0);
boot_bram_m_axi_awsize : out std_logic_vector(2 downto 0);
boot_bram_m_axi_awburst : out std_logic_vector(1 downto 0);
boot_bram_m_axi_awlock : out std_logic;
boot_bram_m_axi_awcache : out std_logic_vector(3 downto 0);
boot_bram_m_axi_awprot : out std_logic_vector(2 downto 0);
boot_bram_m_axi_awqos : out std_logic_vector(3 downto 0);
boot_bram_m_axi_awregion : out std_logic_vector(3 downto 0);
boot_bram_m_axi_awvalid : out std_logic;
boot_bram_m_axi_awready : in std_logic;
boot_bram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
boot_bram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
boot_bram_m_axi_wlast : out std_logic;
boot_bram_m_axi_wvalid : out std_logic;
boot_bram_m_axi_wready : in std_logic;
boot_bram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
boot_bram_m_axi_bresp : in std_logic_vector(1 downto 0);
boot_bram_m_axi_bvalid : in std_logic;
boot_bram_m_axi_bready : out std_logic;
boot_bram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
boot_bram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
boot_bram_m_axi_arlen : out std_logic_vector(7 downto 0);
boot_bram_m_axi_arsize : out std_logic_vector(2 downto 0);
boot_bram_m_axi_arburst : out std_logic_vector(1 downto 0);
boot_bram_m_axi_arlock : out std_logic;
boot_bram_m_axi_arcache : out std_logic_vector(3 downto 0);
boot_bram_m_axi_arprot : out std_logic_vector(2 downto 0);
boot_bram_m_axi_arqos : out std_logic_vector(3 downto 0);
boot_bram_m_axi_arregion : out std_logic_vector(3 downto 0);
boot_bram_m_axi_arvalid : out std_logic;
boot_bram_m_axi_arready : in std_logic;
boot_bram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
boot_bram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
boot_bram_m_axi_rresp : in std_logic_vector(1 downto 0);
boot_bram_m_axi_rlast : in std_logic;
boot_bram_m_axi_rvalid : in std_logic;
boot_bram_m_axi_rready : out std_logic;
ram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_awlen : out std_logic_vector(7 downto 0);
ram_m_axi_awsize : out std_logic_vector(2 downto 0);
ram_m_axi_awburst : out std_logic_vector(1 downto 0);
ram_m_axi_awlock : out std_logic;
ram_m_axi_awcache : out std_logic_vector(3 downto 0);
ram_m_axi_awprot : out std_logic_vector(2 downto 0);
ram_m_axi_awqos : out std_logic_vector(3 downto 0);
ram_m_axi_awregion : out std_logic_vector(3 downto 0);
ram_m_axi_awvalid : out std_logic;
ram_m_axi_awready : in std_logic;
ram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ram_m_axi_wlast : out std_logic;
ram_m_axi_wvalid : out std_logic;
ram_m_axi_wready : in std_logic;
ram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_bresp : in std_logic_vector(1 downto 0);
ram_m_axi_bvalid : in std_logic;
ram_m_axi_bready : out std_logic;
ram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_arlen : out std_logic_vector(7 downto 0);
ram_m_axi_arsize : out std_logic_vector(2 downto 0);
ram_m_axi_arburst : out std_logic_vector(1 downto 0);
ram_m_axi_arlock : out std_logic;
ram_m_axi_arcache : out std_logic_vector(3 downto 0);
ram_m_axi_arprot : out std_logic_vector(2 downto 0);
ram_m_axi_arqos : out std_logic_vector(3 downto 0);
ram_m_axi_arregion : out std_logic_vector(3 downto 0);
ram_m_axi_arvalid : out std_logic;
ram_m_axi_arready : in std_logic;
ram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_rresp : in std_logic_vector(1 downto 0);
ram_m_axi_rlast : in std_logic;
ram_m_axi_rvalid : in std_logic;
ram_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
gpio_m_axi_awlock : out std_logic;
gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
gpio_m_axi_awvalid : out std_logic;
gpio_m_axi_awready : in std_logic;
gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
gpio_m_axi_wlast : out std_logic;
gpio_m_axi_wvalid : out std_logic;
gpio_m_axi_wready : in std_logic;
gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
gpio_m_axi_bvalid : in std_logic;
gpio_m_axi_bready : out std_logic;
gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
gpio_m_axi_arlock : out std_logic;
gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
gpio_m_axi_arvalid : out std_logic;
gpio_m_axi_arready : in std_logic;
gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
gpio_m_axi_rlast : in std_logic;
gpio_m_axi_rvalid : in std_logic;
gpio_m_axi_rready : out std_logic;
uart_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_awlen : out std_logic_vector(7 downto 0);
uart_m_axi_awsize : out std_logic_vector(2 downto 0);
uart_m_axi_awburst : out std_logic_vector(1 downto 0);
uart_m_axi_awlock : out std_logic;
uart_m_axi_awcache : out std_logic_vector(3 downto 0);
uart_m_axi_awprot : out std_logic_vector(2 downto 0);
uart_m_axi_awqos : out std_logic_vector(3 downto 0);
uart_m_axi_awregion : out std_logic_vector(3 downto 0);
uart_m_axi_awvalid : out std_logic;
uart_m_axi_awready : in std_logic;
uart_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
uart_m_axi_wlast : out std_logic;
uart_m_axi_wvalid : out std_logic;
uart_m_axi_wready : in std_logic;
uart_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_bresp : in std_logic_vector(1 downto 0);
uart_m_axi_bvalid : in std_logic;
uart_m_axi_bready : out std_logic;
uart_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_arlen : out std_logic_vector(7 downto 0);
uart_m_axi_arsize : out std_logic_vector(2 downto 0);
uart_m_axi_arburst : out std_logic_vector(1 downto 0);
uart_m_axi_arlock : out std_logic;
uart_m_axi_arcache : out std_logic_vector(3 downto 0);
uart_m_axi_arprot : out std_logic_vector(2 downto 0);
uart_m_axi_arqos : out std_logic_vector(3 downto 0);
uart_m_axi_arregion : out std_logic_vector(3 downto 0);
uart_m_axi_arvalid : out std_logic;
uart_m_axi_arready : in std_logic;
uart_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_rresp : in std_logic_vector(1 downto 0);
uart_m_axi_rlast : in std_logic;
uart_m_axi_rvalid : in std_logic;
uart_m_axi_rready : out std_logic;
lock_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
lock_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
lock_m_axi_awlen : out std_logic_vector(7 downto 0);
lock_m_axi_awsize : out std_logic_vector(2 downto 0);
lock_m_axi_awburst : out std_logic_vector(1 downto 0);
lock_m_axi_awlock : out std_logic;
lock_m_axi_awcache : out std_logic_vector(3 downto 0);
lock_m_axi_awprot : out std_logic_vector(2 downto 0);
lock_m_axi_awqos : out std_logic_vector(3 downto 0);
lock_m_axi_awregion : out std_logic_vector(3 downto 0);
lock_m_axi_awvalid : out std_logic;
lock_m_axi_awready : in std_logic;
lock_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
lock_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
lock_m_axi_wlast : out std_logic;
lock_m_axi_wvalid : out std_logic;
lock_m_axi_wready : in std_logic;
lock_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
lock_m_axi_bresp : in std_logic_vector(1 downto 0);
lock_m_axi_bvalid : in std_logic;
lock_m_axi_bready : out std_logic;
lock_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
lock_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
lock_m_axi_arlen : out std_logic_vector(7 downto 0);
lock_m_axi_arsize : out std_logic_vector(2 downto 0);
lock_m_axi_arburst : out std_logic_vector(1 downto 0);
lock_m_axi_arlock : out std_logic;
lock_m_axi_arcache : out std_logic_vector(3 downto 0);
lock_m_axi_arprot : out std_logic_vector(2 downto 0);
lock_m_axi_arqos : out std_logic_vector(3 downto 0);
lock_m_axi_arregion : out std_logic_vector(3 downto 0);
lock_m_axi_arvalid : out std_logic;
lock_m_axi_arready : in std_logic;
lock_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
lock_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
lock_m_axi_rresp : in std_logic_vector(1 downto 0);
lock_m_axi_rlast : in std_logic;
lock_m_axi_rvalid : in std_logic;
lock_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end plasoc_interconnect_crossbar_wrap;
architecture Behavioral of plasoc_interconnect_crossbar_wrap is
constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width;
signal s_axi_awid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_awaddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_awlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_awsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_awlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_wstrb : std_logic_vector(axi_slave_amount*axi_data_width/8-1 downto 0);
signal s_axi_wlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_bresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_bvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_araddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_arlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_arsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_arlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_rdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_rresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_rlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal m_axi_awid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_awaddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_awlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_awsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_awlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_wstrb : std_logic_vector(axi_master_amount*axi_data_width/8-1 downto 0);
signal m_axi_wlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_bresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_bvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_araddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_arlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_arsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_arlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_rdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_rresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_rlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal s_address_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_response_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_address_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal m_address_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_response_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_address_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
begin
s_axi_awid <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_awid & cpu_1_s_axi_awid & cpu_0_s_axi_awid;
s_axi_awaddr <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_awaddr & cpu_1_s_axi_awaddr & cpu_0_s_axi_awaddr;
s_axi_awlen <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_awlen & cpu_1_s_axi_awlen & cpu_0_s_axi_awlen;
s_axi_awsize <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_awsize & cpu_1_s_axi_awsize & cpu_0_s_axi_awsize;
s_axi_awburst <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_awburst & cpu_1_s_axi_awburst & cpu_0_s_axi_awburst;
s_axi_awlock <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_awlock & cpu_1_s_axi_awlock & cpu_0_s_axi_awlock;
s_axi_awcache <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_awcache & cpu_1_s_axi_awcache & cpu_0_s_axi_awcache;
s_axi_awprot <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_awprot & cpu_1_s_axi_awprot & cpu_0_s_axi_awprot;
s_axi_awqos <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_awqos & cpu_1_s_axi_awqos & cpu_0_s_axi_awqos;
s_axi_awregion <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_awregion & cpu_1_s_axi_awregion & cpu_0_s_axi_awregion;
s_axi_awvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_awvalid & cpu_1_s_axi_awvalid & cpu_0_s_axi_awvalid;
s_axi_wdata <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_wdata & cpu_1_s_axi_wdata & cpu_0_s_axi_wdata;
s_axi_wstrb <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_wstrb & cpu_1_s_axi_wstrb & cpu_0_s_axi_wstrb;
s_axi_wlast <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_wlast & cpu_1_s_axi_wlast & cpu_0_s_axi_wlast;
s_axi_wvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_wvalid & cpu_1_s_axi_wvalid & cpu_0_s_axi_wvalid;
s_axi_bready <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_bready & cpu_1_s_axi_bready & cpu_0_s_axi_bready;
s_axi_arid <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_arid & cpu_1_s_axi_arid & cpu_0_s_axi_arid;
s_axi_araddr <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_araddr & cpu_1_s_axi_araddr & cpu_0_s_axi_araddr;
s_axi_arlen <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_arlen & cpu_1_s_axi_arlen & cpu_0_s_axi_arlen;
s_axi_arsize <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_arsize & cpu_1_s_axi_arsize & cpu_0_s_axi_arsize;
s_axi_arburst <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_arburst & cpu_1_s_axi_arburst & cpu_0_s_axi_arburst;
s_axi_arlock <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_arlock & cpu_1_s_axi_arlock & cpu_0_s_axi_arlock;
s_axi_arcache <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_arcache & cpu_1_s_axi_arcache & cpu_0_s_axi_arcache;
s_axi_arprot <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_arprot & cpu_1_s_axi_arprot & cpu_0_s_axi_arprot;
s_axi_arqos <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_arqos & cpu_1_s_axi_arqos & cpu_0_s_axi_arqos;
s_axi_arregion <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_arregion & cpu_1_s_axi_arregion & cpu_0_s_axi_arregion;
s_axi_arvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_arvalid & cpu_1_s_axi_arvalid & cpu_0_s_axi_arvalid;
s_axi_rready <= std_logic_vector(to_unsigned(0,0)) & cpu_2_s_axi_rready & cpu_1_s_axi_rready & cpu_0_s_axi_rready;
m_axi_awready <= std_logic_vector(to_unsigned(0,0)) & lock_m_axi_awready & uart_m_axi_awready & gpio_m_axi_awready & timer_m_axi_awready & int_m_axi_awready & ram_m_axi_awready & boot_bram_m_axi_awready;
m_axi_wready <= std_logic_vector(to_unsigned(0,0)) & lock_m_axi_wready & uart_m_axi_wready & gpio_m_axi_wready & timer_m_axi_wready & int_m_axi_wready & ram_m_axi_wready & boot_bram_m_axi_wready;
m_axi_bid <= std_logic_vector(to_unsigned(0,0)) & lock_m_axi_bid & uart_m_axi_bid & gpio_m_axi_bid & timer_m_axi_bid & int_m_axi_bid & ram_m_axi_bid & boot_bram_m_axi_bid;
m_axi_bresp <= std_logic_vector(to_unsigned(0,0)) & lock_m_axi_bresp & uart_m_axi_bresp & gpio_m_axi_bresp & timer_m_axi_bresp & int_m_axi_bresp & ram_m_axi_bresp & boot_bram_m_axi_bresp;
m_axi_bvalid <= std_logic_vector(to_unsigned(0,0)) & lock_m_axi_bvalid & uart_m_axi_bvalid & gpio_m_axi_bvalid & timer_m_axi_bvalid & int_m_axi_bvalid & ram_m_axi_bvalid & boot_bram_m_axi_bvalid;
m_axi_arready <= std_logic_vector(to_unsigned(0,0)) & lock_m_axi_arready & uart_m_axi_arready & gpio_m_axi_arready & timer_m_axi_arready & int_m_axi_arready & ram_m_axi_arready & boot_bram_m_axi_arready;
m_axi_rid <= std_logic_vector(to_unsigned(0,0)) & lock_m_axi_rid & uart_m_axi_rid & gpio_m_axi_rid & timer_m_axi_rid & int_m_axi_rid & ram_m_axi_rid & boot_bram_m_axi_rid;
m_axi_rdata <= std_logic_vector(to_unsigned(0,0)) & lock_m_axi_rdata & uart_m_axi_rdata & gpio_m_axi_rdata & timer_m_axi_rdata & int_m_axi_rdata & ram_m_axi_rdata & boot_bram_m_axi_rdata;
m_axi_rresp <= std_logic_vector(to_unsigned(0,0)) & lock_m_axi_rresp & uart_m_axi_rresp & gpio_m_axi_rresp & timer_m_axi_rresp & int_m_axi_rresp & ram_m_axi_rresp & boot_bram_m_axi_rresp;
m_axi_rlast <= std_logic_vector(to_unsigned(0,0)) & lock_m_axi_rlast & uart_m_axi_rlast & gpio_m_axi_rlast & timer_m_axi_rlast & int_m_axi_rlast & ram_m_axi_rlast & boot_bram_m_axi_rlast;
m_axi_rvalid <= std_logic_vector(to_unsigned(0,0)) & lock_m_axi_rvalid & uart_m_axi_rvalid & gpio_m_axi_rvalid & timer_m_axi_rvalid & int_m_axi_rvalid & ram_m_axi_rvalid & boot_bram_m_axi_rvalid;
cpu_0_s_axi_awready <= '0' when s_address_write_connected(0)='0' else s_axi_awready(0);
cpu_1_s_axi_awready <= '0' when s_address_write_connected(1)='0' else s_axi_awready(1);
cpu_2_s_axi_awready <= '0' when s_address_write_connected(2)='0' else s_axi_awready(2);
cpu_0_s_axi_wready <= '0' when s_data_write_connected(0)='0' else s_axi_wready(0);
cpu_1_s_axi_wready <= '0' when s_data_write_connected(1)='0' else s_axi_wready(1);
cpu_2_s_axi_wready <= '0' when s_data_write_connected(2)='0' else s_axi_wready(2);
cpu_0_s_axi_bid <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cpu_1_s_axi_bid <= (others=>'0') when s_response_write_connected(1)='0' else s_axi_bid((1+1)*axi_slave_id_width-1 downto 1*axi_slave_id_width);
cpu_2_s_axi_bid <= (others=>'0') when s_response_write_connected(2)='0' else s_axi_bid((1+2)*axi_slave_id_width-1 downto 2*axi_slave_id_width);
cpu_0_s_axi_bresp <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bresp((1+0)*2-1 downto 0*2);
cpu_1_s_axi_bresp <= (others=>'0') when s_response_write_connected(1)='0' else s_axi_bresp((1+1)*2-1 downto 1*2);
cpu_2_s_axi_bresp <= (others=>'0') when s_response_write_connected(2)='0' else s_axi_bresp((1+2)*2-1 downto 2*2);
cpu_0_s_axi_bvalid <= '0' when s_response_write_connected(0)='0' else s_axi_bvalid(0);
cpu_1_s_axi_bvalid <= '0' when s_response_write_connected(1)='0' else s_axi_bvalid(1);
cpu_2_s_axi_bvalid <= '0' when s_response_write_connected(2)='0' else s_axi_bvalid(2);
cpu_0_s_axi_arready <= '0' when s_address_read_connected(0)='0' else s_axi_arready(0);
cpu_1_s_axi_arready <= '0' when s_address_read_connected(1)='0' else s_axi_arready(1);
cpu_2_s_axi_arready <= '0' when s_address_read_connected(2)='0' else s_axi_arready(2);
cpu_0_s_axi_rid <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cpu_1_s_axi_rid <= (others=>'0') when s_data_read_connected(1)='0' else s_axi_rid((1+1)*axi_slave_id_width-1 downto 1*axi_slave_id_width);
cpu_2_s_axi_rid <= (others=>'0') when s_data_read_connected(2)='0' else s_axi_rid((1+2)*axi_slave_id_width-1 downto 2*axi_slave_id_width);
cpu_0_s_axi_rdata <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
cpu_1_s_axi_rdata <= (others=>'0') when s_data_read_connected(1)='0' else s_axi_rdata((1+1)*axi_data_width-1 downto 1*axi_data_width);
cpu_2_s_axi_rdata <= (others=>'0') when s_data_read_connected(2)='0' else s_axi_rdata((1+2)*axi_data_width-1 downto 2*axi_data_width);
cpu_0_s_axi_rresp <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rresp((1+0)*2-1 downto 0*2);
cpu_1_s_axi_rresp <= (others=>'0') when s_data_read_connected(1)='0' else s_axi_rresp((1+1)*2-1 downto 1*2);
cpu_2_s_axi_rresp <= (others=>'0') when s_data_read_connected(2)='0' else s_axi_rresp((1+2)*2-1 downto 2*2);
cpu_0_s_axi_rlast <= '0' when s_data_read_connected(0)='0' else s_axi_rlast(0);
cpu_1_s_axi_rlast <= '0' when s_data_read_connected(1)='0' else s_axi_rlast(1);
cpu_2_s_axi_rlast <= '0' when s_data_read_connected(2)='0' else s_axi_rlast(2);
cpu_0_s_axi_rvalid <= '0' when s_data_read_connected(0)='0' else s_axi_rvalid(0);
cpu_1_s_axi_rvalid <= '0' when s_data_read_connected(1)='0' else s_axi_rvalid(1);
cpu_2_s_axi_rvalid <= '0' when s_data_read_connected(2)='0' else s_axi_rvalid(2);
boot_bram_m_axi_awid <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
ram_m_axi_awid <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_awid <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
timer_m_axi_awid <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
gpio_m_axi_awid <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
uart_m_axi_awid <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awid((1+5)*axi_master_id_width-1 downto 5*axi_master_id_width);
lock_m_axi_awid <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awid((1+6)*axi_master_id_width-1 downto 6*axi_master_id_width);
boot_bram_m_axi_awaddr <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awaddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
ram_m_axi_awaddr <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awaddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_awaddr <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awaddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
timer_m_axi_awaddr <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awaddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
gpio_m_axi_awaddr <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awaddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
uart_m_axi_awaddr <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awaddr((1+5)*axi_address_width-1 downto 5*axi_address_width);
lock_m_axi_awaddr <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awaddr((1+6)*axi_address_width-1 downto 6*axi_address_width);
boot_bram_m_axi_awlen <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awlen((1+0)*8-1 downto 0*8);
ram_m_axi_awlen <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awlen((1+1)*8-1 downto 1*8);
int_m_axi_awlen <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awlen((1+2)*8-1 downto 2*8);
timer_m_axi_awlen <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awlen((1+3)*8-1 downto 3*8);
gpio_m_axi_awlen <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awlen((1+4)*8-1 downto 4*8);
uart_m_axi_awlen <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awlen((1+5)*8-1 downto 5*8);
lock_m_axi_awlen <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awlen((1+6)*8-1 downto 6*8);
boot_bram_m_axi_awsize <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awsize((1+0)*3-1 downto 0*3);
ram_m_axi_awsize <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awsize((1+1)*3-1 downto 1*3);
int_m_axi_awsize <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awsize((1+2)*3-1 downto 2*3);
timer_m_axi_awsize <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awsize((1+3)*3-1 downto 3*3);
gpio_m_axi_awsize <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awsize((1+4)*3-1 downto 4*3);
uart_m_axi_awsize <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awsize((1+5)*3-1 downto 5*3);
lock_m_axi_awsize <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awsize((1+6)*3-1 downto 6*3);
boot_bram_m_axi_awburst <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awburst((1+0)*2-1 downto 0*2);
ram_m_axi_awburst <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awburst((1+1)*2-1 downto 1*2);
int_m_axi_awburst <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awburst((1+2)*2-1 downto 2*2);
timer_m_axi_awburst <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awburst((1+3)*2-1 downto 3*2);
gpio_m_axi_awburst <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awburst((1+4)*2-1 downto 4*2);
uart_m_axi_awburst <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awburst((1+5)*2-1 downto 5*2);
lock_m_axi_awburst <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awburst((1+6)*2-1 downto 6*2);
boot_bram_m_axi_awlock <= '0' when m_address_write_connected(0)='0' else m_axi_awlock(0);
ram_m_axi_awlock <= '0' when m_address_write_connected(1)='0' else m_axi_awlock(1);
int_m_axi_awlock <= '0' when m_address_write_connected(2)='0' else m_axi_awlock(2);
timer_m_axi_awlock <= '0' when m_address_write_connected(3)='0' else m_axi_awlock(3);
gpio_m_axi_awlock <= '0' when m_address_write_connected(4)='0' else m_axi_awlock(4);
uart_m_axi_awlock <= '0' when m_address_write_connected(5)='0' else m_axi_awlock(5);
lock_m_axi_awlock <= '0' when m_address_write_connected(6)='0' else m_axi_awlock(6);
boot_bram_m_axi_awcache <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awcache((1+0)*4-1 downto 0*4);
ram_m_axi_awcache <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awcache((1+1)*4-1 downto 1*4);
int_m_axi_awcache <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awcache((1+2)*4-1 downto 2*4);
timer_m_axi_awcache <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awcache((1+3)*4-1 downto 3*4);
gpio_m_axi_awcache <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awcache((1+4)*4-1 downto 4*4);
uart_m_axi_awcache <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awcache((1+5)*4-1 downto 5*4);
lock_m_axi_awcache <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awcache((1+6)*4-1 downto 6*4);
boot_bram_m_axi_awprot <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awprot((1+0)*3-1 downto 0*3);
ram_m_axi_awprot <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awprot((1+1)*3-1 downto 1*3);
int_m_axi_awprot <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awprot((1+2)*3-1 downto 2*3);
timer_m_axi_awprot <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awprot((1+3)*3-1 downto 3*3);
gpio_m_axi_awprot <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awprot((1+4)*3-1 downto 4*3);
uart_m_axi_awprot <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awprot((1+5)*3-1 downto 5*3);
lock_m_axi_awprot <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awprot((1+6)*3-1 downto 6*3);
boot_bram_m_axi_awqos <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awqos((1+0)*4-1 downto 0*4);
ram_m_axi_awqos <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awqos((1+1)*4-1 downto 1*4);
int_m_axi_awqos <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awqos((1+2)*4-1 downto 2*4);
timer_m_axi_awqos <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awqos((1+3)*4-1 downto 3*4);
gpio_m_axi_awqos <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awqos((1+4)*4-1 downto 4*4);
uart_m_axi_awqos <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awqos((1+5)*4-1 downto 5*4);
lock_m_axi_awqos <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awqos((1+6)*4-1 downto 6*4);
boot_bram_m_axi_awregion <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awregion((1+0)*4-1 downto 0*4);
ram_m_axi_awregion <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awregion((1+1)*4-1 downto 1*4);
int_m_axi_awregion <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awregion((1+2)*4-1 downto 2*4);
timer_m_axi_awregion <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awregion((1+3)*4-1 downto 3*4);
gpio_m_axi_awregion <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awregion((1+4)*4-1 downto 4*4);
uart_m_axi_awregion <= (others=>'0') when m_address_write_connected(5)='0' else m_axi_awregion((1+5)*4-1 downto 5*4);
lock_m_axi_awregion <= (others=>'0') when m_address_write_connected(6)='0' else m_axi_awregion((1+6)*4-1 downto 6*4);
boot_bram_m_axi_awvalid <= '0' when m_address_write_connected(0)='0' else m_axi_awvalid(0);
ram_m_axi_awvalid <= '0' when m_address_write_connected(1)='0' else m_axi_awvalid(1);
int_m_axi_awvalid <= '0' when m_address_write_connected(2)='0' else m_axi_awvalid(2);
timer_m_axi_awvalid <= '0' when m_address_write_connected(3)='0' else m_axi_awvalid(3);
gpio_m_axi_awvalid <= '0' when m_address_write_connected(4)='0' else m_axi_awvalid(4);
uart_m_axi_awvalid <= '0' when m_address_write_connected(5)='0' else m_axi_awvalid(5);
lock_m_axi_awvalid <= '0' when m_address_write_connected(6)='0' else m_axi_awvalid(6);
boot_bram_m_axi_wdata <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
ram_m_axi_wdata <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wdata((1+1)*axi_data_width-1 downto 1*axi_data_width);
int_m_axi_wdata <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wdata((1+2)*axi_data_width-1 downto 2*axi_data_width);
timer_m_axi_wdata <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wdata((1+3)*axi_data_width-1 downto 3*axi_data_width);
gpio_m_axi_wdata <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wdata((1+4)*axi_data_width-1 downto 4*axi_data_width);
uart_m_axi_wdata <= (others=>'0') when m_data_write_connected(5)='0' else m_axi_wdata((1+5)*axi_data_width-1 downto 5*axi_data_width);
lock_m_axi_wdata <= (others=>'0') when m_data_write_connected(6)='0' else m_axi_wdata((1+6)*axi_data_width-1 downto 6*axi_data_width);
boot_bram_m_axi_wstrb <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wstrb((1+0)*axi_data_width/8-1 downto 0*axi_data_width/8);
ram_m_axi_wstrb <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wstrb((1+1)*axi_data_width/8-1 downto 1*axi_data_width/8);
int_m_axi_wstrb <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wstrb((1+2)*axi_data_width/8-1 downto 2*axi_data_width/8);
timer_m_axi_wstrb <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wstrb((1+3)*axi_data_width/8-1 downto 3*axi_data_width/8);
gpio_m_axi_wstrb <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wstrb((1+4)*axi_data_width/8-1 downto 4*axi_data_width/8);
uart_m_axi_wstrb <= (others=>'0') when m_data_write_connected(5)='0' else m_axi_wstrb((1+5)*axi_data_width/8-1 downto 5*axi_data_width/8);
lock_m_axi_wstrb <= (others=>'0') when m_data_write_connected(6)='0' else m_axi_wstrb((1+6)*axi_data_width/8-1 downto 6*axi_data_width/8);
boot_bram_m_axi_wlast <= '0' when m_data_write_connected(0)='0' else m_axi_wlast(0);
ram_m_axi_wlast <= '0' when m_data_write_connected(1)='0' else m_axi_wlast(1);
int_m_axi_wlast <= '0' when m_data_write_connected(2)='0' else m_axi_wlast(2);
timer_m_axi_wlast <= '0' when m_data_write_connected(3)='0' else m_axi_wlast(3);
gpio_m_axi_wlast <= '0' when m_data_write_connected(4)='0' else m_axi_wlast(4);
uart_m_axi_wlast <= '0' when m_data_write_connected(5)='0' else m_axi_wlast(5);
lock_m_axi_wlast <= '0' when m_data_write_connected(6)='0' else m_axi_wlast(6);
boot_bram_m_axi_wvalid <= '0' when m_data_write_connected(0)='0' else m_axi_wvalid(0);
ram_m_axi_wvalid <= '0' when m_data_write_connected(1)='0' else m_axi_wvalid(1);
int_m_axi_wvalid <= '0' when m_data_write_connected(2)='0' else m_axi_wvalid(2);
timer_m_axi_wvalid <= '0' when m_data_write_connected(3)='0' else m_axi_wvalid(3);
gpio_m_axi_wvalid <= '0' when m_data_write_connected(4)='0' else m_axi_wvalid(4);
uart_m_axi_wvalid <= '0' when m_data_write_connected(5)='0' else m_axi_wvalid(5);
lock_m_axi_wvalid <= '0' when m_data_write_connected(6)='0' else m_axi_wvalid(6);
boot_bram_m_axi_bready <= '0' when m_response_write_connected(0)='0' else m_axi_bready(0);
ram_m_axi_bready <= '0' when m_response_write_connected(1)='0' else m_axi_bready(1);
int_m_axi_bready <= '0' when m_response_write_connected(2)='0' else m_axi_bready(2);
timer_m_axi_bready <= '0' when m_response_write_connected(3)='0' else m_axi_bready(3);
gpio_m_axi_bready <= '0' when m_response_write_connected(4)='0' else m_axi_bready(4);
uart_m_axi_bready <= '0' when m_response_write_connected(5)='0' else m_axi_bready(5);
lock_m_axi_bready <= '0' when m_response_write_connected(6)='0' else m_axi_bready(6);
boot_bram_m_axi_arid <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
ram_m_axi_arid <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_arid <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
timer_m_axi_arid <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
gpio_m_axi_arid <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
uart_m_axi_arid <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arid((1+5)*axi_master_id_width-1 downto 5*axi_master_id_width);
lock_m_axi_arid <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arid((1+6)*axi_master_id_width-1 downto 6*axi_master_id_width);
boot_bram_m_axi_araddr <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_araddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
ram_m_axi_araddr <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_araddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_araddr <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_araddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
timer_m_axi_araddr <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_araddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
gpio_m_axi_araddr <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_araddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
uart_m_axi_araddr <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_araddr((1+5)*axi_address_width-1 downto 5*axi_address_width);
lock_m_axi_araddr <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_araddr((1+6)*axi_address_width-1 downto 6*axi_address_width);
boot_bram_m_axi_arlen <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arlen((1+0)*8-1 downto 0*8);
ram_m_axi_arlen <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arlen((1+1)*8-1 downto 1*8);
int_m_axi_arlen <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arlen((1+2)*8-1 downto 2*8);
timer_m_axi_arlen <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arlen((1+3)*8-1 downto 3*8);
gpio_m_axi_arlen <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arlen((1+4)*8-1 downto 4*8);
uart_m_axi_arlen <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arlen((1+5)*8-1 downto 5*8);
lock_m_axi_arlen <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arlen((1+6)*8-1 downto 6*8);
boot_bram_m_axi_arsize <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arsize((1+0)*3-1 downto 0*3);
ram_m_axi_arsize <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arsize((1+1)*3-1 downto 1*3);
int_m_axi_arsize <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arsize((1+2)*3-1 downto 2*3);
timer_m_axi_arsize <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arsize((1+3)*3-1 downto 3*3);
gpio_m_axi_arsize <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arsize((1+4)*3-1 downto 4*3);
uart_m_axi_arsize <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arsize((1+5)*3-1 downto 5*3);
lock_m_axi_arsize <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arsize((1+6)*3-1 downto 6*3);
boot_bram_m_axi_arburst <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arburst((1+0)*2-1 downto 0*2);
ram_m_axi_arburst <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arburst((1+1)*2-1 downto 1*2);
int_m_axi_arburst <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arburst((1+2)*2-1 downto 2*2);
timer_m_axi_arburst <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arburst((1+3)*2-1 downto 3*2);
gpio_m_axi_arburst <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arburst((1+4)*2-1 downto 4*2);
uart_m_axi_arburst <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arburst((1+5)*2-1 downto 5*2);
lock_m_axi_arburst <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arburst((1+6)*2-1 downto 6*2);
boot_bram_m_axi_arlock <= '0' when m_address_read_connected(0)='0' else m_axi_arlock(0);
ram_m_axi_arlock <= '0' when m_address_read_connected(1)='0' else m_axi_arlock(1);
int_m_axi_arlock <= '0' when m_address_read_connected(2)='0' else m_axi_arlock(2);
timer_m_axi_arlock <= '0' when m_address_read_connected(3)='0' else m_axi_arlock(3);
gpio_m_axi_arlock <= '0' when m_address_read_connected(4)='0' else m_axi_arlock(4);
uart_m_axi_arlock <= '0' when m_address_read_connected(5)='0' else m_axi_arlock(5);
lock_m_axi_arlock <= '0' when m_address_read_connected(6)='0' else m_axi_arlock(6);
boot_bram_m_axi_arcache <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arcache((1+0)*4-1 downto 0*4);
ram_m_axi_arcache <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arcache((1+1)*4-1 downto 1*4);
int_m_axi_arcache <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arcache((1+2)*4-1 downto 2*4);
timer_m_axi_arcache <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arcache((1+3)*4-1 downto 3*4);
gpio_m_axi_arcache <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arcache((1+4)*4-1 downto 4*4);
uart_m_axi_arcache <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arcache((1+5)*4-1 downto 5*4);
lock_m_axi_arcache <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arcache((1+6)*4-1 downto 6*4);
boot_bram_m_axi_arprot <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arprot((1+0)*3-1 downto 0*3);
ram_m_axi_arprot <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arprot((1+1)*3-1 downto 1*3);
int_m_axi_arprot <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arprot((1+2)*3-1 downto 2*3);
timer_m_axi_arprot <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arprot((1+3)*3-1 downto 3*3);
gpio_m_axi_arprot <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arprot((1+4)*3-1 downto 4*3);
uart_m_axi_arprot <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arprot((1+5)*3-1 downto 5*3);
lock_m_axi_arprot <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arprot((1+6)*3-1 downto 6*3);
boot_bram_m_axi_arqos <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arqos((1+0)*4-1 downto 0*4);
ram_m_axi_arqos <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arqos((1+1)*4-1 downto 1*4);
int_m_axi_arqos <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arqos((1+2)*4-1 downto 2*4);
timer_m_axi_arqos <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arqos((1+3)*4-1 downto 3*4);
gpio_m_axi_arqos <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arqos((1+4)*4-1 downto 4*4);
uart_m_axi_arqos <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arqos((1+5)*4-1 downto 5*4);
lock_m_axi_arqos <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arqos((1+6)*4-1 downto 6*4);
boot_bram_m_axi_arregion <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arregion((1+0)*4-1 downto 0*4);
ram_m_axi_arregion <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arregion((1+1)*4-1 downto 1*4);
int_m_axi_arregion <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arregion((1+2)*4-1 downto 2*4);
timer_m_axi_arregion <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arregion((1+3)*4-1 downto 3*4);
gpio_m_axi_arregion <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arregion((1+4)*4-1 downto 4*4);
uart_m_axi_arregion <= (others=>'0') when m_address_read_connected(5)='0' else m_axi_arregion((1+5)*4-1 downto 5*4);
lock_m_axi_arregion <= (others=>'0') when m_address_read_connected(6)='0' else m_axi_arregion((1+6)*4-1 downto 6*4);
boot_bram_m_axi_arvalid <= '0' when m_address_read_connected(0)='0' else m_axi_arvalid(0);
ram_m_axi_arvalid <= '0' when m_address_read_connected(1)='0' else m_axi_arvalid(1);
int_m_axi_arvalid <= '0' when m_address_read_connected(2)='0' else m_axi_arvalid(2);
timer_m_axi_arvalid <= '0' when m_address_read_connected(3)='0' else m_axi_arvalid(3);
gpio_m_axi_arvalid <= '0' when m_address_read_connected(4)='0' else m_axi_arvalid(4);
uart_m_axi_arvalid <= '0' when m_address_read_connected(5)='0' else m_axi_arvalid(5);
lock_m_axi_arvalid <= '0' when m_address_read_connected(6)='0' else m_axi_arvalid(6);
boot_bram_m_axi_rready <= '0' when m_data_read_connected(0)='0' else m_axi_rready(0);
ram_m_axi_rready <= '0' when m_data_read_connected(1)='0' else m_axi_rready(1);
int_m_axi_rready <= '0' when m_data_read_connected(2)='0' else m_axi_rready(2);
timer_m_axi_rready <= '0' when m_data_read_connected(3)='0' else m_axi_rready(3);
gpio_m_axi_rready <= '0' when m_data_read_connected(4)='0' else m_axi_rready(4);
uart_m_axi_rready <= '0' when m_data_read_connected(5)='0' else m_axi_rready(5);
lock_m_axi_rready <= '0' when m_data_read_connected(6)='0' else m_axi_rready(6);
plasoc_crossbar_inst : plasoc_crossbar
generic map
(
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
axi_master_amount => axi_master_amount,
axi_slave_id_width => axi_slave_id_width,
axi_slave_amount => axi_slave_amount,
axi_master_base_address => axi_master_base_address,
axi_master_high_address => axi_master_high_address
)
port map
(
aclk => aclk,
aresetn => aresetn,
s_address_write_connected => s_address_write_connected,
s_data_write_connected => s_data_write_connected,
s_response_write_connected => s_response_write_connected,
s_address_read_connected => s_address_read_connected,
s_data_read_connected => s_data_read_connected,
m_address_write_connected => m_address_write_connected,
m_data_write_connected => m_data_write_connected,
m_response_write_connected => m_response_write_connected,
m_address_read_connected => m_address_read_connected,
m_data_read_connected => m_data_read_connected,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awqos => s_axi_awqos,
s_axi_awregion => s_axi_awregion,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arqos => s_axi_arqos,
s_axi_arregion => s_axi_arregion,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_bid => m_axi_bid,
m_axi_bresp => m_axi_bresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_rid => m_axi_rid,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready
);
end Behavioral;
|
mit
|
2d74626978e362a4cfc64f73a60d2d2a
| 0.675525 | 2.444474 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
unici_core.vhd
| 1 | 985,918 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
--megafunction wizard: %Altera SOPC Builder%
--GENERATION: STANDARD
--VERSION: WM1.0
--Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity avalon64_to_avalon8_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal avalon64_to_avalon8_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_1_downstream_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_downstream_arbitrationshare : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_downstream_burstcount : IN STD_LOGIC;
signal unici_core_burst_1_downstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_1_downstream_latency_counter : IN STD_LOGIC;
signal unici_core_burst_1_downstream_read : IN STD_LOGIC;
signal unici_core_burst_1_downstream_write : IN STD_LOGIC;
signal unici_core_burst_1_downstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal avalon64_to_avalon8_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_read : OUT STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_write : OUT STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0 : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 : OUT STD_LOGIC
);
end entity avalon64_to_avalon8_0_avalon_slave_0_arbitrator;
architecture europa of avalon64_to_avalon8_0_avalon_slave_0_arbitrator is
signal avalon64_to_avalon8_0_avalon_slave_0_allgrants : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_begins_xfer : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_firsttransfer : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_grant_vector : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_waits_for_read : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_waits_for_write : STD_LOGIC;
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_avalon64_to_avalon8_0_avalon_slave_0 : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal internal_avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal internal_unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 : STD_LOGIC;
signal internal_unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 : STD_LOGIC;
signal internal_unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_avalon64_to_avalon8_0_avalon_slave_0_from_unici_core_burst_1_downstream : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_downstream_arbiterlock : STD_LOGIC;
signal unici_core_burst_1_downstream_arbiterlock2 : STD_LOGIC;
signal unici_core_burst_1_downstream_continuerequest : STD_LOGIC;
signal unici_core_burst_1_downstream_saved_grant_avalon64_to_avalon8_0_avalon_slave_0 : STD_LOGIC;
signal wait_for_avalon64_to_avalon8_0_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT avalon64_to_avalon8_0_avalon_slave_0_end_xfer;
end if;
end process;
avalon64_to_avalon8_0_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0);
--assign avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa = avalon64_to_avalon8_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa <= avalon64_to_avalon8_0_avalon_slave_0_readdata;
internal_unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((unici_core_burst_1_downstream_read OR unici_core_burst_1_downstream_write)))))));
--assign avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa = avalon64_to_avalon8_0_avalon_slave_0_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa <= avalon64_to_avalon8_0_avalon_slave_0_waitrequest;
--avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
avalon64_to_avalon8_0_avalon_slave_0_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0)) = '1'), (std_logic_vector'("0000000000000000000000") & (unici_core_burst_1_downstream_arbitrationshare)), std_logic_vector'("00000000000000000000000000000001")), 10);
--avalon64_to_avalon8_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
avalon64_to_avalon8_0_avalon_slave_0_non_bursting_master_requests <= std_logic'('0');
--avalon64_to_avalon8_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
avalon64_to_avalon8_0_avalon_slave_0_any_bursting_master_saved_grant <= unici_core_burst_1_downstream_saved_grant_avalon64_to_avalon8_0_avalon_slave_0;
--avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(avalon64_to_avalon8_0_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000") & (avalon64_to_avalon8_0_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("00000000000000000000000") & (avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 10);
--avalon64_to_avalon8_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
avalon64_to_avalon8_0_avalon_slave_0_allgrants <= avalon64_to_avalon8_0_avalon_slave_0_grant_vector;
--avalon64_to_avalon8_0_avalon_slave_0_end_xfer assignment, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_end_xfer <= NOT ((avalon64_to_avalon8_0_avalon_slave_0_waits_for_read OR avalon64_to_avalon8_0_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_avalon64_to_avalon8_0_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_avalon64_to_avalon8_0_avalon_slave_0 <= avalon64_to_avalon8_0_avalon_slave_0_end_xfer AND (((NOT avalon64_to_avalon8_0_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_avalon64_to_avalon8_0_avalon_slave_0 AND avalon64_to_avalon8_0_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_avalon64_to_avalon8_0_avalon_slave_0 AND NOT avalon64_to_avalon8_0_avalon_slave_0_non_bursting_master_requests));
--avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'(avalon64_to_avalon8_0_avalon_slave_0_arb_counter_enable) = '1' then
avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter <= avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--avalon64_to_avalon8_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
avalon64_to_avalon8_0_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((avalon64_to_avalon8_0_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_avalon64_to_avalon8_0_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_avalon64_to_avalon8_0_avalon_slave_0 AND NOT avalon64_to_avalon8_0_avalon_slave_0_non_bursting_master_requests)))) = '1' then
avalon64_to_avalon8_0_avalon_slave_0_slavearbiterlockenable <= or_reduce(avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--unici_core_burst_1/downstream avalon64_to_avalon8_0/avalon_slave_0 arbiterlock, which is an e_assign
unici_core_burst_1_downstream_arbiterlock <= avalon64_to_avalon8_0_avalon_slave_0_slavearbiterlockenable AND unici_core_burst_1_downstream_continuerequest;
--avalon64_to_avalon8_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(avalon64_to_avalon8_0_avalon_slave_0_arb_share_counter_next_value);
--unici_core_burst_1/downstream avalon64_to_avalon8_0/avalon_slave_0 arbiterlock2, which is an e_assign
unici_core_burst_1_downstream_arbiterlock2 <= avalon64_to_avalon8_0_avalon_slave_0_slavearbiterlockenable2 AND unici_core_burst_1_downstream_continuerequest;
--avalon64_to_avalon8_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_any_continuerequest <= std_logic'('1');
--unici_core_burst_1_downstream_continuerequest continued request, which is an e_assign
unici_core_burst_1_downstream_continuerequest <= std_logic'('1');
internal_unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 <= internal_unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 AND NOT ((unici_core_burst_1_downstream_read AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(unici_core_burst_1_downstream_latency_counter))) /= std_logic_vector'("00000000000000000000000000000000"))))));
--local readdatavalid unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0, which is an e_mux
unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0 <= (internal_unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 AND unici_core_burst_1_downstream_read) AND NOT avalon64_to_avalon8_0_avalon_slave_0_waits_for_read;
--avalon64_to_avalon8_0_avalon_slave_0_writedata mux, which is an e_mux
avalon64_to_avalon8_0_avalon_slave_0_writedata <= unici_core_burst_1_downstream_writedata;
--master is always granted when requested
internal_unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 <= internal_unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0;
--unici_core_burst_1/downstream saved-grant avalon64_to_avalon8_0/avalon_slave_0, which is an e_assign
unici_core_burst_1_downstream_saved_grant_avalon64_to_avalon8_0_avalon_slave_0 <= internal_unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0;
--allow new arb cycle for avalon64_to_avalon8_0/avalon_slave_0, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
avalon64_to_avalon8_0_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
avalon64_to_avalon8_0_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~avalon64_to_avalon8_0_avalon_slave_0_reset assignment, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_reset <= NOT reset_n;
--avalon64_to_avalon8_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(avalon64_to_avalon8_0_avalon_slave_0_begins_xfer) = '1'), avalon64_to_avalon8_0_avalon_slave_0_unreg_firsttransfer, avalon64_to_avalon8_0_avalon_slave_0_reg_firsttransfer);
--avalon64_to_avalon8_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_unreg_firsttransfer <= NOT ((avalon64_to_avalon8_0_avalon_slave_0_slavearbiterlockenable AND avalon64_to_avalon8_0_avalon_slave_0_any_continuerequest));
--avalon64_to_avalon8_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
avalon64_to_avalon8_0_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(avalon64_to_avalon8_0_avalon_slave_0_begins_xfer) = '1' then
avalon64_to_avalon8_0_avalon_slave_0_reg_firsttransfer <= avalon64_to_avalon8_0_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--avalon64_to_avalon8_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_beginbursttransfer_internal <= avalon64_to_avalon8_0_avalon_slave_0_begins_xfer;
--avalon64_to_avalon8_0_avalon_slave_0_read assignment, which is an e_mux
avalon64_to_avalon8_0_avalon_slave_0_read <= internal_unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 AND unici_core_burst_1_downstream_read;
--avalon64_to_avalon8_0_avalon_slave_0_write assignment, which is an e_mux
avalon64_to_avalon8_0_avalon_slave_0_write <= internal_unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 AND unici_core_burst_1_downstream_write;
shifted_address_to_avalon64_to_avalon8_0_avalon_slave_0_from_unici_core_burst_1_downstream <= unici_core_burst_1_downstream_address_to_slave;
--avalon64_to_avalon8_0_avalon_slave_0_address mux, which is an e_mux
avalon64_to_avalon8_0_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_avalon64_to_avalon8_0_avalon_slave_0_from_unici_core_burst_1_downstream,std_logic_vector'("00000000000000000000000000000011")), 15);
--d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer <= avalon64_to_avalon8_0_avalon_slave_0_end_xfer;
end if;
end process;
--avalon64_to_avalon8_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
avalon64_to_avalon8_0_avalon_slave_0_waits_for_read <= avalon64_to_avalon8_0_avalon_slave_0_in_a_read_cycle AND internal_avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa;
--avalon64_to_avalon8_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_in_a_read_cycle <= internal_unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 AND unici_core_burst_1_downstream_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= avalon64_to_avalon8_0_avalon_slave_0_in_a_read_cycle;
--avalon64_to_avalon8_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
avalon64_to_avalon8_0_avalon_slave_0_waits_for_write <= avalon64_to_avalon8_0_avalon_slave_0_in_a_write_cycle AND internal_avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa;
--avalon64_to_avalon8_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
avalon64_to_avalon8_0_avalon_slave_0_in_a_write_cycle <= internal_unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 AND unici_core_burst_1_downstream_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= avalon64_to_avalon8_0_avalon_slave_0_in_a_write_cycle;
wait_for_avalon64_to_avalon8_0_avalon_slave_0_counter <= std_logic'('0');
--avalon64_to_avalon8_0_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
avalon64_to_avalon8_0_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0)) = '1'), (std_logic_vector'("000000000000000000000000") & (unici_core_burst_1_downstream_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 8);
--vhdl renameroo for output signals
avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa <= internal_avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa;
--vhdl renameroo for output signals
unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 <= internal_unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0;
--vhdl renameroo for output signals
unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 <= internal_unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0;
--vhdl renameroo for output signals
unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 <= internal_unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0;
--synthesis translate_off
--avalon64_to_avalon8_0/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--unici_core_burst_1/downstream non-zero arbitrationshare assertion, which is an e_process
process (clk)
VARIABLE write_line : line;
begin
if clk'event and clk = '1' then
if std_logic'(((internal_unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 AND to_std_logic((((std_logic_vector'("0000000000000000000000") & (unici_core_burst_1_downstream_arbitrationshare)) = std_logic_vector'("00000000000000000000000000000000"))))) AND enable_nonzero_assertions)) = '1' then
write(write_line, now);
write(write_line, string'(": "));
write(write_line, string'("unici_core_burst_1/downstream drove 0 on its 'arbitrationshare' port while accessing slave avalon64_to_avalon8_0/avalon_slave_0"));
write(output, write_line.all);
deallocate (write_line);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_1/downstream non-zero burstcount assertion, which is an e_process
process (clk)
VARIABLE write_line1 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((internal_unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(unici_core_burst_1_downstream_burstcount))) = std_logic_vector'("00000000000000000000000000000000"))))) AND enable_nonzero_assertions)) = '1' then
write(write_line1, now);
write(write_line1, string'(": "));
write(write_line1, string'("unici_core_burst_1/downstream drove 0 on its 'burstcount' port while accessing slave avalon64_to_avalon8_0/avalon_slave_0"));
write(output, write_line1.all);
deallocate (write_line1);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ci_bridge_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal ci_bridge_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal ci_bridge_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_write : OUT STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal d1_ci_bridge_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_ci_bridge_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0 : OUT STD_LOGIC
);
end entity ci_bridge_0_avalon_slave_0_arbitrator;
architecture europa of ci_bridge_0_avalon_slave_0_arbitrator is
signal ci_bridge_0_avalon_slave_0_allgrants : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_begins_xfer : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_firsttransfer : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_grant_vector : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_waits_for_read : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_waits_for_write : STD_LOGIC;
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_ci_bridge_0_avalon_slave_0 : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0_segment_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0_segment_1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_ci_bridge_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal internal_int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_ci_bridge_0_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_ci_bridge_0_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT ci_bridge_0_avalon_slave_0_end_xfer;
end if;
end process;
ci_bridge_0_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0);
--assign ci_bridge_0_avalon_slave_0_readdata_from_sa = ci_bridge_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
ci_bridge_0_avalon_slave_0_readdata_from_sa <= ci_bridge_0_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 3) & std_logic_vector'("000")) = std_logic_vector'("100100110000000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--ci_bridge_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
ci_bridge_0_avalon_slave_0_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0)) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000001")), 2);
--ci_bridge_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
ci_bridge_0_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0;
--ci_bridge_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
ci_bridge_0_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--ci_bridge_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
ci_bridge_0_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(ci_bridge_0_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (ci_bridge_0_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(ci_bridge_0_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (ci_bridge_0_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--ci_bridge_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
ci_bridge_0_avalon_slave_0_allgrants <= ci_bridge_0_avalon_slave_0_grant_vector;
--ci_bridge_0_avalon_slave_0_end_xfer assignment, which is an e_assign
ci_bridge_0_avalon_slave_0_end_xfer <= NOT ((ci_bridge_0_avalon_slave_0_waits_for_read OR ci_bridge_0_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_ci_bridge_0_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_ci_bridge_0_avalon_slave_0 <= ci_bridge_0_avalon_slave_0_end_xfer AND (((NOT ci_bridge_0_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--ci_bridge_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
ci_bridge_0_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_ci_bridge_0_avalon_slave_0 AND ci_bridge_0_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_ci_bridge_0_avalon_slave_0 AND NOT ci_bridge_0_avalon_slave_0_non_bursting_master_requests));
--ci_bridge_0_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
ci_bridge_0_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(ci_bridge_0_avalon_slave_0_arb_counter_enable) = '1' then
ci_bridge_0_avalon_slave_0_arb_share_counter <= ci_bridge_0_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--ci_bridge_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
ci_bridge_0_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((ci_bridge_0_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_ci_bridge_0_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_ci_bridge_0_avalon_slave_0 AND NOT ci_bridge_0_avalon_slave_0_non_bursting_master_requests)))) = '1' then
ci_bridge_0_avalon_slave_0_slavearbiterlockenable <= or_reduce(ci_bridge_0_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master ci_bridge_0/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= ci_bridge_0_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--ci_bridge_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
ci_bridge_0_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(ci_bridge_0_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master ci_bridge_0/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= ci_bridge_0_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--ci_bridge_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
ci_bridge_0_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0 AND NOT (((NOT(or_reduce(internal_int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0))) AND int_ctrl_0_avalon_master_write));
--ci_bridge_0_avalon_slave_0_writedata mux, which is an e_mux
ci_bridge_0_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_dbs_write_16;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant ci_bridge_0/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_ci_bridge_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0;
--allow new arb cycle for ci_bridge_0/avalon_slave_0, which is an e_assign
ci_bridge_0_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
ci_bridge_0_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
ci_bridge_0_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~ci_bridge_0_avalon_slave_0_reset assignment, which is an e_assign
ci_bridge_0_avalon_slave_0_reset <= NOT reset_n;
--ci_bridge_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
ci_bridge_0_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(ci_bridge_0_avalon_slave_0_begins_xfer) = '1'), ci_bridge_0_avalon_slave_0_unreg_firsttransfer, ci_bridge_0_avalon_slave_0_reg_firsttransfer);
--ci_bridge_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
ci_bridge_0_avalon_slave_0_unreg_firsttransfer <= NOT ((ci_bridge_0_avalon_slave_0_slavearbiterlockenable AND ci_bridge_0_avalon_slave_0_any_continuerequest));
--ci_bridge_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
ci_bridge_0_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(ci_bridge_0_avalon_slave_0_begins_xfer) = '1' then
ci_bridge_0_avalon_slave_0_reg_firsttransfer <= ci_bridge_0_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--ci_bridge_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
ci_bridge_0_avalon_slave_0_beginbursttransfer_internal <= ci_bridge_0_avalon_slave_0_begins_xfer;
--ci_bridge_0_avalon_slave_0_write assignment, which is an e_mux
ci_bridge_0_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_ci_bridge_0_avalon_slave_0_from_int_ctrl_0_avalon_master <= A_EXT (Std_Logic_Vector'(A_SRL(int_ctrl_0_avalon_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")) & A_ToStdLogicVector(int_ctrl_0_avalon_master_dbs_address(1)) & A_ToStdLogicVector(std_logic'('0'))), 15);
--ci_bridge_0_avalon_slave_0_address mux, which is an e_mux
ci_bridge_0_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_ci_bridge_0_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000001")), 2);
--d1_ci_bridge_0_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_ci_bridge_0_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_ci_bridge_0_avalon_slave_0_end_xfer <= ci_bridge_0_avalon_slave_0_end_xfer;
end if;
end process;
--ci_bridge_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
ci_bridge_0_avalon_slave_0_waits_for_read <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(ci_bridge_0_avalon_slave_0_in_a_read_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--ci_bridge_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
ci_bridge_0_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= ci_bridge_0_avalon_slave_0_in_a_read_cycle;
--ci_bridge_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
ci_bridge_0_avalon_slave_0_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(ci_bridge_0_avalon_slave_0_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--ci_bridge_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
ci_bridge_0_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= ci_bridge_0_avalon_slave_0_in_a_write_cycle;
wait_for_ci_bridge_0_avalon_slave_0_counter <= std_logic'('0');
--ci_bridge_0_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
ci_bridge_0_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (internal_int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 2);
(int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0_segment_1(1), int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0_segment_1(0), int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0_segment_0(1), int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0_segment_0(0)) <= int_ctrl_0_avalon_master_byteenable;
internal_int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_dbs_address(1)))) = std_logic_vector'("00000000000000000000000000000000"))), int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0_segment_0, int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0_segment_1);
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0;
--synthesis translate_off
--ci_bridge_0/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity dma_arbiter_0_avalon_master_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal d1_pcie_compiler_0_Tx_Interface_end_xfer : IN STD_LOGIC;
signal dma_arbiter_0_avalon_master_address : IN STD_LOGIC_VECTOR (30 DOWNTO 0);
signal dma_arbiter_0_avalon_master_burstcount : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma_arbiter_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma_arbiter_0_avalon_master_write : IN STD_LOGIC;
signal dma_arbiter_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface : IN STD_LOGIC;
signal dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface : IN STD_LOGIC;
signal dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface : IN STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_waitrequest_from_sa : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal dma_arbiter_0_avalon_master_address_to_slave : OUT STD_LOGIC_VECTOR (30 DOWNTO 0);
signal dma_arbiter_0_avalon_master_reset : OUT STD_LOGIC;
signal dma_arbiter_0_avalon_master_waitrequest : OUT STD_LOGIC
);
end entity dma_arbiter_0_avalon_master_arbitrator;
architecture europa of dma_arbiter_0_avalon_master_arbitrator is
signal active_and_waiting_last_time : STD_LOGIC;
signal dma_arbiter_0_avalon_master_address_last_time : STD_LOGIC_VECTOR (30 DOWNTO 0);
signal dma_arbiter_0_avalon_master_burstcount_last_time : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma_arbiter_0_avalon_master_byteenable_last_time : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma_arbiter_0_avalon_master_run : STD_LOGIC;
signal dma_arbiter_0_avalon_master_write_last_time : STD_LOGIC;
signal dma_arbiter_0_avalon_master_writedata_last_time : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal internal_dma_arbiter_0_avalon_master_address_to_slave : STD_LOGIC_VECTOR (30 DOWNTO 0);
signal internal_dma_arbiter_0_avalon_master_waitrequest : STD_LOGIC;
signal r_1 : STD_LOGIC;
begin
--r_1 master_run cascaded wait assignment, which is an e_assign
r_1 <= Vector_To_Std_Logic((std_logic_vector'("00000000000000000000000000000001") AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface OR NOT (dma_arbiter_0_avalon_master_write))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT pcie_compiler_0_Tx_Interface_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((dma_arbiter_0_avalon_master_write))))))))));
--cascaded wait assignment, which is an e_assign
dma_arbiter_0_avalon_master_run <= r_1;
--optimize select-logic by passing only those address bits which matter.
internal_dma_arbiter_0_avalon_master_address_to_slave <= dma_arbiter_0_avalon_master_address(30 DOWNTO 0);
--actual waitrequest port, which is an e_assign
internal_dma_arbiter_0_avalon_master_waitrequest <= NOT dma_arbiter_0_avalon_master_run;
--~dma_arbiter_0_avalon_master_reset assignment, which is an e_assign
dma_arbiter_0_avalon_master_reset <= NOT reset_n;
--vhdl renameroo for output signals
dma_arbiter_0_avalon_master_address_to_slave <= internal_dma_arbiter_0_avalon_master_address_to_slave;
--vhdl renameroo for output signals
dma_arbiter_0_avalon_master_waitrequest <= internal_dma_arbiter_0_avalon_master_waitrequest;
--synthesis translate_off
--dma_arbiter_0_avalon_master_address check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dma_arbiter_0_avalon_master_address_last_time <= std_logic_vector'("0000000000000000000000000000000");
elsif clk'event and clk = '1' then
dma_arbiter_0_avalon_master_address_last_time <= dma_arbiter_0_avalon_master_address;
end if;
end process;
--dma_arbiter_0/avalon_master waited last time, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
active_and_waiting_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
active_and_waiting_last_time <= internal_dma_arbiter_0_avalon_master_waitrequest AND (dma_arbiter_0_avalon_master_write);
end if;
end process;
--dma_arbiter_0_avalon_master_address matches last port_name, which is an e_process
process (clk)
VARIABLE write_line2 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((dma_arbiter_0_avalon_master_address /= dma_arbiter_0_avalon_master_address_last_time))))) = '1' then
write(write_line2, now);
write(write_line2, string'(": "));
write(write_line2, string'("dma_arbiter_0_avalon_master_address did not heed wait!!!"));
write(output, write_line2.all);
deallocate (write_line2);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--dma_arbiter_0_avalon_master_burstcount check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dma_arbiter_0_avalon_master_burstcount_last_time <= std_logic_vector'("0000000");
elsif clk'event and clk = '1' then
dma_arbiter_0_avalon_master_burstcount_last_time <= dma_arbiter_0_avalon_master_burstcount;
end if;
end process;
--dma_arbiter_0_avalon_master_burstcount matches last port_name, which is an e_process
process (clk)
VARIABLE write_line3 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((dma_arbiter_0_avalon_master_burstcount /= dma_arbiter_0_avalon_master_burstcount_last_time))))) = '1' then
write(write_line3, now);
write(write_line3, string'(": "));
write(write_line3, string'("dma_arbiter_0_avalon_master_burstcount did not heed wait!!!"));
write(output, write_line3.all);
deallocate (write_line3);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--dma_arbiter_0_avalon_master_byteenable check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dma_arbiter_0_avalon_master_byteenable_last_time <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
dma_arbiter_0_avalon_master_byteenable_last_time <= dma_arbiter_0_avalon_master_byteenable;
end if;
end process;
--dma_arbiter_0_avalon_master_byteenable matches last port_name, which is an e_process
process (clk)
VARIABLE write_line4 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((dma_arbiter_0_avalon_master_byteenable /= dma_arbiter_0_avalon_master_byteenable_last_time))))) = '1' then
write(write_line4, now);
write(write_line4, string'(": "));
write(write_line4, string'("dma_arbiter_0_avalon_master_byteenable did not heed wait!!!"));
write(output, write_line4.all);
deallocate (write_line4);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--dma_arbiter_0_avalon_master_write check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dma_arbiter_0_avalon_master_write_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
dma_arbiter_0_avalon_master_write_last_time <= dma_arbiter_0_avalon_master_write;
end if;
end process;
--dma_arbiter_0_avalon_master_write matches last port_name, which is an e_process
process (clk)
VARIABLE write_line5 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(dma_arbiter_0_avalon_master_write) /= std_logic'(dma_arbiter_0_avalon_master_write_last_time)))))) = '1' then
write(write_line5, now);
write(write_line5, string'(": "));
write(write_line5, string'("dma_arbiter_0_avalon_master_write did not heed wait!!!"));
write(output, write_line5.all);
deallocate (write_line5);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--dma_arbiter_0_avalon_master_writedata check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dma_arbiter_0_avalon_master_writedata_last_time <= std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
dma_arbiter_0_avalon_master_writedata_last_time <= dma_arbiter_0_avalon_master_writedata;
end if;
end process;
--dma_arbiter_0_avalon_master_writedata matches last port_name, which is an e_process
process (clk)
VARIABLE write_line6 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((active_and_waiting_last_time AND to_std_logic(((dma_arbiter_0_avalon_master_writedata /= dma_arbiter_0_avalon_master_writedata_last_time)))) AND dma_arbiter_0_avalon_master_write)) = '1' then
write(write_line6, now);
write(write_line6, string'(": "));
write(write_line6, string'("dma_arbiter_0_avalon_master_writedata did not heed wait!!!"));
write(output, write_line6.all);
deallocate (write_line6);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dvb_dma_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_dvb_dma_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_write : OUT STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_dma_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0 : OUT STD_LOGIC
);
end entity dvb_dma_0_avalon_slave_0_arbitrator;
architecture europa of dvb_dma_0_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_allgrants : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_begins_xfer : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_firsttransfer : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_grant_vector : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_waits_for_read : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_waits_for_write : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_dvb_dma_0_avalon_slave_0 : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_dvb_dma_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_dvb_dma_0_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_dvb_dma_0_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT dvb_dma_0_avalon_slave_0_end_xfer;
end if;
end process;
dvb_dma_0_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0);
--assign dvb_dma_0_avalon_slave_0_readdata_from_sa = dvb_dma_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
dvb_dma_0_avalon_slave_0_readdata_from_sa <= dvb_dma_0_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 6) & std_logic_vector'("000000")) = std_logic_vector'("100100100000000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--dvb_dma_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
dvb_dma_0_avalon_slave_0_arb_share_set_values <= std_logic_vector'("01");
--dvb_dma_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
dvb_dma_0_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0;
--dvb_dma_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
dvb_dma_0_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--dvb_dma_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
dvb_dma_0_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(dvb_dma_0_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (dvb_dma_0_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(dvb_dma_0_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (dvb_dma_0_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--dvb_dma_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
dvb_dma_0_avalon_slave_0_allgrants <= dvb_dma_0_avalon_slave_0_grant_vector;
--dvb_dma_0_avalon_slave_0_end_xfer assignment, which is an e_assign
dvb_dma_0_avalon_slave_0_end_xfer <= NOT ((dvb_dma_0_avalon_slave_0_waits_for_read OR dvb_dma_0_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_dvb_dma_0_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_dvb_dma_0_avalon_slave_0 <= dvb_dma_0_avalon_slave_0_end_xfer AND (((NOT dvb_dma_0_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--dvb_dma_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
dvb_dma_0_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_dvb_dma_0_avalon_slave_0 AND dvb_dma_0_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_dvb_dma_0_avalon_slave_0 AND NOT dvb_dma_0_avalon_slave_0_non_bursting_master_requests));
--dvb_dma_0_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_dma_0_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(dvb_dma_0_avalon_slave_0_arb_counter_enable) = '1' then
dvb_dma_0_avalon_slave_0_arb_share_counter <= dvb_dma_0_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--dvb_dma_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_dma_0_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((dvb_dma_0_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_dvb_dma_0_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_dvb_dma_0_avalon_slave_0 AND NOT dvb_dma_0_avalon_slave_0_non_bursting_master_requests)))) = '1' then
dvb_dma_0_avalon_slave_0_slavearbiterlockenable <= or_reduce(dvb_dma_0_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master dvb_dma_0/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= dvb_dma_0_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--dvb_dma_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
dvb_dma_0_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(dvb_dma_0_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master dvb_dma_0/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= dvb_dma_0_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--dvb_dma_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
dvb_dma_0_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0;
--dvb_dma_0_avalon_slave_0_writedata mux, which is an e_mux
dvb_dma_0_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_writedata;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant dvb_dma_0/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_dvb_dma_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0;
--allow new arb cycle for dvb_dma_0/avalon_slave_0, which is an e_assign
dvb_dma_0_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
dvb_dma_0_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
dvb_dma_0_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~dvb_dma_0_avalon_slave_0_reset assignment, which is an e_assign
dvb_dma_0_avalon_slave_0_reset <= NOT reset_n;
--dvb_dma_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
dvb_dma_0_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(dvb_dma_0_avalon_slave_0_begins_xfer) = '1'), dvb_dma_0_avalon_slave_0_unreg_firsttransfer, dvb_dma_0_avalon_slave_0_reg_firsttransfer);
--dvb_dma_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
dvb_dma_0_avalon_slave_0_unreg_firsttransfer <= NOT ((dvb_dma_0_avalon_slave_0_slavearbiterlockenable AND dvb_dma_0_avalon_slave_0_any_continuerequest));
--dvb_dma_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_dma_0_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(dvb_dma_0_avalon_slave_0_begins_xfer) = '1' then
dvb_dma_0_avalon_slave_0_reg_firsttransfer <= dvb_dma_0_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--dvb_dma_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
dvb_dma_0_avalon_slave_0_beginbursttransfer_internal <= dvb_dma_0_avalon_slave_0_begins_xfer;
--dvb_dma_0_avalon_slave_0_write assignment, which is an e_mux
dvb_dma_0_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_dvb_dma_0_avalon_slave_0_from_int_ctrl_0_avalon_master <= int_ctrl_0_avalon_master_address_to_slave;
--dvb_dma_0_avalon_slave_0_address mux, which is an e_mux
dvb_dma_0_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_dvb_dma_0_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000010")), 4);
--d1_dvb_dma_0_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_dvb_dma_0_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_dvb_dma_0_avalon_slave_0_end_xfer <= dvb_dma_0_avalon_slave_0_end_xfer;
end if;
end process;
--dvb_dma_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
dvb_dma_0_avalon_slave_0_waits_for_read <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dvb_dma_0_avalon_slave_0_in_a_read_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--dvb_dma_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
dvb_dma_0_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= dvb_dma_0_avalon_slave_0_in_a_read_cycle;
--dvb_dma_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
dvb_dma_0_avalon_slave_0_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dvb_dma_0_avalon_slave_0_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--dvb_dma_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
dvb_dma_0_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= dvb_dma_0_avalon_slave_0_in_a_write_cycle;
wait_for_dvb_dma_0_avalon_slave_0_counter <= std_logic'('0');
--dvb_dma_0_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
dvb_dma_0_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (int_ctrl_0_avalon_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0;
--synthesis translate_off
--dvb_dma_0/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dvb_dma_1_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_dvb_dma_1_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_reset : OUT STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_write : OUT STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_dma_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0 : OUT STD_LOGIC
);
end entity dvb_dma_1_avalon_slave_0_arbitrator;
architecture europa of dvb_dma_1_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_allgrants : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_begins_xfer : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_end_xfer : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_firsttransfer : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_grant_vector : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_waits_for_read : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_waits_for_write : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_dvb_dma_1_avalon_slave_0 : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_dvb_dma_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_dvb_dma_1_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_dvb_dma_1_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT dvb_dma_1_avalon_slave_0_end_xfer;
end if;
end process;
dvb_dma_1_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0);
--assign dvb_dma_1_avalon_slave_0_readdata_from_sa = dvb_dma_1_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
dvb_dma_1_avalon_slave_0_readdata_from_sa <= dvb_dma_1_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 6) & std_logic_vector'("000000")) = std_logic_vector'("100100101000000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--dvb_dma_1_avalon_slave_0_arb_share_counter set values, which is an e_mux
dvb_dma_1_avalon_slave_0_arb_share_set_values <= std_logic_vector'("01");
--dvb_dma_1_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
dvb_dma_1_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0;
--dvb_dma_1_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
dvb_dma_1_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--dvb_dma_1_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
dvb_dma_1_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(dvb_dma_1_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (dvb_dma_1_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(dvb_dma_1_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (dvb_dma_1_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--dvb_dma_1_avalon_slave_0_allgrants all slave grants, which is an e_mux
dvb_dma_1_avalon_slave_0_allgrants <= dvb_dma_1_avalon_slave_0_grant_vector;
--dvb_dma_1_avalon_slave_0_end_xfer assignment, which is an e_assign
dvb_dma_1_avalon_slave_0_end_xfer <= NOT ((dvb_dma_1_avalon_slave_0_waits_for_read OR dvb_dma_1_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_dvb_dma_1_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_dvb_dma_1_avalon_slave_0 <= dvb_dma_1_avalon_slave_0_end_xfer AND (((NOT dvb_dma_1_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--dvb_dma_1_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
dvb_dma_1_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_dvb_dma_1_avalon_slave_0 AND dvb_dma_1_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_dvb_dma_1_avalon_slave_0 AND NOT dvb_dma_1_avalon_slave_0_non_bursting_master_requests));
--dvb_dma_1_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_dma_1_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(dvb_dma_1_avalon_slave_0_arb_counter_enable) = '1' then
dvb_dma_1_avalon_slave_0_arb_share_counter <= dvb_dma_1_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--dvb_dma_1_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_dma_1_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((dvb_dma_1_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_dvb_dma_1_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_dvb_dma_1_avalon_slave_0 AND NOT dvb_dma_1_avalon_slave_0_non_bursting_master_requests)))) = '1' then
dvb_dma_1_avalon_slave_0_slavearbiterlockenable <= or_reduce(dvb_dma_1_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master dvb_dma_1/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= dvb_dma_1_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--dvb_dma_1_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
dvb_dma_1_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(dvb_dma_1_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master dvb_dma_1/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= dvb_dma_1_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--dvb_dma_1_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
dvb_dma_1_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0;
--dvb_dma_1_avalon_slave_0_writedata mux, which is an e_mux
dvb_dma_1_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_writedata;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant dvb_dma_1/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_dvb_dma_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0;
--allow new arb cycle for dvb_dma_1/avalon_slave_0, which is an e_assign
dvb_dma_1_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
dvb_dma_1_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
dvb_dma_1_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~dvb_dma_1_avalon_slave_0_reset assignment, which is an e_assign
dvb_dma_1_avalon_slave_0_reset <= NOT reset_n;
--dvb_dma_1_avalon_slave_0_firsttransfer first transaction, which is an e_assign
dvb_dma_1_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(dvb_dma_1_avalon_slave_0_begins_xfer) = '1'), dvb_dma_1_avalon_slave_0_unreg_firsttransfer, dvb_dma_1_avalon_slave_0_reg_firsttransfer);
--dvb_dma_1_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
dvb_dma_1_avalon_slave_0_unreg_firsttransfer <= NOT ((dvb_dma_1_avalon_slave_0_slavearbiterlockenable AND dvb_dma_1_avalon_slave_0_any_continuerequest));
--dvb_dma_1_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_dma_1_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(dvb_dma_1_avalon_slave_0_begins_xfer) = '1' then
dvb_dma_1_avalon_slave_0_reg_firsttransfer <= dvb_dma_1_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--dvb_dma_1_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
dvb_dma_1_avalon_slave_0_beginbursttransfer_internal <= dvb_dma_1_avalon_slave_0_begins_xfer;
--dvb_dma_1_avalon_slave_0_write assignment, which is an e_mux
dvb_dma_1_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_dvb_dma_1_avalon_slave_0_from_int_ctrl_0_avalon_master <= int_ctrl_0_avalon_master_address_to_slave;
--dvb_dma_1_avalon_slave_0_address mux, which is an e_mux
dvb_dma_1_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_dvb_dma_1_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000010")), 4);
--d1_dvb_dma_1_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_dvb_dma_1_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_dvb_dma_1_avalon_slave_0_end_xfer <= dvb_dma_1_avalon_slave_0_end_xfer;
end if;
end process;
--dvb_dma_1_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
dvb_dma_1_avalon_slave_0_waits_for_read <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dvb_dma_1_avalon_slave_0_in_a_read_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--dvb_dma_1_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
dvb_dma_1_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= dvb_dma_1_avalon_slave_0_in_a_read_cycle;
--dvb_dma_1_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
dvb_dma_1_avalon_slave_0_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dvb_dma_1_avalon_slave_0_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--dvb_dma_1_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
dvb_dma_1_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= dvb_dma_1_avalon_slave_0_in_a_write_cycle;
wait_for_dvb_dma_1_avalon_slave_0_counter <= std_logic'('0');
--dvb_dma_1_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
dvb_dma_1_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (int_ctrl_0_avalon_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0;
--synthesis translate_off
--dvb_dma_1/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dvb_ts_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_dvb_ts_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_read : OUT STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_write : OUT STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_ts_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0 : OUT STD_LOGIC
);
end entity dvb_ts_0_avalon_slave_0_arbitrator;
architecture europa of dvb_ts_0_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_allgrants : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_begins_xfer : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_firsttransfer : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_grant_vector : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_waits_for_read : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_waits_for_write : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_dvb_ts_0_avalon_slave_0 : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_dvb_ts_0_avalon_slave_0 : STD_LOGIC;
signal internal_dvb_ts_0_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_dvb_ts_0_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_dvb_ts_0_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT dvb_ts_0_avalon_slave_0_end_xfer;
end if;
end process;
dvb_ts_0_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0);
--assign dvb_ts_0_avalon_slave_0_readdata_from_sa = dvb_ts_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
dvb_ts_0_avalon_slave_0_readdata_from_sa <= dvb_ts_0_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 11) & std_logic_vector'("00000000000")) = std_logic_vector'("101000000000000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--assign dvb_ts_0_avalon_slave_0_waitrequest_from_sa = dvb_ts_0_avalon_slave_0_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_dvb_ts_0_avalon_slave_0_waitrequest_from_sa <= dvb_ts_0_avalon_slave_0_waitrequest;
--dvb_ts_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
dvb_ts_0_avalon_slave_0_arb_share_set_values <= std_logic_vector'("01");
--dvb_ts_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
dvb_ts_0_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0;
--dvb_ts_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
dvb_ts_0_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--dvb_ts_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
dvb_ts_0_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(dvb_ts_0_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (dvb_ts_0_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(dvb_ts_0_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (dvb_ts_0_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--dvb_ts_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
dvb_ts_0_avalon_slave_0_allgrants <= dvb_ts_0_avalon_slave_0_grant_vector;
--dvb_ts_0_avalon_slave_0_end_xfer assignment, which is an e_assign
dvb_ts_0_avalon_slave_0_end_xfer <= NOT ((dvb_ts_0_avalon_slave_0_waits_for_read OR dvb_ts_0_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_dvb_ts_0_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_dvb_ts_0_avalon_slave_0 <= dvb_ts_0_avalon_slave_0_end_xfer AND (((NOT dvb_ts_0_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--dvb_ts_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
dvb_ts_0_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_dvb_ts_0_avalon_slave_0 AND dvb_ts_0_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_dvb_ts_0_avalon_slave_0 AND NOT dvb_ts_0_avalon_slave_0_non_bursting_master_requests));
--dvb_ts_0_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_ts_0_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(dvb_ts_0_avalon_slave_0_arb_counter_enable) = '1' then
dvb_ts_0_avalon_slave_0_arb_share_counter <= dvb_ts_0_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--dvb_ts_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_ts_0_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((dvb_ts_0_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_dvb_ts_0_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_dvb_ts_0_avalon_slave_0 AND NOT dvb_ts_0_avalon_slave_0_non_bursting_master_requests)))) = '1' then
dvb_ts_0_avalon_slave_0_slavearbiterlockenable <= or_reduce(dvb_ts_0_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master dvb_ts_0/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= dvb_ts_0_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--dvb_ts_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
dvb_ts_0_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(dvb_ts_0_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master dvb_ts_0/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= dvb_ts_0_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--dvb_ts_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
dvb_ts_0_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0;
--dvb_ts_0_avalon_slave_0_writedata mux, which is an e_mux
dvb_ts_0_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_writedata;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant dvb_ts_0/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_dvb_ts_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0;
--allow new arb cycle for dvb_ts_0/avalon_slave_0, which is an e_assign
dvb_ts_0_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
dvb_ts_0_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
dvb_ts_0_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~dvb_ts_0_avalon_slave_0_reset assignment, which is an e_assign
dvb_ts_0_avalon_slave_0_reset <= NOT reset_n;
--dvb_ts_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
dvb_ts_0_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(dvb_ts_0_avalon_slave_0_begins_xfer) = '1'), dvb_ts_0_avalon_slave_0_unreg_firsttransfer, dvb_ts_0_avalon_slave_0_reg_firsttransfer);
--dvb_ts_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
dvb_ts_0_avalon_slave_0_unreg_firsttransfer <= NOT ((dvb_ts_0_avalon_slave_0_slavearbiterlockenable AND dvb_ts_0_avalon_slave_0_any_continuerequest));
--dvb_ts_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_ts_0_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(dvb_ts_0_avalon_slave_0_begins_xfer) = '1' then
dvb_ts_0_avalon_slave_0_reg_firsttransfer <= dvb_ts_0_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--dvb_ts_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
dvb_ts_0_avalon_slave_0_beginbursttransfer_internal <= dvb_ts_0_avalon_slave_0_begins_xfer;
--dvb_ts_0_avalon_slave_0_read assignment, which is an e_mux
dvb_ts_0_avalon_slave_0_read <= internal_int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--dvb_ts_0_avalon_slave_0_write assignment, which is an e_mux
dvb_ts_0_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_dvb_ts_0_avalon_slave_0_from_int_ctrl_0_avalon_master <= int_ctrl_0_avalon_master_address_to_slave;
--dvb_ts_0_avalon_slave_0_address mux, which is an e_mux
dvb_ts_0_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_dvb_ts_0_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000010")), 9);
--d1_dvb_ts_0_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_dvb_ts_0_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_dvb_ts_0_avalon_slave_0_end_xfer <= dvb_ts_0_avalon_slave_0_end_xfer;
end if;
end process;
--dvb_ts_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
dvb_ts_0_avalon_slave_0_waits_for_read <= dvb_ts_0_avalon_slave_0_in_a_read_cycle AND internal_dvb_ts_0_avalon_slave_0_waitrequest_from_sa;
--dvb_ts_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
dvb_ts_0_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= dvb_ts_0_avalon_slave_0_in_a_read_cycle;
--dvb_ts_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
dvb_ts_0_avalon_slave_0_waits_for_write <= dvb_ts_0_avalon_slave_0_in_a_write_cycle AND internal_dvb_ts_0_avalon_slave_0_waitrequest_from_sa;
--dvb_ts_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
dvb_ts_0_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= dvb_ts_0_avalon_slave_0_in_a_write_cycle;
wait_for_dvb_ts_0_avalon_slave_0_counter <= std_logic'('0');
--dvb_ts_0_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
dvb_ts_0_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (int_ctrl_0_avalon_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
--vhdl renameroo for output signals
dvb_ts_0_avalon_slave_0_waitrequest_from_sa <= internal_dvb_ts_0_avalon_slave_0_waitrequest_from_sa;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0;
--synthesis translate_off
--dvb_ts_0/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dvb_ts_1_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_dvb_ts_1_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_read : OUT STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_reset : OUT STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_write : OUT STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_ts_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0 : OUT STD_LOGIC
);
end entity dvb_ts_1_avalon_slave_0_arbitrator;
architecture europa of dvb_ts_1_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_allgrants : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_begins_xfer : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_end_xfer : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_firsttransfer : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_grant_vector : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_waits_for_read : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_waits_for_write : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_dvb_ts_1_avalon_slave_0 : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_dvb_ts_1_avalon_slave_0 : STD_LOGIC;
signal internal_dvb_ts_1_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_dvb_ts_1_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_dvb_ts_1_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT dvb_ts_1_avalon_slave_0_end_xfer;
end if;
end process;
dvb_ts_1_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0);
--assign dvb_ts_1_avalon_slave_0_readdata_from_sa = dvb_ts_1_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
dvb_ts_1_avalon_slave_0_readdata_from_sa <= dvb_ts_1_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 11) & std_logic_vector'("00000000000")) = std_logic_vector'("101100000000000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--assign dvb_ts_1_avalon_slave_0_waitrequest_from_sa = dvb_ts_1_avalon_slave_0_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_dvb_ts_1_avalon_slave_0_waitrequest_from_sa <= dvb_ts_1_avalon_slave_0_waitrequest;
--dvb_ts_1_avalon_slave_0_arb_share_counter set values, which is an e_mux
dvb_ts_1_avalon_slave_0_arb_share_set_values <= std_logic_vector'("01");
--dvb_ts_1_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
dvb_ts_1_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0;
--dvb_ts_1_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
dvb_ts_1_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--dvb_ts_1_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
dvb_ts_1_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(dvb_ts_1_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (dvb_ts_1_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(dvb_ts_1_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (dvb_ts_1_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--dvb_ts_1_avalon_slave_0_allgrants all slave grants, which is an e_mux
dvb_ts_1_avalon_slave_0_allgrants <= dvb_ts_1_avalon_slave_0_grant_vector;
--dvb_ts_1_avalon_slave_0_end_xfer assignment, which is an e_assign
dvb_ts_1_avalon_slave_0_end_xfer <= NOT ((dvb_ts_1_avalon_slave_0_waits_for_read OR dvb_ts_1_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_dvb_ts_1_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_dvb_ts_1_avalon_slave_0 <= dvb_ts_1_avalon_slave_0_end_xfer AND (((NOT dvb_ts_1_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--dvb_ts_1_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
dvb_ts_1_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_dvb_ts_1_avalon_slave_0 AND dvb_ts_1_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_dvb_ts_1_avalon_slave_0 AND NOT dvb_ts_1_avalon_slave_0_non_bursting_master_requests));
--dvb_ts_1_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_ts_1_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(dvb_ts_1_avalon_slave_0_arb_counter_enable) = '1' then
dvb_ts_1_avalon_slave_0_arb_share_counter <= dvb_ts_1_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--dvb_ts_1_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_ts_1_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((dvb_ts_1_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_dvb_ts_1_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_dvb_ts_1_avalon_slave_0 AND NOT dvb_ts_1_avalon_slave_0_non_bursting_master_requests)))) = '1' then
dvb_ts_1_avalon_slave_0_slavearbiterlockenable <= or_reduce(dvb_ts_1_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master dvb_ts_1/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= dvb_ts_1_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--dvb_ts_1_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
dvb_ts_1_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(dvb_ts_1_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master dvb_ts_1/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= dvb_ts_1_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--dvb_ts_1_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
dvb_ts_1_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0;
--dvb_ts_1_avalon_slave_0_writedata mux, which is an e_mux
dvb_ts_1_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_writedata;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant dvb_ts_1/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_dvb_ts_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0;
--allow new arb cycle for dvb_ts_1/avalon_slave_0, which is an e_assign
dvb_ts_1_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
dvb_ts_1_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
dvb_ts_1_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~dvb_ts_1_avalon_slave_0_reset assignment, which is an e_assign
dvb_ts_1_avalon_slave_0_reset <= NOT reset_n;
--dvb_ts_1_avalon_slave_0_firsttransfer first transaction, which is an e_assign
dvb_ts_1_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(dvb_ts_1_avalon_slave_0_begins_xfer) = '1'), dvb_ts_1_avalon_slave_0_unreg_firsttransfer, dvb_ts_1_avalon_slave_0_reg_firsttransfer);
--dvb_ts_1_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
dvb_ts_1_avalon_slave_0_unreg_firsttransfer <= NOT ((dvb_ts_1_avalon_slave_0_slavearbiterlockenable AND dvb_ts_1_avalon_slave_0_any_continuerequest));
--dvb_ts_1_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dvb_ts_1_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(dvb_ts_1_avalon_slave_0_begins_xfer) = '1' then
dvb_ts_1_avalon_slave_0_reg_firsttransfer <= dvb_ts_1_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--dvb_ts_1_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
dvb_ts_1_avalon_slave_0_beginbursttransfer_internal <= dvb_ts_1_avalon_slave_0_begins_xfer;
--dvb_ts_1_avalon_slave_0_read assignment, which is an e_mux
dvb_ts_1_avalon_slave_0_read <= internal_int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--dvb_ts_1_avalon_slave_0_write assignment, which is an e_mux
dvb_ts_1_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_dvb_ts_1_avalon_slave_0_from_int_ctrl_0_avalon_master <= int_ctrl_0_avalon_master_address_to_slave;
--dvb_ts_1_avalon_slave_0_address mux, which is an e_mux
dvb_ts_1_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_dvb_ts_1_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000010")), 9);
--d1_dvb_ts_1_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_dvb_ts_1_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_dvb_ts_1_avalon_slave_0_end_xfer <= dvb_ts_1_avalon_slave_0_end_xfer;
end if;
end process;
--dvb_ts_1_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
dvb_ts_1_avalon_slave_0_waits_for_read <= dvb_ts_1_avalon_slave_0_in_a_read_cycle AND internal_dvb_ts_1_avalon_slave_0_waitrequest_from_sa;
--dvb_ts_1_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
dvb_ts_1_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= dvb_ts_1_avalon_slave_0_in_a_read_cycle;
--dvb_ts_1_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
dvb_ts_1_avalon_slave_0_waits_for_write <= dvb_ts_1_avalon_slave_0_in_a_write_cycle AND internal_dvb_ts_1_avalon_slave_0_waitrequest_from_sa;
--dvb_ts_1_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
dvb_ts_1_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= dvb_ts_1_avalon_slave_0_in_a_write_cycle;
wait_for_dvb_ts_1_avalon_slave_0_counter <= std_logic'('0');
--dvb_ts_1_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
dvb_ts_1_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (int_ctrl_0_avalon_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
--vhdl renameroo for output signals
dvb_ts_1_avalon_slave_0_waitrequest_from_sa <= internal_dvb_ts_1_avalon_slave_0_waitrequest_from_sa;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0;
--synthesis translate_off
--dvb_ts_1/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fifo_in_8b_sync_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_read : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_write : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC
);
end entity fifo_in_8b_sync_0_avalon_slave_0_arbitrator;
architecture europa of fifo_in_8b_sync_0_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_fifo_in_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_allgrants : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_begins_xfer : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_firsttransfer : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_grant_vector : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_waits_for_read : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_waits_for_write : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_fifo_in_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal internal_fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_fifo_in_8b_sync_0_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_fifo_in_8b_sync_0_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT fifo_in_8b_sync_0_avalon_slave_0_end_xfer;
end if;
end process;
fifo_in_8b_sync_0_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0);
--assign fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa = fifo_in_8b_sync_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa <= fifo_in_8b_sync_0_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100100000100000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--assign fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa = fifo_in_8b_sync_0_avalon_slave_0_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa <= fifo_in_8b_sync_0_avalon_slave_0_waitrequest;
--fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
fifo_in_8b_sync_0_avalon_slave_0_arb_share_set_values <= std_logic_vector'("01");
--fifo_in_8b_sync_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
fifo_in_8b_sync_0_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0;
--fifo_in_8b_sync_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
fifo_in_8b_sync_0_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(fifo_in_8b_sync_0_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (fifo_in_8b_sync_0_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--fifo_in_8b_sync_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
fifo_in_8b_sync_0_avalon_slave_0_allgrants <= fifo_in_8b_sync_0_avalon_slave_0_grant_vector;
--fifo_in_8b_sync_0_avalon_slave_0_end_xfer assignment, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_end_xfer <= NOT ((fifo_in_8b_sync_0_avalon_slave_0_waits_for_read OR fifo_in_8b_sync_0_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_fifo_in_8b_sync_0_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_fifo_in_8b_sync_0_avalon_slave_0 <= fifo_in_8b_sync_0_avalon_slave_0_end_xfer AND (((NOT fifo_in_8b_sync_0_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_fifo_in_8b_sync_0_avalon_slave_0 AND fifo_in_8b_sync_0_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_fifo_in_8b_sync_0_avalon_slave_0 AND NOT fifo_in_8b_sync_0_avalon_slave_0_non_bursting_master_requests));
--fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(fifo_in_8b_sync_0_avalon_slave_0_arb_counter_enable) = '1' then
fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter <= fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--fifo_in_8b_sync_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_in_8b_sync_0_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((fifo_in_8b_sync_0_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_fifo_in_8b_sync_0_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_fifo_in_8b_sync_0_avalon_slave_0 AND NOT fifo_in_8b_sync_0_avalon_slave_0_non_bursting_master_requests)))) = '1' then
fifo_in_8b_sync_0_avalon_slave_0_slavearbiterlockenable <= or_reduce(fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master fifo_in_8b_sync_0/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= fifo_in_8b_sync_0_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--fifo_in_8b_sync_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(fifo_in_8b_sync_0_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master fifo_in_8b_sync_0/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= fifo_in_8b_sync_0_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--fifo_in_8b_sync_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0;
--fifo_in_8b_sync_0_avalon_slave_0_writedata mux, which is an e_mux
fifo_in_8b_sync_0_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_writedata;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant fifo_in_8b_sync_0/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_fifo_in_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0;
--allow new arb cycle for fifo_in_8b_sync_0/avalon_slave_0, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
fifo_in_8b_sync_0_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
fifo_in_8b_sync_0_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~fifo_in_8b_sync_0_avalon_slave_0_reset assignment, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_reset <= NOT reset_n;
--fifo_in_8b_sync_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(fifo_in_8b_sync_0_avalon_slave_0_begins_xfer) = '1'), fifo_in_8b_sync_0_avalon_slave_0_unreg_firsttransfer, fifo_in_8b_sync_0_avalon_slave_0_reg_firsttransfer);
--fifo_in_8b_sync_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_unreg_firsttransfer <= NOT ((fifo_in_8b_sync_0_avalon_slave_0_slavearbiterlockenable AND fifo_in_8b_sync_0_avalon_slave_0_any_continuerequest));
--fifo_in_8b_sync_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_in_8b_sync_0_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(fifo_in_8b_sync_0_avalon_slave_0_begins_xfer) = '1' then
fifo_in_8b_sync_0_avalon_slave_0_reg_firsttransfer <= fifo_in_8b_sync_0_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--fifo_in_8b_sync_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_beginbursttransfer_internal <= fifo_in_8b_sync_0_avalon_slave_0_begins_xfer;
--fifo_in_8b_sync_0_avalon_slave_0_read assignment, which is an e_mux
fifo_in_8b_sync_0_avalon_slave_0_read <= internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--fifo_in_8b_sync_0_avalon_slave_0_write assignment, which is an e_mux
fifo_in_8b_sync_0_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_fifo_in_8b_sync_0_avalon_slave_0_from_int_ctrl_0_avalon_master <= int_ctrl_0_avalon_master_address_to_slave;
--fifo_in_8b_sync_0_avalon_slave_0_address mux, which is an e_mux
fifo_in_8b_sync_0_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_fifo_in_8b_sync_0_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000010")), 2);
--d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer <= fifo_in_8b_sync_0_avalon_slave_0_end_xfer;
end if;
end process;
--fifo_in_8b_sync_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
fifo_in_8b_sync_0_avalon_slave_0_waits_for_read <= fifo_in_8b_sync_0_avalon_slave_0_in_a_read_cycle AND internal_fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa;
--fifo_in_8b_sync_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= fifo_in_8b_sync_0_avalon_slave_0_in_a_read_cycle;
--fifo_in_8b_sync_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
fifo_in_8b_sync_0_avalon_slave_0_waits_for_write <= fifo_in_8b_sync_0_avalon_slave_0_in_a_write_cycle AND internal_fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa;
--fifo_in_8b_sync_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
fifo_in_8b_sync_0_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= fifo_in_8b_sync_0_avalon_slave_0_in_a_write_cycle;
wait_for_fifo_in_8b_sync_0_avalon_slave_0_counter <= std_logic'('0');
--fifo_in_8b_sync_0_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
fifo_in_8b_sync_0_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (int_ctrl_0_avalon_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
--vhdl renameroo for output signals
fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa <= internal_fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0;
--synthesis translate_off
--fifo_in_8b_sync_0/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fifo_in_8b_sync_0_avalon_streaming_sink_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_streaming_sink_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_0_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_0_avalon_streaming_source_valid : IN STD_LOGIC;
-- outputs:
signal fifo_in_8b_sync_0_avalon_streaming_sink_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_streaming_sink_valid : OUT STD_LOGIC
);
end entity fifo_in_8b_sync_0_avalon_streaming_sink_arbitrator;
architecture europa of fifo_in_8b_sync_0_avalon_streaming_sink_arbitrator is
begin
--mux fifo_in_8b_sync_0_avalon_streaming_sink_data, which is an e_mux
fifo_in_8b_sync_0_avalon_streaming_sink_data <= twi_master_0_avalon_streaming_source_data;
--assign fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa = fifo_in_8b_sync_0_avalon_streaming_sink_ready so that symbol knows where to group signals which may go to master only, which is an e_assign
fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa <= fifo_in_8b_sync_0_avalon_streaming_sink_ready;
--mux fifo_in_8b_sync_0_avalon_streaming_sink_valid, which is an e_mux
fifo_in_8b_sync_0_avalon_streaming_sink_valid <= twi_master_0_avalon_streaming_source_valid;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fifo_in_8b_sync_1_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_read : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_reset : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_write : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC
);
end entity fifo_in_8b_sync_1_avalon_slave_0_arbitrator;
architecture europa of fifo_in_8b_sync_1_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_fifo_in_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_allgrants : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_begins_xfer : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_end_xfer : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_firsttransfer : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_grant_vector : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_waits_for_read : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_waits_for_write : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_fifo_in_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal internal_fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_fifo_in_8b_sync_1_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_fifo_in_8b_sync_1_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT fifo_in_8b_sync_1_avalon_slave_0_end_xfer;
end if;
end process;
fifo_in_8b_sync_1_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0);
--assign fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa = fifo_in_8b_sync_1_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa <= fifo_in_8b_sync_1_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100100001100000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--assign fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa = fifo_in_8b_sync_1_avalon_slave_0_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa <= fifo_in_8b_sync_1_avalon_slave_0_waitrequest;
--fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter set values, which is an e_mux
fifo_in_8b_sync_1_avalon_slave_0_arb_share_set_values <= std_logic_vector'("01");
--fifo_in_8b_sync_1_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
fifo_in_8b_sync_1_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0;
--fifo_in_8b_sync_1_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
fifo_in_8b_sync_1_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(fifo_in_8b_sync_1_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (fifo_in_8b_sync_1_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--fifo_in_8b_sync_1_avalon_slave_0_allgrants all slave grants, which is an e_mux
fifo_in_8b_sync_1_avalon_slave_0_allgrants <= fifo_in_8b_sync_1_avalon_slave_0_grant_vector;
--fifo_in_8b_sync_1_avalon_slave_0_end_xfer assignment, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_end_xfer <= NOT ((fifo_in_8b_sync_1_avalon_slave_0_waits_for_read OR fifo_in_8b_sync_1_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_fifo_in_8b_sync_1_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_fifo_in_8b_sync_1_avalon_slave_0 <= fifo_in_8b_sync_1_avalon_slave_0_end_xfer AND (((NOT fifo_in_8b_sync_1_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_fifo_in_8b_sync_1_avalon_slave_0 AND fifo_in_8b_sync_1_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_fifo_in_8b_sync_1_avalon_slave_0 AND NOT fifo_in_8b_sync_1_avalon_slave_0_non_bursting_master_requests));
--fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(fifo_in_8b_sync_1_avalon_slave_0_arb_counter_enable) = '1' then
fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter <= fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--fifo_in_8b_sync_1_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_in_8b_sync_1_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((fifo_in_8b_sync_1_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_fifo_in_8b_sync_1_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_fifo_in_8b_sync_1_avalon_slave_0 AND NOT fifo_in_8b_sync_1_avalon_slave_0_non_bursting_master_requests)))) = '1' then
fifo_in_8b_sync_1_avalon_slave_0_slavearbiterlockenable <= or_reduce(fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master fifo_in_8b_sync_1/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= fifo_in_8b_sync_1_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--fifo_in_8b_sync_1_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(fifo_in_8b_sync_1_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master fifo_in_8b_sync_1/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= fifo_in_8b_sync_1_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--fifo_in_8b_sync_1_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0;
--fifo_in_8b_sync_1_avalon_slave_0_writedata mux, which is an e_mux
fifo_in_8b_sync_1_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_writedata;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant fifo_in_8b_sync_1/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_fifo_in_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0;
--allow new arb cycle for fifo_in_8b_sync_1/avalon_slave_0, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
fifo_in_8b_sync_1_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
fifo_in_8b_sync_1_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~fifo_in_8b_sync_1_avalon_slave_0_reset assignment, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_reset <= NOT reset_n;
--fifo_in_8b_sync_1_avalon_slave_0_firsttransfer first transaction, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(fifo_in_8b_sync_1_avalon_slave_0_begins_xfer) = '1'), fifo_in_8b_sync_1_avalon_slave_0_unreg_firsttransfer, fifo_in_8b_sync_1_avalon_slave_0_reg_firsttransfer);
--fifo_in_8b_sync_1_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_unreg_firsttransfer <= NOT ((fifo_in_8b_sync_1_avalon_slave_0_slavearbiterlockenable AND fifo_in_8b_sync_1_avalon_slave_0_any_continuerequest));
--fifo_in_8b_sync_1_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_in_8b_sync_1_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(fifo_in_8b_sync_1_avalon_slave_0_begins_xfer) = '1' then
fifo_in_8b_sync_1_avalon_slave_0_reg_firsttransfer <= fifo_in_8b_sync_1_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--fifo_in_8b_sync_1_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_beginbursttransfer_internal <= fifo_in_8b_sync_1_avalon_slave_0_begins_xfer;
--fifo_in_8b_sync_1_avalon_slave_0_read assignment, which is an e_mux
fifo_in_8b_sync_1_avalon_slave_0_read <= internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--fifo_in_8b_sync_1_avalon_slave_0_write assignment, which is an e_mux
fifo_in_8b_sync_1_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_fifo_in_8b_sync_1_avalon_slave_0_from_int_ctrl_0_avalon_master <= int_ctrl_0_avalon_master_address_to_slave;
--fifo_in_8b_sync_1_avalon_slave_0_address mux, which is an e_mux
fifo_in_8b_sync_1_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_fifo_in_8b_sync_1_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000010")), 2);
--d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer <= fifo_in_8b_sync_1_avalon_slave_0_end_xfer;
end if;
end process;
--fifo_in_8b_sync_1_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
fifo_in_8b_sync_1_avalon_slave_0_waits_for_read <= fifo_in_8b_sync_1_avalon_slave_0_in_a_read_cycle AND internal_fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa;
--fifo_in_8b_sync_1_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= fifo_in_8b_sync_1_avalon_slave_0_in_a_read_cycle;
--fifo_in_8b_sync_1_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
fifo_in_8b_sync_1_avalon_slave_0_waits_for_write <= fifo_in_8b_sync_1_avalon_slave_0_in_a_write_cycle AND internal_fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa;
--fifo_in_8b_sync_1_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
fifo_in_8b_sync_1_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= fifo_in_8b_sync_1_avalon_slave_0_in_a_write_cycle;
wait_for_fifo_in_8b_sync_1_avalon_slave_0_counter <= std_logic'('0');
--fifo_in_8b_sync_1_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
fifo_in_8b_sync_1_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (int_ctrl_0_avalon_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
--vhdl renameroo for output signals
fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa <= internal_fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0;
--synthesis translate_off
--fifo_in_8b_sync_1/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fifo_in_8b_sync_1_avalon_streaming_sink_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_streaming_sink_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_1_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_1_avalon_streaming_source_valid : IN STD_LOGIC;
-- outputs:
signal fifo_in_8b_sync_1_avalon_streaming_sink_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_streaming_sink_valid : OUT STD_LOGIC
);
end entity fifo_in_8b_sync_1_avalon_streaming_sink_arbitrator;
architecture europa of fifo_in_8b_sync_1_avalon_streaming_sink_arbitrator is
begin
--mux fifo_in_8b_sync_1_avalon_streaming_sink_data, which is an e_mux
fifo_in_8b_sync_1_avalon_streaming_sink_data <= twi_master_1_avalon_streaming_source_data;
--assign fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa = fifo_in_8b_sync_1_avalon_streaming_sink_ready so that symbol knows where to group signals which may go to master only, which is an e_assign
fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa <= fifo_in_8b_sync_1_avalon_streaming_sink_ready;
--mux fifo_in_8b_sync_1_avalon_streaming_sink_valid, which is an e_mux
fifo_in_8b_sync_1_avalon_streaming_sink_valid <= twi_master_1_avalon_streaming_source_valid;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fifo_out_8b_sync_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_write : OUT STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC
);
end entity fifo_out_8b_sync_0_avalon_slave_0_arbitrator;
architecture europa of fifo_out_8b_sync_0_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_fifo_out_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_allgrants : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_begins_xfer : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_firsttransfer : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_grant_vector : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_waits_for_read : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_waits_for_write : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_fifo_out_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal internal_fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_fifo_out_8b_sync_0_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_fifo_out_8b_sync_0_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT fifo_out_8b_sync_0_avalon_slave_0_end_xfer;
end if;
end process;
fifo_out_8b_sync_0_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0);
--assign fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa = fifo_out_8b_sync_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa <= fifo_out_8b_sync_0_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100100000010000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--assign fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa = fifo_out_8b_sync_0_avalon_slave_0_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa <= fifo_out_8b_sync_0_avalon_slave_0_waitrequest;
--fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
fifo_out_8b_sync_0_avalon_slave_0_arb_share_set_values <= std_logic_vector'("01");
--fifo_out_8b_sync_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
fifo_out_8b_sync_0_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0;
--fifo_out_8b_sync_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
fifo_out_8b_sync_0_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(fifo_out_8b_sync_0_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (fifo_out_8b_sync_0_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--fifo_out_8b_sync_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
fifo_out_8b_sync_0_avalon_slave_0_allgrants <= fifo_out_8b_sync_0_avalon_slave_0_grant_vector;
--fifo_out_8b_sync_0_avalon_slave_0_end_xfer assignment, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_end_xfer <= NOT ((fifo_out_8b_sync_0_avalon_slave_0_waits_for_read OR fifo_out_8b_sync_0_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_fifo_out_8b_sync_0_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_fifo_out_8b_sync_0_avalon_slave_0 <= fifo_out_8b_sync_0_avalon_slave_0_end_xfer AND (((NOT fifo_out_8b_sync_0_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_fifo_out_8b_sync_0_avalon_slave_0 AND fifo_out_8b_sync_0_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_fifo_out_8b_sync_0_avalon_slave_0 AND NOT fifo_out_8b_sync_0_avalon_slave_0_non_bursting_master_requests));
--fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(fifo_out_8b_sync_0_avalon_slave_0_arb_counter_enable) = '1' then
fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter <= fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--fifo_out_8b_sync_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_out_8b_sync_0_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((fifo_out_8b_sync_0_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_fifo_out_8b_sync_0_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_fifo_out_8b_sync_0_avalon_slave_0 AND NOT fifo_out_8b_sync_0_avalon_slave_0_non_bursting_master_requests)))) = '1' then
fifo_out_8b_sync_0_avalon_slave_0_slavearbiterlockenable <= or_reduce(fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master fifo_out_8b_sync_0/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= fifo_out_8b_sync_0_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--fifo_out_8b_sync_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(fifo_out_8b_sync_0_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master fifo_out_8b_sync_0/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= fifo_out_8b_sync_0_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--fifo_out_8b_sync_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0;
--fifo_out_8b_sync_0_avalon_slave_0_writedata mux, which is an e_mux
fifo_out_8b_sync_0_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_writedata;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant fifo_out_8b_sync_0/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_fifo_out_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0;
--allow new arb cycle for fifo_out_8b_sync_0/avalon_slave_0, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
fifo_out_8b_sync_0_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
fifo_out_8b_sync_0_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~fifo_out_8b_sync_0_avalon_slave_0_reset assignment, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_reset <= NOT reset_n;
--fifo_out_8b_sync_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(fifo_out_8b_sync_0_avalon_slave_0_begins_xfer) = '1'), fifo_out_8b_sync_0_avalon_slave_0_unreg_firsttransfer, fifo_out_8b_sync_0_avalon_slave_0_reg_firsttransfer);
--fifo_out_8b_sync_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_unreg_firsttransfer <= NOT ((fifo_out_8b_sync_0_avalon_slave_0_slavearbiterlockenable AND fifo_out_8b_sync_0_avalon_slave_0_any_continuerequest));
--fifo_out_8b_sync_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_out_8b_sync_0_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(fifo_out_8b_sync_0_avalon_slave_0_begins_xfer) = '1' then
fifo_out_8b_sync_0_avalon_slave_0_reg_firsttransfer <= fifo_out_8b_sync_0_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--fifo_out_8b_sync_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_beginbursttransfer_internal <= fifo_out_8b_sync_0_avalon_slave_0_begins_xfer;
--fifo_out_8b_sync_0_avalon_slave_0_write assignment, which is an e_mux
fifo_out_8b_sync_0_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_fifo_out_8b_sync_0_avalon_slave_0_from_int_ctrl_0_avalon_master <= int_ctrl_0_avalon_master_address_to_slave;
--fifo_out_8b_sync_0_avalon_slave_0_address mux, which is an e_mux
fifo_out_8b_sync_0_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_fifo_out_8b_sync_0_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000010")), 2);
--d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer <= fifo_out_8b_sync_0_avalon_slave_0_end_xfer;
end if;
end process;
--fifo_out_8b_sync_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
fifo_out_8b_sync_0_avalon_slave_0_waits_for_read <= fifo_out_8b_sync_0_avalon_slave_0_in_a_read_cycle AND internal_fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa;
--fifo_out_8b_sync_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= fifo_out_8b_sync_0_avalon_slave_0_in_a_read_cycle;
--fifo_out_8b_sync_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
fifo_out_8b_sync_0_avalon_slave_0_waits_for_write <= fifo_out_8b_sync_0_avalon_slave_0_in_a_write_cycle AND internal_fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa;
--fifo_out_8b_sync_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
fifo_out_8b_sync_0_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= fifo_out_8b_sync_0_avalon_slave_0_in_a_write_cycle;
wait_for_fifo_out_8b_sync_0_avalon_slave_0_counter <= std_logic'('0');
--fifo_out_8b_sync_0_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
fifo_out_8b_sync_0_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (int_ctrl_0_avalon_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
--vhdl renameroo for output signals
fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa <= internal_fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0;
--synthesis translate_off
--fifo_out_8b_sync_0/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fifo_out_8b_sync_0_avalon_streaming_source_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_streaming_source_valid : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_0_avalon_streaming_sink_ready_from_sa : IN STD_LOGIC;
-- outputs:
signal fifo_out_8b_sync_0_avalon_streaming_source_ready : OUT STD_LOGIC
);
end entity fifo_out_8b_sync_0_avalon_streaming_source_arbitrator;
architecture europa of fifo_out_8b_sync_0_avalon_streaming_source_arbitrator is
begin
--mux fifo_out_8b_sync_0_avalon_streaming_source_ready, which is an e_mux
fifo_out_8b_sync_0_avalon_streaming_source_ready <= twi_master_0_avalon_streaming_sink_ready_from_sa;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fifo_out_8b_sync_1_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_reset : OUT STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_write : OUT STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC
);
end entity fifo_out_8b_sync_1_avalon_slave_0_arbitrator;
architecture europa of fifo_out_8b_sync_1_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_fifo_out_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_allgrants : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_begins_xfer : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_end_xfer : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_firsttransfer : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_grant_vector : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_waits_for_read : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_waits_for_write : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_fifo_out_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal internal_fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_fifo_out_8b_sync_1_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_fifo_out_8b_sync_1_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT fifo_out_8b_sync_1_avalon_slave_0_end_xfer;
end if;
end process;
fifo_out_8b_sync_1_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0);
--assign fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa = fifo_out_8b_sync_1_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa <= fifo_out_8b_sync_1_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100100001010000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--assign fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa = fifo_out_8b_sync_1_avalon_slave_0_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa <= fifo_out_8b_sync_1_avalon_slave_0_waitrequest;
--fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter set values, which is an e_mux
fifo_out_8b_sync_1_avalon_slave_0_arb_share_set_values <= std_logic_vector'("01");
--fifo_out_8b_sync_1_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
fifo_out_8b_sync_1_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0;
--fifo_out_8b_sync_1_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
fifo_out_8b_sync_1_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(fifo_out_8b_sync_1_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (fifo_out_8b_sync_1_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--fifo_out_8b_sync_1_avalon_slave_0_allgrants all slave grants, which is an e_mux
fifo_out_8b_sync_1_avalon_slave_0_allgrants <= fifo_out_8b_sync_1_avalon_slave_0_grant_vector;
--fifo_out_8b_sync_1_avalon_slave_0_end_xfer assignment, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_end_xfer <= NOT ((fifo_out_8b_sync_1_avalon_slave_0_waits_for_read OR fifo_out_8b_sync_1_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_fifo_out_8b_sync_1_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_fifo_out_8b_sync_1_avalon_slave_0 <= fifo_out_8b_sync_1_avalon_slave_0_end_xfer AND (((NOT fifo_out_8b_sync_1_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_fifo_out_8b_sync_1_avalon_slave_0 AND fifo_out_8b_sync_1_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_fifo_out_8b_sync_1_avalon_slave_0 AND NOT fifo_out_8b_sync_1_avalon_slave_0_non_bursting_master_requests));
--fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(fifo_out_8b_sync_1_avalon_slave_0_arb_counter_enable) = '1' then
fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter <= fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--fifo_out_8b_sync_1_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_out_8b_sync_1_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((fifo_out_8b_sync_1_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_fifo_out_8b_sync_1_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_fifo_out_8b_sync_1_avalon_slave_0 AND NOT fifo_out_8b_sync_1_avalon_slave_0_non_bursting_master_requests)))) = '1' then
fifo_out_8b_sync_1_avalon_slave_0_slavearbiterlockenable <= or_reduce(fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master fifo_out_8b_sync_1/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= fifo_out_8b_sync_1_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--fifo_out_8b_sync_1_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(fifo_out_8b_sync_1_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master fifo_out_8b_sync_1/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= fifo_out_8b_sync_1_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--fifo_out_8b_sync_1_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0;
--fifo_out_8b_sync_1_avalon_slave_0_writedata mux, which is an e_mux
fifo_out_8b_sync_1_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_writedata;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant fifo_out_8b_sync_1/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_fifo_out_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0;
--allow new arb cycle for fifo_out_8b_sync_1/avalon_slave_0, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
fifo_out_8b_sync_1_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
fifo_out_8b_sync_1_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~fifo_out_8b_sync_1_avalon_slave_0_reset assignment, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_reset <= NOT reset_n;
--fifo_out_8b_sync_1_avalon_slave_0_firsttransfer first transaction, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(fifo_out_8b_sync_1_avalon_slave_0_begins_xfer) = '1'), fifo_out_8b_sync_1_avalon_slave_0_unreg_firsttransfer, fifo_out_8b_sync_1_avalon_slave_0_reg_firsttransfer);
--fifo_out_8b_sync_1_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_unreg_firsttransfer <= NOT ((fifo_out_8b_sync_1_avalon_slave_0_slavearbiterlockenable AND fifo_out_8b_sync_1_avalon_slave_0_any_continuerequest));
--fifo_out_8b_sync_1_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_out_8b_sync_1_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(fifo_out_8b_sync_1_avalon_slave_0_begins_xfer) = '1' then
fifo_out_8b_sync_1_avalon_slave_0_reg_firsttransfer <= fifo_out_8b_sync_1_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--fifo_out_8b_sync_1_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_beginbursttransfer_internal <= fifo_out_8b_sync_1_avalon_slave_0_begins_xfer;
--fifo_out_8b_sync_1_avalon_slave_0_write assignment, which is an e_mux
fifo_out_8b_sync_1_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_fifo_out_8b_sync_1_avalon_slave_0_from_int_ctrl_0_avalon_master <= int_ctrl_0_avalon_master_address_to_slave;
--fifo_out_8b_sync_1_avalon_slave_0_address mux, which is an e_mux
fifo_out_8b_sync_1_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_fifo_out_8b_sync_1_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000010")), 2);
--d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer <= fifo_out_8b_sync_1_avalon_slave_0_end_xfer;
end if;
end process;
--fifo_out_8b_sync_1_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
fifo_out_8b_sync_1_avalon_slave_0_waits_for_read <= fifo_out_8b_sync_1_avalon_slave_0_in_a_read_cycle AND internal_fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa;
--fifo_out_8b_sync_1_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= fifo_out_8b_sync_1_avalon_slave_0_in_a_read_cycle;
--fifo_out_8b_sync_1_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
fifo_out_8b_sync_1_avalon_slave_0_waits_for_write <= fifo_out_8b_sync_1_avalon_slave_0_in_a_write_cycle AND internal_fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa;
--fifo_out_8b_sync_1_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
fifo_out_8b_sync_1_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= fifo_out_8b_sync_1_avalon_slave_0_in_a_write_cycle;
wait_for_fifo_out_8b_sync_1_avalon_slave_0_counter <= std_logic'('0');
--fifo_out_8b_sync_1_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
fifo_out_8b_sync_1_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (int_ctrl_0_avalon_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
--vhdl renameroo for output signals
fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa <= internal_fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0;
--synthesis translate_off
--fifo_out_8b_sync_1/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fifo_out_8b_sync_1_avalon_streaming_source_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_streaming_source_valid : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_1_avalon_streaming_sink_ready_from_sa : IN STD_LOGIC;
-- outputs:
signal fifo_out_8b_sync_1_avalon_streaming_source_ready : OUT STD_LOGIC
);
end entity fifo_out_8b_sync_1_avalon_streaming_source_arbitrator;
architecture europa of fifo_out_8b_sync_1_avalon_streaming_source_arbitrator is
begin
--mux fifo_out_8b_sync_1_avalon_streaming_source_ready, which is an e_mux
fifo_out_8b_sync_1_avalon_streaming_source_ready <= twi_master_1_avalon_streaming_sink_ready_from_sa;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity gpout_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal gpout_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_gpout_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal gpout_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal gpout_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal gpout_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal gpout_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal gpout_0_avalon_slave_0_write : OUT STD_LOGIC;
signal gpout_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_gpout_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0 : OUT STD_LOGIC
);
end entity gpout_0_avalon_slave_0_arbitrator;
architecture europa of gpout_0_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_gpout_0_avalon_slave_0 : STD_LOGIC;
signal gpout_0_avalon_slave_0_allgrants : STD_LOGIC;
signal gpout_0_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal gpout_0_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal gpout_0_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal gpout_0_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal gpout_0_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal gpout_0_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal gpout_0_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal gpout_0_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal gpout_0_avalon_slave_0_begins_xfer : STD_LOGIC;
signal gpout_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal gpout_0_avalon_slave_0_firsttransfer : STD_LOGIC;
signal gpout_0_avalon_slave_0_grant_vector : STD_LOGIC;
signal gpout_0_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal gpout_0_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal gpout_0_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal gpout_0_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal gpout_0_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal gpout_0_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal gpout_0_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal gpout_0_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal gpout_0_avalon_slave_0_waits_for_read : STD_LOGIC;
signal gpout_0_avalon_slave_0_waits_for_write : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0_segment_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0_segment_1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_gpout_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal internal_int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_gpout_0_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_gpout_0_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT gpout_0_avalon_slave_0_end_xfer;
end if;
end process;
gpout_0_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0);
--assign gpout_0_avalon_slave_0_readdata_from_sa = gpout_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
gpout_0_avalon_slave_0_readdata_from_sa <= gpout_0_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 3) & std_logic_vector'("000")) = std_logic_vector'("100100010000000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--gpout_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
gpout_0_avalon_slave_0_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0)) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000001")), 2);
--gpout_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
gpout_0_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0;
--gpout_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
gpout_0_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--gpout_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
gpout_0_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(gpout_0_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (gpout_0_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(gpout_0_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (gpout_0_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--gpout_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
gpout_0_avalon_slave_0_allgrants <= gpout_0_avalon_slave_0_grant_vector;
--gpout_0_avalon_slave_0_end_xfer assignment, which is an e_assign
gpout_0_avalon_slave_0_end_xfer <= NOT ((gpout_0_avalon_slave_0_waits_for_read OR gpout_0_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_gpout_0_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_gpout_0_avalon_slave_0 <= gpout_0_avalon_slave_0_end_xfer AND (((NOT gpout_0_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--gpout_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
gpout_0_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_gpout_0_avalon_slave_0 AND gpout_0_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_gpout_0_avalon_slave_0 AND NOT gpout_0_avalon_slave_0_non_bursting_master_requests));
--gpout_0_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
gpout_0_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(gpout_0_avalon_slave_0_arb_counter_enable) = '1' then
gpout_0_avalon_slave_0_arb_share_counter <= gpout_0_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--gpout_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
gpout_0_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((gpout_0_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_gpout_0_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_gpout_0_avalon_slave_0 AND NOT gpout_0_avalon_slave_0_non_bursting_master_requests)))) = '1' then
gpout_0_avalon_slave_0_slavearbiterlockenable <= or_reduce(gpout_0_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master gpout_0/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= gpout_0_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--gpout_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
gpout_0_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(gpout_0_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master gpout_0/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= gpout_0_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--gpout_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
gpout_0_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0 AND NOT (((NOT(or_reduce(internal_int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0))) AND int_ctrl_0_avalon_master_write));
--gpout_0_avalon_slave_0_writedata mux, which is an e_mux
gpout_0_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_dbs_write_16;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant gpout_0/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_gpout_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0;
--allow new arb cycle for gpout_0/avalon_slave_0, which is an e_assign
gpout_0_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
gpout_0_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
gpout_0_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~gpout_0_avalon_slave_0_reset assignment, which is an e_assign
gpout_0_avalon_slave_0_reset <= NOT reset_n;
--gpout_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
gpout_0_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(gpout_0_avalon_slave_0_begins_xfer) = '1'), gpout_0_avalon_slave_0_unreg_firsttransfer, gpout_0_avalon_slave_0_reg_firsttransfer);
--gpout_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
gpout_0_avalon_slave_0_unreg_firsttransfer <= NOT ((gpout_0_avalon_slave_0_slavearbiterlockenable AND gpout_0_avalon_slave_0_any_continuerequest));
--gpout_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
gpout_0_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(gpout_0_avalon_slave_0_begins_xfer) = '1' then
gpout_0_avalon_slave_0_reg_firsttransfer <= gpout_0_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--gpout_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
gpout_0_avalon_slave_0_beginbursttransfer_internal <= gpout_0_avalon_slave_0_begins_xfer;
--gpout_0_avalon_slave_0_write assignment, which is an e_mux
gpout_0_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_gpout_0_avalon_slave_0_from_int_ctrl_0_avalon_master <= A_EXT (Std_Logic_Vector'(A_SRL(int_ctrl_0_avalon_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")) & A_ToStdLogicVector(int_ctrl_0_avalon_master_dbs_address(1)) & A_ToStdLogicVector(std_logic'('0'))), 15);
--gpout_0_avalon_slave_0_address mux, which is an e_mux
gpout_0_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_gpout_0_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000001")), 2);
--d1_gpout_0_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_gpout_0_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_gpout_0_avalon_slave_0_end_xfer <= gpout_0_avalon_slave_0_end_xfer;
end if;
end process;
--gpout_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
gpout_0_avalon_slave_0_waits_for_read <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(gpout_0_avalon_slave_0_in_a_read_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--gpout_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
gpout_0_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= gpout_0_avalon_slave_0_in_a_read_cycle;
--gpout_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
gpout_0_avalon_slave_0_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(gpout_0_avalon_slave_0_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--gpout_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
gpout_0_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= gpout_0_avalon_slave_0_in_a_write_cycle;
wait_for_gpout_0_avalon_slave_0_counter <= std_logic'('0');
--gpout_0_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
gpout_0_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (internal_int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 2);
(int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0_segment_1(1), int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0_segment_1(0), int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0_segment_0(1), int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0_segment_0(0)) <= int_ctrl_0_avalon_master_byteenable;
internal_int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_dbs_address(1)))) = std_logic_vector'("00000000000000000000000000000000"))), int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0_segment_0, int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0_segment_1);
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0;
--synthesis translate_off
--gpout_0/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity int_ctrl_0_avalon_cra_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_cra_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_int_ctrl_0_avalon_cra_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_cra_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_cra_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_cra_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_cra_write : OUT STD_LOGIC;
signal int_ctrl_0_avalon_cra_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_int_ctrl_0_avalon_cra : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra : OUT STD_LOGIC
);
end entity int_ctrl_0_avalon_cra_arbitrator;
architecture europa of int_ctrl_0_avalon_cra_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_int_ctrl_0_avalon_cra : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_cra_allgrants : STD_LOGIC;
signal int_ctrl_0_avalon_cra_allow_new_arb_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_cra_any_bursting_master_saved_grant : STD_LOGIC;
signal int_ctrl_0_avalon_cra_any_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_cra_arb_counter_enable : STD_LOGIC;
signal int_ctrl_0_avalon_cra_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_cra_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_cra_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_cra_beginbursttransfer_internal : STD_LOGIC;
signal int_ctrl_0_avalon_cra_begins_xfer : STD_LOGIC;
signal int_ctrl_0_avalon_cra_end_xfer : STD_LOGIC;
signal int_ctrl_0_avalon_cra_firsttransfer : STD_LOGIC;
signal int_ctrl_0_avalon_cra_grant_vector : STD_LOGIC;
signal int_ctrl_0_avalon_cra_in_a_read_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_cra_in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_cra_master_qreq_vector : STD_LOGIC;
signal int_ctrl_0_avalon_cra_non_bursting_master_requests : STD_LOGIC;
signal int_ctrl_0_avalon_cra_reg_firsttransfer : STD_LOGIC;
signal int_ctrl_0_avalon_cra_slavearbiterlockenable : STD_LOGIC;
signal int_ctrl_0_avalon_cra_slavearbiterlockenable2 : STD_LOGIC;
signal int_ctrl_0_avalon_cra_unreg_firsttransfer : STD_LOGIC;
signal int_ctrl_0_avalon_cra_waits_for_read : STD_LOGIC;
signal int_ctrl_0_avalon_cra_waits_for_write : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra_segment_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra_segment_1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_int_ctrl_0_avalon_cra : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal internal_int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra : STD_LOGIC;
signal shifted_address_to_int_ctrl_0_avalon_cra_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_int_ctrl_0_avalon_cra_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT int_ctrl_0_avalon_cra_end_xfer;
end if;
end process;
int_ctrl_0_avalon_cra_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra);
--assign int_ctrl_0_avalon_cra_readdata_from_sa = int_ctrl_0_avalon_cra_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
int_ctrl_0_avalon_cra_readdata_from_sa <= int_ctrl_0_avalon_cra_readdata;
internal_int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 3) & std_logic_vector'("000")) = std_logic_vector'("100100010010000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--int_ctrl_0_avalon_cra_arb_share_counter set values, which is an e_mux
int_ctrl_0_avalon_cra_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra)) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000001")), 2);
--int_ctrl_0_avalon_cra_non_bursting_master_requests mux, which is an e_mux
int_ctrl_0_avalon_cra_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra;
--int_ctrl_0_avalon_cra_any_bursting_master_saved_grant mux, which is an e_mux
int_ctrl_0_avalon_cra_any_bursting_master_saved_grant <= std_logic'('0');
--int_ctrl_0_avalon_cra_arb_share_counter_next_value assignment, which is an e_assign
int_ctrl_0_avalon_cra_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(int_ctrl_0_avalon_cra_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (int_ctrl_0_avalon_cra_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(int_ctrl_0_avalon_cra_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (int_ctrl_0_avalon_cra_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--int_ctrl_0_avalon_cra_allgrants all slave grants, which is an e_mux
int_ctrl_0_avalon_cra_allgrants <= int_ctrl_0_avalon_cra_grant_vector;
--int_ctrl_0_avalon_cra_end_xfer assignment, which is an e_assign
int_ctrl_0_avalon_cra_end_xfer <= NOT ((int_ctrl_0_avalon_cra_waits_for_read OR int_ctrl_0_avalon_cra_waits_for_write));
--end_xfer_arb_share_counter_term_int_ctrl_0_avalon_cra arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_int_ctrl_0_avalon_cra <= int_ctrl_0_avalon_cra_end_xfer AND (((NOT int_ctrl_0_avalon_cra_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--int_ctrl_0_avalon_cra_arb_share_counter arbitration counter enable, which is an e_assign
int_ctrl_0_avalon_cra_arb_counter_enable <= ((end_xfer_arb_share_counter_term_int_ctrl_0_avalon_cra AND int_ctrl_0_avalon_cra_allgrants)) OR ((end_xfer_arb_share_counter_term_int_ctrl_0_avalon_cra AND NOT int_ctrl_0_avalon_cra_non_bursting_master_requests));
--int_ctrl_0_avalon_cra_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
int_ctrl_0_avalon_cra_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(int_ctrl_0_avalon_cra_arb_counter_enable) = '1' then
int_ctrl_0_avalon_cra_arb_share_counter <= int_ctrl_0_avalon_cra_arb_share_counter_next_value;
end if;
end if;
end process;
--int_ctrl_0_avalon_cra_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
int_ctrl_0_avalon_cra_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((int_ctrl_0_avalon_cra_master_qreq_vector AND end_xfer_arb_share_counter_term_int_ctrl_0_avalon_cra)) OR ((end_xfer_arb_share_counter_term_int_ctrl_0_avalon_cra AND NOT int_ctrl_0_avalon_cra_non_bursting_master_requests)))) = '1' then
int_ctrl_0_avalon_cra_slavearbiterlockenable <= or_reduce(int_ctrl_0_avalon_cra_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master int_ctrl_0/avalon_cra arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= int_ctrl_0_avalon_cra_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--int_ctrl_0_avalon_cra_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
int_ctrl_0_avalon_cra_slavearbiterlockenable2 <= or_reduce(int_ctrl_0_avalon_cra_arb_share_counter_next_value);
--int_ctrl_0/avalon_master int_ctrl_0/avalon_cra arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= int_ctrl_0_avalon_cra_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--int_ctrl_0_avalon_cra_any_continuerequest at least one master continues requesting, which is an e_assign
int_ctrl_0_avalon_cra_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra <= internal_int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra AND NOT (((NOT(or_reduce(internal_int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra))) AND int_ctrl_0_avalon_master_write));
--int_ctrl_0_avalon_cra_writedata mux, which is an e_mux
int_ctrl_0_avalon_cra_writedata <= int_ctrl_0_avalon_master_dbs_write_16;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra <= internal_int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra;
--int_ctrl_0/avalon_master saved-grant int_ctrl_0/avalon_cra, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_int_ctrl_0_avalon_cra <= internal_int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra;
--allow new arb cycle for int_ctrl_0/avalon_cra, which is an e_assign
int_ctrl_0_avalon_cra_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
int_ctrl_0_avalon_cra_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
int_ctrl_0_avalon_cra_master_qreq_vector <= std_logic'('1');
--int_ctrl_0_avalon_cra_firsttransfer first transaction, which is an e_assign
int_ctrl_0_avalon_cra_firsttransfer <= A_WE_StdLogic((std_logic'(int_ctrl_0_avalon_cra_begins_xfer) = '1'), int_ctrl_0_avalon_cra_unreg_firsttransfer, int_ctrl_0_avalon_cra_reg_firsttransfer);
--int_ctrl_0_avalon_cra_unreg_firsttransfer first transaction, which is an e_assign
int_ctrl_0_avalon_cra_unreg_firsttransfer <= NOT ((int_ctrl_0_avalon_cra_slavearbiterlockenable AND int_ctrl_0_avalon_cra_any_continuerequest));
--int_ctrl_0_avalon_cra_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
int_ctrl_0_avalon_cra_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(int_ctrl_0_avalon_cra_begins_xfer) = '1' then
int_ctrl_0_avalon_cra_reg_firsttransfer <= int_ctrl_0_avalon_cra_unreg_firsttransfer;
end if;
end if;
end process;
--int_ctrl_0_avalon_cra_beginbursttransfer_internal begin burst transfer, which is an e_assign
int_ctrl_0_avalon_cra_beginbursttransfer_internal <= int_ctrl_0_avalon_cra_begins_xfer;
--int_ctrl_0_avalon_cra_write assignment, which is an e_mux
int_ctrl_0_avalon_cra_write <= internal_int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra AND int_ctrl_0_avalon_master_write;
shifted_address_to_int_ctrl_0_avalon_cra_from_int_ctrl_0_avalon_master <= A_EXT (Std_Logic_Vector'(A_SRL(int_ctrl_0_avalon_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")) & A_ToStdLogicVector(int_ctrl_0_avalon_master_dbs_address(1)) & A_ToStdLogicVector(std_logic'('0'))), 15);
--int_ctrl_0_avalon_cra_address mux, which is an e_mux
int_ctrl_0_avalon_cra_address <= A_EXT (A_SRL(shifted_address_to_int_ctrl_0_avalon_cra_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000001")), 2);
--d1_int_ctrl_0_avalon_cra_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_int_ctrl_0_avalon_cra_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_int_ctrl_0_avalon_cra_end_xfer <= int_ctrl_0_avalon_cra_end_xfer;
end if;
end process;
--int_ctrl_0_avalon_cra_waits_for_read in a cycle, which is an e_mux
int_ctrl_0_avalon_cra_waits_for_read <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_cra_in_a_read_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--int_ctrl_0_avalon_cra_in_a_read_cycle assignment, which is an e_assign
int_ctrl_0_avalon_cra_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= int_ctrl_0_avalon_cra_in_a_read_cycle;
--int_ctrl_0_avalon_cra_waits_for_write in a cycle, which is an e_mux
int_ctrl_0_avalon_cra_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_cra_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--int_ctrl_0_avalon_cra_in_a_write_cycle assignment, which is an e_assign
int_ctrl_0_avalon_cra_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= int_ctrl_0_avalon_cra_in_a_write_cycle;
wait_for_int_ctrl_0_avalon_cra_counter <= std_logic'('0');
--int_ctrl_0_avalon_cra_byteenable byte enable port mux, which is an e_mux
int_ctrl_0_avalon_cra_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (internal_int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 2);
(int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra_segment_1(1), int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra_segment_1(0), int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra_segment_0(1), int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra_segment_0(0)) <= int_ctrl_0_avalon_master_byteenable;
internal_int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_dbs_address(1)))) = std_logic_vector'("00000000000000000000000000000000"))), int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra_segment_0, int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra_segment_1);
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra <= internal_int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra <= internal_int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra <= internal_int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra <= internal_int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra;
--synthesis translate_off
--int_ctrl_0/avalon_cra enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity int_ctrl_0_avalon_slave_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_slave_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_slave_waitrequest : IN STD_LOGIC;
signal pipeline_bridge_0_m1_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal pipeline_bridge_0_m1_burstcount : IN STD_LOGIC;
signal pipeline_bridge_0_m1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pipeline_bridge_0_m1_chipselect : IN STD_LOGIC;
signal pipeline_bridge_0_m1_dbs_address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal pipeline_bridge_0_m1_dbs_write_32 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pipeline_bridge_0_m1_latency_counter : IN STD_LOGIC;
signal pipeline_bridge_0_m1_read : IN STD_LOGIC;
signal pipeline_bridge_0_m1_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_int_ctrl_0_avalon_slave_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_slave_address : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
signal int_ctrl_0_avalon_slave_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_slave_read : OUT STD_LOGIC;
signal int_ctrl_0_avalon_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_slave_reset : OUT STD_LOGIC;
signal int_ctrl_0_avalon_slave_waitrequest_from_sa : OUT STD_LOGIC;
signal int_ctrl_0_avalon_slave_write : OUT STD_LOGIC;
signal int_ctrl_0_avalon_slave_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave : OUT STD_LOGIC;
signal pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave : OUT STD_LOGIC;
signal pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave : OUT STD_LOGIC;
signal pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave : OUT STD_LOGIC
);
end entity int_ctrl_0_avalon_slave_arbitrator;
architecture europa of int_ctrl_0_avalon_slave_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_int_ctrl_0_avalon_slave : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_slave_allgrants : STD_LOGIC;
signal int_ctrl_0_avalon_slave_allow_new_arb_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_slave_any_bursting_master_saved_grant : STD_LOGIC;
signal int_ctrl_0_avalon_slave_any_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_slave_arb_counter_enable : STD_LOGIC;
signal int_ctrl_0_avalon_slave_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_slave_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_slave_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_slave_beginbursttransfer_internal : STD_LOGIC;
signal int_ctrl_0_avalon_slave_begins_xfer : STD_LOGIC;
signal int_ctrl_0_avalon_slave_end_xfer : STD_LOGIC;
signal int_ctrl_0_avalon_slave_firsttransfer : STD_LOGIC;
signal int_ctrl_0_avalon_slave_grant_vector : STD_LOGIC;
signal int_ctrl_0_avalon_slave_in_a_read_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_slave_in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_slave_master_qreq_vector : STD_LOGIC;
signal int_ctrl_0_avalon_slave_non_bursting_master_requests : STD_LOGIC;
signal int_ctrl_0_avalon_slave_reg_firsttransfer : STD_LOGIC;
signal int_ctrl_0_avalon_slave_slavearbiterlockenable : STD_LOGIC;
signal int_ctrl_0_avalon_slave_slavearbiterlockenable2 : STD_LOGIC;
signal int_ctrl_0_avalon_slave_unreg_firsttransfer : STD_LOGIC;
signal int_ctrl_0_avalon_slave_waits_for_read : STD_LOGIC;
signal int_ctrl_0_avalon_slave_waits_for_write : STD_LOGIC;
signal internal_int_ctrl_0_avalon_slave_waitrequest_from_sa : STD_LOGIC;
signal internal_pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal internal_pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave : STD_LOGIC;
signal internal_pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave : STD_LOGIC;
signal internal_pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave : STD_LOGIC;
signal pipeline_bridge_0_m1_arbiterlock : STD_LOGIC;
signal pipeline_bridge_0_m1_arbiterlock2 : STD_LOGIC;
signal pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pipeline_bridge_0_m1_continuerequest : STD_LOGIC;
signal pipeline_bridge_0_m1_saved_grant_int_ctrl_0_avalon_slave : STD_LOGIC;
signal shifted_address_to_int_ctrl_0_avalon_slave_from_pipeline_bridge_0_m1 : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_int_ctrl_0_avalon_slave_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT int_ctrl_0_avalon_slave_end_xfer;
end if;
end process;
int_ctrl_0_avalon_slave_begins_xfer <= NOT d1_reasons_to_wait AND (internal_pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave);
--assign int_ctrl_0_avalon_slave_readdata_from_sa = int_ctrl_0_avalon_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
int_ctrl_0_avalon_slave_readdata_from_sa <= int_ctrl_0_avalon_slave_readdata;
internal_pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pipeline_bridge_0_m1_chipselect)))));
--assign int_ctrl_0_avalon_slave_waitrequest_from_sa = int_ctrl_0_avalon_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_int_ctrl_0_avalon_slave_waitrequest_from_sa <= int_ctrl_0_avalon_slave_waitrequest;
--int_ctrl_0_avalon_slave_arb_share_counter set values, which is an e_mux
int_ctrl_0_avalon_slave_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave)) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000001")), 2);
--int_ctrl_0_avalon_slave_non_bursting_master_requests mux, which is an e_mux
int_ctrl_0_avalon_slave_non_bursting_master_requests <= internal_pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave;
--int_ctrl_0_avalon_slave_any_bursting_master_saved_grant mux, which is an e_mux
int_ctrl_0_avalon_slave_any_bursting_master_saved_grant <= std_logic'('0');
--int_ctrl_0_avalon_slave_arb_share_counter_next_value assignment, which is an e_assign
int_ctrl_0_avalon_slave_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(int_ctrl_0_avalon_slave_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (int_ctrl_0_avalon_slave_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(int_ctrl_0_avalon_slave_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (int_ctrl_0_avalon_slave_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--int_ctrl_0_avalon_slave_allgrants all slave grants, which is an e_mux
int_ctrl_0_avalon_slave_allgrants <= int_ctrl_0_avalon_slave_grant_vector;
--int_ctrl_0_avalon_slave_end_xfer assignment, which is an e_assign
int_ctrl_0_avalon_slave_end_xfer <= NOT ((int_ctrl_0_avalon_slave_waits_for_read OR int_ctrl_0_avalon_slave_waits_for_write));
--end_xfer_arb_share_counter_term_int_ctrl_0_avalon_slave arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_int_ctrl_0_avalon_slave <= int_ctrl_0_avalon_slave_end_xfer AND (((NOT int_ctrl_0_avalon_slave_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--int_ctrl_0_avalon_slave_arb_share_counter arbitration counter enable, which is an e_assign
int_ctrl_0_avalon_slave_arb_counter_enable <= ((end_xfer_arb_share_counter_term_int_ctrl_0_avalon_slave AND int_ctrl_0_avalon_slave_allgrants)) OR ((end_xfer_arb_share_counter_term_int_ctrl_0_avalon_slave AND NOT int_ctrl_0_avalon_slave_non_bursting_master_requests));
--int_ctrl_0_avalon_slave_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
int_ctrl_0_avalon_slave_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(int_ctrl_0_avalon_slave_arb_counter_enable) = '1' then
int_ctrl_0_avalon_slave_arb_share_counter <= int_ctrl_0_avalon_slave_arb_share_counter_next_value;
end if;
end if;
end process;
--int_ctrl_0_avalon_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
int_ctrl_0_avalon_slave_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((int_ctrl_0_avalon_slave_master_qreq_vector AND end_xfer_arb_share_counter_term_int_ctrl_0_avalon_slave)) OR ((end_xfer_arb_share_counter_term_int_ctrl_0_avalon_slave AND NOT int_ctrl_0_avalon_slave_non_bursting_master_requests)))) = '1' then
int_ctrl_0_avalon_slave_slavearbiterlockenable <= or_reduce(int_ctrl_0_avalon_slave_arb_share_counter_next_value);
end if;
end if;
end process;
--pipeline_bridge_0/m1 int_ctrl_0/avalon_slave arbiterlock, which is an e_assign
pipeline_bridge_0_m1_arbiterlock <= int_ctrl_0_avalon_slave_slavearbiterlockenable AND pipeline_bridge_0_m1_continuerequest;
--int_ctrl_0_avalon_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
int_ctrl_0_avalon_slave_slavearbiterlockenable2 <= or_reduce(int_ctrl_0_avalon_slave_arb_share_counter_next_value);
--pipeline_bridge_0/m1 int_ctrl_0/avalon_slave arbiterlock2, which is an e_assign
pipeline_bridge_0_m1_arbiterlock2 <= int_ctrl_0_avalon_slave_slavearbiterlockenable2 AND pipeline_bridge_0_m1_continuerequest;
--int_ctrl_0_avalon_slave_any_continuerequest at least one master continues requesting, which is an e_assign
int_ctrl_0_avalon_slave_any_continuerequest <= std_logic'('1');
--pipeline_bridge_0_m1_continuerequest continued request, which is an e_assign
pipeline_bridge_0_m1_continuerequest <= std_logic'('1');
internal_pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave <= internal_pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave AND NOT ((((((pipeline_bridge_0_m1_read AND pipeline_bridge_0_m1_chipselect)) AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pipeline_bridge_0_m1_latency_counter))) /= std_logic_vector'("00000000000000000000000000000000")))))) OR (((NOT(or_reduce(internal_pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave))) AND ((pipeline_bridge_0_m1_write AND pipeline_bridge_0_m1_chipselect))))));
--local readdatavalid pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave, which is an e_mux
pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave <= (internal_pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave AND ((pipeline_bridge_0_m1_read AND pipeline_bridge_0_m1_chipselect))) AND NOT int_ctrl_0_avalon_slave_waits_for_read;
--int_ctrl_0_avalon_slave_writedata mux, which is an e_mux
int_ctrl_0_avalon_slave_writedata <= pipeline_bridge_0_m1_dbs_write_32;
--master is always granted when requested
internal_pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave <= internal_pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave;
--pipeline_bridge_0/m1 saved-grant int_ctrl_0/avalon_slave, which is an e_assign
pipeline_bridge_0_m1_saved_grant_int_ctrl_0_avalon_slave <= internal_pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave;
--allow new arb cycle for int_ctrl_0/avalon_slave, which is an e_assign
int_ctrl_0_avalon_slave_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
int_ctrl_0_avalon_slave_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
int_ctrl_0_avalon_slave_master_qreq_vector <= std_logic'('1');
--~int_ctrl_0_avalon_slave_reset assignment, which is an e_assign
int_ctrl_0_avalon_slave_reset <= NOT reset_n;
--int_ctrl_0_avalon_slave_firsttransfer first transaction, which is an e_assign
int_ctrl_0_avalon_slave_firsttransfer <= A_WE_StdLogic((std_logic'(int_ctrl_0_avalon_slave_begins_xfer) = '1'), int_ctrl_0_avalon_slave_unreg_firsttransfer, int_ctrl_0_avalon_slave_reg_firsttransfer);
--int_ctrl_0_avalon_slave_unreg_firsttransfer first transaction, which is an e_assign
int_ctrl_0_avalon_slave_unreg_firsttransfer <= NOT ((int_ctrl_0_avalon_slave_slavearbiterlockenable AND int_ctrl_0_avalon_slave_any_continuerequest));
--int_ctrl_0_avalon_slave_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
int_ctrl_0_avalon_slave_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(int_ctrl_0_avalon_slave_begins_xfer) = '1' then
int_ctrl_0_avalon_slave_reg_firsttransfer <= int_ctrl_0_avalon_slave_unreg_firsttransfer;
end if;
end if;
end process;
--int_ctrl_0_avalon_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
int_ctrl_0_avalon_slave_beginbursttransfer_internal <= int_ctrl_0_avalon_slave_begins_xfer;
--int_ctrl_0_avalon_slave_read assignment, which is an e_mux
int_ctrl_0_avalon_slave_read <= internal_pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave AND ((pipeline_bridge_0_m1_read AND pipeline_bridge_0_m1_chipselect));
--int_ctrl_0_avalon_slave_write assignment, which is an e_mux
int_ctrl_0_avalon_slave_write <= internal_pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave AND ((pipeline_bridge_0_m1_write AND pipeline_bridge_0_m1_chipselect));
shifted_address_to_int_ctrl_0_avalon_slave_from_pipeline_bridge_0_m1 <= A_EXT (Std_Logic_Vector'(A_SRL(pipeline_bridge_0_m1_address_to_slave,std_logic_vector'("00000000000000000000000000000011")) & A_ToStdLogicVector(pipeline_bridge_0_m1_dbs_address(2)) & A_REP(std_logic'('0'), 2)), 15);
--int_ctrl_0_avalon_slave_address mux, which is an e_mux
int_ctrl_0_avalon_slave_address <= A_EXT (A_SRL(shifted_address_to_int_ctrl_0_avalon_slave_from_pipeline_bridge_0_m1,std_logic_vector'("00000000000000000000000000000010")), 13);
--d1_int_ctrl_0_avalon_slave_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_int_ctrl_0_avalon_slave_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_int_ctrl_0_avalon_slave_end_xfer <= int_ctrl_0_avalon_slave_end_xfer;
end if;
end process;
--int_ctrl_0_avalon_slave_waits_for_read in a cycle, which is an e_mux
int_ctrl_0_avalon_slave_waits_for_read <= int_ctrl_0_avalon_slave_in_a_read_cycle AND internal_int_ctrl_0_avalon_slave_waitrequest_from_sa;
--int_ctrl_0_avalon_slave_in_a_read_cycle assignment, which is an e_assign
int_ctrl_0_avalon_slave_in_a_read_cycle <= internal_pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave AND ((pipeline_bridge_0_m1_read AND pipeline_bridge_0_m1_chipselect));
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= int_ctrl_0_avalon_slave_in_a_read_cycle;
--int_ctrl_0_avalon_slave_waits_for_write in a cycle, which is an e_mux
int_ctrl_0_avalon_slave_waits_for_write <= int_ctrl_0_avalon_slave_in_a_write_cycle AND internal_int_ctrl_0_avalon_slave_waitrequest_from_sa;
--int_ctrl_0_avalon_slave_in_a_write_cycle assignment, which is an e_assign
int_ctrl_0_avalon_slave_in_a_write_cycle <= internal_pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave AND ((pipeline_bridge_0_m1_write AND pipeline_bridge_0_m1_chipselect));
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= int_ctrl_0_avalon_slave_in_a_write_cycle;
wait_for_int_ctrl_0_avalon_slave_counter <= std_logic'('0');
--int_ctrl_0_avalon_slave_byteenable byte enable port mux, which is an e_mux
int_ctrl_0_avalon_slave_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (internal_pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
(pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_1(3), pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_1(2), pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_1(1), pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_1(0), pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_0(3), pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_0(2), pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_0(1), pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_0(0)) <= pipeline_bridge_0_m1_byteenable;
internal_pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pipeline_bridge_0_m1_dbs_address(2)))) = std_logic_vector'("00000000000000000000000000000000"))), pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_0, pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave_segment_1);
--vhdl renameroo for output signals
int_ctrl_0_avalon_slave_waitrequest_from_sa <= internal_int_ctrl_0_avalon_slave_waitrequest_from_sa;
--vhdl renameroo for output signals
pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave <= internal_pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave;
--vhdl renameroo for output signals
pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave <= internal_pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave;
--vhdl renameroo for output signals
pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave <= internal_pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave;
--vhdl renameroo for output signals
pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave <= internal_pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave;
--synthesis translate_off
--int_ctrl_0/avalon_slave enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--pipeline_bridge_0/m1 non-zero burstcount assertion, which is an e_process
process (clk)
VARIABLE write_line7 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((internal_pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pipeline_bridge_0_m1_burstcount))) = std_logic_vector'("00000000000000000000000000000000"))))) AND enable_nonzero_assertions)) = '1' then
write(write_line7, now);
write(write_line7, string'(": "));
write(write_line7, string'("pipeline_bridge_0/m1 drove 0 on its 'burstcount' port while accessing slave int_ctrl_0/avalon_slave"));
write(output, write_line7.all);
deallocate (write_line7);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity int_ctrl_0_avalon_master_arbitrator is
port (
-- inputs:
signal ci_bridge_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal d1_ci_bridge_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_dvb_dma_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_dvb_dma_1_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_dvb_ts_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_dvb_ts_1_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_gpout_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_int_ctrl_0_avalon_cra_end_xfer : IN STD_LOGIC;
signal d1_pcie_compiler_0_Control_Register_Access_end_xfer : IN STD_LOGIC;
signal d1_spi_master_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_twi_master_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_twi_master_1_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal gpout_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_cra_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_ci_bridge_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_dma_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_dma_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_ts_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_ts_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_gpout_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_int_ctrl_0_avalon_cra : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_pcie_compiler_0_Control_Register_Access : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_spi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_twi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_twi_master_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_waitrequest_from_sa : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal spi_master_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal spi_master_0_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal twi_master_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_1_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal int_ctrl_0_avalon_master_address_to_slave : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_waitrequest : OUT STD_LOGIC
);
end entity int_ctrl_0_avalon_master_arbitrator;
architecture europa of int_ctrl_0_avalon_master_arbitrator is
signal active_and_waiting_last_time : STD_LOGIC;
signal dbs_16_reg_segment_0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal dbs_count_enable : STD_LOGIC;
signal dbs_counter_overflow : STD_LOGIC;
signal int_ctrl_0_avalon_master_address_last_time : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_last_time : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_increment : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_read_last_time : STD_LOGIC;
signal int_ctrl_0_avalon_master_run : STD_LOGIC;
signal int_ctrl_0_avalon_master_write_last_time : STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata_last_time : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_int_ctrl_0_avalon_master_address_to_slave : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal internal_int_ctrl_0_avalon_master_dbs_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal internal_int_ctrl_0_avalon_master_waitrequest : STD_LOGIC;
signal next_dbs_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal p1_dbs_16_reg_segment_0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal pre_dbs_count_enable : STD_LOGIC;
signal r_0 : STD_LOGIC;
signal r_1 : STD_LOGIC;
signal r_2 : STD_LOGIC;
begin
--r_0 master_run cascaded wait assignment, which is an e_assign
r_0 <= Vector_To_Std_Logic((((((((((((((((((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 OR (((int_ctrl_0_avalon_master_write AND NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0))) AND internal_int_ctrl_0_avalon_master_dbs_address(1)))) OR NOT int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 OR NOT int_ctrl_0_avalon_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 OR NOT int_ctrl_0_avalon_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT dvb_ts_0_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT dvb_ts_0_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT dvb_ts_1_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT dvb_ts_1_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")));
--cascaded wait assignment, which is an e_assign
int_ctrl_0_avalon_master_run <= (r_0 AND r_1) AND r_2;
--r_1 master_run cascaded wait assignment, which is an e_assign
r_1 <= Vector_To_Std_Logic(((((((((((((((((((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 OR (((int_ctrl_0_avalon_master_write AND NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0))) AND internal_int_ctrl_0_avalon_master_dbs_address(1)))) OR NOT int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 OR NOT int_ctrl_0_avalon_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 OR NOT int_ctrl_0_avalon_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra OR (((int_ctrl_0_avalon_master_write AND NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra))) AND internal_int_ctrl_0_avalon_master_dbs_address(1)))) OR NOT int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra OR NOT int_ctrl_0_avalon_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra OR NOT int_ctrl_0_avalon_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT pcie_compiler_0_Control_Register_Access_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access OR NOT ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT pcie_compiler_0_Control_Register_Access_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")));
--r_2 master_run cascaded wait assignment, which is an e_assign
r_2 <= Vector_To_Std_Logic((((((((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 OR (((int_ctrl_0_avalon_master_write AND NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0))) AND internal_int_ctrl_0_avalon_master_dbs_address(1)))) OR NOT int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 OR NOT int_ctrl_0_avalon_master_read)))) OR ((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT spi_master_0_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 OR NOT int_ctrl_0_avalon_master_write)))) OR ((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT spi_master_0_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 OR (((int_ctrl_0_avalon_master_write AND NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0))) AND internal_int_ctrl_0_avalon_master_dbs_address(1)))) OR NOT int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 OR NOT int_ctrl_0_avalon_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 OR NOT int_ctrl_0_avalon_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 OR (((int_ctrl_0_avalon_master_write AND NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0))) AND internal_int_ctrl_0_avalon_master_dbs_address(1)))) OR NOT int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 OR NOT int_ctrl_0_avalon_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 OR NOT int_ctrl_0_avalon_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))))))));
--optimize select-logic by passing only those address bits which matter.
internal_int_ctrl_0_avalon_master_address_to_slave <= int_ctrl_0_avalon_master_address(14 DOWNTO 0);
--pre dbs count enable, which is an e_mux
pre_dbs_count_enable <= Vector_To_Std_Logic(((((((((((((((((((((((NOT std_logic_vector'("00000000000000000000000000000000")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0))))))) OR ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")))) OR ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")))) OR (((((NOT std_logic_vector'("00000000000000000000000000000000")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0)))))))) OR ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")))) OR ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")))) OR (((((NOT std_logic_vector'("00000000000000000000000000000000")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra)))))))) OR ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra AND int_ctrl_0_avalon_master_read)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")))) OR ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra AND int_ctrl_0_avalon_master_write)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")))) OR (((((NOT std_logic_vector'("00000000000000000000000000000000")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0)))))))) OR (((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT spi_master_0_avalon_slave_0_waitrequest_from_sa)))))) OR (((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT spi_master_0_avalon_slave_0_waitrequest_from_sa)))))) OR (((((NOT std_logic_vector'("00000000000000000000000000000000")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0)))))))) OR ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")))) OR ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")))) OR (((((NOT std_logic_vector'("00000000000000000000000000000000")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_write)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT(or_reduce(int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0)))))))) OR ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 AND int_ctrl_0_avalon_master_read)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")))) OR ((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 AND int_ctrl_0_avalon_master_write)))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")))));
--input to dbs-16 stored 0, which is an e_mux
p1_dbs_16_reg_segment_0 <= A_WE_StdLogicVector((std_logic'((int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0)) = '1'), ci_bridge_0_avalon_slave_0_readdata_from_sa, A_WE_StdLogicVector((std_logic'((int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0)) = '1'), gpout_0_avalon_slave_0_readdata_from_sa, A_WE_StdLogicVector((std_logic'((int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra)) = '1'), int_ctrl_0_avalon_cra_readdata_from_sa, A_WE_StdLogicVector((std_logic'((int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0)) = '1'), spi_master_0_avalon_slave_0_readdata_from_sa, A_WE_StdLogicVector((std_logic'((int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0)) = '1'), twi_master_0_avalon_slave_0_readdata_from_sa, twi_master_1_avalon_slave_0_readdata_from_sa)))));
--dbs register for dbs-16 segment 0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dbs_16_reg_segment_0 <= std_logic_vector'("0000000000000000");
elsif clk'event and clk = '1' then
if std_logic'((dbs_count_enable AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_int_ctrl_0_avalon_master_dbs_address(1))))) = std_logic_vector'("00000000000000000000000000000000")))))) = '1' then
dbs_16_reg_segment_0 <= p1_dbs_16_reg_segment_0;
end if;
end if;
end process;
--int_ctrl_0/avalon_master readdata mux, which is an e_mux
int_ctrl_0_avalon_master_readdata <= (((((((((((((((A_REP(NOT int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0, 32) OR Std_Logic_Vector'(ci_bridge_0_avalon_slave_0_readdata_from_sa(15 DOWNTO 0) & dbs_16_reg_segment_0))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0, 32) OR dvb_dma_0_avalon_slave_0_readdata_from_sa))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0, 32) OR dvb_dma_1_avalon_slave_0_readdata_from_sa))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0, 32) OR dvb_ts_0_avalon_slave_0_readdata_from_sa))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0, 32) OR dvb_ts_1_avalon_slave_0_readdata_from_sa))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0, 32) OR fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0, 32) OR fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0, 32) OR fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0, 32) OR fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0, 32) OR Std_Logic_Vector'(gpout_0_avalon_slave_0_readdata_from_sa(15 DOWNTO 0) & dbs_16_reg_segment_0)))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra, 32) OR Std_Logic_Vector'(int_ctrl_0_avalon_cra_readdata_from_sa(15 DOWNTO 0) & dbs_16_reg_segment_0)))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access, 32) OR pcie_compiler_0_Control_Register_Access_readdata_from_sa))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0, 32) OR Std_Logic_Vector'(spi_master_0_avalon_slave_0_readdata_from_sa(15 DOWNTO 0) & dbs_16_reg_segment_0)))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0, 32) OR Std_Logic_Vector'(twi_master_0_avalon_slave_0_readdata_from_sa(15 DOWNTO 0) & dbs_16_reg_segment_0)))) AND ((A_REP(NOT int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0, 32) OR Std_Logic_Vector'(twi_master_1_avalon_slave_0_readdata_from_sa(15 DOWNTO 0) & dbs_16_reg_segment_0)));
--mux write dbs 1, which is an e_mux
int_ctrl_0_avalon_master_dbs_write_16 <= A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_dbs_address(1))) = '1'), int_ctrl_0_avalon_master_writedata(31 DOWNTO 16), A_WE_StdLogicVector((std_logic'((NOT (internal_int_ctrl_0_avalon_master_dbs_address(1)))) = '1'), int_ctrl_0_avalon_master_writedata(15 DOWNTO 0), A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_dbs_address(1))) = '1'), int_ctrl_0_avalon_master_writedata(31 DOWNTO 16), A_WE_StdLogicVector((std_logic'((NOT (internal_int_ctrl_0_avalon_master_dbs_address(1)))) = '1'), int_ctrl_0_avalon_master_writedata(15 DOWNTO 0), A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_dbs_address(1))) = '1'), int_ctrl_0_avalon_master_writedata(31 DOWNTO 16), A_WE_StdLogicVector((std_logic'((NOT (internal_int_ctrl_0_avalon_master_dbs_address(1)))) = '1'), int_ctrl_0_avalon_master_writedata(15 DOWNTO 0), A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_dbs_address(1))) = '1'), int_ctrl_0_avalon_master_writedata(31 DOWNTO 16), A_WE_StdLogicVector((std_logic'((NOT (internal_int_ctrl_0_avalon_master_dbs_address(1)))) = '1'), int_ctrl_0_avalon_master_writedata(15 DOWNTO 0), A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_dbs_address(1))) = '1'), int_ctrl_0_avalon_master_writedata(31 DOWNTO 16), A_WE_StdLogicVector((std_logic'((NOT (internal_int_ctrl_0_avalon_master_dbs_address(1)))) = '1'), int_ctrl_0_avalon_master_writedata(15 DOWNTO 0), A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_dbs_address(1))) = '1'), int_ctrl_0_avalon_master_writedata(31 DOWNTO 16), int_ctrl_0_avalon_master_writedata(15 DOWNTO 0))))))))))));
--actual waitrequest port, which is an e_assign
internal_int_ctrl_0_avalon_master_waitrequest <= NOT int_ctrl_0_avalon_master_run;
--dbs count increment, which is an e_mux
int_ctrl_0_avalon_master_dbs_increment <= A_EXT (A_WE_StdLogicVector((std_logic'((int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0)) = '1'), std_logic_vector'("00000000000000000000000000000010"), A_WE_StdLogicVector((std_logic'((int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0)) = '1'), std_logic_vector'("00000000000000000000000000000010"), A_WE_StdLogicVector((std_logic'((int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra)) = '1'), std_logic_vector'("00000000000000000000000000000010"), A_WE_StdLogicVector((std_logic'((int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0)) = '1'), std_logic_vector'("00000000000000000000000000000010"), A_WE_StdLogicVector((std_logic'((int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0)) = '1'), std_logic_vector'("00000000000000000000000000000010"), A_WE_StdLogicVector((std_logic'((int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0)) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000000"))))))), 2);
--dbs counter overflow, which is an e_assign
dbs_counter_overflow <= internal_int_ctrl_0_avalon_master_dbs_address(1) AND NOT((next_dbs_address(1)));
--next master address, which is an e_assign
next_dbs_address <= A_EXT (((std_logic_vector'("0") & (internal_int_ctrl_0_avalon_master_dbs_address)) + (std_logic_vector'("0") & (int_ctrl_0_avalon_master_dbs_increment))), 2);
--dbs count enable, which is an e_mux
dbs_count_enable <= pre_dbs_count_enable;
--dbs counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
internal_int_ctrl_0_avalon_master_dbs_address <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(dbs_count_enable) = '1' then
internal_int_ctrl_0_avalon_master_dbs_address <= next_dbs_address;
end if;
end if;
end process;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_address_to_slave <= internal_int_ctrl_0_avalon_master_address_to_slave;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_dbs_address <= internal_int_ctrl_0_avalon_master_dbs_address;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_waitrequest <= internal_int_ctrl_0_avalon_master_waitrequest;
--synthesis translate_off
--int_ctrl_0_avalon_master_address check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
int_ctrl_0_avalon_master_address_last_time <= std_logic_vector'("000000000000000");
elsif clk'event and clk = '1' then
int_ctrl_0_avalon_master_address_last_time <= int_ctrl_0_avalon_master_address;
end if;
end process;
--int_ctrl_0/avalon_master waited last time, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
active_and_waiting_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
active_and_waiting_last_time <= internal_int_ctrl_0_avalon_master_waitrequest AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
end if;
end process;
--int_ctrl_0_avalon_master_address matches last port_name, which is an e_process
process (clk)
VARIABLE write_line8 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((int_ctrl_0_avalon_master_address /= int_ctrl_0_avalon_master_address_last_time))))) = '1' then
write(write_line8, now);
write(write_line8, string'(": "));
write(write_line8, string'("int_ctrl_0_avalon_master_address did not heed wait!!!"));
write(output, write_line8.all);
deallocate (write_line8);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--int_ctrl_0_avalon_master_byteenable check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
int_ctrl_0_avalon_master_byteenable_last_time <= std_logic_vector'("0000");
elsif clk'event and clk = '1' then
int_ctrl_0_avalon_master_byteenable_last_time <= int_ctrl_0_avalon_master_byteenable;
end if;
end process;
--int_ctrl_0_avalon_master_byteenable matches last port_name, which is an e_process
process (clk)
VARIABLE write_line9 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((int_ctrl_0_avalon_master_byteenable /= int_ctrl_0_avalon_master_byteenable_last_time))))) = '1' then
write(write_line9, now);
write(write_line9, string'(": "));
write(write_line9, string'("int_ctrl_0_avalon_master_byteenable did not heed wait!!!"));
write(output, write_line9.all);
deallocate (write_line9);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--int_ctrl_0_avalon_master_read check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
int_ctrl_0_avalon_master_read_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
int_ctrl_0_avalon_master_read_last_time <= int_ctrl_0_avalon_master_read;
end if;
end process;
--int_ctrl_0_avalon_master_read matches last port_name, which is an e_process
process (clk)
VARIABLE write_line10 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(int_ctrl_0_avalon_master_read) /= std_logic'(int_ctrl_0_avalon_master_read_last_time)))))) = '1' then
write(write_line10, now);
write(write_line10, string'(": "));
write(write_line10, string'("int_ctrl_0_avalon_master_read did not heed wait!!!"));
write(output, write_line10.all);
deallocate (write_line10);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--int_ctrl_0_avalon_master_write check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
int_ctrl_0_avalon_master_write_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
int_ctrl_0_avalon_master_write_last_time <= int_ctrl_0_avalon_master_write;
end if;
end process;
--int_ctrl_0_avalon_master_write matches last port_name, which is an e_process
process (clk)
VARIABLE write_line11 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(int_ctrl_0_avalon_master_write) /= std_logic'(int_ctrl_0_avalon_master_write_last_time)))))) = '1' then
write(write_line11, now);
write(write_line11, string'(": "));
write(write_line11, string'("int_ctrl_0_avalon_master_write did not heed wait!!!"));
write(output, write_line11.all);
deallocate (write_line11);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--int_ctrl_0_avalon_master_writedata check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
int_ctrl_0_avalon_master_writedata_last_time <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
int_ctrl_0_avalon_master_writedata_last_time <= int_ctrl_0_avalon_master_writedata;
end if;
end process;
--int_ctrl_0_avalon_master_writedata matches last port_name, which is an e_process
process (clk)
VARIABLE write_line12 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((active_and_waiting_last_time AND to_std_logic(((int_ctrl_0_avalon_master_writedata /= int_ctrl_0_avalon_master_writedata_last_time)))) AND int_ctrl_0_avalon_master_write)) = '1' then
write(write_line12, now);
write(write_line12, string'(": "));
write(write_line12, string'("int_ctrl_0_avalon_master_writedata did not heed wait!!!"));
write(output, write_line12.all);
deallocate (write_line12);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pcie_compiler_0_Control_Register_Access_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_pcie_compiler_0_Control_Register_Access_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_pcie_compiler_0_Control_Register_Access : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access : OUT STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_address : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_chipselect : OUT STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_read : OUT STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_waitrequest_from_sa : OUT STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_write : OUT STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity pcie_compiler_0_Control_Register_Access_arbitrator;
architecture europa of pcie_compiler_0_Control_Register_Access_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_pcie_compiler_0_Control_Register_Access : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_pcie_compiler_0_Control_Register_Access : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access : STD_LOGIC;
signal internal_pcie_compiler_0_Control_Register_Access_waitrequest_from_sa : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_allgrants : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_allow_new_arb_cycle : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_any_bursting_master_saved_grant : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_any_continuerequest : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_arb_counter_enable : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_beginbursttransfer_internal : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_begins_xfer : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_end_xfer : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_firsttransfer : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_grant_vector : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_in_a_read_cycle : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_in_a_write_cycle : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_master_qreq_vector : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_non_bursting_master_requests : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_reg_firsttransfer : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_slavearbiterlockenable : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_slavearbiterlockenable2 : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_unreg_firsttransfer : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_waits_for_read : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_waits_for_write : STD_LOGIC;
signal shifted_address_to_pcie_compiler_0_Control_Register_Access_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal wait_for_pcie_compiler_0_Control_Register_Access_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT pcie_compiler_0_Control_Register_Access_end_xfer;
end if;
end process;
pcie_compiler_0_Control_Register_Access_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access);
--assign pcie_compiler_0_Control_Register_Access_readdata_from_sa = pcie_compiler_0_Control_Register_Access_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
pcie_compiler_0_Control_Register_Access_readdata_from_sa <= pcie_compiler_0_Control_Register_Access_readdata;
internal_int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access <= to_std_logic(((Std_Logic_Vector'(A_ToStdLogicVector(int_ctrl_0_avalon_master_address_to_slave(14)) & std_logic_vector'("00000000000000")) = std_logic_vector'("000000000000000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--assign pcie_compiler_0_Control_Register_Access_waitrequest_from_sa = pcie_compiler_0_Control_Register_Access_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_pcie_compiler_0_Control_Register_Access_waitrequest_from_sa <= pcie_compiler_0_Control_Register_Access_waitrequest;
--pcie_compiler_0_Control_Register_Access_arb_share_counter set values, which is an e_mux
pcie_compiler_0_Control_Register_Access_arb_share_set_values <= std_logic_vector'("01");
--pcie_compiler_0_Control_Register_Access_non_bursting_master_requests mux, which is an e_mux
pcie_compiler_0_Control_Register_Access_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access;
--pcie_compiler_0_Control_Register_Access_any_bursting_master_saved_grant mux, which is an e_mux
pcie_compiler_0_Control_Register_Access_any_bursting_master_saved_grant <= std_logic'('0');
--pcie_compiler_0_Control_Register_Access_arb_share_counter_next_value assignment, which is an e_assign
pcie_compiler_0_Control_Register_Access_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(pcie_compiler_0_Control_Register_Access_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (pcie_compiler_0_Control_Register_Access_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(pcie_compiler_0_Control_Register_Access_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (pcie_compiler_0_Control_Register_Access_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--pcie_compiler_0_Control_Register_Access_allgrants all slave grants, which is an e_mux
pcie_compiler_0_Control_Register_Access_allgrants <= pcie_compiler_0_Control_Register_Access_grant_vector;
--pcie_compiler_0_Control_Register_Access_end_xfer assignment, which is an e_assign
pcie_compiler_0_Control_Register_Access_end_xfer <= NOT ((pcie_compiler_0_Control_Register_Access_waits_for_read OR pcie_compiler_0_Control_Register_Access_waits_for_write));
--end_xfer_arb_share_counter_term_pcie_compiler_0_Control_Register_Access arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_pcie_compiler_0_Control_Register_Access <= pcie_compiler_0_Control_Register_Access_end_xfer AND (((NOT pcie_compiler_0_Control_Register_Access_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--pcie_compiler_0_Control_Register_Access_arb_share_counter arbitration counter enable, which is an e_assign
pcie_compiler_0_Control_Register_Access_arb_counter_enable <= ((end_xfer_arb_share_counter_term_pcie_compiler_0_Control_Register_Access AND pcie_compiler_0_Control_Register_Access_allgrants)) OR ((end_xfer_arb_share_counter_term_pcie_compiler_0_Control_Register_Access AND NOT pcie_compiler_0_Control_Register_Access_non_bursting_master_requests));
--pcie_compiler_0_Control_Register_Access_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Control_Register_Access_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(pcie_compiler_0_Control_Register_Access_arb_counter_enable) = '1' then
pcie_compiler_0_Control_Register_Access_arb_share_counter <= pcie_compiler_0_Control_Register_Access_arb_share_counter_next_value;
end if;
end if;
end process;
--pcie_compiler_0_Control_Register_Access_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Control_Register_Access_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((pcie_compiler_0_Control_Register_Access_master_qreq_vector AND end_xfer_arb_share_counter_term_pcie_compiler_0_Control_Register_Access)) OR ((end_xfer_arb_share_counter_term_pcie_compiler_0_Control_Register_Access AND NOT pcie_compiler_0_Control_Register_Access_non_bursting_master_requests)))) = '1' then
pcie_compiler_0_Control_Register_Access_slavearbiterlockenable <= or_reduce(pcie_compiler_0_Control_Register_Access_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master pcie_compiler_0/Control_Register_Access arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= pcie_compiler_0_Control_Register_Access_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--pcie_compiler_0_Control_Register_Access_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
pcie_compiler_0_Control_Register_Access_slavearbiterlockenable2 <= or_reduce(pcie_compiler_0_Control_Register_Access_arb_share_counter_next_value);
--int_ctrl_0/avalon_master pcie_compiler_0/Control_Register_Access arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= pcie_compiler_0_Control_Register_Access_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--pcie_compiler_0_Control_Register_Access_any_continuerequest at least one master continues requesting, which is an e_assign
pcie_compiler_0_Control_Register_Access_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access <= internal_int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access;
--pcie_compiler_0_Control_Register_Access_writedata mux, which is an e_mux
pcie_compiler_0_Control_Register_Access_writedata <= int_ctrl_0_avalon_master_writedata;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access <= internal_int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access;
--int_ctrl_0/avalon_master saved-grant pcie_compiler_0/Control_Register_Access, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_pcie_compiler_0_Control_Register_Access <= internal_int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access;
--allow new arb cycle for pcie_compiler_0/Control_Register_Access, which is an e_assign
pcie_compiler_0_Control_Register_Access_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
pcie_compiler_0_Control_Register_Access_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
pcie_compiler_0_Control_Register_Access_master_qreq_vector <= std_logic'('1');
pcie_compiler_0_Control_Register_Access_chipselect <= internal_int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access;
--pcie_compiler_0_Control_Register_Access_firsttransfer first transaction, which is an e_assign
pcie_compiler_0_Control_Register_Access_firsttransfer <= A_WE_StdLogic((std_logic'(pcie_compiler_0_Control_Register_Access_begins_xfer) = '1'), pcie_compiler_0_Control_Register_Access_unreg_firsttransfer, pcie_compiler_0_Control_Register_Access_reg_firsttransfer);
--pcie_compiler_0_Control_Register_Access_unreg_firsttransfer first transaction, which is an e_assign
pcie_compiler_0_Control_Register_Access_unreg_firsttransfer <= NOT ((pcie_compiler_0_Control_Register_Access_slavearbiterlockenable AND pcie_compiler_0_Control_Register_Access_any_continuerequest));
--pcie_compiler_0_Control_Register_Access_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Control_Register_Access_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(pcie_compiler_0_Control_Register_Access_begins_xfer) = '1' then
pcie_compiler_0_Control_Register_Access_reg_firsttransfer <= pcie_compiler_0_Control_Register_Access_unreg_firsttransfer;
end if;
end if;
end process;
--pcie_compiler_0_Control_Register_Access_beginbursttransfer_internal begin burst transfer, which is an e_assign
pcie_compiler_0_Control_Register_Access_beginbursttransfer_internal <= pcie_compiler_0_Control_Register_Access_begins_xfer;
--pcie_compiler_0_Control_Register_Access_read assignment, which is an e_mux
pcie_compiler_0_Control_Register_Access_read <= internal_int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access AND int_ctrl_0_avalon_master_read;
--pcie_compiler_0_Control_Register_Access_write assignment, which is an e_mux
pcie_compiler_0_Control_Register_Access_write <= internal_int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access AND int_ctrl_0_avalon_master_write;
shifted_address_to_pcie_compiler_0_Control_Register_Access_from_int_ctrl_0_avalon_master <= int_ctrl_0_avalon_master_address_to_slave;
--pcie_compiler_0_Control_Register_Access_address mux, which is an e_mux
pcie_compiler_0_Control_Register_Access_address <= A_EXT (A_SRL(shifted_address_to_pcie_compiler_0_Control_Register_Access_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000010")), 12);
--d1_pcie_compiler_0_Control_Register_Access_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_pcie_compiler_0_Control_Register_Access_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_pcie_compiler_0_Control_Register_Access_end_xfer <= pcie_compiler_0_Control_Register_Access_end_xfer;
end if;
end process;
--pcie_compiler_0_Control_Register_Access_waits_for_read in a cycle, which is an e_mux
pcie_compiler_0_Control_Register_Access_waits_for_read <= pcie_compiler_0_Control_Register_Access_in_a_read_cycle AND internal_pcie_compiler_0_Control_Register_Access_waitrequest_from_sa;
--pcie_compiler_0_Control_Register_Access_in_a_read_cycle assignment, which is an e_assign
pcie_compiler_0_Control_Register_Access_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= pcie_compiler_0_Control_Register_Access_in_a_read_cycle;
--pcie_compiler_0_Control_Register_Access_waits_for_write in a cycle, which is an e_mux
pcie_compiler_0_Control_Register_Access_waits_for_write <= pcie_compiler_0_Control_Register_Access_in_a_write_cycle AND internal_pcie_compiler_0_Control_Register_Access_waitrequest_from_sa;
--pcie_compiler_0_Control_Register_Access_in_a_write_cycle assignment, which is an e_assign
pcie_compiler_0_Control_Register_Access_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= pcie_compiler_0_Control_Register_Access_in_a_write_cycle;
wait_for_pcie_compiler_0_Control_Register_Access_counter <= std_logic'('0');
--pcie_compiler_0_Control_Register_Access_byteenable byte enable port mux, which is an e_mux
pcie_compiler_0_Control_Register_Access_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (int_ctrl_0_avalon_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access <= internal_int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access <= internal_int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access <= internal_int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access;
--vhdl renameroo for output signals
pcie_compiler_0_Control_Register_Access_waitrequest_from_sa <= internal_pcie_compiler_0_Control_Register_Access_waitrequest_from_sa;
--synthesis translate_off
--pcie_compiler_0/Control_Register_Access enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity pcie_compiler_0_Tx_Interface_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dma_arbiter_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (30 DOWNTO 0);
signal dma_arbiter_0_avalon_master_burstcount : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma_arbiter_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma_arbiter_0_avalon_master_write : IN STD_LOGIC;
signal dma_arbiter_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_readdatavalid : IN STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_pcie_compiler_0_Tx_Interface_end_xfer : OUT STD_LOGIC;
signal dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface : OUT STD_LOGIC;
signal dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface : OUT STD_LOGIC;
signal dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_address : OUT STD_LOGIC_VECTOR (27 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_burstcount : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_chipselect : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_read : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_readdata_from_sa : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_readdatavalid_from_sa : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_waitrequest_from_sa : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_write : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
end entity pcie_compiler_0_Tx_Interface_arbitrator;
architecture europa of pcie_compiler_0_Tx_Interface_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal dma_arbiter_0_avalon_master_arbiterlock : STD_LOGIC;
signal dma_arbiter_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal dma_arbiter_0_avalon_master_continuerequest : STD_LOGIC;
signal dma_arbiter_0_saved_grant_pcie_compiler_0_Tx_Interface : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_pcie_compiler_0_Tx_Interface : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal internal_dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface : STD_LOGIC;
signal internal_dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface : STD_LOGIC;
signal internal_dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface : STD_LOGIC;
signal internal_pcie_compiler_0_Tx_Interface_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal internal_pcie_compiler_0_Tx_Interface_read : STD_LOGIC;
signal internal_pcie_compiler_0_Tx_Interface_waitrequest_from_sa : STD_LOGIC;
signal internal_pcie_compiler_0_Tx_Interface_write : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_allgrants : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_allow_new_arb_cycle : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_any_bursting_master_saved_grant : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_any_continuerequest : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_arb_counter_enable : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_arb_share_counter : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_arb_share_counter_next_value : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_arb_share_set_values : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_bbt_burstcounter : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_beginbursttransfer_internal : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_begins_xfer : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_end_xfer : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_firsttransfer : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_grant_vector : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_in_a_read_cycle : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_in_a_write_cycle : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_master_qreq_vector : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_next_bbt_burstcount : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_non_bursting_master_requests : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_reg_firsttransfer : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_slavearbiterlockenable : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_slavearbiterlockenable2 : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_unreg_firsttransfer : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_waits_for_read : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_waits_for_write : STD_LOGIC;
signal shifted_address_to_pcie_compiler_0_Tx_Interface_from_dma_arbiter_0_avalon_master : STD_LOGIC_VECTOR (30 DOWNTO 0);
signal wait_for_pcie_compiler_0_Tx_Interface_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT pcie_compiler_0_Tx_Interface_end_xfer;
end if;
end process;
pcie_compiler_0_Tx_Interface_begins_xfer <= NOT d1_reasons_to_wait AND (internal_dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface);
--assign pcie_compiler_0_Tx_Interface_readdata_from_sa = pcie_compiler_0_Tx_Interface_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
pcie_compiler_0_Tx_Interface_readdata_from_sa <= pcie_compiler_0_Tx_Interface_readdata;
internal_dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface <= Vector_To_Std_Logic(((((std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((dma_arbiter_0_avalon_master_write)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dma_arbiter_0_avalon_master_write)))));
--assign pcie_compiler_0_Tx_Interface_waitrequest_from_sa = pcie_compiler_0_Tx_Interface_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_pcie_compiler_0_Tx_Interface_waitrequest_from_sa <= pcie_compiler_0_Tx_Interface_waitrequest;
--pcie_compiler_0_Tx_Interface_arb_share_counter set values, which is an e_mux
pcie_compiler_0_Tx_Interface_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface)) = '1'), (std_logic_vector'("0000000000000000000000000") & (dma_arbiter_0_avalon_master_burstcount)), std_logic_vector'("00000000000000000000000000000001")), 7);
--pcie_compiler_0_Tx_Interface_non_bursting_master_requests mux, which is an e_mux
pcie_compiler_0_Tx_Interface_non_bursting_master_requests <= std_logic'('0');
--pcie_compiler_0_Tx_Interface_any_bursting_master_saved_grant mux, which is an e_mux
pcie_compiler_0_Tx_Interface_any_bursting_master_saved_grant <= dma_arbiter_0_saved_grant_pcie_compiler_0_Tx_Interface;
--pcie_compiler_0_Tx_Interface_arb_share_counter_next_value assignment, which is an e_assign
pcie_compiler_0_Tx_Interface_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(pcie_compiler_0_Tx_Interface_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000") & (pcie_compiler_0_Tx_Interface_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(pcie_compiler_0_Tx_Interface_arb_share_counter)) = '1'), (((std_logic_vector'("00000000000000000000000000") & (pcie_compiler_0_Tx_Interface_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 7);
--pcie_compiler_0_Tx_Interface_allgrants all slave grants, which is an e_mux
pcie_compiler_0_Tx_Interface_allgrants <= pcie_compiler_0_Tx_Interface_grant_vector;
--pcie_compiler_0_Tx_Interface_end_xfer assignment, which is an e_assign
pcie_compiler_0_Tx_Interface_end_xfer <= NOT ((pcie_compiler_0_Tx_Interface_waits_for_read OR pcie_compiler_0_Tx_Interface_waits_for_write));
--end_xfer_arb_share_counter_term_pcie_compiler_0_Tx_Interface arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_pcie_compiler_0_Tx_Interface <= pcie_compiler_0_Tx_Interface_end_xfer AND (((NOT pcie_compiler_0_Tx_Interface_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--pcie_compiler_0_Tx_Interface_arb_share_counter arbitration counter enable, which is an e_assign
pcie_compiler_0_Tx_Interface_arb_counter_enable <= ((end_xfer_arb_share_counter_term_pcie_compiler_0_Tx_Interface AND pcie_compiler_0_Tx_Interface_allgrants)) OR ((end_xfer_arb_share_counter_term_pcie_compiler_0_Tx_Interface AND NOT pcie_compiler_0_Tx_Interface_non_bursting_master_requests));
--pcie_compiler_0_Tx_Interface_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Tx_Interface_arb_share_counter <= std_logic_vector'("0000000");
elsif clk'event and clk = '1' then
if std_logic'(pcie_compiler_0_Tx_Interface_arb_counter_enable) = '1' then
pcie_compiler_0_Tx_Interface_arb_share_counter <= pcie_compiler_0_Tx_Interface_arb_share_counter_next_value;
end if;
end if;
end process;
--pcie_compiler_0_Tx_Interface_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Tx_Interface_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((pcie_compiler_0_Tx_Interface_master_qreq_vector AND end_xfer_arb_share_counter_term_pcie_compiler_0_Tx_Interface)) OR ((end_xfer_arb_share_counter_term_pcie_compiler_0_Tx_Interface AND NOT pcie_compiler_0_Tx_Interface_non_bursting_master_requests)))) = '1' then
pcie_compiler_0_Tx_Interface_slavearbiterlockenable <= or_reduce(pcie_compiler_0_Tx_Interface_arb_share_counter_next_value);
end if;
end if;
end process;
--dma_arbiter_0/avalon_master pcie_compiler_0/Tx_Interface arbiterlock, which is an e_assign
dma_arbiter_0_avalon_master_arbiterlock <= pcie_compiler_0_Tx_Interface_slavearbiterlockenable AND dma_arbiter_0_avalon_master_continuerequest;
--pcie_compiler_0_Tx_Interface_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
pcie_compiler_0_Tx_Interface_slavearbiterlockenable2 <= or_reduce(pcie_compiler_0_Tx_Interface_arb_share_counter_next_value);
--dma_arbiter_0/avalon_master pcie_compiler_0/Tx_Interface arbiterlock2, which is an e_assign
dma_arbiter_0_avalon_master_arbiterlock2 <= pcie_compiler_0_Tx_Interface_slavearbiterlockenable2 AND dma_arbiter_0_avalon_master_continuerequest;
--pcie_compiler_0_Tx_Interface_any_continuerequest at least one master continues requesting, which is an e_assign
pcie_compiler_0_Tx_Interface_any_continuerequest <= std_logic'('1');
--dma_arbiter_0_avalon_master_continuerequest continued request, which is an e_assign
dma_arbiter_0_avalon_master_continuerequest <= std_logic'('1');
internal_dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface <= internal_dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface;
--pcie_compiler_0_Tx_Interface_writedata mux, which is an e_mux
pcie_compiler_0_Tx_Interface_writedata <= dma_arbiter_0_avalon_master_writedata;
--master is always granted when requested
internal_dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface <= internal_dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface;
--dma_arbiter_0/avalon_master saved-grant pcie_compiler_0/Tx_Interface, which is an e_assign
dma_arbiter_0_saved_grant_pcie_compiler_0_Tx_Interface <= internal_dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface;
--allow new arb cycle for pcie_compiler_0/Tx_Interface, which is an e_assign
pcie_compiler_0_Tx_Interface_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
pcie_compiler_0_Tx_Interface_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
pcie_compiler_0_Tx_Interface_master_qreq_vector <= std_logic'('1');
pcie_compiler_0_Tx_Interface_chipselect <= internal_dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface;
--pcie_compiler_0_Tx_Interface_firsttransfer first transaction, which is an e_assign
pcie_compiler_0_Tx_Interface_firsttransfer <= A_WE_StdLogic((std_logic'(pcie_compiler_0_Tx_Interface_begins_xfer) = '1'), pcie_compiler_0_Tx_Interface_unreg_firsttransfer, pcie_compiler_0_Tx_Interface_reg_firsttransfer);
--pcie_compiler_0_Tx_Interface_unreg_firsttransfer first transaction, which is an e_assign
pcie_compiler_0_Tx_Interface_unreg_firsttransfer <= NOT ((pcie_compiler_0_Tx_Interface_slavearbiterlockenable AND pcie_compiler_0_Tx_Interface_any_continuerequest));
--pcie_compiler_0_Tx_Interface_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Tx_Interface_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(pcie_compiler_0_Tx_Interface_begins_xfer) = '1' then
pcie_compiler_0_Tx_Interface_reg_firsttransfer <= pcie_compiler_0_Tx_Interface_unreg_firsttransfer;
end if;
end if;
end process;
--pcie_compiler_0_Tx_Interface_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
pcie_compiler_0_Tx_Interface_next_bbt_burstcount <= A_EXT (A_WE_StdLogicVector((std_logic'((((internal_pcie_compiler_0_Tx_Interface_write) AND to_std_logic((((std_logic_vector'("00000000000000000000000") & (pcie_compiler_0_Tx_Interface_bbt_burstcounter)) = std_logic_vector'("00000000000000000000000000000000"))))))) = '1'), (((std_logic_vector'("00000000000000000000000") & (internal_pcie_compiler_0_Tx_Interface_burstcount)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'((((internal_pcie_compiler_0_Tx_Interface_read) AND to_std_logic((((std_logic_vector'("00000000000000000000000") & (pcie_compiler_0_Tx_Interface_bbt_burstcounter)) = std_logic_vector'("00000000000000000000000000000000"))))))) = '1'), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("000000000000000000000000") & (pcie_compiler_0_Tx_Interface_bbt_burstcounter)) - std_logic_vector'("000000000000000000000000000000001"))))), 9);
--pcie_compiler_0_Tx_Interface_bbt_burstcounter bbt_burstcounter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Tx_Interface_bbt_burstcounter <= std_logic_vector'("000000000");
elsif clk'event and clk = '1' then
if std_logic'(pcie_compiler_0_Tx_Interface_begins_xfer) = '1' then
pcie_compiler_0_Tx_Interface_bbt_burstcounter <= pcie_compiler_0_Tx_Interface_next_bbt_burstcount;
end if;
end if;
end process;
--pcie_compiler_0_Tx_Interface_beginbursttransfer_internal begin burst transfer, which is an e_assign
pcie_compiler_0_Tx_Interface_beginbursttransfer_internal <= pcie_compiler_0_Tx_Interface_begins_xfer AND to_std_logic((((std_logic_vector'("00000000000000000000000") & (pcie_compiler_0_Tx_Interface_bbt_burstcounter)) = std_logic_vector'("00000000000000000000000000000000"))));
--pcie_compiler_0_Tx_Interface_read assignment, which is an e_mux
internal_pcie_compiler_0_Tx_Interface_read <= std_logic'('0');
--pcie_compiler_0_Tx_Interface_write assignment, which is an e_mux
internal_pcie_compiler_0_Tx_Interface_write <= internal_dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface AND dma_arbiter_0_avalon_master_write;
shifted_address_to_pcie_compiler_0_Tx_Interface_from_dma_arbiter_0_avalon_master <= dma_arbiter_0_avalon_master_address_to_slave;
--pcie_compiler_0_Tx_Interface_address mux, which is an e_mux
pcie_compiler_0_Tx_Interface_address <= A_EXT (A_SRL(shifted_address_to_pcie_compiler_0_Tx_Interface_from_dma_arbiter_0_avalon_master,std_logic_vector'("00000000000000000000000000000011")), 28);
--d1_pcie_compiler_0_Tx_Interface_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_pcie_compiler_0_Tx_Interface_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_pcie_compiler_0_Tx_Interface_end_xfer <= pcie_compiler_0_Tx_Interface_end_xfer;
end if;
end process;
--pcie_compiler_0_Tx_Interface_waits_for_read in a cycle, which is an e_mux
pcie_compiler_0_Tx_Interface_waits_for_read <= pcie_compiler_0_Tx_Interface_in_a_read_cycle AND internal_pcie_compiler_0_Tx_Interface_waitrequest_from_sa;
--pcie_compiler_0_Tx_Interface_in_a_read_cycle assignment, which is an e_assign
pcie_compiler_0_Tx_Interface_in_a_read_cycle <= std_logic'('0');
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= pcie_compiler_0_Tx_Interface_in_a_read_cycle;
--pcie_compiler_0_Tx_Interface_waits_for_write in a cycle, which is an e_mux
pcie_compiler_0_Tx_Interface_waits_for_write <= pcie_compiler_0_Tx_Interface_in_a_write_cycle AND internal_pcie_compiler_0_Tx_Interface_waitrequest_from_sa;
--assign pcie_compiler_0_Tx_Interface_readdatavalid_from_sa = pcie_compiler_0_Tx_Interface_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
pcie_compiler_0_Tx_Interface_readdatavalid_from_sa <= pcie_compiler_0_Tx_Interface_readdatavalid;
--pcie_compiler_0_Tx_Interface_in_a_write_cycle assignment, which is an e_assign
pcie_compiler_0_Tx_Interface_in_a_write_cycle <= internal_dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface AND dma_arbiter_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= pcie_compiler_0_Tx_Interface_in_a_write_cycle;
wait_for_pcie_compiler_0_Tx_Interface_counter <= std_logic'('0');
--pcie_compiler_0_Tx_Interface_byteenable byte enable port mux, which is an e_mux
pcie_compiler_0_Tx_Interface_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface)) = '1'), (std_logic_vector'("000000000000000000000000") & (dma_arbiter_0_avalon_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 8);
--burstcount mux, which is an e_mux
internal_pcie_compiler_0_Tx_Interface_burstcount <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface)) = '1'), (std_logic_vector'("0000000000000000000000000") & (dma_arbiter_0_avalon_master_burstcount)), std_logic_vector'("00000000000000000000000000000001")), 10);
--vhdl renameroo for output signals
dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface <= internal_dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface;
--vhdl renameroo for output signals
dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface <= internal_dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface;
--vhdl renameroo for output signals
dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface <= internal_dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface;
--vhdl renameroo for output signals
pcie_compiler_0_Tx_Interface_burstcount <= internal_pcie_compiler_0_Tx_Interface_burstcount;
--vhdl renameroo for output signals
pcie_compiler_0_Tx_Interface_read <= internal_pcie_compiler_0_Tx_Interface_read;
--vhdl renameroo for output signals
pcie_compiler_0_Tx_Interface_waitrequest_from_sa <= internal_pcie_compiler_0_Tx_Interface_waitrequest_from_sa;
--vhdl renameroo for output signals
pcie_compiler_0_Tx_Interface_write <= internal_pcie_compiler_0_Tx_Interface_write;
--synthesis translate_off
--pcie_compiler_0/Tx_Interface enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--dma_arbiter_0/avalon_master non-zero burstcount assertion, which is an e_process
process (clk)
VARIABLE write_line13 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((internal_dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface AND to_std_logic((((std_logic_vector'("0000000000000000000000000") & (dma_arbiter_0_avalon_master_burstcount)) = std_logic_vector'("00000000000000000000000000000000"))))) AND enable_nonzero_assertions)) = '1' then
write(write_line13, now);
write(write_line13, string'(": "));
write(write_line13, string'("dma_arbiter_0/avalon_master drove 0 on its 'burstcount' port while accessing slave pcie_compiler_0/Tx_Interface"));
write(output, write_line13.all);
deallocate (write_line13);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity pcie_compiler_0_Rx_Interface_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal d1_unici_core_burst_0_upstream_end_xfer : IN STD_LOGIC;
signal d1_unici_core_burst_1_upstream_end_xfer : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_address : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_burstcount : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_write : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_0_upstream_readdata_from_sa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_upstream_waitrequest_from_sa : IN STD_LOGIC;
signal unici_core_burst_1_upstream_readdata_from_sa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_upstream_waitrequest_from_sa : IN STD_LOGIC;
-- outputs:
signal pcie_compiler_0_Rx_Interface_address_to_slave : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_latency_counter : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_readdatavalid : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_reset_n : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_waitrequest : OUT STD_LOGIC
);
end entity pcie_compiler_0_Rx_Interface_arbitrator;
architecture europa of pcie_compiler_0_Rx_Interface_arbitrator is
signal active_and_waiting_last_time : STD_LOGIC;
signal internal_pcie_compiler_0_Rx_Interface_address_to_slave : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_pcie_compiler_0_Rx_Interface_latency_counter : STD_LOGIC;
signal internal_pcie_compiler_0_Rx_Interface_waitrequest : STD_LOGIC;
signal latency_load_value : STD_LOGIC;
signal p1_pcie_compiler_0_Rx_Interface_latency_counter : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_address_last_time : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_burstcount_last_time : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_byteenable_last_time : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_is_granted_some_slave : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_but_no_slave_selected : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_last_time : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_run : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_write_last_time : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_writedata_last_time : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pre_flush_pcie_compiler_0_Rx_Interface_readdatavalid : STD_LOGIC;
signal r_2 : STD_LOGIC;
begin
--r_2 master_run cascaded wait assignment, which is an e_assign
r_2 <= Vector_To_Std_Logic((((((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream OR NOT pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream OR NOT ((pcie_compiler_0_Rx_Interface_read OR pcie_compiler_0_Rx_Interface_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT unici_core_burst_0_upstream_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((pcie_compiler_0_Rx_Interface_read OR pcie_compiler_0_Rx_Interface_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream OR NOT ((pcie_compiler_0_Rx_Interface_read OR pcie_compiler_0_Rx_Interface_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT unici_core_burst_0_upstream_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((pcie_compiler_0_Rx_Interface_read OR pcie_compiler_0_Rx_Interface_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream OR NOT pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream OR NOT ((pcie_compiler_0_Rx_Interface_read OR pcie_compiler_0_Rx_Interface_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT unici_core_burst_1_upstream_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((pcie_compiler_0_Rx_Interface_read OR pcie_compiler_0_Rx_Interface_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream OR NOT ((pcie_compiler_0_Rx_Interface_read OR pcie_compiler_0_Rx_Interface_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT unici_core_burst_1_upstream_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((pcie_compiler_0_Rx_Interface_read OR pcie_compiler_0_Rx_Interface_write)))))))))));
--cascaded wait assignment, which is an e_assign
pcie_compiler_0_Rx_Interface_run <= r_2;
--pcie_compiler_0_Rx_Interface_reset_n assignment, which is an e_assign
pcie_compiler_0_Rx_Interface_reset_n <= reset_n;
--optimize select-logic by passing only those address bits which matter.
internal_pcie_compiler_0_Rx_Interface_address_to_slave <= Std_Logic_Vector'(std_logic_vector'("0000000000000") & pcie_compiler_0_Rx_Interface_address(18 DOWNTO 0));
--pcie_compiler_0_Rx_Interface_read_but_no_slave_selected assignment, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Rx_Interface_read_but_no_slave_selected <= std_logic'('0');
elsif clk'event and clk = '1' then
pcie_compiler_0_Rx_Interface_read_but_no_slave_selected <= (pcie_compiler_0_Rx_Interface_read AND pcie_compiler_0_Rx_Interface_run) AND NOT pcie_compiler_0_Rx_Interface_is_granted_some_slave;
end if;
end process;
--some slave is getting selected, which is an e_mux
pcie_compiler_0_Rx_Interface_is_granted_some_slave <= pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream OR pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream;
--latent slave read data valids which may be flushed, which is an e_mux
pre_flush_pcie_compiler_0_Rx_Interface_readdatavalid <= pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream OR pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream;
--latent slave read data valid which is not flushed, which is an e_mux
pcie_compiler_0_Rx_Interface_readdatavalid <= ((pcie_compiler_0_Rx_Interface_read_but_no_slave_selected OR pre_flush_pcie_compiler_0_Rx_Interface_readdatavalid) OR pcie_compiler_0_Rx_Interface_read_but_no_slave_selected) OR pre_flush_pcie_compiler_0_Rx_Interface_readdatavalid;
--pcie_compiler_0/Rx_Interface readdata mux, which is an e_mux
pcie_compiler_0_Rx_Interface_readdata <= ((A_REP(NOT pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream, 64) OR unici_core_burst_0_upstream_readdata_from_sa)) AND ((A_REP(NOT pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream, 64) OR unici_core_burst_1_upstream_readdata_from_sa));
--actual waitrequest port, which is an e_assign
internal_pcie_compiler_0_Rx_Interface_waitrequest <= NOT pcie_compiler_0_Rx_Interface_run;
--latent max counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
internal_pcie_compiler_0_Rx_Interface_latency_counter <= std_logic'('0');
elsif clk'event and clk = '1' then
internal_pcie_compiler_0_Rx_Interface_latency_counter <= p1_pcie_compiler_0_Rx_Interface_latency_counter;
end if;
end process;
--latency counter load mux, which is an e_mux
p1_pcie_compiler_0_Rx_Interface_latency_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(((pcie_compiler_0_Rx_Interface_run AND pcie_compiler_0_Rx_Interface_read))) = '1'), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(latency_load_value))), A_WE_StdLogicVector((std_logic'((internal_pcie_compiler_0_Rx_Interface_latency_counter)) = '1'), ((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_pcie_compiler_0_Rx_Interface_latency_counter))) - std_logic_vector'("000000000000000000000000000000001")), std_logic_vector'("000000000000000000000000000000000"))));
--read latency load values, which is an e_mux
latency_load_value <= std_logic'('0');
--vhdl renameroo for output signals
pcie_compiler_0_Rx_Interface_address_to_slave <= internal_pcie_compiler_0_Rx_Interface_address_to_slave;
--vhdl renameroo for output signals
pcie_compiler_0_Rx_Interface_latency_counter <= internal_pcie_compiler_0_Rx_Interface_latency_counter;
--vhdl renameroo for output signals
pcie_compiler_0_Rx_Interface_waitrequest <= internal_pcie_compiler_0_Rx_Interface_waitrequest;
--synthesis translate_off
--pcie_compiler_0_Rx_Interface_address check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Rx_Interface_address_last_time <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
pcie_compiler_0_Rx_Interface_address_last_time <= pcie_compiler_0_Rx_Interface_address;
end if;
end process;
--pcie_compiler_0/Rx_Interface waited last time, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
active_and_waiting_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
active_and_waiting_last_time <= internal_pcie_compiler_0_Rx_Interface_waitrequest AND ((pcie_compiler_0_Rx_Interface_read OR pcie_compiler_0_Rx_Interface_write));
end if;
end process;
--pcie_compiler_0_Rx_Interface_address matches last port_name, which is an e_process
process (clk)
VARIABLE write_line14 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((pcie_compiler_0_Rx_Interface_address /= pcie_compiler_0_Rx_Interface_address_last_time))))) = '1' then
write(write_line14, now);
write(write_line14, string'(": "));
write(write_line14, string'("pcie_compiler_0_Rx_Interface_address did not heed wait!!!"));
write(output, write_line14.all);
deallocate (write_line14);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--pcie_compiler_0_Rx_Interface_burstcount check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Rx_Interface_burstcount_last_time <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
pcie_compiler_0_Rx_Interface_burstcount_last_time <= pcie_compiler_0_Rx_Interface_burstcount;
end if;
end process;
--pcie_compiler_0_Rx_Interface_burstcount matches last port_name, which is an e_process
process (clk)
VARIABLE write_line15 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((pcie_compiler_0_Rx_Interface_burstcount /= pcie_compiler_0_Rx_Interface_burstcount_last_time))))) = '1' then
write(write_line15, now);
write(write_line15, string'(": "));
write(write_line15, string'("pcie_compiler_0_Rx_Interface_burstcount did not heed wait!!!"));
write(output, write_line15.all);
deallocate (write_line15);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--pcie_compiler_0_Rx_Interface_byteenable check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Rx_Interface_byteenable_last_time <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
pcie_compiler_0_Rx_Interface_byteenable_last_time <= pcie_compiler_0_Rx_Interface_byteenable;
end if;
end process;
--pcie_compiler_0_Rx_Interface_byteenable matches last port_name, which is an e_process
process (clk)
VARIABLE write_line16 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((pcie_compiler_0_Rx_Interface_byteenable /= pcie_compiler_0_Rx_Interface_byteenable_last_time))))) = '1' then
write(write_line16, now);
write(write_line16, string'(": "));
write(write_line16, string'("pcie_compiler_0_Rx_Interface_byteenable did not heed wait!!!"));
write(output, write_line16.all);
deallocate (write_line16);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--pcie_compiler_0_Rx_Interface_read check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Rx_Interface_read_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
pcie_compiler_0_Rx_Interface_read_last_time <= pcie_compiler_0_Rx_Interface_read;
end if;
end process;
--pcie_compiler_0_Rx_Interface_read matches last port_name, which is an e_process
process (clk)
VARIABLE write_line17 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(pcie_compiler_0_Rx_Interface_read) /= std_logic'(pcie_compiler_0_Rx_Interface_read_last_time)))))) = '1' then
write(write_line17, now);
write(write_line17, string'(": "));
write(write_line17, string'("pcie_compiler_0_Rx_Interface_read did not heed wait!!!"));
write(output, write_line17.all);
deallocate (write_line17);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--pcie_compiler_0_Rx_Interface_write check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Rx_Interface_write_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
pcie_compiler_0_Rx_Interface_write_last_time <= pcie_compiler_0_Rx_Interface_write;
end if;
end process;
--pcie_compiler_0_Rx_Interface_write matches last port_name, which is an e_process
process (clk)
VARIABLE write_line18 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(pcie_compiler_0_Rx_Interface_write) /= std_logic'(pcie_compiler_0_Rx_Interface_write_last_time)))))) = '1' then
write(write_line18, now);
write(write_line18, string'(": "));
write(write_line18, string'("pcie_compiler_0_Rx_Interface_write did not heed wait!!!"));
write(output, write_line18.all);
deallocate (write_line18);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--pcie_compiler_0_Rx_Interface_writedata check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pcie_compiler_0_Rx_Interface_writedata_last_time <= std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
pcie_compiler_0_Rx_Interface_writedata_last_time <= pcie_compiler_0_Rx_Interface_writedata;
end if;
end process;
--pcie_compiler_0_Rx_Interface_writedata matches last port_name, which is an e_process
process (clk)
VARIABLE write_line19 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((active_and_waiting_last_time AND to_std_logic(((pcie_compiler_0_Rx_Interface_writedata /= pcie_compiler_0_Rx_Interface_writedata_last_time)))) AND pcie_compiler_0_Rx_Interface_write)) = '1' then
write(write_line19, now);
write(write_line19, string'(": "));
write(write_line19, string'("pcie_compiler_0_Rx_Interface_writedata did not heed wait!!!"));
write(output, write_line19.all);
deallocate (write_line19);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rdv_fifo_for_unici_core_burst_0_downstream_to_pipeline_bridge_0_s1_module is
port (
-- inputs:
signal clear_fifo : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal read : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC;
signal empty : OUT STD_LOGIC;
signal fifo_contains_ones_n : OUT STD_LOGIC;
signal full : OUT STD_LOGIC
);
end entity rdv_fifo_for_unici_core_burst_0_downstream_to_pipeline_bridge_0_s1_module;
architecture europa of rdv_fifo_for_unici_core_burst_0_downstream_to_pipeline_bridge_0_s1_module is
signal full_0 : STD_LOGIC;
signal full_1 : STD_LOGIC;
signal full_2 : STD_LOGIC;
signal full_3 : STD_LOGIC;
signal how_many_ones : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal one_count_minus_one : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal one_count_plus_one : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal p0_full_0 : STD_LOGIC;
signal p0_stage_0 : STD_LOGIC;
signal p1_full_1 : STD_LOGIC;
signal p1_stage_1 : STD_LOGIC;
signal p2_full_2 : STD_LOGIC;
signal p2_stage_2 : STD_LOGIC;
signal stage_0 : STD_LOGIC;
signal stage_1 : STD_LOGIC;
signal stage_2 : STD_LOGIC;
signal updated_one_count : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
data_out <= stage_0;
full <= full_2;
empty <= NOT(full_0);
full_3 <= std_logic'('0');
--data_2, which is an e_mux
p2_stage_2 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_3 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, data_in);
--data_reg_2, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_2 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_2))))) = '1' then
if std_logic'(((sync_reset AND full_2) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_3))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_2 <= std_logic'('0');
else
stage_2 <= p2_stage_2;
end if;
end if;
end if;
end process;
--control_2, which is an e_mux
p2_full_2 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1))), std_logic_vector'("00000000000000000000000000000000")));
--control_reg_2, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_2 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_2 <= std_logic'('0');
else
full_2 <= p2_full_2;
end if;
end if;
end if;
end process;
--data_1, which is an e_mux
p1_stage_1 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_2 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_2);
--data_reg_1, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_1))))) = '1' then
if std_logic'(((sync_reset AND full_1) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_2))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_1 <= std_logic'('0');
else
stage_1 <= p1_stage_1;
end if;
end if;
end if;
end process;
--control_1, which is an e_mux
p1_full_1 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_0, full_2);
--control_reg_1, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_1 <= std_logic'('0');
else
full_1 <= p1_full_1;
end if;
end if;
end if;
end process;
--data_0, which is an e_mux
p0_stage_0 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_1 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_1);
--data_reg_0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_0 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(((sync_reset AND full_0) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_0 <= std_logic'('0');
else
stage_0 <= p0_stage_0;
end if;
end if;
end if;
end process;
--control_0, which is an e_mux
p0_full_0 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), std_logic_vector'("00000000000000000000000000000001"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1)))));
--control_reg_0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_0 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'((clear_fifo AND NOT write)) = '1' then
full_0 <= std_logic'('0');
else
full_0 <= p0_full_0;
end if;
end if;
end if;
end process;
one_count_plus_one <= A_EXT (((std_logic_vector'("000000000000000000000000000000") & (how_many_ones)) + std_logic_vector'("000000000000000000000000000000001")), 3);
one_count_minus_one <= A_EXT (((std_logic_vector'("000000000000000000000000000000") & (how_many_ones)) - std_logic_vector'("000000000000000000000000000000001")), 3);
--updated_one_count, which is an e_mux
updated_one_count <= A_EXT (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND NOT(write)))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND write))) = '1'), (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(data_in))), A_WE_StdLogicVector((std_logic'(((((read AND (data_in)) AND write) AND (stage_0)))) = '1'), how_many_ones, A_WE_StdLogicVector((std_logic'(((write AND (data_in)))) = '1'), one_count_plus_one, A_WE_StdLogicVector((std_logic'(((read AND (stage_0)))) = '1'), one_count_minus_one, how_many_ones))))))), 3);
--counts how many ones in the data pipeline, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
how_many_ones <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then
how_many_ones <= updated_one_count;
end if;
end if;
end process;
--this fifo contains ones in the data pipeline, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_contains_ones_n <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then
fifo_contains_ones_n <= NOT (or_reduce(updated_one_count));
end if;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity pipeline_bridge_0_s1_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal pipeline_bridge_0_s1_endofpacket : IN STD_LOGIC;
signal pipeline_bridge_0_s1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_s1_readdatavalid : IN STD_LOGIC;
signal pipeline_bridge_0_s1_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_0_downstream_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_arbitrationshare : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_downstream_burstcount : IN STD_LOGIC;
signal unici_core_burst_0_downstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_0_downstream_debugaccess : IN STD_LOGIC;
signal unici_core_burst_0_downstream_latency_counter : IN STD_LOGIC;
signal unici_core_burst_0_downstream_nativeaddress : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_read : IN STD_LOGIC;
signal unici_core_burst_0_downstream_write : IN STD_LOGIC;
signal unici_core_burst_0_downstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal d1_pipeline_bridge_0_s1_end_xfer : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_address : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal pipeline_bridge_0_s1_arbiterlock : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_arbiterlock2 : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_burstcount : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pipeline_bridge_0_s1_chipselect : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_debugaccess : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_endofpacket_from_sa : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal pipeline_bridge_0_s1_read : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_s1_reset_n : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_waitrequest_from_sa : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_write : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1 : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1_shift_register : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 : OUT STD_LOGIC
);
end entity pipeline_bridge_0_s1_arbitrator;
architecture europa of pipeline_bridge_0_s1_arbitrator is
component rdv_fifo_for_unici_core_burst_0_downstream_to_pipeline_bridge_0_s1_module is
port (
-- inputs:
signal clear_fifo : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal read : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC;
signal empty : OUT STD_LOGIC;
signal fifo_contains_ones_n : OUT STD_LOGIC;
signal full : OUT STD_LOGIC
);
end component rdv_fifo_for_unici_core_burst_0_downstream_to_pipeline_bridge_0_s1_module;
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_pipeline_bridge_0_s1 : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal internal_pipeline_bridge_0_s1_waitrequest_from_sa : STD_LOGIC;
signal internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 : STD_LOGIC;
signal internal_unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 : STD_LOGIC;
signal internal_unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 : STD_LOGIC;
signal module_input : STD_LOGIC;
signal module_input1 : STD_LOGIC;
signal module_input2 : STD_LOGIC;
signal pipeline_bridge_0_s1_allgrants : STD_LOGIC;
signal pipeline_bridge_0_s1_allow_new_arb_cycle : STD_LOGIC;
signal pipeline_bridge_0_s1_any_bursting_master_saved_grant : STD_LOGIC;
signal pipeline_bridge_0_s1_any_continuerequest : STD_LOGIC;
signal pipeline_bridge_0_s1_arb_counter_enable : STD_LOGIC;
signal pipeline_bridge_0_s1_arb_share_counter : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pipeline_bridge_0_s1_arb_share_counter_next_value : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pipeline_bridge_0_s1_arb_share_set_values : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pipeline_bridge_0_s1_arbitration_holdoff_internal : STD_LOGIC;
signal pipeline_bridge_0_s1_beginbursttransfer_internal : STD_LOGIC;
signal pipeline_bridge_0_s1_begins_xfer : STD_LOGIC;
signal pipeline_bridge_0_s1_end_xfer : STD_LOGIC;
signal pipeline_bridge_0_s1_firsttransfer : STD_LOGIC;
signal pipeline_bridge_0_s1_grant_vector : STD_LOGIC;
signal pipeline_bridge_0_s1_in_a_read_cycle : STD_LOGIC;
signal pipeline_bridge_0_s1_in_a_write_cycle : STD_LOGIC;
signal pipeline_bridge_0_s1_master_qreq_vector : STD_LOGIC;
signal pipeline_bridge_0_s1_move_on_to_next_transaction : STD_LOGIC;
signal pipeline_bridge_0_s1_non_bursting_master_requests : STD_LOGIC;
signal pipeline_bridge_0_s1_readdatavalid_from_sa : STD_LOGIC;
signal pipeline_bridge_0_s1_reg_firsttransfer : STD_LOGIC;
signal pipeline_bridge_0_s1_slavearbiterlockenable : STD_LOGIC;
signal pipeline_bridge_0_s1_slavearbiterlockenable2 : STD_LOGIC;
signal pipeline_bridge_0_s1_unreg_firsttransfer : STD_LOGIC;
signal pipeline_bridge_0_s1_waits_for_read : STD_LOGIC;
signal pipeline_bridge_0_s1_waits_for_write : STD_LOGIC;
signal shifted_address_to_pipeline_bridge_0_s1_from_unici_core_burst_0_downstream : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_arbiterlock : STD_LOGIC;
signal unici_core_burst_0_downstream_arbiterlock2 : STD_LOGIC;
signal unici_core_burst_0_downstream_continuerequest : STD_LOGIC;
signal unici_core_burst_0_downstream_rdv_fifo_empty_pipeline_bridge_0_s1 : STD_LOGIC;
signal unici_core_burst_0_downstream_rdv_fifo_output_from_pipeline_bridge_0_s1 : STD_LOGIC;
signal unici_core_burst_0_downstream_saved_grant_pipeline_bridge_0_s1 : STD_LOGIC;
signal wait_for_pipeline_bridge_0_s1_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT pipeline_bridge_0_s1_end_xfer;
end if;
end process;
pipeline_bridge_0_s1_begins_xfer <= NOT d1_reasons_to_wait AND (internal_unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1);
--assign pipeline_bridge_0_s1_readdata_from_sa = pipeline_bridge_0_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
pipeline_bridge_0_s1_readdata_from_sa <= pipeline_bridge_0_s1_readdata;
internal_unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((unici_core_burst_0_downstream_read OR unici_core_burst_0_downstream_write)))))));
--assign pipeline_bridge_0_s1_waitrequest_from_sa = pipeline_bridge_0_s1_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_pipeline_bridge_0_s1_waitrequest_from_sa <= pipeline_bridge_0_s1_waitrequest;
--assign pipeline_bridge_0_s1_readdatavalid_from_sa = pipeline_bridge_0_s1_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
pipeline_bridge_0_s1_readdatavalid_from_sa <= pipeline_bridge_0_s1_readdatavalid;
--pipeline_bridge_0_s1_arb_share_counter set values, which is an e_mux
pipeline_bridge_0_s1_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1)) = '1'), (std_logic_vector'("0000000000000000000000") & (unici_core_burst_0_downstream_arbitrationshare)), A_WE_StdLogicVector((std_logic'((internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1)) = '1'), (std_logic_vector'("0000000000000000000000") & (unici_core_burst_0_downstream_arbitrationshare)), std_logic_vector'("00000000000000000000000000000001"))), 10);
--pipeline_bridge_0_s1_non_bursting_master_requests mux, which is an e_mux
pipeline_bridge_0_s1_non_bursting_master_requests <= std_logic'('0');
--pipeline_bridge_0_s1_any_bursting_master_saved_grant mux, which is an e_mux
pipeline_bridge_0_s1_any_bursting_master_saved_grant <= unici_core_burst_0_downstream_saved_grant_pipeline_bridge_0_s1 OR unici_core_burst_0_downstream_saved_grant_pipeline_bridge_0_s1;
--pipeline_bridge_0_s1_arb_share_counter_next_value assignment, which is an e_assign
pipeline_bridge_0_s1_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(pipeline_bridge_0_s1_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000") & (pipeline_bridge_0_s1_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(pipeline_bridge_0_s1_arb_share_counter)) = '1'), (((std_logic_vector'("00000000000000000000000") & (pipeline_bridge_0_s1_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 10);
--pipeline_bridge_0_s1_allgrants all slave grants, which is an e_mux
pipeline_bridge_0_s1_allgrants <= (pipeline_bridge_0_s1_grant_vector) OR (pipeline_bridge_0_s1_grant_vector);
--pipeline_bridge_0_s1_end_xfer assignment, which is an e_assign
pipeline_bridge_0_s1_end_xfer <= NOT ((pipeline_bridge_0_s1_waits_for_read OR pipeline_bridge_0_s1_waits_for_write));
--end_xfer_arb_share_counter_term_pipeline_bridge_0_s1 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_pipeline_bridge_0_s1 <= pipeline_bridge_0_s1_end_xfer AND (((NOT pipeline_bridge_0_s1_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--pipeline_bridge_0_s1_arb_share_counter arbitration counter enable, which is an e_assign
pipeline_bridge_0_s1_arb_counter_enable <= ((end_xfer_arb_share_counter_term_pipeline_bridge_0_s1 AND pipeline_bridge_0_s1_allgrants)) OR ((end_xfer_arb_share_counter_term_pipeline_bridge_0_s1 AND NOT pipeline_bridge_0_s1_non_bursting_master_requests));
--pipeline_bridge_0_s1_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pipeline_bridge_0_s1_arb_share_counter <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'(pipeline_bridge_0_s1_arb_counter_enable) = '1' then
pipeline_bridge_0_s1_arb_share_counter <= pipeline_bridge_0_s1_arb_share_counter_next_value;
end if;
end if;
end process;
--pipeline_bridge_0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pipeline_bridge_0_s1_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((pipeline_bridge_0_s1_master_qreq_vector AND end_xfer_arb_share_counter_term_pipeline_bridge_0_s1)) OR ((end_xfer_arb_share_counter_term_pipeline_bridge_0_s1 AND NOT pipeline_bridge_0_s1_non_bursting_master_requests)))) = '1' then
pipeline_bridge_0_s1_slavearbiterlockenable <= or_reduce(pipeline_bridge_0_s1_arb_share_counter_next_value);
end if;
end if;
end process;
--unici_core_burst_0/downstream pipeline_bridge_0/s1 arbiterlock, which is an e_assign
unici_core_burst_0_downstream_arbiterlock <= pipeline_bridge_0_s1_slavearbiterlockenable AND unici_core_burst_0_downstream_continuerequest;
--pipeline_bridge_0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
pipeline_bridge_0_s1_slavearbiterlockenable2 <= or_reduce(pipeline_bridge_0_s1_arb_share_counter_next_value);
--unici_core_burst_0/downstream pipeline_bridge_0/s1 arbiterlock2, which is an e_assign
unici_core_burst_0_downstream_arbiterlock2 <= pipeline_bridge_0_s1_slavearbiterlockenable2 AND unici_core_burst_0_downstream_continuerequest;
--pipeline_bridge_0_s1_any_continuerequest at least one master continues requesting, which is an e_assign
pipeline_bridge_0_s1_any_continuerequest <= std_logic'('1');
--unici_core_burst_0_downstream_continuerequest continued request, which is an e_assign
unici_core_burst_0_downstream_continuerequest <= std_logic'('1');
internal_unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 <= internal_unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 AND NOT ((unici_core_burst_0_downstream_read AND to_std_logic((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(unici_core_burst_0_downstream_latency_counter))) /= std_logic_vector'("00000000000000000000000000000000"))) OR ((std_logic_vector'("00000000000000000000000000000001")<(std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(unici_core_burst_0_downstream_latency_counter))))))))));
--unique name for pipeline_bridge_0_s1_move_on_to_next_transaction, which is an e_assign
pipeline_bridge_0_s1_move_on_to_next_transaction <= pipeline_bridge_0_s1_readdatavalid_from_sa;
--rdv_fifo_for_unici_core_burst_0_downstream_to_pipeline_bridge_0_s1, which is an e_fifo_with_registered_outputs
rdv_fifo_for_unici_core_burst_0_downstream_to_pipeline_bridge_0_s1 : rdv_fifo_for_unici_core_burst_0_downstream_to_pipeline_bridge_0_s1_module
port map(
data_out => unici_core_burst_0_downstream_rdv_fifo_output_from_pipeline_bridge_0_s1,
empty => open,
fifo_contains_ones_n => unici_core_burst_0_downstream_rdv_fifo_empty_pipeline_bridge_0_s1,
full => open,
clear_fifo => module_input,
clk => clk,
data_in => internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1,
read => pipeline_bridge_0_s1_move_on_to_next_transaction,
reset_n => reset_n,
sync_reset => module_input1,
write => module_input2
);
module_input <= std_logic'('0');
module_input1 <= std_logic'('0');
module_input2 <= in_a_read_cycle AND NOT pipeline_bridge_0_s1_waits_for_read;
unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1_shift_register <= NOT unici_core_burst_0_downstream_rdv_fifo_empty_pipeline_bridge_0_s1;
--local readdatavalid unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1, which is an e_mux
unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1 <= pipeline_bridge_0_s1_readdatavalid_from_sa;
--pipeline_bridge_0_s1_writedata mux, which is an e_mux
pipeline_bridge_0_s1_writedata <= unici_core_burst_0_downstream_writedata;
--assign pipeline_bridge_0_s1_endofpacket_from_sa = pipeline_bridge_0_s1_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
pipeline_bridge_0_s1_endofpacket_from_sa <= pipeline_bridge_0_s1_endofpacket;
--master is always granted when requested
internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 <= internal_unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1;
--unici_core_burst_0/downstream saved-grant pipeline_bridge_0/s1, which is an e_assign
unici_core_burst_0_downstream_saved_grant_pipeline_bridge_0_s1 <= internal_unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1;
--allow new arb cycle for pipeline_bridge_0/s1, which is an e_assign
pipeline_bridge_0_s1_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
pipeline_bridge_0_s1_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
pipeline_bridge_0_s1_master_qreq_vector <= std_logic'('1');
--pipeline_bridge_0_s1_reset_n assignment, which is an e_assign
pipeline_bridge_0_s1_reset_n <= reset_n;
pipeline_bridge_0_s1_chipselect <= internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1;
--pipeline_bridge_0_s1_firsttransfer first transaction, which is an e_assign
pipeline_bridge_0_s1_firsttransfer <= A_WE_StdLogic((std_logic'(pipeline_bridge_0_s1_begins_xfer) = '1'), pipeline_bridge_0_s1_unreg_firsttransfer, pipeline_bridge_0_s1_reg_firsttransfer);
--pipeline_bridge_0_s1_unreg_firsttransfer first transaction, which is an e_assign
pipeline_bridge_0_s1_unreg_firsttransfer <= NOT ((pipeline_bridge_0_s1_slavearbiterlockenable AND pipeline_bridge_0_s1_any_continuerequest));
--pipeline_bridge_0_s1_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pipeline_bridge_0_s1_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(pipeline_bridge_0_s1_begins_xfer) = '1' then
pipeline_bridge_0_s1_reg_firsttransfer <= pipeline_bridge_0_s1_unreg_firsttransfer;
end if;
end if;
end process;
--pipeline_bridge_0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
pipeline_bridge_0_s1_beginbursttransfer_internal <= pipeline_bridge_0_s1_begins_xfer;
--pipeline_bridge_0_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
pipeline_bridge_0_s1_arbitration_holdoff_internal <= pipeline_bridge_0_s1_begins_xfer AND pipeline_bridge_0_s1_firsttransfer;
--pipeline_bridge_0_s1_read assignment, which is an e_mux
pipeline_bridge_0_s1_read <= internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 AND unici_core_burst_0_downstream_read;
--pipeline_bridge_0_s1_write assignment, which is an e_mux
pipeline_bridge_0_s1_write <= internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 AND unici_core_burst_0_downstream_write;
shifted_address_to_pipeline_bridge_0_s1_from_unici_core_burst_0_downstream <= unici_core_burst_0_downstream_address_to_slave;
--pipeline_bridge_0_s1_address mux, which is an e_mux
pipeline_bridge_0_s1_address <= A_EXT (A_SRL(shifted_address_to_pipeline_bridge_0_s1_from_unici_core_burst_0_downstream,std_logic_vector'("00000000000000000000000000000011")), 12);
--slaveid pipeline_bridge_0_s1_nativeaddress nativeaddress mux, which is an e_mux
pipeline_bridge_0_s1_nativeaddress <= unici_core_burst_0_downstream_nativeaddress (11 DOWNTO 0);
--d1_pipeline_bridge_0_s1_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_pipeline_bridge_0_s1_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_pipeline_bridge_0_s1_end_xfer <= pipeline_bridge_0_s1_end_xfer;
end if;
end process;
--pipeline_bridge_0_s1_waits_for_read in a cycle, which is an e_mux
pipeline_bridge_0_s1_waits_for_read <= pipeline_bridge_0_s1_in_a_read_cycle AND internal_pipeline_bridge_0_s1_waitrequest_from_sa;
--pipeline_bridge_0_s1_in_a_read_cycle assignment, which is an e_assign
pipeline_bridge_0_s1_in_a_read_cycle <= internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 AND unici_core_burst_0_downstream_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= pipeline_bridge_0_s1_in_a_read_cycle;
--pipeline_bridge_0_s1_waits_for_write in a cycle, which is an e_mux
pipeline_bridge_0_s1_waits_for_write <= pipeline_bridge_0_s1_in_a_write_cycle AND internal_pipeline_bridge_0_s1_waitrequest_from_sa;
--pipeline_bridge_0_s1_in_a_write_cycle assignment, which is an e_assign
pipeline_bridge_0_s1_in_a_write_cycle <= internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 AND unici_core_burst_0_downstream_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= pipeline_bridge_0_s1_in_a_write_cycle;
wait_for_pipeline_bridge_0_s1_counter <= std_logic'('0');
--pipeline_bridge_0_s1_byteenable byte enable port mux, which is an e_mux
pipeline_bridge_0_s1_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1)) = '1'), (std_logic_vector'("000000000000000000000000") & (unici_core_burst_0_downstream_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 8);
--burstcount mux, which is an e_mux
pipeline_bridge_0_s1_burstcount <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1)) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(unici_core_burst_0_downstream_burstcount))), std_logic_vector'("00000000000000000000000000000001")));
--pipeline_bridge_0/s1 arbiterlock assigned from _handle_arbiterlock, which is an e_mux
pipeline_bridge_0_s1_arbiterlock <= unici_core_burst_0_downstream_arbiterlock;
--pipeline_bridge_0/s1 arbiterlock2 assigned from _handle_arbiterlock2, which is an e_mux
pipeline_bridge_0_s1_arbiterlock2 <= unici_core_burst_0_downstream_arbiterlock2;
--debugaccess mux, which is an e_mux
pipeline_bridge_0_s1_debugaccess <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1)) = '1'), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(unici_core_burst_0_downstream_debugaccess))), std_logic_vector'("00000000000000000000000000000000")));
--vhdl renameroo for output signals
pipeline_bridge_0_s1_waitrequest_from_sa <= internal_pipeline_bridge_0_s1_waitrequest_from_sa;
--vhdl renameroo for output signals
unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 <= internal_unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1;
--vhdl renameroo for output signals
unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 <= internal_unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1;
--vhdl renameroo for output signals
unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 <= internal_unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1;
--synthesis translate_off
--pipeline_bridge_0/s1 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--unici_core_burst_0/downstream non-zero arbitrationshare assertion, which is an e_process
process (clk)
VARIABLE write_line20 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((internal_unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 AND to_std_logic((((std_logic_vector'("0000000000000000000000") & (unici_core_burst_0_downstream_arbitrationshare)) = std_logic_vector'("00000000000000000000000000000000"))))) AND enable_nonzero_assertions)) = '1' then
write(write_line20, now);
write(write_line20, string'(": "));
write(write_line20, string'("unici_core_burst_0/downstream drove 0 on its 'arbitrationshare' port while accessing slave pipeline_bridge_0/s1"));
write(output, write_line20.all);
deallocate (write_line20);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_0/downstream non-zero burstcount assertion, which is an e_process
process (clk)
VARIABLE write_line21 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((internal_unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(unici_core_burst_0_downstream_burstcount))) = std_logic_vector'("00000000000000000000000000000000"))))) AND enable_nonzero_assertions)) = '1' then
write(write_line21, now);
write(write_line21, string'(": "));
write(write_line21, string'("unici_core_burst_0/downstream drove 0 on its 'burstcount' port while accessing slave pipeline_bridge_0/s1"));
write(output, write_line21.all);
deallocate (write_line21);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity pipeline_bridge_0_m1_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal d1_int_ctrl_0_avalon_slave_end_xfer : IN STD_LOGIC;
signal int_ctrl_0_avalon_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_slave_waitrequest_from_sa : IN STD_LOGIC;
signal pipeline_bridge_0_m1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal pipeline_bridge_0_m1_burstcount : IN STD_LOGIC;
signal pipeline_bridge_0_m1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pipeline_bridge_0_m1_chipselect : IN STD_LOGIC;
signal pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave : IN STD_LOGIC;
signal pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave : IN STD_LOGIC;
signal pipeline_bridge_0_m1_read : IN STD_LOGIC;
signal pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave : IN STD_LOGIC;
signal pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave : IN STD_LOGIC;
signal pipeline_bridge_0_m1_write : IN STD_LOGIC;
signal pipeline_bridge_0_m1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal pipeline_bridge_0_m1_address_to_slave : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal pipeline_bridge_0_m1_dbs_address : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal pipeline_bridge_0_m1_dbs_write_32 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pipeline_bridge_0_m1_latency_counter : OUT STD_LOGIC;
signal pipeline_bridge_0_m1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_m1_readdatavalid : OUT STD_LOGIC;
signal pipeline_bridge_0_m1_waitrequest : OUT STD_LOGIC
);
end entity pipeline_bridge_0_m1_arbitrator;
architecture europa of pipeline_bridge_0_m1_arbitrator is
signal active_and_waiting_last_time : STD_LOGIC;
signal dbs_32_reg_segment_0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dbs_count_enable : STD_LOGIC;
signal dbs_counter_overflow : STD_LOGIC;
signal internal_pipeline_bridge_0_m1_address_to_slave : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal internal_pipeline_bridge_0_m1_dbs_address : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal internal_pipeline_bridge_0_m1_waitrequest : STD_LOGIC;
signal next_dbs_address : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal p1_dbs_32_reg_segment_0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pipeline_bridge_0_m1_address_last_time : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal pipeline_bridge_0_m1_burstcount_last_time : STD_LOGIC;
signal pipeline_bridge_0_m1_byteenable_last_time : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pipeline_bridge_0_m1_chipselect_last_time : STD_LOGIC;
signal pipeline_bridge_0_m1_dbs_increment : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal pipeline_bridge_0_m1_read_last_time : STD_LOGIC;
signal pipeline_bridge_0_m1_run : STD_LOGIC;
signal pipeline_bridge_0_m1_write_last_time : STD_LOGIC;
signal pipeline_bridge_0_m1_writedata_last_time : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pre_dbs_count_enable : STD_LOGIC;
signal pre_flush_pipeline_bridge_0_m1_readdatavalid : STD_LOGIC;
signal r_1 : STD_LOGIC;
begin
--r_1 master_run cascaded wait assignment, which is an e_assign
r_1 <= Vector_To_Std_Logic((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave OR (((((pipeline_bridge_0_m1_write AND pipeline_bridge_0_m1_chipselect)) AND NOT(or_reduce(pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave))) AND internal_pipeline_bridge_0_m1_dbs_address(2)))) OR NOT pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave OR NOT ((pipeline_bridge_0_m1_read AND pipeline_bridge_0_m1_chipselect)))))) OR ((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT int_ctrl_0_avalon_slave_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_pipeline_bridge_0_m1_dbs_address(2)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((pipeline_bridge_0_m1_read AND pipeline_bridge_0_m1_chipselect)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave OR NOT ((pipeline_bridge_0_m1_write AND pipeline_bridge_0_m1_chipselect)))))) OR ((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT int_ctrl_0_avalon_slave_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_pipeline_bridge_0_m1_dbs_address(2)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((pipeline_bridge_0_m1_write AND pipeline_bridge_0_m1_chipselect)))))))))));
--cascaded wait assignment, which is an e_assign
pipeline_bridge_0_m1_run <= r_1;
--optimize select-logic by passing only those address bits which matter.
internal_pipeline_bridge_0_m1_address_to_slave <= pipeline_bridge_0_m1_address(14 DOWNTO 0);
--pre dbs count enable, which is an e_mux
pre_dbs_count_enable <= Vector_To_Std_Logic((((((((NOT std_logic_vector'("00000000000000000000000000000000")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((pipeline_bridge_0_m1_write AND pipeline_bridge_0_m1_chipselect)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT(or_reduce(pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave))))))) OR (((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave AND ((pipeline_bridge_0_m1_read AND pipeline_bridge_0_m1_chipselect)))))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT int_ctrl_0_avalon_slave_waitrequest_from_sa)))))) OR (((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave AND ((pipeline_bridge_0_m1_write AND pipeline_bridge_0_m1_chipselect)))))) AND std_logic_vector'("00000000000000000000000000000001")) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT int_ctrl_0_avalon_slave_waitrequest_from_sa)))))));
--latent slave read data valids which may be flushed, which is an e_mux
pre_flush_pipeline_bridge_0_m1_readdatavalid <= std_logic'('0');
--latent slave read data valid which is not flushed, which is an e_mux
pipeline_bridge_0_m1_readdatavalid <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000000") OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pre_flush_pipeline_bridge_0_m1_readdatavalid)))) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave AND dbs_counter_overflow)))))));
--input to dbs-32 stored 0, which is an e_mux
p1_dbs_32_reg_segment_0 <= int_ctrl_0_avalon_slave_readdata_from_sa;
--dbs register for dbs-32 segment 0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
dbs_32_reg_segment_0 <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'((dbs_count_enable AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((internal_pipeline_bridge_0_m1_dbs_address(2))))) = std_logic_vector'("00000000000000000000000000000000")))))) = '1' then
dbs_32_reg_segment_0 <= p1_dbs_32_reg_segment_0;
end if;
end if;
end process;
--pipeline_bridge_0/m1 readdata mux, which is an e_mux
pipeline_bridge_0_m1_readdata <= Std_Logic_Vector'(int_ctrl_0_avalon_slave_readdata_from_sa(31 DOWNTO 0) & dbs_32_reg_segment_0);
--mux write dbs 1, which is an e_mux
pipeline_bridge_0_m1_dbs_write_32 <= A_WE_StdLogicVector((std_logic'((internal_pipeline_bridge_0_m1_dbs_address(2))) = '1'), pipeline_bridge_0_m1_writedata(63 DOWNTO 32), pipeline_bridge_0_m1_writedata(31 DOWNTO 0));
--actual waitrequest port, which is an e_assign
internal_pipeline_bridge_0_m1_waitrequest <= NOT pipeline_bridge_0_m1_run;
--latent max counter, which is an e_assign
pipeline_bridge_0_m1_latency_counter <= std_logic'('0');
--dbs count increment, which is an e_mux
pipeline_bridge_0_m1_dbs_increment <= A_EXT (A_WE_StdLogicVector((std_logic'((pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave)) = '1'), std_logic_vector'("00000000000000000000000000000100"), std_logic_vector'("00000000000000000000000000000000")), 3);
--dbs counter overflow, which is an e_assign
dbs_counter_overflow <= internal_pipeline_bridge_0_m1_dbs_address(2) AND NOT((next_dbs_address(2)));
--next master address, which is an e_assign
next_dbs_address <= A_EXT (((std_logic_vector'("0") & (internal_pipeline_bridge_0_m1_dbs_address)) + (std_logic_vector'("0") & (pipeline_bridge_0_m1_dbs_increment))), 3);
--dbs count enable, which is an e_mux
dbs_count_enable <= pre_dbs_count_enable;
--dbs counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
internal_pipeline_bridge_0_m1_dbs_address <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'(dbs_count_enable) = '1' then
internal_pipeline_bridge_0_m1_dbs_address <= next_dbs_address;
end if;
end if;
end process;
--vhdl renameroo for output signals
pipeline_bridge_0_m1_address_to_slave <= internal_pipeline_bridge_0_m1_address_to_slave;
--vhdl renameroo for output signals
pipeline_bridge_0_m1_dbs_address <= internal_pipeline_bridge_0_m1_dbs_address;
--vhdl renameroo for output signals
pipeline_bridge_0_m1_waitrequest <= internal_pipeline_bridge_0_m1_waitrequest;
--synthesis translate_off
--pipeline_bridge_0_m1_address check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pipeline_bridge_0_m1_address_last_time <= std_logic_vector'("000000000000000");
elsif clk'event and clk = '1' then
pipeline_bridge_0_m1_address_last_time <= pipeline_bridge_0_m1_address;
end if;
end process;
--pipeline_bridge_0/m1 waited last time, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
active_and_waiting_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
active_and_waiting_last_time <= internal_pipeline_bridge_0_m1_waitrequest AND pipeline_bridge_0_m1_chipselect;
end if;
end process;
--pipeline_bridge_0_m1_address matches last port_name, which is an e_process
process (clk)
VARIABLE write_line22 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((pipeline_bridge_0_m1_address /= pipeline_bridge_0_m1_address_last_time))))) = '1' then
write(write_line22, now);
write(write_line22, string'(": "));
write(write_line22, string'("pipeline_bridge_0_m1_address did not heed wait!!!"));
write(output, write_line22.all);
deallocate (write_line22);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--pipeline_bridge_0_m1_chipselect check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pipeline_bridge_0_m1_chipselect_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
pipeline_bridge_0_m1_chipselect_last_time <= pipeline_bridge_0_m1_chipselect;
end if;
end process;
--pipeline_bridge_0_m1_chipselect matches last port_name, which is an e_process
process (clk)
VARIABLE write_line23 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(pipeline_bridge_0_m1_chipselect) /= std_logic'(pipeline_bridge_0_m1_chipselect_last_time)))))) = '1' then
write(write_line23, now);
write(write_line23, string'(": "));
write(write_line23, string'("pipeline_bridge_0_m1_chipselect did not heed wait!!!"));
write(output, write_line23.all);
deallocate (write_line23);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--pipeline_bridge_0_m1_burstcount check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pipeline_bridge_0_m1_burstcount_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
pipeline_bridge_0_m1_burstcount_last_time <= pipeline_bridge_0_m1_burstcount;
end if;
end process;
--pipeline_bridge_0_m1_burstcount matches last port_name, which is an e_process
process (clk)
VARIABLE write_line24 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(pipeline_bridge_0_m1_burstcount) /= std_logic'(pipeline_bridge_0_m1_burstcount_last_time)))))) = '1' then
write(write_line24, now);
write(write_line24, string'(": "));
write(write_line24, string'("pipeline_bridge_0_m1_burstcount did not heed wait!!!"));
write(output, write_line24.all);
deallocate (write_line24);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--pipeline_bridge_0_m1_byteenable check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pipeline_bridge_0_m1_byteenable_last_time <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
pipeline_bridge_0_m1_byteenable_last_time <= pipeline_bridge_0_m1_byteenable;
end if;
end process;
--pipeline_bridge_0_m1_byteenable matches last port_name, which is an e_process
process (clk)
VARIABLE write_line25 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((pipeline_bridge_0_m1_byteenable /= pipeline_bridge_0_m1_byteenable_last_time))))) = '1' then
write(write_line25, now);
write(write_line25, string'(": "));
write(write_line25, string'("pipeline_bridge_0_m1_byteenable did not heed wait!!!"));
write(output, write_line25.all);
deallocate (write_line25);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--pipeline_bridge_0_m1_read check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pipeline_bridge_0_m1_read_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
pipeline_bridge_0_m1_read_last_time <= pipeline_bridge_0_m1_read;
end if;
end process;
--pipeline_bridge_0_m1_read matches last port_name, which is an e_process
process (clk)
VARIABLE write_line26 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(pipeline_bridge_0_m1_read) /= std_logic'(pipeline_bridge_0_m1_read_last_time)))))) = '1' then
write(write_line26, now);
write(write_line26, string'(": "));
write(write_line26, string'("pipeline_bridge_0_m1_read did not heed wait!!!"));
write(output, write_line26.all);
deallocate (write_line26);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--pipeline_bridge_0_m1_write check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pipeline_bridge_0_m1_write_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
pipeline_bridge_0_m1_write_last_time <= pipeline_bridge_0_m1_write;
end if;
end process;
--pipeline_bridge_0_m1_write matches last port_name, which is an e_process
process (clk)
VARIABLE write_line27 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(pipeline_bridge_0_m1_write) /= std_logic'(pipeline_bridge_0_m1_write_last_time)))))) = '1' then
write(write_line27, now);
write(write_line27, string'(": "));
write(write_line27, string'("pipeline_bridge_0_m1_write did not heed wait!!!"));
write(output, write_line27.all);
deallocate (write_line27);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--pipeline_bridge_0_m1_writedata check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
pipeline_bridge_0_m1_writedata_last_time <= std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
pipeline_bridge_0_m1_writedata_last_time <= pipeline_bridge_0_m1_writedata;
end if;
end process;
--pipeline_bridge_0_m1_writedata matches last port_name, which is an e_process
process (clk)
VARIABLE write_line28 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((active_and_waiting_last_time AND to_std_logic(((pipeline_bridge_0_m1_writedata /= pipeline_bridge_0_m1_writedata_last_time)))) AND ((pipeline_bridge_0_m1_write AND pipeline_bridge_0_m1_chipselect)))) = '1' then
write(write_line28, now);
write(write_line28, string'(": "));
write(write_line28, string'("pipeline_bridge_0_m1_writedata did not heed wait!!!"));
write(output, write_line28.all);
deallocate (write_line28);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pipeline_bridge_0_bridge_arbitrator is
end entity pipeline_bridge_0_bridge_arbitrator;
architecture europa of pipeline_bridge_0_bridge_arbitrator is
begin
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_master_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal spi_master_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal spi_master_0_avalon_slave_0_waitrequest : IN STD_LOGIC;
-- outputs:
signal d1_spi_master_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_spi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal spi_master_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal spi_master_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal spi_master_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal spi_master_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal spi_master_0_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal spi_master_0_avalon_slave_0_write : OUT STD_LOGIC;
signal spi_master_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end entity spi_master_0_avalon_slave_0_arbitrator;
architecture europa of spi_master_0_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_spi_master_0_avalon_slave_0 : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0_segment_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0_segment_1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_spi_master_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal internal_int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0 : STD_LOGIC;
signal internal_spi_master_0_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal shifted_address_to_spi_master_0_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal spi_master_0_avalon_slave_0_allgrants : STD_LOGIC;
signal spi_master_0_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal spi_master_0_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal spi_master_0_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal spi_master_0_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal spi_master_0_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal spi_master_0_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal spi_master_0_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal spi_master_0_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal spi_master_0_avalon_slave_0_begins_xfer : STD_LOGIC;
signal spi_master_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal spi_master_0_avalon_slave_0_firsttransfer : STD_LOGIC;
signal spi_master_0_avalon_slave_0_grant_vector : STD_LOGIC;
signal spi_master_0_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal spi_master_0_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal spi_master_0_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal spi_master_0_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal spi_master_0_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal spi_master_0_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal spi_master_0_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal spi_master_0_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal spi_master_0_avalon_slave_0_waits_for_read : STD_LOGIC;
signal spi_master_0_avalon_slave_0_waits_for_write : STD_LOGIC;
signal wait_for_spi_master_0_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT spi_master_0_avalon_slave_0_end_xfer;
end if;
end process;
spi_master_0_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0);
--assign spi_master_0_avalon_slave_0_readdata_from_sa = spi_master_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
spi_master_0_avalon_slave_0_readdata_from_sa <= spi_master_0_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 11) & std_logic_vector'("00000000000")) = std_logic_vector'("100000000000000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--assign spi_master_0_avalon_slave_0_waitrequest_from_sa = spi_master_0_avalon_slave_0_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_spi_master_0_avalon_slave_0_waitrequest_from_sa <= spi_master_0_avalon_slave_0_waitrequest;
--spi_master_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
spi_master_0_avalon_slave_0_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0)) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000001")), 2);
--spi_master_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
spi_master_0_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0;
--spi_master_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
spi_master_0_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--spi_master_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
spi_master_0_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(spi_master_0_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (spi_master_0_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(spi_master_0_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (spi_master_0_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--spi_master_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
spi_master_0_avalon_slave_0_allgrants <= spi_master_0_avalon_slave_0_grant_vector;
--spi_master_0_avalon_slave_0_end_xfer assignment, which is an e_assign
spi_master_0_avalon_slave_0_end_xfer <= NOT ((spi_master_0_avalon_slave_0_waits_for_read OR spi_master_0_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_spi_master_0_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_spi_master_0_avalon_slave_0 <= spi_master_0_avalon_slave_0_end_xfer AND (((NOT spi_master_0_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--spi_master_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
spi_master_0_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_spi_master_0_avalon_slave_0 AND spi_master_0_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_spi_master_0_avalon_slave_0 AND NOT spi_master_0_avalon_slave_0_non_bursting_master_requests));
--spi_master_0_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
spi_master_0_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(spi_master_0_avalon_slave_0_arb_counter_enable) = '1' then
spi_master_0_avalon_slave_0_arb_share_counter <= spi_master_0_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--spi_master_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
spi_master_0_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((spi_master_0_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_spi_master_0_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_spi_master_0_avalon_slave_0 AND NOT spi_master_0_avalon_slave_0_non_bursting_master_requests)))) = '1' then
spi_master_0_avalon_slave_0_slavearbiterlockenable <= or_reduce(spi_master_0_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master spi_master_0/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= spi_master_0_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--spi_master_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
spi_master_0_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(spi_master_0_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master spi_master_0/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= spi_master_0_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--spi_master_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
spi_master_0_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0 AND NOT (((NOT(or_reduce(internal_int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0))) AND int_ctrl_0_avalon_master_write));
--spi_master_0_avalon_slave_0_writedata mux, which is an e_mux
spi_master_0_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_dbs_write_16;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant spi_master_0/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_spi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0;
--allow new arb cycle for spi_master_0/avalon_slave_0, which is an e_assign
spi_master_0_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
spi_master_0_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
spi_master_0_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~spi_master_0_avalon_slave_0_reset assignment, which is an e_assign
spi_master_0_avalon_slave_0_reset <= NOT reset_n;
--spi_master_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
spi_master_0_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(spi_master_0_avalon_slave_0_begins_xfer) = '1'), spi_master_0_avalon_slave_0_unreg_firsttransfer, spi_master_0_avalon_slave_0_reg_firsttransfer);
--spi_master_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
spi_master_0_avalon_slave_0_unreg_firsttransfer <= NOT ((spi_master_0_avalon_slave_0_slavearbiterlockenable AND spi_master_0_avalon_slave_0_any_continuerequest));
--spi_master_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
spi_master_0_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(spi_master_0_avalon_slave_0_begins_xfer) = '1' then
spi_master_0_avalon_slave_0_reg_firsttransfer <= spi_master_0_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--spi_master_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
spi_master_0_avalon_slave_0_beginbursttransfer_internal <= spi_master_0_avalon_slave_0_begins_xfer;
--spi_master_0_avalon_slave_0_write assignment, which is an e_mux
spi_master_0_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_spi_master_0_avalon_slave_0_from_int_ctrl_0_avalon_master <= A_EXT (Std_Logic_Vector'(A_SRL(int_ctrl_0_avalon_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")) & A_ToStdLogicVector(int_ctrl_0_avalon_master_dbs_address(1)) & A_ToStdLogicVector(std_logic'('0'))), 15);
--spi_master_0_avalon_slave_0_address mux, which is an e_mux
spi_master_0_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_spi_master_0_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000001")), 10);
--d1_spi_master_0_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_spi_master_0_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_spi_master_0_avalon_slave_0_end_xfer <= spi_master_0_avalon_slave_0_end_xfer;
end if;
end process;
--spi_master_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
spi_master_0_avalon_slave_0_waits_for_read <= spi_master_0_avalon_slave_0_in_a_read_cycle AND internal_spi_master_0_avalon_slave_0_waitrequest_from_sa;
--spi_master_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
spi_master_0_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= spi_master_0_avalon_slave_0_in_a_read_cycle;
--spi_master_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
spi_master_0_avalon_slave_0_waits_for_write <= spi_master_0_avalon_slave_0_in_a_write_cycle AND internal_spi_master_0_avalon_slave_0_waitrequest_from_sa;
--spi_master_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
spi_master_0_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= spi_master_0_avalon_slave_0_in_a_write_cycle;
wait_for_spi_master_0_avalon_slave_0_counter <= std_logic'('0');
--spi_master_0_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
spi_master_0_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (internal_int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 2);
(int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0_segment_1(1), int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0_segment_1(0), int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0_segment_0(1), int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0_segment_0(0)) <= int_ctrl_0_avalon_master_byteenable;
internal_int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_dbs_address(1)))) = std_logic_vector'("00000000000000000000000000000000"))), int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0_segment_0, int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0_segment_1);
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0;
--vhdl renameroo for output signals
spi_master_0_avalon_slave_0_waitrequest_from_sa <= internal_spi_master_0_avalon_slave_0_waitrequest_from_sa;
--synthesis translate_off
--spi_master_0/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity twi_master_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal d1_twi_master_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_twi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal twi_master_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal twi_master_0_avalon_slave_0_write : OUT STD_LOGIC;
signal twi_master_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end entity twi_master_0_avalon_slave_0_arbitrator;
architecture europa of twi_master_0_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_twi_master_0_avalon_slave_0 : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0_segment_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0_segment_1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_twi_master_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal internal_int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_twi_master_0_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal twi_master_0_avalon_slave_0_allgrants : STD_LOGIC;
signal twi_master_0_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal twi_master_0_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal twi_master_0_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal twi_master_0_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal twi_master_0_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_0_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_0_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_0_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal twi_master_0_avalon_slave_0_begins_xfer : STD_LOGIC;
signal twi_master_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal twi_master_0_avalon_slave_0_firsttransfer : STD_LOGIC;
signal twi_master_0_avalon_slave_0_grant_vector : STD_LOGIC;
signal twi_master_0_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal twi_master_0_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal twi_master_0_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal twi_master_0_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal twi_master_0_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal twi_master_0_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal twi_master_0_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal twi_master_0_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal twi_master_0_avalon_slave_0_waits_for_read : STD_LOGIC;
signal twi_master_0_avalon_slave_0_waits_for_write : STD_LOGIC;
signal wait_for_twi_master_0_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT twi_master_0_avalon_slave_0_end_xfer;
end if;
end process;
twi_master_0_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0);
--assign twi_master_0_avalon_slave_0_readdata_from_sa = twi_master_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
twi_master_0_avalon_slave_0_readdata_from_sa <= twi_master_0_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 3) & std_logic_vector'("000")) = std_logic_vector'("100100000000000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--twi_master_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
twi_master_0_avalon_slave_0_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0)) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000001")), 2);
--twi_master_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
twi_master_0_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0;
--twi_master_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
twi_master_0_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--twi_master_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
twi_master_0_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(twi_master_0_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (twi_master_0_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(twi_master_0_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (twi_master_0_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--twi_master_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
twi_master_0_avalon_slave_0_allgrants <= twi_master_0_avalon_slave_0_grant_vector;
--twi_master_0_avalon_slave_0_end_xfer assignment, which is an e_assign
twi_master_0_avalon_slave_0_end_xfer <= NOT ((twi_master_0_avalon_slave_0_waits_for_read OR twi_master_0_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_twi_master_0_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_twi_master_0_avalon_slave_0 <= twi_master_0_avalon_slave_0_end_xfer AND (((NOT twi_master_0_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--twi_master_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
twi_master_0_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_twi_master_0_avalon_slave_0 AND twi_master_0_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_twi_master_0_avalon_slave_0 AND NOT twi_master_0_avalon_slave_0_non_bursting_master_requests));
--twi_master_0_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
twi_master_0_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(twi_master_0_avalon_slave_0_arb_counter_enable) = '1' then
twi_master_0_avalon_slave_0_arb_share_counter <= twi_master_0_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--twi_master_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
twi_master_0_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((twi_master_0_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_twi_master_0_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_twi_master_0_avalon_slave_0 AND NOT twi_master_0_avalon_slave_0_non_bursting_master_requests)))) = '1' then
twi_master_0_avalon_slave_0_slavearbiterlockenable <= or_reduce(twi_master_0_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master twi_master_0/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= twi_master_0_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--twi_master_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
twi_master_0_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(twi_master_0_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master twi_master_0/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= twi_master_0_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--twi_master_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
twi_master_0_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0 AND NOT (((NOT(or_reduce(internal_int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0))) AND int_ctrl_0_avalon_master_write));
--twi_master_0_avalon_slave_0_writedata mux, which is an e_mux
twi_master_0_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_dbs_write_16;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant twi_master_0/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_twi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0;
--allow new arb cycle for twi_master_0/avalon_slave_0, which is an e_assign
twi_master_0_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
twi_master_0_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
twi_master_0_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~twi_master_0_avalon_slave_0_reset assignment, which is an e_assign
twi_master_0_avalon_slave_0_reset <= NOT reset_n;
--twi_master_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
twi_master_0_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(twi_master_0_avalon_slave_0_begins_xfer) = '1'), twi_master_0_avalon_slave_0_unreg_firsttransfer, twi_master_0_avalon_slave_0_reg_firsttransfer);
--twi_master_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
twi_master_0_avalon_slave_0_unreg_firsttransfer <= NOT ((twi_master_0_avalon_slave_0_slavearbiterlockenable AND twi_master_0_avalon_slave_0_any_continuerequest));
--twi_master_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
twi_master_0_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(twi_master_0_avalon_slave_0_begins_xfer) = '1' then
twi_master_0_avalon_slave_0_reg_firsttransfer <= twi_master_0_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--twi_master_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
twi_master_0_avalon_slave_0_beginbursttransfer_internal <= twi_master_0_avalon_slave_0_begins_xfer;
--twi_master_0_avalon_slave_0_write assignment, which is an e_mux
twi_master_0_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_twi_master_0_avalon_slave_0_from_int_ctrl_0_avalon_master <= A_EXT (Std_Logic_Vector'(A_SRL(int_ctrl_0_avalon_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")) & A_ToStdLogicVector(int_ctrl_0_avalon_master_dbs_address(1)) & A_ToStdLogicVector(std_logic'('0'))), 15);
--twi_master_0_avalon_slave_0_address mux, which is an e_mux
twi_master_0_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_twi_master_0_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000001")), 2);
--d1_twi_master_0_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_twi_master_0_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_twi_master_0_avalon_slave_0_end_xfer <= twi_master_0_avalon_slave_0_end_xfer;
end if;
end process;
--twi_master_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
twi_master_0_avalon_slave_0_waits_for_read <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(twi_master_0_avalon_slave_0_in_a_read_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--twi_master_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
twi_master_0_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= twi_master_0_avalon_slave_0_in_a_read_cycle;
--twi_master_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
twi_master_0_avalon_slave_0_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(twi_master_0_avalon_slave_0_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--twi_master_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
twi_master_0_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= twi_master_0_avalon_slave_0_in_a_write_cycle;
wait_for_twi_master_0_avalon_slave_0_counter <= std_logic'('0');
--twi_master_0_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
twi_master_0_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (internal_int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 2);
(int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0_segment_1(1), int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0_segment_1(0), int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0_segment_0(1), int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0_segment_0(0)) <= int_ctrl_0_avalon_master_byteenable;
internal_int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_dbs_address(1)))) = std_logic_vector'("00000000000000000000000000000000"))), int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0_segment_0, int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0_segment_1);
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0;
--synthesis translate_off
--twi_master_0/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity twi_master_0_avalon_streaming_sink_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_streaming_source_valid : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_0_avalon_streaming_sink_ready : IN STD_LOGIC;
-- outputs:
signal twi_master_0_avalon_streaming_sink_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_0_avalon_streaming_sink_ready_from_sa : OUT STD_LOGIC;
signal twi_master_0_avalon_streaming_sink_valid : OUT STD_LOGIC
);
end entity twi_master_0_avalon_streaming_sink_arbitrator;
architecture europa of twi_master_0_avalon_streaming_sink_arbitrator is
begin
--mux twi_master_0_avalon_streaming_sink_data, which is an e_mux
twi_master_0_avalon_streaming_sink_data <= fifo_out_8b_sync_0_avalon_streaming_source_data;
--assign twi_master_0_avalon_streaming_sink_ready_from_sa = twi_master_0_avalon_streaming_sink_ready so that symbol knows where to group signals which may go to master only, which is an e_assign
twi_master_0_avalon_streaming_sink_ready_from_sa <= twi_master_0_avalon_streaming_sink_ready;
--mux twi_master_0_avalon_streaming_sink_valid, which is an e_mux
twi_master_0_avalon_streaming_sink_valid <= fifo_out_8b_sync_0_avalon_streaming_source_valid;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity twi_master_0_avalon_streaming_source_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_0_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_0_avalon_streaming_source_valid : IN STD_LOGIC;
-- outputs:
signal twi_master_0_avalon_streaming_source_ready : OUT STD_LOGIC
);
end entity twi_master_0_avalon_streaming_source_arbitrator;
architecture europa of twi_master_0_avalon_streaming_source_arbitrator is
begin
--mux twi_master_0_avalon_streaming_source_ready, which is an e_mux
twi_master_0_avalon_streaming_source_ready <= fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity twi_master_1_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_1_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal d1_twi_master_1_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_twi_master_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0 : OUT STD_LOGIC;
signal twi_master_1_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_1_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_1_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_1_avalon_slave_0_reset : OUT STD_LOGIC;
signal twi_master_1_avalon_slave_0_write : OUT STD_LOGIC;
signal twi_master_1_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end entity twi_master_1_avalon_slave_0_arbitrator;
architecture europa of twi_master_1_avalon_slave_0_arbitrator is
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_twi_master_1_avalon_slave_0 : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock : STD_LOGIC;
signal int_ctrl_0_avalon_master_arbiterlock2 : STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0_segment_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0_segment_1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_continuerequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_saved_grant_twi_master_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal internal_int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 : STD_LOGIC;
signal internal_int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0 : STD_LOGIC;
signal shifted_address_to_twi_master_1_avalon_slave_0_from_int_ctrl_0_avalon_master : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal twi_master_1_avalon_slave_0_allgrants : STD_LOGIC;
signal twi_master_1_avalon_slave_0_allow_new_arb_cycle : STD_LOGIC;
signal twi_master_1_avalon_slave_0_any_bursting_master_saved_grant : STD_LOGIC;
signal twi_master_1_avalon_slave_0_any_continuerequest : STD_LOGIC;
signal twi_master_1_avalon_slave_0_arb_counter_enable : STD_LOGIC;
signal twi_master_1_avalon_slave_0_arb_share_counter : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_1_avalon_slave_0_arb_share_counter_next_value : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_1_avalon_slave_0_arb_share_set_values : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_1_avalon_slave_0_beginbursttransfer_internal : STD_LOGIC;
signal twi_master_1_avalon_slave_0_begins_xfer : STD_LOGIC;
signal twi_master_1_avalon_slave_0_end_xfer : STD_LOGIC;
signal twi_master_1_avalon_slave_0_firsttransfer : STD_LOGIC;
signal twi_master_1_avalon_slave_0_grant_vector : STD_LOGIC;
signal twi_master_1_avalon_slave_0_in_a_read_cycle : STD_LOGIC;
signal twi_master_1_avalon_slave_0_in_a_write_cycle : STD_LOGIC;
signal twi_master_1_avalon_slave_0_master_qreq_vector : STD_LOGIC;
signal twi_master_1_avalon_slave_0_non_bursting_master_requests : STD_LOGIC;
signal twi_master_1_avalon_slave_0_reg_firsttransfer : STD_LOGIC;
signal twi_master_1_avalon_slave_0_slavearbiterlockenable : STD_LOGIC;
signal twi_master_1_avalon_slave_0_slavearbiterlockenable2 : STD_LOGIC;
signal twi_master_1_avalon_slave_0_unreg_firsttransfer : STD_LOGIC;
signal twi_master_1_avalon_slave_0_waits_for_read : STD_LOGIC;
signal twi_master_1_avalon_slave_0_waits_for_write : STD_LOGIC;
signal wait_for_twi_master_1_avalon_slave_0_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT twi_master_1_avalon_slave_0_end_xfer;
end if;
end process;
twi_master_1_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0);
--assign twi_master_1_avalon_slave_0_readdata_from_sa = twi_master_1_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
twi_master_1_avalon_slave_0_readdata_from_sa <= twi_master_1_avalon_slave_0_readdata;
internal_int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(int_ctrl_0_avalon_master_address_to_slave(14 DOWNTO 3) & std_logic_vector'("000")) = std_logic_vector'("100100001000000")))) AND ((int_ctrl_0_avalon_master_read OR int_ctrl_0_avalon_master_write));
--twi_master_1_avalon_slave_0_arb_share_counter set values, which is an e_mux
twi_master_1_avalon_slave_0_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0)) = '1'), std_logic_vector'("00000000000000000000000000000010"), std_logic_vector'("00000000000000000000000000000001")), 2);
--twi_master_1_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
twi_master_1_avalon_slave_0_non_bursting_master_requests <= internal_int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0;
--twi_master_1_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
twi_master_1_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
--twi_master_1_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
twi_master_1_avalon_slave_0_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(twi_master_1_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (twi_master_1_avalon_slave_0_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(twi_master_1_avalon_slave_0_arb_share_counter)) = '1'), (((std_logic_vector'("0000000000000000000000000000000") & (twi_master_1_avalon_slave_0_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 2);
--twi_master_1_avalon_slave_0_allgrants all slave grants, which is an e_mux
twi_master_1_avalon_slave_0_allgrants <= twi_master_1_avalon_slave_0_grant_vector;
--twi_master_1_avalon_slave_0_end_xfer assignment, which is an e_assign
twi_master_1_avalon_slave_0_end_xfer <= NOT ((twi_master_1_avalon_slave_0_waits_for_read OR twi_master_1_avalon_slave_0_waits_for_write));
--end_xfer_arb_share_counter_term_twi_master_1_avalon_slave_0 arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_twi_master_1_avalon_slave_0 <= twi_master_1_avalon_slave_0_end_xfer AND (((NOT twi_master_1_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--twi_master_1_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
twi_master_1_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_twi_master_1_avalon_slave_0 AND twi_master_1_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_twi_master_1_avalon_slave_0 AND NOT twi_master_1_avalon_slave_0_non_bursting_master_requests));
--twi_master_1_avalon_slave_0_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
twi_master_1_avalon_slave_0_arb_share_counter <= std_logic_vector'("00");
elsif clk'event and clk = '1' then
if std_logic'(twi_master_1_avalon_slave_0_arb_counter_enable) = '1' then
twi_master_1_avalon_slave_0_arb_share_counter <= twi_master_1_avalon_slave_0_arb_share_counter_next_value;
end if;
end if;
end process;
--twi_master_1_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
twi_master_1_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((twi_master_1_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_twi_master_1_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_twi_master_1_avalon_slave_0 AND NOT twi_master_1_avalon_slave_0_non_bursting_master_requests)))) = '1' then
twi_master_1_avalon_slave_0_slavearbiterlockenable <= or_reduce(twi_master_1_avalon_slave_0_arb_share_counter_next_value);
end if;
end if;
end process;
--int_ctrl_0/avalon_master twi_master_1/avalon_slave_0 arbiterlock, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock <= twi_master_1_avalon_slave_0_slavearbiterlockenable AND int_ctrl_0_avalon_master_continuerequest;
--twi_master_1_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
twi_master_1_avalon_slave_0_slavearbiterlockenable2 <= or_reduce(twi_master_1_avalon_slave_0_arb_share_counter_next_value);
--int_ctrl_0/avalon_master twi_master_1/avalon_slave_0 arbiterlock2, which is an e_assign
int_ctrl_0_avalon_master_arbiterlock2 <= twi_master_1_avalon_slave_0_slavearbiterlockenable2 AND int_ctrl_0_avalon_master_continuerequest;
--twi_master_1_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
twi_master_1_avalon_slave_0_any_continuerequest <= std_logic'('1');
--int_ctrl_0_avalon_master_continuerequest continued request, which is an e_assign
int_ctrl_0_avalon_master_continuerequest <= std_logic'('1');
internal_int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0 AND NOT (((NOT(or_reduce(internal_int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0))) AND int_ctrl_0_avalon_master_write));
--twi_master_1_avalon_slave_0_writedata mux, which is an e_mux
twi_master_1_avalon_slave_0_writedata <= int_ctrl_0_avalon_master_dbs_write_16;
--master is always granted when requested
internal_int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0;
--int_ctrl_0/avalon_master saved-grant twi_master_1/avalon_slave_0, which is an e_assign
int_ctrl_0_avalon_master_saved_grant_twi_master_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0;
--allow new arb cycle for twi_master_1/avalon_slave_0, which is an e_assign
twi_master_1_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
twi_master_1_avalon_slave_0_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
twi_master_1_avalon_slave_0_master_qreq_vector <= std_logic'('1');
--~twi_master_1_avalon_slave_0_reset assignment, which is an e_assign
twi_master_1_avalon_slave_0_reset <= NOT reset_n;
--twi_master_1_avalon_slave_0_firsttransfer first transaction, which is an e_assign
twi_master_1_avalon_slave_0_firsttransfer <= A_WE_StdLogic((std_logic'(twi_master_1_avalon_slave_0_begins_xfer) = '1'), twi_master_1_avalon_slave_0_unreg_firsttransfer, twi_master_1_avalon_slave_0_reg_firsttransfer);
--twi_master_1_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
twi_master_1_avalon_slave_0_unreg_firsttransfer <= NOT ((twi_master_1_avalon_slave_0_slavearbiterlockenable AND twi_master_1_avalon_slave_0_any_continuerequest));
--twi_master_1_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
twi_master_1_avalon_slave_0_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(twi_master_1_avalon_slave_0_begins_xfer) = '1' then
twi_master_1_avalon_slave_0_reg_firsttransfer <= twi_master_1_avalon_slave_0_unreg_firsttransfer;
end if;
end if;
end process;
--twi_master_1_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
twi_master_1_avalon_slave_0_beginbursttransfer_internal <= twi_master_1_avalon_slave_0_begins_xfer;
--twi_master_1_avalon_slave_0_write assignment, which is an e_mux
twi_master_1_avalon_slave_0_write <= internal_int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
shifted_address_to_twi_master_1_avalon_slave_0_from_int_ctrl_0_avalon_master <= A_EXT (Std_Logic_Vector'(A_SRL(int_ctrl_0_avalon_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")) & A_ToStdLogicVector(int_ctrl_0_avalon_master_dbs_address(1)) & A_ToStdLogicVector(std_logic'('0'))), 15);
--twi_master_1_avalon_slave_0_address mux, which is an e_mux
twi_master_1_avalon_slave_0_address <= A_EXT (A_SRL(shifted_address_to_twi_master_1_avalon_slave_0_from_int_ctrl_0_avalon_master,std_logic_vector'("00000000000000000000000000000001")), 2);
--d1_twi_master_1_avalon_slave_0_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_twi_master_1_avalon_slave_0_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_twi_master_1_avalon_slave_0_end_xfer <= twi_master_1_avalon_slave_0_end_xfer;
end if;
end process;
--twi_master_1_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
twi_master_1_avalon_slave_0_waits_for_read <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(twi_master_1_avalon_slave_0_in_a_read_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--twi_master_1_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
twi_master_1_avalon_slave_0_in_a_read_cycle <= internal_int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 AND int_ctrl_0_avalon_master_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= twi_master_1_avalon_slave_0_in_a_read_cycle;
--twi_master_1_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
twi_master_1_avalon_slave_0_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(twi_master_1_avalon_slave_0_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
--twi_master_1_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
twi_master_1_avalon_slave_0_in_a_write_cycle <= internal_int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 AND int_ctrl_0_avalon_master_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= twi_master_1_avalon_slave_0_in_a_write_cycle;
wait_for_twi_master_1_avalon_slave_0_counter <= std_logic'('0');
--twi_master_1_avalon_slave_0_byteenable byte enable port mux, which is an e_mux
twi_master_1_avalon_slave_0_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0)) = '1'), (std_logic_vector'("000000000000000000000000000000") & (internal_int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 2);
(int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0_segment_1(1), int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0_segment_1(0), int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0_segment_0(1), int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0_segment_0(0)) <= int_ctrl_0_avalon_master_byteenable;
internal_int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(int_ctrl_0_avalon_master_dbs_address(1)))) = std_logic_vector'("00000000000000000000000000000000"))), int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0_segment_0, int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0_segment_1);
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0;
--vhdl renameroo for output signals
int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0 <= internal_int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0;
--synthesis translate_off
--twi_master_1/avalon_slave_0 enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity twi_master_1_avalon_streaming_sink_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_streaming_source_valid : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_1_avalon_streaming_sink_ready : IN STD_LOGIC;
-- outputs:
signal twi_master_1_avalon_streaming_sink_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_1_avalon_streaming_sink_ready_from_sa : OUT STD_LOGIC;
signal twi_master_1_avalon_streaming_sink_valid : OUT STD_LOGIC
);
end entity twi_master_1_avalon_streaming_sink_arbitrator;
architecture europa of twi_master_1_avalon_streaming_sink_arbitrator is
begin
--mux twi_master_1_avalon_streaming_sink_data, which is an e_mux
twi_master_1_avalon_streaming_sink_data <= fifo_out_8b_sync_1_avalon_streaming_source_data;
--assign twi_master_1_avalon_streaming_sink_ready_from_sa = twi_master_1_avalon_streaming_sink_ready so that symbol knows where to group signals which may go to master only, which is an e_assign
twi_master_1_avalon_streaming_sink_ready_from_sa <= twi_master_1_avalon_streaming_sink_ready;
--mux twi_master_1_avalon_streaming_sink_valid, which is an e_mux
twi_master_1_avalon_streaming_sink_valid <= fifo_out_8b_sync_1_avalon_streaming_source_valid;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity twi_master_1_avalon_streaming_source_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_1_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_1_avalon_streaming_source_valid : IN STD_LOGIC;
-- outputs:
signal twi_master_1_avalon_streaming_source_ready : OUT STD_LOGIC
);
end entity twi_master_1_avalon_streaming_source_arbitrator;
architecture europa of twi_master_1_avalon_streaming_source_arbitrator is
begin
--mux twi_master_1_avalon_streaming_source_ready, which is an e_mux
twi_master_1_avalon_streaming_source_ready <= fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity burstcount_fifo_for_unici_core_burst_0_upstream_module is
port (
-- inputs:
signal clear_fifo : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal read : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal empty : OUT STD_LOGIC;
signal fifo_contains_ones_n : OUT STD_LOGIC;
signal full : OUT STD_LOGIC
);
end entity burstcount_fifo_for_unici_core_burst_0_upstream_module;
architecture europa of burstcount_fifo_for_unici_core_burst_0_upstream_module is
signal full_0 : STD_LOGIC;
signal full_1 : STD_LOGIC;
signal full_2 : STD_LOGIC;
signal full_3 : STD_LOGIC;
signal full_4 : STD_LOGIC;
signal full_5 : STD_LOGIC;
signal how_many_ones : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal one_count_minus_one : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal one_count_plus_one : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal p0_full_0 : STD_LOGIC;
signal p0_stage_0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal p1_full_1 : STD_LOGIC;
signal p1_stage_1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal p2_full_2 : STD_LOGIC;
signal p2_stage_2 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal p3_full_3 : STD_LOGIC;
signal p3_stage_3 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal p4_full_4 : STD_LOGIC;
signal p4_stage_4 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal stage_0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal stage_1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal stage_2 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal stage_3 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal stage_4 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal updated_one_count : STD_LOGIC_VECTOR (3 DOWNTO 0);
begin
data_out <= stage_0;
full <= full_4;
empty <= NOT(full_0);
full_5 <= std_logic'('0');
--data_4, which is an e_mux
p4_stage_4 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_5 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, data_in);
--data_reg_4, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_4 <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_4))))) = '1' then
if std_logic'(((sync_reset AND full_4) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_5))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_4 <= std_logic_vector'("0000000000");
else
stage_4 <= p4_stage_4;
end if;
end if;
end if;
end process;
--control_4, which is an e_mux
p4_full_4 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_3))), std_logic_vector'("00000000000000000000000000000000")));
--control_reg_4, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_4 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_4 <= std_logic'('0');
else
full_4 <= p4_full_4;
end if;
end if;
end if;
end process;
--data_3, which is an e_mux
p3_stage_3 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_4 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_4);
--data_reg_3, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_3 <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_3))))) = '1' then
if std_logic'(((sync_reset AND full_3) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_4))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_3 <= std_logic_vector'("0000000000");
else
stage_3 <= p3_stage_3;
end if;
end if;
end if;
end process;
--control_3, which is an e_mux
p3_full_3 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_2, full_4);
--control_reg_3, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_3 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_3 <= std_logic'('0');
else
full_3 <= p3_full_3;
end if;
end if;
end if;
end process;
--data_2, which is an e_mux
p2_stage_2 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_3 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_3);
--data_reg_2, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_2 <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_2))))) = '1' then
if std_logic'(((sync_reset AND full_2) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_3))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_2 <= std_logic_vector'("0000000000");
else
stage_2 <= p2_stage_2;
end if;
end if;
end if;
end process;
--control_2, which is an e_mux
p2_full_2 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_1, full_3);
--control_reg_2, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_2 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_2 <= std_logic'('0');
else
full_2 <= p2_full_2;
end if;
end if;
end if;
end process;
--data_1, which is an e_mux
p1_stage_1 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_2 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_2);
--data_reg_1, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_1 <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_1))))) = '1' then
if std_logic'(((sync_reset AND full_1) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_2))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_1 <= std_logic_vector'("0000000000");
else
stage_1 <= p1_stage_1;
end if;
end if;
end if;
end process;
--control_1, which is an e_mux
p1_full_1 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_0, full_2);
--control_reg_1, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_1 <= std_logic'('0');
else
full_1 <= p1_full_1;
end if;
end if;
end if;
end process;
--data_0, which is an e_mux
p0_stage_0 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_1 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_1);
--data_reg_0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_0 <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(((sync_reset AND full_0) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_0 <= std_logic_vector'("0000000000");
else
stage_0 <= p0_stage_0;
end if;
end if;
end if;
end process;
--control_0, which is an e_mux
p0_full_0 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), std_logic_vector'("00000000000000000000000000000001"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1)))));
--control_reg_0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_0 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'((clear_fifo AND NOT write)) = '1' then
full_0 <= std_logic'('0');
else
full_0 <= p0_full_0;
end if;
end if;
end if;
end process;
one_count_plus_one <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (how_many_ones)) + std_logic_vector'("000000000000000000000000000000001")), 4);
one_count_minus_one <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (how_many_ones)) - std_logic_vector'("000000000000000000000000000000001")), 4);
--updated_one_count, which is an e_mux
updated_one_count <= A_EXT (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND NOT(write)))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND write))) = '1'), (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(or_reduce(data_in)))), A_WE_StdLogicVector((std_logic'(((((read AND (or_reduce(data_in))) AND write) AND (or_reduce(stage_0))))) = '1'), how_many_ones, A_WE_StdLogicVector((std_logic'(((write AND (or_reduce(data_in))))) = '1'), one_count_plus_one, A_WE_StdLogicVector((std_logic'(((read AND (or_reduce(stage_0))))) = '1'), one_count_minus_one, how_many_ones))))))), 4);
--counts how many ones in the data pipeline, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
how_many_ones <= std_logic_vector'("0000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then
how_many_ones <= updated_one_count;
end if;
end if;
end process;
--this fifo contains ones in the data pipeline, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_contains_ones_n <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then
fifo_contains_ones_n <= NOT (or_reduce(updated_one_count));
end if;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_0_upstream_module is
port (
-- inputs:
signal clear_fifo : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal read : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC;
signal empty : OUT STD_LOGIC;
signal fifo_contains_ones_n : OUT STD_LOGIC;
signal full : OUT STD_LOGIC
);
end entity rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_0_upstream_module;
architecture europa of rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_0_upstream_module is
signal full_0 : STD_LOGIC;
signal full_1 : STD_LOGIC;
signal full_2 : STD_LOGIC;
signal full_3 : STD_LOGIC;
signal full_4 : STD_LOGIC;
signal full_5 : STD_LOGIC;
signal how_many_ones : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal one_count_minus_one : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal one_count_plus_one : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal p0_full_0 : STD_LOGIC;
signal p0_stage_0 : STD_LOGIC;
signal p1_full_1 : STD_LOGIC;
signal p1_stage_1 : STD_LOGIC;
signal p2_full_2 : STD_LOGIC;
signal p2_stage_2 : STD_LOGIC;
signal p3_full_3 : STD_LOGIC;
signal p3_stage_3 : STD_LOGIC;
signal p4_full_4 : STD_LOGIC;
signal p4_stage_4 : STD_LOGIC;
signal stage_0 : STD_LOGIC;
signal stage_1 : STD_LOGIC;
signal stage_2 : STD_LOGIC;
signal stage_3 : STD_LOGIC;
signal stage_4 : STD_LOGIC;
signal updated_one_count : STD_LOGIC_VECTOR (3 DOWNTO 0);
begin
data_out <= stage_0;
full <= full_4;
empty <= NOT(full_0);
full_5 <= std_logic'('0');
--data_4, which is an e_mux
p4_stage_4 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_5 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, data_in);
--data_reg_4, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_4 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_4))))) = '1' then
if std_logic'(((sync_reset AND full_4) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_5))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_4 <= std_logic'('0');
else
stage_4 <= p4_stage_4;
end if;
end if;
end if;
end process;
--control_4, which is an e_mux
p4_full_4 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_3))), std_logic_vector'("00000000000000000000000000000000")));
--control_reg_4, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_4 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_4 <= std_logic'('0');
else
full_4 <= p4_full_4;
end if;
end if;
end if;
end process;
--data_3, which is an e_mux
p3_stage_3 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_4 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_4);
--data_reg_3, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_3 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_3))))) = '1' then
if std_logic'(((sync_reset AND full_3) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_4))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_3 <= std_logic'('0');
else
stage_3 <= p3_stage_3;
end if;
end if;
end if;
end process;
--control_3, which is an e_mux
p3_full_3 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_2, full_4);
--control_reg_3, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_3 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_3 <= std_logic'('0');
else
full_3 <= p3_full_3;
end if;
end if;
end if;
end process;
--data_2, which is an e_mux
p2_stage_2 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_3 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_3);
--data_reg_2, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_2 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_2))))) = '1' then
if std_logic'(((sync_reset AND full_2) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_3))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_2 <= std_logic'('0');
else
stage_2 <= p2_stage_2;
end if;
end if;
end if;
end process;
--control_2, which is an e_mux
p2_full_2 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_1, full_3);
--control_reg_2, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_2 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_2 <= std_logic'('0');
else
full_2 <= p2_full_2;
end if;
end if;
end if;
end process;
--data_1, which is an e_mux
p1_stage_1 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_2 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_2);
--data_reg_1, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_1))))) = '1' then
if std_logic'(((sync_reset AND full_1) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_2))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_1 <= std_logic'('0');
else
stage_1 <= p1_stage_1;
end if;
end if;
end if;
end process;
--control_1, which is an e_mux
p1_full_1 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), full_0, full_2);
--control_reg_1, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_1 <= std_logic'('0');
else
full_1 <= p1_full_1;
end if;
end if;
end if;
end process;
--data_0, which is an e_mux
p0_stage_0 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_1 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_1);
--data_reg_0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_0 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(((sync_reset AND full_0) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_0 <= std_logic'('0');
else
stage_0 <= p0_stage_0;
end if;
end if;
end if;
end process;
--control_0, which is an e_mux
p0_full_0 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), std_logic_vector'("00000000000000000000000000000001"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1)))));
--control_reg_0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_0 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'((clear_fifo AND NOT write)) = '1' then
full_0 <= std_logic'('0');
else
full_0 <= p0_full_0;
end if;
end if;
end if;
end process;
one_count_plus_one <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (how_many_ones)) + std_logic_vector'("000000000000000000000000000000001")), 4);
one_count_minus_one <= A_EXT (((std_logic_vector'("00000000000000000000000000000") & (how_many_ones)) - std_logic_vector'("000000000000000000000000000000001")), 4);
--updated_one_count, which is an e_mux
updated_one_count <= A_EXT (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND NOT(write)))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND write))) = '1'), (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(data_in))), A_WE_StdLogicVector((std_logic'(((((read AND (data_in)) AND write) AND (stage_0)))) = '1'), how_many_ones, A_WE_StdLogicVector((std_logic'(((write AND (data_in)))) = '1'), one_count_plus_one, A_WE_StdLogicVector((std_logic'(((read AND (stage_0)))) = '1'), one_count_minus_one, how_many_ones))))))), 4);
--counts how many ones in the data pipeline, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
how_many_ones <= std_logic_vector'("0000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then
how_many_ones <= updated_one_count;
end if;
end if;
end process;
--this fifo contains ones in the data pipeline, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_contains_ones_n <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then
fifo_contains_ones_n <= NOT (or_reduce(updated_one_count));
end if;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity unici_core_burst_0_upstream_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_address_to_slave : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_burstcount : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_latency_counter : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_write : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_0_upstream_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_upstream_readdatavalid : IN STD_LOGIC;
signal unici_core_burst_0_upstream_waitrequest : IN STD_LOGIC;
-- outputs:
signal d1_unici_core_burst_0_upstream_end_xfer : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream : OUT STD_LOGIC;
signal unici_core_burst_0_upstream_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_upstream_burstcount : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_upstream_byteaddress : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_0_upstream_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_0_upstream_debugaccess : OUT STD_LOGIC;
signal unici_core_burst_0_upstream_read : OUT STD_LOGIC;
signal unici_core_burst_0_upstream_readdata_from_sa : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_upstream_waitrequest_from_sa : OUT STD_LOGIC;
signal unici_core_burst_0_upstream_write : OUT STD_LOGIC;
signal unici_core_burst_0_upstream_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
end entity unici_core_burst_0_upstream_arbitrator;
architecture europa of unici_core_burst_0_upstream_arbitrator is
component burstcount_fifo_for_unici_core_burst_0_upstream_module is
port (
-- inputs:
signal clear_fifo : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal read : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal empty : OUT STD_LOGIC;
signal fifo_contains_ones_n : OUT STD_LOGIC;
signal full : OUT STD_LOGIC
);
end component burstcount_fifo_for_unici_core_burst_0_upstream_module;
component rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_0_upstream_module is
port (
-- inputs:
signal clear_fifo : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal read : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC;
signal empty : OUT STD_LOGIC;
signal fifo_contains_ones_n : OUT STD_LOGIC;
signal full : OUT STD_LOGIC
);
end component rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_0_upstream_module;
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_unici_core_burst_0_upstream : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream : STD_LOGIC;
signal internal_pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream : STD_LOGIC;
signal internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream : STD_LOGIC;
signal internal_unici_core_burst_0_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal internal_unici_core_burst_0_upstream_read : STD_LOGIC;
signal internal_unici_core_burst_0_upstream_waitrequest_from_sa : STD_LOGIC;
signal internal_unici_core_burst_0_upstream_write : STD_LOGIC;
signal module_input3 : STD_LOGIC;
signal module_input4 : STD_LOGIC;
signal module_input5 : STD_LOGIC;
signal module_input6 : STD_LOGIC;
signal module_input7 : STD_LOGIC;
signal module_input8 : STD_LOGIC;
signal p0_unici_core_burst_0_upstream_load_fifo : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_arbiterlock : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_arbiterlock2 : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_continuerequest : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_rdv_fifo_empty_unici_core_burst_0_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_rdv_fifo_output_from_unici_core_burst_0_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_saved_grant_unici_core_burst_0_upstream : STD_LOGIC;
signal unici_core_burst_0_upstream_allgrants : STD_LOGIC;
signal unici_core_burst_0_upstream_allow_new_arb_cycle : STD_LOGIC;
signal unici_core_burst_0_upstream_any_bursting_master_saved_grant : STD_LOGIC;
signal unici_core_burst_0_upstream_any_continuerequest : STD_LOGIC;
signal unici_core_burst_0_upstream_arb_counter_enable : STD_LOGIC;
signal unici_core_burst_0_upstream_arb_share_counter : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_upstream_arb_share_counter_next_value : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_upstream_arb_share_set_values : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_upstream_bbt_burstcounter : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal unici_core_burst_0_upstream_beginbursttransfer_internal : STD_LOGIC;
signal unici_core_burst_0_upstream_begins_xfer : STD_LOGIC;
signal unici_core_burst_0_upstream_burstcount_fifo_empty : STD_LOGIC;
signal unici_core_burst_0_upstream_current_burst : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_upstream_current_burst_minus_one : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_upstream_end_xfer : STD_LOGIC;
signal unici_core_burst_0_upstream_firsttransfer : STD_LOGIC;
signal unici_core_burst_0_upstream_grant_vector : STD_LOGIC;
signal unici_core_burst_0_upstream_in_a_read_cycle : STD_LOGIC;
signal unici_core_burst_0_upstream_in_a_write_cycle : STD_LOGIC;
signal unici_core_burst_0_upstream_load_fifo : STD_LOGIC;
signal unici_core_burst_0_upstream_master_qreq_vector : STD_LOGIC;
signal unici_core_burst_0_upstream_move_on_to_next_transaction : STD_LOGIC;
signal unici_core_burst_0_upstream_next_bbt_burstcount : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal unici_core_burst_0_upstream_next_burst_count : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_upstream_non_bursting_master_requests : STD_LOGIC;
signal unici_core_burst_0_upstream_readdatavalid_from_sa : STD_LOGIC;
signal unici_core_burst_0_upstream_reg_firsttransfer : STD_LOGIC;
signal unici_core_burst_0_upstream_selected_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_upstream_slavearbiterlockenable : STD_LOGIC;
signal unici_core_burst_0_upstream_slavearbiterlockenable2 : STD_LOGIC;
signal unici_core_burst_0_upstream_this_cycle_is_the_last_burst : STD_LOGIC;
signal unici_core_burst_0_upstream_transaction_burst_count : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_upstream_unreg_firsttransfer : STD_LOGIC;
signal unici_core_burst_0_upstream_waits_for_read : STD_LOGIC;
signal unici_core_burst_0_upstream_waits_for_write : STD_LOGIC;
signal wait_for_unici_core_burst_0_upstream_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT unici_core_burst_0_upstream_end_xfer;
end if;
end process;
unici_core_burst_0_upstream_begins_xfer <= NOT d1_reasons_to_wait AND (internal_pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream);
--assign unici_core_burst_0_upstream_readdata_from_sa = unici_core_burst_0_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
unici_core_burst_0_upstream_readdata_from_sa <= unici_core_burst_0_upstream_readdata;
internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream <= to_std_logic(((Std_Logic_Vector'(pcie_compiler_0_Rx_Interface_address_to_slave(31 DOWNTO 15) & std_logic_vector'("000000000000000")) = std_logic_vector'("00000000000000000000000000000000")))) AND ((pcie_compiler_0_Rx_Interface_read OR pcie_compiler_0_Rx_Interface_write));
--assign unici_core_burst_0_upstream_waitrequest_from_sa = unici_core_burst_0_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_unici_core_burst_0_upstream_waitrequest_from_sa <= unici_core_burst_0_upstream_waitrequest;
--assign unici_core_burst_0_upstream_readdatavalid_from_sa = unici_core_burst_0_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
unici_core_burst_0_upstream_readdatavalid_from_sa <= unici_core_burst_0_upstream_readdatavalid;
--unici_core_burst_0_upstream_arb_share_counter set values, which is an e_mux
unici_core_burst_0_upstream_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream)) = '1'), (A_WE_StdLogicVector((std_logic'((pcie_compiler_0_Rx_Interface_write)) = '1'), (std_logic_vector'("0000000000000000000000") & (pcie_compiler_0_Rx_Interface_burstcount)), std_logic_vector'("00000000000000000000000000000001"))), std_logic_vector'("00000000000000000000000000000001")), 10);
--unici_core_burst_0_upstream_non_bursting_master_requests mux, which is an e_mux
unici_core_burst_0_upstream_non_bursting_master_requests <= std_logic'('0');
--unici_core_burst_0_upstream_any_bursting_master_saved_grant mux, which is an e_mux
unici_core_burst_0_upstream_any_bursting_master_saved_grant <= pcie_compiler_0_Rx_Interface_saved_grant_unici_core_burst_0_upstream;
--unici_core_burst_0_upstream_arb_share_counter_next_value assignment, which is an e_assign
unici_core_burst_0_upstream_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(unici_core_burst_0_upstream_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000") & (unici_core_burst_0_upstream_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(unici_core_burst_0_upstream_arb_share_counter)) = '1'), (((std_logic_vector'("00000000000000000000000") & (unici_core_burst_0_upstream_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 10);
--unici_core_burst_0_upstream_allgrants all slave grants, which is an e_mux
unici_core_burst_0_upstream_allgrants <= unici_core_burst_0_upstream_grant_vector;
--unici_core_burst_0_upstream_end_xfer assignment, which is an e_assign
unici_core_burst_0_upstream_end_xfer <= NOT ((unici_core_burst_0_upstream_waits_for_read OR unici_core_burst_0_upstream_waits_for_write));
--end_xfer_arb_share_counter_term_unici_core_burst_0_upstream arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_unici_core_burst_0_upstream <= unici_core_burst_0_upstream_end_xfer AND (((NOT unici_core_burst_0_upstream_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--unici_core_burst_0_upstream_arb_share_counter arbitration counter enable, which is an e_assign
unici_core_burst_0_upstream_arb_counter_enable <= ((end_xfer_arb_share_counter_term_unici_core_burst_0_upstream AND unici_core_burst_0_upstream_allgrants)) OR ((end_xfer_arb_share_counter_term_unici_core_burst_0_upstream AND NOT unici_core_burst_0_upstream_non_bursting_master_requests));
--unici_core_burst_0_upstream_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_upstream_arb_share_counter <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'(unici_core_burst_0_upstream_arb_counter_enable) = '1' then
unici_core_burst_0_upstream_arb_share_counter <= unici_core_burst_0_upstream_arb_share_counter_next_value;
end if;
end if;
end process;
--unici_core_burst_0_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_upstream_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((unici_core_burst_0_upstream_master_qreq_vector AND end_xfer_arb_share_counter_term_unici_core_burst_0_upstream)) OR ((end_xfer_arb_share_counter_term_unici_core_burst_0_upstream AND NOT unici_core_burst_0_upstream_non_bursting_master_requests)))) = '1' then
unici_core_burst_0_upstream_slavearbiterlockenable <= or_reduce(unici_core_burst_0_upstream_arb_share_counter_next_value);
end if;
end if;
end process;
--pcie_compiler_0/Rx_Interface unici_core_burst_0/upstream arbiterlock, which is an e_assign
pcie_compiler_0_Rx_Interface_arbiterlock <= unici_core_burst_0_upstream_slavearbiterlockenable AND pcie_compiler_0_Rx_Interface_continuerequest;
--unici_core_burst_0_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
unici_core_burst_0_upstream_slavearbiterlockenable2 <= or_reduce(unici_core_burst_0_upstream_arb_share_counter_next_value);
--pcie_compiler_0/Rx_Interface unici_core_burst_0/upstream arbiterlock2, which is an e_assign
pcie_compiler_0_Rx_Interface_arbiterlock2 <= unici_core_burst_0_upstream_slavearbiterlockenable2 AND pcie_compiler_0_Rx_Interface_continuerequest;
--unici_core_burst_0_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
unici_core_burst_0_upstream_any_continuerequest <= std_logic'('1');
--pcie_compiler_0_Rx_Interface_continuerequest continued request, which is an e_assign
pcie_compiler_0_Rx_Interface_continuerequest <= std_logic'('1');
internal_pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream <= internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream AND NOT ((pcie_compiler_0_Rx_Interface_read AND ((to_std_logic(((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pcie_compiler_0_Rx_Interface_latency_counter))) /= std_logic_vector'("00000000000000000000000000000000"))) OR ((std_logic_vector'("00000000000000000000000000000001")<(std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pcie_compiler_0_Rx_Interface_latency_counter))))))) OR (pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register)))));
--unique name for unici_core_burst_0_upstream_move_on_to_next_transaction, which is an e_assign
unici_core_burst_0_upstream_move_on_to_next_transaction <= unici_core_burst_0_upstream_this_cycle_is_the_last_burst AND unici_core_burst_0_upstream_load_fifo;
--the currently selected burstcount for unici_core_burst_0_upstream, which is an e_mux
unici_core_burst_0_upstream_selected_burstcount <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream)) = '1'), (std_logic_vector'("0000000000000000000000") & (pcie_compiler_0_Rx_Interface_burstcount)), std_logic_vector'("00000000000000000000000000000001")), 10);
--burstcount_fifo_for_unici_core_burst_0_upstream, which is an e_fifo_with_registered_outputs
burstcount_fifo_for_unici_core_burst_0_upstream : burstcount_fifo_for_unici_core_burst_0_upstream_module
port map(
data_out => unici_core_burst_0_upstream_transaction_burst_count,
empty => unici_core_burst_0_upstream_burstcount_fifo_empty,
fifo_contains_ones_n => open,
full => open,
clear_fifo => module_input3,
clk => clk,
data_in => unici_core_burst_0_upstream_selected_burstcount,
read => unici_core_burst_0_upstream_this_cycle_is_the_last_burst,
reset_n => reset_n,
sync_reset => module_input4,
write => module_input5
);
module_input3 <= std_logic'('0');
module_input4 <= std_logic'('0');
module_input5 <= ((in_a_read_cycle AND NOT unici_core_burst_0_upstream_waits_for_read) AND unici_core_burst_0_upstream_load_fifo) AND NOT ((unici_core_burst_0_upstream_this_cycle_is_the_last_burst AND unici_core_burst_0_upstream_burstcount_fifo_empty));
--unici_core_burst_0_upstream current burst minus one, which is an e_assign
unici_core_burst_0_upstream_current_burst_minus_one <= A_EXT (((std_logic_vector'("00000000000000000000000") & (unici_core_burst_0_upstream_current_burst)) - std_logic_vector'("000000000000000000000000000000001")), 10);
--what to load in current_burst, for unici_core_burst_0_upstream, which is an e_mux
unici_core_burst_0_upstream_next_burst_count <= A_WE_StdLogicVector((std_logic'(((((in_a_read_cycle AND NOT unici_core_burst_0_upstream_waits_for_read)) AND NOT unici_core_burst_0_upstream_load_fifo))) = '1'), unici_core_burst_0_upstream_selected_burstcount, A_WE_StdLogicVector((std_logic'(((((in_a_read_cycle AND NOT unici_core_burst_0_upstream_waits_for_read) AND unici_core_burst_0_upstream_this_cycle_is_the_last_burst) AND unici_core_burst_0_upstream_burstcount_fifo_empty))) = '1'), unici_core_burst_0_upstream_selected_burstcount, A_WE_StdLogicVector((std_logic'((unici_core_burst_0_upstream_this_cycle_is_the_last_burst)) = '1'), unici_core_burst_0_upstream_transaction_burst_count, unici_core_burst_0_upstream_current_burst_minus_one)));
--the current burst count for unici_core_burst_0_upstream, to be decremented, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_upstream_current_burst <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'((unici_core_burst_0_upstream_readdatavalid_from_sa OR ((NOT unici_core_burst_0_upstream_load_fifo AND ((in_a_read_cycle AND NOT unici_core_burst_0_upstream_waits_for_read)))))) = '1' then
unici_core_burst_0_upstream_current_burst <= unici_core_burst_0_upstream_next_burst_count;
end if;
end if;
end process;
--a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
p0_unici_core_burst_0_upstream_load_fifo <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((NOT unici_core_burst_0_upstream_load_fifo)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((((in_a_read_cycle AND NOT unici_core_burst_0_upstream_waits_for_read)) AND unici_core_burst_0_upstream_load_fifo))) = '1'), std_logic_vector'("00000000000000000000000000000001"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT unici_core_burst_0_upstream_burstcount_fifo_empty))))));
--whether to load directly to the counter or to the fifo, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_upstream_load_fifo <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((((in_a_read_cycle AND NOT unici_core_burst_0_upstream_waits_for_read)) AND NOT unici_core_burst_0_upstream_load_fifo) OR unici_core_burst_0_upstream_this_cycle_is_the_last_burst)) = '1' then
unici_core_burst_0_upstream_load_fifo <= p0_unici_core_burst_0_upstream_load_fifo;
end if;
end if;
end process;
--the last cycle in the burst for unici_core_burst_0_upstream, which is an e_assign
unici_core_burst_0_upstream_this_cycle_is_the_last_burst <= NOT (or_reduce(unici_core_burst_0_upstream_current_burst_minus_one)) AND unici_core_burst_0_upstream_readdatavalid_from_sa;
--rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_0_upstream, which is an e_fifo_with_registered_outputs
rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_0_upstream : rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_0_upstream_module
port map(
data_out => pcie_compiler_0_Rx_Interface_rdv_fifo_output_from_unici_core_burst_0_upstream,
empty => open,
fifo_contains_ones_n => pcie_compiler_0_Rx_Interface_rdv_fifo_empty_unici_core_burst_0_upstream,
full => open,
clear_fifo => module_input6,
clk => clk,
data_in => internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream,
read => unici_core_burst_0_upstream_move_on_to_next_transaction,
reset_n => reset_n,
sync_reset => module_input7,
write => module_input8
);
module_input6 <= std_logic'('0');
module_input7 <= std_logic'('0');
module_input8 <= in_a_read_cycle AND NOT unici_core_burst_0_upstream_waits_for_read;
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register <= NOT pcie_compiler_0_Rx_Interface_rdv_fifo_empty_unici_core_burst_0_upstream;
--local readdatavalid pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream, which is an e_mux
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream <= unici_core_burst_0_upstream_readdatavalid_from_sa;
--unici_core_burst_0_upstream_writedata mux, which is an e_mux
unici_core_burst_0_upstream_writedata <= pcie_compiler_0_Rx_Interface_writedata;
--byteaddress mux for unici_core_burst_0/upstream, which is an e_mux
unici_core_burst_0_upstream_byteaddress <= pcie_compiler_0_Rx_Interface_address_to_slave (17 DOWNTO 0);
--master is always granted when requested
internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream <= internal_pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream;
--pcie_compiler_0/Rx_Interface saved-grant unici_core_burst_0/upstream, which is an e_assign
pcie_compiler_0_Rx_Interface_saved_grant_unici_core_burst_0_upstream <= internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream;
--allow new arb cycle for unici_core_burst_0/upstream, which is an e_assign
unici_core_burst_0_upstream_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
unici_core_burst_0_upstream_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
unici_core_burst_0_upstream_master_qreq_vector <= std_logic'('1');
--unici_core_burst_0_upstream_firsttransfer first transaction, which is an e_assign
unici_core_burst_0_upstream_firsttransfer <= A_WE_StdLogic((std_logic'(unici_core_burst_0_upstream_begins_xfer) = '1'), unici_core_burst_0_upstream_unreg_firsttransfer, unici_core_burst_0_upstream_reg_firsttransfer);
--unici_core_burst_0_upstream_unreg_firsttransfer first transaction, which is an e_assign
unici_core_burst_0_upstream_unreg_firsttransfer <= NOT ((unici_core_burst_0_upstream_slavearbiterlockenable AND unici_core_burst_0_upstream_any_continuerequest));
--unici_core_burst_0_upstream_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_upstream_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(unici_core_burst_0_upstream_begins_xfer) = '1' then
unici_core_burst_0_upstream_reg_firsttransfer <= unici_core_burst_0_upstream_unreg_firsttransfer;
end if;
end if;
end process;
--unici_core_burst_0_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
unici_core_burst_0_upstream_next_bbt_burstcount <= A_EXT (A_WE_StdLogicVector((std_logic'((((internal_unici_core_burst_0_upstream_write) AND to_std_logic((((std_logic_vector'("00000000000000000000000") & (unici_core_burst_0_upstream_bbt_burstcounter)) = std_logic_vector'("00000000000000000000000000000000"))))))) = '1'), (((std_logic_vector'("00000000000000000000000") & (internal_unici_core_burst_0_upstream_burstcount)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'((((internal_unici_core_burst_0_upstream_read) AND to_std_logic((((std_logic_vector'("00000000000000000000000") & (unici_core_burst_0_upstream_bbt_burstcounter)) = std_logic_vector'("00000000000000000000000000000000"))))))) = '1'), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("000000000000000000000000") & (unici_core_burst_0_upstream_bbt_burstcounter)) - std_logic_vector'("000000000000000000000000000000001"))))), 9);
--unici_core_burst_0_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_upstream_bbt_burstcounter <= std_logic_vector'("000000000");
elsif clk'event and clk = '1' then
if std_logic'(unici_core_burst_0_upstream_begins_xfer) = '1' then
unici_core_burst_0_upstream_bbt_burstcounter <= unici_core_burst_0_upstream_next_bbt_burstcount;
end if;
end if;
end process;
--unici_core_burst_0_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
unici_core_burst_0_upstream_beginbursttransfer_internal <= unici_core_burst_0_upstream_begins_xfer AND to_std_logic((((std_logic_vector'("00000000000000000000000") & (unici_core_burst_0_upstream_bbt_burstcounter)) = std_logic_vector'("00000000000000000000000000000000"))));
--unici_core_burst_0_upstream_read assignment, which is an e_mux
internal_unici_core_burst_0_upstream_read <= internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream AND pcie_compiler_0_Rx_Interface_read;
--unici_core_burst_0_upstream_write assignment, which is an e_mux
internal_unici_core_burst_0_upstream_write <= internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream AND pcie_compiler_0_Rx_Interface_write;
--unici_core_burst_0_upstream_address mux, which is an e_mux
unici_core_burst_0_upstream_address <= pcie_compiler_0_Rx_Interface_address_to_slave (14 DOWNTO 0);
--d1_unici_core_burst_0_upstream_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_unici_core_burst_0_upstream_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_unici_core_burst_0_upstream_end_xfer <= unici_core_burst_0_upstream_end_xfer;
end if;
end process;
--unici_core_burst_0_upstream_waits_for_read in a cycle, which is an e_mux
unici_core_burst_0_upstream_waits_for_read <= unici_core_burst_0_upstream_in_a_read_cycle AND internal_unici_core_burst_0_upstream_waitrequest_from_sa;
--unici_core_burst_0_upstream_in_a_read_cycle assignment, which is an e_assign
unici_core_burst_0_upstream_in_a_read_cycle <= internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream AND pcie_compiler_0_Rx_Interface_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= unici_core_burst_0_upstream_in_a_read_cycle;
--unici_core_burst_0_upstream_waits_for_write in a cycle, which is an e_mux
unici_core_burst_0_upstream_waits_for_write <= unici_core_burst_0_upstream_in_a_write_cycle AND internal_unici_core_burst_0_upstream_waitrequest_from_sa;
--unici_core_burst_0_upstream_in_a_write_cycle assignment, which is an e_assign
unici_core_burst_0_upstream_in_a_write_cycle <= internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream AND pcie_compiler_0_Rx_Interface_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= unici_core_burst_0_upstream_in_a_write_cycle;
wait_for_unici_core_burst_0_upstream_counter <= std_logic'('0');
--unici_core_burst_0_upstream_byteenable byte enable port mux, which is an e_mux
unici_core_burst_0_upstream_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream)) = '1'), (std_logic_vector'("000000000000000000000000") & (pcie_compiler_0_Rx_Interface_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 8);
--burstcount mux, which is an e_mux
internal_unici_core_burst_0_upstream_burstcount <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream)) = '1'), (std_logic_vector'("0000000000000000000000") & (pcie_compiler_0_Rx_Interface_burstcount)), std_logic_vector'("00000000000000000000000000000001")), 10);
--debugaccess mux, which is an e_mux
unici_core_burst_0_upstream_debugaccess <= std_logic'('0');
--vhdl renameroo for output signals
pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream <= internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream;
--vhdl renameroo for output signals
pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream <= internal_pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream;
--vhdl renameroo for output signals
pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream <= internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream;
--vhdl renameroo for output signals
unici_core_burst_0_upstream_burstcount <= internal_unici_core_burst_0_upstream_burstcount;
--vhdl renameroo for output signals
unici_core_burst_0_upstream_read <= internal_unici_core_burst_0_upstream_read;
--vhdl renameroo for output signals
unici_core_burst_0_upstream_waitrequest_from_sa <= internal_unici_core_burst_0_upstream_waitrequest_from_sa;
--vhdl renameroo for output signals
unici_core_burst_0_upstream_write <= internal_unici_core_burst_0_upstream_write;
--synthesis translate_off
--unici_core_burst_0/upstream enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--pcie_compiler_0/Rx_Interface non-zero burstcount assertion, which is an e_process
process (clk)
VARIABLE write_line29 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream AND to_std_logic((((std_logic_vector'("0000000000000000000000") & (pcie_compiler_0_Rx_Interface_burstcount)) = std_logic_vector'("00000000000000000000000000000000"))))) AND enable_nonzero_assertions)) = '1' then
write(write_line29, now);
write(write_line29, string'(": "));
write(write_line29, string'("pcie_compiler_0/Rx_Interface drove 0 on its 'burstcount' port while accessing slave unici_core_burst_0/upstream"));
write(output, write_line29.all);
deallocate (write_line29);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity unici_core_burst_0_downstream_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal d1_pipeline_bridge_0_s1_end_xfer : IN STD_LOGIC;
signal pipeline_bridge_0_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_s1_waitrequest_from_sa : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_0_downstream_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_burstcount : IN STD_LOGIC;
signal unici_core_burst_0_downstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 : IN STD_LOGIC;
signal unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 : IN STD_LOGIC;
signal unici_core_burst_0_downstream_read : IN STD_LOGIC;
signal unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1 : IN STD_LOGIC;
signal unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1_shift_register : IN STD_LOGIC;
signal unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 : IN STD_LOGIC;
signal unici_core_burst_0_downstream_write : IN STD_LOGIC;
signal unici_core_burst_0_downstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal unici_core_burst_0_downstream_address_to_slave : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_latency_counter : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_downstream_readdatavalid : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_reset_n : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_waitrequest : OUT STD_LOGIC
);
end entity unici_core_burst_0_downstream_arbitrator;
architecture europa of unici_core_burst_0_downstream_arbitrator is
signal active_and_waiting_last_time : STD_LOGIC;
signal internal_unici_core_burst_0_downstream_address_to_slave : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal internal_unici_core_burst_0_downstream_waitrequest : STD_LOGIC;
signal pre_flush_unici_core_burst_0_downstream_readdatavalid : STD_LOGIC;
signal r_1 : STD_LOGIC;
signal unici_core_burst_0_downstream_address_last_time : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_burstcount_last_time : STD_LOGIC;
signal unici_core_burst_0_downstream_byteenable_last_time : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_0_downstream_read_last_time : STD_LOGIC;
signal unici_core_burst_0_downstream_run : STD_LOGIC;
signal unici_core_burst_0_downstream_write_last_time : STD_LOGIC;
signal unici_core_burst_0_downstream_writedata_last_time : STD_LOGIC_VECTOR (63 DOWNTO 0);
begin
--r_1 master_run cascaded wait assignment, which is an e_assign
r_1 <= Vector_To_Std_Logic((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 OR NOT unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 OR NOT ((unici_core_burst_0_downstream_read OR unici_core_burst_0_downstream_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT pipeline_bridge_0_s1_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((unici_core_burst_0_downstream_read OR unici_core_burst_0_downstream_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 OR NOT ((unici_core_burst_0_downstream_read OR unici_core_burst_0_downstream_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT pipeline_bridge_0_s1_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((unici_core_burst_0_downstream_read OR unici_core_burst_0_downstream_write)))))))))));
--cascaded wait assignment, which is an e_assign
unici_core_burst_0_downstream_run <= r_1;
--optimize select-logic by passing only those address bits which matter.
internal_unici_core_burst_0_downstream_address_to_slave <= unici_core_burst_0_downstream_address;
--latent slave read data valids which may be flushed, which is an e_mux
pre_flush_unici_core_burst_0_downstream_readdatavalid <= unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1;
--latent slave read data valid which is not flushed, which is an e_mux
unici_core_burst_0_downstream_readdatavalid <= Vector_To_Std_Logic((std_logic_vector'("00000000000000000000000000000000") OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pre_flush_unici_core_burst_0_downstream_readdatavalid)))));
--unici_core_burst_0/downstream readdata mux, which is an e_mux
unici_core_burst_0_downstream_readdata <= pipeline_bridge_0_s1_readdata_from_sa;
--actual waitrequest port, which is an e_assign
internal_unici_core_burst_0_downstream_waitrequest <= NOT unici_core_burst_0_downstream_run;
--latent max counter, which is an e_assign
unici_core_burst_0_downstream_latency_counter <= std_logic'('0');
--unici_core_burst_0_downstream_reset_n assignment, which is an e_assign
unici_core_burst_0_downstream_reset_n <= reset_n;
--vhdl renameroo for output signals
unici_core_burst_0_downstream_address_to_slave <= internal_unici_core_burst_0_downstream_address_to_slave;
--vhdl renameroo for output signals
unici_core_burst_0_downstream_waitrequest <= internal_unici_core_burst_0_downstream_waitrequest;
--synthesis translate_off
--unici_core_burst_0_downstream_address check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_downstream_address_last_time <= std_logic_vector'("000000000000000");
elsif clk'event and clk = '1' then
unici_core_burst_0_downstream_address_last_time <= unici_core_burst_0_downstream_address;
end if;
end process;
--unici_core_burst_0/downstream waited last time, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
active_and_waiting_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
active_and_waiting_last_time <= internal_unici_core_burst_0_downstream_waitrequest AND ((unici_core_burst_0_downstream_read OR unici_core_burst_0_downstream_write));
end if;
end process;
--unici_core_burst_0_downstream_address matches last port_name, which is an e_process
process (clk)
VARIABLE write_line30 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((unici_core_burst_0_downstream_address /= unici_core_burst_0_downstream_address_last_time))))) = '1' then
write(write_line30, now);
write(write_line30, string'(": "));
write(write_line30, string'("unici_core_burst_0_downstream_address did not heed wait!!!"));
write(output, write_line30.all);
deallocate (write_line30);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_0_downstream_burstcount check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_downstream_burstcount_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
unici_core_burst_0_downstream_burstcount_last_time <= unici_core_burst_0_downstream_burstcount;
end if;
end process;
--unici_core_burst_0_downstream_burstcount matches last port_name, which is an e_process
process (clk)
VARIABLE write_line31 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(unici_core_burst_0_downstream_burstcount) /= std_logic'(unici_core_burst_0_downstream_burstcount_last_time)))))) = '1' then
write(write_line31, now);
write(write_line31, string'(": "));
write(write_line31, string'("unici_core_burst_0_downstream_burstcount did not heed wait!!!"));
write(output, write_line31.all);
deallocate (write_line31);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_0_downstream_byteenable check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_downstream_byteenable_last_time <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
unici_core_burst_0_downstream_byteenable_last_time <= unici_core_burst_0_downstream_byteenable;
end if;
end process;
--unici_core_burst_0_downstream_byteenable matches last port_name, which is an e_process
process (clk)
VARIABLE write_line32 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((unici_core_burst_0_downstream_byteenable /= unici_core_burst_0_downstream_byteenable_last_time))))) = '1' then
write(write_line32, now);
write(write_line32, string'(": "));
write(write_line32, string'("unici_core_burst_0_downstream_byteenable did not heed wait!!!"));
write(output, write_line32.all);
deallocate (write_line32);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_0_downstream_read check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_downstream_read_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
unici_core_burst_0_downstream_read_last_time <= unici_core_burst_0_downstream_read;
end if;
end process;
--unici_core_burst_0_downstream_read matches last port_name, which is an e_process
process (clk)
VARIABLE write_line33 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(unici_core_burst_0_downstream_read) /= std_logic'(unici_core_burst_0_downstream_read_last_time)))))) = '1' then
write(write_line33, now);
write(write_line33, string'(": "));
write(write_line33, string'("unici_core_burst_0_downstream_read did not heed wait!!!"));
write(output, write_line33.all);
deallocate (write_line33);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_0_downstream_write check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_downstream_write_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
unici_core_burst_0_downstream_write_last_time <= unici_core_burst_0_downstream_write;
end if;
end process;
--unici_core_burst_0_downstream_write matches last port_name, which is an e_process
process (clk)
VARIABLE write_line34 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(unici_core_burst_0_downstream_write) /= std_logic'(unici_core_burst_0_downstream_write_last_time)))))) = '1' then
write(write_line34, now);
write(write_line34, string'(": "));
write(write_line34, string'("unici_core_burst_0_downstream_write did not heed wait!!!"));
write(output, write_line34.all);
deallocate (write_line34);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_0_downstream_writedata check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_0_downstream_writedata_last_time <= std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
unici_core_burst_0_downstream_writedata_last_time <= unici_core_burst_0_downstream_writedata;
end if;
end process;
--unici_core_burst_0_downstream_writedata matches last port_name, which is an e_process
process (clk)
VARIABLE write_line35 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((active_and_waiting_last_time AND to_std_logic(((unici_core_burst_0_downstream_writedata /= unici_core_burst_0_downstream_writedata_last_time)))) AND unici_core_burst_0_downstream_write)) = '1' then
write(write_line35, now);
write(write_line35, string'(": "));
write(write_line35, string'("unici_core_burst_0_downstream_writedata did not heed wait!!!"));
write(output, write_line35.all);
deallocate (write_line35);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity burstcount_fifo_for_unici_core_burst_1_upstream_module is
port (
-- inputs:
signal clear_fifo : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal read : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal empty : OUT STD_LOGIC;
signal fifo_contains_ones_n : OUT STD_LOGIC;
signal full : OUT STD_LOGIC
);
end entity burstcount_fifo_for_unici_core_burst_1_upstream_module;
architecture europa of burstcount_fifo_for_unici_core_burst_1_upstream_module is
signal full_0 : STD_LOGIC;
signal full_1 : STD_LOGIC;
signal full_2 : STD_LOGIC;
signal how_many_ones : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal one_count_minus_one : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal one_count_plus_one : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal p0_full_0 : STD_LOGIC;
signal p0_stage_0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal p1_full_1 : STD_LOGIC;
signal p1_stage_1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal stage_0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal stage_1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal updated_one_count : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
data_out <= stage_0;
full <= full_1;
empty <= NOT(full_0);
full_2 <= std_logic'('0');
--data_1, which is an e_mux
p1_stage_1 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_2 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, data_in);
--data_reg_1, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_1 <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_1))))) = '1' then
if std_logic'(((sync_reset AND full_1) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_2))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_1 <= std_logic_vector'("0000000000");
else
stage_1 <= p1_stage_1;
end if;
end if;
end if;
end process;
--control_1, which is an e_mux
p1_full_1 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_0))), std_logic_vector'("00000000000000000000000000000000")));
--control_reg_1, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_1 <= std_logic'('0');
else
full_1 <= p1_full_1;
end if;
end if;
end if;
end process;
--data_0, which is an e_mux
p0_stage_0 <= A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_1 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_1);
--data_reg_0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_0 <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(((sync_reset AND full_0) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_0 <= std_logic_vector'("0000000000");
else
stage_0 <= p0_stage_0;
end if;
end if;
end if;
end process;
--control_0, which is an e_mux
p0_full_0 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), std_logic_vector'("00000000000000000000000000000001"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1)))));
--control_reg_0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_0 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'((clear_fifo AND NOT write)) = '1' then
full_0 <= std_logic'('0');
else
full_0 <= p0_full_0;
end if;
end if;
end if;
end process;
one_count_plus_one <= A_EXT (((std_logic_vector'("000000000000000000000000000000") & (how_many_ones)) + std_logic_vector'("000000000000000000000000000000001")), 3);
one_count_minus_one <= A_EXT (((std_logic_vector'("000000000000000000000000000000") & (how_many_ones)) - std_logic_vector'("000000000000000000000000000000001")), 3);
--updated_one_count, which is an e_mux
updated_one_count <= A_EXT (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND NOT(write)))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND write))) = '1'), (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(or_reduce(data_in)))), A_WE_StdLogicVector((std_logic'(((((read AND (or_reduce(data_in))) AND write) AND (or_reduce(stage_0))))) = '1'), how_many_ones, A_WE_StdLogicVector((std_logic'(((write AND (or_reduce(data_in))))) = '1'), one_count_plus_one, A_WE_StdLogicVector((std_logic'(((read AND (or_reduce(stage_0))))) = '1'), one_count_minus_one, how_many_ones))))))), 3);
--counts how many ones in the data pipeline, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
how_many_ones <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then
how_many_ones <= updated_one_count;
end if;
end if;
end process;
--this fifo contains ones in the data pipeline, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_contains_ones_n <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then
fifo_contains_ones_n <= NOT (or_reduce(updated_one_count));
end if;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_1_upstream_module is
port (
-- inputs:
signal clear_fifo : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal read : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC;
signal empty : OUT STD_LOGIC;
signal fifo_contains_ones_n : OUT STD_LOGIC;
signal full : OUT STD_LOGIC
);
end entity rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_1_upstream_module;
architecture europa of rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_1_upstream_module is
signal full_0 : STD_LOGIC;
signal full_1 : STD_LOGIC;
signal full_2 : STD_LOGIC;
signal how_many_ones : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal one_count_minus_one : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal one_count_plus_one : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal p0_full_0 : STD_LOGIC;
signal p0_stage_0 : STD_LOGIC;
signal p1_full_1 : STD_LOGIC;
signal p1_stage_1 : STD_LOGIC;
signal stage_0 : STD_LOGIC;
signal stage_1 : STD_LOGIC;
signal updated_one_count : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
data_out <= stage_0;
full <= full_1;
empty <= NOT(full_0);
full_2 <= std_logic'('0');
--data_1, which is an e_mux
p1_stage_1 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_2 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, data_in);
--data_reg_1, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_1))))) = '1' then
if std_logic'(((sync_reset AND full_1) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_2))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_1 <= std_logic'('0');
else
stage_1 <= p1_stage_1;
end if;
end if;
end if;
end process;
--control_1, which is an e_mux
p1_full_1 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_0))), std_logic_vector'("00000000000000000000000000000000")));
--control_reg_1, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_1 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(clear_fifo) = '1' then
full_1 <= std_logic'('0');
else
full_1 <= p1_full_1;
end if;
end if;
end if;
end process;
--data_0, which is an e_mux
p0_stage_0 <= A_WE_StdLogic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((full_1 AND NOT clear_fifo))))) = std_logic_vector'("00000000000000000000000000000000"))), data_in, stage_1);
--data_reg_0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
stage_0 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'(((sync_reset AND full_0) AND NOT((((to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1))) = std_logic_vector'("00000000000000000000000000000000")))) AND read) AND write))))) = '1' then
stage_0 <= std_logic'('0');
else
stage_0 <= p0_stage_0;
end if;
end if;
end if;
end process;
--control_0, which is an e_mux
p0_full_0 <= Vector_To_Std_Logic(A_WE_StdLogicVector((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((read AND NOT(write)))))) = std_logic_vector'("00000000000000000000000000000000"))), std_logic_vector'("00000000000000000000000000000001"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(full_1)))));
--control_reg_0, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
full_0 <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((clear_fifo OR ((read XOR write))) OR ((write AND NOT(full_0))))) = '1' then
if std_logic'((clear_fifo AND NOT write)) = '1' then
full_0 <= std_logic'('0');
else
full_0 <= p0_full_0;
end if;
end if;
end if;
end process;
one_count_plus_one <= A_EXT (((std_logic_vector'("000000000000000000000000000000") & (how_many_ones)) + std_logic_vector'("000000000000000000000000000000001")), 3);
one_count_minus_one <= A_EXT (((std_logic_vector'("000000000000000000000000000000") & (how_many_ones)) - std_logic_vector'("000000000000000000000000000000001")), 3);
--updated_one_count, which is an e_mux
updated_one_count <= A_EXT (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND NOT(write)))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("00000000000000000000000000000") & (A_WE_StdLogicVector((std_logic'(((((clear_fifo OR sync_reset)) AND write))) = '1'), (std_logic_vector'("00") & (A_TOSTDLOGICVECTOR(data_in))), A_WE_StdLogicVector((std_logic'(((((read AND (data_in)) AND write) AND (stage_0)))) = '1'), how_many_ones, A_WE_StdLogicVector((std_logic'(((write AND (data_in)))) = '1'), one_count_plus_one, A_WE_StdLogicVector((std_logic'(((read AND (stage_0)))) = '1'), one_count_minus_one, how_many_ones))))))), 3);
--counts how many ones in the data pipeline, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
how_many_ones <= std_logic_vector'("000");
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then
how_many_ones <= updated_one_count;
end if;
end if;
end process;
--this fifo contains ones in the data pipeline, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
fifo_contains_ones_n <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'((((clear_fifo OR sync_reset) OR read) OR write)) = '1' then
fifo_contains_ones_n <= NOT (or_reduce(updated_one_count));
end if;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity unici_core_burst_1_upstream_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_address_to_slave : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_burstcount : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_latency_counter : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_write : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_1_upstream_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_upstream_readdatavalid : IN STD_LOGIC;
signal unici_core_burst_1_upstream_waitrequest : IN STD_LOGIC;
-- outputs:
signal d1_unici_core_burst_1_upstream_end_xfer : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream : OUT STD_LOGIC;
signal unici_core_burst_1_upstream_address : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_upstream_burstcount : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_upstream_byteaddress : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
signal unici_core_burst_1_upstream_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_1_upstream_debugaccess : OUT STD_LOGIC;
signal unici_core_burst_1_upstream_read : OUT STD_LOGIC;
signal unici_core_burst_1_upstream_readdata_from_sa : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_upstream_waitrequest_from_sa : OUT STD_LOGIC;
signal unici_core_burst_1_upstream_write : OUT STD_LOGIC;
signal unici_core_burst_1_upstream_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
end entity unici_core_burst_1_upstream_arbitrator;
architecture europa of unici_core_burst_1_upstream_arbitrator is
component burstcount_fifo_for_unici_core_burst_1_upstream_module is
port (
-- inputs:
signal clear_fifo : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal read : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal empty : OUT STD_LOGIC;
signal fifo_contains_ones_n : OUT STD_LOGIC;
signal full : OUT STD_LOGIC
);
end component burstcount_fifo_for_unici_core_burst_1_upstream_module;
component rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_1_upstream_module is
port (
-- inputs:
signal clear_fifo : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal read : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal sync_reset : IN STD_LOGIC;
signal write : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC;
signal empty : OUT STD_LOGIC;
signal fifo_contains_ones_n : OUT STD_LOGIC;
signal full : OUT STD_LOGIC
);
end component rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_1_upstream_module;
signal d1_reasons_to_wait : STD_LOGIC;
signal enable_nonzero_assertions : STD_LOGIC;
signal end_xfer_arb_share_counter_term_unici_core_burst_1_upstream : STD_LOGIC;
signal in_a_read_cycle : STD_LOGIC;
signal in_a_write_cycle : STD_LOGIC;
signal internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream : STD_LOGIC;
signal internal_pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream : STD_LOGIC;
signal internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream : STD_LOGIC;
signal internal_unici_core_burst_1_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal internal_unici_core_burst_1_upstream_read : STD_LOGIC;
signal internal_unici_core_burst_1_upstream_waitrequest_from_sa : STD_LOGIC;
signal internal_unici_core_burst_1_upstream_write : STD_LOGIC;
signal module_input10 : STD_LOGIC;
signal module_input11 : STD_LOGIC;
signal module_input12 : STD_LOGIC;
signal module_input13 : STD_LOGIC;
signal module_input14 : STD_LOGIC;
signal module_input9 : STD_LOGIC;
signal p0_unici_core_burst_1_upstream_load_fifo : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_arbiterlock : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_arbiterlock2 : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_continuerequest : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_rdv_fifo_empty_unici_core_burst_1_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_rdv_fifo_output_from_unici_core_burst_1_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_saved_grant_unici_core_burst_1_upstream : STD_LOGIC;
signal unici_core_burst_1_upstream_allgrants : STD_LOGIC;
signal unici_core_burst_1_upstream_allow_new_arb_cycle : STD_LOGIC;
signal unici_core_burst_1_upstream_any_bursting_master_saved_grant : STD_LOGIC;
signal unici_core_burst_1_upstream_any_continuerequest : STD_LOGIC;
signal unici_core_burst_1_upstream_arb_counter_enable : STD_LOGIC;
signal unici_core_burst_1_upstream_arb_share_counter : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_upstream_arb_share_counter_next_value : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_upstream_arb_share_set_values : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_upstream_bbt_burstcounter : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal unici_core_burst_1_upstream_beginbursttransfer_internal : STD_LOGIC;
signal unici_core_burst_1_upstream_begins_xfer : STD_LOGIC;
signal unici_core_burst_1_upstream_burstcount_fifo_empty : STD_LOGIC;
signal unici_core_burst_1_upstream_current_burst : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_upstream_current_burst_minus_one : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_upstream_end_xfer : STD_LOGIC;
signal unici_core_burst_1_upstream_firsttransfer : STD_LOGIC;
signal unici_core_burst_1_upstream_grant_vector : STD_LOGIC;
signal unici_core_burst_1_upstream_in_a_read_cycle : STD_LOGIC;
signal unici_core_burst_1_upstream_in_a_write_cycle : STD_LOGIC;
signal unici_core_burst_1_upstream_load_fifo : STD_LOGIC;
signal unici_core_burst_1_upstream_master_qreq_vector : STD_LOGIC;
signal unici_core_burst_1_upstream_move_on_to_next_transaction : STD_LOGIC;
signal unici_core_burst_1_upstream_next_bbt_burstcount : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal unici_core_burst_1_upstream_next_burst_count : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_upstream_non_bursting_master_requests : STD_LOGIC;
signal unici_core_burst_1_upstream_readdatavalid_from_sa : STD_LOGIC;
signal unici_core_burst_1_upstream_reg_firsttransfer : STD_LOGIC;
signal unici_core_burst_1_upstream_selected_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_upstream_slavearbiterlockenable : STD_LOGIC;
signal unici_core_burst_1_upstream_slavearbiterlockenable2 : STD_LOGIC;
signal unici_core_burst_1_upstream_this_cycle_is_the_last_burst : STD_LOGIC;
signal unici_core_burst_1_upstream_transaction_burst_count : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_upstream_unreg_firsttransfer : STD_LOGIC;
signal unici_core_burst_1_upstream_waits_for_read : STD_LOGIC;
signal unici_core_burst_1_upstream_waits_for_write : STD_LOGIC;
signal wait_for_unici_core_burst_1_upstream_counter : STD_LOGIC;
begin
process (clk, reset_n)
begin
if reset_n = '0' then
d1_reasons_to_wait <= std_logic'('0');
elsif clk'event and clk = '1' then
d1_reasons_to_wait <= NOT unici_core_burst_1_upstream_end_xfer;
end if;
end process;
unici_core_burst_1_upstream_begins_xfer <= NOT d1_reasons_to_wait AND (internal_pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream);
--assign unici_core_burst_1_upstream_readdatavalid_from_sa = unici_core_burst_1_upstream_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
unici_core_burst_1_upstream_readdatavalid_from_sa <= unici_core_burst_1_upstream_readdatavalid;
--assign unici_core_burst_1_upstream_readdata_from_sa = unici_core_burst_1_upstream_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
unici_core_burst_1_upstream_readdata_from_sa <= unici_core_burst_1_upstream_readdata;
internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream <= to_std_logic(((Std_Logic_Vector'(pcie_compiler_0_Rx_Interface_address_to_slave(31 DOWNTO 18) & std_logic_vector'("000000000000000000")) = std_logic_vector'("00000000000001000000000000000000")))) AND ((pcie_compiler_0_Rx_Interface_read OR pcie_compiler_0_Rx_Interface_write));
--assign unici_core_burst_1_upstream_waitrequest_from_sa = unici_core_burst_1_upstream_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
internal_unici_core_burst_1_upstream_waitrequest_from_sa <= unici_core_burst_1_upstream_waitrequest;
--unici_core_burst_1_upstream_arb_share_counter set values, which is an e_mux
unici_core_burst_1_upstream_arb_share_set_values <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream)) = '1'), (A_WE_StdLogicVector((std_logic'((pcie_compiler_0_Rx_Interface_write)) = '1'), (std_logic_vector'("0000000000000000000000") & (pcie_compiler_0_Rx_Interface_burstcount)), std_logic_vector'("00000000000000000000000000000001"))), std_logic_vector'("00000000000000000000000000000001")), 10);
--unici_core_burst_1_upstream_non_bursting_master_requests mux, which is an e_mux
unici_core_burst_1_upstream_non_bursting_master_requests <= std_logic'('0');
--unici_core_burst_1_upstream_any_bursting_master_saved_grant mux, which is an e_mux
unici_core_burst_1_upstream_any_bursting_master_saved_grant <= pcie_compiler_0_Rx_Interface_saved_grant_unici_core_burst_1_upstream;
--unici_core_burst_1_upstream_arb_share_counter_next_value assignment, which is an e_assign
unici_core_burst_1_upstream_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(unici_core_burst_1_upstream_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000") & (unici_core_burst_1_upstream_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(unici_core_burst_1_upstream_arb_share_counter)) = '1'), (((std_logic_vector'("00000000000000000000000") & (unici_core_burst_1_upstream_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 10);
--unici_core_burst_1_upstream_allgrants all slave grants, which is an e_mux
unici_core_burst_1_upstream_allgrants <= unici_core_burst_1_upstream_grant_vector;
--unici_core_burst_1_upstream_end_xfer assignment, which is an e_assign
unici_core_burst_1_upstream_end_xfer <= NOT ((unici_core_burst_1_upstream_waits_for_read OR unici_core_burst_1_upstream_waits_for_write));
--end_xfer_arb_share_counter_term_unici_core_burst_1_upstream arb share counter enable term, which is an e_assign
end_xfer_arb_share_counter_term_unici_core_burst_1_upstream <= unici_core_burst_1_upstream_end_xfer AND (((NOT unici_core_burst_1_upstream_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
--unici_core_burst_1_upstream_arb_share_counter arbitration counter enable, which is an e_assign
unici_core_burst_1_upstream_arb_counter_enable <= ((end_xfer_arb_share_counter_term_unici_core_burst_1_upstream AND unici_core_burst_1_upstream_allgrants)) OR ((end_xfer_arb_share_counter_term_unici_core_burst_1_upstream AND NOT unici_core_burst_1_upstream_non_bursting_master_requests));
--unici_core_burst_1_upstream_arb_share_counter counter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_upstream_arb_share_counter <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'(unici_core_burst_1_upstream_arb_counter_enable) = '1' then
unici_core_burst_1_upstream_arb_share_counter <= unici_core_burst_1_upstream_arb_share_counter_next_value;
end if;
end if;
end process;
--unici_core_burst_1_upstream_slavearbiterlockenable slave enables arbiterlock, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_upstream_slavearbiterlockenable <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'((((unici_core_burst_1_upstream_master_qreq_vector AND end_xfer_arb_share_counter_term_unici_core_burst_1_upstream)) OR ((end_xfer_arb_share_counter_term_unici_core_burst_1_upstream AND NOT unici_core_burst_1_upstream_non_bursting_master_requests)))) = '1' then
unici_core_burst_1_upstream_slavearbiterlockenable <= or_reduce(unici_core_burst_1_upstream_arb_share_counter_next_value);
end if;
end if;
end process;
--pcie_compiler_0/Rx_Interface unici_core_burst_1/upstream arbiterlock, which is an e_assign
pcie_compiler_0_Rx_Interface_arbiterlock <= unici_core_burst_1_upstream_slavearbiterlockenable AND pcie_compiler_0_Rx_Interface_continuerequest;
--unici_core_burst_1_upstream_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
unici_core_burst_1_upstream_slavearbiterlockenable2 <= or_reduce(unici_core_burst_1_upstream_arb_share_counter_next_value);
--pcie_compiler_0/Rx_Interface unici_core_burst_1/upstream arbiterlock2, which is an e_assign
pcie_compiler_0_Rx_Interface_arbiterlock2 <= unici_core_burst_1_upstream_slavearbiterlockenable2 AND pcie_compiler_0_Rx_Interface_continuerequest;
--unici_core_burst_1_upstream_any_continuerequest at least one master continues requesting, which is an e_assign
unici_core_burst_1_upstream_any_continuerequest <= std_logic'('1');
--pcie_compiler_0_Rx_Interface_continuerequest continued request, which is an e_assign
pcie_compiler_0_Rx_Interface_continuerequest <= std_logic'('1');
internal_pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream <= internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream AND NOT ((pcie_compiler_0_Rx_Interface_read AND ((to_std_logic(((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pcie_compiler_0_Rx_Interface_latency_counter))) /= std_logic_vector'("00000000000000000000000000000000"))) OR ((std_logic_vector'("00000000000000000000000000000001")<(std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pcie_compiler_0_Rx_Interface_latency_counter))))))) OR (pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register)))));
--unique name for unici_core_burst_1_upstream_move_on_to_next_transaction, which is an e_assign
unici_core_burst_1_upstream_move_on_to_next_transaction <= unici_core_burst_1_upstream_this_cycle_is_the_last_burst AND unici_core_burst_1_upstream_load_fifo;
--the currently selected burstcount for unici_core_burst_1_upstream, which is an e_mux
unici_core_burst_1_upstream_selected_burstcount <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream)) = '1'), (std_logic_vector'("0000000000000000000000") & (pcie_compiler_0_Rx_Interface_burstcount)), std_logic_vector'("00000000000000000000000000000001")), 10);
--burstcount_fifo_for_unici_core_burst_1_upstream, which is an e_fifo_with_registered_outputs
burstcount_fifo_for_unici_core_burst_1_upstream : burstcount_fifo_for_unici_core_burst_1_upstream_module
port map(
data_out => unici_core_burst_1_upstream_transaction_burst_count,
empty => unici_core_burst_1_upstream_burstcount_fifo_empty,
fifo_contains_ones_n => open,
full => open,
clear_fifo => module_input9,
clk => clk,
data_in => unici_core_burst_1_upstream_selected_burstcount,
read => unici_core_burst_1_upstream_this_cycle_is_the_last_burst,
reset_n => reset_n,
sync_reset => module_input10,
write => module_input11
);
module_input9 <= std_logic'('0');
module_input10 <= std_logic'('0');
module_input11 <= ((in_a_read_cycle AND NOT unici_core_burst_1_upstream_waits_for_read) AND unici_core_burst_1_upstream_load_fifo) AND NOT ((unici_core_burst_1_upstream_this_cycle_is_the_last_burst AND unici_core_burst_1_upstream_burstcount_fifo_empty));
--unici_core_burst_1_upstream current burst minus one, which is an e_assign
unici_core_burst_1_upstream_current_burst_minus_one <= A_EXT (((std_logic_vector'("00000000000000000000000") & (unici_core_burst_1_upstream_current_burst)) - std_logic_vector'("000000000000000000000000000000001")), 10);
--what to load in current_burst, for unici_core_burst_1_upstream, which is an e_mux
unici_core_burst_1_upstream_next_burst_count <= A_WE_StdLogicVector((std_logic'(((((in_a_read_cycle AND NOT unici_core_burst_1_upstream_waits_for_read)) AND NOT unici_core_burst_1_upstream_load_fifo))) = '1'), unici_core_burst_1_upstream_selected_burstcount, A_WE_StdLogicVector((std_logic'(((((in_a_read_cycle AND NOT unici_core_burst_1_upstream_waits_for_read) AND unici_core_burst_1_upstream_this_cycle_is_the_last_burst) AND unici_core_burst_1_upstream_burstcount_fifo_empty))) = '1'), unici_core_burst_1_upstream_selected_burstcount, A_WE_StdLogicVector((std_logic'((unici_core_burst_1_upstream_this_cycle_is_the_last_burst)) = '1'), unici_core_burst_1_upstream_transaction_burst_count, unici_core_burst_1_upstream_current_burst_minus_one)));
--the current burst count for unici_core_burst_1_upstream, to be decremented, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_upstream_current_burst <= std_logic_vector'("0000000000");
elsif clk'event and clk = '1' then
if std_logic'((unici_core_burst_1_upstream_readdatavalid_from_sa OR ((NOT unici_core_burst_1_upstream_load_fifo AND ((in_a_read_cycle AND NOT unici_core_burst_1_upstream_waits_for_read)))))) = '1' then
unici_core_burst_1_upstream_current_burst <= unici_core_burst_1_upstream_next_burst_count;
end if;
end if;
end process;
--a 1 or burstcount fifo empty, to initialize the counter, which is an e_mux
p0_unici_core_burst_1_upstream_load_fifo <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((NOT unici_core_burst_1_upstream_load_fifo)) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((((in_a_read_cycle AND NOT unici_core_burst_1_upstream_waits_for_read)) AND unici_core_burst_1_upstream_load_fifo))) = '1'), std_logic_vector'("00000000000000000000000000000001"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT unici_core_burst_1_upstream_burstcount_fifo_empty))))));
--whether to load directly to the counter or to the fifo, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_upstream_load_fifo <= std_logic'('0');
elsif clk'event and clk = '1' then
if std_logic'(((((in_a_read_cycle AND NOT unici_core_burst_1_upstream_waits_for_read)) AND NOT unici_core_burst_1_upstream_load_fifo) OR unici_core_burst_1_upstream_this_cycle_is_the_last_burst)) = '1' then
unici_core_burst_1_upstream_load_fifo <= p0_unici_core_burst_1_upstream_load_fifo;
end if;
end if;
end process;
--the last cycle in the burst for unici_core_burst_1_upstream, which is an e_assign
unici_core_burst_1_upstream_this_cycle_is_the_last_burst <= NOT (or_reduce(unici_core_burst_1_upstream_current_burst_minus_one)) AND unici_core_burst_1_upstream_readdatavalid_from_sa;
--rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_1_upstream, which is an e_fifo_with_registered_outputs
rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_1_upstream : rdv_fifo_for_pcie_compiler_0_Rx_Interface_to_unici_core_burst_1_upstream_module
port map(
data_out => pcie_compiler_0_Rx_Interface_rdv_fifo_output_from_unici_core_burst_1_upstream,
empty => open,
fifo_contains_ones_n => pcie_compiler_0_Rx_Interface_rdv_fifo_empty_unici_core_burst_1_upstream,
full => open,
clear_fifo => module_input12,
clk => clk,
data_in => internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream,
read => unici_core_burst_1_upstream_move_on_to_next_transaction,
reset_n => reset_n,
sync_reset => module_input13,
write => module_input14
);
module_input12 <= std_logic'('0');
module_input13 <= std_logic'('0');
module_input14 <= in_a_read_cycle AND NOT unici_core_burst_1_upstream_waits_for_read;
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register <= NOT pcie_compiler_0_Rx_Interface_rdv_fifo_empty_unici_core_burst_1_upstream;
--local readdatavalid pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream, which is an e_mux
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream <= unici_core_burst_1_upstream_readdatavalid_from_sa;
--unici_core_burst_1_upstream_writedata mux, which is an e_mux
unici_core_burst_1_upstream_writedata <= pcie_compiler_0_Rx_Interface_writedata;
--byteaddress mux for unici_core_burst_1/upstream, which is an e_mux
unici_core_burst_1_upstream_byteaddress <= pcie_compiler_0_Rx_Interface_address_to_slave (20 DOWNTO 0);
--master is always granted when requested
internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream <= internal_pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream;
--pcie_compiler_0/Rx_Interface saved-grant unici_core_burst_1/upstream, which is an e_assign
pcie_compiler_0_Rx_Interface_saved_grant_unici_core_burst_1_upstream <= internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream;
--allow new arb cycle for unici_core_burst_1/upstream, which is an e_assign
unici_core_burst_1_upstream_allow_new_arb_cycle <= std_logic'('1');
--placeholder chosen master
unici_core_burst_1_upstream_grant_vector <= std_logic'('1');
--placeholder vector of master qualified-requests
unici_core_burst_1_upstream_master_qreq_vector <= std_logic'('1');
--unici_core_burst_1_upstream_firsttransfer first transaction, which is an e_assign
unici_core_burst_1_upstream_firsttransfer <= A_WE_StdLogic((std_logic'(unici_core_burst_1_upstream_begins_xfer) = '1'), unici_core_burst_1_upstream_unreg_firsttransfer, unici_core_burst_1_upstream_reg_firsttransfer);
--unici_core_burst_1_upstream_unreg_firsttransfer first transaction, which is an e_assign
unici_core_burst_1_upstream_unreg_firsttransfer <= NOT ((unici_core_burst_1_upstream_slavearbiterlockenable AND unici_core_burst_1_upstream_any_continuerequest));
--unici_core_burst_1_upstream_reg_firsttransfer first transaction, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_upstream_reg_firsttransfer <= std_logic'('1');
elsif clk'event and clk = '1' then
if std_logic'(unici_core_burst_1_upstream_begins_xfer) = '1' then
unici_core_burst_1_upstream_reg_firsttransfer <= unici_core_burst_1_upstream_unreg_firsttransfer;
end if;
end if;
end process;
--unici_core_burst_1_upstream_next_bbt_burstcount next_bbt_burstcount, which is an e_mux
unici_core_burst_1_upstream_next_bbt_burstcount <= A_EXT (A_WE_StdLogicVector((std_logic'((((internal_unici_core_burst_1_upstream_write) AND to_std_logic((((std_logic_vector'("00000000000000000000000") & (unici_core_burst_1_upstream_bbt_burstcounter)) = std_logic_vector'("00000000000000000000000000000000"))))))) = '1'), (((std_logic_vector'("00000000000000000000000") & (internal_unici_core_burst_1_upstream_burstcount)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'((((internal_unici_core_burst_1_upstream_read) AND to_std_logic((((std_logic_vector'("00000000000000000000000") & (unici_core_burst_1_upstream_bbt_burstcounter)) = std_logic_vector'("00000000000000000000000000000000"))))))) = '1'), std_logic_vector'("000000000000000000000000000000000"), (((std_logic_vector'("000000000000000000000000") & (unici_core_burst_1_upstream_bbt_burstcounter)) - std_logic_vector'("000000000000000000000000000000001"))))), 9);
--unici_core_burst_1_upstream_bbt_burstcounter bbt_burstcounter, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_upstream_bbt_burstcounter <= std_logic_vector'("000000000");
elsif clk'event and clk = '1' then
if std_logic'(unici_core_burst_1_upstream_begins_xfer) = '1' then
unici_core_burst_1_upstream_bbt_burstcounter <= unici_core_burst_1_upstream_next_bbt_burstcount;
end if;
end if;
end process;
--unici_core_burst_1_upstream_beginbursttransfer_internal begin burst transfer, which is an e_assign
unici_core_burst_1_upstream_beginbursttransfer_internal <= unici_core_burst_1_upstream_begins_xfer AND to_std_logic((((std_logic_vector'("00000000000000000000000") & (unici_core_burst_1_upstream_bbt_burstcounter)) = std_logic_vector'("00000000000000000000000000000000"))));
--unici_core_burst_1_upstream_read assignment, which is an e_mux
internal_unici_core_burst_1_upstream_read <= internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream AND pcie_compiler_0_Rx_Interface_read;
--unici_core_burst_1_upstream_write assignment, which is an e_mux
internal_unici_core_burst_1_upstream_write <= internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream AND pcie_compiler_0_Rx_Interface_write;
--unici_core_burst_1_upstream_address mux, which is an e_mux
unici_core_burst_1_upstream_address <= pcie_compiler_0_Rx_Interface_address_to_slave (17 DOWNTO 0);
--d1_unici_core_burst_1_upstream_end_xfer register, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
d1_unici_core_burst_1_upstream_end_xfer <= std_logic'('1');
elsif clk'event and clk = '1' then
d1_unici_core_burst_1_upstream_end_xfer <= unici_core_burst_1_upstream_end_xfer;
end if;
end process;
--unici_core_burst_1_upstream_waits_for_read in a cycle, which is an e_mux
unici_core_burst_1_upstream_waits_for_read <= unici_core_burst_1_upstream_in_a_read_cycle AND internal_unici_core_burst_1_upstream_waitrequest_from_sa;
--unici_core_burst_1_upstream_in_a_read_cycle assignment, which is an e_assign
unici_core_burst_1_upstream_in_a_read_cycle <= internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream AND pcie_compiler_0_Rx_Interface_read;
--in_a_read_cycle assignment, which is an e_mux
in_a_read_cycle <= unici_core_burst_1_upstream_in_a_read_cycle;
--unici_core_burst_1_upstream_waits_for_write in a cycle, which is an e_mux
unici_core_burst_1_upstream_waits_for_write <= unici_core_burst_1_upstream_in_a_write_cycle AND internal_unici_core_burst_1_upstream_waitrequest_from_sa;
--unici_core_burst_1_upstream_in_a_write_cycle assignment, which is an e_assign
unici_core_burst_1_upstream_in_a_write_cycle <= internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream AND pcie_compiler_0_Rx_Interface_write;
--in_a_write_cycle assignment, which is an e_mux
in_a_write_cycle <= unici_core_burst_1_upstream_in_a_write_cycle;
wait_for_unici_core_burst_1_upstream_counter <= std_logic'('0');
--unici_core_burst_1_upstream_byteenable byte enable port mux, which is an e_mux
unici_core_burst_1_upstream_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream)) = '1'), (std_logic_vector'("000000000000000000000000") & (pcie_compiler_0_Rx_Interface_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 8);
--burstcount mux, which is an e_mux
internal_unici_core_burst_1_upstream_burstcount <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream)) = '1'), (std_logic_vector'("0000000000000000000000") & (pcie_compiler_0_Rx_Interface_burstcount)), std_logic_vector'("00000000000000000000000000000001")), 10);
--debugaccess mux, which is an e_mux
unici_core_burst_1_upstream_debugaccess <= std_logic'('0');
--vhdl renameroo for output signals
pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream <= internal_pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream;
--vhdl renameroo for output signals
pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream <= internal_pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream;
--vhdl renameroo for output signals
pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream <= internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream;
--vhdl renameroo for output signals
unici_core_burst_1_upstream_burstcount <= internal_unici_core_burst_1_upstream_burstcount;
--vhdl renameroo for output signals
unici_core_burst_1_upstream_read <= internal_unici_core_burst_1_upstream_read;
--vhdl renameroo for output signals
unici_core_burst_1_upstream_waitrequest_from_sa <= internal_unici_core_burst_1_upstream_waitrequest_from_sa;
--vhdl renameroo for output signals
unici_core_burst_1_upstream_write <= internal_unici_core_burst_1_upstream_write;
--synthesis translate_off
--unici_core_burst_1/upstream enable non-zero assertions, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
enable_nonzero_assertions <= std_logic'('0');
elsif clk'event and clk = '1' then
enable_nonzero_assertions <= std_logic'('1');
end if;
end process;
--pcie_compiler_0/Rx_Interface non-zero burstcount assertion, which is an e_process
process (clk)
VARIABLE write_line36 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((internal_pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream AND to_std_logic((((std_logic_vector'("0000000000000000000000") & (pcie_compiler_0_Rx_Interface_burstcount)) = std_logic_vector'("00000000000000000000000000000000"))))) AND enable_nonzero_assertions)) = '1' then
write(write_line36, now);
write(write_line36, string'(": "));
write(write_line36, string'("pcie_compiler_0/Rx_Interface drove 0 on its 'burstcount' port while accessing slave unici_core_burst_1/upstream"));
write(output, write_line36.all);
deallocate (write_line36);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity unici_core_burst_1_downstream_arbitrator is
port (
-- inputs:
signal avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_1_downstream_address : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_downstream_burstcount : IN STD_LOGIC;
signal unici_core_burst_1_downstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 : IN STD_LOGIC;
signal unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 : IN STD_LOGIC;
signal unici_core_burst_1_downstream_read : IN STD_LOGIC;
signal unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0 : IN STD_LOGIC;
signal unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 : IN STD_LOGIC;
signal unici_core_burst_1_downstream_write : IN STD_LOGIC;
signal unici_core_burst_1_downstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal unici_core_burst_1_downstream_address_to_slave : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_downstream_latency_counter : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_downstream_readdatavalid : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_reset_n : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_waitrequest : OUT STD_LOGIC
);
end entity unici_core_burst_1_downstream_arbitrator;
architecture europa of unici_core_burst_1_downstream_arbitrator is
signal active_and_waiting_last_time : STD_LOGIC;
signal internal_unici_core_burst_1_downstream_address_to_slave : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal internal_unici_core_burst_1_downstream_waitrequest : STD_LOGIC;
signal pre_flush_unici_core_burst_1_downstream_readdatavalid : STD_LOGIC;
signal r_0 : STD_LOGIC;
signal unici_core_burst_1_downstream_address_last_time : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_downstream_burstcount_last_time : STD_LOGIC;
signal unici_core_burst_1_downstream_byteenable_last_time : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_1_downstream_read_last_time : STD_LOGIC;
signal unici_core_burst_1_downstream_run : STD_LOGIC;
signal unici_core_burst_1_downstream_write_last_time : STD_LOGIC;
signal unici_core_burst_1_downstream_writedata_last_time : STD_LOGIC_VECTOR (63 DOWNTO 0);
begin
--r_0 master_run cascaded wait assignment, which is an e_assign
r_0 <= Vector_To_Std_Logic((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 OR NOT unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 OR NOT ((unici_core_burst_1_downstream_read OR unici_core_burst_1_downstream_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((unici_core_burst_1_downstream_read OR unici_core_burst_1_downstream_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 OR NOT ((unici_core_burst_1_downstream_read OR unici_core_burst_1_downstream_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((unici_core_burst_1_downstream_read OR unici_core_burst_1_downstream_write)))))))))));
--cascaded wait assignment, which is an e_assign
unici_core_burst_1_downstream_run <= r_0;
--optimize select-logic by passing only those address bits which matter.
internal_unici_core_burst_1_downstream_address_to_slave <= unici_core_burst_1_downstream_address;
--latent slave read data valids which may be flushed, which is an e_mux
pre_flush_unici_core_burst_1_downstream_readdatavalid <= std_logic'('0');
--latent slave read data valid which is not flushed, which is an e_mux
unici_core_burst_1_downstream_readdatavalid <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000000") OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pre_flush_unici_core_burst_1_downstream_readdatavalid)))) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0)))));
--unici_core_burst_1/downstream readdata mux, which is an e_mux
unici_core_burst_1_downstream_readdata <= avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa;
--actual waitrequest port, which is an e_assign
internal_unici_core_burst_1_downstream_waitrequest <= NOT unici_core_burst_1_downstream_run;
--latent max counter, which is an e_assign
unici_core_burst_1_downstream_latency_counter <= std_logic'('0');
--unici_core_burst_1_downstream_reset_n assignment, which is an e_assign
unici_core_burst_1_downstream_reset_n <= reset_n;
--vhdl renameroo for output signals
unici_core_burst_1_downstream_address_to_slave <= internal_unici_core_burst_1_downstream_address_to_slave;
--vhdl renameroo for output signals
unici_core_burst_1_downstream_waitrequest <= internal_unici_core_burst_1_downstream_waitrequest;
--synthesis translate_off
--unici_core_burst_1_downstream_address check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_downstream_address_last_time <= std_logic_vector'("000000000000000000");
elsif clk'event and clk = '1' then
unici_core_burst_1_downstream_address_last_time <= unici_core_burst_1_downstream_address;
end if;
end process;
--unici_core_burst_1/downstream waited last time, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
active_and_waiting_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
active_and_waiting_last_time <= internal_unici_core_burst_1_downstream_waitrequest AND ((unici_core_burst_1_downstream_read OR unici_core_burst_1_downstream_write));
end if;
end process;
--unici_core_burst_1_downstream_address matches last port_name, which is an e_process
process (clk)
VARIABLE write_line37 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((unici_core_burst_1_downstream_address /= unici_core_burst_1_downstream_address_last_time))))) = '1' then
write(write_line37, now);
write(write_line37, string'(": "));
write(write_line37, string'("unici_core_burst_1_downstream_address did not heed wait!!!"));
write(output, write_line37.all);
deallocate (write_line37);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_1_downstream_burstcount check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_downstream_burstcount_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
unici_core_burst_1_downstream_burstcount_last_time <= unici_core_burst_1_downstream_burstcount;
end if;
end process;
--unici_core_burst_1_downstream_burstcount matches last port_name, which is an e_process
process (clk)
VARIABLE write_line38 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(unici_core_burst_1_downstream_burstcount) /= std_logic'(unici_core_burst_1_downstream_burstcount_last_time)))))) = '1' then
write(write_line38, now);
write(write_line38, string'(": "));
write(write_line38, string'("unici_core_burst_1_downstream_burstcount did not heed wait!!!"));
write(output, write_line38.all);
deallocate (write_line38);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_1_downstream_byteenable check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_downstream_byteenable_last_time <= std_logic_vector'("00000000");
elsif clk'event and clk = '1' then
unici_core_burst_1_downstream_byteenable_last_time <= unici_core_burst_1_downstream_byteenable;
end if;
end process;
--unici_core_burst_1_downstream_byteenable matches last port_name, which is an e_process
process (clk)
VARIABLE write_line39 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((unici_core_burst_1_downstream_byteenable /= unici_core_burst_1_downstream_byteenable_last_time))))) = '1' then
write(write_line39, now);
write(write_line39, string'(": "));
write(write_line39, string'("unici_core_burst_1_downstream_byteenable did not heed wait!!!"));
write(output, write_line39.all);
deallocate (write_line39);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_1_downstream_read check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_downstream_read_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
unici_core_burst_1_downstream_read_last_time <= unici_core_burst_1_downstream_read;
end if;
end process;
--unici_core_burst_1_downstream_read matches last port_name, which is an e_process
process (clk)
VARIABLE write_line40 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(unici_core_burst_1_downstream_read) /= std_logic'(unici_core_burst_1_downstream_read_last_time)))))) = '1' then
write(write_line40, now);
write(write_line40, string'(": "));
write(write_line40, string'("unici_core_burst_1_downstream_read did not heed wait!!!"));
write(output, write_line40.all);
deallocate (write_line40);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_1_downstream_write check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_downstream_write_last_time <= std_logic'('0');
elsif clk'event and clk = '1' then
unici_core_burst_1_downstream_write_last_time <= unici_core_burst_1_downstream_write;
end if;
end process;
--unici_core_burst_1_downstream_write matches last port_name, which is an e_process
process (clk)
VARIABLE write_line41 : line;
begin
if clk'event and clk = '1' then
if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(unici_core_burst_1_downstream_write) /= std_logic'(unici_core_burst_1_downstream_write_last_time)))))) = '1' then
write(write_line41, now);
write(write_line41, string'(": "));
write(write_line41, string'("unici_core_burst_1_downstream_write did not heed wait!!!"));
write(output, write_line41.all);
deallocate (write_line41);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--unici_core_burst_1_downstream_writedata check against wait, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unici_core_burst_1_downstream_writedata_last_time <= std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000");
elsif clk'event and clk = '1' then
unici_core_burst_1_downstream_writedata_last_time <= unici_core_burst_1_downstream_writedata;
end if;
end process;
--unici_core_burst_1_downstream_writedata matches last port_name, which is an e_process
process (clk)
VARIABLE write_line42 : line;
begin
if clk'event and clk = '1' then
if std_logic'(((active_and_waiting_last_time AND to_std_logic(((unici_core_burst_1_downstream_writedata /= unici_core_burst_1_downstream_writedata_last_time)))) AND unici_core_burst_1_downstream_write)) = '1' then
write(write_line42, now);
write(write_line42, string'(": "));
write(write_line42, string'("unici_core_burst_1_downstream_writedata did not heed wait!!!"));
write(output, write_line42.all);
deallocate (write_line42);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end process;
--synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity unici_core_reset_pcie_compiler_0_pcie_core_clk_out_domain_synch_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity unici_core_reset_pcie_compiler_0_pcie_core_clk_out_domain_synch_module;
architecture europa of unici_core_reset_pcie_compiler_0_pcie_core_clk_out_domain_synch_module is
signal data_in_d1 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "{-from ""*""} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101";
begin
process (clk, reset_n)
begin
if reset_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clk'event and clk = '1' then
data_in_d1 <= data_in;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
data_out <= std_logic'('0');
elsif clk'event and clk = '1' then
data_out <= data_in_d1;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity unici_core is
port (
-- 1) global signals:
signal pcie_compiler_0_pcie_core_clk_out : OUT STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- the_avalon64_to_avalon8_0
signal out_address_from_the_avalon64_to_avalon8_0 : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal out_read_from_the_avalon64_to_avalon8_0 : OUT STD_LOGIC;
signal out_readdata_to_the_avalon64_to_avalon8_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal out_waitrequest_to_the_avalon64_to_avalon8_0 : IN STD_LOGIC;
signal out_write_from_the_avalon64_to_avalon8_0 : OUT STD_LOGIC;
signal out_writedata_from_the_avalon64_to_avalon8_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-- the_ci_bridge_0
signal cam0_bypass_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam0_fail_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam0_ready_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam1_bypass_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam1_fail_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam1_ready_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam_address_to_the_ci_bridge_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal cam_interrupts_from_the_ci_bridge_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cam_read_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cam_readdata_from_the_ci_bridge_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_waitreq_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam_write_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cam_writedata_to_the_ci_bridge_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ci_a_from_the_ci_bridge_0 : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal ci_bus_dir_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_d_en_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_d_in_to_the_ci_bridge_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ci_d_out_from_the_ci_bridge_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ci_iord_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_iowr_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_oe_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_reg_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_we_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cia_cd_n_to_the_ci_bridge_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cia_ce_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cia_data_buf_oe_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cia_ireq_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cia_overcurrent_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cia_reset_buf_oe_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cia_reset_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cia_wait_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cib_cd_n_to_the_ci_bridge_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cib_ce_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cib_data_buf_oe_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cib_ireq_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cib_overcurrent_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cib_reset_buf_oe_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cib_reset_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cib_wait_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal interrupt_from_the_ci_bridge_0 : OUT STD_LOGIC;
-- the_dma_arbiter_0
signal dma0_addr_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (60 DOWNTO 0);
signal dma0_byteen_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma0_size_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma0_wait_from_the_dma_arbiter_0 : OUT STD_LOGIC;
signal dma0_wrdata_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal dma0_write_to_the_dma_arbiter_0 : IN STD_LOGIC;
signal dma1_addr_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (60 DOWNTO 0);
signal dma1_byteen_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma1_size_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma1_wait_from_the_dma_arbiter_0 : OUT STD_LOGIC;
signal dma1_wrdata_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal dma1_write_to_the_dma_arbiter_0 : IN STD_LOGIC;
-- the_dvb_dma_0
signal dvb_data_to_the_dvb_dma_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_dval_to_the_dvb_dma_0 : IN STD_LOGIC;
signal dvb_sop_to_the_dvb_dma_0 : IN STD_LOGIC;
signal interrupt_from_the_dvb_dma_0 : OUT STD_LOGIC;
signal mem_addr_from_the_dvb_dma_0 : OUT STD_LOGIC_VECTOR (60 DOWNTO 0);
signal mem_byteen_from_the_dvb_dma_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_size_from_the_dvb_dma_0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
signal mem_waitreq_to_the_dvb_dma_0 : IN STD_LOGIC;
signal mem_wrdata_from_the_dvb_dma_0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal mem_write_from_the_dvb_dma_0 : OUT STD_LOGIC;
-- the_dvb_dma_1
signal dvb_data_to_the_dvb_dma_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_dval_to_the_dvb_dma_1 : IN STD_LOGIC;
signal dvb_sop_to_the_dvb_dma_1 : IN STD_LOGIC;
signal interrupt_from_the_dvb_dma_1 : OUT STD_LOGIC;
signal mem_addr_from_the_dvb_dma_1 : OUT STD_LOGIC_VECTOR (60 DOWNTO 0);
signal mem_byteen_from_the_dvb_dma_1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_size_from_the_dvb_dma_1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
signal mem_waitreq_to_the_dvb_dma_1 : IN STD_LOGIC;
signal mem_wrdata_from_the_dvb_dma_1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal mem_write_from_the_dvb_dma_1 : OUT STD_LOGIC;
-- the_dvb_ts_0
signal cam_baseclk_to_the_dvb_ts_0 : IN STD_LOGIC;
signal cam_bypass_to_the_dvb_ts_0 : IN STD_LOGIC;
signal cam_mclki_from_the_dvb_ts_0 : OUT STD_LOGIC;
signal cam_mclko_to_the_dvb_ts_0 : IN STD_LOGIC;
signal cam_mdi_from_the_dvb_ts_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mdo_to_the_dvb_ts_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mistrt_from_the_dvb_ts_0 : OUT STD_LOGIC;
signal cam_mival_from_the_dvb_ts_0 : OUT STD_LOGIC;
signal cam_mostrt_to_the_dvb_ts_0 : IN STD_LOGIC;
signal cam_moval_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in0_data_to_the_dvb_ts_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in0_dsop_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in0_dval_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in1_data_to_the_dvb_ts_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in1_dsop_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in1_dval_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in2_data_to_the_dvb_ts_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in2_dsop_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in2_dval_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_out_data_from_the_dvb_ts_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_out_dsop_from_the_dvb_ts_0 : OUT STD_LOGIC;
signal dvb_out_dval_from_the_dvb_ts_0 : OUT STD_LOGIC;
signal interrupt_from_the_dvb_ts_0 : OUT STD_LOGIC;
-- the_dvb_ts_1
signal cam_baseclk_to_the_dvb_ts_1 : IN STD_LOGIC;
signal cam_bypass_to_the_dvb_ts_1 : IN STD_LOGIC;
signal cam_mclki_from_the_dvb_ts_1 : OUT STD_LOGIC;
signal cam_mclko_to_the_dvb_ts_1 : IN STD_LOGIC;
signal cam_mdi_from_the_dvb_ts_1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mdo_to_the_dvb_ts_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mistrt_from_the_dvb_ts_1 : OUT STD_LOGIC;
signal cam_mival_from_the_dvb_ts_1 : OUT STD_LOGIC;
signal cam_mostrt_to_the_dvb_ts_1 : IN STD_LOGIC;
signal cam_moval_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in0_data_to_the_dvb_ts_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in0_dsop_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in0_dval_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in1_data_to_the_dvb_ts_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in1_dsop_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in1_dval_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in2_data_to_the_dvb_ts_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in2_dsop_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in2_dval_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_out_data_from_the_dvb_ts_1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_out_dsop_from_the_dvb_ts_1 : OUT STD_LOGIC;
signal dvb_out_dval_from_the_dvb_ts_1 : OUT STD_LOGIC;
signal interrupt_from_the_dvb_ts_1 : OUT STD_LOGIC;
-- the_fifo_in_8b_sync_0
signal irq_from_the_fifo_in_8b_sync_0 : OUT STD_LOGIC;
-- the_fifo_in_8b_sync_1
signal irq_from_the_fifo_in_8b_sync_1 : OUT STD_LOGIC;
-- the_fifo_out_8b_sync_0
signal irq_from_the_fifo_out_8b_sync_0 : OUT STD_LOGIC;
-- the_fifo_out_8b_sync_1
signal irq_from_the_fifo_out_8b_sync_1 : OUT STD_LOGIC;
-- the_gpout_0
signal pins_from_the_gpout_0 : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
-- the_int_ctrl_0
signal avlm_irq_to_the_int_ctrl_0 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- the_pcie_compiler_0
signal busy_altgxb_reconfig_pcie_compiler_0 : IN STD_LOGIC;
signal clk125_out_pcie_compiler_0 : OUT STD_LOGIC;
signal clk250_out_pcie_compiler_0 : OUT STD_LOGIC;
signal clk500_out_pcie_compiler_0 : OUT STD_LOGIC;
signal fixedclk_serdes_pcie_compiler_0 : IN STD_LOGIC;
signal gxb_powerdown_pcie_compiler_0 : IN STD_LOGIC;
signal pcie_rstn_pcie_compiler_0 : IN STD_LOGIC;
signal phystatus_ext_pcie_compiler_0 : IN STD_LOGIC;
signal pipe_mode_pcie_compiler_0 : IN STD_LOGIC;
signal pll_powerdown_pcie_compiler_0 : IN STD_LOGIC;
signal powerdown_ext_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rate_ext_pcie_compiler_0 : OUT STD_LOGIC;
signal reconfig_clk_pcie_compiler_0 : IN STD_LOGIC;
signal reconfig_fromgxb_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reconfig_togxb_pcie_compiler_0 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk_pcie_compiler_0 : IN STD_LOGIC;
signal rx_in0_pcie_compiler_0 : IN STD_LOGIC;
signal rxdata0_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext_pcie_compiler_0 : IN STD_LOGIC;
signal rxelecidle0_ext_pcie_compiler_0 : IN STD_LOGIC;
signal rxpolarity0_ext_pcie_compiler_0 : OUT STD_LOGIC;
signal rxstatus0_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext_pcie_compiler_0 : IN STD_LOGIC;
signal test_in_pcie_compiler_0 : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal tx_out0_pcie_compiler_0 : OUT STD_LOGIC;
signal txcompl0_ext_pcie_compiler_0 : OUT STD_LOGIC;
signal txdata0_ext_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext_pcie_compiler_0 : OUT STD_LOGIC;
signal txdetectrx_ext_pcie_compiler_0 : OUT STD_LOGIC;
signal txelecidle0_ext_pcie_compiler_0 : OUT STD_LOGIC;
-- the_spi_master_0
signal cs_n_from_the_spi_master_0 : OUT STD_LOGIC;
signal irq_from_the_spi_master_0 : OUT STD_LOGIC;
signal miso_to_the_spi_master_0 : IN STD_LOGIC;
signal mosi_from_the_spi_master_0 : OUT STD_LOGIC;
signal sclk_from_the_spi_master_0 : OUT STD_LOGIC;
-- the_twi_master_0
signal irq_from_the_twi_master_0 : OUT STD_LOGIC;
signal scl_act_from_the_twi_master_0 : OUT STD_LOGIC;
signal scl_in_to_the_twi_master_0 : IN STD_LOGIC;
signal sda_act_from_the_twi_master_0 : OUT STD_LOGIC;
signal sda_in_to_the_twi_master_0 : IN STD_LOGIC;
signal sink_irq_to_the_twi_master_0 : IN STD_LOGIC;
signal source_irq_to_the_twi_master_0 : IN STD_LOGIC;
-- the_twi_master_1
signal irq_from_the_twi_master_1 : OUT STD_LOGIC;
signal scl_act_from_the_twi_master_1 : OUT STD_LOGIC;
signal scl_in_to_the_twi_master_1 : IN STD_LOGIC;
signal sda_act_from_the_twi_master_1 : OUT STD_LOGIC;
signal sda_in_to_the_twi_master_1 : IN STD_LOGIC;
signal sink_irq_to_the_twi_master_1 : IN STD_LOGIC;
signal source_irq_to_the_twi_master_1 : IN STD_LOGIC
);
end entity unici_core;
architecture europa of unici_core is
component avalon64_to_avalon8_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal avalon64_to_avalon8_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_1_downstream_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_downstream_arbitrationshare : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_downstream_burstcount : IN STD_LOGIC;
signal unici_core_burst_1_downstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_1_downstream_latency_counter : IN STD_LOGIC;
signal unici_core_burst_1_downstream_read : IN STD_LOGIC;
signal unici_core_burst_1_downstream_write : IN STD_LOGIC;
signal unici_core_burst_1_downstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal avalon64_to_avalon8_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_read : OUT STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_write : OUT STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0 : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 : OUT STD_LOGIC
);
end component avalon64_to_avalon8_0_avalon_slave_0_arbitrator;
component avalon64_to_avalon8_0 is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal out_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal out_waitrequest : IN STD_LOGIC;
signal read : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal out_address : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal out_read : OUT STD_LOGIC;
signal out_write : OUT STD_LOGIC;
signal out_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal waitrequest : OUT STD_LOGIC
);
end component avalon64_to_avalon8_0;
component ci_bridge_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal ci_bridge_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal ci_bridge_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_write : OUT STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal d1_ci_bridge_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_ci_bridge_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0 : OUT STD_LOGIC
);
end component ci_bridge_0_avalon_slave_0_arbitrator;
component ci_bridge_0 is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cam_address : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal cam_read : IN STD_LOGIC;
signal cam_write : IN STD_LOGIC;
signal cam_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ci_d_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cia_cd_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cia_ireq_n : IN STD_LOGIC;
signal cia_overcurrent_n : IN STD_LOGIC;
signal cia_wait_n : IN STD_LOGIC;
signal cib_cd_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cib_ireq_n : IN STD_LOGIC;
signal cib_overcurrent_n : IN STD_LOGIC;
signal cib_wait_n : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal cam0_bypass : OUT STD_LOGIC;
signal cam0_fail : OUT STD_LOGIC;
signal cam0_ready : OUT STD_LOGIC;
signal cam1_bypass : OUT STD_LOGIC;
signal cam1_fail : OUT STD_LOGIC;
signal cam1_ready : OUT STD_LOGIC;
signal cam_interrupts : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cam_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_waitreq : OUT STD_LOGIC;
signal ci_a : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal ci_bus_dir : OUT STD_LOGIC;
signal ci_d_en : OUT STD_LOGIC;
signal ci_d_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ci_iord_n : OUT STD_LOGIC;
signal ci_iowr_n : OUT STD_LOGIC;
signal ci_oe_n : OUT STD_LOGIC;
signal ci_reg_n : OUT STD_LOGIC;
signal ci_we_n : OUT STD_LOGIC;
signal cia_ce_n : OUT STD_LOGIC;
signal cia_data_buf_oe_n : OUT STD_LOGIC;
signal cia_reset : OUT STD_LOGIC;
signal cia_reset_buf_oe_n : OUT STD_LOGIC;
signal cib_ce_n : OUT STD_LOGIC;
signal cib_data_buf_oe_n : OUT STD_LOGIC;
signal cib_reset : OUT STD_LOGIC;
signal cib_reset_buf_oe_n : OUT STD_LOGIC;
signal interrupt : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component ci_bridge_0;
component dma_arbiter_0_avalon_master_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal d1_pcie_compiler_0_Tx_Interface_end_xfer : IN STD_LOGIC;
signal dma_arbiter_0_avalon_master_address : IN STD_LOGIC_VECTOR (30 DOWNTO 0);
signal dma_arbiter_0_avalon_master_burstcount : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma_arbiter_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma_arbiter_0_avalon_master_write : IN STD_LOGIC;
signal dma_arbiter_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface : IN STD_LOGIC;
signal dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface : IN STD_LOGIC;
signal dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface : IN STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_waitrequest_from_sa : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal dma_arbiter_0_avalon_master_address_to_slave : OUT STD_LOGIC_VECTOR (30 DOWNTO 0);
signal dma_arbiter_0_avalon_master_reset : OUT STD_LOGIC;
signal dma_arbiter_0_avalon_master_waitrequest : OUT STD_LOGIC
);
end component dma_arbiter_0_avalon_master_arbitrator;
component dma_arbiter_0 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dma0_addr : IN STD_LOGIC_VECTOR (60 DOWNTO 0);
signal dma0_byteen : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma0_size : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma0_wrdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal dma0_write : IN STD_LOGIC;
signal dma1_addr : IN STD_LOGIC_VECTOR (60 DOWNTO 0);
signal dma1_byteen : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma1_size : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma1_wrdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal dma1_write : IN STD_LOGIC;
signal mem_waitreq : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
-- outputs:
signal dma0_wait : OUT STD_LOGIC;
signal dma1_wait : OUT STD_LOGIC;
signal mem_addr : OUT STD_LOGIC_VECTOR (30 DOWNTO 0);
signal mem_byteen : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_size : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
signal mem_wrdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal mem_write : OUT STD_LOGIC
);
end component dma_arbiter_0;
component dvb_dma_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_dvb_dma_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_write : OUT STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_dma_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0 : OUT STD_LOGIC
);
end component dvb_dma_0_avalon_slave_0_arbitrator;
component dvb_dma_0 is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dvb_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_dval : IN STD_LOGIC;
signal dvb_sop : IN STD_LOGIC;
signal mem_waitreq : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal interrupt : OUT STD_LOGIC;
signal mem_addr : OUT STD_LOGIC_VECTOR (60 DOWNTO 0);
signal mem_byteen : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_size : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
signal mem_wrdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal mem_write : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component dvb_dma_0;
component dvb_dma_1_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_dvb_dma_1_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_reset : OUT STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_write : OUT STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_dma_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0 : OUT STD_LOGIC
);
end component dvb_dma_1_avalon_slave_0_arbitrator;
component dvb_dma_1 is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal dvb_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_dval : IN STD_LOGIC;
signal dvb_sop : IN STD_LOGIC;
signal mem_waitreq : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal interrupt : OUT STD_LOGIC;
signal mem_addr : OUT STD_LOGIC_VECTOR (60 DOWNTO 0);
signal mem_byteen : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_size : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
signal mem_wrdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal mem_write : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component dvb_dma_1;
component dvb_ts_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_dvb_ts_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_read : OUT STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_write : OUT STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_ts_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0 : OUT STD_LOGIC
);
end component dvb_ts_0_avalon_slave_0_arbitrator;
component dvb_ts_0 is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal cam_baseclk : IN STD_LOGIC;
signal cam_bypass : IN STD_LOGIC;
signal cam_mclko : IN STD_LOGIC;
signal cam_mdo : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mostrt : IN STD_LOGIC;
signal cam_moval : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal dvb_in0_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in0_dsop : IN STD_LOGIC;
signal dvb_in0_dval : IN STD_LOGIC;
signal dvb_in1_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in1_dsop : IN STD_LOGIC;
signal dvb_in1_dval : IN STD_LOGIC;
signal dvb_in2_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in2_dsop : IN STD_LOGIC;
signal dvb_in2_dval : IN STD_LOGIC;
signal read : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal cam_mclki : OUT STD_LOGIC;
signal cam_mdi : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mistrt : OUT STD_LOGIC;
signal cam_mival : OUT STD_LOGIC;
signal dvb_out_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_out_dsop : OUT STD_LOGIC;
signal dvb_out_dval : OUT STD_LOGIC;
signal interrupt : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal waitrequest : OUT STD_LOGIC
);
end component dvb_ts_0;
component dvb_ts_1_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_dvb_ts_1_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_read : OUT STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_reset : OUT STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_write : OUT STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_ts_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0 : OUT STD_LOGIC
);
end component dvb_ts_1_avalon_slave_0_arbitrator;
component dvb_ts_1 is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal cam_baseclk : IN STD_LOGIC;
signal cam_bypass : IN STD_LOGIC;
signal cam_mclko : IN STD_LOGIC;
signal cam_mdo : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mostrt : IN STD_LOGIC;
signal cam_moval : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal dvb_in0_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in0_dsop : IN STD_LOGIC;
signal dvb_in0_dval : IN STD_LOGIC;
signal dvb_in1_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in1_dsop : IN STD_LOGIC;
signal dvb_in1_dval : IN STD_LOGIC;
signal dvb_in2_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in2_dsop : IN STD_LOGIC;
signal dvb_in2_dval : IN STD_LOGIC;
signal read : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- outputs:
signal cam_mclki : OUT STD_LOGIC;
signal cam_mdi : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mistrt : OUT STD_LOGIC;
signal cam_mival : OUT STD_LOGIC;
signal dvb_out_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_out_dsop : OUT STD_LOGIC;
signal dvb_out_dval : OUT STD_LOGIC;
signal interrupt : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal waitrequest : OUT STD_LOGIC
);
end component dvb_ts_1;
component fifo_in_8b_sync_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_read : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_write : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC
);
end component fifo_in_8b_sync_0_avalon_slave_0_arbitrator;
component fifo_in_8b_sync_0_avalon_streaming_sink_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_streaming_sink_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_0_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_0_avalon_streaming_source_valid : IN STD_LOGIC;
-- outputs:
signal fifo_in_8b_sync_0_avalon_streaming_sink_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa : OUT STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_streaming_sink_valid : OUT STD_LOGIC
);
end component fifo_in_8b_sync_0_avalon_streaming_sink_arbitrator;
component fifo_in_8b_sync_0 is
port (
-- inputs:
signal addr : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal byte_en : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rd_en : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal st_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal st_valid : IN STD_LOGIC;
signal wr_en : IN STD_LOGIC;
-- outputs:
signal irq : OUT STD_LOGIC;
signal out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal st_ready : OUT STD_LOGIC;
signal wait_req : OUT STD_LOGIC
);
end component fifo_in_8b_sync_0;
component fifo_in_8b_sync_1_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_read : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_reset : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_write : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC
);
end component fifo_in_8b_sync_1_avalon_slave_0_arbitrator;
component fifo_in_8b_sync_1_avalon_streaming_sink_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_streaming_sink_ready : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_1_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_1_avalon_streaming_source_valid : IN STD_LOGIC;
-- outputs:
signal fifo_in_8b_sync_1_avalon_streaming_sink_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa : OUT STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_streaming_sink_valid : OUT STD_LOGIC
);
end component fifo_in_8b_sync_1_avalon_streaming_sink_arbitrator;
component fifo_in_8b_sync_1 is
port (
-- inputs:
signal addr : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal byte_en : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rd_en : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal st_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal st_valid : IN STD_LOGIC;
signal wr_en : IN STD_LOGIC;
-- outputs:
signal irq : OUT STD_LOGIC;
signal out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal st_ready : OUT STD_LOGIC;
signal wait_req : OUT STD_LOGIC
);
end component fifo_in_8b_sync_1;
component fifo_out_8b_sync_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_write : OUT STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0 : OUT STD_LOGIC
);
end component fifo_out_8b_sync_0_avalon_slave_0_arbitrator;
component fifo_out_8b_sync_0_avalon_streaming_source_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_streaming_source_valid : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_0_avalon_streaming_sink_ready_from_sa : IN STD_LOGIC;
-- outputs:
signal fifo_out_8b_sync_0_avalon_streaming_source_ready : OUT STD_LOGIC
);
end component fifo_out_8b_sync_0_avalon_streaming_source_arbitrator;
component fifo_out_8b_sync_0 is
port (
-- inputs:
signal addr : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal byte_en : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rst : IN STD_LOGIC;
signal st_ready : IN STD_LOGIC;
signal wr_en : IN STD_LOGIC;
-- outputs:
signal irq : OUT STD_LOGIC;
signal out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal st_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal st_valid : OUT STD_LOGIC;
signal wait_req : OUT STD_LOGIC
);
end component fifo_out_8b_sync_0;
component fifo_out_8b_sync_1_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_waitrequest : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_reset : OUT STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_write : OUT STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0 : OUT STD_LOGIC
);
end component fifo_out_8b_sync_1_avalon_slave_0_arbitrator;
component fifo_out_8b_sync_1_avalon_streaming_source_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_streaming_source_valid : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_1_avalon_streaming_sink_ready_from_sa : IN STD_LOGIC;
-- outputs:
signal fifo_out_8b_sync_1_avalon_streaming_source_ready : OUT STD_LOGIC
);
end component fifo_out_8b_sync_1_avalon_streaming_source_arbitrator;
component fifo_out_8b_sync_1 is
port (
-- inputs:
signal addr : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal byte_en : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal rst : IN STD_LOGIC;
signal st_ready : IN STD_LOGIC;
signal wr_en : IN STD_LOGIC;
-- outputs:
signal irq : OUT STD_LOGIC;
signal out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal st_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal st_valid : OUT STD_LOGIC;
signal wait_req : OUT STD_LOGIC
);
end component fifo_out_8b_sync_1;
component gpout_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal gpout_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_gpout_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal gpout_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal gpout_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal gpout_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal gpout_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal gpout_0_avalon_slave_0_write : OUT STD_LOGIC;
signal gpout_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_gpout_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0 : OUT STD_LOGIC
);
end component gpout_0_avalon_slave_0_arbitrator;
component gpout_0 is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal pins : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component gpout_0;
component int_ctrl_0_avalon_cra_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_cra_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_int_ctrl_0_avalon_cra_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_cra_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_cra_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_cra_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_cra_write : OUT STD_LOGIC;
signal int_ctrl_0_avalon_cra_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_int_ctrl_0_avalon_cra : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra : OUT STD_LOGIC
);
end component int_ctrl_0_avalon_cra_arbitrator;
component int_ctrl_0_avalon_slave_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_slave_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_slave_waitrequest : IN STD_LOGIC;
signal pipeline_bridge_0_m1_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal pipeline_bridge_0_m1_burstcount : IN STD_LOGIC;
signal pipeline_bridge_0_m1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pipeline_bridge_0_m1_chipselect : IN STD_LOGIC;
signal pipeline_bridge_0_m1_dbs_address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal pipeline_bridge_0_m1_dbs_write_32 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pipeline_bridge_0_m1_latency_counter : IN STD_LOGIC;
signal pipeline_bridge_0_m1_read : IN STD_LOGIC;
signal pipeline_bridge_0_m1_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_int_ctrl_0_avalon_slave_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_slave_address : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
signal int_ctrl_0_avalon_slave_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_slave_read : OUT STD_LOGIC;
signal int_ctrl_0_avalon_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_slave_reset : OUT STD_LOGIC;
signal int_ctrl_0_avalon_slave_waitrequest_from_sa : OUT STD_LOGIC;
signal int_ctrl_0_avalon_slave_write : OUT STD_LOGIC;
signal int_ctrl_0_avalon_slave_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave : OUT STD_LOGIC;
signal pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave : OUT STD_LOGIC;
signal pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave : OUT STD_LOGIC;
signal pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave : OUT STD_LOGIC
);
end component int_ctrl_0_avalon_slave_arbitrator;
component int_ctrl_0_avalon_master_arbitrator is
port (
-- inputs:
signal ci_bridge_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal d1_ci_bridge_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_dvb_dma_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_dvb_dma_1_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_dvb_ts_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_dvb_ts_1_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_gpout_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_int_ctrl_0_avalon_cra_end_xfer : IN STD_LOGIC;
signal d1_pcie_compiler_0_Control_Register_Access_end_xfer : IN STD_LOGIC;
signal d1_spi_master_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_twi_master_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal d1_twi_master_1_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal gpout_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_cra_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_ci_bridge_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_dma_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_dma_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_ts_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_ts_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_gpout_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_int_ctrl_0_avalon_cra : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_pcie_compiler_0_Control_Register_Access : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_spi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_twi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_twi_master_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0 : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_waitrequest_from_sa : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal spi_master_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal spi_master_0_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal twi_master_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_1_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal int_ctrl_0_avalon_master_address_to_slave : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_waitrequest : OUT STD_LOGIC
);
end component int_ctrl_0_avalon_master_arbitrator;
component int_ctrl_0 is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal avlm_irq : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal avlm_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal avlm_waitrequest : IN STD_LOGIC;
signal avls_address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
signal avls_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal avls_read : IN STD_LOGIC;
signal avls_write : IN STD_LOGIC;
signal avls_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal byteenable : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal write : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal avlm_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal avlm_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal avlm_read : OUT STD_LOGIC;
signal avlm_write : OUT STD_LOGIC;
signal avlm_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal avls_irq : OUT STD_LOGIC;
signal avls_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal avls_waitrequest : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component int_ctrl_0;
component pcie_compiler_0_Control_Register_Access_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_pcie_compiler_0_Control_Register_Access_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_pcie_compiler_0_Control_Register_Access : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access : OUT STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_address : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_chipselect : OUT STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_read : OUT STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_waitrequest_from_sa : OUT STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_write : OUT STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component pcie_compiler_0_Control_Register_Access_arbitrator;
component pcie_compiler_0_Tx_Interface_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal dma_arbiter_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (30 DOWNTO 0);
signal dma_arbiter_0_avalon_master_burstcount : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma_arbiter_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma_arbiter_0_avalon_master_write : IN STD_LOGIC;
signal dma_arbiter_0_avalon_master_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_readdatavalid : IN STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal d1_pcie_compiler_0_Tx_Interface_end_xfer : OUT STD_LOGIC;
signal dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface : OUT STD_LOGIC;
signal dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface : OUT STD_LOGIC;
signal dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_address : OUT STD_LOGIC_VECTOR (27 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_burstcount : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_chipselect : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_read : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_readdata_from_sa : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_readdatavalid_from_sa : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_waitrequest_from_sa : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_write : OUT STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
end component pcie_compiler_0_Tx_Interface_arbitrator;
component pcie_compiler_0_Rx_Interface_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal d1_unici_core_burst_0_upstream_end_xfer : IN STD_LOGIC;
signal d1_unici_core_burst_1_upstream_end_xfer : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_address : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_burstcount : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_write : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_0_upstream_readdata_from_sa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_upstream_waitrequest_from_sa : IN STD_LOGIC;
signal unici_core_burst_1_upstream_readdata_from_sa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_upstream_waitrequest_from_sa : IN STD_LOGIC;
-- outputs:
signal pcie_compiler_0_Rx_Interface_address_to_slave : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_latency_counter : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_readdatavalid : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_reset_n : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_waitrequest : OUT STD_LOGIC
);
end component pcie_compiler_0_Rx_Interface_arbitrator;
component pcie_compiler_0 is
port (
-- inputs:
signal AvlClk_i : IN STD_LOGIC;
signal CraAddress_i : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal CraByteEnable_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal CraChipSelect_i : IN STD_LOGIC;
signal CraRead : IN STD_LOGIC;
signal CraWrite : IN STD_LOGIC;
signal CraWriteData_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal RxmIrqNum_i : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal RxmIrq_i : IN STD_LOGIC;
signal RxmReadDataValid_i : IN STD_LOGIC;
signal RxmReadData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal RxmWaitRequest_i : IN STD_LOGIC;
signal TxsAddress_i : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
signal TxsBurstCount_i : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal TxsByteEnable_i : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal TxsChipSelect_i : IN STD_LOGIC;
signal TxsRead_i : IN STD_LOGIC;
signal TxsWriteData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal TxsWrite_i : IN STD_LOGIC;
signal busy_altgxb_reconfig : IN STD_LOGIC;
signal cal_blk_clk : IN STD_LOGIC;
signal fixedclk_serdes : IN STD_LOGIC;
signal gxb_powerdown : IN STD_LOGIC;
signal pcie_rstn : IN STD_LOGIC;
signal phystatus_ext : IN STD_LOGIC;
signal pipe_mode : IN STD_LOGIC;
signal pll_powerdown : IN STD_LOGIC;
signal reconfig_clk : IN STD_LOGIC;
signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal rx_in0 : IN STD_LOGIC;
signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext : IN STD_LOGIC;
signal rxelecidle0_ext : IN STD_LOGIC;
signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
-- outputs:
signal CraIrq_o : OUT STD_LOGIC;
signal CraReadData_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal CraWaitRequest_o : OUT STD_LOGIC;
signal RxmAddress_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal RxmBurstCount_o : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal RxmByteEnable_o : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal RxmRead_o : OUT STD_LOGIC;
signal RxmResetRequest_o : OUT STD_LOGIC;
signal RxmWriteData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal RxmWrite_o : OUT STD_LOGIC;
signal TxsReadDataValid_o : OUT STD_LOGIC;
signal TxsReadData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal TxsWaitRequest_o : OUT STD_LOGIC;
signal clk125_out : OUT STD_LOGIC;
signal clk250_out : OUT STD_LOGIC;
signal clk500_out : OUT STD_LOGIC;
signal pcie_core_clk : OUT STD_LOGIC;
signal powerdown_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rate_ext : OUT STD_LOGIC;
signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal rxpolarity0_ext : OUT STD_LOGIC;
signal tx_out0 : OUT STD_LOGIC;
signal txcompl0_ext : OUT STD_LOGIC;
signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext : OUT STD_LOGIC;
signal txdetectrx_ext : OUT STD_LOGIC;
signal txelecidle0_ext : OUT STD_LOGIC
);
end component pcie_compiler_0;
component pipeline_bridge_0_s1_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal pipeline_bridge_0_s1_endofpacket : IN STD_LOGIC;
signal pipeline_bridge_0_s1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_s1_readdatavalid : IN STD_LOGIC;
signal pipeline_bridge_0_s1_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_0_downstream_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_arbitrationshare : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_downstream_burstcount : IN STD_LOGIC;
signal unici_core_burst_0_downstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_0_downstream_debugaccess : IN STD_LOGIC;
signal unici_core_burst_0_downstream_latency_counter : IN STD_LOGIC;
signal unici_core_burst_0_downstream_nativeaddress : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_read : IN STD_LOGIC;
signal unici_core_burst_0_downstream_write : IN STD_LOGIC;
signal unici_core_burst_0_downstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal d1_pipeline_bridge_0_s1_end_xfer : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_address : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal pipeline_bridge_0_s1_arbiterlock : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_arbiterlock2 : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_burstcount : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pipeline_bridge_0_s1_chipselect : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_debugaccess : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_endofpacket_from_sa : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal pipeline_bridge_0_s1_read : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_s1_reset_n : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_waitrequest_from_sa : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_write : OUT STD_LOGIC;
signal pipeline_bridge_0_s1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1 : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1_shift_register : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 : OUT STD_LOGIC
);
end component pipeline_bridge_0_s1_arbitrator;
component pipeline_bridge_0_m1_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal d1_int_ctrl_0_avalon_slave_end_xfer : IN STD_LOGIC;
signal int_ctrl_0_avalon_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_slave_waitrequest_from_sa : IN STD_LOGIC;
signal pipeline_bridge_0_m1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal pipeline_bridge_0_m1_burstcount : IN STD_LOGIC;
signal pipeline_bridge_0_m1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pipeline_bridge_0_m1_chipselect : IN STD_LOGIC;
signal pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave : IN STD_LOGIC;
signal pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave : IN STD_LOGIC;
signal pipeline_bridge_0_m1_read : IN STD_LOGIC;
signal pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave : IN STD_LOGIC;
signal pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave : IN STD_LOGIC;
signal pipeline_bridge_0_m1_write : IN STD_LOGIC;
signal pipeline_bridge_0_m1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
-- outputs:
signal pipeline_bridge_0_m1_address_to_slave : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal pipeline_bridge_0_m1_dbs_address : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal pipeline_bridge_0_m1_dbs_write_32 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pipeline_bridge_0_m1_latency_counter : OUT STD_LOGIC;
signal pipeline_bridge_0_m1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_m1_readdatavalid : OUT STD_LOGIC;
signal pipeline_bridge_0_m1_waitrequest : OUT STD_LOGIC
);
end component pipeline_bridge_0_m1_arbitrator;
component pipeline_bridge_0 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end component pipeline_bridge_0;
component pipeline_bridge_0_bridge_arbitrator is
end component pipeline_bridge_0_bridge_arbitrator;
component spi_master_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal spi_master_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal spi_master_0_avalon_slave_0_waitrequest : IN STD_LOGIC;
-- outputs:
signal d1_spi_master_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_spi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal spi_master_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal spi_master_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal spi_master_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal spi_master_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal spi_master_0_avalon_slave_0_waitrequest_from_sa : OUT STD_LOGIC;
signal spi_master_0_avalon_slave_0_write : OUT STD_LOGIC;
signal spi_master_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component spi_master_0_avalon_slave_0_arbitrator;
component spi_master_0 is
port (
-- inputs:
signal addr : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal byte_en : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal in_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal miso : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal wr_en : IN STD_LOGIC;
-- outputs:
signal cs_n : OUT STD_LOGIC;
signal irq : OUT STD_LOGIC;
signal mosi : OUT STD_LOGIC;
signal out_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal sclk : OUT STD_LOGIC;
signal wait_req : OUT STD_LOGIC
);
end component spi_master_0;
component twi_master_0_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal d1_twi_master_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_twi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0 : OUT STD_LOGIC;
signal twi_master_0_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_0_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_0_avalon_slave_0_reset : OUT STD_LOGIC;
signal twi_master_0_avalon_slave_0_write : OUT STD_LOGIC;
signal twi_master_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component twi_master_0_avalon_slave_0_arbitrator;
component twi_master_0_avalon_streaming_sink_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_streaming_source_valid : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_0_avalon_streaming_sink_ready : IN STD_LOGIC;
-- outputs:
signal twi_master_0_avalon_streaming_sink_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_0_avalon_streaming_sink_ready_from_sa : OUT STD_LOGIC;
signal twi_master_0_avalon_streaming_sink_valid : OUT STD_LOGIC
);
end component twi_master_0_avalon_streaming_sink_arbitrator;
component twi_master_0_avalon_streaming_source_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_0_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_0_avalon_streaming_source_valid : IN STD_LOGIC;
-- outputs:
signal twi_master_0_avalon_streaming_source_ready : OUT STD_LOGIC
);
end component twi_master_0_avalon_streaming_source_arbitrator;
component twi_master_0 is
port (
-- inputs:
signal addr : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal byte_en : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal in_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal in_octet : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal in_valid : IN STD_LOGIC;
signal out_ready : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal scl_in : IN STD_LOGIC;
signal sda_in : IN STD_LOGIC;
signal sink_irq : IN STD_LOGIC;
signal source_irq : IN STD_LOGIC;
signal wr_en : IN STD_LOGIC;
-- outputs:
signal in_ready : OUT STD_LOGIC;
signal irq : OUT STD_LOGIC;
signal out_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal out_octet : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal out_valid : OUT STD_LOGIC;
signal scl_act : OUT STD_LOGIC;
signal sda_act : OUT STD_LOGIC
);
end component twi_master_0;
component twi_master_1_avalon_slave_0_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_address_to_slave : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_read : IN STD_LOGIC;
signal int_ctrl_0_avalon_master_write : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_1_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal d1_twi_master_1_avalon_slave_0_end_xfer : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_twi_master_1_avalon_slave_0 : OUT STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0 : OUT STD_LOGIC;
signal twi_master_1_avalon_slave_0_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_1_avalon_slave_0_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_1_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_1_avalon_slave_0_reset : OUT STD_LOGIC;
signal twi_master_1_avalon_slave_0_write : OUT STD_LOGIC;
signal twi_master_1_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component twi_master_1_avalon_slave_0_arbitrator;
component twi_master_1_avalon_streaming_sink_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_streaming_source_valid : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_1_avalon_streaming_sink_ready : IN STD_LOGIC;
-- outputs:
signal twi_master_1_avalon_streaming_sink_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_1_avalon_streaming_sink_ready_from_sa : OUT STD_LOGIC;
signal twi_master_1_avalon_streaming_sink_valid : OUT STD_LOGIC
);
end component twi_master_1_avalon_streaming_sink_arbitrator;
component twi_master_1_avalon_streaming_source_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal twi_master_1_avalon_streaming_source_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_1_avalon_streaming_source_valid : IN STD_LOGIC;
-- outputs:
signal twi_master_1_avalon_streaming_source_ready : OUT STD_LOGIC
);
end component twi_master_1_avalon_streaming_source_arbitrator;
component twi_master_1 is
port (
-- inputs:
signal addr : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal byte_en : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal in_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal in_octet : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal in_valid : IN STD_LOGIC;
signal out_ready : IN STD_LOGIC;
signal rst : IN STD_LOGIC;
signal scl_in : IN STD_LOGIC;
signal sda_in : IN STD_LOGIC;
signal sink_irq : IN STD_LOGIC;
signal source_irq : IN STD_LOGIC;
signal wr_en : IN STD_LOGIC;
-- outputs:
signal in_ready : OUT STD_LOGIC;
signal irq : OUT STD_LOGIC;
signal out_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal out_octet : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal out_valid : OUT STD_LOGIC;
signal scl_act : OUT STD_LOGIC;
signal sda_act : OUT STD_LOGIC
);
end component twi_master_1;
component unici_core_burst_0_upstream_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_address_to_slave : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_burstcount : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_latency_counter : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_write : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_0_upstream_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_upstream_readdatavalid : IN STD_LOGIC;
signal unici_core_burst_0_upstream_waitrequest : IN STD_LOGIC;
-- outputs:
signal d1_unici_core_burst_0_upstream_end_xfer : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream : OUT STD_LOGIC;
signal unici_core_burst_0_upstream_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_upstream_burstcount : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_upstream_byteaddress : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_0_upstream_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_0_upstream_debugaccess : OUT STD_LOGIC;
signal unici_core_burst_0_upstream_read : OUT STD_LOGIC;
signal unici_core_burst_0_upstream_readdata_from_sa : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_upstream_waitrequest_from_sa : OUT STD_LOGIC;
signal unici_core_burst_0_upstream_write : OUT STD_LOGIC;
signal unici_core_burst_0_upstream_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
end component unici_core_burst_0_upstream_arbitrator;
component unici_core_burst_0_downstream_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal d1_pipeline_bridge_0_s1_end_xfer : IN STD_LOGIC;
signal pipeline_bridge_0_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_s1_waitrequest_from_sa : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_0_downstream_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_burstcount : IN STD_LOGIC;
signal unici_core_burst_0_downstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 : IN STD_LOGIC;
signal unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 : IN STD_LOGIC;
signal unici_core_burst_0_downstream_read : IN STD_LOGIC;
signal unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1 : IN STD_LOGIC;
signal unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1_shift_register : IN STD_LOGIC;
signal unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 : IN STD_LOGIC;
signal unici_core_burst_0_downstream_write : IN STD_LOGIC;
signal unici_core_burst_0_downstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal unici_core_burst_0_downstream_address_to_slave : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_latency_counter : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_downstream_readdatavalid : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_reset_n : OUT STD_LOGIC;
signal unici_core_burst_0_downstream_waitrequest : OUT STD_LOGIC
);
end component unici_core_burst_0_downstream_arbitrator;
component unici_core_burst_0 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal downstream_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal downstream_readdatavalid : IN STD_LOGIC;
signal downstream_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal upstream_address : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal upstream_burstcount : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal upstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal upstream_debugaccess : IN STD_LOGIC;
signal upstream_nativeaddress : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal upstream_read : IN STD_LOGIC;
signal upstream_write : IN STD_LOGIC;
signal upstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal downstream_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal downstream_arbitrationshare : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal downstream_burstcount : OUT STD_LOGIC;
signal downstream_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal downstream_debugaccess : OUT STD_LOGIC;
signal downstream_nativeaddress : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal downstream_read : OUT STD_LOGIC;
signal downstream_write : OUT STD_LOGIC;
signal downstream_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_readdatavalid : OUT STD_LOGIC;
signal upstream_waitrequest : OUT STD_LOGIC
);
end component unici_core_burst_0;
component unici_core_burst_1_upstream_arbitrator is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_address_to_slave : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_burstcount : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_latency_counter : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_write : IN STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_1_upstream_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_upstream_readdatavalid : IN STD_LOGIC;
signal unici_core_burst_1_upstream_waitrequest : IN STD_LOGIC;
-- outputs:
signal d1_unici_core_burst_1_upstream_end_xfer : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register : OUT STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream : OUT STD_LOGIC;
signal unici_core_burst_1_upstream_address : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_upstream_burstcount : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_upstream_byteaddress : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
signal unici_core_burst_1_upstream_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_1_upstream_debugaccess : OUT STD_LOGIC;
signal unici_core_burst_1_upstream_read : OUT STD_LOGIC;
signal unici_core_burst_1_upstream_readdata_from_sa : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_upstream_waitrequest_from_sa : OUT STD_LOGIC;
signal unici_core_burst_1_upstream_write : OUT STD_LOGIC;
signal unici_core_burst_1_upstream_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
end component unici_core_burst_1_upstream_arbitrator;
component unici_core_burst_1_downstream_arbitrator is
port (
-- inputs:
signal avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal unici_core_burst_1_downstream_address : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_downstream_burstcount : IN STD_LOGIC;
signal unici_core_burst_1_downstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 : IN STD_LOGIC;
signal unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 : IN STD_LOGIC;
signal unici_core_burst_1_downstream_read : IN STD_LOGIC;
signal unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0 : IN STD_LOGIC;
signal unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 : IN STD_LOGIC;
signal unici_core_burst_1_downstream_write : IN STD_LOGIC;
signal unici_core_burst_1_downstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal unici_core_burst_1_downstream_address_to_slave : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_downstream_latency_counter : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_downstream_readdatavalid : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_reset_n : OUT STD_LOGIC;
signal unici_core_burst_1_downstream_waitrequest : OUT STD_LOGIC
);
end component unici_core_burst_1_downstream_arbitrator;
component unici_core_burst_1 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal downstream_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal downstream_readdatavalid : IN STD_LOGIC;
signal downstream_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal upstream_address : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
signal upstream_burstcount : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal upstream_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal upstream_debugaccess : IN STD_LOGIC;
signal upstream_nativeaddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal upstream_read : IN STD_LOGIC;
signal upstream_write : IN STD_LOGIC;
signal upstream_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal downstream_address : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal downstream_arbitrationshare : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
signal downstream_burstcount : OUT STD_LOGIC;
signal downstream_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal downstream_debugaccess : OUT STD_LOGIC;
signal downstream_nativeaddress : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal downstream_read : OUT STD_LOGIC;
signal downstream_write : OUT STD_LOGIC;
signal downstream_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_readdatavalid : OUT STD_LOGIC;
signal upstream_waitrequest : OUT STD_LOGIC
);
end component unici_core_burst_1;
component unici_core_reset_pcie_compiler_0_pcie_core_clk_out_domain_synch_module is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component unici_core_reset_pcie_compiler_0_pcie_core_clk_out_domain_synch_module;
signal avalon64_to_avalon8_0_avalon_slave_0_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_read : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal avalon64_to_avalon8_0_avalon_slave_0_reset : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_waitrequest : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_write : STD_LOGIC;
signal avalon64_to_avalon8_0_avalon_slave_0_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_readdata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal ci_bridge_0_avalon_slave_0_reset : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_write : STD_LOGIC;
signal ci_bridge_0_avalon_slave_0_writedata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_ci_bridge_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_dvb_dma_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_dvb_dma_1_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_dvb_ts_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_dvb_ts_1_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_gpout_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_int_ctrl_0_avalon_cra_end_xfer : STD_LOGIC;
signal d1_int_ctrl_0_avalon_slave_end_xfer : STD_LOGIC;
signal d1_pcie_compiler_0_Control_Register_Access_end_xfer : STD_LOGIC;
signal d1_pcie_compiler_0_Tx_Interface_end_xfer : STD_LOGIC;
signal d1_pipeline_bridge_0_s1_end_xfer : STD_LOGIC;
signal d1_spi_master_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_twi_master_0_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_twi_master_1_avalon_slave_0_end_xfer : STD_LOGIC;
signal d1_unici_core_burst_0_upstream_end_xfer : STD_LOGIC;
signal d1_unici_core_burst_1_upstream_end_xfer : STD_LOGIC;
signal dma_arbiter_0_avalon_master_address : STD_LOGIC_VECTOR (30 DOWNTO 0);
signal dma_arbiter_0_avalon_master_address_to_slave : STD_LOGIC_VECTOR (30 DOWNTO 0);
signal dma_arbiter_0_avalon_master_burstcount : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma_arbiter_0_avalon_master_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma_arbiter_0_avalon_master_reset : STD_LOGIC;
signal dma_arbiter_0_avalon_master_waitrequest : STD_LOGIC;
signal dma_arbiter_0_avalon_master_write : STD_LOGIC;
signal dma_arbiter_0_avalon_master_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface : STD_LOGIC;
signal dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface : STD_LOGIC;
signal dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_address : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_dma_0_avalon_slave_0_reset : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_write : STD_LOGIC;
signal dvb_dma_0_avalon_slave_0_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_address : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_dma_1_avalon_slave_0_reset : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_write : STD_LOGIC;
signal dvb_dma_1_avalon_slave_0_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_address : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_read : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_0_avalon_slave_0_reset : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_waitrequest : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_write : STD_LOGIC;
signal dvb_ts_0_avalon_slave_0_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_address : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_read : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal dvb_ts_1_avalon_slave_0_reset : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_waitrequest : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_write : STD_LOGIC;
signal dvb_ts_1_avalon_slave_0_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_read : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_slave_0_reset : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_waitrequest : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_write : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_slave_0_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_streaming_sink_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_in_8b_sync_0_avalon_streaming_sink_ready : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa : STD_LOGIC;
signal fifo_in_8b_sync_0_avalon_streaming_sink_valid : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_read : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_slave_0_reset : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_waitrequest : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_write : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_slave_0_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_streaming_sink_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_in_8b_sync_1_avalon_streaming_sink_ready : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa : STD_LOGIC;
signal fifo_in_8b_sync_1_avalon_streaming_sink_valid : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_slave_0_reset : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_waitrequest : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_write : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_slave_0_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_streaming_source_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_out_8b_sync_0_avalon_streaming_source_ready : STD_LOGIC;
signal fifo_out_8b_sync_0_avalon_streaming_source_valid : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_slave_0_reset : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_waitrequest : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_write : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_slave_0_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_streaming_source_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal fifo_out_8b_sync_1_avalon_streaming_source_ready : STD_LOGIC;
signal fifo_out_8b_sync_1_avalon_streaming_source_valid : STD_LOGIC;
signal gpout_0_avalon_slave_0_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal gpout_0_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal gpout_0_avalon_slave_0_readdata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal gpout_0_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal gpout_0_avalon_slave_0_reset : STD_LOGIC;
signal gpout_0_avalon_slave_0_write : STD_LOGIC;
signal gpout_0_avalon_slave_0_writedata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_cra_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_cra_byteenable : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_cra_readdata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_cra_readdata_from_sa : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_cra_write : STD_LOGIC;
signal int_ctrl_0_avalon_cra_writedata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_address_to_slave : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal int_ctrl_0_avalon_master_dbs_write_16 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_ci_bridge_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_dma_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_dma_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_ts_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_dvb_ts_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_gpout_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_int_ctrl_0_avalon_cra : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_pcie_compiler_0_Control_Register_Access : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_spi_master_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_twi_master_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_read_data_valid_twi_master_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0 : STD_LOGIC;
signal int_ctrl_0_avalon_master_waitrequest : STD_LOGIC;
signal int_ctrl_0_avalon_master_write : STD_LOGIC;
signal int_ctrl_0_avalon_master_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_slave_address : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal int_ctrl_0_avalon_slave_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal int_ctrl_0_avalon_slave_irq : STD_LOGIC;
signal int_ctrl_0_avalon_slave_read : STD_LOGIC;
signal int_ctrl_0_avalon_slave_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_slave_readdata_from_sa : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal int_ctrl_0_avalon_slave_reset : STD_LOGIC;
signal int_ctrl_0_avalon_slave_waitrequest : STD_LOGIC;
signal int_ctrl_0_avalon_slave_waitrequest_from_sa : STD_LOGIC;
signal int_ctrl_0_avalon_slave_write : STD_LOGIC;
signal int_ctrl_0_avalon_slave_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_cam0_bypass_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cam0_fail_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cam0_ready_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cam1_bypass_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cam1_fail_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cam1_ready_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cam_interrupts_from_the_ci_bridge_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal internal_cam_mclki_from_the_dvb_ts_0 : STD_LOGIC;
signal internal_cam_mclki_from_the_dvb_ts_1 : STD_LOGIC;
signal internal_cam_mdi_from_the_dvb_ts_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_cam_mdi_from_the_dvb_ts_1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_cam_mistrt_from_the_dvb_ts_0 : STD_LOGIC;
signal internal_cam_mistrt_from_the_dvb_ts_1 : STD_LOGIC;
signal internal_cam_mival_from_the_dvb_ts_0 : STD_LOGIC;
signal internal_cam_mival_from_the_dvb_ts_1 : STD_LOGIC;
signal internal_cam_readdata_from_the_ci_bridge_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_cam_waitreq_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_ci_a_from_the_ci_bridge_0 : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal internal_ci_bus_dir_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_ci_d_en_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_ci_d_out_from_the_ci_bridge_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_ci_iord_n_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_ci_iowr_n_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_ci_oe_n_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_ci_reg_n_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_ci_we_n_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cia_ce_n_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cia_data_buf_oe_n_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cia_reset_buf_oe_n_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cia_reset_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cib_ce_n_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cib_data_buf_oe_n_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cib_reset_buf_oe_n_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_cib_reset_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_clk125_out_pcie_compiler_0 : STD_LOGIC;
signal internal_clk250_out_pcie_compiler_0 : STD_LOGIC;
signal internal_clk500_out_pcie_compiler_0 : STD_LOGIC;
signal internal_cs_n_from_the_spi_master_0 : STD_LOGIC;
signal internal_dma0_wait_from_the_dma_arbiter_0 : STD_LOGIC;
signal internal_dma1_wait_from_the_dma_arbiter_0 : STD_LOGIC;
signal internal_dvb_out_data_from_the_dvb_ts_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_dvb_out_data_from_the_dvb_ts_1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_dvb_out_dsop_from_the_dvb_ts_0 : STD_LOGIC;
signal internal_dvb_out_dsop_from_the_dvb_ts_1 : STD_LOGIC;
signal internal_dvb_out_dval_from_the_dvb_ts_0 : STD_LOGIC;
signal internal_dvb_out_dval_from_the_dvb_ts_1 : STD_LOGIC;
signal internal_interrupt_from_the_ci_bridge_0 : STD_LOGIC;
signal internal_interrupt_from_the_dvb_dma_0 : STD_LOGIC;
signal internal_interrupt_from_the_dvb_dma_1 : STD_LOGIC;
signal internal_interrupt_from_the_dvb_ts_0 : STD_LOGIC;
signal internal_interrupt_from_the_dvb_ts_1 : STD_LOGIC;
signal internal_irq_from_the_fifo_in_8b_sync_0 : STD_LOGIC;
signal internal_irq_from_the_fifo_in_8b_sync_1 : STD_LOGIC;
signal internal_irq_from_the_fifo_out_8b_sync_0 : STD_LOGIC;
signal internal_irq_from_the_fifo_out_8b_sync_1 : STD_LOGIC;
signal internal_irq_from_the_spi_master_0 : STD_LOGIC;
signal internal_irq_from_the_twi_master_0 : STD_LOGIC;
signal internal_irq_from_the_twi_master_1 : STD_LOGIC;
signal internal_mem_addr_from_the_dvb_dma_0 : STD_LOGIC_VECTOR (60 DOWNTO 0);
signal internal_mem_addr_from_the_dvb_dma_1 : STD_LOGIC_VECTOR (60 DOWNTO 0);
signal internal_mem_byteen_from_the_dvb_dma_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_mem_byteen_from_the_dvb_dma_1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_mem_size_from_the_dvb_dma_0 : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal internal_mem_size_from_the_dvb_dma_1 : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal internal_mem_wrdata_from_the_dvb_dma_0 : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal internal_mem_wrdata_from_the_dvb_dma_1 : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal internal_mem_write_from_the_dvb_dma_0 : STD_LOGIC;
signal internal_mem_write_from_the_dvb_dma_1 : STD_LOGIC;
signal internal_mosi_from_the_spi_master_0 : STD_LOGIC;
signal internal_out_address_from_the_avalon64_to_avalon8_0 : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal internal_out_read_from_the_avalon64_to_avalon8_0 : STD_LOGIC;
signal internal_out_write_from_the_avalon64_to_avalon8_0 : STD_LOGIC;
signal internal_out_writedata_from_the_avalon64_to_avalon8_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_pcie_compiler_0_pcie_core_clk_out : STD_LOGIC;
signal internal_pins_from_the_gpout_0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal internal_powerdown_ext_pcie_compiler_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal internal_rate_ext_pcie_compiler_0 : STD_LOGIC;
signal internal_reconfig_fromgxb_pcie_compiler_0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal internal_rxpolarity0_ext_pcie_compiler_0 : STD_LOGIC;
signal internal_scl_act_from_the_twi_master_0 : STD_LOGIC;
signal internal_scl_act_from_the_twi_master_1 : STD_LOGIC;
signal internal_sclk_from_the_spi_master_0 : STD_LOGIC;
signal internal_sda_act_from_the_twi_master_0 : STD_LOGIC;
signal internal_sda_act_from_the_twi_master_1 : STD_LOGIC;
signal internal_tx_out0_pcie_compiler_0 : STD_LOGIC;
signal internal_txcompl0_ext_pcie_compiler_0 : STD_LOGIC;
signal internal_txdata0_ext_pcie_compiler_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal internal_txdatak0_ext_pcie_compiler_0 : STD_LOGIC;
signal internal_txdetectrx_ext_pcie_compiler_0 : STD_LOGIC;
signal internal_txelecidle0_ext_pcie_compiler_0 : STD_LOGIC;
signal module_input15 : STD_LOGIC;
signal out_clk_pcie_compiler_0_pcie_core_clk : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_address : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_byteenable : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_chipselect : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_irq : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_read : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_readdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_readdata_from_sa : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_waitrequest : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_waitrequest_from_sa : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_write : STD_LOGIC;
signal pcie_compiler_0_Control_Register_Access_writedata : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_address : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_address_to_slave : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_irq : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_irqnumber : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_latency_counter : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Rx_Interface_readdatavalid : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_reset_n : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_resetrequest : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_waitrequest : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_write : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_address : STD_LOGIC_VECTOR (27 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_chipselect : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_read : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_readdata_from_sa : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_readdatavalid : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_readdatavalid_from_sa : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_waitrequest : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_waitrequest_from_sa : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_write : STD_LOGIC;
signal pcie_compiler_0_Tx_Interface_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_pcie_core_clk_out_reset_n : STD_LOGIC;
signal pipeline_bridge_0_m1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal pipeline_bridge_0_m1_address_to_slave : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal pipeline_bridge_0_m1_burstcount : STD_LOGIC;
signal pipeline_bridge_0_m1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal pipeline_bridge_0_m1_chipselect : STD_LOGIC;
signal pipeline_bridge_0_m1_dbs_address : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal pipeline_bridge_0_m1_dbs_write_32 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal pipeline_bridge_0_m1_debugaccess : STD_LOGIC;
signal pipeline_bridge_0_m1_endofpacket : STD_LOGIC;
signal pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave : STD_LOGIC;
signal pipeline_bridge_0_m1_latency_counter : STD_LOGIC;
signal pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave : STD_LOGIC;
signal pipeline_bridge_0_m1_read : STD_LOGIC;
signal pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave : STD_LOGIC;
signal pipeline_bridge_0_m1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_m1_readdatavalid : STD_LOGIC;
signal pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave : STD_LOGIC;
signal pipeline_bridge_0_m1_waitrequest : STD_LOGIC;
signal pipeline_bridge_0_m1_write : STD_LOGIC;
signal pipeline_bridge_0_m1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_s1_address : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal pipeline_bridge_0_s1_arbiterlock : STD_LOGIC;
signal pipeline_bridge_0_s1_arbiterlock2 : STD_LOGIC;
signal pipeline_bridge_0_s1_burstcount : STD_LOGIC;
signal pipeline_bridge_0_s1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pipeline_bridge_0_s1_chipselect : STD_LOGIC;
signal pipeline_bridge_0_s1_debugaccess : STD_LOGIC;
signal pipeline_bridge_0_s1_endofpacket : STD_LOGIC;
signal pipeline_bridge_0_s1_endofpacket_from_sa : STD_LOGIC;
signal pipeline_bridge_0_s1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal pipeline_bridge_0_s1_read : STD_LOGIC;
signal pipeline_bridge_0_s1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_s1_readdata_from_sa : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pipeline_bridge_0_s1_readdatavalid : STD_LOGIC;
signal pipeline_bridge_0_s1_reset_n : STD_LOGIC;
signal pipeline_bridge_0_s1_waitrequest : STD_LOGIC;
signal pipeline_bridge_0_s1_waitrequest_from_sa : STD_LOGIC;
signal pipeline_bridge_0_s1_write : STD_LOGIC;
signal pipeline_bridge_0_s1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal reset_n_sources : STD_LOGIC;
signal spi_master_0_avalon_slave_0_address : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal spi_master_0_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal spi_master_0_avalon_slave_0_readdata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal spi_master_0_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal spi_master_0_avalon_slave_0_reset : STD_LOGIC;
signal spi_master_0_avalon_slave_0_waitrequest : STD_LOGIC;
signal spi_master_0_avalon_slave_0_waitrequest_from_sa : STD_LOGIC;
signal spi_master_0_avalon_slave_0_write : STD_LOGIC;
signal spi_master_0_avalon_slave_0_writedata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_0_avalon_slave_0_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_0_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_0_avalon_slave_0_readdata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_0_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_0_avalon_slave_0_reset : STD_LOGIC;
signal twi_master_0_avalon_slave_0_write : STD_LOGIC;
signal twi_master_0_avalon_slave_0_writedata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_0_avalon_streaming_sink_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_0_avalon_streaming_sink_ready : STD_LOGIC;
signal twi_master_0_avalon_streaming_sink_ready_from_sa : STD_LOGIC;
signal twi_master_0_avalon_streaming_sink_valid : STD_LOGIC;
signal twi_master_0_avalon_streaming_source_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_0_avalon_streaming_source_ready : STD_LOGIC;
signal twi_master_0_avalon_streaming_source_valid : STD_LOGIC;
signal twi_master_1_avalon_slave_0_address : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_1_avalon_slave_0_byteenable : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal twi_master_1_avalon_slave_0_readdata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_1_avalon_slave_0_readdata_from_sa : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_1_avalon_slave_0_reset : STD_LOGIC;
signal twi_master_1_avalon_slave_0_write : STD_LOGIC;
signal twi_master_1_avalon_slave_0_writedata : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal twi_master_1_avalon_streaming_sink_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_1_avalon_streaming_sink_ready : STD_LOGIC;
signal twi_master_1_avalon_streaming_sink_ready_from_sa : STD_LOGIC;
signal twi_master_1_avalon_streaming_sink_valid : STD_LOGIC;
signal twi_master_1_avalon_streaming_source_data : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal twi_master_1_avalon_streaming_source_ready : STD_LOGIC;
signal twi_master_1_avalon_streaming_source_valid : STD_LOGIC;
signal unici_core_burst_0_downstream_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_address_to_slave : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_arbitrationshare : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_downstream_burstcount : STD_LOGIC;
signal unici_core_burst_0_downstream_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_0_downstream_debugaccess : STD_LOGIC;
signal unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 : STD_LOGIC;
signal unici_core_burst_0_downstream_latency_counter : STD_LOGIC;
signal unici_core_burst_0_downstream_nativeaddress : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 : STD_LOGIC;
signal unici_core_burst_0_downstream_read : STD_LOGIC;
signal unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1 : STD_LOGIC;
signal unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1_shift_register : STD_LOGIC;
signal unici_core_burst_0_downstream_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_downstream_readdatavalid : STD_LOGIC;
signal unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 : STD_LOGIC;
signal unici_core_burst_0_downstream_reset_n : STD_LOGIC;
signal unici_core_burst_0_downstream_waitrequest : STD_LOGIC;
signal unici_core_burst_0_downstream_write : STD_LOGIC;
signal unici_core_burst_0_downstream_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_upstream_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal unici_core_burst_0_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_0_upstream_byteaddress : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_0_upstream_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_0_upstream_debugaccess : STD_LOGIC;
signal unici_core_burst_0_upstream_read : STD_LOGIC;
signal unici_core_burst_0_upstream_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_upstream_readdata_from_sa : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_0_upstream_readdatavalid : STD_LOGIC;
signal unici_core_burst_0_upstream_waitrequest : STD_LOGIC;
signal unici_core_burst_0_upstream_waitrequest_from_sa : STD_LOGIC;
signal unici_core_burst_0_upstream_write : STD_LOGIC;
signal unici_core_burst_0_upstream_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_downstream_address : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_downstream_address_to_slave : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_downstream_arbitrationshare : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_downstream_burstcount : STD_LOGIC;
signal unici_core_burst_1_downstream_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_1_downstream_debugaccess : STD_LOGIC;
signal unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 : STD_LOGIC;
signal unici_core_burst_1_downstream_latency_counter : STD_LOGIC;
signal unici_core_burst_1_downstream_nativeaddress : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 : STD_LOGIC;
signal unici_core_burst_1_downstream_read : STD_LOGIC;
signal unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0 : STD_LOGIC;
signal unici_core_burst_1_downstream_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_downstream_readdatavalid : STD_LOGIC;
signal unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 : STD_LOGIC;
signal unici_core_burst_1_downstream_reset_n : STD_LOGIC;
signal unici_core_burst_1_downstream_waitrequest : STD_LOGIC;
signal unici_core_burst_1_downstream_write : STD_LOGIC;
signal unici_core_burst_1_downstream_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_upstream_address : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal unici_core_burst_1_upstream_burstcount : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unici_core_burst_1_upstream_byteaddress : STD_LOGIC_VECTOR (20 DOWNTO 0);
signal unici_core_burst_1_upstream_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal unici_core_burst_1_upstream_debugaccess : STD_LOGIC;
signal unici_core_burst_1_upstream_read : STD_LOGIC;
signal unici_core_burst_1_upstream_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_upstream_readdata_from_sa : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal unici_core_burst_1_upstream_readdatavalid : STD_LOGIC;
signal unici_core_burst_1_upstream_waitrequest : STD_LOGIC;
signal unici_core_burst_1_upstream_waitrequest_from_sa : STD_LOGIC;
signal unici_core_burst_1_upstream_write : STD_LOGIC;
signal unici_core_burst_1_upstream_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
begin
--the_avalon64_to_avalon8_0_avalon_slave_0, which is an e_instance
the_avalon64_to_avalon8_0_avalon_slave_0 : avalon64_to_avalon8_0_avalon_slave_0_arbitrator
port map(
avalon64_to_avalon8_0_avalon_slave_0_address => avalon64_to_avalon8_0_avalon_slave_0_address,
avalon64_to_avalon8_0_avalon_slave_0_byteenable => avalon64_to_avalon8_0_avalon_slave_0_byteenable,
avalon64_to_avalon8_0_avalon_slave_0_read => avalon64_to_avalon8_0_avalon_slave_0_read,
avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa => avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa,
avalon64_to_avalon8_0_avalon_slave_0_reset => avalon64_to_avalon8_0_avalon_slave_0_reset,
avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa => avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa,
avalon64_to_avalon8_0_avalon_slave_0_write => avalon64_to_avalon8_0_avalon_slave_0_write,
avalon64_to_avalon8_0_avalon_slave_0_writedata => avalon64_to_avalon8_0_avalon_slave_0_writedata,
d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer => d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer,
unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 => unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0,
unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 => unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0,
unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0 => unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0,
unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 => unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0,
avalon64_to_avalon8_0_avalon_slave_0_readdata => avalon64_to_avalon8_0_avalon_slave_0_readdata,
avalon64_to_avalon8_0_avalon_slave_0_waitrequest => avalon64_to_avalon8_0_avalon_slave_0_waitrequest,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
unici_core_burst_1_downstream_address_to_slave => unici_core_burst_1_downstream_address_to_slave,
unici_core_burst_1_downstream_arbitrationshare => unici_core_burst_1_downstream_arbitrationshare,
unici_core_burst_1_downstream_burstcount => unici_core_burst_1_downstream_burstcount,
unici_core_burst_1_downstream_byteenable => unici_core_burst_1_downstream_byteenable,
unici_core_burst_1_downstream_latency_counter => unici_core_burst_1_downstream_latency_counter,
unici_core_burst_1_downstream_read => unici_core_burst_1_downstream_read,
unici_core_burst_1_downstream_write => unici_core_burst_1_downstream_write,
unici_core_burst_1_downstream_writedata => unici_core_burst_1_downstream_writedata
);
--the_avalon64_to_avalon8_0, which is an e_ptf_instance
the_avalon64_to_avalon8_0 : avalon64_to_avalon8_0
port map(
out_address => internal_out_address_from_the_avalon64_to_avalon8_0,
out_read => internal_out_read_from_the_avalon64_to_avalon8_0,
out_write => internal_out_write_from_the_avalon64_to_avalon8_0,
out_writedata => internal_out_writedata_from_the_avalon64_to_avalon8_0,
readdata => avalon64_to_avalon8_0_avalon_slave_0_readdata,
waitrequest => avalon64_to_avalon8_0_avalon_slave_0_waitrequest,
address => avalon64_to_avalon8_0_avalon_slave_0_address,
byteenable => avalon64_to_avalon8_0_avalon_slave_0_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
out_readdata => out_readdata_to_the_avalon64_to_avalon8_0,
out_waitrequest => out_waitrequest_to_the_avalon64_to_avalon8_0,
read => avalon64_to_avalon8_0_avalon_slave_0_read,
rst => avalon64_to_avalon8_0_avalon_slave_0_reset,
write => avalon64_to_avalon8_0_avalon_slave_0_write,
writedata => avalon64_to_avalon8_0_avalon_slave_0_writedata
);
--the_ci_bridge_0_avalon_slave_0, which is an e_instance
the_ci_bridge_0_avalon_slave_0 : ci_bridge_0_avalon_slave_0_arbitrator
port map(
ci_bridge_0_avalon_slave_0_address => ci_bridge_0_avalon_slave_0_address,
ci_bridge_0_avalon_slave_0_byteenable => ci_bridge_0_avalon_slave_0_byteenable,
ci_bridge_0_avalon_slave_0_readdata_from_sa => ci_bridge_0_avalon_slave_0_readdata_from_sa,
ci_bridge_0_avalon_slave_0_reset => ci_bridge_0_avalon_slave_0_reset,
ci_bridge_0_avalon_slave_0_write => ci_bridge_0_avalon_slave_0_write,
ci_bridge_0_avalon_slave_0_writedata => ci_bridge_0_avalon_slave_0_writedata,
d1_ci_bridge_0_avalon_slave_0_end_xfer => d1_ci_bridge_0_avalon_slave_0_end_xfer,
int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0 => int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_ci_bridge_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_ci_bridge_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0,
ci_bridge_0_avalon_slave_0_readdata => ci_bridge_0_avalon_slave_0_readdata,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_dbs_address => int_ctrl_0_avalon_master_dbs_address,
int_ctrl_0_avalon_master_dbs_write_16 => int_ctrl_0_avalon_master_dbs_write_16,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_ci_bridge_0, which is an e_ptf_instance
the_ci_bridge_0 : ci_bridge_0
port map(
cam0_bypass => internal_cam0_bypass_from_the_ci_bridge_0,
cam0_fail => internal_cam0_fail_from_the_ci_bridge_0,
cam0_ready => internal_cam0_ready_from_the_ci_bridge_0,
cam1_bypass => internal_cam1_bypass_from_the_ci_bridge_0,
cam1_fail => internal_cam1_fail_from_the_ci_bridge_0,
cam1_ready => internal_cam1_ready_from_the_ci_bridge_0,
cam_interrupts => internal_cam_interrupts_from_the_ci_bridge_0,
cam_readdata => internal_cam_readdata_from_the_ci_bridge_0,
cam_waitreq => internal_cam_waitreq_from_the_ci_bridge_0,
ci_a => internal_ci_a_from_the_ci_bridge_0,
ci_bus_dir => internal_ci_bus_dir_from_the_ci_bridge_0,
ci_d_en => internal_ci_d_en_from_the_ci_bridge_0,
ci_d_out => internal_ci_d_out_from_the_ci_bridge_0,
ci_iord_n => internal_ci_iord_n_from_the_ci_bridge_0,
ci_iowr_n => internal_ci_iowr_n_from_the_ci_bridge_0,
ci_oe_n => internal_ci_oe_n_from_the_ci_bridge_0,
ci_reg_n => internal_ci_reg_n_from_the_ci_bridge_0,
ci_we_n => internal_ci_we_n_from_the_ci_bridge_0,
cia_ce_n => internal_cia_ce_n_from_the_ci_bridge_0,
cia_data_buf_oe_n => internal_cia_data_buf_oe_n_from_the_ci_bridge_0,
cia_reset => internal_cia_reset_from_the_ci_bridge_0,
cia_reset_buf_oe_n => internal_cia_reset_buf_oe_n_from_the_ci_bridge_0,
cib_ce_n => internal_cib_ce_n_from_the_ci_bridge_0,
cib_data_buf_oe_n => internal_cib_data_buf_oe_n_from_the_ci_bridge_0,
cib_reset => internal_cib_reset_from_the_ci_bridge_0,
cib_reset_buf_oe_n => internal_cib_reset_buf_oe_n_from_the_ci_bridge_0,
interrupt => internal_interrupt_from_the_ci_bridge_0,
readdata => ci_bridge_0_avalon_slave_0_readdata,
address => ci_bridge_0_avalon_slave_0_address,
byteenable => ci_bridge_0_avalon_slave_0_byteenable,
cam_address => cam_address_to_the_ci_bridge_0,
cam_read => cam_read_to_the_ci_bridge_0,
cam_write => cam_write_to_the_ci_bridge_0,
cam_writedata => cam_writedata_to_the_ci_bridge_0,
ci_d_in => ci_d_in_to_the_ci_bridge_0,
cia_cd_n => cia_cd_n_to_the_ci_bridge_0,
cia_ireq_n => cia_ireq_n_to_the_ci_bridge_0,
cia_overcurrent_n => cia_overcurrent_n_to_the_ci_bridge_0,
cia_wait_n => cia_wait_n_to_the_ci_bridge_0,
cib_cd_n => cib_cd_n_to_the_ci_bridge_0,
cib_ireq_n => cib_ireq_n_to_the_ci_bridge_0,
cib_overcurrent_n => cib_overcurrent_n_to_the_ci_bridge_0,
cib_wait_n => cib_wait_n_to_the_ci_bridge_0,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
rst => ci_bridge_0_avalon_slave_0_reset,
write => ci_bridge_0_avalon_slave_0_write,
writedata => ci_bridge_0_avalon_slave_0_writedata
);
--the_dma_arbiter_0_avalon_master, which is an e_instance
the_dma_arbiter_0_avalon_master : dma_arbiter_0_avalon_master_arbitrator
port map(
dma_arbiter_0_avalon_master_address_to_slave => dma_arbiter_0_avalon_master_address_to_slave,
dma_arbiter_0_avalon_master_reset => dma_arbiter_0_avalon_master_reset,
dma_arbiter_0_avalon_master_waitrequest => dma_arbiter_0_avalon_master_waitrequest,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
d1_pcie_compiler_0_Tx_Interface_end_xfer => d1_pcie_compiler_0_Tx_Interface_end_xfer,
dma_arbiter_0_avalon_master_address => dma_arbiter_0_avalon_master_address,
dma_arbiter_0_avalon_master_burstcount => dma_arbiter_0_avalon_master_burstcount,
dma_arbiter_0_avalon_master_byteenable => dma_arbiter_0_avalon_master_byteenable,
dma_arbiter_0_avalon_master_write => dma_arbiter_0_avalon_master_write,
dma_arbiter_0_avalon_master_writedata => dma_arbiter_0_avalon_master_writedata,
dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface => dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface,
dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface => dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface,
dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface => dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface,
pcie_compiler_0_Tx_Interface_waitrequest_from_sa => pcie_compiler_0_Tx_Interface_waitrequest_from_sa,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_dma_arbiter_0, which is an e_ptf_instance
the_dma_arbiter_0 : dma_arbiter_0
port map(
dma0_wait => internal_dma0_wait_from_the_dma_arbiter_0,
dma1_wait => internal_dma1_wait_from_the_dma_arbiter_0,
mem_addr => dma_arbiter_0_avalon_master_address,
mem_byteen => dma_arbiter_0_avalon_master_byteenable,
mem_size => dma_arbiter_0_avalon_master_burstcount,
mem_wrdata => dma_arbiter_0_avalon_master_writedata,
mem_write => dma_arbiter_0_avalon_master_write,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
dma0_addr => dma0_addr_to_the_dma_arbiter_0,
dma0_byteen => dma0_byteen_to_the_dma_arbiter_0,
dma0_size => dma0_size_to_the_dma_arbiter_0,
dma0_wrdata => dma0_wrdata_to_the_dma_arbiter_0,
dma0_write => dma0_write_to_the_dma_arbiter_0,
dma1_addr => dma1_addr_to_the_dma_arbiter_0,
dma1_byteen => dma1_byteen_to_the_dma_arbiter_0,
dma1_size => dma1_size_to_the_dma_arbiter_0,
dma1_wrdata => dma1_wrdata_to_the_dma_arbiter_0,
dma1_write => dma1_write_to_the_dma_arbiter_0,
mem_waitreq => dma_arbiter_0_avalon_master_waitrequest,
rst => dma_arbiter_0_avalon_master_reset
);
--the_dvb_dma_0_avalon_slave_0, which is an e_instance
the_dvb_dma_0_avalon_slave_0 : dvb_dma_0_avalon_slave_0_arbitrator
port map(
d1_dvb_dma_0_avalon_slave_0_end_xfer => d1_dvb_dma_0_avalon_slave_0_end_xfer,
dvb_dma_0_avalon_slave_0_address => dvb_dma_0_avalon_slave_0_address,
dvb_dma_0_avalon_slave_0_byteenable => dvb_dma_0_avalon_slave_0_byteenable,
dvb_dma_0_avalon_slave_0_readdata_from_sa => dvb_dma_0_avalon_slave_0_readdata_from_sa,
dvb_dma_0_avalon_slave_0_reset => dvb_dma_0_avalon_slave_0_reset,
dvb_dma_0_avalon_slave_0_write => dvb_dma_0_avalon_slave_0_write,
dvb_dma_0_avalon_slave_0_writedata => dvb_dma_0_avalon_slave_0_writedata,
int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_dvb_dma_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_dvb_dma_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
dvb_dma_0_avalon_slave_0_readdata => dvb_dma_0_avalon_slave_0_readdata,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
int_ctrl_0_avalon_master_writedata => int_ctrl_0_avalon_master_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_dvb_dma_0, which is an e_ptf_instance
the_dvb_dma_0 : dvb_dma_0
port map(
interrupt => internal_interrupt_from_the_dvb_dma_0,
mem_addr => internal_mem_addr_from_the_dvb_dma_0,
mem_byteen => internal_mem_byteen_from_the_dvb_dma_0,
mem_size => internal_mem_size_from_the_dvb_dma_0,
mem_wrdata => internal_mem_wrdata_from_the_dvb_dma_0,
mem_write => internal_mem_write_from_the_dvb_dma_0,
readdata => dvb_dma_0_avalon_slave_0_readdata,
address => dvb_dma_0_avalon_slave_0_address,
byteenable => dvb_dma_0_avalon_slave_0_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
dvb_data => dvb_data_to_the_dvb_dma_0,
dvb_dval => dvb_dval_to_the_dvb_dma_0,
dvb_sop => dvb_sop_to_the_dvb_dma_0,
mem_waitreq => mem_waitreq_to_the_dvb_dma_0,
rst => dvb_dma_0_avalon_slave_0_reset,
write => dvb_dma_0_avalon_slave_0_write,
writedata => dvb_dma_0_avalon_slave_0_writedata
);
--the_dvb_dma_1_avalon_slave_0, which is an e_instance
the_dvb_dma_1_avalon_slave_0 : dvb_dma_1_avalon_slave_0_arbitrator
port map(
d1_dvb_dma_1_avalon_slave_0_end_xfer => d1_dvb_dma_1_avalon_slave_0_end_xfer,
dvb_dma_1_avalon_slave_0_address => dvb_dma_1_avalon_slave_0_address,
dvb_dma_1_avalon_slave_0_byteenable => dvb_dma_1_avalon_slave_0_byteenable,
dvb_dma_1_avalon_slave_0_readdata_from_sa => dvb_dma_1_avalon_slave_0_readdata_from_sa,
dvb_dma_1_avalon_slave_0_reset => dvb_dma_1_avalon_slave_0_reset,
dvb_dma_1_avalon_slave_0_write => dvb_dma_1_avalon_slave_0_write,
dvb_dma_1_avalon_slave_0_writedata => dvb_dma_1_avalon_slave_0_writedata,
int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 => int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_dvb_dma_1_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_dvb_dma_1_avalon_slave_0,
int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0 => int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
dvb_dma_1_avalon_slave_0_readdata => dvb_dma_1_avalon_slave_0_readdata,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
int_ctrl_0_avalon_master_writedata => int_ctrl_0_avalon_master_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_dvb_dma_1, which is an e_ptf_instance
the_dvb_dma_1 : dvb_dma_1
port map(
interrupt => internal_interrupt_from_the_dvb_dma_1,
mem_addr => internal_mem_addr_from_the_dvb_dma_1,
mem_byteen => internal_mem_byteen_from_the_dvb_dma_1,
mem_size => internal_mem_size_from_the_dvb_dma_1,
mem_wrdata => internal_mem_wrdata_from_the_dvb_dma_1,
mem_write => internal_mem_write_from_the_dvb_dma_1,
readdata => dvb_dma_1_avalon_slave_0_readdata,
address => dvb_dma_1_avalon_slave_0_address,
byteenable => dvb_dma_1_avalon_slave_0_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
dvb_data => dvb_data_to_the_dvb_dma_1,
dvb_dval => dvb_dval_to_the_dvb_dma_1,
dvb_sop => dvb_sop_to_the_dvb_dma_1,
mem_waitreq => mem_waitreq_to_the_dvb_dma_1,
rst => dvb_dma_1_avalon_slave_0_reset,
write => dvb_dma_1_avalon_slave_0_write,
writedata => dvb_dma_1_avalon_slave_0_writedata
);
--the_dvb_ts_0_avalon_slave_0, which is an e_instance
the_dvb_ts_0_avalon_slave_0 : dvb_ts_0_avalon_slave_0_arbitrator
port map(
d1_dvb_ts_0_avalon_slave_0_end_xfer => d1_dvb_ts_0_avalon_slave_0_end_xfer,
dvb_ts_0_avalon_slave_0_address => dvb_ts_0_avalon_slave_0_address,
dvb_ts_0_avalon_slave_0_byteenable => dvb_ts_0_avalon_slave_0_byteenable,
dvb_ts_0_avalon_slave_0_read => dvb_ts_0_avalon_slave_0_read,
dvb_ts_0_avalon_slave_0_readdata_from_sa => dvb_ts_0_avalon_slave_0_readdata_from_sa,
dvb_ts_0_avalon_slave_0_reset => dvb_ts_0_avalon_slave_0_reset,
dvb_ts_0_avalon_slave_0_waitrequest_from_sa => dvb_ts_0_avalon_slave_0_waitrequest_from_sa,
dvb_ts_0_avalon_slave_0_write => dvb_ts_0_avalon_slave_0_write,
dvb_ts_0_avalon_slave_0_writedata => dvb_ts_0_avalon_slave_0_writedata,
int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_dvb_ts_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_dvb_ts_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
dvb_ts_0_avalon_slave_0_readdata => dvb_ts_0_avalon_slave_0_readdata,
dvb_ts_0_avalon_slave_0_waitrequest => dvb_ts_0_avalon_slave_0_waitrequest,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
int_ctrl_0_avalon_master_writedata => int_ctrl_0_avalon_master_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_dvb_ts_0, which is an e_ptf_instance
the_dvb_ts_0 : dvb_ts_0
port map(
cam_mclki => internal_cam_mclki_from_the_dvb_ts_0,
cam_mdi => internal_cam_mdi_from_the_dvb_ts_0,
cam_mistrt => internal_cam_mistrt_from_the_dvb_ts_0,
cam_mival => internal_cam_mival_from_the_dvb_ts_0,
dvb_out_data => internal_dvb_out_data_from_the_dvb_ts_0,
dvb_out_dsop => internal_dvb_out_dsop_from_the_dvb_ts_0,
dvb_out_dval => internal_dvb_out_dval_from_the_dvb_ts_0,
interrupt => internal_interrupt_from_the_dvb_ts_0,
readdata => dvb_ts_0_avalon_slave_0_readdata,
waitrequest => dvb_ts_0_avalon_slave_0_waitrequest,
address => dvb_ts_0_avalon_slave_0_address,
byteenable => dvb_ts_0_avalon_slave_0_byteenable,
cam_baseclk => cam_baseclk_to_the_dvb_ts_0,
cam_bypass => cam_bypass_to_the_dvb_ts_0,
cam_mclko => cam_mclko_to_the_dvb_ts_0,
cam_mdo => cam_mdo_to_the_dvb_ts_0,
cam_mostrt => cam_mostrt_to_the_dvb_ts_0,
cam_moval => cam_moval_to_the_dvb_ts_0,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
dvb_in0_data => dvb_in0_data_to_the_dvb_ts_0,
dvb_in0_dsop => dvb_in0_dsop_to_the_dvb_ts_0,
dvb_in0_dval => dvb_in0_dval_to_the_dvb_ts_0,
dvb_in1_data => dvb_in1_data_to_the_dvb_ts_0,
dvb_in1_dsop => dvb_in1_dsop_to_the_dvb_ts_0,
dvb_in1_dval => dvb_in1_dval_to_the_dvb_ts_0,
dvb_in2_data => dvb_in2_data_to_the_dvb_ts_0,
dvb_in2_dsop => dvb_in2_dsop_to_the_dvb_ts_0,
dvb_in2_dval => dvb_in2_dval_to_the_dvb_ts_0,
read => dvb_ts_0_avalon_slave_0_read,
rst => dvb_ts_0_avalon_slave_0_reset,
write => dvb_ts_0_avalon_slave_0_write,
writedata => dvb_ts_0_avalon_slave_0_writedata
);
--the_dvb_ts_1_avalon_slave_0, which is an e_instance
the_dvb_ts_1_avalon_slave_0 : dvb_ts_1_avalon_slave_0_arbitrator
port map(
d1_dvb_ts_1_avalon_slave_0_end_xfer => d1_dvb_ts_1_avalon_slave_0_end_xfer,
dvb_ts_1_avalon_slave_0_address => dvb_ts_1_avalon_slave_0_address,
dvb_ts_1_avalon_slave_0_byteenable => dvb_ts_1_avalon_slave_0_byteenable,
dvb_ts_1_avalon_slave_0_read => dvb_ts_1_avalon_slave_0_read,
dvb_ts_1_avalon_slave_0_readdata_from_sa => dvb_ts_1_avalon_slave_0_readdata_from_sa,
dvb_ts_1_avalon_slave_0_reset => dvb_ts_1_avalon_slave_0_reset,
dvb_ts_1_avalon_slave_0_waitrequest_from_sa => dvb_ts_1_avalon_slave_0_waitrequest_from_sa,
dvb_ts_1_avalon_slave_0_write => dvb_ts_1_avalon_slave_0_write,
dvb_ts_1_avalon_slave_0_writedata => dvb_ts_1_avalon_slave_0_writedata,
int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 => int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_dvb_ts_1_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_dvb_ts_1_avalon_slave_0,
int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0 => int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
dvb_ts_1_avalon_slave_0_readdata => dvb_ts_1_avalon_slave_0_readdata,
dvb_ts_1_avalon_slave_0_waitrequest => dvb_ts_1_avalon_slave_0_waitrequest,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
int_ctrl_0_avalon_master_writedata => int_ctrl_0_avalon_master_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_dvb_ts_1, which is an e_ptf_instance
the_dvb_ts_1 : dvb_ts_1
port map(
cam_mclki => internal_cam_mclki_from_the_dvb_ts_1,
cam_mdi => internal_cam_mdi_from_the_dvb_ts_1,
cam_mistrt => internal_cam_mistrt_from_the_dvb_ts_1,
cam_mival => internal_cam_mival_from_the_dvb_ts_1,
dvb_out_data => internal_dvb_out_data_from_the_dvb_ts_1,
dvb_out_dsop => internal_dvb_out_dsop_from_the_dvb_ts_1,
dvb_out_dval => internal_dvb_out_dval_from_the_dvb_ts_1,
interrupt => internal_interrupt_from_the_dvb_ts_1,
readdata => dvb_ts_1_avalon_slave_0_readdata,
waitrequest => dvb_ts_1_avalon_slave_0_waitrequest,
address => dvb_ts_1_avalon_slave_0_address,
byteenable => dvb_ts_1_avalon_slave_0_byteenable,
cam_baseclk => cam_baseclk_to_the_dvb_ts_1,
cam_bypass => cam_bypass_to_the_dvb_ts_1,
cam_mclko => cam_mclko_to_the_dvb_ts_1,
cam_mdo => cam_mdo_to_the_dvb_ts_1,
cam_mostrt => cam_mostrt_to_the_dvb_ts_1,
cam_moval => cam_moval_to_the_dvb_ts_1,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
dvb_in0_data => dvb_in0_data_to_the_dvb_ts_1,
dvb_in0_dsop => dvb_in0_dsop_to_the_dvb_ts_1,
dvb_in0_dval => dvb_in0_dval_to_the_dvb_ts_1,
dvb_in1_data => dvb_in1_data_to_the_dvb_ts_1,
dvb_in1_dsop => dvb_in1_dsop_to_the_dvb_ts_1,
dvb_in1_dval => dvb_in1_dval_to_the_dvb_ts_1,
dvb_in2_data => dvb_in2_data_to_the_dvb_ts_1,
dvb_in2_dsop => dvb_in2_dsop_to_the_dvb_ts_1,
dvb_in2_dval => dvb_in2_dval_to_the_dvb_ts_1,
read => dvb_ts_1_avalon_slave_0_read,
rst => dvb_ts_1_avalon_slave_0_reset,
write => dvb_ts_1_avalon_slave_0_write,
writedata => dvb_ts_1_avalon_slave_0_writedata
);
--the_fifo_in_8b_sync_0_avalon_slave_0, which is an e_instance
the_fifo_in_8b_sync_0_avalon_slave_0 : fifo_in_8b_sync_0_avalon_slave_0_arbitrator
port map(
d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer => d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer,
fifo_in_8b_sync_0_avalon_slave_0_address => fifo_in_8b_sync_0_avalon_slave_0_address,
fifo_in_8b_sync_0_avalon_slave_0_byteenable => fifo_in_8b_sync_0_avalon_slave_0_byteenable,
fifo_in_8b_sync_0_avalon_slave_0_read => fifo_in_8b_sync_0_avalon_slave_0_read,
fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa => fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa,
fifo_in_8b_sync_0_avalon_slave_0_reset => fifo_in_8b_sync_0_avalon_slave_0_reset,
fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa => fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa,
fifo_in_8b_sync_0_avalon_slave_0_write => fifo_in_8b_sync_0_avalon_slave_0_write,
fifo_in_8b_sync_0_avalon_slave_0_writedata => fifo_in_8b_sync_0_avalon_slave_0_writedata,
int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_in_8b_sync_0_avalon_slave_0_readdata => fifo_in_8b_sync_0_avalon_slave_0_readdata,
fifo_in_8b_sync_0_avalon_slave_0_waitrequest => fifo_in_8b_sync_0_avalon_slave_0_waitrequest,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
int_ctrl_0_avalon_master_writedata => int_ctrl_0_avalon_master_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_fifo_in_8b_sync_0_avalon_streaming_sink, which is an e_instance
the_fifo_in_8b_sync_0_avalon_streaming_sink : fifo_in_8b_sync_0_avalon_streaming_sink_arbitrator
port map(
fifo_in_8b_sync_0_avalon_streaming_sink_data => fifo_in_8b_sync_0_avalon_streaming_sink_data,
fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa => fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa,
fifo_in_8b_sync_0_avalon_streaming_sink_valid => fifo_in_8b_sync_0_avalon_streaming_sink_valid,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_in_8b_sync_0_avalon_streaming_sink_ready => fifo_in_8b_sync_0_avalon_streaming_sink_ready,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
twi_master_0_avalon_streaming_source_data => twi_master_0_avalon_streaming_source_data,
twi_master_0_avalon_streaming_source_valid => twi_master_0_avalon_streaming_source_valid
);
--the_fifo_in_8b_sync_0, which is an e_ptf_instance
the_fifo_in_8b_sync_0 : fifo_in_8b_sync_0
port map(
irq => internal_irq_from_the_fifo_in_8b_sync_0,
out_data => fifo_in_8b_sync_0_avalon_slave_0_readdata,
st_ready => fifo_in_8b_sync_0_avalon_streaming_sink_ready,
wait_req => fifo_in_8b_sync_0_avalon_slave_0_waitrequest,
addr => fifo_in_8b_sync_0_avalon_slave_0_address,
byte_en => fifo_in_8b_sync_0_avalon_slave_0_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
in_data => fifo_in_8b_sync_0_avalon_slave_0_writedata,
rd_en => fifo_in_8b_sync_0_avalon_slave_0_read,
rst => fifo_in_8b_sync_0_avalon_slave_0_reset,
st_data => fifo_in_8b_sync_0_avalon_streaming_sink_data,
st_valid => fifo_in_8b_sync_0_avalon_streaming_sink_valid,
wr_en => fifo_in_8b_sync_0_avalon_slave_0_write
);
--the_fifo_in_8b_sync_1_avalon_slave_0, which is an e_instance
the_fifo_in_8b_sync_1_avalon_slave_0 : fifo_in_8b_sync_1_avalon_slave_0_arbitrator
port map(
d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer => d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer,
fifo_in_8b_sync_1_avalon_slave_0_address => fifo_in_8b_sync_1_avalon_slave_0_address,
fifo_in_8b_sync_1_avalon_slave_0_byteenable => fifo_in_8b_sync_1_avalon_slave_0_byteenable,
fifo_in_8b_sync_1_avalon_slave_0_read => fifo_in_8b_sync_1_avalon_slave_0_read,
fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa => fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa,
fifo_in_8b_sync_1_avalon_slave_0_reset => fifo_in_8b_sync_1_avalon_slave_0_reset,
fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa => fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa,
fifo_in_8b_sync_1_avalon_slave_0_write => fifo_in_8b_sync_1_avalon_slave_0_write,
fifo_in_8b_sync_1_avalon_slave_0_writedata => fifo_in_8b_sync_1_avalon_slave_0_writedata,
int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_in_8b_sync_1_avalon_slave_0_readdata => fifo_in_8b_sync_1_avalon_slave_0_readdata,
fifo_in_8b_sync_1_avalon_slave_0_waitrequest => fifo_in_8b_sync_1_avalon_slave_0_waitrequest,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
int_ctrl_0_avalon_master_writedata => int_ctrl_0_avalon_master_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_fifo_in_8b_sync_1_avalon_streaming_sink, which is an e_instance
the_fifo_in_8b_sync_1_avalon_streaming_sink : fifo_in_8b_sync_1_avalon_streaming_sink_arbitrator
port map(
fifo_in_8b_sync_1_avalon_streaming_sink_data => fifo_in_8b_sync_1_avalon_streaming_sink_data,
fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa => fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa,
fifo_in_8b_sync_1_avalon_streaming_sink_valid => fifo_in_8b_sync_1_avalon_streaming_sink_valid,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_in_8b_sync_1_avalon_streaming_sink_ready => fifo_in_8b_sync_1_avalon_streaming_sink_ready,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
twi_master_1_avalon_streaming_source_data => twi_master_1_avalon_streaming_source_data,
twi_master_1_avalon_streaming_source_valid => twi_master_1_avalon_streaming_source_valid
);
--the_fifo_in_8b_sync_1, which is an e_ptf_instance
the_fifo_in_8b_sync_1 : fifo_in_8b_sync_1
port map(
irq => internal_irq_from_the_fifo_in_8b_sync_1,
out_data => fifo_in_8b_sync_1_avalon_slave_0_readdata,
st_ready => fifo_in_8b_sync_1_avalon_streaming_sink_ready,
wait_req => fifo_in_8b_sync_1_avalon_slave_0_waitrequest,
addr => fifo_in_8b_sync_1_avalon_slave_0_address,
byte_en => fifo_in_8b_sync_1_avalon_slave_0_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
in_data => fifo_in_8b_sync_1_avalon_slave_0_writedata,
rd_en => fifo_in_8b_sync_1_avalon_slave_0_read,
rst => fifo_in_8b_sync_1_avalon_slave_0_reset,
st_data => fifo_in_8b_sync_1_avalon_streaming_sink_data,
st_valid => fifo_in_8b_sync_1_avalon_streaming_sink_valid,
wr_en => fifo_in_8b_sync_1_avalon_slave_0_write
);
--the_fifo_out_8b_sync_0_avalon_slave_0, which is an e_instance
the_fifo_out_8b_sync_0_avalon_slave_0 : fifo_out_8b_sync_0_avalon_slave_0_arbitrator
port map(
d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer => d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer,
fifo_out_8b_sync_0_avalon_slave_0_address => fifo_out_8b_sync_0_avalon_slave_0_address,
fifo_out_8b_sync_0_avalon_slave_0_byteenable => fifo_out_8b_sync_0_avalon_slave_0_byteenable,
fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa => fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa,
fifo_out_8b_sync_0_avalon_slave_0_reset => fifo_out_8b_sync_0_avalon_slave_0_reset,
fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa => fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa,
fifo_out_8b_sync_0_avalon_slave_0_write => fifo_out_8b_sync_0_avalon_slave_0_write,
fifo_out_8b_sync_0_avalon_slave_0_writedata => fifo_out_8b_sync_0_avalon_slave_0_writedata,
int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_out_8b_sync_0_avalon_slave_0_readdata => fifo_out_8b_sync_0_avalon_slave_0_readdata,
fifo_out_8b_sync_0_avalon_slave_0_waitrequest => fifo_out_8b_sync_0_avalon_slave_0_waitrequest,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
int_ctrl_0_avalon_master_writedata => int_ctrl_0_avalon_master_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_fifo_out_8b_sync_0_avalon_streaming_source, which is an e_instance
the_fifo_out_8b_sync_0_avalon_streaming_source : fifo_out_8b_sync_0_avalon_streaming_source_arbitrator
port map(
fifo_out_8b_sync_0_avalon_streaming_source_ready => fifo_out_8b_sync_0_avalon_streaming_source_ready,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_out_8b_sync_0_avalon_streaming_source_data => fifo_out_8b_sync_0_avalon_streaming_source_data,
fifo_out_8b_sync_0_avalon_streaming_source_valid => fifo_out_8b_sync_0_avalon_streaming_source_valid,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
twi_master_0_avalon_streaming_sink_ready_from_sa => twi_master_0_avalon_streaming_sink_ready_from_sa
);
--the_fifo_out_8b_sync_0, which is an e_ptf_instance
the_fifo_out_8b_sync_0 : fifo_out_8b_sync_0
port map(
irq => internal_irq_from_the_fifo_out_8b_sync_0,
out_data => fifo_out_8b_sync_0_avalon_slave_0_readdata,
st_data => fifo_out_8b_sync_0_avalon_streaming_source_data,
st_valid => fifo_out_8b_sync_0_avalon_streaming_source_valid,
wait_req => fifo_out_8b_sync_0_avalon_slave_0_waitrequest,
addr => fifo_out_8b_sync_0_avalon_slave_0_address,
byte_en => fifo_out_8b_sync_0_avalon_slave_0_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
in_data => fifo_out_8b_sync_0_avalon_slave_0_writedata,
rst => fifo_out_8b_sync_0_avalon_slave_0_reset,
st_ready => fifo_out_8b_sync_0_avalon_streaming_source_ready,
wr_en => fifo_out_8b_sync_0_avalon_slave_0_write
);
--the_fifo_out_8b_sync_1_avalon_slave_0, which is an e_instance
the_fifo_out_8b_sync_1_avalon_slave_0 : fifo_out_8b_sync_1_avalon_slave_0_arbitrator
port map(
d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer => d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer,
fifo_out_8b_sync_1_avalon_slave_0_address => fifo_out_8b_sync_1_avalon_slave_0_address,
fifo_out_8b_sync_1_avalon_slave_0_byteenable => fifo_out_8b_sync_1_avalon_slave_0_byteenable,
fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa => fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa,
fifo_out_8b_sync_1_avalon_slave_0_reset => fifo_out_8b_sync_1_avalon_slave_0_reset,
fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa => fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa,
fifo_out_8b_sync_1_avalon_slave_0_write => fifo_out_8b_sync_1_avalon_slave_0_write,
fifo_out_8b_sync_1_avalon_slave_0_writedata => fifo_out_8b_sync_1_avalon_slave_0_writedata,
int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_out_8b_sync_1_avalon_slave_0_readdata => fifo_out_8b_sync_1_avalon_slave_0_readdata,
fifo_out_8b_sync_1_avalon_slave_0_waitrequest => fifo_out_8b_sync_1_avalon_slave_0_waitrequest,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
int_ctrl_0_avalon_master_writedata => int_ctrl_0_avalon_master_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_fifo_out_8b_sync_1_avalon_streaming_source, which is an e_instance
the_fifo_out_8b_sync_1_avalon_streaming_source : fifo_out_8b_sync_1_avalon_streaming_source_arbitrator
port map(
fifo_out_8b_sync_1_avalon_streaming_source_ready => fifo_out_8b_sync_1_avalon_streaming_source_ready,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_out_8b_sync_1_avalon_streaming_source_data => fifo_out_8b_sync_1_avalon_streaming_source_data,
fifo_out_8b_sync_1_avalon_streaming_source_valid => fifo_out_8b_sync_1_avalon_streaming_source_valid,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
twi_master_1_avalon_streaming_sink_ready_from_sa => twi_master_1_avalon_streaming_sink_ready_from_sa
);
--the_fifo_out_8b_sync_1, which is an e_ptf_instance
the_fifo_out_8b_sync_1 : fifo_out_8b_sync_1
port map(
irq => internal_irq_from_the_fifo_out_8b_sync_1,
out_data => fifo_out_8b_sync_1_avalon_slave_0_readdata,
st_data => fifo_out_8b_sync_1_avalon_streaming_source_data,
st_valid => fifo_out_8b_sync_1_avalon_streaming_source_valid,
wait_req => fifo_out_8b_sync_1_avalon_slave_0_waitrequest,
addr => fifo_out_8b_sync_1_avalon_slave_0_address,
byte_en => fifo_out_8b_sync_1_avalon_slave_0_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
in_data => fifo_out_8b_sync_1_avalon_slave_0_writedata,
rst => fifo_out_8b_sync_1_avalon_slave_0_reset,
st_ready => fifo_out_8b_sync_1_avalon_streaming_source_ready,
wr_en => fifo_out_8b_sync_1_avalon_slave_0_write
);
--the_gpout_0_avalon_slave_0, which is an e_instance
the_gpout_0_avalon_slave_0 : gpout_0_avalon_slave_0_arbitrator
port map(
d1_gpout_0_avalon_slave_0_end_xfer => d1_gpout_0_avalon_slave_0_end_xfer,
gpout_0_avalon_slave_0_address => gpout_0_avalon_slave_0_address,
gpout_0_avalon_slave_0_byteenable => gpout_0_avalon_slave_0_byteenable,
gpout_0_avalon_slave_0_readdata_from_sa => gpout_0_avalon_slave_0_readdata_from_sa,
gpout_0_avalon_slave_0_reset => gpout_0_avalon_slave_0_reset,
gpout_0_avalon_slave_0_write => gpout_0_avalon_slave_0_write,
gpout_0_avalon_slave_0_writedata => gpout_0_avalon_slave_0_writedata,
int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0 => int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_gpout_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_gpout_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
gpout_0_avalon_slave_0_readdata => gpout_0_avalon_slave_0_readdata,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_dbs_address => int_ctrl_0_avalon_master_dbs_address,
int_ctrl_0_avalon_master_dbs_write_16 => int_ctrl_0_avalon_master_dbs_write_16,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_gpout_0, which is an e_ptf_instance
the_gpout_0 : gpout_0
port map(
pins => internal_pins_from_the_gpout_0,
readdata => gpout_0_avalon_slave_0_readdata,
address => gpout_0_avalon_slave_0_address,
byteenable => gpout_0_avalon_slave_0_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
rst => gpout_0_avalon_slave_0_reset,
write => gpout_0_avalon_slave_0_write,
writedata => gpout_0_avalon_slave_0_writedata
);
--the_int_ctrl_0_avalon_cra, which is an e_instance
the_int_ctrl_0_avalon_cra : int_ctrl_0_avalon_cra_arbitrator
port map(
d1_int_ctrl_0_avalon_cra_end_xfer => d1_int_ctrl_0_avalon_cra_end_xfer,
int_ctrl_0_avalon_cra_address => int_ctrl_0_avalon_cra_address,
int_ctrl_0_avalon_cra_byteenable => int_ctrl_0_avalon_cra_byteenable,
int_ctrl_0_avalon_cra_readdata_from_sa => int_ctrl_0_avalon_cra_readdata_from_sa,
int_ctrl_0_avalon_cra_write => int_ctrl_0_avalon_cra_write,
int_ctrl_0_avalon_cra_writedata => int_ctrl_0_avalon_cra_writedata,
int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra => int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra,
int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra => int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra,
int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra => int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra,
int_ctrl_0_avalon_master_read_data_valid_int_ctrl_0_avalon_cra => int_ctrl_0_avalon_master_read_data_valid_int_ctrl_0_avalon_cra,
int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra => int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
int_ctrl_0_avalon_cra_readdata => int_ctrl_0_avalon_cra_readdata,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_dbs_address => int_ctrl_0_avalon_master_dbs_address,
int_ctrl_0_avalon_master_dbs_write_16 => int_ctrl_0_avalon_master_dbs_write_16,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_int_ctrl_0_avalon_slave, which is an e_instance
the_int_ctrl_0_avalon_slave : int_ctrl_0_avalon_slave_arbitrator
port map(
d1_int_ctrl_0_avalon_slave_end_xfer => d1_int_ctrl_0_avalon_slave_end_xfer,
int_ctrl_0_avalon_slave_address => int_ctrl_0_avalon_slave_address,
int_ctrl_0_avalon_slave_byteenable => int_ctrl_0_avalon_slave_byteenable,
int_ctrl_0_avalon_slave_read => int_ctrl_0_avalon_slave_read,
int_ctrl_0_avalon_slave_readdata_from_sa => int_ctrl_0_avalon_slave_readdata_from_sa,
int_ctrl_0_avalon_slave_reset => int_ctrl_0_avalon_slave_reset,
int_ctrl_0_avalon_slave_waitrequest_from_sa => int_ctrl_0_avalon_slave_waitrequest_from_sa,
int_ctrl_0_avalon_slave_write => int_ctrl_0_avalon_slave_write,
int_ctrl_0_avalon_slave_writedata => int_ctrl_0_avalon_slave_writedata,
pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave => pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave,
pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave => pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave,
pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave => pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave,
pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave => pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave,
pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave => pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
int_ctrl_0_avalon_slave_readdata => int_ctrl_0_avalon_slave_readdata,
int_ctrl_0_avalon_slave_waitrequest => int_ctrl_0_avalon_slave_waitrequest,
pipeline_bridge_0_m1_address_to_slave => pipeline_bridge_0_m1_address_to_slave,
pipeline_bridge_0_m1_burstcount => pipeline_bridge_0_m1_burstcount,
pipeline_bridge_0_m1_byteenable => pipeline_bridge_0_m1_byteenable,
pipeline_bridge_0_m1_chipselect => pipeline_bridge_0_m1_chipselect,
pipeline_bridge_0_m1_dbs_address => pipeline_bridge_0_m1_dbs_address,
pipeline_bridge_0_m1_dbs_write_32 => pipeline_bridge_0_m1_dbs_write_32,
pipeline_bridge_0_m1_latency_counter => pipeline_bridge_0_m1_latency_counter,
pipeline_bridge_0_m1_read => pipeline_bridge_0_m1_read,
pipeline_bridge_0_m1_write => pipeline_bridge_0_m1_write,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_int_ctrl_0_avalon_master, which is an e_instance
the_int_ctrl_0_avalon_master : int_ctrl_0_avalon_master_arbitrator
port map(
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_dbs_address => int_ctrl_0_avalon_master_dbs_address,
int_ctrl_0_avalon_master_dbs_write_16 => int_ctrl_0_avalon_master_dbs_write_16,
int_ctrl_0_avalon_master_readdata => int_ctrl_0_avalon_master_readdata,
int_ctrl_0_avalon_master_waitrequest => int_ctrl_0_avalon_master_waitrequest,
ci_bridge_0_avalon_slave_0_readdata_from_sa => ci_bridge_0_avalon_slave_0_readdata_from_sa,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
d1_ci_bridge_0_avalon_slave_0_end_xfer => d1_ci_bridge_0_avalon_slave_0_end_xfer,
d1_dvb_dma_0_avalon_slave_0_end_xfer => d1_dvb_dma_0_avalon_slave_0_end_xfer,
d1_dvb_dma_1_avalon_slave_0_end_xfer => d1_dvb_dma_1_avalon_slave_0_end_xfer,
d1_dvb_ts_0_avalon_slave_0_end_xfer => d1_dvb_ts_0_avalon_slave_0_end_xfer,
d1_dvb_ts_1_avalon_slave_0_end_xfer => d1_dvb_ts_1_avalon_slave_0_end_xfer,
d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer => d1_fifo_in_8b_sync_0_avalon_slave_0_end_xfer,
d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer => d1_fifo_in_8b_sync_1_avalon_slave_0_end_xfer,
d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer => d1_fifo_out_8b_sync_0_avalon_slave_0_end_xfer,
d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer => d1_fifo_out_8b_sync_1_avalon_slave_0_end_xfer,
d1_gpout_0_avalon_slave_0_end_xfer => d1_gpout_0_avalon_slave_0_end_xfer,
d1_int_ctrl_0_avalon_cra_end_xfer => d1_int_ctrl_0_avalon_cra_end_xfer,
d1_pcie_compiler_0_Control_Register_Access_end_xfer => d1_pcie_compiler_0_Control_Register_Access_end_xfer,
d1_spi_master_0_avalon_slave_0_end_xfer => d1_spi_master_0_avalon_slave_0_end_xfer,
d1_twi_master_0_avalon_slave_0_end_xfer => d1_twi_master_0_avalon_slave_0_end_xfer,
d1_twi_master_1_avalon_slave_0_end_xfer => d1_twi_master_1_avalon_slave_0_end_xfer,
dvb_dma_0_avalon_slave_0_readdata_from_sa => dvb_dma_0_avalon_slave_0_readdata_from_sa,
dvb_dma_1_avalon_slave_0_readdata_from_sa => dvb_dma_1_avalon_slave_0_readdata_from_sa,
dvb_ts_0_avalon_slave_0_readdata_from_sa => dvb_ts_0_avalon_slave_0_readdata_from_sa,
dvb_ts_0_avalon_slave_0_waitrequest_from_sa => dvb_ts_0_avalon_slave_0_waitrequest_from_sa,
dvb_ts_1_avalon_slave_0_readdata_from_sa => dvb_ts_1_avalon_slave_0_readdata_from_sa,
dvb_ts_1_avalon_slave_0_waitrequest_from_sa => dvb_ts_1_avalon_slave_0_waitrequest_from_sa,
fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa => fifo_in_8b_sync_0_avalon_slave_0_readdata_from_sa,
fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa => fifo_in_8b_sync_0_avalon_slave_0_waitrequest_from_sa,
fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa => fifo_in_8b_sync_1_avalon_slave_0_readdata_from_sa,
fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa => fifo_in_8b_sync_1_avalon_slave_0_waitrequest_from_sa,
fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa => fifo_out_8b_sync_0_avalon_slave_0_readdata_from_sa,
fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa => fifo_out_8b_sync_0_avalon_slave_0_waitrequest_from_sa,
fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa => fifo_out_8b_sync_1_avalon_slave_0_readdata_from_sa,
fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa => fifo_out_8b_sync_1_avalon_slave_0_waitrequest_from_sa,
gpout_0_avalon_slave_0_readdata_from_sa => gpout_0_avalon_slave_0_readdata_from_sa,
int_ctrl_0_avalon_cra_readdata_from_sa => int_ctrl_0_avalon_cra_readdata_from_sa,
int_ctrl_0_avalon_master_address => int_ctrl_0_avalon_master_address,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0 => int_ctrl_0_avalon_master_byteenable_ci_bridge_0_avalon_slave_0,
int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0 => int_ctrl_0_avalon_master_byteenable_gpout_0_avalon_slave_0,
int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra => int_ctrl_0_avalon_master_byteenable_int_ctrl_0_avalon_cra,
int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0 => int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0,
int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_ci_bridge_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_dvb_dma_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0 => int_ctrl_0_avalon_master_granted_dvb_dma_1_avalon_slave_0,
int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_dvb_ts_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0 => int_ctrl_0_avalon_master_granted_dvb_ts_1_avalon_slave_0,
int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_granted_fifo_in_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_granted_fifo_out_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_gpout_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra => int_ctrl_0_avalon_master_granted_int_ctrl_0_avalon_cra,
int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access => int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access,
int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 => int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_ci_bridge_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_dvb_dma_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_dvb_dma_1_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_dvb_ts_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_dvb_ts_1_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_fifo_in_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_fifo_out_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_gpout_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra => int_ctrl_0_avalon_master_qualified_request_int_ctrl_0_avalon_cra,
int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access => int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access,
int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_read_data_valid_ci_bridge_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_ci_bridge_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_dvb_dma_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_dvb_dma_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_dvb_dma_1_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_dvb_dma_1_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_dvb_ts_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_dvb_ts_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_dvb_ts_1_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_dvb_ts_1_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_fifo_in_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_fifo_out_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_gpout_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_gpout_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_int_ctrl_0_avalon_cra => int_ctrl_0_avalon_master_read_data_valid_int_ctrl_0_avalon_cra,
int_ctrl_0_avalon_master_read_data_valid_pcie_compiler_0_Control_Register_Access => int_ctrl_0_avalon_master_read_data_valid_pcie_compiler_0_Control_Register_Access,
int_ctrl_0_avalon_master_read_data_valid_spi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_spi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_twi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_twi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_twi_master_1_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_twi_master_1_avalon_slave_0,
int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_ci_bridge_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_dvb_dma_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0 => int_ctrl_0_avalon_master_requests_dvb_dma_1_avalon_slave_0,
int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_dvb_ts_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0 => int_ctrl_0_avalon_master_requests_dvb_ts_1_avalon_slave_0,
int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_requests_fifo_in_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0 => int_ctrl_0_avalon_master_requests_fifo_out_8b_sync_1_avalon_slave_0,
int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_gpout_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra => int_ctrl_0_avalon_master_requests_int_ctrl_0_avalon_cra,
int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access => int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access,
int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0 => int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
int_ctrl_0_avalon_master_writedata => int_ctrl_0_avalon_master_writedata,
pcie_compiler_0_Control_Register_Access_readdata_from_sa => pcie_compiler_0_Control_Register_Access_readdata_from_sa,
pcie_compiler_0_Control_Register_Access_waitrequest_from_sa => pcie_compiler_0_Control_Register_Access_waitrequest_from_sa,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
spi_master_0_avalon_slave_0_readdata_from_sa => spi_master_0_avalon_slave_0_readdata_from_sa,
spi_master_0_avalon_slave_0_waitrequest_from_sa => spi_master_0_avalon_slave_0_waitrequest_from_sa,
twi_master_0_avalon_slave_0_readdata_from_sa => twi_master_0_avalon_slave_0_readdata_from_sa,
twi_master_1_avalon_slave_0_readdata_from_sa => twi_master_1_avalon_slave_0_readdata_from_sa
);
--the_int_ctrl_0, which is an e_ptf_instance
the_int_ctrl_0 : int_ctrl_0
port map(
avlm_address => int_ctrl_0_avalon_master_address,
avlm_byteenable => int_ctrl_0_avalon_master_byteenable,
avlm_read => int_ctrl_0_avalon_master_read,
avlm_write => int_ctrl_0_avalon_master_write,
avlm_writedata => int_ctrl_0_avalon_master_writedata,
avls_irq => int_ctrl_0_avalon_slave_irq,
avls_readdata => int_ctrl_0_avalon_slave_readdata,
avls_waitrequest => int_ctrl_0_avalon_slave_waitrequest,
readdata => int_ctrl_0_avalon_cra_readdata,
address => int_ctrl_0_avalon_cra_address,
avlm_irq => avlm_irq_to_the_int_ctrl_0,
avlm_readdata => int_ctrl_0_avalon_master_readdata,
avlm_waitrequest => int_ctrl_0_avalon_master_waitrequest,
avls_address => int_ctrl_0_avalon_slave_address,
avls_byteenable => int_ctrl_0_avalon_slave_byteenable,
avls_read => int_ctrl_0_avalon_slave_read,
avls_write => int_ctrl_0_avalon_slave_write,
avls_writedata => int_ctrl_0_avalon_slave_writedata,
byteenable => int_ctrl_0_avalon_cra_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
rst => int_ctrl_0_avalon_slave_reset,
write => int_ctrl_0_avalon_cra_write,
writedata => int_ctrl_0_avalon_cra_writedata
);
--the_pcie_compiler_0_Control_Register_Access, which is an e_instance
the_pcie_compiler_0_Control_Register_Access : pcie_compiler_0_Control_Register_Access_arbitrator
port map(
d1_pcie_compiler_0_Control_Register_Access_end_xfer => d1_pcie_compiler_0_Control_Register_Access_end_xfer,
int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access => int_ctrl_0_avalon_master_granted_pcie_compiler_0_Control_Register_Access,
int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access => int_ctrl_0_avalon_master_qualified_request_pcie_compiler_0_Control_Register_Access,
int_ctrl_0_avalon_master_read_data_valid_pcie_compiler_0_Control_Register_Access => int_ctrl_0_avalon_master_read_data_valid_pcie_compiler_0_Control_Register_Access,
int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access => int_ctrl_0_avalon_master_requests_pcie_compiler_0_Control_Register_Access,
pcie_compiler_0_Control_Register_Access_address => pcie_compiler_0_Control_Register_Access_address,
pcie_compiler_0_Control_Register_Access_byteenable => pcie_compiler_0_Control_Register_Access_byteenable,
pcie_compiler_0_Control_Register_Access_chipselect => pcie_compiler_0_Control_Register_Access_chipselect,
pcie_compiler_0_Control_Register_Access_read => pcie_compiler_0_Control_Register_Access_read,
pcie_compiler_0_Control_Register_Access_readdata_from_sa => pcie_compiler_0_Control_Register_Access_readdata_from_sa,
pcie_compiler_0_Control_Register_Access_waitrequest_from_sa => pcie_compiler_0_Control_Register_Access_waitrequest_from_sa,
pcie_compiler_0_Control_Register_Access_write => pcie_compiler_0_Control_Register_Access_write,
pcie_compiler_0_Control_Register_Access_writedata => pcie_compiler_0_Control_Register_Access_writedata,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
int_ctrl_0_avalon_master_writedata => int_ctrl_0_avalon_master_writedata,
pcie_compiler_0_Control_Register_Access_readdata => pcie_compiler_0_Control_Register_Access_readdata,
pcie_compiler_0_Control_Register_Access_waitrequest => pcie_compiler_0_Control_Register_Access_waitrequest,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_pcie_compiler_0_Tx_Interface, which is an e_instance
the_pcie_compiler_0_Tx_Interface : pcie_compiler_0_Tx_Interface_arbitrator
port map(
d1_pcie_compiler_0_Tx_Interface_end_xfer => d1_pcie_compiler_0_Tx_Interface_end_xfer,
dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface => dma_arbiter_0_granted_pcie_compiler_0_Tx_Interface,
dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface => dma_arbiter_0_qualified_request_pcie_compiler_0_Tx_Interface,
dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface => dma_arbiter_0_requests_pcie_compiler_0_Tx_Interface,
pcie_compiler_0_Tx_Interface_address => pcie_compiler_0_Tx_Interface_address,
pcie_compiler_0_Tx_Interface_burstcount => pcie_compiler_0_Tx_Interface_burstcount,
pcie_compiler_0_Tx_Interface_byteenable => pcie_compiler_0_Tx_Interface_byteenable,
pcie_compiler_0_Tx_Interface_chipselect => pcie_compiler_0_Tx_Interface_chipselect,
pcie_compiler_0_Tx_Interface_read => pcie_compiler_0_Tx_Interface_read,
pcie_compiler_0_Tx_Interface_readdata_from_sa => pcie_compiler_0_Tx_Interface_readdata_from_sa,
pcie_compiler_0_Tx_Interface_readdatavalid_from_sa => pcie_compiler_0_Tx_Interface_readdatavalid_from_sa,
pcie_compiler_0_Tx_Interface_waitrequest_from_sa => pcie_compiler_0_Tx_Interface_waitrequest_from_sa,
pcie_compiler_0_Tx_Interface_write => pcie_compiler_0_Tx_Interface_write,
pcie_compiler_0_Tx_Interface_writedata => pcie_compiler_0_Tx_Interface_writedata,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
dma_arbiter_0_avalon_master_address_to_slave => dma_arbiter_0_avalon_master_address_to_slave,
dma_arbiter_0_avalon_master_burstcount => dma_arbiter_0_avalon_master_burstcount,
dma_arbiter_0_avalon_master_byteenable => dma_arbiter_0_avalon_master_byteenable,
dma_arbiter_0_avalon_master_write => dma_arbiter_0_avalon_master_write,
dma_arbiter_0_avalon_master_writedata => dma_arbiter_0_avalon_master_writedata,
pcie_compiler_0_Tx_Interface_readdata => pcie_compiler_0_Tx_Interface_readdata,
pcie_compiler_0_Tx_Interface_readdatavalid => pcie_compiler_0_Tx_Interface_readdatavalid,
pcie_compiler_0_Tx_Interface_waitrequest => pcie_compiler_0_Tx_Interface_waitrequest,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_pcie_compiler_0_Rx_Interface, which is an e_instance
the_pcie_compiler_0_Rx_Interface : pcie_compiler_0_Rx_Interface_arbitrator
port map(
pcie_compiler_0_Rx_Interface_address_to_slave => pcie_compiler_0_Rx_Interface_address_to_slave,
pcie_compiler_0_Rx_Interface_latency_counter => pcie_compiler_0_Rx_Interface_latency_counter,
pcie_compiler_0_Rx_Interface_readdata => pcie_compiler_0_Rx_Interface_readdata,
pcie_compiler_0_Rx_Interface_readdatavalid => pcie_compiler_0_Rx_Interface_readdatavalid,
pcie_compiler_0_Rx_Interface_reset_n => pcie_compiler_0_Rx_Interface_reset_n,
pcie_compiler_0_Rx_Interface_waitrequest => pcie_compiler_0_Rx_Interface_waitrequest,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
d1_unici_core_burst_0_upstream_end_xfer => d1_unici_core_burst_0_upstream_end_xfer,
d1_unici_core_burst_1_upstream_end_xfer => d1_unici_core_burst_1_upstream_end_xfer,
pcie_compiler_0_Rx_Interface_address => pcie_compiler_0_Rx_Interface_address,
pcie_compiler_0_Rx_Interface_burstcount => pcie_compiler_0_Rx_Interface_burstcount,
pcie_compiler_0_Rx_Interface_byteenable => pcie_compiler_0_Rx_Interface_byteenable,
pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream => pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream,
pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream => pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream,
pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream => pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream,
pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream => pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream,
pcie_compiler_0_Rx_Interface_read => pcie_compiler_0_Rx_Interface_read,
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream => pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream,
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register => pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register,
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream => pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream,
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register => pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register,
pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream => pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream,
pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream => pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream,
pcie_compiler_0_Rx_Interface_write => pcie_compiler_0_Rx_Interface_write,
pcie_compiler_0_Rx_Interface_writedata => pcie_compiler_0_Rx_Interface_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
unici_core_burst_0_upstream_readdata_from_sa => unici_core_burst_0_upstream_readdata_from_sa,
unici_core_burst_0_upstream_waitrequest_from_sa => unici_core_burst_0_upstream_waitrequest_from_sa,
unici_core_burst_1_upstream_readdata_from_sa => unici_core_burst_1_upstream_readdata_from_sa,
unici_core_burst_1_upstream_waitrequest_from_sa => unici_core_burst_1_upstream_waitrequest_from_sa
);
--pcie_compiler_0_pcie_core_clk_out out_clk assignment, which is an e_assign
internal_pcie_compiler_0_pcie_core_clk_out <= out_clk_pcie_compiler_0_pcie_core_clk;
--the_pcie_compiler_0, which is an e_ptf_instance
the_pcie_compiler_0 : pcie_compiler_0
port map(
CraIrq_o => pcie_compiler_0_Control_Register_Access_irq,
CraReadData_o => pcie_compiler_0_Control_Register_Access_readdata,
CraWaitRequest_o => pcie_compiler_0_Control_Register_Access_waitrequest,
RxmAddress_o => pcie_compiler_0_Rx_Interface_address,
RxmBurstCount_o => pcie_compiler_0_Rx_Interface_burstcount,
RxmByteEnable_o => pcie_compiler_0_Rx_Interface_byteenable,
RxmRead_o => pcie_compiler_0_Rx_Interface_read,
RxmResetRequest_o => pcie_compiler_0_Rx_Interface_resetrequest,
RxmWriteData_o => pcie_compiler_0_Rx_Interface_writedata,
RxmWrite_o => pcie_compiler_0_Rx_Interface_write,
TxsReadDataValid_o => pcie_compiler_0_Tx_Interface_readdatavalid,
TxsReadData_o => pcie_compiler_0_Tx_Interface_readdata,
TxsWaitRequest_o => pcie_compiler_0_Tx_Interface_waitrequest,
clk125_out => internal_clk125_out_pcie_compiler_0,
clk250_out => internal_clk250_out_pcie_compiler_0,
clk500_out => internal_clk500_out_pcie_compiler_0,
pcie_core_clk => out_clk_pcie_compiler_0_pcie_core_clk,
powerdown_ext => internal_powerdown_ext_pcie_compiler_0,
rate_ext => internal_rate_ext_pcie_compiler_0,
reconfig_fromgxb => internal_reconfig_fromgxb_pcie_compiler_0,
rxpolarity0_ext => internal_rxpolarity0_ext_pcie_compiler_0,
tx_out0 => internal_tx_out0_pcie_compiler_0,
txcompl0_ext => internal_txcompl0_ext_pcie_compiler_0,
txdata0_ext => internal_txdata0_ext_pcie_compiler_0,
txdatak0_ext => internal_txdatak0_ext_pcie_compiler_0,
txdetectrx_ext => internal_txdetectrx_ext_pcie_compiler_0,
txelecidle0_ext => internal_txelecidle0_ext_pcie_compiler_0,
AvlClk_i => internal_pcie_compiler_0_pcie_core_clk_out,
CraAddress_i => pcie_compiler_0_Control_Register_Access_address,
CraByteEnable_i => pcie_compiler_0_Control_Register_Access_byteenable,
CraChipSelect_i => pcie_compiler_0_Control_Register_Access_chipselect,
CraRead => pcie_compiler_0_Control_Register_Access_read,
CraWrite => pcie_compiler_0_Control_Register_Access_write,
CraWriteData_i => pcie_compiler_0_Control_Register_Access_writedata,
RxmIrqNum_i => pcie_compiler_0_Rx_Interface_irqnumber,
RxmIrq_i => pcie_compiler_0_Rx_Interface_irq,
RxmReadDataValid_i => pcie_compiler_0_Rx_Interface_readdatavalid,
RxmReadData_i => pcie_compiler_0_Rx_Interface_readdata,
RxmWaitRequest_i => pcie_compiler_0_Rx_Interface_waitrequest,
TxsAddress_i => pcie_compiler_0_Tx_Interface_address,
TxsBurstCount_i => pcie_compiler_0_Tx_Interface_burstcount,
TxsByteEnable_i => pcie_compiler_0_Tx_Interface_byteenable,
TxsChipSelect_i => pcie_compiler_0_Tx_Interface_chipselect,
TxsRead_i => pcie_compiler_0_Tx_Interface_read,
TxsWriteData_i => pcie_compiler_0_Tx_Interface_writedata,
TxsWrite_i => pcie_compiler_0_Tx_Interface_write,
busy_altgxb_reconfig => busy_altgxb_reconfig_pcie_compiler_0,
cal_blk_clk => internal_pcie_compiler_0_pcie_core_clk_out,
fixedclk_serdes => fixedclk_serdes_pcie_compiler_0,
gxb_powerdown => gxb_powerdown_pcie_compiler_0,
pcie_rstn => pcie_rstn_pcie_compiler_0,
phystatus_ext => phystatus_ext_pcie_compiler_0,
pipe_mode => pipe_mode_pcie_compiler_0,
pll_powerdown => pll_powerdown_pcie_compiler_0,
reconfig_clk => reconfig_clk_pcie_compiler_0,
reconfig_togxb => reconfig_togxb_pcie_compiler_0,
refclk => refclk_pcie_compiler_0,
reset_n => pcie_compiler_0_Rx_Interface_reset_n,
rx_in0 => rx_in0_pcie_compiler_0,
rxdata0_ext => rxdata0_ext_pcie_compiler_0,
rxdatak0_ext => rxdatak0_ext_pcie_compiler_0,
rxelecidle0_ext => rxelecidle0_ext_pcie_compiler_0,
rxstatus0_ext => rxstatus0_ext_pcie_compiler_0,
rxvalid0_ext => rxvalid0_ext_pcie_compiler_0,
test_in => test_in_pcie_compiler_0
);
--the_pipeline_bridge_0_s1, which is an e_instance
the_pipeline_bridge_0_s1 : pipeline_bridge_0_s1_arbitrator
port map(
d1_pipeline_bridge_0_s1_end_xfer => d1_pipeline_bridge_0_s1_end_xfer,
pipeline_bridge_0_s1_address => pipeline_bridge_0_s1_address,
pipeline_bridge_0_s1_arbiterlock => pipeline_bridge_0_s1_arbiterlock,
pipeline_bridge_0_s1_arbiterlock2 => pipeline_bridge_0_s1_arbiterlock2,
pipeline_bridge_0_s1_burstcount => pipeline_bridge_0_s1_burstcount,
pipeline_bridge_0_s1_byteenable => pipeline_bridge_0_s1_byteenable,
pipeline_bridge_0_s1_chipselect => pipeline_bridge_0_s1_chipselect,
pipeline_bridge_0_s1_debugaccess => pipeline_bridge_0_s1_debugaccess,
pipeline_bridge_0_s1_endofpacket_from_sa => pipeline_bridge_0_s1_endofpacket_from_sa,
pipeline_bridge_0_s1_nativeaddress => pipeline_bridge_0_s1_nativeaddress,
pipeline_bridge_0_s1_read => pipeline_bridge_0_s1_read,
pipeline_bridge_0_s1_readdata_from_sa => pipeline_bridge_0_s1_readdata_from_sa,
pipeline_bridge_0_s1_reset_n => pipeline_bridge_0_s1_reset_n,
pipeline_bridge_0_s1_waitrequest_from_sa => pipeline_bridge_0_s1_waitrequest_from_sa,
pipeline_bridge_0_s1_write => pipeline_bridge_0_s1_write,
pipeline_bridge_0_s1_writedata => pipeline_bridge_0_s1_writedata,
unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 => unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1,
unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 => unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1,
unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1 => unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1,
unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1_shift_register => unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1_shift_register,
unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 => unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
pipeline_bridge_0_s1_endofpacket => pipeline_bridge_0_s1_endofpacket,
pipeline_bridge_0_s1_readdata => pipeline_bridge_0_s1_readdata,
pipeline_bridge_0_s1_readdatavalid => pipeline_bridge_0_s1_readdatavalid,
pipeline_bridge_0_s1_waitrequest => pipeline_bridge_0_s1_waitrequest,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
unici_core_burst_0_downstream_address_to_slave => unici_core_burst_0_downstream_address_to_slave,
unici_core_burst_0_downstream_arbitrationshare => unici_core_burst_0_downstream_arbitrationshare,
unici_core_burst_0_downstream_burstcount => unici_core_burst_0_downstream_burstcount,
unici_core_burst_0_downstream_byteenable => unici_core_burst_0_downstream_byteenable,
unici_core_burst_0_downstream_debugaccess => unici_core_burst_0_downstream_debugaccess,
unici_core_burst_0_downstream_latency_counter => unici_core_burst_0_downstream_latency_counter,
unici_core_burst_0_downstream_nativeaddress => unici_core_burst_0_downstream_nativeaddress,
unici_core_burst_0_downstream_read => unici_core_burst_0_downstream_read,
unici_core_burst_0_downstream_write => unici_core_burst_0_downstream_write,
unici_core_burst_0_downstream_writedata => unici_core_burst_0_downstream_writedata
);
--the_pipeline_bridge_0_m1, which is an e_instance
the_pipeline_bridge_0_m1 : pipeline_bridge_0_m1_arbitrator
port map(
pipeline_bridge_0_m1_address_to_slave => pipeline_bridge_0_m1_address_to_slave,
pipeline_bridge_0_m1_dbs_address => pipeline_bridge_0_m1_dbs_address,
pipeline_bridge_0_m1_dbs_write_32 => pipeline_bridge_0_m1_dbs_write_32,
pipeline_bridge_0_m1_latency_counter => pipeline_bridge_0_m1_latency_counter,
pipeline_bridge_0_m1_readdata => pipeline_bridge_0_m1_readdata,
pipeline_bridge_0_m1_readdatavalid => pipeline_bridge_0_m1_readdatavalid,
pipeline_bridge_0_m1_waitrequest => pipeline_bridge_0_m1_waitrequest,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
d1_int_ctrl_0_avalon_slave_end_xfer => d1_int_ctrl_0_avalon_slave_end_xfer,
int_ctrl_0_avalon_slave_readdata_from_sa => int_ctrl_0_avalon_slave_readdata_from_sa,
int_ctrl_0_avalon_slave_waitrequest_from_sa => int_ctrl_0_avalon_slave_waitrequest_from_sa,
pipeline_bridge_0_m1_address => pipeline_bridge_0_m1_address,
pipeline_bridge_0_m1_burstcount => pipeline_bridge_0_m1_burstcount,
pipeline_bridge_0_m1_byteenable => pipeline_bridge_0_m1_byteenable,
pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave => pipeline_bridge_0_m1_byteenable_int_ctrl_0_avalon_slave,
pipeline_bridge_0_m1_chipselect => pipeline_bridge_0_m1_chipselect,
pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave => pipeline_bridge_0_m1_granted_int_ctrl_0_avalon_slave,
pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave => pipeline_bridge_0_m1_qualified_request_int_ctrl_0_avalon_slave,
pipeline_bridge_0_m1_read => pipeline_bridge_0_m1_read,
pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave => pipeline_bridge_0_m1_read_data_valid_int_ctrl_0_avalon_slave,
pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave => pipeline_bridge_0_m1_requests_int_ctrl_0_avalon_slave,
pipeline_bridge_0_m1_write => pipeline_bridge_0_m1_write,
pipeline_bridge_0_m1_writedata => pipeline_bridge_0_m1_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n
);
--the_pipeline_bridge_0, which is an e_ptf_instance
the_pipeline_bridge_0 : pipeline_bridge_0
port map(
m1_address => pipeline_bridge_0_m1_address,
m1_burstcount => pipeline_bridge_0_m1_burstcount,
m1_byteenable => pipeline_bridge_0_m1_byteenable,
m1_chipselect => pipeline_bridge_0_m1_chipselect,
m1_debugaccess => pipeline_bridge_0_m1_debugaccess,
m1_read => pipeline_bridge_0_m1_read,
m1_write => pipeline_bridge_0_m1_write,
m1_writedata => pipeline_bridge_0_m1_writedata,
s1_endofpacket => pipeline_bridge_0_s1_endofpacket,
s1_readdata => pipeline_bridge_0_s1_readdata,
s1_readdatavalid => pipeline_bridge_0_s1_readdatavalid,
s1_waitrequest => pipeline_bridge_0_s1_waitrequest,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
m1_endofpacket => pipeline_bridge_0_m1_endofpacket,
m1_readdata => pipeline_bridge_0_m1_readdata,
m1_readdatavalid => pipeline_bridge_0_m1_readdatavalid,
m1_waitrequest => pipeline_bridge_0_m1_waitrequest,
reset_n => pipeline_bridge_0_s1_reset_n,
s1_address => pipeline_bridge_0_s1_address,
s1_arbiterlock => pipeline_bridge_0_s1_arbiterlock,
s1_arbiterlock2 => pipeline_bridge_0_s1_arbiterlock2,
s1_burstcount => pipeline_bridge_0_s1_burstcount,
s1_byteenable => pipeline_bridge_0_s1_byteenable,
s1_chipselect => pipeline_bridge_0_s1_chipselect,
s1_debugaccess => pipeline_bridge_0_s1_debugaccess,
s1_nativeaddress => pipeline_bridge_0_s1_nativeaddress,
s1_read => pipeline_bridge_0_s1_read,
s1_write => pipeline_bridge_0_s1_write,
s1_writedata => pipeline_bridge_0_s1_writedata
);
--the_spi_master_0_avalon_slave_0, which is an e_instance
the_spi_master_0_avalon_slave_0 : spi_master_0_avalon_slave_0_arbitrator
port map(
d1_spi_master_0_avalon_slave_0_end_xfer => d1_spi_master_0_avalon_slave_0_end_xfer,
int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_byteenable_spi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_spi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_spi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_spi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_spi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_spi_master_0_avalon_slave_0,
spi_master_0_avalon_slave_0_address => spi_master_0_avalon_slave_0_address,
spi_master_0_avalon_slave_0_byteenable => spi_master_0_avalon_slave_0_byteenable,
spi_master_0_avalon_slave_0_readdata_from_sa => spi_master_0_avalon_slave_0_readdata_from_sa,
spi_master_0_avalon_slave_0_reset => spi_master_0_avalon_slave_0_reset,
spi_master_0_avalon_slave_0_waitrequest_from_sa => spi_master_0_avalon_slave_0_waitrequest_from_sa,
spi_master_0_avalon_slave_0_write => spi_master_0_avalon_slave_0_write,
spi_master_0_avalon_slave_0_writedata => spi_master_0_avalon_slave_0_writedata,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_dbs_address => int_ctrl_0_avalon_master_dbs_address,
int_ctrl_0_avalon_master_dbs_write_16 => int_ctrl_0_avalon_master_dbs_write_16,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
spi_master_0_avalon_slave_0_readdata => spi_master_0_avalon_slave_0_readdata,
spi_master_0_avalon_slave_0_waitrequest => spi_master_0_avalon_slave_0_waitrequest
);
--the_spi_master_0, which is an e_ptf_instance
the_spi_master_0 : spi_master_0
port map(
cs_n => internal_cs_n_from_the_spi_master_0,
irq => internal_irq_from_the_spi_master_0,
mosi => internal_mosi_from_the_spi_master_0,
out_data => spi_master_0_avalon_slave_0_readdata,
sclk => internal_sclk_from_the_spi_master_0,
wait_req => spi_master_0_avalon_slave_0_waitrequest,
addr => spi_master_0_avalon_slave_0_address,
byte_en => spi_master_0_avalon_slave_0_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
in_data => spi_master_0_avalon_slave_0_writedata,
miso => miso_to_the_spi_master_0,
rst => spi_master_0_avalon_slave_0_reset,
wr_en => spi_master_0_avalon_slave_0_write
);
--the_twi_master_0_avalon_slave_0, which is an e_instance
the_twi_master_0_avalon_slave_0 : twi_master_0_avalon_slave_0_arbitrator
port map(
d1_twi_master_0_avalon_slave_0_end_xfer => d1_twi_master_0_avalon_slave_0_end_xfer,
int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_byteenable_twi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_granted_twi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_twi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_twi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_twi_master_0_avalon_slave_0,
int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0 => int_ctrl_0_avalon_master_requests_twi_master_0_avalon_slave_0,
twi_master_0_avalon_slave_0_address => twi_master_0_avalon_slave_0_address,
twi_master_0_avalon_slave_0_byteenable => twi_master_0_avalon_slave_0_byteenable,
twi_master_0_avalon_slave_0_readdata_from_sa => twi_master_0_avalon_slave_0_readdata_from_sa,
twi_master_0_avalon_slave_0_reset => twi_master_0_avalon_slave_0_reset,
twi_master_0_avalon_slave_0_write => twi_master_0_avalon_slave_0_write,
twi_master_0_avalon_slave_0_writedata => twi_master_0_avalon_slave_0_writedata,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_dbs_address => int_ctrl_0_avalon_master_dbs_address,
int_ctrl_0_avalon_master_dbs_write_16 => int_ctrl_0_avalon_master_dbs_write_16,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
twi_master_0_avalon_slave_0_readdata => twi_master_0_avalon_slave_0_readdata
);
--the_twi_master_0_avalon_streaming_sink, which is an e_instance
the_twi_master_0_avalon_streaming_sink : twi_master_0_avalon_streaming_sink_arbitrator
port map(
twi_master_0_avalon_streaming_sink_data => twi_master_0_avalon_streaming_sink_data,
twi_master_0_avalon_streaming_sink_ready_from_sa => twi_master_0_avalon_streaming_sink_ready_from_sa,
twi_master_0_avalon_streaming_sink_valid => twi_master_0_avalon_streaming_sink_valid,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_out_8b_sync_0_avalon_streaming_source_data => fifo_out_8b_sync_0_avalon_streaming_source_data,
fifo_out_8b_sync_0_avalon_streaming_source_valid => fifo_out_8b_sync_0_avalon_streaming_source_valid,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
twi_master_0_avalon_streaming_sink_ready => twi_master_0_avalon_streaming_sink_ready
);
--the_twi_master_0_avalon_streaming_source, which is an e_instance
the_twi_master_0_avalon_streaming_source : twi_master_0_avalon_streaming_source_arbitrator
port map(
twi_master_0_avalon_streaming_source_ready => twi_master_0_avalon_streaming_source_ready,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa => fifo_in_8b_sync_0_avalon_streaming_sink_ready_from_sa,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
twi_master_0_avalon_streaming_source_data => twi_master_0_avalon_streaming_source_data,
twi_master_0_avalon_streaming_source_valid => twi_master_0_avalon_streaming_source_valid
);
--the_twi_master_0, which is an e_ptf_instance
the_twi_master_0 : twi_master_0
port map(
in_ready => twi_master_0_avalon_streaming_sink_ready,
irq => internal_irq_from_the_twi_master_0,
out_data => twi_master_0_avalon_slave_0_readdata,
out_octet => twi_master_0_avalon_streaming_source_data,
out_valid => twi_master_0_avalon_streaming_source_valid,
scl_act => internal_scl_act_from_the_twi_master_0,
sda_act => internal_sda_act_from_the_twi_master_0,
addr => twi_master_0_avalon_slave_0_address,
byte_en => twi_master_0_avalon_slave_0_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
in_data => twi_master_0_avalon_slave_0_writedata,
in_octet => twi_master_0_avalon_streaming_sink_data,
in_valid => twi_master_0_avalon_streaming_sink_valid,
out_ready => twi_master_0_avalon_streaming_source_ready,
rst => twi_master_0_avalon_slave_0_reset,
scl_in => scl_in_to_the_twi_master_0,
sda_in => sda_in_to_the_twi_master_0,
sink_irq => sink_irq_to_the_twi_master_0,
source_irq => source_irq_to_the_twi_master_0,
wr_en => twi_master_0_avalon_slave_0_write
);
--the_twi_master_1_avalon_slave_0, which is an e_instance
the_twi_master_1_avalon_slave_0 : twi_master_1_avalon_slave_0_arbitrator
port map(
d1_twi_master_1_avalon_slave_0_end_xfer => d1_twi_master_1_avalon_slave_0_end_xfer,
int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0 => int_ctrl_0_avalon_master_byteenable_twi_master_1_avalon_slave_0,
int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0 => int_ctrl_0_avalon_master_granted_twi_master_1_avalon_slave_0,
int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0 => int_ctrl_0_avalon_master_qualified_request_twi_master_1_avalon_slave_0,
int_ctrl_0_avalon_master_read_data_valid_twi_master_1_avalon_slave_0 => int_ctrl_0_avalon_master_read_data_valid_twi_master_1_avalon_slave_0,
int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0 => int_ctrl_0_avalon_master_requests_twi_master_1_avalon_slave_0,
twi_master_1_avalon_slave_0_address => twi_master_1_avalon_slave_0_address,
twi_master_1_avalon_slave_0_byteenable => twi_master_1_avalon_slave_0_byteenable,
twi_master_1_avalon_slave_0_readdata_from_sa => twi_master_1_avalon_slave_0_readdata_from_sa,
twi_master_1_avalon_slave_0_reset => twi_master_1_avalon_slave_0_reset,
twi_master_1_avalon_slave_0_write => twi_master_1_avalon_slave_0_write,
twi_master_1_avalon_slave_0_writedata => twi_master_1_avalon_slave_0_writedata,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
int_ctrl_0_avalon_master_address_to_slave => int_ctrl_0_avalon_master_address_to_slave,
int_ctrl_0_avalon_master_byteenable => int_ctrl_0_avalon_master_byteenable,
int_ctrl_0_avalon_master_dbs_address => int_ctrl_0_avalon_master_dbs_address,
int_ctrl_0_avalon_master_dbs_write_16 => int_ctrl_0_avalon_master_dbs_write_16,
int_ctrl_0_avalon_master_read => int_ctrl_0_avalon_master_read,
int_ctrl_0_avalon_master_write => int_ctrl_0_avalon_master_write,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
twi_master_1_avalon_slave_0_readdata => twi_master_1_avalon_slave_0_readdata
);
--the_twi_master_1_avalon_streaming_sink, which is an e_instance
the_twi_master_1_avalon_streaming_sink : twi_master_1_avalon_streaming_sink_arbitrator
port map(
twi_master_1_avalon_streaming_sink_data => twi_master_1_avalon_streaming_sink_data,
twi_master_1_avalon_streaming_sink_ready_from_sa => twi_master_1_avalon_streaming_sink_ready_from_sa,
twi_master_1_avalon_streaming_sink_valid => twi_master_1_avalon_streaming_sink_valid,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_out_8b_sync_1_avalon_streaming_source_data => fifo_out_8b_sync_1_avalon_streaming_source_data,
fifo_out_8b_sync_1_avalon_streaming_source_valid => fifo_out_8b_sync_1_avalon_streaming_source_valid,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
twi_master_1_avalon_streaming_sink_ready => twi_master_1_avalon_streaming_sink_ready
);
--the_twi_master_1_avalon_streaming_source, which is an e_instance
the_twi_master_1_avalon_streaming_source : twi_master_1_avalon_streaming_source_arbitrator
port map(
twi_master_1_avalon_streaming_source_ready => twi_master_1_avalon_streaming_source_ready,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa => fifo_in_8b_sync_1_avalon_streaming_sink_ready_from_sa,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
twi_master_1_avalon_streaming_source_data => twi_master_1_avalon_streaming_source_data,
twi_master_1_avalon_streaming_source_valid => twi_master_1_avalon_streaming_source_valid
);
--the_twi_master_1, which is an e_ptf_instance
the_twi_master_1 : twi_master_1
port map(
in_ready => twi_master_1_avalon_streaming_sink_ready,
irq => internal_irq_from_the_twi_master_1,
out_data => twi_master_1_avalon_slave_0_readdata,
out_octet => twi_master_1_avalon_streaming_source_data,
out_valid => twi_master_1_avalon_streaming_source_valid,
scl_act => internal_scl_act_from_the_twi_master_1,
sda_act => internal_sda_act_from_the_twi_master_1,
addr => twi_master_1_avalon_slave_0_address,
byte_en => twi_master_1_avalon_slave_0_byteenable,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
in_data => twi_master_1_avalon_slave_0_writedata,
in_octet => twi_master_1_avalon_streaming_sink_data,
in_valid => twi_master_1_avalon_streaming_sink_valid,
out_ready => twi_master_1_avalon_streaming_source_ready,
rst => twi_master_1_avalon_slave_0_reset,
scl_in => scl_in_to_the_twi_master_1,
sda_in => sda_in_to_the_twi_master_1,
sink_irq => sink_irq_to_the_twi_master_1,
source_irq => source_irq_to_the_twi_master_1,
wr_en => twi_master_1_avalon_slave_0_write
);
--the_unici_core_burst_0_upstream, which is an e_instance
the_unici_core_burst_0_upstream : unici_core_burst_0_upstream_arbitrator
port map(
d1_unici_core_burst_0_upstream_end_xfer => d1_unici_core_burst_0_upstream_end_xfer,
pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream => pcie_compiler_0_Rx_Interface_granted_unici_core_burst_0_upstream,
pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream => pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_0_upstream,
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream => pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream,
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register => pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register,
pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream => pcie_compiler_0_Rx_Interface_requests_unici_core_burst_0_upstream,
unici_core_burst_0_upstream_address => unici_core_burst_0_upstream_address,
unici_core_burst_0_upstream_burstcount => unici_core_burst_0_upstream_burstcount,
unici_core_burst_0_upstream_byteaddress => unici_core_burst_0_upstream_byteaddress,
unici_core_burst_0_upstream_byteenable => unici_core_burst_0_upstream_byteenable,
unici_core_burst_0_upstream_debugaccess => unici_core_burst_0_upstream_debugaccess,
unici_core_burst_0_upstream_read => unici_core_burst_0_upstream_read,
unici_core_burst_0_upstream_readdata_from_sa => unici_core_burst_0_upstream_readdata_from_sa,
unici_core_burst_0_upstream_waitrequest_from_sa => unici_core_burst_0_upstream_waitrequest_from_sa,
unici_core_burst_0_upstream_write => unici_core_burst_0_upstream_write,
unici_core_burst_0_upstream_writedata => unici_core_burst_0_upstream_writedata,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
pcie_compiler_0_Rx_Interface_address_to_slave => pcie_compiler_0_Rx_Interface_address_to_slave,
pcie_compiler_0_Rx_Interface_burstcount => pcie_compiler_0_Rx_Interface_burstcount,
pcie_compiler_0_Rx_Interface_byteenable => pcie_compiler_0_Rx_Interface_byteenable,
pcie_compiler_0_Rx_Interface_latency_counter => pcie_compiler_0_Rx_Interface_latency_counter,
pcie_compiler_0_Rx_Interface_read => pcie_compiler_0_Rx_Interface_read,
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register => pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register,
pcie_compiler_0_Rx_Interface_write => pcie_compiler_0_Rx_Interface_write,
pcie_compiler_0_Rx_Interface_writedata => pcie_compiler_0_Rx_Interface_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
unici_core_burst_0_upstream_readdata => unici_core_burst_0_upstream_readdata,
unici_core_burst_0_upstream_readdatavalid => unici_core_burst_0_upstream_readdatavalid,
unici_core_burst_0_upstream_waitrequest => unici_core_burst_0_upstream_waitrequest
);
--the_unici_core_burst_0_downstream, which is an e_instance
the_unici_core_burst_0_downstream : unici_core_burst_0_downstream_arbitrator
port map(
unici_core_burst_0_downstream_address_to_slave => unici_core_burst_0_downstream_address_to_slave,
unici_core_burst_0_downstream_latency_counter => unici_core_burst_0_downstream_latency_counter,
unici_core_burst_0_downstream_readdata => unici_core_burst_0_downstream_readdata,
unici_core_burst_0_downstream_readdatavalid => unici_core_burst_0_downstream_readdatavalid,
unici_core_burst_0_downstream_reset_n => unici_core_burst_0_downstream_reset_n,
unici_core_burst_0_downstream_waitrequest => unici_core_burst_0_downstream_waitrequest,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
d1_pipeline_bridge_0_s1_end_xfer => d1_pipeline_bridge_0_s1_end_xfer,
pipeline_bridge_0_s1_readdata_from_sa => pipeline_bridge_0_s1_readdata_from_sa,
pipeline_bridge_0_s1_waitrequest_from_sa => pipeline_bridge_0_s1_waitrequest_from_sa,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
unici_core_burst_0_downstream_address => unici_core_burst_0_downstream_address,
unici_core_burst_0_downstream_burstcount => unici_core_burst_0_downstream_burstcount,
unici_core_burst_0_downstream_byteenable => unici_core_burst_0_downstream_byteenable,
unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1 => unici_core_burst_0_downstream_granted_pipeline_bridge_0_s1,
unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1 => unici_core_burst_0_downstream_qualified_request_pipeline_bridge_0_s1,
unici_core_burst_0_downstream_read => unici_core_burst_0_downstream_read,
unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1 => unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1,
unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1_shift_register => unici_core_burst_0_downstream_read_data_valid_pipeline_bridge_0_s1_shift_register,
unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1 => unici_core_burst_0_downstream_requests_pipeline_bridge_0_s1,
unici_core_burst_0_downstream_write => unici_core_burst_0_downstream_write,
unici_core_burst_0_downstream_writedata => unici_core_burst_0_downstream_writedata
);
--the_unici_core_burst_0, which is an e_ptf_instance
the_unici_core_burst_0 : unici_core_burst_0
port map(
downstream_address => unici_core_burst_0_downstream_address,
downstream_arbitrationshare => unici_core_burst_0_downstream_arbitrationshare,
downstream_burstcount => unici_core_burst_0_downstream_burstcount,
downstream_byteenable => unici_core_burst_0_downstream_byteenable,
downstream_debugaccess => unici_core_burst_0_downstream_debugaccess,
downstream_nativeaddress => unici_core_burst_0_downstream_nativeaddress,
downstream_read => unici_core_burst_0_downstream_read,
downstream_write => unici_core_burst_0_downstream_write,
downstream_writedata => unici_core_burst_0_downstream_writedata,
upstream_readdata => unici_core_burst_0_upstream_readdata,
upstream_readdatavalid => unici_core_burst_0_upstream_readdatavalid,
upstream_waitrequest => unici_core_burst_0_upstream_waitrequest,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
downstream_readdata => unici_core_burst_0_downstream_readdata,
downstream_readdatavalid => unici_core_burst_0_downstream_readdatavalid,
downstream_waitrequest => unici_core_burst_0_downstream_waitrequest,
reset_n => unici_core_burst_0_downstream_reset_n,
upstream_address => unici_core_burst_0_upstream_byteaddress,
upstream_burstcount => unici_core_burst_0_upstream_burstcount,
upstream_byteenable => unici_core_burst_0_upstream_byteenable,
upstream_debugaccess => unici_core_burst_0_upstream_debugaccess,
upstream_nativeaddress => unici_core_burst_0_upstream_address,
upstream_read => unici_core_burst_0_upstream_read,
upstream_write => unici_core_burst_0_upstream_write,
upstream_writedata => unici_core_burst_0_upstream_writedata
);
--the_unici_core_burst_1_upstream, which is an e_instance
the_unici_core_burst_1_upstream : unici_core_burst_1_upstream_arbitrator
port map(
d1_unici_core_burst_1_upstream_end_xfer => d1_unici_core_burst_1_upstream_end_xfer,
pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream => pcie_compiler_0_Rx_Interface_granted_unici_core_burst_1_upstream,
pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream => pcie_compiler_0_Rx_Interface_qualified_request_unici_core_burst_1_upstream,
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream => pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream,
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register => pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_1_upstream_shift_register,
pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream => pcie_compiler_0_Rx_Interface_requests_unici_core_burst_1_upstream,
unici_core_burst_1_upstream_address => unici_core_burst_1_upstream_address,
unici_core_burst_1_upstream_burstcount => unici_core_burst_1_upstream_burstcount,
unici_core_burst_1_upstream_byteaddress => unici_core_burst_1_upstream_byteaddress,
unici_core_burst_1_upstream_byteenable => unici_core_burst_1_upstream_byteenable,
unici_core_burst_1_upstream_debugaccess => unici_core_burst_1_upstream_debugaccess,
unici_core_burst_1_upstream_read => unici_core_burst_1_upstream_read,
unici_core_burst_1_upstream_readdata_from_sa => unici_core_burst_1_upstream_readdata_from_sa,
unici_core_burst_1_upstream_waitrequest_from_sa => unici_core_burst_1_upstream_waitrequest_from_sa,
unici_core_burst_1_upstream_write => unici_core_burst_1_upstream_write,
unici_core_burst_1_upstream_writedata => unici_core_burst_1_upstream_writedata,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
pcie_compiler_0_Rx_Interface_address_to_slave => pcie_compiler_0_Rx_Interface_address_to_slave,
pcie_compiler_0_Rx_Interface_burstcount => pcie_compiler_0_Rx_Interface_burstcount,
pcie_compiler_0_Rx_Interface_byteenable => pcie_compiler_0_Rx_Interface_byteenable,
pcie_compiler_0_Rx_Interface_latency_counter => pcie_compiler_0_Rx_Interface_latency_counter,
pcie_compiler_0_Rx_Interface_read => pcie_compiler_0_Rx_Interface_read,
pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register => pcie_compiler_0_Rx_Interface_read_data_valid_unici_core_burst_0_upstream_shift_register,
pcie_compiler_0_Rx_Interface_write => pcie_compiler_0_Rx_Interface_write,
pcie_compiler_0_Rx_Interface_writedata => pcie_compiler_0_Rx_Interface_writedata,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
unici_core_burst_1_upstream_readdata => unici_core_burst_1_upstream_readdata,
unici_core_burst_1_upstream_readdatavalid => unici_core_burst_1_upstream_readdatavalid,
unici_core_burst_1_upstream_waitrequest => unici_core_burst_1_upstream_waitrequest
);
--the_unici_core_burst_1_downstream, which is an e_instance
the_unici_core_burst_1_downstream : unici_core_burst_1_downstream_arbitrator
port map(
unici_core_burst_1_downstream_address_to_slave => unici_core_burst_1_downstream_address_to_slave,
unici_core_burst_1_downstream_latency_counter => unici_core_burst_1_downstream_latency_counter,
unici_core_burst_1_downstream_readdata => unici_core_burst_1_downstream_readdata,
unici_core_burst_1_downstream_readdatavalid => unici_core_burst_1_downstream_readdatavalid,
unici_core_burst_1_downstream_reset_n => unici_core_burst_1_downstream_reset_n,
unici_core_burst_1_downstream_waitrequest => unici_core_burst_1_downstream_waitrequest,
avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa => avalon64_to_avalon8_0_avalon_slave_0_readdata_from_sa,
avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa => avalon64_to_avalon8_0_avalon_slave_0_waitrequest_from_sa,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer => d1_avalon64_to_avalon8_0_avalon_slave_0_end_xfer,
reset_n => pcie_compiler_0_pcie_core_clk_out_reset_n,
unici_core_burst_1_downstream_address => unici_core_burst_1_downstream_address,
unici_core_burst_1_downstream_burstcount => unici_core_burst_1_downstream_burstcount,
unici_core_burst_1_downstream_byteenable => unici_core_burst_1_downstream_byteenable,
unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0 => unici_core_burst_1_downstream_granted_avalon64_to_avalon8_0_avalon_slave_0,
unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0 => unici_core_burst_1_downstream_qualified_request_avalon64_to_avalon8_0_avalon_slave_0,
unici_core_burst_1_downstream_read => unici_core_burst_1_downstream_read,
unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0 => unici_core_burst_1_downstream_read_data_valid_avalon64_to_avalon8_0_avalon_slave_0,
unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0 => unici_core_burst_1_downstream_requests_avalon64_to_avalon8_0_avalon_slave_0,
unici_core_burst_1_downstream_write => unici_core_burst_1_downstream_write,
unici_core_burst_1_downstream_writedata => unici_core_burst_1_downstream_writedata
);
--the_unici_core_burst_1, which is an e_ptf_instance
the_unici_core_burst_1 : unici_core_burst_1
port map(
downstream_address => unici_core_burst_1_downstream_address,
downstream_arbitrationshare => unici_core_burst_1_downstream_arbitrationshare,
downstream_burstcount => unici_core_burst_1_downstream_burstcount,
downstream_byteenable => unici_core_burst_1_downstream_byteenable,
downstream_debugaccess => unici_core_burst_1_downstream_debugaccess,
downstream_nativeaddress => unici_core_burst_1_downstream_nativeaddress,
downstream_read => unici_core_burst_1_downstream_read,
downstream_write => unici_core_burst_1_downstream_write,
downstream_writedata => unici_core_burst_1_downstream_writedata,
upstream_readdata => unici_core_burst_1_upstream_readdata,
upstream_readdatavalid => unici_core_burst_1_upstream_readdatavalid,
upstream_waitrequest => unici_core_burst_1_upstream_waitrequest,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
downstream_readdata => unici_core_burst_1_downstream_readdata,
downstream_readdatavalid => unici_core_burst_1_downstream_readdatavalid,
downstream_waitrequest => unici_core_burst_1_downstream_waitrequest,
reset_n => unici_core_burst_1_downstream_reset_n,
upstream_address => unici_core_burst_1_upstream_byteaddress,
upstream_burstcount => unici_core_burst_1_upstream_burstcount,
upstream_byteenable => unici_core_burst_1_upstream_byteenable,
upstream_debugaccess => unici_core_burst_1_upstream_debugaccess,
upstream_nativeaddress => unici_core_burst_1_upstream_address,
upstream_read => unici_core_burst_1_upstream_read,
upstream_write => unici_core_burst_1_upstream_write,
upstream_writedata => unici_core_burst_1_upstream_writedata
);
--reset is asserted asynchronously and deasserted synchronously
unici_core_reset_pcie_compiler_0_pcie_core_clk_out_domain_synch : unici_core_reset_pcie_compiler_0_pcie_core_clk_out_domain_synch_module
port map(
data_out => pcie_compiler_0_pcie_core_clk_out_reset_n,
clk => internal_pcie_compiler_0_pcie_core_clk_out,
data_in => module_input15,
reset_n => reset_n_sources
);
module_input15 <= std_logic'('1');
--reset sources mux, which is an e_mux
reset_n_sources <= Vector_To_Std_Logic(NOT (((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT reset_n))) OR std_logic_vector'("00000000000000000000000000000000")) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pcie_compiler_0_Rx_Interface_resetrequest)))) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pcie_compiler_0_Rx_Interface_resetrequest)))) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pcie_compiler_0_Rx_Interface_resetrequest)))) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(pcie_compiler_0_Rx_Interface_resetrequest))))));
--pcie_compiler_0_Rx_Interface_irq of type irq does not connect to anything so wire it to default (0)
pcie_compiler_0_Rx_Interface_irq <= int_ctrl_0_avalon_slave_irq;
--pcie_compiler_0_Rx_Interface_irqnumber of type irqnumber does not connect to anything so wire it to default (0)
pcie_compiler_0_Rx_Interface_irqnumber <= std_logic_vector'("000000");
--pipeline_bridge_0_m1_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
pipeline_bridge_0_m1_endofpacket <= std_logic'('0');
--vhdl renameroo for output signals
cam0_bypass_from_the_ci_bridge_0 <= internal_cam0_bypass_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cam0_fail_from_the_ci_bridge_0 <= internal_cam0_fail_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cam0_ready_from_the_ci_bridge_0 <= internal_cam0_ready_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cam1_bypass_from_the_ci_bridge_0 <= internal_cam1_bypass_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cam1_fail_from_the_ci_bridge_0 <= internal_cam1_fail_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cam1_ready_from_the_ci_bridge_0 <= internal_cam1_ready_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cam_interrupts_from_the_ci_bridge_0 <= internal_cam_interrupts_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cam_mclki_from_the_dvb_ts_0 <= internal_cam_mclki_from_the_dvb_ts_0;
--vhdl renameroo for output signals
cam_mclki_from_the_dvb_ts_1 <= internal_cam_mclki_from_the_dvb_ts_1;
--vhdl renameroo for output signals
cam_mdi_from_the_dvb_ts_0 <= internal_cam_mdi_from_the_dvb_ts_0;
--vhdl renameroo for output signals
cam_mdi_from_the_dvb_ts_1 <= internal_cam_mdi_from_the_dvb_ts_1;
--vhdl renameroo for output signals
cam_mistrt_from_the_dvb_ts_0 <= internal_cam_mistrt_from_the_dvb_ts_0;
--vhdl renameroo for output signals
cam_mistrt_from_the_dvb_ts_1 <= internal_cam_mistrt_from_the_dvb_ts_1;
--vhdl renameroo for output signals
cam_mival_from_the_dvb_ts_0 <= internal_cam_mival_from_the_dvb_ts_0;
--vhdl renameroo for output signals
cam_mival_from_the_dvb_ts_1 <= internal_cam_mival_from_the_dvb_ts_1;
--vhdl renameroo for output signals
cam_readdata_from_the_ci_bridge_0 <= internal_cam_readdata_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cam_waitreq_from_the_ci_bridge_0 <= internal_cam_waitreq_from_the_ci_bridge_0;
--vhdl renameroo for output signals
ci_a_from_the_ci_bridge_0 <= internal_ci_a_from_the_ci_bridge_0;
--vhdl renameroo for output signals
ci_bus_dir_from_the_ci_bridge_0 <= internal_ci_bus_dir_from_the_ci_bridge_0;
--vhdl renameroo for output signals
ci_d_en_from_the_ci_bridge_0 <= internal_ci_d_en_from_the_ci_bridge_0;
--vhdl renameroo for output signals
ci_d_out_from_the_ci_bridge_0 <= internal_ci_d_out_from_the_ci_bridge_0;
--vhdl renameroo for output signals
ci_iord_n_from_the_ci_bridge_0 <= internal_ci_iord_n_from_the_ci_bridge_0;
--vhdl renameroo for output signals
ci_iowr_n_from_the_ci_bridge_0 <= internal_ci_iowr_n_from_the_ci_bridge_0;
--vhdl renameroo for output signals
ci_oe_n_from_the_ci_bridge_0 <= internal_ci_oe_n_from_the_ci_bridge_0;
--vhdl renameroo for output signals
ci_reg_n_from_the_ci_bridge_0 <= internal_ci_reg_n_from_the_ci_bridge_0;
--vhdl renameroo for output signals
ci_we_n_from_the_ci_bridge_0 <= internal_ci_we_n_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cia_ce_n_from_the_ci_bridge_0 <= internal_cia_ce_n_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cia_data_buf_oe_n_from_the_ci_bridge_0 <= internal_cia_data_buf_oe_n_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cia_reset_buf_oe_n_from_the_ci_bridge_0 <= internal_cia_reset_buf_oe_n_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cia_reset_from_the_ci_bridge_0 <= internal_cia_reset_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cib_ce_n_from_the_ci_bridge_0 <= internal_cib_ce_n_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cib_data_buf_oe_n_from_the_ci_bridge_0 <= internal_cib_data_buf_oe_n_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cib_reset_buf_oe_n_from_the_ci_bridge_0 <= internal_cib_reset_buf_oe_n_from_the_ci_bridge_0;
--vhdl renameroo for output signals
cib_reset_from_the_ci_bridge_0 <= internal_cib_reset_from_the_ci_bridge_0;
--vhdl renameroo for output signals
clk125_out_pcie_compiler_0 <= internal_clk125_out_pcie_compiler_0;
--vhdl renameroo for output signals
clk250_out_pcie_compiler_0 <= internal_clk250_out_pcie_compiler_0;
--vhdl renameroo for output signals
clk500_out_pcie_compiler_0 <= internal_clk500_out_pcie_compiler_0;
--vhdl renameroo for output signals
cs_n_from_the_spi_master_0 <= internal_cs_n_from_the_spi_master_0;
--vhdl renameroo for output signals
dma0_wait_from_the_dma_arbiter_0 <= internal_dma0_wait_from_the_dma_arbiter_0;
--vhdl renameroo for output signals
dma1_wait_from_the_dma_arbiter_0 <= internal_dma1_wait_from_the_dma_arbiter_0;
--vhdl renameroo for output signals
dvb_out_data_from_the_dvb_ts_0 <= internal_dvb_out_data_from_the_dvb_ts_0;
--vhdl renameroo for output signals
dvb_out_data_from_the_dvb_ts_1 <= internal_dvb_out_data_from_the_dvb_ts_1;
--vhdl renameroo for output signals
dvb_out_dsop_from_the_dvb_ts_0 <= internal_dvb_out_dsop_from_the_dvb_ts_0;
--vhdl renameroo for output signals
dvb_out_dsop_from_the_dvb_ts_1 <= internal_dvb_out_dsop_from_the_dvb_ts_1;
--vhdl renameroo for output signals
dvb_out_dval_from_the_dvb_ts_0 <= internal_dvb_out_dval_from_the_dvb_ts_0;
--vhdl renameroo for output signals
dvb_out_dval_from_the_dvb_ts_1 <= internal_dvb_out_dval_from_the_dvb_ts_1;
--vhdl renameroo for output signals
interrupt_from_the_ci_bridge_0 <= internal_interrupt_from_the_ci_bridge_0;
--vhdl renameroo for output signals
interrupt_from_the_dvb_dma_0 <= internal_interrupt_from_the_dvb_dma_0;
--vhdl renameroo for output signals
interrupt_from_the_dvb_dma_1 <= internal_interrupt_from_the_dvb_dma_1;
--vhdl renameroo for output signals
interrupt_from_the_dvb_ts_0 <= internal_interrupt_from_the_dvb_ts_0;
--vhdl renameroo for output signals
interrupt_from_the_dvb_ts_1 <= internal_interrupt_from_the_dvb_ts_1;
--vhdl renameroo for output signals
irq_from_the_fifo_in_8b_sync_0 <= internal_irq_from_the_fifo_in_8b_sync_0;
--vhdl renameroo for output signals
irq_from_the_fifo_in_8b_sync_1 <= internal_irq_from_the_fifo_in_8b_sync_1;
--vhdl renameroo for output signals
irq_from_the_fifo_out_8b_sync_0 <= internal_irq_from_the_fifo_out_8b_sync_0;
--vhdl renameroo for output signals
irq_from_the_fifo_out_8b_sync_1 <= internal_irq_from_the_fifo_out_8b_sync_1;
--vhdl renameroo for output signals
irq_from_the_spi_master_0 <= internal_irq_from_the_spi_master_0;
--vhdl renameroo for output signals
irq_from_the_twi_master_0 <= internal_irq_from_the_twi_master_0;
--vhdl renameroo for output signals
irq_from_the_twi_master_1 <= internal_irq_from_the_twi_master_1;
--vhdl renameroo for output signals
mem_addr_from_the_dvb_dma_0 <= internal_mem_addr_from_the_dvb_dma_0;
--vhdl renameroo for output signals
mem_addr_from_the_dvb_dma_1 <= internal_mem_addr_from_the_dvb_dma_1;
--vhdl renameroo for output signals
mem_byteen_from_the_dvb_dma_0 <= internal_mem_byteen_from_the_dvb_dma_0;
--vhdl renameroo for output signals
mem_byteen_from_the_dvb_dma_1 <= internal_mem_byteen_from_the_dvb_dma_1;
--vhdl renameroo for output signals
mem_size_from_the_dvb_dma_0 <= internal_mem_size_from_the_dvb_dma_0;
--vhdl renameroo for output signals
mem_size_from_the_dvb_dma_1 <= internal_mem_size_from_the_dvb_dma_1;
--vhdl renameroo for output signals
mem_wrdata_from_the_dvb_dma_0 <= internal_mem_wrdata_from_the_dvb_dma_0;
--vhdl renameroo for output signals
mem_wrdata_from_the_dvb_dma_1 <= internal_mem_wrdata_from_the_dvb_dma_1;
--vhdl renameroo for output signals
mem_write_from_the_dvb_dma_0 <= internal_mem_write_from_the_dvb_dma_0;
--vhdl renameroo for output signals
mem_write_from_the_dvb_dma_1 <= internal_mem_write_from_the_dvb_dma_1;
--vhdl renameroo for output signals
mosi_from_the_spi_master_0 <= internal_mosi_from_the_spi_master_0;
--vhdl renameroo for output signals
out_address_from_the_avalon64_to_avalon8_0 <= internal_out_address_from_the_avalon64_to_avalon8_0;
--vhdl renameroo for output signals
out_read_from_the_avalon64_to_avalon8_0 <= internal_out_read_from_the_avalon64_to_avalon8_0;
--vhdl renameroo for output signals
out_write_from_the_avalon64_to_avalon8_0 <= internal_out_write_from_the_avalon64_to_avalon8_0;
--vhdl renameroo for output signals
out_writedata_from_the_avalon64_to_avalon8_0 <= internal_out_writedata_from_the_avalon64_to_avalon8_0;
--vhdl renameroo for output signals
pcie_compiler_0_pcie_core_clk_out <= internal_pcie_compiler_0_pcie_core_clk_out;
--vhdl renameroo for output signals
pins_from_the_gpout_0 <= internal_pins_from_the_gpout_0;
--vhdl renameroo for output signals
powerdown_ext_pcie_compiler_0 <= internal_powerdown_ext_pcie_compiler_0;
--vhdl renameroo for output signals
rate_ext_pcie_compiler_0 <= internal_rate_ext_pcie_compiler_0;
--vhdl renameroo for output signals
reconfig_fromgxb_pcie_compiler_0 <= internal_reconfig_fromgxb_pcie_compiler_0;
--vhdl renameroo for output signals
rxpolarity0_ext_pcie_compiler_0 <= internal_rxpolarity0_ext_pcie_compiler_0;
--vhdl renameroo for output signals
scl_act_from_the_twi_master_0 <= internal_scl_act_from_the_twi_master_0;
--vhdl renameroo for output signals
scl_act_from_the_twi_master_1 <= internal_scl_act_from_the_twi_master_1;
--vhdl renameroo for output signals
sclk_from_the_spi_master_0 <= internal_sclk_from_the_spi_master_0;
--vhdl renameroo for output signals
sda_act_from_the_twi_master_0 <= internal_sda_act_from_the_twi_master_0;
--vhdl renameroo for output signals
sda_act_from_the_twi_master_1 <= internal_sda_act_from_the_twi_master_1;
--vhdl renameroo for output signals
tx_out0_pcie_compiler_0 <= internal_tx_out0_pcie_compiler_0;
--vhdl renameroo for output signals
txcompl0_ext_pcie_compiler_0 <= internal_txcompl0_ext_pcie_compiler_0;
--vhdl renameroo for output signals
txdata0_ext_pcie_compiler_0 <= internal_txdata0_ext_pcie_compiler_0;
--vhdl renameroo for output signals
txdatak0_ext_pcie_compiler_0 <= internal_txdatak0_ext_pcie_compiler_0;
--vhdl renameroo for output signals
txdetectrx_ext_pcie_compiler_0 <= internal_txdetectrx_ext_pcie_compiler_0;
--vhdl renameroo for output signals
txelecidle0_ext_pcie_compiler_0 <= internal_txelecidle0_ext_pcie_compiler_0;
end europa;
--synthesis translate_off
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
--add your libraries here
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>
entity test_bench is
end entity test_bench;
architecture europa of test_bench is
component unici_core is
port (
-- 1) global signals:
signal pcie_compiler_0_pcie_core_clk_out : OUT STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- the_avalon64_to_avalon8_0
signal out_address_from_the_avalon64_to_avalon8_0 : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
signal out_read_from_the_avalon64_to_avalon8_0 : OUT STD_LOGIC;
signal out_readdata_to_the_avalon64_to_avalon8_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal out_waitrequest_to_the_avalon64_to_avalon8_0 : IN STD_LOGIC;
signal out_write_from_the_avalon64_to_avalon8_0 : OUT STD_LOGIC;
signal out_writedata_from_the_avalon64_to_avalon8_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-- the_ci_bridge_0
signal cam0_bypass_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam0_fail_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam0_ready_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam1_bypass_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam1_fail_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam1_ready_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam_address_to_the_ci_bridge_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
signal cam_interrupts_from_the_ci_bridge_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cam_read_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cam_readdata_from_the_ci_bridge_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_waitreq_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cam_write_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cam_writedata_to_the_ci_bridge_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ci_a_from_the_ci_bridge_0 : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal ci_bus_dir_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_d_en_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_d_in_to_the_ci_bridge_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ci_d_out_from_the_ci_bridge_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ci_iord_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_iowr_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_oe_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_reg_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal ci_we_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cia_cd_n_to_the_ci_bridge_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cia_ce_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cia_data_buf_oe_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cia_ireq_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cia_overcurrent_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cia_reset_buf_oe_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cia_reset_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cia_wait_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cib_cd_n_to_the_ci_bridge_0 : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cib_ce_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cib_data_buf_oe_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cib_ireq_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cib_overcurrent_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal cib_reset_buf_oe_n_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cib_reset_from_the_ci_bridge_0 : OUT STD_LOGIC;
signal cib_wait_n_to_the_ci_bridge_0 : IN STD_LOGIC;
signal interrupt_from_the_ci_bridge_0 : OUT STD_LOGIC;
-- the_dma_arbiter_0
signal dma0_addr_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (60 DOWNTO 0);
signal dma0_byteen_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma0_size_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma0_wait_from_the_dma_arbiter_0 : OUT STD_LOGIC;
signal dma0_wrdata_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal dma0_write_to_the_dma_arbiter_0 : IN STD_LOGIC;
signal dma1_addr_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (60 DOWNTO 0);
signal dma1_byteen_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma1_size_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma1_wait_from_the_dma_arbiter_0 : OUT STD_LOGIC;
signal dma1_wrdata_to_the_dma_arbiter_0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal dma1_write_to_the_dma_arbiter_0 : IN STD_LOGIC;
-- the_dvb_dma_0
signal dvb_data_to_the_dvb_dma_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_dval_to_the_dvb_dma_0 : IN STD_LOGIC;
signal dvb_sop_to_the_dvb_dma_0 : IN STD_LOGIC;
signal interrupt_from_the_dvb_dma_0 : OUT STD_LOGIC;
signal mem_addr_from_the_dvb_dma_0 : OUT STD_LOGIC_VECTOR (60 DOWNTO 0);
signal mem_byteen_from_the_dvb_dma_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_size_from_the_dvb_dma_0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
signal mem_waitreq_to_the_dvb_dma_0 : IN STD_LOGIC;
signal mem_wrdata_from_the_dvb_dma_0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal mem_write_from_the_dvb_dma_0 : OUT STD_LOGIC;
-- the_dvb_dma_1
signal dvb_data_to_the_dvb_dma_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_dval_to_the_dvb_dma_1 : IN STD_LOGIC;
signal dvb_sop_to_the_dvb_dma_1 : IN STD_LOGIC;
signal interrupt_from_the_dvb_dma_1 : OUT STD_LOGIC;
signal mem_addr_from_the_dvb_dma_1 : OUT STD_LOGIC_VECTOR (60 DOWNTO 0);
signal mem_byteen_from_the_dvb_dma_1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_size_from_the_dvb_dma_1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
signal mem_waitreq_to_the_dvb_dma_1 : IN STD_LOGIC;
signal mem_wrdata_from_the_dvb_dma_1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal mem_write_from_the_dvb_dma_1 : OUT STD_LOGIC;
-- the_dvb_ts_0
signal cam_baseclk_to_the_dvb_ts_0 : IN STD_LOGIC;
signal cam_bypass_to_the_dvb_ts_0 : IN STD_LOGIC;
signal cam_mclki_from_the_dvb_ts_0 : OUT STD_LOGIC;
signal cam_mclko_to_the_dvb_ts_0 : IN STD_LOGIC;
signal cam_mdi_from_the_dvb_ts_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mdo_to_the_dvb_ts_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mistrt_from_the_dvb_ts_0 : OUT STD_LOGIC;
signal cam_mival_from_the_dvb_ts_0 : OUT STD_LOGIC;
signal cam_mostrt_to_the_dvb_ts_0 : IN STD_LOGIC;
signal cam_moval_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in0_data_to_the_dvb_ts_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in0_dsop_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in0_dval_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in1_data_to_the_dvb_ts_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in1_dsop_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in1_dval_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in2_data_to_the_dvb_ts_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in2_dsop_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_in2_dval_to_the_dvb_ts_0 : IN STD_LOGIC;
signal dvb_out_data_from_the_dvb_ts_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_out_dsop_from_the_dvb_ts_0 : OUT STD_LOGIC;
signal dvb_out_dval_from_the_dvb_ts_0 : OUT STD_LOGIC;
signal interrupt_from_the_dvb_ts_0 : OUT STD_LOGIC;
-- the_dvb_ts_1
signal cam_baseclk_to_the_dvb_ts_1 : IN STD_LOGIC;
signal cam_bypass_to_the_dvb_ts_1 : IN STD_LOGIC;
signal cam_mclki_from_the_dvb_ts_1 : OUT STD_LOGIC;
signal cam_mclko_to_the_dvb_ts_1 : IN STD_LOGIC;
signal cam_mdi_from_the_dvb_ts_1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mdo_to_the_dvb_ts_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mistrt_from_the_dvb_ts_1 : OUT STD_LOGIC;
signal cam_mival_from_the_dvb_ts_1 : OUT STD_LOGIC;
signal cam_mostrt_to_the_dvb_ts_1 : IN STD_LOGIC;
signal cam_moval_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in0_data_to_the_dvb_ts_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in0_dsop_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in0_dval_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in1_data_to_the_dvb_ts_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in1_dsop_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in1_dval_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in2_data_to_the_dvb_ts_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in2_dsop_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_in2_dval_to_the_dvb_ts_1 : IN STD_LOGIC;
signal dvb_out_data_from_the_dvb_ts_1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_out_dsop_from_the_dvb_ts_1 : OUT STD_LOGIC;
signal dvb_out_dval_from_the_dvb_ts_1 : OUT STD_LOGIC;
signal interrupt_from_the_dvb_ts_1 : OUT STD_LOGIC;
-- the_fifo_in_8b_sync_0
signal irq_from_the_fifo_in_8b_sync_0 : OUT STD_LOGIC;
-- the_fifo_in_8b_sync_1
signal irq_from_the_fifo_in_8b_sync_1 : OUT STD_LOGIC;
-- the_fifo_out_8b_sync_0
signal irq_from_the_fifo_out_8b_sync_0 : OUT STD_LOGIC;
-- the_fifo_out_8b_sync_1
signal irq_from_the_fifo_out_8b_sync_1 : OUT STD_LOGIC;
-- the_gpout_0
signal pins_from_the_gpout_0 : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
-- the_int_ctrl_0
signal avlm_irq_to_the_int_ctrl_0 : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- the_pcie_compiler_0
signal busy_altgxb_reconfig_pcie_compiler_0 : IN STD_LOGIC;
signal clk125_out_pcie_compiler_0 : OUT STD_LOGIC;
signal clk250_out_pcie_compiler_0 : OUT STD_LOGIC;
signal clk500_out_pcie_compiler_0 : OUT STD_LOGIC;
signal fixedclk_serdes_pcie_compiler_0 : IN STD_LOGIC;
signal gxb_powerdown_pcie_compiler_0 : IN STD_LOGIC;
signal pcie_rstn_pcie_compiler_0 : IN STD_LOGIC;
signal phystatus_ext_pcie_compiler_0 : IN STD_LOGIC;
signal pipe_mode_pcie_compiler_0 : IN STD_LOGIC;
signal pll_powerdown_pcie_compiler_0 : IN STD_LOGIC;
signal powerdown_ext_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rate_ext_pcie_compiler_0 : OUT STD_LOGIC;
signal reconfig_clk_pcie_compiler_0 : IN STD_LOGIC;
signal reconfig_fromgxb_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reconfig_togxb_pcie_compiler_0 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk_pcie_compiler_0 : IN STD_LOGIC;
signal rx_in0_pcie_compiler_0 : IN STD_LOGIC;
signal rxdata0_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext_pcie_compiler_0 : IN STD_LOGIC;
signal rxelecidle0_ext_pcie_compiler_0 : IN STD_LOGIC;
signal rxpolarity0_ext_pcie_compiler_0 : OUT STD_LOGIC;
signal rxstatus0_ext_pcie_compiler_0 : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext_pcie_compiler_0 : IN STD_LOGIC;
signal test_in_pcie_compiler_0 : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal tx_out0_pcie_compiler_0 : OUT STD_LOGIC;
signal txcompl0_ext_pcie_compiler_0 : OUT STD_LOGIC;
signal txdata0_ext_pcie_compiler_0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext_pcie_compiler_0 : OUT STD_LOGIC;
signal txdetectrx_ext_pcie_compiler_0 : OUT STD_LOGIC;
signal txelecidle0_ext_pcie_compiler_0 : OUT STD_LOGIC;
-- the_spi_master_0
signal cs_n_from_the_spi_master_0 : OUT STD_LOGIC;
signal irq_from_the_spi_master_0 : OUT STD_LOGIC;
signal miso_to_the_spi_master_0 : IN STD_LOGIC;
signal mosi_from_the_spi_master_0 : OUT STD_LOGIC;
signal sclk_from_the_spi_master_0 : OUT STD_LOGIC;
-- the_twi_master_0
signal irq_from_the_twi_master_0 : OUT STD_LOGIC;
signal scl_act_from_the_twi_master_0 : OUT STD_LOGIC;
signal scl_in_to_the_twi_master_0 : IN STD_LOGIC;
signal sda_act_from_the_twi_master_0 : OUT STD_LOGIC;
signal sda_in_to_the_twi_master_0 : IN STD_LOGIC;
signal sink_irq_to_the_twi_master_0 : IN STD_LOGIC;
signal source_irq_to_the_twi_master_0 : IN STD_LOGIC;
-- the_twi_master_1
signal irq_from_the_twi_master_1 : OUT STD_LOGIC;
signal scl_act_from_the_twi_master_1 : OUT STD_LOGIC;
signal scl_in_to_the_twi_master_1 : IN STD_LOGIC;
signal sda_act_from_the_twi_master_1 : OUT STD_LOGIC;
signal sda_in_to_the_twi_master_1 : IN STD_LOGIC;
signal sink_irq_to_the_twi_master_1 : IN STD_LOGIC;
signal source_irq_to_the_twi_master_1 : IN STD_LOGIC
);
end component unici_core;
component pcie_compiler_0_testbench is
port (
-- inputs:
signal clk125_out : IN STD_LOGIC;
signal clk250_out : IN STD_LOGIC;
signal clk500_out : IN STD_LOGIC;
signal powerdown_ext : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rate_ext : IN STD_LOGIC;
signal reconfig_fromgxb : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal rxpolarity0_ext : IN STD_LOGIC;
signal tx_out0 : IN STD_LOGIC;
signal txcompl0_ext : IN STD_LOGIC;
signal txdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext : IN STD_LOGIC;
signal txdetectrx_ext : IN STD_LOGIC;
signal txelecidle0_ext : IN STD_LOGIC;
-- outputs:
signal busy_altgxb_reconfig : OUT STD_LOGIC;
signal fixedclk_serdes : OUT STD_LOGIC;
signal gxb_powerdown : OUT STD_LOGIC;
signal pcie_rstn : OUT STD_LOGIC;
signal phystatus_ext : OUT STD_LOGIC;
signal pipe_mode : OUT STD_LOGIC;
signal pll_powerdown : OUT STD_LOGIC;
signal reconfig_clk : OUT STD_LOGIC;
signal reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk : OUT STD_LOGIC;
signal rx_in0 : OUT STD_LOGIC;
signal rxdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext : OUT STD_LOGIC;
signal rxelecidle0_ext : OUT STD_LOGIC;
signal rxstatus0_ext : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext : OUT STD_LOGIC;
signal test_in : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
end component pcie_compiler_0_testbench;
signal avlm_irq_to_the_int_ctrl_0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal busy_altgxb_reconfig_pcie_compiler_0 : STD_LOGIC;
signal cam0_bypass_from_the_ci_bridge_0 : STD_LOGIC;
signal cam0_fail_from_the_ci_bridge_0 : STD_LOGIC;
signal cam0_ready_from_the_ci_bridge_0 : STD_LOGIC;
signal cam1_bypass_from_the_ci_bridge_0 : STD_LOGIC;
signal cam1_fail_from_the_ci_bridge_0 : STD_LOGIC;
signal cam1_ready_from_the_ci_bridge_0 : STD_LOGIC;
signal cam_address_to_the_ci_bridge_0 : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal cam_baseclk_to_the_dvb_ts_0 : STD_LOGIC;
signal cam_baseclk_to_the_dvb_ts_1 : STD_LOGIC;
signal cam_bypass_to_the_dvb_ts_0 : STD_LOGIC;
signal cam_bypass_to_the_dvb_ts_1 : STD_LOGIC;
signal cam_interrupts_from_the_ci_bridge_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cam_mclki_from_the_dvb_ts_0 : STD_LOGIC;
signal cam_mclki_from_the_dvb_ts_1 : STD_LOGIC;
signal cam_mclko_to_the_dvb_ts_0 : STD_LOGIC;
signal cam_mclko_to_the_dvb_ts_1 : STD_LOGIC;
signal cam_mdi_from_the_dvb_ts_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mdi_from_the_dvb_ts_1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mdo_to_the_dvb_ts_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mdo_to_the_dvb_ts_1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_mistrt_from_the_dvb_ts_0 : STD_LOGIC;
signal cam_mistrt_from_the_dvb_ts_1 : STD_LOGIC;
signal cam_mival_from_the_dvb_ts_0 : STD_LOGIC;
signal cam_mival_from_the_dvb_ts_1 : STD_LOGIC;
signal cam_mostrt_to_the_dvb_ts_0 : STD_LOGIC;
signal cam_mostrt_to_the_dvb_ts_1 : STD_LOGIC;
signal cam_moval_to_the_dvb_ts_0 : STD_LOGIC;
signal cam_moval_to_the_dvb_ts_1 : STD_LOGIC;
signal cam_read_to_the_ci_bridge_0 : STD_LOGIC;
signal cam_readdata_from_the_ci_bridge_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal cam_waitreq_from_the_ci_bridge_0 : STD_LOGIC;
signal cam_write_to_the_ci_bridge_0 : STD_LOGIC;
signal cam_writedata_to_the_ci_bridge_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ci_a_from_the_ci_bridge_0 : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal ci_bus_dir_from_the_ci_bridge_0 : STD_LOGIC;
signal ci_d_en_from_the_ci_bridge_0 : STD_LOGIC;
signal ci_d_in_to_the_ci_bridge_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ci_d_out_from_the_ci_bridge_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ci_iord_n_from_the_ci_bridge_0 : STD_LOGIC;
signal ci_iowr_n_from_the_ci_bridge_0 : STD_LOGIC;
signal ci_oe_n_from_the_ci_bridge_0 : STD_LOGIC;
signal ci_reg_n_from_the_ci_bridge_0 : STD_LOGIC;
signal ci_we_n_from_the_ci_bridge_0 : STD_LOGIC;
signal cia_cd_n_to_the_ci_bridge_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cia_ce_n_from_the_ci_bridge_0 : STD_LOGIC;
signal cia_data_buf_oe_n_from_the_ci_bridge_0 : STD_LOGIC;
signal cia_ireq_n_to_the_ci_bridge_0 : STD_LOGIC;
signal cia_overcurrent_n_to_the_ci_bridge_0 : STD_LOGIC;
signal cia_reset_buf_oe_n_from_the_ci_bridge_0 : STD_LOGIC;
signal cia_reset_from_the_ci_bridge_0 : STD_LOGIC;
signal cia_wait_n_to_the_ci_bridge_0 : STD_LOGIC;
signal cib_cd_n_to_the_ci_bridge_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cib_ce_n_from_the_ci_bridge_0 : STD_LOGIC;
signal cib_data_buf_oe_n_from_the_ci_bridge_0 : STD_LOGIC;
signal cib_ireq_n_to_the_ci_bridge_0 : STD_LOGIC;
signal cib_overcurrent_n_to_the_ci_bridge_0 : STD_LOGIC;
signal cib_reset_buf_oe_n_from_the_ci_bridge_0 : STD_LOGIC;
signal cib_reset_from_the_ci_bridge_0 : STD_LOGIC;
signal cib_wait_n_to_the_ci_bridge_0 : STD_LOGIC;
signal clk : STD_LOGIC;
signal clk125_out_pcie_compiler_0 : STD_LOGIC;
signal clk250_out_pcie_compiler_0 : STD_LOGIC;
signal clk500_out_pcie_compiler_0 : STD_LOGIC;
signal cs_n_from_the_spi_master_0 : STD_LOGIC;
signal dma0_addr_to_the_dma_arbiter_0 : STD_LOGIC_VECTOR (60 DOWNTO 0);
signal dma0_byteen_to_the_dma_arbiter_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma0_size_to_the_dma_arbiter_0 : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma0_wait_from_the_dma_arbiter_0 : STD_LOGIC;
signal dma0_wrdata_to_the_dma_arbiter_0 : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal dma0_write_to_the_dma_arbiter_0 : STD_LOGIC;
signal dma1_addr_to_the_dma_arbiter_0 : STD_LOGIC_VECTOR (60 DOWNTO 0);
signal dma1_byteen_to_the_dma_arbiter_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dma1_size_to_the_dma_arbiter_0 : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal dma1_wait_from_the_dma_arbiter_0 : STD_LOGIC;
signal dma1_wrdata_to_the_dma_arbiter_0 : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal dma1_write_to_the_dma_arbiter_0 : STD_LOGIC;
signal dvb_data_to_the_dvb_dma_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_data_to_the_dvb_dma_1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_dval_to_the_dvb_dma_0 : STD_LOGIC;
signal dvb_dval_to_the_dvb_dma_1 : STD_LOGIC;
signal dvb_in0_data_to_the_dvb_ts_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in0_data_to_the_dvb_ts_1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in0_dsop_to_the_dvb_ts_0 : STD_LOGIC;
signal dvb_in0_dsop_to_the_dvb_ts_1 : STD_LOGIC;
signal dvb_in0_dval_to_the_dvb_ts_0 : STD_LOGIC;
signal dvb_in0_dval_to_the_dvb_ts_1 : STD_LOGIC;
signal dvb_in1_data_to_the_dvb_ts_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in1_data_to_the_dvb_ts_1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in1_dsop_to_the_dvb_ts_0 : STD_LOGIC;
signal dvb_in1_dsop_to_the_dvb_ts_1 : STD_LOGIC;
signal dvb_in1_dval_to_the_dvb_ts_0 : STD_LOGIC;
signal dvb_in1_dval_to_the_dvb_ts_1 : STD_LOGIC;
signal dvb_in2_data_to_the_dvb_ts_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in2_data_to_the_dvb_ts_1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_in2_dsop_to_the_dvb_ts_0 : STD_LOGIC;
signal dvb_in2_dsop_to_the_dvb_ts_1 : STD_LOGIC;
signal dvb_in2_dval_to_the_dvb_ts_0 : STD_LOGIC;
signal dvb_in2_dval_to_the_dvb_ts_1 : STD_LOGIC;
signal dvb_out_data_from_the_dvb_ts_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_out_data_from_the_dvb_ts_1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dvb_out_dsop_from_the_dvb_ts_0 : STD_LOGIC;
signal dvb_out_dsop_from_the_dvb_ts_1 : STD_LOGIC;
signal dvb_out_dval_from_the_dvb_ts_0 : STD_LOGIC;
signal dvb_out_dval_from_the_dvb_ts_1 : STD_LOGIC;
signal dvb_sop_to_the_dvb_dma_0 : STD_LOGIC;
signal dvb_sop_to_the_dvb_dma_1 : STD_LOGIC;
signal fixedclk_serdes_pcie_compiler_0 : STD_LOGIC;
signal gxb_powerdown_pcie_compiler_0 : STD_LOGIC;
signal int_ctrl_0_avalon_slave_irq : STD_LOGIC;
signal interrupt_from_the_ci_bridge_0 : STD_LOGIC;
signal interrupt_from_the_dvb_dma_0 : STD_LOGIC;
signal interrupt_from_the_dvb_dma_1 : STD_LOGIC;
signal interrupt_from_the_dvb_ts_0 : STD_LOGIC;
signal interrupt_from_the_dvb_ts_1 : STD_LOGIC;
signal irq_from_the_fifo_in_8b_sync_0 : STD_LOGIC;
signal irq_from_the_fifo_in_8b_sync_1 : STD_LOGIC;
signal irq_from_the_fifo_out_8b_sync_0 : STD_LOGIC;
signal irq_from_the_fifo_out_8b_sync_1 : STD_LOGIC;
signal irq_from_the_spi_master_0 : STD_LOGIC;
signal irq_from_the_twi_master_0 : STD_LOGIC;
signal irq_from_the_twi_master_1 : STD_LOGIC;
signal mem_addr_from_the_dvb_dma_0 : STD_LOGIC_VECTOR (60 DOWNTO 0);
signal mem_addr_from_the_dvb_dma_1 : STD_LOGIC_VECTOR (60 DOWNTO 0);
signal mem_byteen_from_the_dvb_dma_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_byteen_from_the_dvb_dma_1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal mem_size_from_the_dvb_dma_0 : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal mem_size_from_the_dvb_dma_1 : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal mem_waitreq_to_the_dvb_dma_0 : STD_LOGIC;
signal mem_waitreq_to_the_dvb_dma_1 : STD_LOGIC;
signal mem_wrdata_from_the_dvb_dma_0 : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal mem_wrdata_from_the_dvb_dma_1 : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal mem_write_from_the_dvb_dma_0 : STD_LOGIC;
signal mem_write_from_the_dvb_dma_1 : STD_LOGIC;
signal miso_to_the_spi_master_0 : STD_LOGIC;
signal mosi_from_the_spi_master_0 : STD_LOGIC;
signal out_address_from_the_avalon64_to_avalon8_0 : STD_LOGIC_VECTOR (17 DOWNTO 0);
signal out_read_from_the_avalon64_to_avalon8_0 : STD_LOGIC;
signal out_readdata_to_the_avalon64_to_avalon8_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal out_waitrequest_to_the_avalon64_to_avalon8_0 : STD_LOGIC;
signal out_write_from_the_avalon64_to_avalon8_0 : STD_LOGIC;
signal out_writedata_from_the_avalon64_to_avalon8_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal pcie_compiler_0_Control_Register_Access_irq : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_irq : STD_LOGIC;
signal pcie_compiler_0_Rx_Interface_irqnumber : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_readdata_from_sa : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal pcie_compiler_0_Tx_Interface_readdatavalid_from_sa : STD_LOGIC;
signal pcie_compiler_0_pcie_core_clk_out : STD_LOGIC;
signal pcie_rstn_pcie_compiler_0 : STD_LOGIC;
signal phystatus_ext_pcie_compiler_0 : STD_LOGIC;
signal pins_from_the_gpout_0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal pipe_mode_pcie_compiler_0 : STD_LOGIC;
signal pipeline_bridge_0_m1_debugaccess : STD_LOGIC;
signal pipeline_bridge_0_m1_endofpacket : STD_LOGIC;
signal pipeline_bridge_0_s1_endofpacket_from_sa : STD_LOGIC;
signal pll_powerdown_pcie_compiler_0 : STD_LOGIC;
signal powerdown_ext_pcie_compiler_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rate_ext_pcie_compiler_0 : STD_LOGIC;
signal reconfig_clk_pcie_compiler_0 : STD_LOGIC;
signal reconfig_fromgxb_pcie_compiler_0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reconfig_togxb_pcie_compiler_0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk_pcie_compiler_0 : STD_LOGIC;
signal reset_n : STD_LOGIC;
signal rx_in0_pcie_compiler_0 : STD_LOGIC;
signal rxdata0_ext_pcie_compiler_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext_pcie_compiler_0 : STD_LOGIC;
signal rxelecidle0_ext_pcie_compiler_0 : STD_LOGIC;
signal rxpolarity0_ext_pcie_compiler_0 : STD_LOGIC;
signal rxstatus0_ext_pcie_compiler_0 : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext_pcie_compiler_0 : STD_LOGIC;
signal scl_act_from_the_twi_master_0 : STD_LOGIC;
signal scl_act_from_the_twi_master_1 : STD_LOGIC;
signal scl_in_to_the_twi_master_0 : STD_LOGIC;
signal scl_in_to_the_twi_master_1 : STD_LOGIC;
signal sclk_from_the_spi_master_0 : STD_LOGIC;
signal sda_act_from_the_twi_master_0 : STD_LOGIC;
signal sda_act_from_the_twi_master_1 : STD_LOGIC;
signal sda_in_to_the_twi_master_0 : STD_LOGIC;
signal sda_in_to_the_twi_master_1 : STD_LOGIC;
signal sink_irq_to_the_twi_master_0 : STD_LOGIC;
signal sink_irq_to_the_twi_master_1 : STD_LOGIC;
signal source_irq_to_the_twi_master_0 : STD_LOGIC;
signal source_irq_to_the_twi_master_1 : STD_LOGIC;
signal test_in_pcie_compiler_0 : STD_LOGIC_VECTOR (39 DOWNTO 0);
signal tx_out0_pcie_compiler_0 : STD_LOGIC;
signal txcompl0_ext_pcie_compiler_0 : STD_LOGIC;
signal txdata0_ext_pcie_compiler_0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext_pcie_compiler_0 : STD_LOGIC;
signal txdetectrx_ext_pcie_compiler_0 : STD_LOGIC;
signal txelecidle0_ext_pcie_compiler_0 : STD_LOGIC;
signal unici_core_burst_1_downstream_debugaccess : STD_LOGIC;
signal unici_core_burst_1_downstream_nativeaddress : STD_LOGIC_VECTOR (17 DOWNTO 0);
-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
--add your component and signal declaration here
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>
begin
--Set us up the Dut
DUT : unici_core
port map(
cam0_bypass_from_the_ci_bridge_0 => cam0_bypass_from_the_ci_bridge_0,
cam0_fail_from_the_ci_bridge_0 => cam0_fail_from_the_ci_bridge_0,
cam0_ready_from_the_ci_bridge_0 => cam0_ready_from_the_ci_bridge_0,
cam1_bypass_from_the_ci_bridge_0 => cam1_bypass_from_the_ci_bridge_0,
cam1_fail_from_the_ci_bridge_0 => cam1_fail_from_the_ci_bridge_0,
cam1_ready_from_the_ci_bridge_0 => cam1_ready_from_the_ci_bridge_0,
cam_interrupts_from_the_ci_bridge_0 => cam_interrupts_from_the_ci_bridge_0,
cam_mclki_from_the_dvb_ts_0 => cam_mclki_from_the_dvb_ts_0,
cam_mclki_from_the_dvb_ts_1 => cam_mclki_from_the_dvb_ts_1,
cam_mdi_from_the_dvb_ts_0 => cam_mdi_from_the_dvb_ts_0,
cam_mdi_from_the_dvb_ts_1 => cam_mdi_from_the_dvb_ts_1,
cam_mistrt_from_the_dvb_ts_0 => cam_mistrt_from_the_dvb_ts_0,
cam_mistrt_from_the_dvb_ts_1 => cam_mistrt_from_the_dvb_ts_1,
cam_mival_from_the_dvb_ts_0 => cam_mival_from_the_dvb_ts_0,
cam_mival_from_the_dvb_ts_1 => cam_mival_from_the_dvb_ts_1,
cam_readdata_from_the_ci_bridge_0 => cam_readdata_from_the_ci_bridge_0,
cam_waitreq_from_the_ci_bridge_0 => cam_waitreq_from_the_ci_bridge_0,
ci_a_from_the_ci_bridge_0 => ci_a_from_the_ci_bridge_0,
ci_bus_dir_from_the_ci_bridge_0 => ci_bus_dir_from_the_ci_bridge_0,
ci_d_en_from_the_ci_bridge_0 => ci_d_en_from_the_ci_bridge_0,
ci_d_out_from_the_ci_bridge_0 => ci_d_out_from_the_ci_bridge_0,
ci_iord_n_from_the_ci_bridge_0 => ci_iord_n_from_the_ci_bridge_0,
ci_iowr_n_from_the_ci_bridge_0 => ci_iowr_n_from_the_ci_bridge_0,
ci_oe_n_from_the_ci_bridge_0 => ci_oe_n_from_the_ci_bridge_0,
ci_reg_n_from_the_ci_bridge_0 => ci_reg_n_from_the_ci_bridge_0,
ci_we_n_from_the_ci_bridge_0 => ci_we_n_from_the_ci_bridge_0,
cia_ce_n_from_the_ci_bridge_0 => cia_ce_n_from_the_ci_bridge_0,
cia_data_buf_oe_n_from_the_ci_bridge_0 => cia_data_buf_oe_n_from_the_ci_bridge_0,
cia_reset_buf_oe_n_from_the_ci_bridge_0 => cia_reset_buf_oe_n_from_the_ci_bridge_0,
cia_reset_from_the_ci_bridge_0 => cia_reset_from_the_ci_bridge_0,
cib_ce_n_from_the_ci_bridge_0 => cib_ce_n_from_the_ci_bridge_0,
cib_data_buf_oe_n_from_the_ci_bridge_0 => cib_data_buf_oe_n_from_the_ci_bridge_0,
cib_reset_buf_oe_n_from_the_ci_bridge_0 => cib_reset_buf_oe_n_from_the_ci_bridge_0,
cib_reset_from_the_ci_bridge_0 => cib_reset_from_the_ci_bridge_0,
clk125_out_pcie_compiler_0 => clk125_out_pcie_compiler_0,
clk250_out_pcie_compiler_0 => clk250_out_pcie_compiler_0,
clk500_out_pcie_compiler_0 => clk500_out_pcie_compiler_0,
cs_n_from_the_spi_master_0 => cs_n_from_the_spi_master_0,
dma0_wait_from_the_dma_arbiter_0 => dma0_wait_from_the_dma_arbiter_0,
dma1_wait_from_the_dma_arbiter_0 => dma1_wait_from_the_dma_arbiter_0,
dvb_out_data_from_the_dvb_ts_0 => dvb_out_data_from_the_dvb_ts_0,
dvb_out_data_from_the_dvb_ts_1 => dvb_out_data_from_the_dvb_ts_1,
dvb_out_dsop_from_the_dvb_ts_0 => dvb_out_dsop_from_the_dvb_ts_0,
dvb_out_dsop_from_the_dvb_ts_1 => dvb_out_dsop_from_the_dvb_ts_1,
dvb_out_dval_from_the_dvb_ts_0 => dvb_out_dval_from_the_dvb_ts_0,
dvb_out_dval_from_the_dvb_ts_1 => dvb_out_dval_from_the_dvb_ts_1,
interrupt_from_the_ci_bridge_0 => interrupt_from_the_ci_bridge_0,
interrupt_from_the_dvb_dma_0 => interrupt_from_the_dvb_dma_0,
interrupt_from_the_dvb_dma_1 => interrupt_from_the_dvb_dma_1,
interrupt_from_the_dvb_ts_0 => interrupt_from_the_dvb_ts_0,
interrupt_from_the_dvb_ts_1 => interrupt_from_the_dvb_ts_1,
irq_from_the_fifo_in_8b_sync_0 => irq_from_the_fifo_in_8b_sync_0,
irq_from_the_fifo_in_8b_sync_1 => irq_from_the_fifo_in_8b_sync_1,
irq_from_the_fifo_out_8b_sync_0 => irq_from_the_fifo_out_8b_sync_0,
irq_from_the_fifo_out_8b_sync_1 => irq_from_the_fifo_out_8b_sync_1,
irq_from_the_spi_master_0 => irq_from_the_spi_master_0,
irq_from_the_twi_master_0 => irq_from_the_twi_master_0,
irq_from_the_twi_master_1 => irq_from_the_twi_master_1,
mem_addr_from_the_dvb_dma_0 => mem_addr_from_the_dvb_dma_0,
mem_addr_from_the_dvb_dma_1 => mem_addr_from_the_dvb_dma_1,
mem_byteen_from_the_dvb_dma_0 => mem_byteen_from_the_dvb_dma_0,
mem_byteen_from_the_dvb_dma_1 => mem_byteen_from_the_dvb_dma_1,
mem_size_from_the_dvb_dma_0 => mem_size_from_the_dvb_dma_0,
mem_size_from_the_dvb_dma_1 => mem_size_from_the_dvb_dma_1,
mem_wrdata_from_the_dvb_dma_0 => mem_wrdata_from_the_dvb_dma_0,
mem_wrdata_from_the_dvb_dma_1 => mem_wrdata_from_the_dvb_dma_1,
mem_write_from_the_dvb_dma_0 => mem_write_from_the_dvb_dma_0,
mem_write_from_the_dvb_dma_1 => mem_write_from_the_dvb_dma_1,
mosi_from_the_spi_master_0 => mosi_from_the_spi_master_0,
out_address_from_the_avalon64_to_avalon8_0 => out_address_from_the_avalon64_to_avalon8_0,
out_read_from_the_avalon64_to_avalon8_0 => out_read_from_the_avalon64_to_avalon8_0,
out_write_from_the_avalon64_to_avalon8_0 => out_write_from_the_avalon64_to_avalon8_0,
out_writedata_from_the_avalon64_to_avalon8_0 => out_writedata_from_the_avalon64_to_avalon8_0,
pcie_compiler_0_pcie_core_clk_out => pcie_compiler_0_pcie_core_clk_out,
pins_from_the_gpout_0 => pins_from_the_gpout_0,
powerdown_ext_pcie_compiler_0 => powerdown_ext_pcie_compiler_0,
rate_ext_pcie_compiler_0 => rate_ext_pcie_compiler_0,
reconfig_fromgxb_pcie_compiler_0 => reconfig_fromgxb_pcie_compiler_0,
rxpolarity0_ext_pcie_compiler_0 => rxpolarity0_ext_pcie_compiler_0,
scl_act_from_the_twi_master_0 => scl_act_from_the_twi_master_0,
scl_act_from_the_twi_master_1 => scl_act_from_the_twi_master_1,
sclk_from_the_spi_master_0 => sclk_from_the_spi_master_0,
sda_act_from_the_twi_master_0 => sda_act_from_the_twi_master_0,
sda_act_from_the_twi_master_1 => sda_act_from_the_twi_master_1,
tx_out0_pcie_compiler_0 => tx_out0_pcie_compiler_0,
txcompl0_ext_pcie_compiler_0 => txcompl0_ext_pcie_compiler_0,
txdata0_ext_pcie_compiler_0 => txdata0_ext_pcie_compiler_0,
txdatak0_ext_pcie_compiler_0 => txdatak0_ext_pcie_compiler_0,
txdetectrx_ext_pcie_compiler_0 => txdetectrx_ext_pcie_compiler_0,
txelecidle0_ext_pcie_compiler_0 => txelecidle0_ext_pcie_compiler_0,
avlm_irq_to_the_int_ctrl_0 => avlm_irq_to_the_int_ctrl_0,
busy_altgxb_reconfig_pcie_compiler_0 => busy_altgxb_reconfig_pcie_compiler_0,
cam_address_to_the_ci_bridge_0 => cam_address_to_the_ci_bridge_0,
cam_baseclk_to_the_dvb_ts_0 => cam_baseclk_to_the_dvb_ts_0,
cam_baseclk_to_the_dvb_ts_1 => cam_baseclk_to_the_dvb_ts_1,
cam_bypass_to_the_dvb_ts_0 => cam_bypass_to_the_dvb_ts_0,
cam_bypass_to_the_dvb_ts_1 => cam_bypass_to_the_dvb_ts_1,
cam_mclko_to_the_dvb_ts_0 => cam_mclko_to_the_dvb_ts_0,
cam_mclko_to_the_dvb_ts_1 => cam_mclko_to_the_dvb_ts_1,
cam_mdo_to_the_dvb_ts_0 => cam_mdo_to_the_dvb_ts_0,
cam_mdo_to_the_dvb_ts_1 => cam_mdo_to_the_dvb_ts_1,
cam_mostrt_to_the_dvb_ts_0 => cam_mostrt_to_the_dvb_ts_0,
cam_mostrt_to_the_dvb_ts_1 => cam_mostrt_to_the_dvb_ts_1,
cam_moval_to_the_dvb_ts_0 => cam_moval_to_the_dvb_ts_0,
cam_moval_to_the_dvb_ts_1 => cam_moval_to_the_dvb_ts_1,
cam_read_to_the_ci_bridge_0 => cam_read_to_the_ci_bridge_0,
cam_write_to_the_ci_bridge_0 => cam_write_to_the_ci_bridge_0,
cam_writedata_to_the_ci_bridge_0 => cam_writedata_to_the_ci_bridge_0,
ci_d_in_to_the_ci_bridge_0 => ci_d_in_to_the_ci_bridge_0,
cia_cd_n_to_the_ci_bridge_0 => cia_cd_n_to_the_ci_bridge_0,
cia_ireq_n_to_the_ci_bridge_0 => cia_ireq_n_to_the_ci_bridge_0,
cia_overcurrent_n_to_the_ci_bridge_0 => cia_overcurrent_n_to_the_ci_bridge_0,
cia_wait_n_to_the_ci_bridge_0 => cia_wait_n_to_the_ci_bridge_0,
cib_cd_n_to_the_ci_bridge_0 => cib_cd_n_to_the_ci_bridge_0,
cib_ireq_n_to_the_ci_bridge_0 => cib_ireq_n_to_the_ci_bridge_0,
cib_overcurrent_n_to_the_ci_bridge_0 => cib_overcurrent_n_to_the_ci_bridge_0,
cib_wait_n_to_the_ci_bridge_0 => cib_wait_n_to_the_ci_bridge_0,
dma0_addr_to_the_dma_arbiter_0 => dma0_addr_to_the_dma_arbiter_0,
dma0_byteen_to_the_dma_arbiter_0 => dma0_byteen_to_the_dma_arbiter_0,
dma0_size_to_the_dma_arbiter_0 => dma0_size_to_the_dma_arbiter_0,
dma0_wrdata_to_the_dma_arbiter_0 => dma0_wrdata_to_the_dma_arbiter_0,
dma0_write_to_the_dma_arbiter_0 => dma0_write_to_the_dma_arbiter_0,
dma1_addr_to_the_dma_arbiter_0 => dma1_addr_to_the_dma_arbiter_0,
dma1_byteen_to_the_dma_arbiter_0 => dma1_byteen_to_the_dma_arbiter_0,
dma1_size_to_the_dma_arbiter_0 => dma1_size_to_the_dma_arbiter_0,
dma1_wrdata_to_the_dma_arbiter_0 => dma1_wrdata_to_the_dma_arbiter_0,
dma1_write_to_the_dma_arbiter_0 => dma1_write_to_the_dma_arbiter_0,
dvb_data_to_the_dvb_dma_0 => dvb_data_to_the_dvb_dma_0,
dvb_data_to_the_dvb_dma_1 => dvb_data_to_the_dvb_dma_1,
dvb_dval_to_the_dvb_dma_0 => dvb_dval_to_the_dvb_dma_0,
dvb_dval_to_the_dvb_dma_1 => dvb_dval_to_the_dvb_dma_1,
dvb_in0_data_to_the_dvb_ts_0 => dvb_in0_data_to_the_dvb_ts_0,
dvb_in0_data_to_the_dvb_ts_1 => dvb_in0_data_to_the_dvb_ts_1,
dvb_in0_dsop_to_the_dvb_ts_0 => dvb_in0_dsop_to_the_dvb_ts_0,
dvb_in0_dsop_to_the_dvb_ts_1 => dvb_in0_dsop_to_the_dvb_ts_1,
dvb_in0_dval_to_the_dvb_ts_0 => dvb_in0_dval_to_the_dvb_ts_0,
dvb_in0_dval_to_the_dvb_ts_1 => dvb_in0_dval_to_the_dvb_ts_1,
dvb_in1_data_to_the_dvb_ts_0 => dvb_in1_data_to_the_dvb_ts_0,
dvb_in1_data_to_the_dvb_ts_1 => dvb_in1_data_to_the_dvb_ts_1,
dvb_in1_dsop_to_the_dvb_ts_0 => dvb_in1_dsop_to_the_dvb_ts_0,
dvb_in1_dsop_to_the_dvb_ts_1 => dvb_in1_dsop_to_the_dvb_ts_1,
dvb_in1_dval_to_the_dvb_ts_0 => dvb_in1_dval_to_the_dvb_ts_0,
dvb_in1_dval_to_the_dvb_ts_1 => dvb_in1_dval_to_the_dvb_ts_1,
dvb_in2_data_to_the_dvb_ts_0 => dvb_in2_data_to_the_dvb_ts_0,
dvb_in2_data_to_the_dvb_ts_1 => dvb_in2_data_to_the_dvb_ts_1,
dvb_in2_dsop_to_the_dvb_ts_0 => dvb_in2_dsop_to_the_dvb_ts_0,
dvb_in2_dsop_to_the_dvb_ts_1 => dvb_in2_dsop_to_the_dvb_ts_1,
dvb_in2_dval_to_the_dvb_ts_0 => dvb_in2_dval_to_the_dvb_ts_0,
dvb_in2_dval_to_the_dvb_ts_1 => dvb_in2_dval_to_the_dvb_ts_1,
dvb_sop_to_the_dvb_dma_0 => dvb_sop_to_the_dvb_dma_0,
dvb_sop_to_the_dvb_dma_1 => dvb_sop_to_the_dvb_dma_1,
fixedclk_serdes_pcie_compiler_0 => fixedclk_serdes_pcie_compiler_0,
gxb_powerdown_pcie_compiler_0 => gxb_powerdown_pcie_compiler_0,
mem_waitreq_to_the_dvb_dma_0 => mem_waitreq_to_the_dvb_dma_0,
mem_waitreq_to_the_dvb_dma_1 => mem_waitreq_to_the_dvb_dma_1,
miso_to_the_spi_master_0 => miso_to_the_spi_master_0,
out_readdata_to_the_avalon64_to_avalon8_0 => out_readdata_to_the_avalon64_to_avalon8_0,
out_waitrequest_to_the_avalon64_to_avalon8_0 => out_waitrequest_to_the_avalon64_to_avalon8_0,
pcie_rstn_pcie_compiler_0 => pcie_rstn_pcie_compiler_0,
phystatus_ext_pcie_compiler_0 => phystatus_ext_pcie_compiler_0,
pipe_mode_pcie_compiler_0 => pipe_mode_pcie_compiler_0,
pll_powerdown_pcie_compiler_0 => pll_powerdown_pcie_compiler_0,
reconfig_clk_pcie_compiler_0 => reconfig_clk_pcie_compiler_0,
reconfig_togxb_pcie_compiler_0 => reconfig_togxb_pcie_compiler_0,
refclk_pcie_compiler_0 => refclk_pcie_compiler_0,
reset_n => reset_n,
rx_in0_pcie_compiler_0 => rx_in0_pcie_compiler_0,
rxdata0_ext_pcie_compiler_0 => rxdata0_ext_pcie_compiler_0,
rxdatak0_ext_pcie_compiler_0 => rxdatak0_ext_pcie_compiler_0,
rxelecidle0_ext_pcie_compiler_0 => rxelecidle0_ext_pcie_compiler_0,
rxstatus0_ext_pcie_compiler_0 => rxstatus0_ext_pcie_compiler_0,
rxvalid0_ext_pcie_compiler_0 => rxvalid0_ext_pcie_compiler_0,
scl_in_to_the_twi_master_0 => scl_in_to_the_twi_master_0,
scl_in_to_the_twi_master_1 => scl_in_to_the_twi_master_1,
sda_in_to_the_twi_master_0 => sda_in_to_the_twi_master_0,
sda_in_to_the_twi_master_1 => sda_in_to_the_twi_master_1,
sink_irq_to_the_twi_master_0 => sink_irq_to_the_twi_master_0,
sink_irq_to_the_twi_master_1 => sink_irq_to_the_twi_master_1,
source_irq_to_the_twi_master_0 => source_irq_to_the_twi_master_0,
source_irq_to_the_twi_master_1 => source_irq_to_the_twi_master_1,
test_in_pcie_compiler_0 => test_in_pcie_compiler_0
);
--the_pcie_compiler_0_testbench, which is an e_instance
the_pcie_compiler_0_testbench : pcie_compiler_0_testbench
port map(
busy_altgxb_reconfig => busy_altgxb_reconfig_pcie_compiler_0,
fixedclk_serdes => fixedclk_serdes_pcie_compiler_0,
gxb_powerdown => gxb_powerdown_pcie_compiler_0,
pcie_rstn => pcie_rstn_pcie_compiler_0,
phystatus_ext => phystatus_ext_pcie_compiler_0,
pipe_mode => pipe_mode_pcie_compiler_0,
pll_powerdown => pll_powerdown_pcie_compiler_0,
reconfig_clk => reconfig_clk_pcie_compiler_0,
reconfig_togxb => reconfig_togxb_pcie_compiler_0,
refclk => refclk_pcie_compiler_0,
rx_in0 => rx_in0_pcie_compiler_0,
rxdata0_ext => rxdata0_ext_pcie_compiler_0,
rxdatak0_ext => rxdatak0_ext_pcie_compiler_0,
rxelecidle0_ext => rxelecidle0_ext_pcie_compiler_0,
rxstatus0_ext => rxstatus0_ext_pcie_compiler_0,
rxvalid0_ext => rxvalid0_ext_pcie_compiler_0,
test_in => test_in_pcie_compiler_0,
clk125_out => clk125_out_pcie_compiler_0,
clk250_out => clk250_out_pcie_compiler_0,
clk500_out => clk500_out_pcie_compiler_0,
powerdown_ext => powerdown_ext_pcie_compiler_0,
rate_ext => rate_ext_pcie_compiler_0,
reconfig_fromgxb => reconfig_fromgxb_pcie_compiler_0,
rxpolarity0_ext => rxpolarity0_ext_pcie_compiler_0,
tx_out0 => tx_out0_pcie_compiler_0,
txcompl0_ext => txcompl0_ext_pcie_compiler_0,
txdata0_ext => txdata0_ext_pcie_compiler_0,
txdatak0_ext => txdatak0_ext_pcie_compiler_0,
txdetectrx_ext => txdetectrx_ext_pcie_compiler_0,
txelecidle0_ext => txelecidle0_ext_pcie_compiler_0
);
PROCESS
BEGIN
reset_n <= '0';
wait for 200 ns;
reset_n <= '1';
WAIT;
END PROCESS;
-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
--add additional architecture here
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>
end europa;
--synthesis translate_on
|
gpl-3.0
|
baa213deead9e268f204b7112c3cd883
| 0.671524 | 3.29507 | false | false | false | false |
SalvatoreBarone/Zynq7000DriverPack
|
Src/myGPIO/VHDL/myGPIO_AXI.vhd
| 1 | 28,068 |
--! @file myGPIO_AXI.vhd
--! @author Salvatore Barone <[email protected]>
--! @date 22 06 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <[email protected]>
--!
--! This file is part of Zynq7000DriverPack
--!
--! Zynq7000DriverPack is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Zynq7000DriverPack is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--!
--! @addtogroup myGPIO
--! @{
--! @addtogroup AXI-internal
--! @{
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--! @brief Periferica AXI4 Lite che implementa una GPIO pilotabile da processing-system.
--!
--! @details
--!
--! <h4>Registri interni del device</h4>
--! Il device possiede i registri indicati di seguito. Per oognuno di essi viene indicata la modalità di
--! accesso (R sola lettura, W sola scrittura, R/W lettura scrittura), e l'offset, rispetto all'indirizzo
--! base del device, col quale è possibile indirizzarli.
--!
--! - MODE (R/W, offset +0x0): consente di impostare i singoli pin del device come ingressi o uscite; solo i
--! GPIO_width bit meno significativi del registro hanno significato, agire sui restanti bit non produce
--! nessun effetto; Il valore che i singoli pin possono
--! assumere è:
--! - '1': il pin viene configurato come pin di uscita;
--! - 'ò: il pin viene configurato come pin di ingresso;
--! .
--! - WRITE (R/W, offset +0x4): consente di imporre un valore ai pin del device, qualora essi siano configurati
--! come uscite; solo i GPIO_width bit meno significativi del hanno significato, agire sui restanti bit non produce
--! nessun effetto;
--! - READ (R, offset +0x8): consente di leggere il valore dei pin del device, sia quelli configurati come
--! ingressi che quelli configurati come uscite (il cui valore coincide con quello settato nel registro
--! WRITE); solo i GPIO_width bit meno significativi del registro hanno significato, gli altri vengono letti
--! zero;
--! - GIES (Global Interrupt Enable/Status, R/W, offset 0xC): Consente di abilitare/disabilitare gli interrupt
--! globali della periferica; solo due dei bit sono significativi:
--! - IE (bit 0): interrupt enable, abilita gli interrupt, può essere scritto e letto; se posto ad '1'
--! la periferica potrà generare interrupt quando uno dei pin impostati come ingresso assume
--! valore '1' (ed il corrispondente bit in PIE è impostato ad '1'); se posto a '0' il device
--! non genererà mai interruzioni;
--! - IS (bit 1): interrupt status, settato internamente ad '1' nel caso in cui la periferica abbia
--! generato interrupt; replica del segnale "interrupt" diretto verso il processing-system.
--! - PIE (Pin Interrupt Enable, R/W, offset 0x10): consente di abilitare/disabilitare gli interrupt per i
--! singoli pin. Con GIES(0)='1' e MODE(n)='0' (cioè se gli interrupt globali sono abilitati e il pin
--! n-esimo è configurato come input), se PIE(n)='1' allora il device genererà un interrupt verso il
--! processing-system quando il pin n-esimo assumerà valore '1', mentre, se PIE(n)='0' non verrà
--! generata una interruzione;
--! - IRQ (Interrupt Request, R, offset 0x14): IRQ(n)='1' indica che la sorgente di interruzione è il bit
--! n-esimo; la or-reduce di tale registro costituisce il flag "interrupt" (IS) di GIES, mentre lo stesso
--! segnale, posto in AND con GIES(0) - interrupt enable - è diretto verso il processing system.
--! - IACK (Interrupt Ack, W, offset 0x18): imponento IACK(n)='1' è possibile segnalare al device che
--! l'interruzione generata dal in n-esimo è stata servita; il bit IRQ(n) verrà resettato automaticamente.
--!
--!
--! <h4>Process di scrittura dei registri della periferica</h4>
--! Il process che implementa la logica di scrittura dei registri è stato modificato in modo da ottenere
--! il seguente indirizzamento:
--! <table>
--! <tr><th>Indirizzo</th><th>Offset</th><th>Registro</th></tr>
--! <tr><td>b"00000"</td><td>0x00</td><td>MODE</td></tr>
--! <tr><td>b"00100"</td><td>0x04</td><td>WRITE</td></tr>
--! <tr><td>b"01000"</td><td>0x08</td><td>READ(*)</td></tr>
--! <tr><td>b"01100"</td><td>0x0C</td><td>GIES(**)</td></tr>
--! <tr><td>b"10000"</td><td>0x10</td><td>PIE</td></tr>
--! <tr><td>b"10100"</td><td>0x14</td><td>IRQ(***)</td></tr>
--! <tr><td>b"11000"</td><td>0x18</td><td>IACK(****)</td></tr>
--! </table>
--! (*) Il registro READ è a sola lettura: le scritture su questo registro non producono effetti;
--! la scrittura, infatti, avviene su slv_reg2, che è inutilizzato;<br>
--! (**) La scrittura ha effetto solo sul bit zero del registro;<br>
--! (***) Il registro IRQ è a sola lettura: le scritture su questo registro non producono effetti;
--! la scrittura, infatti, avviene su slv_reg5, che è inutilizzato;<br>
--! (****) La scrittura su IACK è fittizzia, nel senso che appena si smette di indirizzare il registro,
--! esso assume valore zero;<br>
--!
--!
--! <h4>Process di lettura dei registri della periferica</h4>
--! Il process che implementa la logica di lettura dei registri è stato modificato in modo da ottenere
--! il seguente indirizzamento:
--! <table>
--! <tr><th>Indirizzo</th><th>Offset</th><th>Registro</th></tr>
--! <tr><td>b"00000"</td><td>0x00</td><td>MODE</td></tr>
--! <tr><td>b"00100"</td><td>0x04</td><td>WRITE</td></tr>
--! <tr><td>b"01000"</td><td>0x08</td><td>READ(*)</td></tr>
--! <tr><td>b"01100"</td><td>0x0C</td><td>GIES(**)</td></tr>
--! <tr><td>b"10000"</td><td>0x10</td><td>PIE</td></tr>
--! <tr><td>b"10100"</td><td>0x14</td><td>IRQ</td></tr>
--! <tr><td>b"11000"</td><td>0x18</td><td>IACK(***)</td></tr>
--! </table>
--! (*) Il registro READ è direttamente connesso alla porta GPIO_inout<br>
--! (**) Il bit 2 di GIES è il flag "interrupt", che vale '1' nel caso in cui la periferica abbia generato
--! interrupt ancora non gestiti.<br>
--! (***) Viene letto sempre zero, dal momento che la scrittura su tale registro è fittizzia.
--!
--!
--! <h4>Process di scrittura su IRQ</h4>
--! La logica di scrittura su IRQ è semplice (non viene scritto come un normale registro, ma pilotato
--! internamente dalla periferica):
--! se uno dei bit di GPIO_inout_masked è '1', (la or-reduce è 1) allora il valore del segnale GPIO_inout_masked
--! viene posto in bitwise-or con il valore attuale del registro IRQ, in modo da non resettare i bit di quest'
--! ultimo che siano stati settati a seguito di una interruzione non ancora servita
--! se uno dei bit di IACK è '1' (la or-reduce è '1'), allora il nuovo valore del registro IRQ viene ottenuto
--! - mascherando IACK con l'attuale valore di IRQ, in modo da non effettuare il set di bit resettati
--! - ponendo in XOR la maschera precedente con il valore attuale del registro
entity myGPIO_AXI is
generic (
-- Users to add parameters here
GPIO_width : natural := 4; --! numero di GPIO offerti dalla periferica, di default pari a 4 celle.
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
GPIO_inout : inout std_logic_vector (GPIO_width-1 downto 0); --!
--! segnale bidirezionale diretto verso l'esterno del device.
interrupt : out std_logic; --!
--! segnale di interrupt a livelli diretto verso il processing - system. Se le interruzioni sono
--! abilitate ed uno dei pin del device è settato come input ed è abilitato a generare interruzioni,
--! diventa '1' appena tale pin assume valore '1', e mantiene tale valore fino a quando tutte le
--! interruzioni non siano state servite.
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end myGPIO_AXI;
architecture arch_imp of myGPIO_AXI is
component GPIOarray is
Generic ( GPIO_width : natural := 4);
Port ( GPIO_enable : in std_logic_vector (GPIO_width-1 downto 0);
GPIO_write : in std_logic_vector (GPIO_width-1 downto 0);
GPIO_inout : inout std_logic_vector (GPIO_width-1 downto 0);
GPIO_read : out std_logic_vector (GPIO_width-1 downto 0));
end component;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
signal MODE : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal WRITE :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal READ :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal GIES :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal PIE :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal IRQ :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal IACK :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
-- Segnali ausiliari
signal GPIO_inout_masked : std_logic_vector (GPIO_width-1 downto 0); --!
-- segnale GPIO_inout mascherato: viene ottenuto tramite bitwise-and tra
-- - GPIO_inout
-- - il registro MODE (negato), in modo che solo i bit impostati come input possano generare interrupt;
-- - il registro PIE, in modo che solo i pin abilitati a generare interrupt lo facciano
signal interrupt_tmp : std_logic := '0'; --!
-- segnale "di appoggio", connesso al segnale "interrupt" ed usato per leggere il valore di quest'ultimo
-- attraverso GIES(1). Viene ottenuto mediante la or-reduce di IRQ
-- il segnale interrupt viene ottenuto come and tra interrupt_tmp GIES(0)
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
MODE <= (others => '0');
WRITE <= (others => '0');
slv_reg2 <= (others => '0');
GIES <= (others => '0');
PIE <= (others => '0');
IACK <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
IACK <= (others => '0'); -- questa riga serve a definire il valore di IACK quando
-- non viene indirizzato, in modo che per esso non venga istanziato un registro
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
MODE(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
WRITE(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010" =>
-- READ non viene scritto, la scrittura avviene su slv_reg2, lasciato inutilizzato
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
GIES(C_S_AXI_DATA_WIDTH-1 downto 1) <= (others => '0');
GIES(0) <= S_AXI_WDATA(0);
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
PIE(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
-- IRQ non viene scritto, la scrittura avviene su slv_reg5, lasciato inutilizzato
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
IACK(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
MODE <= MODE;
WRITE <= WRITE;
slv_reg2 <= slv_reg2;
GIES <= GIES;
PIE <= PIE;
slv_reg5 <= slv_reg5;
IACK <= (others => '0'); -- questa riga serve a definire il valore di IACK quando
-- non viene indirizzato, in modo che per esso non venga istanziato un registro
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (MODE, WRITE, slv_reg2, GIES, PIE, IRQ, IACK, slv_reg7, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= MODE;
when b"001" =>
reg_data_out <= WRITE;
when b"010" =>
reg_data_out <= READ;
when b"011" =>
-- al posto di GIES(1) viene letto interrupt_tmp
reg_data_out <= GIES(C_S_AXI_DATA_WIDTH-1 downto 2) & interrupt_tmp & GIES(0);
when b"100" =>
reg_data_out <= PIE;
when b"101" =>
reg_data_out <= IRQ;
when b"110" =>
reg_data_out <= IACK;
when b"111" =>
reg_data_out <= slv_reg7;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- istanziazione dell'array di GPIO
GPIOarray_inst : GPIOarray
Generic map ( GPIO_width => GPIO_width)
Port map ( GPIO_enable => MODE(GPIO_width-1 downto 0),
GPIO_write => WRITE(GPIO_width-1 downto 0),
GPIO_inout => GPIO_inout,
GPIO_read => READ(GPIO_width-1 downto 0));
-- GPIO_inout mascherato: viene ottenuto tramite bitwise-and tra
-- - GPIO_inout
-- - il registro MODE (negato), in modo che solo i bit impostati come input possano generare interrupt;
-- - il registro PIE, in modo che solo i pin abilitati a generare interrupt lo facciano
GPIO_inout_masked <= GPIO_inout and (not MODE(GPIO_width-1 downto 0)) and PIE(GPIO_width-1 downto 0);
-- interrupt_tmp è ottenuto mediante la or-reduce di IRQ
interrupt_tmp <= or_reduce(IRQ);
-- interrupt è ottenuto mediante and tra interrupt_tmp e GIES(0) (interrupt-enable)
interrupt <= interrupt_tmp and GIES(0);
-- Process di scrittura su IRQ
-- La logica di scrittura su IRQ è semplice (non viene scritto come un normale registro, ma pilotato
-- internamente dalla periferica):
--
-- se uno dei bit di GPIO_inout_masked è '1', (la or-reduce è 1) allora il valore del segnale GPIO_inout_masked
-- viene posto in bitwise-or con il valore attuale del registro IRQ, in modo da non resettare i bit di quest'
-- ultimo che siano stati settati a seguito di una interruzione non ancora servita
--
-- se uno dei bit di IACK è '1' (la or-reduce è '1'), allora il nuovo valore del registro IRQ viene ottenuto
-- - mascherando IACK con l'attuale valore di IRQ, in modo da non effettuare il set di bit resettati
-- - ponendo in XOR la maschera precedente con il valore attuale del registro
process (S_AXI_ACLK, S_AXI_ARESETN, GPIO_inout_masked, IACK)
begin
if S_AXI_ARESETN = '0' then
IRQ <= (others => '0');
elsif rising_edge(S_AXI_ACLK) then
if or_reduce(GPIO_inout_masked) = '1' then
IRQ(GPIO_width-1 downto 0) <= IRQ(GPIO_width-1 downto 0) or GPIO_inout_masked;
end if;
if or_reduce(IACK) = '1' then
IRQ(GPIO_width-1 downto 0) <= IRQ(GPIO_width-1 downto 0) xor (IACK(GPIO_width-1 downto 0) and IRQ(GPIO_width-1 downto 0));
end if;
end if;
end process;
-- User logic ends
end arch_imp;
--! @endcond
--! @}
--! @}
|
gpl-3.0
|
07c43ab0e0c2f7b3648ae1ba754b16ee
| 0.646471 | 3.292528 | false | false | false | false |
Anding/DDR2_memory_interface
|
rtl/system/ByteHEXdisplay.vhd
| 1 | 2,113 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ByteHEXdisplay is
Port (
clk : in STD_LOGIC;
ssData : in STD_LOGIC_VECTOR (31 downto 0);
sevenseg : out STD_LOGIC_VECTOR (6 downto 0);
anode : out STD_LOGIC_VECTOR (7 downto 0)
);
end ByteHEXdisplay;
architecture Behavioral of ByteHEXdisplay is
signal nibble : STD_LOGIC_VECTOR (3 downto 0);
signal count : STD_LOGIC_VECTOR (15 downto 0);
begin
PROCESS
begin
wait until rising_edge(clk);
count <= count + 1;
if count(15 downto 13) = "001" then -- toggle on MSBits of count
anode <= "11111110";
nibble <= ssData(3 downto 0);
elsif count(15 downto 13) = "010" then
anode <= "11111101";
nibble <= ssData(7 downto 4);
elsif count(15 downto 13) = "011" then
anode <= "11111011";
nibble <= ssData(11 downto 8);
elsif count(15 downto 13) = "100" then
anode <= "11110111";
nibble <= ssData(15 downto 12);
elsif count(15 downto 13) = "101" then
anode <= "11101111";
nibble <= ssData(19 downto 16);
elsif count(15 downto 13) = "110" then
anode <= "11011111";
nibble <= ssData(23 downto 20);
elsif count(15 downto 13) = "111" then
anode <= "10111111";
nibble <= ssData(27 downto 24);
else
anode <= "01111111";
nibble <= ssData(31 downto 28);
end if;
case nibble is
when "0000" => sevenseg <= "1000000";
when "0001" => sevenseg <= "1111001";
when "0010" => sevenseg <= "0100100";
when "0011" => sevenseg <= "0110000";
when "0100" => sevenseg <= "0011001";
when "0101" => sevenseg <= "0010010";
when "0110" => sevenseg <= "0000010";
when "0111" => sevenseg <= "1111000";
when "1000" => sevenseg <= "0000000";
when "1001" => sevenseg <= "0011000";
when "1010" => sevenseg <= "0001000";
when "1011" => sevenseg <= "0000011";
when "1100" => sevenseg <= "1000110";
when "1101" => sevenseg <= "0100001";
when "1110" => sevenseg <= "0000110";
when others => sevenseg <= "0001110";
end case;
end process;
end Behavioral;
|
gpl-2.0
|
fd88bd1c9dedbd8f6f5e7695fa6a8e61
| 0.611926 | 3.235835 | false | false | false | false |
rinatzakirov/vhdl
|
one_element_fifo.vhd
| 1 | 2,015 |
------------------------------------------------------------------------
-- One element fifo
--
-- Copyright (c) 2014-2014 Rinat Zakirov
-- SPDX-License-Identifier: BSL-1.0
--
------------------------------------------------------------------------
NOT TESTED
library ieee;
use ieee.std_logic_1164.all;
entity one_element_fifo is
generic
(
BW: positive := 8
);
port
(
clk : in std_ulogic;
rst : in std_ulogic;
in_data : in std_ulogic_vector(BW - 1 downto 0);
in_valid : in std_ulogic;
in_ready : out std_ulogic;
out_data : out std_ulogic_vector(BW - 1 downto 0);
out_valid : out std_ulogic;
out_ready : in std_ulogic
);
end entity;
architecture rtl of one_element_fifo is
signal buf_val: std_ulogic;
signal buf: std_ulogic_vector(in_data'range);
signal in_ready_i, out_valid_i: std_ulogic;
begin
in_ready <= in_ready_i;
out_valid <= out_valid_i;
in_ready_i <= '1' when out_ready = '1' or buf_val = '0' else '0';
out_valid_i <= '1' when in_valid = '1' or buf_val = '1' else '0';
out_data <= in_data when buf_val = '0' else buf;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
buf_val <= '0';
else
if in_valid = '1' then
if out_ready = '1' then
assert (in_ready_i = '1') report "BAD FIFO LOGIC" severity failure;
if buf_val = '1' then
buf <= in_data;
end if;
else
if buf_val = '1' then
assert (in_ready_i = '0') report "BAD FIFO LOGIC" severity failure;
else
buf <= in_data;
buf_val <= '1';
end if;
end if;
else
if out_ready = '1' then
if buf_val = '1' then
buf_val <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
end architecture rtl;
|
lgpl-2.1
|
bdfa9d4b001a3272d29ec40cdd7c163d
| 0.468486 | 3.560071 | false | false | false | false |
arthurTemporim/SD_SS
|
rel/5/projetos/projeto2/projeto2.vhd
| 1 | 671 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto2 is
port (
a : in std_logic := '0';
b : in std_logic := '1';
c : in std_logic := '0';
s : out std_logic
);
end projeto2;
architecture Behavioral of projeto2 is
signal multiplex : std_logic;
signal out_multiplex : std_logic;
signal demultiplex : std_logic;
begin
process (multiplex, a, b, c)
begin
if(a = '0') then
multiplex <= b;
else
multiplex <= c;
end if;
out_multiplex <= multiplex;
end process;
process (out_multiplex, a, b, c)
begin
if (a = '0') then
demultiplex <= out_multiplex;
else
demultiplex <= out_multiplex;
end if;
end process;
s <= demultiplex;
end Behavioral;
|
mit
|
ecf8aa962f2dda800d873020fcfab206
| 0.658718 | 2.738776 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Testbenches/PhaseGenerator_Tester.vhd
| 1 | 6,352 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the frequency generator.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PhaseGenerator_Tester is
end entity;
architecture stdarch of PhaseGenerator_Tester is
--------------------
-- Constants
--------------------
constant clk_period: time := 10ns;
constant phase_width: natural := 32;
constant sample_width: natural := 32;
constant phase_increment_1: integer := 16#19999999#; -- needs about 10 clock cycles
constant clk_cycles_per_counter_cycle: integer := 10;
--------------------
-- Inputs
--------------------
signal clk: std_logic := '0';
signal phase_increment: unsigned(phase_width-1 downto 0) :=
to_unsigned(phase_increment_1, phase_width);
signal reset_phase: std_logic := '0';
--------------------
-- Outputs
--------------------
signal frequency_signal: std_logic;
signal phase: unsigned (phase_width-1 downto 0);
--------------------
-- Internals
--------------------
signal run_test: boolean := true;
signal phase_reset_test_has_started: boolean := false;
begin
--------------------------------------------------------------------------------
-- Connections to and from internal signals.
--------------------------------------------------------------------------------
-- Just use the phase´s MSB as a frequency signal.
frequency_signal <= phase(phase'high);
--------------------------------------------------------------------------------
-- UUT instantiation.
--------------------------------------------------------------------------------
uut: entity work.PhaseGenerator
generic map
(
phase_width => phase_width
)
port map
(
clk => clk,
phase_increment => phase_increment,
reset_phase => reset_phase,
phase => phase
);
--------------------------------------------------------------------------------
-- UUT stimulation.
--------------------------------------------------------------------------------
-- Generates the system clock.
clk <= not clk after clk_period/2 when run_test;
-- Stimulates and controls the UUT and the tests at all.
stimulus: process is
constant signal_cycles_to_test: integer := 10;
begin
-- Do the tests for the specified duration.
wait until rising_edge(frequency_signal);
wait for 2*signal_cycles_to_test * (clk_cycles_per_counter_cycle/2) * clk_period;
phase_reset_test_has_started <= true;
wait for 10*clk_period;
wait until falling_edge(clk);
reset_phase <= '1';
wait until falling_edge(clk);
reset_phase <= '0';
wait for 10*clk_period;
-- Stop the tests.
run_test <= false;
wait;
end process;
--------------------------------------------------------------------------------
-- Specifications.
--------------------------------------------------------------------------------
-- Verifies proper frequency signal generation.
must_create_correct_frequency_signal: process is
variable previous_signal: std_logic;
begin
-- The first signal edge comes rather randomly (depending on the phase
-- increment). Thus synchronize to that signal.
wait until rising_edge(frequency_signal);
if not phase_reset_test_has_started then
-- Verify the correct duration of high and the low phase (i.e. the right
-- frequency and the 50% duty cycle). This test might not work exactly for
-- increments that aren´t a power of two.
wait until falling_edge(clk);
previous_signal := frequency_signal;
for clk_cycle in 1 to (clk_cycles_per_counter_cycle/2)-1 loop
wait until falling_edge(clk);
assert (frequency_signal = previous_signal)
report "Signal not changed or changed unexpectedly."
severity error;
end loop;
end if;
end process;
-- Verifies whether the phase is incremented correctly.
must_increment_phase_per_clk_cycle: process is
variable previous_phase: unsigned (phase_width-1 downto 0) := (others => '0');
begin
wait until falling_edge(clk);
if not phase_reset_test_has_started then
assert (phase = previous_phase + to_unsigned(phase_increment_1, phase_width))
report "Phase not incremented as expected." & integer'image(to_integer(previous_phase))
severity error;
previous_phase := phase;
end if;
end process;
-- Verifies correct phase reset.
must_reset_phase_on_request: process is
begin
wait until rising_edge(clk);
wait until falling_edge(clk);
if reset_phase = '1' then
assert (phase = (phase'range => '0'))
report "Phase not reset as expected."
severity error;
end if;
end process;
end architecture;
|
gpl-3.0
|
036b2e006f0c34d9b65c5e8fc4053689
| 0.48961 | 5.288926 | false | true | false | false |
arthurbenemann/fpga-bits
|
undocumented/flashyLights/ipcore_dir/memmory/example_design/memmory_prod.vhd
| 1 | 9,894 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: memmory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : memmory.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY memmory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END memmory_prod;
ARCHITECTURE xilinx OF memmory_prod IS
COMPONENT memmory_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : memmory_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-3.0
|
5494c4fd70a027e0e5ef28fd6a56edbb
| 0.49434 | 3.839348 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/VGA1/vga800x600.vhd
| 1 | 1,581 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga800x600 is Port (
clk : in std_logic; -- 40 MHz
red : out std_logic_vector(3 downto 0);
green : out std_logic_vector(3 downto 0);
blue : out std_logic_vector(3 downto 0);
hsync: out std_logic;
vsync: out std_logic;
SW : in std_logic);
end vga800x600;
architecture Behavioral of vga800x600 is
signal hcount : std_logic_vector(10 downto 0) := (others =>'0');
signal vcount : std_logic_vector(9 downto 0) := (others =>'0');
begin
counters : process(clk) begin
if rising_edge(clk) then
-- Counters
if hcount = 1055 then
hcount <= (others =>'0');
if vcount = 627 then
vcount <= (others =>'0');
else
vcount <= vcount + 1;
end if;
else
hcount <= hcount + 1;
end if;
-- Hsync
if hcount >= (800+40) and hcount < (800+40+128) then
hsync <= '0';
else
hsync <= '1';
end if;
-- Vsync
if vcount >= (600+1) and vcount < (600+1+4) then
vsync <= '0';
else
vsync <= '1';
end if;
-- Colors
if hcount < 800 and vcount < 600 then
if SW='1' then
red <= hcount(3 downto 0);
green <= "0000";
blue <= vcount(3 downto 0);
else
if (hcount(0) xor vcount(0)) = '1' then
red <= "1111";
green <= "1111";
blue <= "1111";
else
red <= "0000";
green <= "0000";
blue <= "0000";
end if;
end if;
else
red <= "0000";
green <= "0000";
blue <= "0000";
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
ee5f5fffd133748db16e820aaa6b6bd2
| 0.550917 | 2.938662 | false | false | false | false |
meriororen/i2s-interface-vhdl
|
i2s_tb.vhd
| 1 | 4,026 |
library ieee;
use ieee.std_logic_1164.all;
entity i2s_tb is
generic ( DATA_WIDTH : integer := 24;
BITPERFRAME : integer := 64);
end i2s_tb;
architecture behavioral of i2s_tb is
signal clk_50 : std_logic;
signal dac_d : std_logic;
signal adc_d : std_logic;
signal bclk : std_logic;
signal lrclk : std_logic;
signal dstim : std_logic_vector(63 downto 0) := x"aaaaeeeebbbb5555";
signal sample : std_logic_vector(DATA_WIDTH - 1 downto 0) := x"fafafa";
constant period : time := 20 ns;
constant bclk_period : time := 32552 ns / BITPERFRAME;
signal zbclk, zzbclk, zzzbclk : std_logic;
signal neg_edge, pos_edge : std_logic;
signal wdth : integer := DATA_WIDTH;
signal cnt : integer := 0;
signal toggle : std_logic := '1';
signal new_sample : std_logic := '0';
signal sample_out : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal valid : std_logic;
signal ready : std_logic := '1';
signal rst : std_logic := '0';
component i2s_interface is
generic ( DATA_WIDTH : integer range 16 to 32;
BITPERFRAME: integer );
port (
clk : in std_logic;
reset : in std_logic;
bclk : in std_logic;
lrclk : in std_logic;
sample_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
sample_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
dac_data : out std_logic;
adc_data : in std_logic;
valid : out std_logic;
ready : out std_logic
);
end component;
begin
-- Instantiate
DUT : i2s_interface
generic map ( DATA_WIDTH => DATA_WIDTH,
BITPERFRAME => BITPERFRAME )
port map (
clk => clk_50,
reset => rst,
bclk => bclk,
lrclk => lrclk,
sample_out => sample_out,
sample_in => sample,
dac_data => dac_d,
adc_data => adc_d,
valid => valid,
ready => ready
);
clk_proc : process
begin
clk_50 <= '0';
wait for period/2;
clk_50 <= '1';
wait for period/2;
end process;
-- lrclk <= lrstim(lrstim'high);
i2s_bclk : process
begin
bclk <= '0';
-- lrstim <= lrstim(lrstim'high - 1 downto 0) & lrstim(lrstim'high);
wait for bclk_period/2;
-- lrstim <= lrstim(lrstim'high - 1 downto 0) & lrstim(lrstim'high);
bclk <= '1';
wait for bclk_period/2;
end process;
detect : process(clk_50)
begin
if rising_edge(clk_50) then
zbclk <= bclk;
zzbclk <= zbclk;
zzzbclk <= zzbclk;
if zzbclk = '1' and zzzbclk = '0' then
neg_edge <= '1';
elsif zzbclk = '0' and zzzbclk = '1' then
pos_edge <= '1';
else
neg_edge <= '0';
pos_edge <= '0';
end if;
end if;
end process;
lrclk <= toggle;
i2s_lrclk : process(bclk)
begin
if rising_edge(bclk) then
if cnt < BITPERFRAME/2 - 1 then
cnt <= cnt + 1;
elsif cnt = BITPERFRAME/2 - 1 then
cnt <= 0;
end if;
end if;
if falling_edge(bclk) then
if cnt >= BITPERFRAME/2 - 1 then
toggle <= not toggle;
else
if cnt = 0 then
new_sample <= '1';
elsif cnt >= wdth then
new_sample <= '0';
end if;
end if;
end if;
end process;
adc_d <= dstim(dstim'high);
i2s_data : process(bclk)
begin
if falling_edge(bclk) then
if new_sample = '1' then
dstim <= dstim(dstim'high - 1 downto 0) & dstim(dstim'high);
end if;
end if;
if rising_edge(clk_50) then
if ready = '1' then
sample <= dstim(dstim'high downto dstim'high - DATA_WIDTH + 1);
else
sample <= (others => '0');
end if;
end if;
end process;
end behavioral;
|
gpl-2.0
|
1a6a91843db5d4bf45dbc2306d66a4cc
| 0.517884 | 3.441026 | false | false | false | false |
arthurbenemann/fpga-bits
|
fm_transmitter/netgen/synthesis/topModule_synthesis.vhd
| 1 | 36,462 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: topModule_synthesis.vhd
-- /___/ /\ Timestamp: Fri Feb 26 15:16:56 2016
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm topModule -w -dir netgen/synthesis -ofmt vhdl -sim topModule.ngc topModule_synthesis.vhd
-- Device : xc6slx9-2-tqg144
-- Input file : topModule.ngc
-- Output file : C:\Users\Arthur\Documents\GitHub\fpga-bits\fm_transmitter\netgen\synthesis\topModule_synthesis.vhd
-- # of Entities : 1
-- Design Name : topModule
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity topModule is
port (
CLK : in STD_LOGIC := 'X';
GPIO0 : out STD_LOGIC;
AUDIO1_RIGHT : out STD_LOGIC;
AUDIO1_LEFT : out STD_LOGIC
);
end topModule;
architecture Structure of topModule is
component counter
port (
clk : in STD_LOGIC := 'X';
q : out STD_LOGIC_VECTOR ( 27 downto 0 )
);
end component;
component rom_memory
port (
clka : in STD_LOGIC := 'X';
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
douta : out STD_LOGIC_VECTOR ( 8 downto 0 )
);
end component;
component phase_adder
port (
clk : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 31 downto 0 );
b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component;
signal clk_272 : STD_LOGIC;
signal clk_32 : STD_LOGIC;
signal GPIO0_OBUF_3 : STD_LOGIC;
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal clock_manager_clkfx : STD_LOGIC;
signal clock_manager_clk0 : STD_LOGIC;
signal clock_manager_clkin1 : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_10_bdd8 : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_11_bdd0 : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_4_Q : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_5_Q : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_6_Q : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_7_Q : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_8_Q : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_9_Q : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_10_Q : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_11_Q : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_12_Q : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_13_Q : STD_LOGIC;
signal Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_15_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_4_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_5_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_6_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_7_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_8_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_9_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_10_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_11_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_12_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_13_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_15_Q : STD_LOGIC;
signal Inst_fm_modulator_ph_shift_2_Q : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_CLK2X180_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_CLK2X_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_CLK180_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_CLK270_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_CLKFX180_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_CLKDV_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_CLK90_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_STATUS_7_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_STATUS_6_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_STATUS_5_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_STATUS_4_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_STATUS_3_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_STATUS_2_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_STATUS_1_UNCONNECTED : STD_LOGIC;
signal NLW_clock_manager_dcm_sp_inst_STATUS_0_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_11_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_10_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_9_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_8_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_7_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_6_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_5_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_4_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_3_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_2_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_1_UNCONNECTED : STD_LOGIC;
signal NLW_addr_counter1_q_0_UNCONNECTED : STD_LOGIC;
signal addr_counter : STD_LOGIC_VECTOR ( 27 downto 12 );
signal douta : STD_LOGIC_VECTOR ( 8 downto 8 );
signal Inst_audio_dac_8bit_sum : STD_LOGIC_VECTOR ( 9 downto 0 );
signal audio_data_signed : STD_LOGIC_VECTOR ( 8 downto 0 );
signal Inst_fm_modulator_ph_shift_data : STD_LOGIC_VECTOR ( 12 downto 4 );
signal Inst_fm_modulator_sum : STD_LOGIC_VECTOR ( 30 downto 0 );
signal Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
signal Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut : STD_LOGIC_VECTOR ( 8 downto 0 );
signal Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT : STD_LOGIC_VECTOR ( 8 downto 0 );
signal Inst_audio_dac_8bit_unsigned_data : STD_LOGIC_VECTOR ( 8 downto 8 );
begin
XST_VCC : VCC
port map (
P => N0
);
XST_GND : GND
port map (
G => N1
);
clock_manager_clkout1_buf : BUFG
port map (
O => clk_272,
I => clock_manager_clkfx
);
clock_manager_clkout2_buf : BUFG
port map (
O => clk_32,
I => clock_manager_clk0
);
clock_manager_dcm_sp_inst : DCM_SP
generic map(
CLKDV_DIVIDE => 2.000000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 10,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250000,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DSS_MODE => "NONE",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"0000",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE
)
port map (
CLK2X180 => NLW_clock_manager_dcm_sp_inst_CLK2X180_UNCONNECTED,
PSCLK => N1,
CLK2X => NLW_clock_manager_dcm_sp_inst_CLK2X_UNCONNECTED,
CLKFX => clock_manager_clkfx,
CLK180 => NLW_clock_manager_dcm_sp_inst_CLK180_UNCONNECTED,
CLK270 => NLW_clock_manager_dcm_sp_inst_CLK270_UNCONNECTED,
RST => N1,
PSINCDEC => N1,
CLKIN => clock_manager_clkin1,
CLKFB => clk_32,
PSEN => N1,
CLK0 => clock_manager_clk0,
CLKFX180 => NLW_clock_manager_dcm_sp_inst_CLKFX180_UNCONNECTED,
CLKDV => NLW_clock_manager_dcm_sp_inst_CLKDV_UNCONNECTED,
PSDONE => NLW_clock_manager_dcm_sp_inst_PSDONE_UNCONNECTED,
CLK90 => NLW_clock_manager_dcm_sp_inst_CLK90_UNCONNECTED,
LOCKED => NLW_clock_manager_dcm_sp_inst_LOCKED_UNCONNECTED,
DSSEN => N1,
STATUS(7) => NLW_clock_manager_dcm_sp_inst_STATUS_7_UNCONNECTED,
STATUS(6) => NLW_clock_manager_dcm_sp_inst_STATUS_6_UNCONNECTED,
STATUS(5) => NLW_clock_manager_dcm_sp_inst_STATUS_5_UNCONNECTED,
STATUS(4) => NLW_clock_manager_dcm_sp_inst_STATUS_4_UNCONNECTED,
STATUS(3) => NLW_clock_manager_dcm_sp_inst_STATUS_3_UNCONNECTED,
STATUS(2) => NLW_clock_manager_dcm_sp_inst_STATUS_2_UNCONNECTED,
STATUS(1) => NLW_clock_manager_dcm_sp_inst_STATUS_1_UNCONNECTED,
STATUS(0) => NLW_clock_manager_dcm_sp_inst_STATUS_0_UNCONNECTED
);
clock_manager_clkin1_buf : IBUFG
generic map(
CAPACITANCE => "DONT_CARE",
IBUF_DELAY_VALUE => "0",
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT"
)
port map (
I => CLK,
O => clock_manager_clkin1
);
Inst_fm_modulator_ph_shift_15 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_15_Q,
Q => Inst_fm_modulator_ph_shift_15_Q
);
Inst_fm_modulator_ph_shift_13 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_13_Q,
Q => Inst_fm_modulator_ph_shift_13_Q
);
Inst_fm_modulator_ph_shift_12 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_12_Q,
Q => Inst_fm_modulator_ph_shift_12_Q
);
Inst_fm_modulator_ph_shift_11 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_11_Q,
Q => Inst_fm_modulator_ph_shift_11_Q
);
Inst_fm_modulator_ph_shift_10 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_10_Q,
Q => Inst_fm_modulator_ph_shift_10_Q
);
Inst_fm_modulator_ph_shift_9 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_9_Q,
Q => Inst_fm_modulator_ph_shift_9_Q
);
Inst_fm_modulator_ph_shift_8 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_8_Q,
Q => Inst_fm_modulator_ph_shift_8_Q
);
Inst_fm_modulator_ph_shift_7 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_7_Q,
Q => Inst_fm_modulator_ph_shift_7_Q
);
Inst_fm_modulator_ph_shift_6 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_6_Q,
Q => Inst_fm_modulator_ph_shift_6_Q
);
Inst_fm_modulator_ph_shift_5 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_5_Q,
Q => Inst_fm_modulator_ph_shift_5_Q
);
Inst_fm_modulator_ph_shift_4 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_4_Q,
Q => Inst_fm_modulator_ph_shift_4_Q
);
Inst_fm_modulator_ph_shift_2 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => N0,
Q => Inst_fm_modulator_ph_shift_2_Q
);
Inst_fm_modulator_ph_shift_data_12 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => audio_data_signed(8),
Q => Inst_fm_modulator_ph_shift_data(12)
);
Inst_fm_modulator_ph_shift_data_11 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => audio_data_signed(7),
Q => Inst_fm_modulator_ph_shift_data(11)
);
Inst_fm_modulator_ph_shift_data_10 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => audio_data_signed(6),
Q => Inst_fm_modulator_ph_shift_data(10)
);
Inst_fm_modulator_ph_shift_data_9 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => audio_data_signed(5),
Q => Inst_fm_modulator_ph_shift_data(9)
);
Inst_fm_modulator_ph_shift_data_8 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => audio_data_signed(4),
Q => Inst_fm_modulator_ph_shift_data(8)
);
Inst_fm_modulator_ph_shift_data_7 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => audio_data_signed(3),
Q => Inst_fm_modulator_ph_shift_data(7)
);
Inst_fm_modulator_ph_shift_data_6 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => audio_data_signed(2),
Q => Inst_fm_modulator_ph_shift_data(6)
);
Inst_fm_modulator_ph_shift_data_5 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => audio_data_signed(1),
Q => Inst_fm_modulator_ph_shift_data(5)
);
Inst_fm_modulator_ph_shift_data_4 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => audio_data_signed(0),
Q => Inst_fm_modulator_ph_shift_data(4)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_xor_8_Q : XORCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(7),
LI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(8),
O => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(8)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy_8_Q : MUXCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(7),
DI => Inst_audio_dac_8bit_sum(8),
S => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(8),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(8)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut_8_Q : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Inst_audio_dac_8bit_sum(8),
I1 => Inst_audio_dac_8bit_unsigned_data(8),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(8)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_xor_7_Q : XORCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(6),
LI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(7),
O => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(7)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy_7_Q : MUXCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(6),
DI => Inst_audio_dac_8bit_sum(7),
S => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(7),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(7)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut_7_Q : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Inst_audio_dac_8bit_sum(7),
I1 => Inst_fm_modulator_ph_shift_data(11),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(7)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_xor_6_Q : XORCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(5),
LI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(6),
O => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(6)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy_6_Q : MUXCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(5),
DI => Inst_audio_dac_8bit_sum(6),
S => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(6),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(6)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut_6_Q : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Inst_audio_dac_8bit_sum(6),
I1 => Inst_fm_modulator_ph_shift_data(10),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(6)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_xor_5_Q : XORCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(4),
LI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(5),
O => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(5)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy_5_Q : MUXCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(4),
DI => Inst_audio_dac_8bit_sum(5),
S => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(5),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(5)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut_5_Q : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Inst_audio_dac_8bit_sum(5),
I1 => Inst_fm_modulator_ph_shift_data(9),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(5)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_xor_4_Q : XORCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(3),
LI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(4),
O => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(4)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy_4_Q : MUXCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(3),
DI => Inst_audio_dac_8bit_sum(4),
S => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(4),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(4)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut_4_Q : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Inst_audio_dac_8bit_sum(4),
I1 => Inst_fm_modulator_ph_shift_data(8),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(4)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_xor_3_Q : XORCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(2),
LI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(3),
O => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(3)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy_3_Q : MUXCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(2),
DI => Inst_audio_dac_8bit_sum(3),
S => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(3),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(3)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut_3_Q : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Inst_audio_dac_8bit_sum(3),
I1 => Inst_fm_modulator_ph_shift_data(7),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(3)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_xor_2_Q : XORCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(1),
LI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(2),
O => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(2)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy_2_Q : MUXCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(1),
DI => Inst_audio_dac_8bit_sum(2),
S => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(2),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(2)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut_2_Q : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Inst_audio_dac_8bit_sum(2),
I1 => Inst_fm_modulator_ph_shift_data(6),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(2)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_xor_1_Q : XORCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(0),
LI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(1),
O => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(1)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy_1_Q : MUXCY
port map (
CI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(0),
DI => Inst_audio_dac_8bit_sum(1),
S => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(1),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(1)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut_1_Q : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Inst_audio_dac_8bit_sum(1),
I1 => Inst_fm_modulator_ph_shift_data(5),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(1)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_xor_0_Q : XORCY
port map (
CI => N1,
LI => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(0),
O => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(0)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy_0_Q : MUXCY
port map (
CI => N1,
DI => Inst_audio_dac_8bit_sum(0),
S => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(0),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(0)
);
Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut_0_Q : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Inst_audio_dac_8bit_sum(0),
I1 => Inst_fm_modulator_ph_shift_data(4),
O => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_lut(0)
);
Inst_audio_dac_8bit_sum_9 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_audio_dac_8bit_Madd_GND_16_o_GND_16_o_add_1_OUT_cy(8),
Q => Inst_audio_dac_8bit_sum(9)
);
Inst_audio_dac_8bit_sum_8 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(8),
Q => Inst_audio_dac_8bit_sum(8)
);
Inst_audio_dac_8bit_sum_7 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(7),
Q => Inst_audio_dac_8bit_sum(7)
);
Inst_audio_dac_8bit_sum_6 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(6),
Q => Inst_audio_dac_8bit_sum(6)
);
Inst_audio_dac_8bit_sum_5 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(5),
Q => Inst_audio_dac_8bit_sum(5)
);
Inst_audio_dac_8bit_sum_4 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(4),
Q => Inst_audio_dac_8bit_sum(4)
);
Inst_audio_dac_8bit_sum_3 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(3),
Q => Inst_audio_dac_8bit_sum(3)
);
Inst_audio_dac_8bit_sum_2 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(2),
Q => Inst_audio_dac_8bit_sum(2)
);
Inst_audio_dac_8bit_sum_1 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(1),
Q => Inst_audio_dac_8bit_sum(1)
);
Inst_audio_dac_8bit_sum_0 : FD
generic map(
INIT => '0'
)
port map (
C => clk_32,
D => Inst_audio_dac_8bit_GND_16_o_GND_16_o_add_1_OUT(0),
Q => Inst_audio_dac_8bit_sum(0)
);
Inst_audio_dac_8bit_unsigned_data_8 : FD
port map (
C => clk_32,
D => douta(8),
Q => Inst_audio_dac_8bit_unsigned_data(8)
);
Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_10_51 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(4),
I1 => Inst_fm_modulator_ph_shift_data(5),
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_10_bdd8
);
Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_11_2 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(11),
I1 => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_11_bdd0,
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_11_Q
);
Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_10_1 : LUT6
generic map(
INIT => X"AAA9AAA9AAA9A9A9"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(10),
I1 => Inst_fm_modulator_ph_shift_data(9),
I2 => Inst_fm_modulator_ph_shift_data(8),
I3 => Inst_fm_modulator_ph_shift_data(7),
I4 => Inst_fm_modulator_ph_shift_data(6),
I5 => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_10_bdd8,
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_10_Q
);
Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_11_11 : LUT6
generic map(
INIT => X"0000000101010101"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(10),
I1 => Inst_fm_modulator_ph_shift_data(9),
I2 => Inst_fm_modulator_ph_shift_data(8),
I3 => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_10_bdd8,
I4 => Inst_fm_modulator_ph_shift_data(6),
I5 => Inst_fm_modulator_ph_shift_data(7),
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_11_bdd0
);
Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_12_1 : LUT3
generic map(
INIT => X"65"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(12),
I1 => Inst_fm_modulator_ph_shift_data(11),
I2 => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_11_bdd0,
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_12_Q
);
Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_13_1 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(12),
I1 => Inst_fm_modulator_ph_shift_data(11),
I2 => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_11_bdd0,
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_13_Q
);
Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_15_1 : LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(11),
I1 => Inst_fm_modulator_ph_shift_data(12),
I2 => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_11_bdd0,
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_15_Q
);
Inst_fm_modulator_Madd_GND_18_o_ph_shift_data_31_add_0_OUT_xor_5_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(5),
I1 => Inst_fm_modulator_ph_shift_data(4),
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_5_Q
);
GPIO0_OBUF : OBUF
port map (
I => GPIO0_OBUF_3,
O => GPIO0
);
AUDIO1_RIGHT_OBUF : OBUF
port map (
I => Inst_audio_dac_8bit_sum(9),
O => AUDIO1_RIGHT
);
AUDIO1_LEFT_OBUF : OBUF
port map (
I => Inst_audio_dac_8bit_sum(9),
O => AUDIO1_LEFT
);
Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_6_1 : LUT3
generic map(
INIT => X"95"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(6),
I1 => Inst_fm_modulator_ph_shift_data(4),
I2 => Inst_fm_modulator_ph_shift_data(5),
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_6_Q
);
Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_7_1 : LUT4
generic map(
INIT => X"5666"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(7),
I1 => Inst_fm_modulator_ph_shift_data(6),
I2 => Inst_fm_modulator_ph_shift_data(4),
I3 => Inst_fm_modulator_ph_shift_data(5),
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_7_Q
);
Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_8_1 : LUT5
generic map(
INIT => X"99959595"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(8),
I1 => Inst_fm_modulator_ph_shift_data(7),
I2 => Inst_fm_modulator_ph_shift_data(6),
I3 => Inst_fm_modulator_ph_shift_data(4),
I4 => Inst_fm_modulator_ph_shift_data(5),
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_8_Q
);
Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_9_1 : LUT6
generic map(
INIT => X"A9A9A999A999A999"
)
port map (
I0 => Inst_fm_modulator_ph_shift_data(9),
I1 => Inst_fm_modulator_ph_shift_data(8),
I2 => Inst_fm_modulator_ph_shift_data(7),
I3 => Inst_fm_modulator_ph_shift_data(6),
I4 => Inst_fm_modulator_ph_shift_data(4),
I5 => Inst_fm_modulator_ph_shift_data(5),
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_9_Q
);
Mxor_audio_data_signed_8_xo_0_1_INV_0 : INV
port map (
I => douta(8),
O => audio_data_signed(8)
);
Inst_fm_modulator_Madd_GND_18_o_ph_shift_data_31_add_0_OUT_xor_4_11_INV_0 : INV
port map (
I => Inst_fm_modulator_ph_shift_data(4),
O => Inst_fm_modulator_GND_18_o_ph_shift_data_31_add_0_OUT_4_Q
);
addr_counter1 : counter
port map (
clk => clk_32,
q(27) => addr_counter(27),
q(26) => addr_counter(26),
q(25) => addr_counter(25),
q(24) => addr_counter(24),
q(23) => addr_counter(23),
q(22) => addr_counter(22),
q(21) => addr_counter(21),
q(20) => addr_counter(20),
q(19) => addr_counter(19),
q(18) => addr_counter(18),
q(17) => addr_counter(17),
q(16) => addr_counter(16),
q(15) => addr_counter(15),
q(14) => addr_counter(14),
q(13) => addr_counter(13),
q(12) => addr_counter(12),
q(11) => NLW_addr_counter1_q_11_UNCONNECTED,
q(10) => NLW_addr_counter1_q_10_UNCONNECTED,
q(9) => NLW_addr_counter1_q_9_UNCONNECTED,
q(8) => NLW_addr_counter1_q_8_UNCONNECTED,
q(7) => NLW_addr_counter1_q_7_UNCONNECTED,
q(6) => NLW_addr_counter1_q_6_UNCONNECTED,
q(5) => NLW_addr_counter1_q_5_UNCONNECTED,
q(4) => NLW_addr_counter1_q_4_UNCONNECTED,
q(3) => NLW_addr_counter1_q_3_UNCONNECTED,
q(2) => NLW_addr_counter1_q_2_UNCONNECTED,
q(1) => NLW_addr_counter1_q_1_UNCONNECTED,
q(0) => NLW_addr_counter1_q_0_UNCONNECTED
);
waveform_rom : rom_memory
port map (
clka => clk_32,
addra(15) => addr_counter(27),
addra(14) => addr_counter(26),
addra(13) => addr_counter(25),
addra(12) => addr_counter(24),
addra(11) => addr_counter(23),
addra(10) => addr_counter(22),
addra(9) => addr_counter(21),
addra(8) => addr_counter(20),
addra(7) => addr_counter(19),
addra(6) => addr_counter(18),
addra(5) => addr_counter(17),
addra(4) => addr_counter(16),
addra(3) => addr_counter(15),
addra(2) => addr_counter(14),
addra(1) => addr_counter(13),
addra(0) => addr_counter(12),
douta(8) => douta(8),
douta(7) => audio_data_signed(7),
douta(6) => audio_data_signed(6),
douta(5) => audio_data_signed(5),
douta(4) => audio_data_signed(4),
douta(3) => audio_data_signed(3),
douta(2) => audio_data_signed(2),
douta(1) => audio_data_signed(1),
douta(0) => audio_data_signed(0)
);
Inst_fm_modulator_fast_adder : phase_adder
port map (
clk => clk_272,
a(31) => GPIO0_OBUF_3,
a(30) => Inst_fm_modulator_sum(30),
a(29) => Inst_fm_modulator_sum(29),
a(28) => Inst_fm_modulator_sum(28),
a(27) => Inst_fm_modulator_sum(27),
a(26) => Inst_fm_modulator_sum(26),
a(25) => Inst_fm_modulator_sum(25),
a(24) => Inst_fm_modulator_sum(24),
a(23) => Inst_fm_modulator_sum(23),
a(22) => Inst_fm_modulator_sum(22),
a(21) => Inst_fm_modulator_sum(21),
a(20) => Inst_fm_modulator_sum(20),
a(19) => Inst_fm_modulator_sum(19),
a(18) => Inst_fm_modulator_sum(18),
a(17) => Inst_fm_modulator_sum(17),
a(16) => Inst_fm_modulator_sum(16),
a(15) => Inst_fm_modulator_sum(15),
a(14) => Inst_fm_modulator_sum(14),
a(13) => Inst_fm_modulator_sum(13),
a(12) => Inst_fm_modulator_sum(12),
a(11) => Inst_fm_modulator_sum(11),
a(10) => Inst_fm_modulator_sum(10),
a(9) => Inst_fm_modulator_sum(9),
a(8) => Inst_fm_modulator_sum(8),
a(7) => Inst_fm_modulator_sum(7),
a(6) => Inst_fm_modulator_sum(6),
a(5) => Inst_fm_modulator_sum(5),
a(4) => Inst_fm_modulator_sum(4),
a(3) => Inst_fm_modulator_sum(3),
a(2) => Inst_fm_modulator_sum(2),
a(1) => Inst_fm_modulator_sum(1),
a(0) => Inst_fm_modulator_sum(0),
b(31) => N1,
b(30) => Inst_fm_modulator_ph_shift_2_Q,
b(29) => N1,
b(28) => N1,
b(27) => Inst_fm_modulator_ph_shift_2_Q,
b(26) => N1,
b(25) => Inst_fm_modulator_ph_shift_2_Q,
b(24) => Inst_fm_modulator_ph_shift_2_Q,
b(23) => Inst_fm_modulator_ph_shift_2_Q,
b(22) => Inst_fm_modulator_ph_shift_2_Q,
b(21) => N1,
b(20) => N1,
b(19) => N1,
b(18) => N1,
b(17) => Inst_fm_modulator_ph_shift_2_Q,
b(16) => N1,
b(15) => Inst_fm_modulator_ph_shift_15_Q,
b(14) => Inst_fm_modulator_ph_shift_13_Q,
b(13) => Inst_fm_modulator_ph_shift_13_Q,
b(12) => Inst_fm_modulator_ph_shift_12_Q,
b(11) => Inst_fm_modulator_ph_shift_11_Q,
b(10) => Inst_fm_modulator_ph_shift_10_Q,
b(9) => Inst_fm_modulator_ph_shift_9_Q,
b(8) => Inst_fm_modulator_ph_shift_8_Q,
b(7) => Inst_fm_modulator_ph_shift_7_Q,
b(6) => Inst_fm_modulator_ph_shift_6_Q,
b(5) => Inst_fm_modulator_ph_shift_5_Q,
b(4) => Inst_fm_modulator_ph_shift_4_Q,
b(3) => Inst_fm_modulator_ph_shift_2_Q,
b(2) => Inst_fm_modulator_ph_shift_2_Q,
b(1) => N1,
b(0) => N1,
s(31) => GPIO0_OBUF_3,
s(30) => Inst_fm_modulator_sum(30),
s(29) => Inst_fm_modulator_sum(29),
s(28) => Inst_fm_modulator_sum(28),
s(27) => Inst_fm_modulator_sum(27),
s(26) => Inst_fm_modulator_sum(26),
s(25) => Inst_fm_modulator_sum(25),
s(24) => Inst_fm_modulator_sum(24),
s(23) => Inst_fm_modulator_sum(23),
s(22) => Inst_fm_modulator_sum(22),
s(21) => Inst_fm_modulator_sum(21),
s(20) => Inst_fm_modulator_sum(20),
s(19) => Inst_fm_modulator_sum(19),
s(18) => Inst_fm_modulator_sum(18),
s(17) => Inst_fm_modulator_sum(17),
s(16) => Inst_fm_modulator_sum(16),
s(15) => Inst_fm_modulator_sum(15),
s(14) => Inst_fm_modulator_sum(14),
s(13) => Inst_fm_modulator_sum(13),
s(12) => Inst_fm_modulator_sum(12),
s(11) => Inst_fm_modulator_sum(11),
s(10) => Inst_fm_modulator_sum(10),
s(9) => Inst_fm_modulator_sum(9),
s(8) => Inst_fm_modulator_sum(8),
s(7) => Inst_fm_modulator_sum(7),
s(6) => Inst_fm_modulator_sum(6),
s(5) => Inst_fm_modulator_sum(5),
s(4) => Inst_fm_modulator_sum(4),
s(3) => Inst_fm_modulator_sum(3),
s(2) => Inst_fm_modulator_sum(2),
s(1) => Inst_fm_modulator_sum(1),
s(0) => Inst_fm_modulator_sum(0)
);
end Structure;
-- synthesis translate_on
|
gpl-3.0
|
79e92149e2e98818f28d21718dbbf1dd
| 0.582113 | 2.579372 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/serial_out/tb_uart.vhd
| 1 | 2,364 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:34:36 02/22/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/FPGA_temp/serial_out/tb_uart.vhd
-- Project Name: serial_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: uart
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_uart IS
END tb_uart;
ARCHITECTURE behavior OF tb_uart IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT uart
PORT(
clk : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_ready : out std_logic;
tx : out std_logic);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0) := "10101011";
signal tx_en : std_logic := '0';
--Outputs
signal tx_ready : std_logic;
signal tx : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: uart PORT MAP (
clk => clk,
tx_en => tx_en,
tx_data => tx_data,
tx_ready => tx_ready,
tx => tx
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 5 us;
-- insert stimulus here
tx_en <= '1';
wait for 5 us;
tx_en <= '0';
wait for 120 us;
tx_en <= '1';
wait for 100 us;
tx_en <= '0';
wait for 300 us;
end process;
END;
|
gpl-3.0
|
c7c9dacb7556d4b827d403e5cb55372b
| 0.588832 | 3.592705 | false | true | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/mandel_mono.vhd
| 1 | 3,637 |
--
-- Monochromatic Mandelbrot set on VGA interface
--
-- This project is trying to generate a mandelbrot set without using external memmory. There
-- are two ways in which this might be viable:
-- * VGA with 400*300*4bit = 480 kb monochromatic interface which would fit in the 576 kb of internal RAM
-- * Reduce the number of iterations to generate the pixels in real time
--
-- The pseudo-code for each iteration is:
-- xout = x*x - y*y + x0
-- yout = 2*x*y + y0
-- overflow = x*x + y*y > 2*2
--
-- Data is stored in Q2.16 as the spartan 6 DSP blocks can do 18x18 multiplication
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mandel_mono is port (
CLK : in std_logic;
DIR_UP,DIR_DOWN,DIR_LEFT,DIR_RIGHT : in std_logic;
VGA_RED,VGA_GREEN,VGA_BLUE : out STD_LOGIC_VECTOR(3 downto 0);
VGA_VSYNC,VGA_HSYNC : out STD_LOGIC;
SW : in std_logic_vector(7 downto 0);
LED : out std_logic_vector(7 downto 0));
end mandel_mono;
architecture Behavioral of mandel_mono is
component clock_manager port(
CLK_IN1 : in std_logic;
CLK_80, CLK_40 : out std_logic);
end component;
signal CLK_80, CLK_40 : std_logic;
component user_interface port(
clk,DIR_UP,DIR_DOWN,DIR_LEFT,DIR_RIGHT : in std_logic;
x_offset,y_offset : out std_logic_vector(8 downto 0));
end component;
signal x_offset,y_offset : std_logic_vector(8 downto 0);
component pixel_scaling port(
clk : in std_logic;
x_pixel : in std_logic_vector (10 downto 0);
y_pixel : in std_logic_vector (9 downto 0);
x_offset,y_offset : in std_logic_vector(8 downto 0);
x0,y0 : out std_logic_vector (17 downto 0));
end component;
signal x_pixel : std_logic_vector(10 downto 0);
signal y_pixel : std_logic_vector(9 downto 0);
signal x0,y0 : std_logic_vector (17 downto 0);
component pixel_gen port (
clk : in std_logic;
x0,y0 : in std_logic_vector(17 downto 0);
overflow_bits : out std_logic_vector(19 downto 0));
end component;
signal overflow_bits : std_logic_vector(19 downto 0);
component color_generator port (
clk : in std_logic;
overflow_bits : in STD_LOGIC_VECTOR (19 downto 0);
color_rgb : out STD_LOGIC_VECTOR (11 downto 0));
end component;
signal color_rgb : std_logic_vector(11 downto 0);
component vga800x600 port(
clk : IN std_logic;
color : in std_logic_vector(11 downto 0);
h : out std_logic_vector(10 downto 0);
v : out std_logic_vector(9 downto 0);
red,green,blue : OUT std_logic_vector(3 downto 0);
hsync,vsync : OUT std_logic);
end component;
signal vsync,hsync : std_logic;
begin
LED <= SW;
clock_manager1 : clock_manager port map(
CLK_IN1 => CLK,
CLK_80 => CLK_80,
CLK_40 => CLK_40
);
interface : user_interface PORT MAP(
CLK_40, DIR_UP=>DIR_UP,DIR_DOWN=>DIR_DOWN,DIR_LEFT=>DIR_LEFT,DIR_RIGHT=>DIR_RIGHT,
x_offset => x_offset, y_offset => y_offset
);
scaler : pixel_scaling port map(
clk => CLK_80,
x_pixel => x_pixel, y_pixel => y_pixel,
x_offset => x_offset, y_offset => y_offset,
x0 => x0, y0 => y0
);
pixel : pixel_gen port map(
clk => CLK_80,
x0 => x0, y0 => y0,
overflow_bits => overflow_bits
);
color_mapping : color_generator port map(
clk => CLK_40,
overflow_bits => overflow_bits, color_rgb => color_rgb
);
vga_port: vga800x600 port map(
clk => CLK_40,
-- input
color => color_rgb,
-- logical interface
h => x_pixel, v => y_pixel,
-- physical interface
red => VGA_RED, green => VGA_GREEN, blue => VGA_BLUE,
vsync => vsync, hsync => hsync
);
VGA_VSYNC <= vsync;
VGA_HSYNC <= hsync;
end Behavioral;
|
gpl-3.0
|
fc07118ea94075dddeff8749c4a7b585
| 0.65851 | 2.868297 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
pcie_compiler_0_serdes.vhd
| 1 | 107,048 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- megafunction wizard: %ALTGX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: alt_c3gxb
-- ============================================================
-- File Name: pcie_compiler_0_serdes.vhd
-- Megafunction Name(s):
-- alt_c3gxb
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" equalization_setting=1 equalizer_dcgain_setting=1 gxb_powerdown_width=1 hip_enable="true" loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="2" pll_inclk_period=10000 pll_multiply_by="25" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=1 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="indv" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="pipe" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="false" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="pcie_compiler_0_serdes" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_bonding="indv" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="low" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk fixedclk gxb_powerdown hip_tx_clkout pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_areset pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_elecidleinfersel rx_freqlocked rx_patterndetect rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle intended_device_family="Cyclone IV GX"
--VERSION_BEGIN 11.1SP2 cbx_alt_c3gxb 2012:01:25:21:13:53:SJ cbx_altclkbuf 2012:01:25:21:13:53:SJ cbx_altiobuf_bidir 2012:01:25:21:13:53:SJ cbx_altiobuf_in 2012:01:25:21:13:53:SJ cbx_altiobuf_out 2012:01:25:21:13:53:SJ cbx_altpll 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_decode 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stingray 2012:01:25:21:13:52:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_stratixiii 2012:01:25:21:13:53:SJ cbx_stratixv 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
LIBRARY altera_mf;
USE altera_mf.all;
LIBRARY cycloneiv_hssi;
USE cycloneiv_hssi.all;
--synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 reg 3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pcie_compiler_0_serdes_alt_c3gxb_euf8 IS
GENERIC
(
starting_channel_number : NATURAL := 0
);
PORT
(
cal_blk_clk : IN STD_LOGIC := '0';
fixedclk : IN STD_LOGIC := '0';
gxb_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
hip_tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipe8b10binvpolarity : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
pipedatavalid : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipeelecidle : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipephydonestatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipestatus : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
pll_areset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
pll_inclk : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
powerdn : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
reconfig_clk : IN STD_LOGIC := '0';
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => 'Z');
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
rx_ctrldetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => 'Z');
rx_dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
rx_elecidleinfersel : IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0');
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_syncstatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_ctrlenable : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
tx_datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_detectrxloop : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
tx_forcedispcompliance : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
tx_forceelecidle : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0')
);
END pcie_compiler_0_serdes_alt_c3gxb_euf8;
ARCHITECTURE RTL OF pcie_compiler_0_serdes_alt_c3gxb_euf8 IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "suppress_da_rule_internal=c104";
SIGNAL wire_pll0_areset : STD_LOGIC;
SIGNAL wire_w_lg_w_pll_areset_range32w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pll0_clk : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_pll0_fref : STD_LOGIC;
SIGNAL wire_pll0_icdrclk : STD_LOGIC;
SIGNAL wire_pll0_inclk : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_pll0_locked : STD_LOGIC;
SIGNAL wire_cal_blk0_nonusertocmu : STD_LOGIC;
SIGNAL wire_cent_unit0_adet : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_dpriodisableout : STD_LOGIC;
SIGNAL wire_cent_unit0_dprioout : STD_LOGIC;
SIGNAL wire_cent_unit0_fixedclk : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_quadresetout : STD_LOGIC;
SIGNAL wire_cent_unit0_rdalign : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_cent_unit0_rxanalogreset : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxanalogresetout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxcrupowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxctrl : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxdatain : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_cent_unit0_rxdatavalid : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxdigitalreset : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxdigitalresetout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxibpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxpcsdprioin : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL wire_cent_unit0_rxpcsdprioout : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL wire_cent_unit0_rxpmadprioin : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL wire_cent_unit0_rxpmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL wire_cent_unit0_rxpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxrunningdisp : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_syncstatus : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txanalogresetout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txctrl : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txdatain : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_cent_unit0_txdetectrxpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txdigitalreset : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txdigitalresetout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txdividerpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txobpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txpcsdprioin : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL wire_cent_unit0_txpcsdprioout : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL wire_cent_unit0_txpmadprioin : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL wire_cent_unit0_txpmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL wire_receive_pcs0_cdrctrlearlyeios : STD_LOGIC;
SIGNAL wire_receive_pcs0_cdrctrllocktorefclkout : STD_LOGIC;
SIGNAL wire_receive_pcs0_dprioout : STD_LOGIC_VECTOR (399 DOWNTO 0);
SIGNAL wire_receive_pcs0_hipdataout : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_receive_pcs0_hipdatavalid : STD_LOGIC;
SIGNAL wire_receive_pcs0_hipelecidle : STD_LOGIC;
SIGNAL wire_receive_pcs0_hipelecidleinfersel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_receive_pcs0_hipphydonestatus : STD_LOGIC;
SIGNAL wire_receive_pcs0_hipstatus : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_receive_pcs0_parallelfdbk : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL wire_receive_pcs0_revparallelfdbkdata : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL wire_receive_pcs0_xgmdatain : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_receive_pma0_w_lg_freqlocked337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_receive_pma0_analogtestbus : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_receive_pma0_clockout : STD_LOGIC;
SIGNAL wire_receive_pma0_diagnosticlpbkout : STD_LOGIC;
SIGNAL wire_receive_pma0_dprioout : STD_LOGIC_VECTOR (299 DOWNTO 0);
SIGNAL wire_receive_pma0_freqlocked : STD_LOGIC;
SIGNAL wire_receive_pma0_locktodata : STD_LOGIC;
SIGNAL wire_w_lg_w_lg_reconfig_togxb_busy267w326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_receive_pma0_locktorefout : STD_LOGIC;
SIGNAL wire_receive_pma0_recoverdataout : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_receive_pma0_reverselpbkout : STD_LOGIC;
SIGNAL wire_receive_pma0_signaldetect : STD_LOGIC;
SIGNAL wire_receive_pma0_testbussel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_transmit_pcs0_clkout : STD_LOGIC;
SIGNAL wire_transmit_pcs0_ctrlenable : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_transmit_pcs0_datainfull : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_transmit_pcs0_dataout : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_transmit_pcs0_dispval : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_transmit_pcs0_dprioout : STD_LOGIC_VECTOR (149 DOWNTO 0);
SIGNAL wire_transmit_pcs0_forcedisp : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_transmit_pcs0_forceelecidleout : STD_LOGIC;
SIGNAL wire_transmit_pcs0_grayelecidleinferselout : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_transmit_pcs0_hipdatain : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_transmit_pcs0_hiptxclkout : STD_LOGIC;
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_transmit_pcs0_pipeenrevparallellpbkout : STD_LOGIC;
SIGNAL wire_transmit_pcs0_pipepowerdownout : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_transmit_pcs0_pipepowerstateout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_transmit_pcs0_txdetectrx : STD_LOGIC;
SIGNAL wire_transmit_pma0_clockout : STD_LOGIC;
SIGNAL wire_transmit_pma0_datain : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_transmit_pma0_dataout : STD_LOGIC;
SIGNAL wire_transmit_pma0_dprioout : STD_LOGIC_VECTOR (299 DOWNTO 0);
SIGNAL wire_transmit_pma0_rxdetectvalidout : STD_LOGIC;
SIGNAL wire_transmit_pma0_rxfoundout : STD_LOGIC;
SIGNAL wire_transmit_pma0_seriallpbkout : STD_LOGIC;
SIGNAL fixedclk_div : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL reconfig_togxb_busy_reg : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_fixedclk_sel39w40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_fixedclk_sel39w46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_fixedclk_sel39w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_fixedclk_sel39w56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_fixedclk_sel35w36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_reconfig_togxb_busy267w268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_fixedclk_sel39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_fixedclk_enable34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_fixedclk_sel35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_reconfig_togxb_busy267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rx_analogreset_range266w336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL cal_blk_powerdown : STD_LOGIC;
SIGNAL cent_unit_quadresetout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL cent_unit_rxcrupowerdn : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cent_unit_rxibpowerdn : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cent_unit_rxpcsdprioin : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL cent_unit_rxpcsdprioout : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL cent_unit_rxpmadprioin : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL cent_unit_rxpmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL cent_unit_tx_dprioin : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL cent_unit_txdetectrxpowerdn : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cent_unit_txdividerpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cent_unit_txdprioout : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL cent_unit_txobpowerdn : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cent_unit_txpmadprioin : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL cent_unit_txpmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL fixedclk_div_in : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL fixedclk_enable : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL fixedclk_fast : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL fixedclk_sel : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL fixedclk_to_cmu : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL int_pipeenrevparallellpbkfromtx : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nonusertocmu_out : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL pipedatavalid_out : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL pipeelecidle_out : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL pll_powerdown : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_togxb_busy : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_togxb_disable : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_togxb_in : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_togxb_load : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL refclk_pma : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_analogreset_in : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rx_analogreset_out : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rx_deserclock_in : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_digitalreset_in : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rx_digitalreset_out : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rx_enapatternalign : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_locktodata : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_locktorefclk_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_out_wire : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL rx_pcs_rxfound_wire : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL rx_pcsdprioin_wire : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL rx_pcsdprioout : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL rx_phfifordenable : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_phfiforeset : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_phfifowrdisable : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_pll_pfdrefclkout_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_pma_analogtestbus : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rx_pma_clockout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_pma_recoverdataout_wire : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL rx_pmadprioin_wire : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL rx_pmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL rx_powerdown : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_powerdown_in : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rx_prbscidenable : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_reverselpbkout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_revparallelfdbkdata : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL rx_rmfiforeset : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_signaldetect_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_analogreset_out : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tx_clkout_int_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_core_clkout_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_datain_wire : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL tx_dataout_pcs_to_pma : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL tx_diagnosticlpbkin : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_digitalreset_in : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tx_digitalreset_out : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tx_dprioin_wire : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL tx_invpolarity : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_localrefclk : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_pcs_forceelecidleout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_phfiforeset : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_pipepowerdownout : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL tx_pipepowerstateout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tx_pma_fastrefclk0in : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_pma_refclk0in : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_pma_refclk0inpulse : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_pmadprioin_wire : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL tx_pmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL tx_revparallellpbken : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_rxdetectvalidout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_rxfoundout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_serialloopbackout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_txdprioout : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL txdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL txdetectrxout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL w_cent_unit_dpriodisableout1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fixedclk_fast_range38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fixedclk_fast_range45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fixedclk_fast_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fixedclk_fast_range55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rx_analogreset_range266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC
(
bandwidth_type : STRING := "AUTO";
clk0_divide_by : NATURAL := 1;
clk0_multiply_by : NATURAL := 1;
clk1_divide_by : NATURAL := 1;
clk1_multiply_by : NATURAL := 1;
clk2_divide_by : NATURAL := 1;
clk2_duty_cycle : NATURAL := 50;
clk2_multiply_by : NATURAL := 1;
DPA_DIVIDE_BY : NATURAL := 1;
DPA_MULTIPLY_BY : NATURAL := 0;
inclk0_input_frequency : NATURAL := 0;
operation_mode : STRING := "normal";
INTENDED_DEVICE_FAMILY : STRING := "Cyclone IV GX"
);
PORT
(
areset : IN STD_LOGIC := '0';
clk : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
fref : OUT STD_LOGIC;
icdrclk : OUT STD_LOGIC;
inclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
locked : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiv_hssi_calibration_block
GENERIC
(
cont_cal_mode : STRING := "false";
enable_rx_cal_tw : STRING := "false";
enable_tx_cal_tw : STRING := "false";
rtest : STRING := "false";
rx_cal_wt_value : NATURAL := 0;
send_rx_cal_status : STRING := "false";
tx_cal_wt_value : NATURAL := 1;
lpm_type : STRING := "cycloneiv_hssi_calibration_block"
);
PORT
(
calibrationstatus : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
clk : IN STD_LOGIC := '0';
nonusertocmu : OUT STD_LOGIC;
powerdn : IN STD_LOGIC := '0';
testctrl : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT cycloneiv_hssi_cmu
GENERIC
(
auto_spd_deassert_ph_fifo_rst_count : NATURAL := 0;
auto_spd_phystatus_notify_count : NATURAL := 0;
coreclk_out_gated_by_quad_reset : STRING := "false";
devaddr : NATURAL := 1;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
in_xaui_mode : STRING := "false";
portaddr : NATURAL := 1;
rx0_channel_bonding : STRING := "none";
rx0_clk1_mux_select : STRING := "recovered clock";
rx0_clk2_mux_select : STRING := "recovered clock";
rx0_clk_pd_enable : STRING := "false";
rx0_logical_to_physical_mapping : NATURAL := 0;
rx0_ph_fifo_reg_mode : STRING := "false";
rx0_ph_fifo_reset_enable : STRING := "false";
rx0_ph_fifo_user_ctrl_enable : STRING := "false";
rx0_rd_clk_mux_select : STRING := "int clock";
rx0_recovered_clk_mux_select : STRING := "recovered clock";
rx0_reset_clock_output_during_digital_reset : STRING := "false";
rx0_use_double_data_mode : STRING := "false";
rx1_logical_to_physical_mapping : NATURAL := 1;
rx2_logical_to_physical_mapping : NATURAL := 2;
rx3_logical_to_physical_mapping : NATURAL := 3;
rx_xaui_sm_backward_compatible_enable : STRING := "false";
select_refclk_dig : STRING := "false";
tx0_channel_bonding : STRING := "none";
tx0_clk_pd_enable : STRING := "false";
tx0_logical_to_physical_mapping : NATURAL := 0;
tx0_ph_fifo_reset_enable : STRING := "false";
tx0_ph_fifo_user_ctrl_enable : STRING := "false";
tx0_rd_clk_mux_select : STRING := "local";
tx0_reset_clock_output_during_digital_reset : STRING := "false";
tx0_use_double_data_mode : STRING := "false";
tx0_wr_clk_mux_select : STRING := "int_clk";
tx1_logical_to_physical_mapping : NATURAL := 1;
tx2_logical_to_physical_mapping : NATURAL := 2;
tx3_logical_to_physical_mapping : NATURAL := 3;
tx_xaui_sm_backward_compatible_enable : STRING := "false";
use_coreclk_out_post_divider : STRING := "false";
use_deskew_fifo : STRING := "false";
lpm_type : STRING := "cycloneiv_hssi_cmu"
);
PORT
(
adet : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
alignstatus : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dpriodisableout : OUT STD_LOGIC;
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
dpriooe : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC;
enabledeskew : OUT STD_LOGIC;
fiforesetrd : OUT STD_LOGIC;
fixedclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
nonuserfromcal : IN STD_LOGIC := '0';
pmacramtest : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
quadresetout : OUT STD_LOGIC;
rdalign : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rdenablesync : IN STD_LOGIC := '1';
recovclk : IN STD_LOGIC := '0';
refclkdig : IN STD_LOGIC := '0';
refclkout : OUT STD_LOGIC;
rxanalogreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rxanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxcoreclk : IN STD_LOGIC := '0';
rxcrupowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rxctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
rxdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxdatavalid : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rxdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rxdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxibpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0) := (OTHERS => '0');
rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0);
rxphfifordenable : IN STD_LOGIC := '1';
rxphfiforeset : IN STD_LOGIC := '0';
rxphfifowrdisable : IN STD_LOGIC := '0';
rxphfifox4byteselout : OUT STD_LOGIC;
rxphfifox4rdenableout : OUT STD_LOGIC;
rxphfifox4wrclkout : OUT STD_LOGIC;
rxphfifox4wrenableout : OUT STD_LOGIC;
rxpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (OTHERS => '0');
rxpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0);
rxpowerdown : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rxrunningdisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
scanclk : IN STD_LOGIC := '0';
scanmode : IN STD_LOGIC := '0';
scanshift : IN STD_LOGIC := '0';
syncstatus : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
testin : IN STD_LOGIC_VECTOR(1999 DOWNTO 0) := (OTHERS => '0');
testout : OUT STD_LOGIC_VECTOR(2399 DOWNTO 0);
txanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txclk : IN STD_LOGIC := '0';
txcoreclk : IN STD_LOGIC := '0';
txctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
txctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
txdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
txdetectrxpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
txdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdividerpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txobpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (OTHERS => '0');
txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
txphfiforddisable : IN STD_LOGIC := '0';
txphfiforeset : IN STD_LOGIC := '0';
txphfifowrenable : IN STD_LOGIC := '0';
txphfifox4byteselout : OUT STD_LOGIC;
txphfifox4rdclkout : OUT STD_LOGIC;
txphfifox4rdenableout : OUT STD_LOGIC;
txphfifox4wrenableout : OUT STD_LOGIC;
txpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (OTHERS => '0');
txpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiv_hssi_rx_pcs
GENERIC
(
align_ordered_set_based : STRING := "false";
align_pattern : STRING := "UNUSED";
align_pattern_length : NATURAL := 7;
align_to_deskew_pattern_pos_disp_only : STRING := "false";
allow_align_polarity_inversion : STRING := "false";
allow_pipe_polarity_inversion : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : NATURAL := 0;
auto_spd_phystatus_notify_count : NATURAL := 0;
bit_slip_enable : STRING := "false";
byte_order_back_compat_enable : STRING := "false";
byte_order_invalid_code_or_run_disp_error : STRING := "false";
byte_order_mode : STRING := "none";
byte_order_pad_pattern : STRING := "UNUSED";
byte_order_pattern : STRING := "UNUSED";
byte_order_pld_ctrl_enable : STRING := "false";
cdrctrl_bypass_ppm_detector_cycle : NATURAL := 0;
cdrctrl_cid_mode_enable : STRING := "false";
cdrctrl_enable : STRING := "false";
cdrctrl_mask_cycle : NATURAL := 0;
cdrctrl_min_lock_to_ref_cycle : NATURAL := 0;
cdrctrl_rxvalid_mask : STRING := "false";
channel_bonding : STRING := "none";
channel_number : NATURAL := 0;
channel_width : NATURAL := 8;
clk1_mux_select : STRING := "recovered clock";
clk2_mux_select : STRING := "recovered clock";
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false";
datapath_protocol : STRING := "basic";
dec_8b_10b_compatibility_mode : STRING := "false";
dec_8b_10b_mode : STRING := "none";
deskew_pattern : STRING := "UNUSED";
disable_auto_idle_insertion : STRING := "false";
disable_running_disp_in_word_align : STRING := "false";
disallow_kchar_after_pattern_ordered_set : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_eios_detect_priority_over_eidle_disable : STRING := "false";
elec_idle_gen1_sigdet_enable : STRING := "false";
elec_idle_infer_enable : STRING := "false";
elec_idle_num_com_detect : NATURAL := 0;
enable_bit_reversal : STRING := "false";
enable_self_test_mode : STRING := "false";
error_from_wa_or_8b_10b_select : STRING := "false";
force_signal_detect_dig : STRING := "false";
hip_enable : STRING := "false";
infiniband_invalid_code : NATURAL := 0;
insert_pad_on_underflow : STRING := "false";
logical_channel_address : NATURAL := 0;
num_align_code_groups_in_ordered_set : NATURAL := 0;
num_align_cons_good_data : NATURAL := 1;
num_align_cons_pat : NATURAL := 1;
num_align_loss_sync_error : NATURAL := 1;
ph_fifo_low_latency_enable : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
phystatus_delay : NATURAL := 0;
phystatus_reset_toggle : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : NATURAL := 0;
protocol_hint : STRING := "basic";
rate_match_back_to_back : STRING := "false";
rate_match_delete_threshold : NATURAL := 0;
rate_match_empty_threshold : NATURAL := 0;
rate_match_fifo_mode : STRING := "false";
rate_match_full_threshold : NATURAL := 0;
rate_match_insert_threshold : NATURAL := 0;
rate_match_ordered_set_based : STRING := "false";
rate_match_pattern1 : STRING := "UNUSED";
rate_match_pattern2 : STRING := "UNUSED";
rate_match_pattern_size : NATURAL := 10;
rate_match_pipe_enable : STRING := "false";
rate_match_reset_enable : STRING := "false";
rate_match_skip_set_based : STRING := "false";
rate_match_start_threshold : NATURAL := 0;
rd_clk_mux_select : STRING := "int clock";
recovered_clk_mux_select : STRING := "recovered clock";
reset_clock_output_during_digital_reset : STRING := "false";
run_length : NATURAL := 4;
run_length_enable : STRING := "false";
rx_detect_bypass : STRING := "false";
rx_phfifo_wait_cnt : NATURAL := 0;
rxstatus_error_report_mode : NATURAL := 0;
self_test_mode : STRING := "prbs7";
test_bus_sel : NATURAL := 0;
use_alignment_state_machine : STRING := "false";
use_deskew_fifo : STRING := "false";
use_double_data_mode : STRING := "false";
use_parallel_loopback : STRING := "false";
lpm_type : STRING := "cycloneiv_hssi_rx_pcs"
);
PORT
(
a1a2size : IN STD_LOGIC := '0';
a1a2sizeout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
a1detect : OUT STD_LOGIC;
a2detect : OUT STD_LOGIC;
adetectdeskew : OUT STD_LOGIC;
alignstatus : IN STD_LOGIC := '0';
alignstatussync : IN STD_LOGIC := '0';
alignstatussyncout : OUT STD_LOGIC;
bistdone : OUT STD_LOGIC;
bisterr : OUT STD_LOGIC;
bitslip : IN STD_LOGIC := '0';
bitslipboundaryselectout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
byteorderalignstatus : OUT STD_LOGIC;
cdrctrlearlyeios : OUT STD_LOGIC;
cdrctrllocktorefcl : IN STD_LOGIC := '0';
cdrctrllocktorefclkout : OUT STD_LOGIC;
clkout : OUT STD_LOGIC;
coreclk : IN STD_LOGIC := '0';
coreclkout : OUT STD_LOGIC;
ctrldetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
dataoutfull : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
digitalreset : IN STD_LOGIC := '0';
disperr : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(399 DOWNTO 0) := (OTHERS => '0');
dprioout : OUT STD_LOGIC_VECTOR(399 DOWNTO 0);
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
enabledeskew : IN STD_LOGIC := '0';
enabyteord : IN STD_LOGIC := '0';
enapatternalign : IN STD_LOGIC := '0';
errdetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
fifordin : IN STD_LOGIC := '0';
fifordout : OUT STD_LOGIC;
fiforesetrd : IN STD_LOGIC := '0';
grayelecidleinferselfromtx : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
hip8b10binvpolarity : IN STD_LOGIC := '0';
hipdataout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
hipdatavalid : OUT STD_LOGIC;
hipelecidle : OUT STD_LOGIC;
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
hipphydonestatus : OUT STD_LOGIC;
hippowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
hipstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
invpol : IN STD_LOGIC := '0';
k1detect : OUT STD_LOGIC;
k2detect : OUT STD_LOGIC;
localrefclk : IN STD_LOGIC := '0';
masterclk : IN STD_LOGIC := '0';
parallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
patterndetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
phfifooverflow : OUT STD_LOGIC;
phfifordenable : IN STD_LOGIC := '1';
phfifordenableout : OUT STD_LOGIC;
phfiforeset : IN STD_LOGIC := '0';
phfiforesetout : OUT STD_LOGIC;
phfifounderflow : OUT STD_LOGIC;
phfifowrdisable : IN STD_LOGIC := '0';
phfifowrdisableout : OUT STD_LOGIC;
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrclk : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
pipe8b10binvpolarity : IN STD_LOGIC := '0';
pipebufferstat : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC;
pipeelecidle : OUT STD_LOGIC;
pipeenrevparallellpbkfromtx : IN STD_LOGIC := '0';
pipephydonestatus : OUT STD_LOGIC;
pipepowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
pipepowerstate : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
pipestatetransdoneout : OUT STD_LOGIC;
pipestatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
pmatestbusin : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
prbscidenable : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rdalign : OUT STD_LOGIC;
recoveredclk : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revbitorderwa : IN STD_LOGIC := '0';
revbyteorderwa : IN STD_LOGIC := '0';
revparallelfdbkdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
rlv : OUT STD_LOGIC;
rmfifodatadeleted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmfifodatainserted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmfifoempty : OUT STD_LOGIC;
rmfifofull : OUT STD_LOGIC;
rmfifordena : IN STD_LOGIC := '1';
rmfiforeset : IN STD_LOGIC := '0';
rmfifowrena : IN STD_LOGIC := '1';
runningdisp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxdetectvalid : IN STD_LOGIC := '0';
rxfound : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
signaldetect : OUT STD_LOGIC;
signaldetected : IN STD_LOGIC := '0';
syncstatus : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
syncstatusdeskew : OUT STD_LOGIC;
wareset : IN STD_LOGIC := '0';
xauidelcondmet : IN STD_LOGIC := '0';
xauidelcondmetout : OUT STD_LOGIC;
xauififoovr : IN STD_LOGIC := '0';
xauififoovrout : OUT STD_LOGIC;
xauiinsertincomplete : IN STD_LOGIC := '0';
xauiinsertincompleteout : OUT STD_LOGIC;
xauilatencycomp : IN STD_LOGIC := '0';
xauilatencycompout : OUT STD_LOGIC;
xgmctrldet : OUT STD_LOGIC;
xgmctrlin : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
xgmdatavalid : OUT STD_LOGIC;
xgmrunningdisp : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiv_hssi_rx_pma
GENERIC
(
allow_serial_loopback : STRING := "false";
channel_number : NATURAL := 0;
common_mode : STRING := "0.82V";
deserialization_factor : NATURAL := 8;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "UNUSED";
enable_dpa_shift : STRING := "false";
enable_initial_phase_selection : STRING := "true";
enable_local_divider : STRING := "false";
enable_ltd : STRING := "false";
enable_ltr : STRING := "false";
enable_pd_counter_accumulate_mode : STRING := "true";
enable_second_order_loop : STRING := "false";
eq_dc_gain : NATURAL := 0;
eq_setting : NATURAL := 1;
force_signal_detect : STRING := "false";
initial_phase_value : NATURAL := 0;
logical_channel_address : NATURAL := 0;
loop_1_digital_filter : NATURAL := 8;
offset_cancellation : NATURAL := 0;
pd1_counter_setting : NATURAL := 3;
pd2_counter_setting : NATURAL := 2;
pd_rising_edge_only : STRING := "false";
phase_step_add_setting : NATURAL := 2;
phase_step_sub_setting : NATURAL := 1;
pi_frequency_selector : NATURAL := 0;
ppm_gen1_2_xcnt_en : NATURAL := 0;
ppm_post_eidle : NATURAL := 0;
ppmselect : NATURAL := 0;
protocol_hint : STRING := "basic";
send_reverse_serial_loopback_data : STRING := "false";
send_reverse_serial_loopback_recovered_clk : STRING := "false";
signal_detect_hysteresis : NATURAL := 4;
signal_detect_hysteresis_valid_threshold : NATURAL := 14;
signal_detect_loss_threshold : NATURAL := 3;
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
lpm_type : STRING := "cycloneiv_hssi_rx_pma"
);
PORT
(
analogtestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clockout : OUT STD_LOGIC;
crupowerdn : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
datastrobeout : OUT STD_LOGIC;
deserclock : IN STD_LOGIC := '0';
diagnosticlpbkout : OUT STD_LOGIC;
dpashift : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(299 DOWNTO 0) := (OTHERS => '0');
dprioout : OUT STD_LOGIC_VECTOR(299 DOWNTO 0);
freqlocked : OUT STD_LOGIC;
locktodata : IN STD_LOGIC := '0';
locktoref : IN STD_LOGIC := '0';
locktorefout : OUT STD_LOGIC;
powerdn : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
recoverdataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
reverselpbkout : OUT STD_LOGIC;
rxpmareset : IN STD_LOGIC := '0';
seriallpbkin : IN STD_LOGIC := '0';
signaldetect : OUT STD_LOGIC;
testbussel : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT cycloneiv_hssi_tx_pcs
GENERIC
(
allow_polarity_inversion : STRING := "false";
bitslip_enable : STRING := "false";
channel_bonding : STRING := "none";
channel_number : NATURAL := 0;
channel_width : NATURAL := 8;
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false";
datapath_protocol : STRING := "basic";
disable_ph_low_latency_mode : STRING := "false";
disparity_mode : STRING := "none";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_delay : NATURAL := 3;
enable_bit_reversal : STRING := "false";
enable_idle_selection : STRING := "false";
enable_phfifo_bypass : STRING := "false";
enable_reverse_parallel_loopback : STRING := "false";
enable_self_test_mode : STRING := "false";
enc_8b_10b_compatibility_mode : STRING := "false";
enc_8b_10b_mode : STRING := "none";
force_echar : STRING := "false";
force_kchar : STRING := "false";
hip_enable : STRING := "false";
logical_channel_address : NATURAL := 0;
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
pipe_voltage_swing_control : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : NATURAL := 0;
protocol_hint : STRING := "basic";
refclk_select : STRING := "local";
reset_clock_output_during_digital_reset : STRING := "false";
self_test_mode : STRING := "crpat";
use_double_data_mode : STRING := "false";
wr_clk_mux_select : STRING := "int_clk";
lpm_type : STRING := "cycloneiv_hssi_tx_pcs"
);
PORT
(
bitslipboundaryselect : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
clkout : OUT STD_LOGIC;
coreclk : IN STD_LOGIC := '0';
coreclkout : OUT STD_LOGIC;
ctrlenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
datain : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
datainfull : IN STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
detectrxloop : IN STD_LOGIC := '0';
digitalreset : IN STD_LOGIC := '0';
dispval : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(149 DOWNTO 0) := (OTHERS => '0');
dprioout : OUT STD_LOGIC_VECTOR(149 DOWNTO 0);
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
enrevparallellpbk : IN STD_LOGIC := '0';
forcedisp : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
forceelecidle : IN STD_LOGIC := '0';
forceelecidleout : OUT STD_LOGIC;
grayelecidleinferselout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hipdatain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
hipdetectrxloop : IN STD_LOGIC := '0';
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
hipforceelecidle : IN STD_LOGIC := '0';
hippowerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
hiptxclkout : OUT STD_LOGIC;
invpol : IN STD_LOGIC := '0';
localrefclk : IN STD_LOGIC := '0';
parallelfdbkout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
phfifooverflow : OUT STD_LOGIC;
phfiforddisable : IN STD_LOGIC := '0';
phfiforddisableout : OUT STD_LOGIC;
phfiforeset : IN STD_LOGIC := '0';
phfiforesetout : OUT STD_LOGIC;
phfifounderflow : OUT STD_LOGIC;
phfifowrenable : IN STD_LOGIC := '1';
phfifowrenableout : OUT STD_LOGIC;
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdclk : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
pipeenrevparallellpbkout : OUT STD_LOGIC;
pipepowerdownout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pipepowerstateout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pipestatetransdone : IN STD_LOGIC := '0';
pipetxswing : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
prbscidenable : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rdenablesync : OUT STD_LOGIC;
refclk : IN STD_LOGIC := '0';
revparallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
txdetectrx : OUT STD_LOGIC;
xgmctrl : IN STD_LOGIC := '0';
xgmctrlenable : OUT STD_LOGIC;
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiv_hssi_tx_pma
GENERIC
(
channel_number : NATURAL := 0;
common_mode : STRING := "0.65V";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "UNUSED";
enable_diagnostic_loopback : STRING := "false";
enable_reverse_serial_loopback : STRING := "false";
enable_txclkout_loopback : STRING := "false";
logical_channel_address : NATURAL := 0;
preemp_tap_1 : NATURAL := 0;
protocol_hint : STRING := "basic";
rx_detect : NATURAL := 0;
serialization_factor : NATURAL := 8;
slew_rate : STRING := "low";
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
use_rx_detect : STRING := "false";
vod_selection : NATURAL := 0;
lpm_type : STRING := "cycloneiv_hssi_tx_pma"
);
PORT
(
cgbpowerdn : IN STD_LOGIC := '0';
clockout : OUT STD_LOGIC;
datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC;
detectrxpowerdown : IN STD_LOGIC := '0';
diagnosticlpbkin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '0';
dprioin : IN STD_LOGIC_VECTOR(299 DOWNTO 0) := (OTHERS => '0');
dprioout : OUT STD_LOGIC_VECTOR(299 DOWNTO 0);
fastrefclk0in : IN STD_LOGIC := '0';
forceelecidle : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC := '0';
refclk0in : IN STD_LOGIC := '0';
refclk0inpulse : IN STD_LOGIC := '0';
reverselpbkin : IN STD_LOGIC := '0';
rxdetectclk : IN STD_LOGIC := '0';
rxdetecten : IN STD_LOGIC := '0';
rxdetectvalidout : OUT STD_LOGIC;
rxfoundout : OUT STD_LOGIC;
seriallpbkout : OUT STD_LOGIC;
txpmareset : IN STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w(0) <= wire_w_lg_w_lg_fixedclk_sel39w40w(0) AND fixedclk_div_in(0);
wire_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w(0) <= wire_w_lg_w_lg_fixedclk_sel39w46w(0) AND fixedclk_div_in(0);
wire_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w(0) <= wire_w_lg_w_lg_fixedclk_sel39w51w(0) AND fixedclk_div_in(0);
wire_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w(0) <= wire_w_lg_w_lg_fixedclk_sel39w56w(0) AND fixedclk_div_in(0);
wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w(0) <= wire_w_lg_w_lg_fixedclk_sel35w36w(0) AND fixedclk;
wire_w_lg_w_lg_fixedclk_sel39w40w(0) <= wire_w_lg_fixedclk_sel39w(0) AND wire_w_fixedclk_fast_range38w(0);
wire_w_lg_w_lg_fixedclk_sel39w46w(0) <= wire_w_lg_fixedclk_sel39w(0) AND wire_w_fixedclk_fast_range45w(0);
wire_w_lg_w_lg_fixedclk_sel39w51w(0) <= wire_w_lg_fixedclk_sel39w(0) AND wire_w_fixedclk_fast_range50w(0);
wire_w_lg_w_lg_fixedclk_sel39w56w(0) <= wire_w_lg_fixedclk_sel39w(0) AND wire_w_fixedclk_fast_range55w(0);
wire_w_lg_w_lg_fixedclk_sel35w36w(0) <= wire_w_lg_fixedclk_sel35w(0) AND wire_w_lg_fixedclk_enable34w(0);
wire_w_lg_w_lg_reconfig_togxb_busy267w268w(0) <= wire_w_lg_reconfig_togxb_busy267w(0) AND wire_w_rx_analogreset_range266w(0);
wire_w_lg_fixedclk_sel39w(0) <= fixedclk_sel(0) AND fixedclk_enable(0);
wire_w_lg_fixedclk_enable34w(0) <= NOT fixedclk_enable(0);
wire_w_lg_fixedclk_sel35w(0) <= NOT fixedclk_sel(0);
wire_w_lg_reconfig_togxb_busy267w(0) <= NOT reconfig_togxb_busy(0);
wire_w_lg_w_rx_analogreset_range266w336w(0) <= NOT wire_w_rx_analogreset_range266w(0);
wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w42w(0) <= wire_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w(0) OR wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w(0);
wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w48w(0) <= wire_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w(0) OR wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w(0);
wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w53w(0) <= wire_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w(0) OR wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w(0);
wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w58w(0) <= wire_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w(0) OR wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w(0);
cal_blk_powerdown <= '0';
cent_unit_quadresetout(0) <= ( wire_cent_unit0_quadresetout);
cent_unit_rxcrupowerdn <= ( wire_cent_unit0_rxcrupowerdown(3 DOWNTO 0));
cent_unit_rxibpowerdn <= ( wire_cent_unit0_rxibpowerdown(3 DOWNTO 0));
cent_unit_rxpcsdprioin <= ( "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& rx_pcsdprioout(399 DOWNTO 0));
cent_unit_rxpcsdprioout <= ( wire_cent_unit0_rxpcsdprioout(1599 DOWNTO 0));
cent_unit_rxpmadprioin <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & rx_pmadprioout(299 DOWNTO 0));
cent_unit_rxpmadprioout <= ( wire_cent_unit0_rxpmadprioout(1199 DOWNTO 0));
cent_unit_tx_dprioin <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & tx_txdprioout(149 DOWNTO 0));
cent_unit_txdetectrxpowerdn <= ( wire_cent_unit0_txdetectrxpowerdown(3 DOWNTO 0));
cent_unit_txdividerpowerdown <= ( wire_cent_unit0_txdividerpowerdown(3 DOWNTO 0));
cent_unit_txdprioout <= ( wire_cent_unit0_txpcsdprioout(599 DOWNTO 0));
cent_unit_txobpowerdn <= ( wire_cent_unit0_txobpowerdown(3 DOWNTO 0));
cent_unit_txpmadprioin <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & tx_pmadprioout(299 DOWNTO 0));
cent_unit_txpmadprioout <= ( wire_cent_unit0_txpmadprioout(1199 DOWNTO 0));
fixedclk_div_in <= fixedclk_div;
fixedclk_enable(0) <= reconfig_togxb_busy_reg(0);
fixedclk_fast <= (OTHERS => '1');
fixedclk_sel(0) <= reconfig_togxb_busy_reg(1);
fixedclk_to_cmu <= ( wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w58w & wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w53w & wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w48w & wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w42w);
hip_tx_clkout(0) <= ( wire_transmit_pcs0_hiptxclkout);
int_pipeenrevparallellpbkfromtx(0) <= ( wire_transmit_pcs0_pipeenrevparallellpbkout);
nonusertocmu_out(0) <= ( wire_cal_blk0_nonusertocmu);
pipedatavalid(0) <= ( pipedatavalid_out(0));
pipedatavalid_out(0) <= ( wire_receive_pcs0_hipdatavalid);
pipeelecidle(0) <= ( pipeelecidle_out(0));
pipeelecidle_out(0) <= ( wire_receive_pcs0_hipelecidle);
pipephydonestatus(0) <= ( wire_receive_pcs0_hipphydonestatus);
pipestatus <= ( wire_receive_pcs0_hipstatus);
pll_locked(0) <= ( wire_pll0_locked);
pll_powerdown <= (OTHERS => '0');
reconfig_fromgxb <= ( rx_pma_analogtestbus(4 DOWNTO 1) & wire_cent_unit0_dprioout);
reconfig_togxb_busy(0) <= reconfig_togxb(3);
reconfig_togxb_disable(0) <= reconfig_togxb(1);
reconfig_togxb_in(0) <= reconfig_togxb(0);
reconfig_togxb_load(0) <= reconfig_togxb(2);
rx_analogreset_in <= ( "000" & wire_w_lg_w_lg_reconfig_togxb_busy267w268w);
rx_analogreset_out <= ( wire_cent_unit0_rxanalogresetout(3 DOWNTO 0));
rx_ctrldetect(0) <= ( wire_receive_pcs0_hipdataout(8));
rx_dataout <= ( rx_out_wire(7 DOWNTO 0));
rx_deserclock_in(0) <= ( wire_pll0_icdrclk);
rx_digitalreset_in <= ( "000" & rx_digitalreset(0));
rx_digitalreset_out <= ( wire_cent_unit0_rxdigitalresetout(3 DOWNTO 0));
rx_enapatternalign <= (OTHERS => '0');
rx_freqlocked <= ( wire_receive_pma0_w_lg_freqlocked337w);
rx_locktodata <= (OTHERS => '0');
rx_locktorefclk_wire(0) <= ( wire_receive_pcs0_cdrctrllocktorefclkout);
rx_out_wire <= ( wire_receive_pcs0_hipdataout(7 DOWNTO 0));
rx_pcs_rxfound_wire <= ( txdetectrxout(0) & tx_rxfoundout(0));
rx_pcsdprioin_wire <= ( "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& cent_unit_rxpcsdprioout(399 DOWNTO 0));
rx_pcsdprioout <= ( "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& wire_receive_pcs0_dprioout);
rx_phfifordenable <= (OTHERS => '1');
rx_phfiforeset <= (OTHERS => '0');
rx_phfifowrdisable <= (OTHERS => '0');
rx_pll_pfdrefclkout_wire(0) <= ( wire_pll0_fref);
rx_pma_analogtestbus <= ( "0000" & wire_receive_pma0_analogtestbus(6));
rx_pma_clockout(0) <= ( wire_receive_pma0_clockout);
rx_pma_recoverdataout_wire <= ( wire_receive_pma0_recoverdataout(9 DOWNTO 0));
rx_pmadprioin_wire <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & cent_unit_rxpmadprioout(299 DOWNTO 0));
rx_pmadprioout <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & wire_receive_pma0_dprioout);
rx_powerdown <= (OTHERS => '0');
rx_powerdown_in <= ( "000" & rx_powerdown(0));
rx_prbscidenable <= (OTHERS => '0');
rx_reverselpbkout(0) <= ( wire_receive_pma0_reverselpbkout);
rx_revparallelfdbkdata <= ( wire_receive_pcs0_revparallelfdbkdata);
rx_rmfiforeset <= (OTHERS => '0');
rx_signaldetect_wire(0) <= ( wire_receive_pma0_signaldetect);
tx_analogreset_out <= ( wire_cent_unit0_txanalogresetout(3 DOWNTO 0));
tx_clkout(0) <= ( tx_core_clkout_wire(0));
tx_clkout_int_wire(0) <= ( wire_transmit_pcs0_clkout);
tx_core_clkout_wire(0) <= ( tx_clkout_int_wire(0));
tx_datain_wire <= ( tx_datain(7 DOWNTO 0));
tx_dataout(0) <= ( txdataout(0));
tx_dataout_pcs_to_pma <= ( wire_transmit_pcs0_dataout(9 DOWNTO 0));
tx_diagnosticlpbkin(0) <= ( wire_receive_pma0_diagnosticlpbkout);
tx_digitalreset_in <= ( "000" & tx_digitalreset(0));
tx_digitalreset_out <= ( wire_cent_unit0_txdigitalresetout(3 DOWNTO 0));
tx_dprioin_wire <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & cent_unit_txdprioout(149 DOWNTO 0));
tx_invpolarity <= (OTHERS => '0');
tx_localrefclk(0) <= ( wire_transmit_pma0_clockout);
tx_pcs_forceelecidleout(0) <= ( wire_transmit_pcs0_forceelecidleout);
tx_phfiforeset <= (OTHERS => '0');
tx_pipepowerdownout <= ( wire_transmit_pcs0_pipepowerdownout);
tx_pipepowerstateout <= ( wire_transmit_pcs0_pipepowerstateout);
tx_pma_fastrefclk0in(0) <= ( wire_pll0_clk(0));
tx_pma_refclk0in(0) <= ( wire_pll0_clk(1));
tx_pma_refclk0inpulse(0) <= ( wire_pll0_clk(2));
tx_pmadprioin_wire <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & cent_unit_txpmadprioout(299 DOWNTO 0));
tx_pmadprioout <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & wire_transmit_pma0_dprioout);
tx_revparallellpbken <= (OTHERS => '0');
tx_rxdetectvalidout(0) <= ( wire_transmit_pma0_rxdetectvalidout);
tx_rxfoundout(0) <= ( wire_transmit_pma0_rxfoundout);
tx_serialloopbackout(0) <= ( wire_transmit_pma0_seriallpbkout);
tx_txdprioout <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & wire_transmit_pcs0_dprioout);
txdataout(0) <= ( wire_transmit_pma0_dataout);
txdetectrxout(0) <= ( wire_transmit_pcs0_txdetectrx);
w_cent_unit_dpriodisableout1w(0) <= ( wire_cent_unit0_dpriodisableout);
wire_w_fixedclk_fast_range38w(0) <= fixedclk_fast(0);
wire_w_fixedclk_fast_range45w(0) <= fixedclk_fast(1);
wire_w_fixedclk_fast_range50w(0) <= fixedclk_fast(2);
wire_w_fixedclk_fast_range55w(0) <= fixedclk_fast(3);
wire_w_rx_analogreset_range266w(0) <= rx_analogreset(0);
wire_pll0_areset <= wire_w_lg_w_pll_areset_range32w33w(0);
wire_w_lg_w_pll_areset_range32w33w(0) <= pll_areset(0) OR pll_powerdown(0);
wire_pll0_inclk <= ( "0" & pll_inclk(0));
pll0 : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_multiply_by => 25,
clk1_divide_by => 10,
clk1_multiply_by => 25,
clk2_divide_by => 10,
clk2_duty_cycle => 20,
clk2_multiply_by => 25,
DPA_DIVIDE_BY => 2,
DPA_MULTIPLY_BY => 25,
inclk0_input_frequency => 10000,
operation_mode => "no_compensation",
INTENDED_DEVICE_FAMILY => "Cyclone IV GX"
)
PORT MAP (
areset => wire_pll0_areset,
clk => wire_pll0_clk,
fref => wire_pll0_fref,
icdrclk => wire_pll0_icdrclk,
inclk => wire_pll0_inclk,
locked => wire_pll0_locked
);
cal_blk0 : cycloneiv_hssi_calibration_block
PORT MAP (
clk => cal_blk_clk,
nonusertocmu => wire_cal_blk0_nonusertocmu,
powerdn => cal_blk_powerdown
);
wire_cent_unit0_adet <= (OTHERS => '0');
wire_cent_unit0_fixedclk <= ( "000" & fixedclk_to_cmu(0));
wire_cent_unit0_rdalign <= (OTHERS => '0');
wire_cent_unit0_rxanalogreset <= ( rx_analogreset_in(3 DOWNTO 0));
wire_cent_unit0_rxctrl <= (OTHERS => '0');
wire_cent_unit0_rxdatain <= (OTHERS => '0');
wire_cent_unit0_rxdatavalid <= (OTHERS => '0');
wire_cent_unit0_rxdigitalreset <= ( rx_digitalreset_in(3 DOWNTO 0));
wire_cent_unit0_rxpcsdprioin <= ( cent_unit_rxpcsdprioin(1599 DOWNTO 0));
wire_cent_unit0_rxpmadprioin <= ( cent_unit_rxpmadprioin(1199 DOWNTO 0));
wire_cent_unit0_rxpowerdown <= ( rx_powerdown_in(3 DOWNTO 0));
wire_cent_unit0_rxrunningdisp <= (OTHERS => '0');
wire_cent_unit0_syncstatus <= (OTHERS => '0');
wire_cent_unit0_txctrl <= (OTHERS => '0');
wire_cent_unit0_txdatain <= (OTHERS => '0');
wire_cent_unit0_txdigitalreset <= ( tx_digitalreset_in(3 DOWNTO 0));
wire_cent_unit0_txpcsdprioin <= ( cent_unit_tx_dprioin(599 DOWNTO 0));
wire_cent_unit0_txpmadprioin <= ( cent_unit_txpmadprioin(1199 DOWNTO 0));
cent_unit0 : cycloneiv_hssi_cmu
GENERIC MAP (
auto_spd_deassert_ph_fifo_rst_count => 8,
auto_spd_phystatus_notify_count => 14,
devaddr => ((((starting_channel_number / 4) + 0) MOD 32) + 1),
dprio_config_mode => "000001",
in_xaui_mode => "false",
portaddr => (((starting_channel_number + 0) / 128) + 1),
rx0_channel_bonding => "none",
rx0_clk1_mux_select => "recovered clock",
rx0_clk2_mux_select => "local reference clock",
rx0_ph_fifo_reg_mode => "true",
rx0_rd_clk_mux_select => "int clock",
rx0_recovered_clk_mux_select => "recovered clock",
rx0_reset_clock_output_during_digital_reset => "false",
rx0_use_double_data_mode => "false",
tx0_channel_bonding => "none",
tx0_rd_clk_mux_select => "central",
tx0_reset_clock_output_during_digital_reset => "false",
tx0_use_double_data_mode => "false",
tx0_wr_clk_mux_select => "int_clk",
use_coreclk_out_post_divider => "false",
use_deskew_fifo => "false"
)
PORT MAP (
adet => wire_cent_unit0_adet,
dpclk => reconfig_clk,
dpriodisable => reconfig_togxb_disable(0),
dpriodisableout => wire_cent_unit0_dpriodisableout,
dprioin => reconfig_togxb_in(0),
dprioload => reconfig_togxb_load(0),
dprioout => wire_cent_unit0_dprioout,
fixedclk => wire_cent_unit0_fixedclk,
nonuserfromcal => nonusertocmu_out(0),
quadreset => gxb_powerdown(0),
quadresetout => wire_cent_unit0_quadresetout,
rdalign => wire_cent_unit0_rdalign,
rdenablesync => wire_gnd,
recovclk => wire_gnd,
rxanalogreset => wire_cent_unit0_rxanalogreset,
rxanalogresetout => wire_cent_unit0_rxanalogresetout,
rxcrupowerdown => wire_cent_unit0_rxcrupowerdown,
rxctrl => wire_cent_unit0_rxctrl,
rxdatain => wire_cent_unit0_rxdatain,
rxdatavalid => wire_cent_unit0_rxdatavalid,
rxdigitalreset => wire_cent_unit0_rxdigitalreset,
rxdigitalresetout => wire_cent_unit0_rxdigitalresetout,
rxibpowerdown => wire_cent_unit0_rxibpowerdown,
rxpcsdprioin => wire_cent_unit0_rxpcsdprioin,
rxpcsdprioout => wire_cent_unit0_rxpcsdprioout,
rxpmadprioin => wire_cent_unit0_rxpmadprioin,
rxpmadprioout => wire_cent_unit0_rxpmadprioout,
rxpowerdown => wire_cent_unit0_rxpowerdown,
rxrunningdisp => wire_cent_unit0_rxrunningdisp,
syncstatus => wire_cent_unit0_syncstatus,
txanalogresetout => wire_cent_unit0_txanalogresetout,
txctrl => wire_cent_unit0_txctrl,
txdatain => wire_cent_unit0_txdatain,
txdetectrxpowerdown => wire_cent_unit0_txdetectrxpowerdown,
txdigitalreset => wire_cent_unit0_txdigitalreset,
txdigitalresetout => wire_cent_unit0_txdigitalresetout,
txdividerpowerdown => wire_cent_unit0_txdividerpowerdown,
txobpowerdown => wire_cent_unit0_txobpowerdown,
txpcsdprioin => wire_cent_unit0_txpcsdprioin,
txpcsdprioout => wire_cent_unit0_txpcsdprioout,
txpmadprioin => wire_cent_unit0_txpmadprioin,
txpmadprioout => wire_cent_unit0_txpmadprioout
);
wire_receive_pcs0_hipelecidleinfersel <= (OTHERS => '0');
wire_receive_pcs0_parallelfdbk <= (OTHERS => '0');
wire_receive_pcs0_xgmdatain <= (OTHERS => '0');
receive_pcs0 : cycloneiv_hssi_rx_pcs
GENERIC MAP (
align_pattern => "0101111100",
align_pattern_length => 10,
allow_align_polarity_inversion => "false",
allow_pipe_polarity_inversion => "true",
auto_spd_deassert_ph_fifo_rst_count => 8,
auto_spd_phystatus_notify_count => 14,
bit_slip_enable => "false",
byte_order_invalid_code_or_run_disp_error => "true",
byte_order_mode => "none",
byte_order_pad_pattern => "0",
byte_order_pattern => "0",
byte_order_pld_ctrl_enable => "false",
cdrctrl_bypass_ppm_detector_cycle => 1000,
cdrctrl_cid_mode_enable => "true",
cdrctrl_enable => "true",
cdrctrl_mask_cycle => 800,
cdrctrl_min_lock_to_ref_cycle => 63,
cdrctrl_rxvalid_mask => "true",
channel_bonding => "none",
channel_number => ((starting_channel_number + 0) MOD 4),
channel_width => 8,
clk1_mux_select => "recovered clock",
clk2_mux_select => "local reference clock",
core_clock_0ppm => "false",
datapath_low_latency_mode => "false",
datapath_protocol => "pipe",
dec_8b_10b_compatibility_mode => "true",
dec_8b_10b_mode => "normal",
deskew_pattern => "0",
disable_auto_idle_insertion => "false",
disable_running_disp_in_word_align => "false",
disallow_kchar_after_pattern_ordered_set => "false",
dprio_config_mode => "000001",
elec_idle_gen1_sigdet_enable => "true",
elec_idle_infer_enable => "false",
elec_idle_num_com_detect => 3,
enable_bit_reversal => "false",
enable_self_test_mode => "false",
force_signal_detect_dig => "true",
hip_enable => "true",
infiniband_invalid_code => 0,
insert_pad_on_underflow => "false",
num_align_code_groups_in_ordered_set => 0,
num_align_cons_good_data => 16,
num_align_cons_pat => 4,
num_align_loss_sync_error => 17,
ph_fifo_low_latency_enable => "true",
ph_fifo_reg_mode => "true",
protocol_hint => "pcie",
rate_match_back_to_back => "false",
rate_match_delete_threshold => 13,
rate_match_empty_threshold => 5,
rate_match_fifo_mode => "true",
rate_match_full_threshold => 20,
rate_match_insert_threshold => 11,
rate_match_ordered_set_based => "false",
rate_match_pattern1 => "11010000111010000011",
rate_match_pattern2 => "00101111000101111100",
rate_match_pattern_size => 20,
rate_match_pipe_enable => "true",
rate_match_reset_enable => "false",
rate_match_skip_set_based => "true",
rate_match_start_threshold => 7,
rd_clk_mux_select => "int clock",
recovered_clk_mux_select => "recovered clock",
run_length => 40,
run_length_enable => "true",
rx_detect_bypass => "false",
rx_phfifo_wait_cnt => 32,
rxstatus_error_report_mode => 1,
self_test_mode => "incremental",
use_alignment_state_machine => "true",
use_deskew_fifo => "false",
use_double_data_mode => "false",
use_parallel_loopback => "false"
)
PORT MAP (
a1a2size => wire_gnd,
alignstatus => wire_gnd,
alignstatussync => wire_gnd,
cdrctrlearlyeios => wire_receive_pcs0_cdrctrlearlyeios,
cdrctrllocktorefclkout => wire_receive_pcs0_cdrctrllocktorefclkout,
datain => rx_pma_recoverdataout_wire(9 DOWNTO 0),
digitalreset => rx_digitalreset_out(0),
dpriodisable => w_cent_unit_dpriodisableout1w(0),
dprioin => rx_pcsdprioin_wire(399 DOWNTO 0),
dprioout => wire_receive_pcs0_dprioout,
enabledeskew => wire_gnd,
enabyteord => wire_gnd,
enapatternalign => rx_enapatternalign(0),
fifordin => wire_gnd,
fiforesetrd => wire_gnd,
hip8b10binvpolarity => pipe8b10binvpolarity(0),
hipdataout => wire_receive_pcs0_hipdataout,
hipdatavalid => wire_receive_pcs0_hipdatavalid,
hipelecidle => wire_receive_pcs0_hipelecidle,
hipelecidleinfersel => wire_receive_pcs0_hipelecidleinfersel,
hipphydonestatus => wire_receive_pcs0_hipphydonestatus,
hippowerdown => powerdn(1 DOWNTO 0),
hipstatus => wire_receive_pcs0_hipstatus,
invpol => wire_gnd,
localrefclk => tx_localrefclk(0),
masterclk => wire_gnd,
parallelfdbk => wire_receive_pcs0_parallelfdbk,
phfifordenable => rx_phfifordenable(0),
phfiforeset => rx_phfiforeset(0),
phfifowrdisable => rx_phfifowrdisable(0),
pipeenrevparallellpbkfromtx => int_pipeenrevparallellpbkfromtx(0),
pipepowerdown => tx_pipepowerdownout(1 DOWNTO 0),
pipepowerstate => tx_pipepowerstateout(3 DOWNTO 0),
prbscidenable => rx_prbscidenable(0),
quadreset => cent_unit_quadresetout(0),
recoveredclk => rx_pma_clockout(0),
refclk => refclk_pma(0),
revbitorderwa => wire_gnd,
revparallelfdbkdata => wire_receive_pcs0_revparallelfdbkdata,
rmfifordena => wire_gnd,
rmfiforeset => rx_rmfiforeset(0),
rmfifowrena => wire_gnd,
rxdetectvalid => tx_rxdetectvalidout(0),
rxfound => rx_pcs_rxfound_wire(1 DOWNTO 0),
signaldetected => rx_signaldetect_wire(0),
xgmctrlin => wire_gnd,
xgmdatain => wire_receive_pcs0_xgmdatain
);
wire_receive_pma0_w_lg_freqlocked337w(0) <= wire_receive_pma0_freqlocked AND wire_w_lg_w_rx_analogreset_range266w336w(0);
wire_receive_pma0_locktodata <= wire_w_lg_w_lg_reconfig_togxb_busy267w326w(0);
wire_w_lg_w_lg_reconfig_togxb_busy267w326w(0) <= wire_w_lg_reconfig_togxb_busy267w(0) AND rx_locktodata(0);
wire_receive_pma0_testbussel <= "0110";
receive_pma0 : cycloneiv_hssi_rx_pma
GENERIC MAP (
allow_serial_loopback => "false",
channel_number => ((starting_channel_number + 0) MOD 4),
common_mode => "0.82V",
deserialization_factor => 10,
dprio_config_mode => "000001",
effective_data_rate => "2500 Mbps",
enable_local_divider => "false",
enable_ltd => "false",
enable_ltr => "false",
enable_second_order_loop => "false",
eq_dc_gain => 3,
eq_setting => 1,
force_signal_detect => "false",
logical_channel_address => (starting_channel_number + 0),
loop_1_digital_filter => 8,
offset_cancellation => 1,
ppm_gen1_2_xcnt_en => 1,
ppm_post_eidle => 0,
ppmselect => 8,
protocol_hint => "pcie",
signal_detect_hysteresis => 4,
signal_detect_hysteresis_valid_threshold => 14,
signal_detect_loss_threshold => 3,
termination => "OCT 100 Ohms",
use_external_termination => "false"
)
PORT MAP (
analogtestbus => wire_receive_pma0_analogtestbus,
clockout => wire_receive_pma0_clockout,
crupowerdn => cent_unit_rxcrupowerdn(0),
datain => rx_datain(0),
deserclock => rx_deserclock_in(0),
diagnosticlpbkout => wire_receive_pma0_diagnosticlpbkout,
dpriodisable => w_cent_unit_dpriodisableout1w(0),
dprioin => rx_pmadprioin_wire(299 DOWNTO 0),
dprioout => wire_receive_pma0_dprioout,
freqlocked => wire_receive_pma0_freqlocked,
locktodata => wire_receive_pma0_locktodata,
locktoref => rx_locktorefclk_wire(0),
locktorefout => wire_receive_pma0_locktorefout,
powerdn => cent_unit_rxibpowerdn(0),
ppmdetectrefclk => rx_pll_pfdrefclkout_wire(0),
recoverdataout => wire_receive_pma0_recoverdataout,
reverselpbkout => wire_receive_pma0_reverselpbkout,
rxpmareset => rx_analogreset_out(0),
seriallpbkin => tx_serialloopbackout(0),
signaldetect => wire_receive_pma0_signaldetect,
testbussel => wire_receive_pma0_testbussel
);
wire_transmit_pcs0_ctrlenable <= ( "0" & "0");
wire_transmit_pcs0_datainfull <= (OTHERS => '0');
wire_transmit_pcs0_dispval <= ( "0" & "0");
wire_transmit_pcs0_forcedisp <= ( "0" & "0");
wire_transmit_pcs0_hipdatain <= ( tx_forcedispcompliance(0) & tx_ctrlenable(0) & tx_datain_wire(7 DOWNTO 0));
transmit_pcs0 : cycloneiv_hssi_tx_pcs
GENERIC MAP (
allow_polarity_inversion => "false",
bitslip_enable => "false",
channel_bonding => "none",
channel_number => ((starting_channel_number + 0) MOD 4),
channel_width => 8,
core_clock_0ppm => "false",
datapath_low_latency_mode => "false",
datapath_protocol => "pipe",
disable_ph_low_latency_mode => "false",
disparity_mode => "new",
dprio_config_mode => "000001",
elec_idle_delay => 4,
enable_bit_reversal => "false",
enable_idle_selection => "false",
enable_reverse_parallel_loopback => "true",
enable_self_test_mode => "false",
enc_8b_10b_compatibility_mode => "true",
enc_8b_10b_mode => "normal",
hip_enable => "true",
ph_fifo_reg_mode => "true",
prbs_cid_pattern => "false",
protocol_hint => "pcie",
refclk_select => "local",
self_test_mode => "incremental",
use_double_data_mode => "false",
wr_clk_mux_select => "int_clk"
)
PORT MAP (
clkout => wire_transmit_pcs0_clkout,
ctrlenable => wire_transmit_pcs0_ctrlenable,
datainfull => wire_transmit_pcs0_datainfull,
dataout => wire_transmit_pcs0_dataout,
digitalreset => tx_digitalreset_out(0),
dispval => wire_transmit_pcs0_dispval,
dpriodisable => w_cent_unit_dpriodisableout1w(0),
dprioin => tx_dprioin_wire(149 DOWNTO 0),
dprioout => wire_transmit_pcs0_dprioout,
enrevparallellpbk => tx_revparallellpbken(0),
forcedisp => wire_transmit_pcs0_forcedisp,
forceelecidleout => wire_transmit_pcs0_forceelecidleout,
grayelecidleinferselout => wire_transmit_pcs0_grayelecidleinferselout,
hipdatain => wire_transmit_pcs0_hipdatain,
hipdetectrxloop => tx_detectrxloop(0),
hipelecidleinfersel => rx_elecidleinfersel(2 DOWNTO 0),
hipforceelecidle => tx_forceelecidle(0),
hippowerdn => powerdn(1 DOWNTO 0),
hiptxclkout => wire_transmit_pcs0_hiptxclkout,
invpol => tx_invpolarity(0),
localrefclk => tx_localrefclk(0),
phfiforddisable => wire_gnd,
phfiforeset => tx_phfiforeset(0),
phfifowrenable => wire_vcc,
pipeenrevparallellpbkout => wire_transmit_pcs0_pipeenrevparallellpbkout,
pipepowerdownout => wire_transmit_pcs0_pipepowerdownout,
pipepowerstateout => wire_transmit_pcs0_pipepowerstateout,
pipestatetransdone => wire_gnd,
quadreset => cent_unit_quadresetout(0),
refclk => refclk_pma(0),
revparallelfdbk => rx_revparallelfdbkdata(19 DOWNTO 0),
txdetectrx => wire_transmit_pcs0_txdetectrx
);
wire_transmit_pma0_datain <= ( tx_dataout_pcs_to_pma(9 DOWNTO 0));
transmit_pma0 : cycloneiv_hssi_tx_pma
GENERIC MAP (
channel_number => ((starting_channel_number + 0) MOD 4),
common_mode => "0.65V",
dprio_config_mode => "000001",
effective_data_rate => "2500 Mbps",
enable_diagnostic_loopback => "false",
enable_reverse_serial_loopback => "false",
logical_channel_address => (starting_channel_number + 0),
preemp_tap_1 => 1,
protocol_hint => "pcie",
rx_detect => 0,
serialization_factor => 10,
slew_rate => "low",
termination => "OCT 100 Ohms",
use_external_termination => "false",
use_rx_detect => "true",
vod_selection => 4
)
PORT MAP (
cgbpowerdn => cent_unit_txdividerpowerdown(0),
clockout => wire_transmit_pma0_clockout,
datain => wire_transmit_pma0_datain,
dataout => wire_transmit_pma0_dataout,
detectrxpowerdown => cent_unit_txdetectrxpowerdn(0),
diagnosticlpbkin => tx_diagnosticlpbkin(0),
dpriodisable => w_cent_unit_dpriodisableout1w(0),
dprioin => tx_pmadprioin_wire(299 DOWNTO 0),
dprioout => wire_transmit_pma0_dprioout,
fastrefclk0in => tx_pma_fastrefclk0in(0),
forceelecidle => tx_pcs_forceelecidleout(0),
powerdn => cent_unit_txobpowerdn(0),
refclk0in => tx_pma_refclk0in(0),
refclk0inpulse => tx_pma_refclk0inpulse(0),
reverselpbkin => rx_reverselpbkout(0),
rxdetecten => txdetectrxout(0),
rxdetectvalidout => wire_transmit_pma0_rxdetectvalidout,
rxfoundout => wire_transmit_pma0_rxfoundout,
seriallpbkout => wire_transmit_pma0_seriallpbkout,
txpmareset => tx_analogreset_out(0)
);
PROCESS (fixedclk)
BEGIN
IF (fixedclk = '1' AND fixedclk'event) THEN fixedclk_div <= (NOT fixedclk_div_in);
END IF;
END PROCESS;
PROCESS (fixedclk)
BEGIN
IF (fixedclk = '0' AND fixedclk'event) THEN reconfig_togxb_busy_reg <= ( reconfig_togxb_busy_reg(0) & reconfig_togxb_busy);
END IF;
END PROCESS;
END RTL; --pcie_compiler_0_serdes_alt_c3gxb_euf8
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pcie_compiler_0_serdes IS
GENERIC
(
starting_channel_number : NATURAL := 0
);
PORT
(
cal_blk_clk : IN STD_LOGIC ;
fixedclk : IN STD_LOGIC ;
gxb_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pipe8b10binvpolarity : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_areset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_inclk : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
powerdn : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
reconfig_clk : IN STD_LOGIC ;
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_elecidleinfersel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tx_ctrlenable : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
tx_detectrxloop : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_forcedispcompliance : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_forceelecidle : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
hip_tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipeelecidle : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipephydonestatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipestatus : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
rx_ctrldetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_syncstatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END pcie_compiler_0_serdes;
ARCHITECTURE RTL OF pcie_compiler_0_serdes IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
ATTRIBUTE clearbox_macroname: string;
ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt_c3gxb";
ATTRIBUTE clearbox_defparam: string;
ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "effective_data_rate=2500 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gx_channel_type=;input_clock_frequency=100.0 MHz;intended_device_family=Cyclone IV GX;intended_device_speed_grade=6;intended_device_variant=ANY;loopback_mode=none;lpm_type=alt_c3gxb;number_of_channels=1;operation_mode=duplex;pll_bandwidth_type=Auto;pll_control_width=1;pll_inclk_period=10000;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=1;protocol=pcie;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=indv;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=2500;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=false;rx_ppmselect=8;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;rx_use_clkout=false;rx_use_coreclk=false;" &
"rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_channel_bonding=indv;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=2500;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=Auto;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=low;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=4;elec_idle_infer_enable=false;enable_0ppm=false;equalization_setting=1;gxb_powerdown_width=1;hip_enable=true;iqtxrxclk_allowed=;number_of_quads=1;pll_divide_by=2;pll_multiply_by=25;reconfig_calibration=true;reconfig_fromgxb_port_width=5;reconfig_pll_control_width=1;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_deskew_pattern=0;rx_dwidth_factor=1;rx_enable_second_order_loop=false;rx_loop_1_digital_filter=8;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;top_module_name=pcie_compiler_0_serdes;tx_bitslip_enable=FALSE;tx_dwidth_factor=1;tx_use_external_termination=false;";
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire10 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire11 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire12 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire13 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT pcie_compiler_0_serdes_alt_c3gxb_euf8
GENERIC (
starting_channel_number : NATURAL
);
PORT (
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
cal_blk_clk : IN STD_LOGIC ;
pipephydonestatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_forceelecidle : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
fixedclk : IN STD_LOGIC ;
pipestatus : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_syncstatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_areset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
pipe8b10binvpolarity : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
gxb_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
hip_tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipeelecidle : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_forcedispcompliance : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_clk : IN STD_LOGIC ;
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
powerdn : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
rx_ctrldetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_ctrlenable : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_inclk : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_elecidleinfersel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tx_detectrxloop : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
rx_patterndetect <= sub_wire0(0 DOWNTO 0);
pipephydonestatus <= sub_wire1(0 DOWNTO 0);
pll_locked <= sub_wire2(0 DOWNTO 0);
reconfig_fromgxb <= sub_wire3(4 DOWNTO 0);
rx_freqlocked <= sub_wire4(0 DOWNTO 0);
pipestatus <= sub_wire5(2 DOWNTO 0);
rx_syncstatus <= sub_wire6(0 DOWNTO 0);
rx_dataout <= sub_wire7(7 DOWNTO 0);
hip_tx_clkout <= sub_wire8(0 DOWNTO 0);
pipeelecidle <= sub_wire9(0 DOWNTO 0);
tx_clkout <= sub_wire10(0 DOWNTO 0);
tx_dataout <= sub_wire11(0 DOWNTO 0);
rx_ctrldetect <= sub_wire12(0 DOWNTO 0);
pipedatavalid <= sub_wire13(0 DOWNTO 0);
pcie_compiler_0_serdes_alt_c3gxb_euf8_component : pcie_compiler_0_serdes_alt_c3gxb_euf8
GENERIC MAP (
starting_channel_number => starting_channel_number
)
PORT MAP (
reconfig_togxb => reconfig_togxb,
cal_blk_clk => cal_blk_clk,
tx_forceelecidle => tx_forceelecidle,
fixedclk => fixedclk,
rx_datain => rx_datain,
rx_digitalreset => rx_digitalreset,
pll_areset => pll_areset,
pipe8b10binvpolarity => pipe8b10binvpolarity,
tx_datain => tx_datain,
tx_digitalreset => tx_digitalreset,
gxb_powerdown => gxb_powerdown,
tx_forcedispcompliance => tx_forcedispcompliance,
reconfig_clk => reconfig_clk,
rx_analogreset => rx_analogreset,
powerdn => powerdn,
tx_ctrlenable => tx_ctrlenable,
pll_inclk => pll_inclk,
rx_elecidleinfersel => rx_elecidleinfersel,
tx_detectrxloop => tx_detectrxloop,
rx_patterndetect => sub_wire0,
pipephydonestatus => sub_wire1,
pll_locked => sub_wire2,
reconfig_fromgxb => sub_wire3,
rx_freqlocked => sub_wire4,
pipestatus => sub_wire5,
rx_syncstatus => sub_wire6,
rx_dataout => sub_wire7,
hip_tx_clkout => sub_wire8,
pipeelecidle => sub_wire9,
tx_clkout => sub_wire10,
tx_dataout => sub_wire11,
rx_ctrldetect => sub_wire12,
pipedatavalid => sub_wire13
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: IP_MODE STRING "PCIE_HIP_8"
-- Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "PCIE"
-- Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
-- Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
-- Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
-- Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
-- Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
-- Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "1"
-- Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "5"
-- Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
-- Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
-- Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0 125.0"
-- Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
-- Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
-- Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
-- Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
-- Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
-- Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x1"
-- Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
-- Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
-- Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
-- Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
-- Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
-- Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
-- Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
-- Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
-- Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
-- Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
-- Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
-- Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "Auto"
-- Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "10000"
-- Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
-- Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1"
-- Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
-- Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
-- Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
-- Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
-- Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
-- Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
-- Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
-- Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
-- Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
-- Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
-- Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
-- Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
-- Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
-- Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
-- Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
-- Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
-- Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
-- Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
-- Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
-- Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
-- Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
-- Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
-- Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
-- Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
-- Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
-- Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
-- Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
-- Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
-- Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
-- Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
-- Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
-- Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
-- Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
-- Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
-- Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
-- Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
-- Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
-- Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
-- Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
-- Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
-- Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
-- Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
-- Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
-- Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
-- Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
-- Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
-- Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
-- Retrieval info: CONSTANT: TX_SLEW_RATE STRING "low"
-- Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
-- Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
-- Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
-- Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
-- Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
-- Retrieval info: CONSTANT: enable_0ppm STRING "false"
-- Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
-- Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
-- Retrieval info: CONSTANT: hip_enable STRING "true"
-- Retrieval info: CONSTANT: iqtxrxclk_allowed STRING ""
-- Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
-- Retrieval info: CONSTANT: pll_divide_by STRING "2"
-- Retrieval info: CONSTANT: pll_multiply_by STRING "25"
-- Retrieval info: CONSTANT: reconfig_calibration STRING "true"
-- Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
-- Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1"
-- Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
-- Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
-- Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
-- Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
-- Retrieval info: CONSTANT: rx_enable_second_order_loop STRING "false"
-- Retrieval info: CONSTANT: rx_loop_1_digital_filter NUMERIC "8"
-- Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
-- Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
-- Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
-- Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
-- Retrieval info: CONSTANT: top_module_name STRING "pcie_compiler_0_serdes"
-- Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
-- Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
-- Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
-- Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
-- Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
-- Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
-- Retrieval info: USED_PORT: hip_tx_clkout 0 0 1 0 OUTPUT NODEFVAL "hip_tx_clkout[0..0]"
-- Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
-- Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
-- Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
-- Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
-- Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
-- Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
-- Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
-- Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
-- Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
-- Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
-- Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
-- Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
-- Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
-- Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
-- Retrieval info: USED_PORT: rx_elecidleinfersel 0 0 3 0 INPUT NODEFVAL "rx_elecidleinfersel[2..0]"
-- Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
-- Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
-- Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
-- Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
-- Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
-- Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
-- Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
-- Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
-- Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
-- Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
-- Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
-- Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
-- Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
-- Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
-- Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
-- Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
-- Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
-- Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
-- Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
-- Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
-- Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
-- Retrieval info: CONNECT: @rx_elecidleinfersel 0 0 3 0 rx_elecidleinfersel 0 0 3 0
-- Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
-- Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
-- Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
-- Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
-- Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
-- Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
-- Retrieval info: CONNECT: hip_tx_clkout 0 0 1 0 @hip_tx_clkout 0 0 1 0
-- Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
-- Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
-- Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
-- Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
-- Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
-- Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
-- Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
-- Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
-- Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
-- Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
-- Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
-- Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
-- Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes_inst.vhd FALSE
|
gpl-3.0
|
e3092d99b030742718056357ae691d25
| 0.729934 | 3.19804 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/flashyLights/flashyLights.vhd
| 1 | 724 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity flashyLights is
Port ( CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end flashyLights;
architecture Behavioral of flashyLights is
COMPONENT counter30 PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(29 DOWNTO 0));
END COMPONENT;
COMPONENT memmory PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
signal count : STD_LOGIC_VECTOR(29 downto 0);
begin
addr_counter : counter30 PORT MAP (
clk => CLK,
q => count
);
rom_memory : memmory
PORT MAP (
clka => CLK,
addra => count(29 downto 20),
douta => LED
);
end Behavioral;
|
gpl-3.0
|
69c55064c0df762efcf3e464da0b53da
| 0.661602 | 3.094017 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/7/projetos/projeto1/flip_flop_jk.vhd
| 1 | 926 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity flip_flop_jk is
port( J,K: in std_logic := '1';
Reset: in std_logic := '0';
Clock_enable: in std_logic := '1';
Clock: in std_logic;
Output: out std_logic);
end flip_flop_jk;
architecture Behavioral of flip_flop_jk is
signal temp: std_logic;
begin
process (Clock)
begin
if rising_edge(Clock) then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if (J='0' and K='0') then
temp <= temp;
elsif (J='0' and K='1') then
temp <= '0';
elsif (J='1' and K='0') then
temp <= '1';
elsif (J='1' and K='1') then
temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
|
mit
|
8e8908a8b356b09ee94d94b0761fc4fe
| 0.482721 | 3.561538 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SRAM_Controller/Source/Main.vhd
| 1 | 12,746 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides a test application that simply writes to and reads from the SRAM.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library SPI_Interface;
use SPI_Interface.globals.all;
entity Main is
generic
(
-- The width of the SRAM address and data.
ram_address_width: natural := 19;
ram_data_width: natural := 8
);
port
(
-- The system clock.
sysclk: in std_logic;
-- The internal SPI interface.
f_sck: in std_logic; --
f_rs: in std_logic; -- low during transmission
f_ds: in std_logic; -- low during transmission
f_mosi: in std_logic;
f_miso: out std_logic;
-- The external SPI interface.
ext_sck: in std_logic; --
ext_rs: in std_logic; -- low during transmission
ext_ds: in std_logic; -- low during transmission
ext_mosi: in std_logic;
ext_miso: out std_logic;
-- The test LED output.
test_led: out std_logic;
-- The SRAM data and control signals.
ram_we_n: out std_logic;
ram_oe_n: out std_logic;
ram_address: out unsigned(ram_address_width-1 downto 0);
ram_data: inout std_logic_vector(ram_data_width-1 downto 0);
-- The DAC control signals.
dac_clk: out std_logic;
dac_channel_select: out std_logic;
dac_write_n: out std_logic
);
end entity;
architecture stdarch of Main is
-- Configuration constants
-----------------------------------------------------------------------------
-- SPI interface.
constant use_internal_spi: boolean := true;
constant use_external_spi: boolean := false;
constant address_width: positive := 5; -- max. 8 (for addresses 0..255)
constant number_of_data_buffers: positive := 2**address_width;
-- SRAM controller.
constant num_of_total_wait_states: natural := 9; -- 90ns @ 100MHz (min 70ns)
constant num_of_write_pulse_wait_states: natural := 6; -- 60ns @ 100MHz (min 50ns)
constant num_of_wait_states_before_write_after_read: natural := 4; -- 40ns @ 100MHz (min 30ns)
-- SPI sub-address constants
-----------------------------------------------------------------------------
constant sram_subaddr: integer := 24;
-- Signals
-----------------------------------------------------------------------------
-- Clocks
signal clk_50mhz: std_logic;
signal clk_100mhz: std_logic;
-- SPI interfaces
type spi_in_type is record
mosi: std_logic;
sclk: std_logic;
ss_address: std_logic;
ss_data: std_logic;
end record;
signal selected_spi_in, internal_spi_in, external_spi_in, inactive_spi_in: spi_in_type :=
(
-- Initialize to proper idle values.
mosi => '0',
sclk => '1',
ss_address => '1',
ss_data => '1'
);
signal miso: std_logic;
-- Memory controller
signal memory_read: std_logic;
signal memory_write: std_logic;
signal memory_ready: std_logic;
signal memory_auto_increment_address: std_logic;
signal memory_auto_increment_end_address_reached: std_logic;
signal memory_address: unsigned(ram_address_width-1 downto 0);
signal memory_data_in: std_logic_vector(ram_data_width-1 downto 0);
signal memory_data_out: std_logic_vector(ram_data_width-1 downto 0);
-- Interconnection
signal transmit_data_x: data_buffer_vector(number_of_data_buffers-1 downto 0)
:= (others => (others => '0'));
signal received_data_x: data_buffer_vector(number_of_data_buffers-1 downto 0);
signal ready_x: std_logic_vector(number_of_data_buffers-1 downto 0);
begin
--------------------------------------------------------------------------------
-- Connections to and from internal signals.
--------------------------------------------------------------------------------
-- NOTE: Reading to and writing from an SPI address always happen together. Each time
-- the SPI master reads a value from the slave's transmit register, it also writes a value
-- to the slave's receive register of the same address, overwriting any previous value.
--
-- If the internal SPI connection is used, the microcontroller of the c'Lab FPGA board
-- acts as the SPI master. It accesses a particular SPI adress as follows:
-- 1) If one of the Param or Value screens is selected on the panel, the microcontroller
-- accesses the SPI bus periodically to read the value from and write the parameter to
-- the according SPI address.
-- 2) When processing a c't Lab protocol set command, the microcontroller writes the
-- according parameter to the SPI slave and ignores the value read from the SPI slave.
-- 3) When processing a c't Lab protocol query command, the microcontroller writes an
-- arbitrary parameter to the SPI slave and returns the value read from the SPI slave.
-- It happens to be that the parameter sent most recently to the same or any other SPI
-- address is reused as this arbitrary parameter.
--
-- If the external SPI connection is used, it's up to the external SPI master how to handle
-- values read from the SPI slave and how to generate parameters written to the SPI slave.
-- SPI receiver data (index 0 to 3 are also available via the FPGA panel).
-----------------------------------------------------------------------------
-- Combination of mode (5 bits), address (19 bits) and write data (8 bits).
-- Mode is sum of
-- automatic address increment: 0 = off, 8 = on
-- memory access: 0 = off, 1 = read, 2 = write
-- Here is 1 unused bit (data_buffer'high).
memory_auto_increment_address <= received_data_x(sram_subaddr)(data_buffer'high-1);
-- Here is 1 unused bit (data_buffer'high-2).
memory_write <= received_data_x(sram_subaddr)(data_buffer'high-3);
memory_read <= received_data_x(sram_subaddr)(data_buffer'high-4);
memory_address <= unsigned(received_data_x(sram_subaddr)(ram_address_width-1+ram_data_width downto ram_data_width));
memory_data_in <= received_data_x(sram_subaddr)(ram_data_width-1 downto 0);
-- SPI transmitter data (index 0 to 3 are also available via the FPGA panel).
-----------------------------------------------------------------------------
-- Combination of memory state (1 bit), memory auto-increment state (1 bit), '0' (1 bit),
-- partial mode loopback (2 bits), address loopback (19 bits) and read data (8 bits).
-- State is sum of
-- memory state: 0 = working, 16 = ready
-- memory auto-increment state: 0 = end address not reached, 8 = end address reached
-- mode loopback: 0 = off, 1 = reading, 2 = writing
transmit_data_x(sram_subaddr) <= memory_ready
& memory_auto_increment_end_address_reached
& '0'
& received_data_x(sram_subaddr)(data_buffer'high-3 downto ram_data_width)
& memory_data_out;
--------------------------------------------------------------------------------
-- SPI input selection logic.
--------------------------------------------------------------------------------
-- The internal SPI bus (i.e. the one connected to the microcontroller of the
-- c'Lab FPGA board).
internal_spi_in.mosi <= f_mosi;
internal_spi_in.sclk <= f_sck;
internal_spi_in.ss_address <= f_rs;
internal_spi_in.ss_data <= f_ds;
-- The external SPI bus (i.e. the one connected to the expansion ports of the
-- c'Lab FPGA board).
external_spi_in.mosi <= ext_mosi;
external_spi_in.sclk <= ext_sck;
external_spi_in.ss_address <= ext_rs;
external_spi_in.ss_data <= ext_ds;
-- Select the SPI connection to use.
-- NOTE: If one of the Param or Value screens is selected on the panel, the microcontroller
-- of the c'Lab FPGA board accesses the SPI bus periodically to read the value from and write
-- the parameter to the according SPI address (SPI reading and writing always happen together).
-- Thus, when both connections are activated, while using the *external* connection, set the
-- panel to the file selection screen to avoid this interference.
-- Also, when both connections are activated, while using the *internal* connection, ensure
-- that the selection pins of the external connection (ext_rs and ext_ds) are pulled up properly.
-- If they are e.g. connected to the SPI interface of a Raspberry Pi, ensure that the latter is
-- switched on. Don't leave the pins unconnected, pull them up instead.
selected_spi_in <=
internal_spi_in when use_internal_spi and
(internal_spi_in.ss_address = '0' or internal_spi_in.ss_data = '0') else
external_spi_in when use_external_spi and
(external_spi_in.ss_address = '0' or external_spi_in.ss_data = '0') else
inactive_spi_in;
--------------------------------------------------------------------------------
-- Component instantiation.
--------------------------------------------------------------------------------
-- The clock manager generating the clocks used throughout the system.
clock_manager: entity work.ClockManager
port map
(
clk => sysclk,
clk_50mhz => clk_50mhz,
clk_100mhz => clk_100mhz
);
-- The slave of the SPI interface.
slave: entity SPI_Interface.SPI_Slave
generic map
(
address_width => address_width,
synchronize_data_to_clk => true
)
port map
(
clk => clk_50mhz,
sclk => selected_spi_in.sclk,
ss_address => selected_spi_in.ss_address,
ss_data => selected_spi_in.ss_data,
transmit_data_x => transmit_data_x,
mosi => selected_spi_in.mosi,
miso => miso,
received_data_x => received_data_x,
ready_x => ready_x
);
-- The SRAM controller.
sram: entity work.SRAM_Controller
generic map
(
num_of_total_wait_states => num_of_total_wait_states,
num_of_write_pulse_wait_states => num_of_write_pulse_wait_states,
num_of_wait_states_before_write_after_read => num_of_wait_states_before_write_after_read,
data_width => ram_data_width,
address_width => ram_address_width
)
port map
(
clk => clk_100mhz,
read => memory_read,
write => memory_write,
ready => memory_ready,
auto_increment_address => memory_auto_increment_address,
auto_increment_end_address_reached => memory_auto_increment_end_address_reached,
address => memory_address,
data_in => memory_data_in,
data_out => memory_data_out,
ram_we_n => ram_we_n,
ram_oe_n => ram_oe_n,
ram_address => ram_address,
ram_data => ram_data
);
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
-- SPI & test LED.
f_miso <= miso when f_ds = '0' else 'Z';
ext_miso <= miso when ext_ds = '0' else 'Z';
test_led <= not memory_ready; -- LED is active low
-- Single and dual DAC.
dac_clk <= '1';
dac_channel_select <= '1';
dac_write_n <= '1';
end architecture;
|
gpl-3.0
|
742356c39b31ae7bae988311bb93657f
| 0.556174 | 4.314827 | false | false | false | false |
arthurTemporim/SD_SS
|
rel/4/projetos/projeto1/projeto1.vhd
| 1 | 546 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto1 is
port (
e : in std_logic_vector (3 downto 0):= "0001";
s: out std_logic_vector (6 downto 0)
);
end projeto1;
architecture Behavioral of projeto1 is
begin
s <= "0110000" when e = "0001" else
"1101101" when e = "0010" else
"1111001" when e = "0011" else
"0110010" when e = "0100" else
"1011010" when e = "0101" else
"1011111" when e = "0110" else
"1110000" when e = "0111" else
"1111111" when e = "1000" else
"1111011" when e = "1001" ;
end Behavioral;
|
mit
|
6e2c2fb8972fafe35e7827272a17e422
| 0.637363 | 2.967391 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Source/SPI_Slave.vhd
| 1 | 4,982 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides an SPI slave receiver consisting of a receiver, a transmitter, and an
-- optional synchronizer. The parallel output and input data are synchronous to
-- the system clock (CLK) so that they can be read from or written to by internal
-- components controlled by that clock. Without synchronization the system clock
-- (CLK) and the SPI shift clock (SCLK) must be related to each other and satisfy
-- specific timing requirements between each other. With synchronization there is
-- a delay of three rising system (CLK) clock edges before received data are
-- available at the parallel output. There must also be three rising system clock
-- (CLK) edges between the indication of a transmission (by SS_DATA becoming active)
-- and the beginning of that transmission (the first leading SCLK edge).
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library Common;
use work.globals.all;
entity SPI_Slave is
generic
(
-- The width of the address.
address_width: positive;
-- Indicates whether the data in- and outputs are to be synchronized to CLK.
synchronize_data_to_clk: boolean := true
);
port
(
-- The system clock.
clk: in std_logic;
-- The clock controlling the serial data transmission.
sclk: in std_logic;
-- The (active low) address slave select.
ss_address: in std_logic;
-- The (active low) data slave select.
ss_data: in std_logic;
-- The parallel inputs used to get the data to be sent from.
transmit_data_x: in data_buffer_vector((2**address_width)-1 downto 0);
-- The serial input.
mosi: in std_logic;
-- The serial output.
miso: out std_logic;
-- The parallel output for each buffer providing the data received.
received_data_x: out data_buffer_vector((2**address_width)-1 downto 0);
-- Indicates for each buffer whether the received data are stable.
ready_x: out std_logic_vector((2**address_width)-1 downto 0)
);
end entity;
architecture stdarch of SPI_Slave is
signal buffer_enable: std_logic;
signal address: unsigned(address_width-1 downto 0);
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
-- The optional synchronizer or shortcuts replacing them.
generate_synchronizer: if synchronize_data_to_clk generate
-- Synchronizes the data slave select signal to the system clock (CLK).
ss_data_synchronizer: entity Common.Synchronizer
port map
(
clk => clk,
in_async => ss_data,
out_sync => buffer_enable
);
end generate;
dont_generate_synchronizer: if not synchronize_data_to_clk generate
-- Don't synchronizes the data slave select signal.
buffer_enable <= ss_data;
end generate;
-- The receiver (holding n data buffers and an additional address buffer).
receiver: entity work.SPI_SlaveReceiver
generic map
(
address_width => address_width
)
port map
(
clk => clk,
buffer_enable => buffer_enable,
sclk => sclk,
ss_address => ss_address,
address => address,
mosi => mosi,
data_x => received_data_x,
ready_x => ready_x
);
-- The transmitter.
transmitter: entity work.SPI_SlaveTransmitter
generic map
(
address_width => address_width
)
port map
(
clk => clk,
buffer_enable => buffer_enable,
sclk => sclk,
ss => ss_data,
address => address,
data_x => transmit_data_x,
miso => miso
);
end architecture;
|
gpl-3.0
|
bb660fae6c0cc43a62b6b07f8c13beda
| 0.574267 | 4.785783 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/testbench.vhd
| 1 | 10,520 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nexys4_pack.all;
use work.boot_pack.all;
entity testbench is
end testbench;
architecture Behavioral of testbench is
component koc_wrapper is
generic (
lower_app : string := "jump";
upper_app : string := "main";
upper_ext : boolean := false);
port (
sys_clk_i : in std_logic;
sys_rst : in std_logic;
gpio_output : out std_logic_vector(data_out_width-1 downto 0);
gpio_input : in std_logic_vector(data_in_width-1 downto 0);
uart_tx : out std_logic;
uart_rx : in std_logic;
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC);
end component;
constant clock_period : time := 10 ns;
constant uart_period : time := 104166.67 ns;
constant time_out_threshold : integer := 2**30;
subtype gpio_type is std_logic_vector(data_out_width-1 downto 0);
signal sys_clk_i : std_logic := '1';
signal sys_rst : std_logic := '0';
signal gpio_output : gpio_type;
signal gpio_input : gpio_type := (others=>'0');
signal uart_tx : std_logic;
signal uart_clock : std_logic := '1';
signal uart_tx_data_avail : std_logic := '0';
signal uart_tx_data_ack : std_logic := '0';
signal uart_tx_started : boolean := false;
signal uart_tx_counter : integer range 0 to 8 := 0;
signal uart_tx_buffer : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_tx_data : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_rx : std_logic := '1';
signal uart_rx_enable : std_logic := '0';
signal uart_rx_done : std_logic := '0';
signal uart_rx_data : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_rx_counter : integer range 0 to 9 := 0;
signal boot_checksum : std_logic_vector(7 downto 0) := (others=>'0');
begin
sys_clk_i <= not sys_clk_i after clock_period/2;
sys_rst <= '1' after 10*clock_period;
koc_wrapper_inst : koc_wrapper
port map (
sys_clk_i => sys_clk_i,
sys_rst => sys_rst,
gpio_output => gpio_output,
gpio_input => gpio_input,
uart_tx => uart_tx,
uart_rx => uart_rx,
DDR2_addr => open,
DDR2_ba => open,
DDR2_cas_n => open,
DDR2_ck_n => open,
DDR2_ck_p => open,
DDR2_cke => open,
DDR2_cs_n => open,
DDR2_dm => open,
DDR2_dq => open,
DDR2_dqs_n => open,
DDR2_dqs_p => open,
DDR2_odt => open,
DDR2_ras_n => open,
DDR2_we_n => open);
-- Get uart_tx
uart_clock <= not uart_clock after uart_period/2;
process (uart_clock)
begin
if rising_edge(uart_clock) then
if uart_tx_started then
uart_tx_counter <= uart_tx_counter+1;
if uart_tx_counter=8 then
uart_tx_data <= uart_tx_buffer;
uart_tx_started <= false;
else
uart_tx_buffer(uart_tx_counter) <= uart_tx;
end if;
elsif uart_tx='0' then
uart_tx_started <= true;
uart_tx_counter <= 0;
end if;
if uart_tx_data_ack='1' then
uart_tx_data_avail <= '0';
elsif uart_tx_started and uart_tx_counter=8 then
uart_tx_data_avail <= '1';
end if;
end if;
end process;
-- Set uart_rx
uart_rx_done <= '1' when uart_rx_counter=9 else '0';
process (uart_clock)
begin
if rising_edge(uart_clock) then
if uart_rx_enable='1' then
if uart_rx_counter/=9 then
uart_rx_counter <= uart_rx_counter+1;
if uart_rx_counter=0 then
uart_rx <= '0';
elsif uart_rx_counter<= 8 then
uart_rx <= uart_rx_data(uart_rx_counter-1);
end if;
else
uart_rx <= '1';
end if;
else
uart_rx_counter <= 0;
uart_rx <= '1';
end if;
end if;
end process;
-- process
-- constant word_width : integer := 32;
-- subtype byte_type is std_logic_vector(7 downto 0);
-- subtype word_type is std_logic_vector(word_width-1 downto 0);
-- constant BOOT_LOADER_START_WORD : word_type := x"f0f0f0f0";
-- constant BOOT_LOADER_ACK_SUCCESS_BYTE : byte_type := x"01";
-- constant BOOT_LOADER_ACK_FAILURE_BYTE : byte_type := x"02";
-- constant BOOT_LOADER_STATUS_MORE : byte_type := x"01";
-- constant BOOT_LOADER_STATUS_DONE : byte_type := x"02";
-- constant BOOT_LOADER_CHECKSUM_DIVISOR : integer := 230;
-- variable word : word_type;
-- variable byte : byte_type;
-- variable app_data : ram_type := load_hex;
-- variable app_ptr : integer := 0;
-- procedure set_uart_rx( byte : in byte_type ) is
-- begin
-- uart_rx_data <= byte;
-- uart_rx_enable <= '1';
-- wait until uart_rx_done='1';
-- wait for uart_period;
-- uart_rx_enable <= '0';
-- wait for uart_period;
-- end;
-- procedure set_uart_word ( word : in word_type ) is
-- begin
-- for each_byte in 0 to word_width/8-1 loop
-- set_uart_rx(word(7+each_byte*8 downto each_byte*8));
-- end loop;
-- end;
-- procedure get_uart_tx is
-- begin
-- wait until uart_tx_data_avail='1';
-- wait for uart_period;
-- byte := uart_tx_data;
-- uart_tx_data_ack <= '1';
-- wait for uart_period;
-- uart_tx_data_ack <= '0';
-- wait for uart_period;
-- end;
-- begin
-- wait until sys_rst='1';
-- wait until gpio_output=X"0001";
-- --wait for 2 ms;
-- set_uart_word(BOOT_LOADER_START_WORD);
-- get_uart_tx;
-- if byte=BOOT_LOADER_ACK_SUCCESS_BYTE then
-- report "Success ACK";
-- elsif byte=BOOT_LOADER_ACK_FAILURE_BYTE then
-- report "Failed ACK";
-- wait;
-- else
-- report "???";
-- wait;
-- end if;
-- while true loop
-- -- instruction
-- word := app_data(app_ptr);
-- set_uart_word(word);
-- -- checksum
-- word := std_logic_vector(unsigned(word) mod BOOT_LOADER_CHECKSUM_DIVISOR);
-- boot_checksum <= word(7 downto 0);
-- set_uart_rx(word(7 downto 0));
-- -- status
-- app_ptr := app_ptr+1;
-- --if app_ptr=ram_size then
-- if app_ptr=13 then
-- set_uart_rx(BOOT_LOADER_STATUS_DONE);
-- exit;
-- else
-- set_uart_rx(BOOT_LOADER_STATUS_MORE);
-- end if;
-- -- ack
-- get_uart_tx;
-- if byte=BOOT_LOADER_ACK_SUCCESS_BYTE then
-- report "Success ACK";
-- elsif byte=BOOT_LOADER_ACK_FAILURE_BYTE then
-- report "Failed ACK";
-- wait;
-- else
-- report "???";
-- wait;
-- end if;
-- end loop;
-- wait;
-- end process;
-- Run testbench application.
process
-- This procedure should force the simulation to stop if a
-- problem becomes apparent.
procedure assert_procedure( state : boolean; mesg : string ) is
variable breaksimulation : std_logic_vector(0 downto 0);
begin
if not state then
assert False report mesg severity error;
breaksimulation(1) := '1';
end if;
end;
-- The procedure sets a single specified bit of the gpio input interface.
procedure set_gpio_input( gpio_index : integer ) is
variable gpio_input_buff : gpio_type := (others=>'0');
begin
gpio_input_buff(gpio_index) := '1';
gpio_input <= gpio_input_buff;
wait for clock_period;
end;
-- Waits for the corresponding output response. If it takes too long,
-- it is assumed there is an error and the simulation should end as a result.
procedure wait_for_gpio_output is
variable assert_counter : integer := 0;
begin
while gpio_output/=gpio_input loop
assert_procedure( state => assert_counter/=time_out_threshold, mesg => "Timeout occurred." );
assert_counter := assert_counter+1;
wait for clock_period;
end loop;
wait for clock_period;
end;
begin
wait until sys_rst='1';
wait until gpio_output=X"0001";
wait for 500 us;
gpio_input <= "0000000000111111";
while True loop
gpio_input <= X"00f1";
wait for 50 us;
gpio_input <= X"00f0";
wait for 50 us;
gpio_input <= X"00f5";
wait for 50 us;
gpio_input <= X"00ff";
wait for 50 us;
gpio_input <= X"05f7";
wait for 50 us;
gpio_input <= X"10f0";
wait for 50 us;
end loop;
wait;
end process;
end Behavioral;
|
mit
|
e0035e972726351175a34decba6b54eb
| 0.4923 | 3.745105 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
ci_bridge_0.vhd
| 1 | 12,840 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- ci_bridge_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ci_bridge_0 is
port (
clk : in std_logic := '0'; -- clock.clk
address : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_slave_0.address
byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(15 downto 0); -- .readdata
rst : in std_logic := '0'; -- reset_sink.reset
cia_reset : out std_logic; -- conduit_end.export
cib_reset : out std_logic; -- .export
cia_ce_n : out std_logic; -- .export
cib_ce_n : out std_logic; -- .export
ci_reg_n : out std_logic; -- .export
ci_a : out std_logic_vector(14 downto 0); -- .export
ci_we_n : out std_logic; -- .export
ci_oe_n : out std_logic; -- .export
ci_iowr_n : out std_logic; -- .export
ci_iord_n : out std_logic; -- .export
cia_wait_n : in std_logic := '0'; -- .export
cib_wait_n : in std_logic := '0'; -- .export
cia_ireq_n : in std_logic := '0'; -- .export
cib_ireq_n : in std_logic := '0'; -- .export
cia_cd_n : in std_logic_vector(1 downto 0) := (others => '0'); -- .export
cib_cd_n : in std_logic_vector(1 downto 0) := (others => '0'); -- .export
cia_overcurrent_n : in std_logic := '0'; -- .export
cib_overcurrent_n : in std_logic := '0'; -- .export
cia_reset_buf_oe_n : out std_logic; -- .export
cib_reset_buf_oe_n : out std_logic; -- .export
cia_data_buf_oe_n : out std_logic; -- .export
cib_data_buf_oe_n : out std_logic; -- .export
ci_bus_dir : out std_logic; -- .export
interrupt : out std_logic; -- .export
cam_interrupts : out std_logic_vector(1 downto 0); -- .export
cam0_ready : out std_logic; -- .export
cam0_bypass : out std_logic; -- .export
cam1_ready : out std_logic; -- .export
cam1_bypass : out std_logic; -- .export
cam0_fail : out std_logic; -- .export
cam1_fail : out std_logic; -- .export
ci_d_out : out std_logic_vector(7 downto 0); -- .export
ci_d_in : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
ci_d_en : out std_logic; -- .export
cam_writedata : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
cam_write : in std_logic := '0'; -- .export
cam_readdata : out std_logic_vector(7 downto 0); -- .export
cam_read : in std_logic := '0'; -- .export
cam_address : in std_logic_vector(17 downto 0) := (others => '0'); -- .export
cam_waitreq : out std_logic -- .export
);
end entity ci_bridge_0;
architecture rtl of ci_bridge_0 is
component ci_bridge is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(15 downto 0); -- readdata
rst : in std_logic := 'X'; -- reset
cia_reset : out std_logic; -- export
cib_reset : out std_logic; -- export
cia_ce_n : out std_logic; -- export
cib_ce_n : out std_logic; -- export
ci_reg_n : out std_logic; -- export
ci_a : out std_logic_vector(14 downto 0); -- export
ci_we_n : out std_logic; -- export
ci_oe_n : out std_logic; -- export
ci_iowr_n : out std_logic; -- export
ci_iord_n : out std_logic; -- export
cia_wait_n : in std_logic := 'X'; -- export
cib_wait_n : in std_logic := 'X'; -- export
cia_ireq_n : in std_logic := 'X'; -- export
cib_ireq_n : in std_logic := 'X'; -- export
cia_cd_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
cib_cd_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
cia_overcurrent_n : in std_logic := 'X'; -- export
cib_overcurrent_n : in std_logic := 'X'; -- export
cia_reset_buf_oe_n : out std_logic; -- export
cib_reset_buf_oe_n : out std_logic; -- export
cia_data_buf_oe_n : out std_logic; -- export
cib_data_buf_oe_n : out std_logic; -- export
ci_bus_dir : out std_logic; -- export
interrupt : out std_logic; -- export
cam_interrupts : out std_logic_vector(1 downto 0); -- export
cam0_ready : out std_logic; -- export
cam0_bypass : out std_logic; -- export
cam1_ready : out std_logic; -- export
cam1_bypass : out std_logic; -- export
cam0_fail : out std_logic; -- export
cam1_fail : out std_logic; -- export
ci_d_out : out std_logic_vector(7 downto 0); -- export
ci_d_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
ci_d_en : out std_logic; -- export
cam_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
cam_write : in std_logic := 'X'; -- export
cam_readdata : out std_logic_vector(7 downto 0); -- export
cam_read : in std_logic := 'X'; -- export
cam_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- export
cam_waitreq : out std_logic -- export
);
end component ci_bridge;
begin
ci_bridge_0 : component ci_bridge
port map (
clk => clk, -- clock.clk
address => address, -- avalon_slave_0.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
rst => rst, -- reset_sink.reset
cia_reset => cia_reset, -- conduit_end.export
cib_reset => cib_reset, -- .export
cia_ce_n => cia_ce_n, -- .export
cib_ce_n => cib_ce_n, -- .export
ci_reg_n => ci_reg_n, -- .export
ci_a => ci_a, -- .export
ci_we_n => ci_we_n, -- .export
ci_oe_n => ci_oe_n, -- .export
ci_iowr_n => ci_iowr_n, -- .export
ci_iord_n => ci_iord_n, -- .export
cia_wait_n => cia_wait_n, -- .export
cib_wait_n => cib_wait_n, -- .export
cia_ireq_n => cia_ireq_n, -- .export
cib_ireq_n => cib_ireq_n, -- .export
cia_cd_n => cia_cd_n, -- .export
cib_cd_n => cib_cd_n, -- .export
cia_overcurrent_n => cia_overcurrent_n, -- .export
cib_overcurrent_n => cib_overcurrent_n, -- .export
cia_reset_buf_oe_n => cia_reset_buf_oe_n, -- .export
cib_reset_buf_oe_n => cib_reset_buf_oe_n, -- .export
cia_data_buf_oe_n => cia_data_buf_oe_n, -- .export
cib_data_buf_oe_n => cib_data_buf_oe_n, -- .export
ci_bus_dir => ci_bus_dir, -- .export
interrupt => interrupt, -- .export
cam_interrupts => cam_interrupts, -- .export
cam0_ready => cam0_ready, -- .export
cam0_bypass => cam0_bypass, -- .export
cam1_ready => cam1_ready, -- .export
cam1_bypass => cam1_bypass, -- .export
cam0_fail => cam0_fail, -- .export
cam1_fail => cam1_fail, -- .export
ci_d_out => ci_d_out, -- .export
ci_d_in => ci_d_in, -- .export
ci_d_en => ci_d_en, -- .export
cam_writedata => cam_writedata, -- .export
cam_write => cam_write, -- .export
cam_readdata => cam_readdata, -- .export
cam_read => cam_read, -- .export
cam_address => cam_address, -- .export
cam_waitreq => cam_waitreq -- .export
);
end architecture rtl; -- of ci_bridge_0
|
gpl-3.0
|
395831844e833003395fa5bb677e8b03
| 0.344782 | 4.189233 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/Common/Source/Synchronizer.vhd
| 1 | 4,252 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Synchronizes an asynchronous signal to a clock. Optionally, the asynchronous
-- signal´s high pulses can be stretched to be long enough to get reliably
-- fetched by the synchronizer.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Synchronizer is
generic
(
-- Determines whether to stretch the incoming pulse to match the destination
-- clock's timing.
pulse_stretcher: boolean := false;
-- The number of FFs the synchronizer consists of (usually 2 is recommended).
nr_of_stages: natural range 1 to 3 := 2
);
port
(
-- The system clock the asynchronous signal is synchronized to.
clk: in std_logic;
-- The asynchronous signal to be synchronized.
in_async: in std_logic;
-- The synchronization stages.
out_sync_stages: out std_logic_vector(nr_of_stages - 1 downto 0);
-- The synchronized signal (i.e. the last synchronization stages´ output signal).
out_sync: out std_logic
);
end entity;
architecture stdarch of Synchronizer is
type reg_type is record
out_sync_stages: std_logic_vector(nr_of_stages - 1 downto 0);
end record;
signal state, next_state: reg_type := (out_sync_stages => (others => '0'));
signal in_async_stretched: std_logic := '0';
-- Constraints-
attribute TIG: string;
attribute TIG of in_async: signal is "TRUE";
begin
------------------------------------------
-- Optional asynchronous pulse stretcher.
------------------------------------------
stretch_pulse: if (pulse_stretcher) generate
-- Set the stretched pulse immediately if a pulse arrives, reset it as soon as the
-- synchronizer has fetched it and the pulse has been deactivated.
stretcher: process(in_async, state.out_sync_stages(nr_of_stages-1)) is
begin
if (state.out_sync_stages(state.out_sync_stages'high) = '1' and in_async = '0') then
in_async_stretched <= '0';
elsif (rising_edge(in_async)) then
in_async_stretched <= '1';
end if;
end process;
end generate;
do_not_stretch_pulse: if (not pulse_stretcher) generate
in_async_stretched <= in_async;
end generate;
------------------------------------------
-- State register.
------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
------------------------------------------
-- Next state logic.
------------------------------------------
create_nr_of_stages: for i in nr_of_stages - 1 downto 1 generate
next_state.out_sync_stages(i) <= state.out_sync_stages(i - 1);
end generate;
next_state.out_sync_stages(0) <= in_async_stretched;
-------------------------------------
-- Output logic
-------------------------------------
out_sync_stages <= state.out_sync_stages;
out_sync <= state.out_sync_stages(state.out_sync_stages'high);
end architecture;
|
gpl-3.0
|
85aa61b88b1388c61ec005c3298aa057
| 0.534807 | 4.734967 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/7/projetos/projeto1/bla.vhd
| 1 | 1,612 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bla IS
END bla;
ARCHITECTURE behavior OF bla IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT flip_flop_jk
PORT(
J : IN std_logic;
K : IN std_logic;
Reset : IN std_logic;
Clock_enable : IN std_logic;
Clock : IN std_logic;
Output : OUT std_logic
);
END COMPONENT;
--Inputs
signal J : std_logic := '0';
signal K : std_logic := '0';
signal Reset : std_logic := '0';
signal Clock_enable : std_logic := '0';
signal Clock : std_logic := '0';
--Outputs
signal Output : std_logic;
-- Clock period definitions
constant Clock_enable_period : time := 10 ns;
constant Clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: flip_flop_jk PORT MAP (
J => J,
K => K,
Reset => Reset,
Clock_enable => Clock_enable,
Clock => Clock,
Output => Output
);
-- Clock process definitions
Clock_enable_process :process
begin
Clock_enable <= '0';
wait for Clock_enable_period/2;
Clock_enable <= '1';
wait for Clock_enable_period/2;
end process;
Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clock_enable_period*10;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
ddd611eb33f8571965b738e2774b3fb9
| 0.57134 | 3.663636 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
fifo_out_8b_sync.vhd
| 1 | 4,812 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_out_8b_sync is
generic (
FIFO_DEPTH : natural range 8 to 64 := 16;
BUS_WIDTH : natural range 16 to 64 := 32
);
port (
rst : in std_logic;
clk : in std_logic;
irq : out std_logic;
-- Avalon-MM 32-bits slave
addr : in std_logic_vector(1 downto 0);
byte_en : in std_logic_vector(3 downto 0) := (others => '1');
in_data : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
out_data : out std_logic_vector(31 downto 0);
wait_req : out std_logic;
-- output stream
st_data : out std_logic_vector(7 downto 0);
st_valid : out std_logic;
st_ready : in std_logic
);
end entity;
architecture RTL of fifo_out_8b_sync is
function log2ceil (arg: natural) return natural is
begin
if arg < 2 then
return 1;
else
return log2ceil(arg / 2) + 1;
end if;
end function;
constant FIFO_ADDR_WIDTH : natural := log2ceil(FIFO_DEPTH - 1);
constant REG_DATA : std_logic_vector(1 downto 0) := "00";
constant REG_CTRL_STAT : std_logic_vector(1 downto 0) := "10";
signal read_ptr : unsigned(FIFO_ADDR_WIDTH downto 0);
signal write_ptr : unsigned(FIFO_ADDR_WIDTH downto 0);
signal not_empty : std_logic;
signal data_wren : std_logic;
signal ctrl_wren : std_logic;
signal write_phase : unsigned(1 downto 0);
signal end_phase : std_logic_vector(2 downto 0);
signal write_not_compl : std_logic;
signal fifo_reset : std_logic;
signal imask : std_logic;
signal ipend : std_logic;
signal fill : unsigned(FIFO_ADDR_WIDTH downto 0);
signal threshold : unsigned(FIFO_ADDR_WIDTH - 1 downto 0);
signal st_valid_i : std_logic;
type mem_t is array(0 to FIFO_DEPTH - 1) of std_logic_vector(7 downto 0);
signal fifo_ram : mem_t;
signal fifo_ram_we : std_logic;
signal fifo_ram_re : std_logic;
signal fifo_ram_d : std_logic_vector(7 downto 0);
signal fifo_ram_q : std_logic_vector(7 downto 0);
attribute ramstyle : string;
attribute ramstyle of fifo_ram : signal is "logic";
begin
-- RAM block logic
process (clk)
begin
if rising_edge(clk) then
if fifo_ram_we = '1' then
fifo_ram(to_integer(write_ptr(FIFO_ADDR_WIDTH - 1 downto 0))) <= fifo_ram_d;
end if;
if fifo_ram_re = '1' then
fifo_ram_q <= fifo_ram(to_integer(read_ptr(FIFO_ADDR_WIDTH - 1 downto 0)));
end if;
end if;
end process;
-- FIFO pointers logic
process (rst, clk)
begin
if rising_edge(clk) then
if fifo_ram_we = '1' then
write_ptr <= write_ptr + 1;
end if;
if fifo_ram_re = '1' then
read_ptr <= read_ptr + 1;
end if;
st_valid_i <= not_empty or (st_valid_i and not st_ready);
if fifo_reset = '1' then
read_ptr <= (others => '0');
write_ptr <= (others => '0');
st_valid_i <= '0';
end if;
end if;
if rst = '1' then
read_ptr <= (others => '0');
write_ptr <= (others => '0');
st_valid_i <= '0';
end if;
end process;
not_empty <= '0' when read_ptr = write_ptr else '1';
fill <= write_ptr - read_ptr;
-- bus interface logic
ipend <= '0' when fill > unsigned('0' & threshold) else '1';
with addr select
out_data <= (BUS_WIDTH - 1 downto 16 => '0') & imask & (14 downto FIFO_ADDR_WIDTH + 8 => '0') & std_logic_vector(threshold) & ipend & (6 downto FIFO_ADDR_WIDTH + 1 => '0') & std_logic_vector(fill) when REG_CTRL_STAT,
(others => '0') when others;
data_wren <= wr_en and not fill(FIFO_ADDR_WIDTH) when addr = REG_DATA else '0';
ctrl_wren <= (byte_en(1) and wr_en) when addr = REG_CTRL_STAT else '0';
fifo_reset <= ctrl_wren and in_data(14);
with byte_en select
end_phase <= data_wren & "00" when "0001",
data_wren & "01" when "0011",
data_wren & "11" when "1111",
"000" when others;
write_not_compl <= end_phase(2) when write_phase /= unsigned(end_phase(1 downto 0)) else '0';
process (rst, clk)
begin
if rising_edge(clk) then
if ctrl_wren = '1' then
imask <= in_data(15);
threshold <= unsigned(in_data(FIFO_ADDR_WIDTH + 7 downto 8));
end if;
if write_not_compl = '0' then
write_phase <= (others => '0');
else
write_phase <= write_phase + 1;
end if;
end if;
if rst = '1' then
imask <= '0';
threshold <= (others => '0');
write_phase <= (others => '0');
end if;
end process;
wait_req <= write_not_compl;
fifo_ram_we <= end_phase(2);
fifo_ram_re <= not_empty and (st_ready or not st_valid_i);
with write_phase select
fifo_ram_d <= in_data(31 downto 24) when "11",
in_data(23 downto 16) when "10",
in_data(15 downto 8) when "01",
in_data(7 downto 0) when others;
st_data <= fifo_ram_q;
st_valid <= st_valid_i;
irq <= ipend and imask;
end architecture;
|
gpl-3.0
|
6318b9dd503b5025b1aaf52bf212cc03
| 0.629468 | 2.682274 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/numeric_bit-body.vhd
| 7 | 57,051 |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
--==============================================================================
--======================= Package Body =========================================
--==============================================================================
package body NUMERIC_BIT is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: BIT) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: BIT) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
---------------- Local Subprograms - Relational Operators --------------------
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
variable CBIT: BIT := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) := (others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
QNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
RNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
RNEG := TRUE;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
--START-V93
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--END-V93
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
if ARG(ARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER;
SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: BIT := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '1';
end RISING_EDGE;
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '0';
end FALLING_EDGE;
--============================================================================
end NUMERIC_BIT;
|
mit
|
ad81d400dddb7104edaeb55d7f351e61
| 0.566914 | 3.779213 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/seven_seg.vhd
| 2 | 2,084 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seven_seg is
Port ( display_hex : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
double_dot : IN STD_LOGIC;
anodes : out STD_LOGIC_VECTOR (4 downto 0);
sevenseg : out STD_LOGIC_VECTOR (7 downto 0));
end seven_seg;
architecture Behavioral of seven_seg is
signal value : STD_LOGIC_VECTOR(4 downto 0) := (OTHERS =>'0');
signal anodes_buf : STD_LOGIC_VECTOR(4 downto 0);
begin
anodes <= anodes_buf;
display_update:process(clk) begin
if rising_edge(clk) then
CASE anodes_buf IS
WHEN "01111" =>
anodes_buf <= "10111";
value <= "0" & display_hex(3 downto 0);
WHEN "10111" =>
anodes_buf <= "11011";
value <= "0" & display_hex(7 downto 4);
WHEN "11011" =>
anodes_buf <= "11101";
value <= "0" & display_hex(11 downto 8);
WHEN "11101" =>
anodes_buf <= "11110";
value <= "0" & display_hex(15 downto 12);
WHEN OTHERS =>
anodes_buf <= "01111";
value <= "10000";
END CASE;
end if;
end process;
display_mapping:process(value, double_dot) begin
CASE value IS
WHEN "0" & x"0" => sevenseg <= NOT x"3F"; -- 0
WHEN "0" & x"1" => sevenseg <= NOT x"06"; -- 1
WHEN "0" & x"2" => sevenseg <= NOT x"5B"; -- 2
WHEN "0" & x"3" => sevenseg <= NOT x"4F"; -- 3
WHEN "0" & x"4" => sevenseg <= NOT x"66"; -- 4
WHEN "0" & x"5" => sevenseg <= NOT x"6D"; -- 5
WHEN "0" & x"6" => sevenseg <= NOT x"7D"; -- 6
WHEN "0" & x"7" => sevenseg <= NOT x"07"; -- 7
WHEN "0" & x"8" => sevenseg <= NOT x"7F"; -- 8
WHEN "0" & x"9" => sevenseg <= NOT x"6F"; -- 9
WHEN "0" & x"a" => sevenseg <= NOT x"77"; -- A
WHEN "0" & x"b" => sevenseg <= NOT x"7C"; -- b
WHEN "0" & x"c" => sevenseg <= NOT x"39"; -- C
WHEN "0" & x"d" => sevenseg <= NOT x"5E"; -- d
WHEN "0" & x"e" => sevenseg <= NOT x"79"; -- E
WHEN "0" & x"f" => sevenseg <= NOT x"71"; -- F
WHEN OTHERS => sevenseg <= "1111111" & ( NOT double_dot);
END CASE;
end process;
end Behavioral;
|
gpl-3.0
|
f0be418401239a1403b97441de2fa0c9
| 0.542706 | 2.839237 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_proc_sys_reset_0_0/sim/bd_proc_sys_reset_0_0.vhd
| 1 | 5,829 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY bd_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END bd_proc_sys_reset_0_0;
ARCHITECTURE bd_proc_sys_reset_0_0_arch OF bd_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END bd_proc_sys_reset_0_0_arch;
|
mit
|
138b596e57284aebc7c98ce50227cd32
| 0.70561 | 3.578269 | false | false | false | false |
rinatzakirov/vhdl
|
synchronizing.vhdl
| 1 | 9,769 |
--------------------------------------------------------------------
-- _ __ __ __ ____ __ = --
-- | | / // / / // __ \ / / = --
-- | | / // /_/ // / / // / = .__ |/ _/_ .__ .__ __ --
-- | |/ // __ // /_/ // /___ = /___) | / / ) / ) (_ ` --
-- |___//_/ /_//_____//_____/ = (___ /| (_ / (___(_ (__) --
-- ===== / --
-- === --
----------------------------- = ----------------------------------
--# synchronizing.vhdl - Clock domain synchronization components
--# $Id$
--# Freely available from VHDL-extras (http://code.google.com/p/vhdl-extras)
--#
--# Copyright � 2010 Kevin Thibedeau
--# (kevin 'period' thibedeau 'at' gmail 'punto' com)
--#
--# Permission is hereby granted, free of charge, to any person obtaining a
--# copy of this software and associated documentation files (the "Software"),
--# to deal in the Software without restriction, including without limitation
--# the rights to use, copy, modify, merge, publish, distribute, sublicense,
--# and/or sell copies of the Software, and to permit persons to whom the
--# Software is furnished to do so, subject to the following conditions:
--#
--# The above copyright notice and this permission notice shall be included in
--# all copies or substantial portions of the Software.
--#
--# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
--# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
--# DEALINGS IN THE SOFTWARE.
--#
--# DEPENDENCIES: none
--#
--# DESCRIPTION:
--# This package provides a number of synchronizer components for managing
--# data transmission between clock domains.
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package synchronizing is
--## A basic synchronizer with a configurable number of stages
component bit_synchronizer is
generic (
STAGES : natural := 2; -- number of flip-flops in the synchronizer
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock : in std_ulogic;
Reset : in std_ulogic; -- Asynchronous reset
Bit_in : in std_ulogic; -- Unsynchronized signal
Sync : out std_ulogic -- Synchronized to Clock's domain
);
end component;
--## Synchronizer for generating a synchronized reset
component reset_synchronizer is
generic (
STAGES : natural := 2;
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock : in std_ulogic;
Reset : in std_ulogic; -- Asynchronous reset
Sync_reset : out std_ulogic -- Synchronized reset
);
end component;
--## A handshaking synchronizer for sending an array between clock domains
--# This uses the four-phase handshake protocol.
component handshake_synchronizer is
generic (
STAGES : natural := 2;
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock_tx : in std_ulogic; -- Transmitting domain clock
Reset_tx : in std_ulogic;
Clock_rx : in std_ulogic; -- Receiving domain clock
Reset_rx : in std_ulogic;
Tx_data : in std_ulogic_vector; -- Data to send
Send_data : in std_ulogic; -- Control signal to send new data
Sending : out std_ulogic; -- Active while TX is in process
Data_sent : out std_ulogic; -- Flag to indicate TX completion
Rx_data : out std_ulogic_vector; -- Data received in clock_rx domain
New_data : out std_ulogic -- Flag to indicate new data
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
--## A basic synchronizer with a configurable number of stages
entity bit_synchronizer is
generic (
STAGES : natural := 2; -- number of flip-flops in the synchronizer
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock : in std_ulogic;
Reset : in std_ulogic; -- Asynchronous reset
Bit_in : in std_ulogic; -- Unsynchronized signal
Sync : out std_ulogic -- Synchronized to Clock's domain
);
end entity;
architecture rtl of bit_synchronizer is
signal sr : std_ulogic_vector(1 to STAGES);
begin
reg: process(Clock, Reset) is
begin
if Reset = RESET_ACTIVE_LEVEL then
sr <= (others => '0');
elsif rising_edge(Clock) then
sr <= to_X01(Bit_in) & sr(1 to sr'right-1);
end if;
end process;
Sync <= sr(sr'right);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
--## Synchronizer for generating a synchronized reset
entity reset_synchronizer is
generic (
STAGES : natural := 2;
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock : in std_ulogic;
Reset : in std_ulogic; -- Asynchronous reset
Sync_reset : out std_ulogic -- Synchronized reset
);
end entity;
architecture rtl of reset_synchronizer is
signal sr : std_ulogic_vector(1 to STAGES);
begin
reg: process(Clock, Reset) is
begin
if Reset = RESET_ACTIVE_LEVEL then
sr <= (others => RESET_ACTIVE_LEVEL);
elsif rising_edge(Clock) then
sr <= (not RESET_ACTIVE_LEVEL) & sr(1 to sr'right-1);
end if;
end process;
Sync_reset <= sr(sr'right);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.synchronizing.bit_synchronizer;
--## A handshaking synchronizer for sending an array between clock domains
--# This uses the four-phase handshake protocol.
entity handshake_synchronizer is
generic (
STAGES : natural := 2;
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock_tx : in std_ulogic; -- Transmitting domain clock
Reset_tx : in std_ulogic;
Clock_rx : in std_ulogic; -- Receiving domain clock
Reset_rx : in std_ulogic;
Tx_data : in std_ulogic_vector; -- Data to send
Send_data : in std_ulogic; -- Control signal to send new data
Sending : out std_ulogic; -- Active while TX is in process
Data_sent : out std_ulogic; -- Flag to indicate TX completion
Rx_data : out std_ulogic_vector; -- Data received in clock_rx domain
New_data : out std_ulogic -- Flag to indicate new data
);
end entity;
architecture rtl of handshake_synchronizer is
signal ack_rx, ack_tx : std_ulogic;
signal prev_ack : std_ulogic;
signal tx_reg_en : std_ulogic;
signal tx_data_reg : std_ulogic_vector(Tx_data'range);
signal req_tx, req_rx : std_ulogic;
signal prev_req : std_ulogic;
begin
-----------
-- TX logic
-----------
as: bit_synchronizer
generic map (
STAGES => STAGES,
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock => Clock_tx,
Reset => Reset_tx,
Bit_in => ack_rx,
Sync => ack_tx
);
ack_change: process(Clock_tx, Reset_tx) is
begin
if Reset_tx = RESET_ACTIVE_LEVEL then
prev_ack <= '0';
elsif rising_edge(Clock_tx) then
prev_ack <= ack_tx;
end if;
end process;
Data_sent <= '1' when ack_tx = '0' and prev_ack = '1' else '0';
fsm: block
type states is (IDLE, SEND, FINISH);
signal cur_state : states;
begin
process(Clock_tx, Reset_tx) is
variable next_state : states;
begin
if Reset_tx = RESET_ACTIVE_LEVEL then
cur_state <= IDLE;
tx_reg_en <= '0';
req_tx <= '0';
Sending <= '0';
elsif rising_edge(Clock_tx) then
next_state := cur_state;
tx_reg_en <= '0';
case cur_state is
when IDLE =>
if Send_data = '1' then
next_state := SEND;
tx_reg_en <= '1';
end if;
when SEND => -- Wait for Rx side to assert ack
if ack_tx = '1' then
next_state := FINISH;
end if;
when FINISH => -- Wait for Rx side to deassert ack
if ack_tx = '0' then
next_state := IDLE;
end if;
when others =>
next_state := IDLE;
end case;
cur_state <= next_state;
req_tx <= '0';
Sending <= '0';
case next_state is
when IDLE =>
null;
when SEND =>
req_tx <= '1';
Sending <= '1';
when FINISH =>
Sending <= '1';
when others =>
null;
end case;
end if;
end process;
end block;
tx_reg: process(Clock_tx, Reset_tx) is
begin
if Reset_tx = RESET_ACTIVE_LEVEL then
tx_data_reg <= (others => '0');
elsif rising_edge(Clock_tx) then
if tx_reg_en = '1' then
tx_data_reg <= Tx_data;
end if;
end if;
end process;
-----------
-- RX logic
-----------
rs: bit_synchronizer
generic map (
STAGES => STAGES,
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock => Clock_rx,
Reset => Reset_rx,
Bit_in => req_tx,
Sync => req_rx
);
ack_rx <= req_rx;
req_change: process(Clock_rx, Reset_rx) is
begin
if Reset_rx = RESET_ACTIVE_LEVEL then
prev_req <= '0';
Rx_data <= (Rx_data'range => '0');
New_data <= '0';
elsif rising_edge(Clock_rx) then
prev_req <= req_rx;
New_data <= '0';
if req_rx = '1' and prev_req = '0' then -- Capture data
Rx_data <= tx_data_reg;
New_data <= '1';
end if;
end if;
end process;
end architecture;
|
lgpl-2.1
|
eb90ecfb8c74ed7d8b4ed29cce96c27e
| 0.571107 | 3.883499 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
Dual_Universal_CI.vhd
| 1 | 18,611 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity netup_unidvb_top is
port (
nPERST : in std_logic;
SYSCLK : in std_logic;
-- config
FLASH_SCLK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_nCS : out std_logic;
-- Frontend A
FEA_CLOCK : in std_logic;
FEA_START : in std_logic;
FEA_VALID : in std_logic;
FEA_DATA : in std_logic_vector(7 downto 0);
-- Frontend B
FEB_CLOCK : in std_logic;
FEB_START : in std_logic;
FEB_VALID : in std_logic;
FEB_DATA : in std_logic_vector(7 downto 0);
-- CI global
CI_ADDR : out std_logic_vector(14 downto 0);
CI_nREG : out std_logic;
CI_DATA : inout std_logic_vector(7 downto 0);
CI_nIOWR : out std_logic;
CI_nWR : out std_logic;
CI_nIORD : out std_logic;
CI_nOE : out std_logic;
CI_BUS_DIR : out std_logic;
-- CI_A
CIA_RST : out std_logic;
CIA_nRSTEN : out std_logic;
CIA_nCE1 : out std_logic;
CIA_nBUS_OE : out std_logic;
CIA_nIREQ : in std_logic;
CIA_nWAIT : in std_logic;
CIA_nCD1 : in std_logic;
CIA_nCD2 : in std_logic;
CIA_MCLKI : out std_logic;
CIA_MDI : out std_logic_vector(7 downto 0);
CIA_MIVAL : out std_logic;
CIA_MISTRT : out std_logic;
CIA_MCLKO : in std_logic;
CIA_MDO : in std_logic_vector(7 downto 0);
CIA_MOVAL : in std_logic;
CIA_MOSTRT : in std_logic;
-- CI_B
CIB_RST : out std_logic;
CIB_nRSTEN : out std_logic;
CIB_nCE1 : out std_logic;
CIB_nBUS_OE : out std_logic;
CIB_nIREQ : in std_logic;
CIB_nWAIT : in std_logic;
CIB_nCD1 : in std_logic;
CIB_nCD2 : in std_logic;
CIB_MCLKI : out std_logic;
CIB_MDI : out std_logic_vector(7 downto 0);
CIB_MIVAL : out std_logic;
CIB_MISTRT : out std_logic;
CIB_MCLKO : in std_logic;
CIB_MDO : in std_logic_vector(7 downto 0);
CIB_MOVAL : in std_logic;
CIB_MOSTRT : in std_logic;
-- POWER SWITCH
SW_nOC : in std_logic_vector(1 downto 0);
-- RF switches control
RFA_CTL : out std_logic;
RFB_CTL : out std_logic;
-- IIC interfaces
IIC0_SCL : inout std_logic;
IIC0_SDA : inout std_logic;
IIC1_SCL : inout std_logic;
IIC1_SDA : inout std_logic;
-- LED controls
LED0_GRN : out std_logic;
LED0_RED : out std_logic;
LED1_GRN : out std_logic;
LED1_RED : out std_logic;
-- Demod/Tuner controls
FEA_TU_nRST : out std_logic;
FEB_TU_nRST : out std_logic;
FEA_nRST : out std_logic;
FEB_nRST : out std_logic;
FEA_nIRQ0 : in std_logic;
FEA_nIRQ1 : in std_logic;
FEB_nIRQ0 : in std_logic;
FEB_nIRQ1 : in std_logic;
-- PCIe Interface
PCI_REFCLK : in std_logic;
PCI_PET0 : out std_logic;
PCI_PER0 : in std_logic
);
end;
architecture rtl of netup_unidvb_top is
component altpcie_reconfig_3cgx is
port (
signal offset_cancellation_reset : in std_logic;
signal reconfig_clk : in std_logic;
signal reconfig_fromgxb : in std_logic_vector (4 downto 0);
signal busy : out std_logic;
signal reconfig_togxb : out std_logic_vector (3 downto 0)
);
end component altpcie_reconfig_3cgx;
signal pll_rst_meta : std_logic;
signal pll_rst_n : std_logic;
signal gxb_fixedclk : std_logic;
signal gxb_reconfig_clk : std_logic;
signal gxb_pll_locked : std_logic;
signal reconfig_busy : std_logic;
signal reconfig_fromgxb : std_logic_vector(4 downto 0);
signal reconfig_togxb : std_logic_vector(3 downto 0);
signal bus_reset : std_logic;
signal bus_clk : std_logic;
signal dvb_clk : std_logic;
signal tsa_sop : std_logic;
signal tsa_dval : std_logic;
signal tsa_data : std_logic_vector(7 downto 0);
signal tsb_sop : std_logic;
signal tsb_dval : std_logic;
signal tsb_data : std_logic_vector(7 downto 0);
signal dma0_sop : std_logic;
signal dma0_dval : std_logic;
signal dma0_data : std_logic_vector(7 downto 0);
signal dma1_sop : std_logic;
signal dma1_dval : std_logic;
signal dma1_data : std_logic_vector(7 downto 0);
signal iic0_scl_act : std_logic;
signal iic0_sda_act : std_logic;
signal iic1_scl_act : std_logic;
signal iic1_sda_act : std_logic;
signal irq_fifo_in_0 : std_logic;
signal irq_fifo_out_0 : std_logic;
signal irq_fifo_in_1 : std_logic;
signal irq_fifo_out_1 : std_logic;
signal gpout : std_logic_vector(15 downto 0);
signal dma0_wait : std_logic;
signal dma0_addr : std_logic_vector(63 downto 3);
signal dma0_byteen : std_logic_vector(7 downto 0);
signal dma0_size : std_logic_vector(6 downto 0);
signal dma0_wrdata : std_logic_vector(63 downto 0);
signal dma0_write : std_logic;
signal dma1_wait : std_logic;
signal dma1_addr : std_logic_vector(63 downto 3);
signal dma1_byteen : std_logic_vector(7 downto 0);
signal dma1_size : std_logic_vector(6 downto 0);
signal dma1_wrdata : std_logic_vector(63 downto 0);
signal dma1_write : std_logic;
signal irq : std_logic_vector(15 downto 0);
signal irq_spi : std_logic;
signal irq_twi0 : std_logic;
signal irq_twi1 : std_logic;
signal irq_fea0 : std_logic;
signal irq_fea1 : std_logic;
signal irq_feb0 : std_logic;
signal irq_feb1 : std_logic;
signal irq_dma0 : std_logic;
signal irq_dma1 : std_logic;
signal irq_ci_stat : std_logic;
signal irq_cam : std_logic_vector(1 downto 0);
signal irq_ts : std_logic_vector(1 downto 0);
signal irq_fea0_meta : std_logic;
signal irq_fea1_meta : std_logic;
signal irq_feb0_meta : std_logic;
signal irq_feb1_meta : std_logic;
signal cam0_bypass : std_logic;
signal cam0_ready : std_logic;
signal cam0_fail : std_logic;
signal cam1_bypass : std_logic;
signal cam1_ready : std_logic;
signal cam1_fail : std_logic;
signal cam_address : std_logic_vector(17 downto 0);
signal cam_writedata : std_logic_vector(7 downto 0);
signal cam_write : std_logic;
signal cam_readdata : std_logic_vector(7 downto 0);
signal cam_read : std_logic;
signal cam_waitreq : std_logic;
signal ci_data_out : std_logic_vector(7 downto 0);
signal ci_data_out_en : std_logic;
begin
process (SYSCLK, nPERST)
begin
if rising_edge(SYSCLK) then
pll_rst_meta <= '1';
pll_rst_n <= pll_rst_meta;
end if;
if not nPERST then
pll_rst_meta <= '0';
pll_rst_n <= '0';
end if;
end process;
DVB_PLL_0 : entity work.dvb_pll
port map (
areset => not pll_rst_n,
inclk0 => SYSCLK,
c0 => dvb_clk, -- 108 MHz
locked => open
);
GXB_PLL_0 : entity work.gxb_pll
port map (
areset => '0',
inclk0 => SYSCLK,
c0 => gxb_fixedclk, -- 125 MHz
c1 => gxb_reconfig_clk, -- 37.5 MHz
locked => gxb_pll_locked
);
DVB_TSIN_0 : entity work.dvb_ts_sync
port map (
ts_clk => FEA_CLOCK,
ts_strt => FEA_START,
ts_dval => FEA_VALID,
ts_data => FEA_DATA,
--
rst => bus_reset,
clk => bus_clk,
--
strt => tsa_sop,
data => tsa_data,
dval => tsa_dval
);
DVB_TSIN_1 : entity work.dvb_ts_sync
port map (
ts_clk => FEB_CLOCK,
ts_strt => FEB_START,
ts_dval => FEB_VALID,
ts_data => FEB_DATA,
--
rst => bus_reset,
clk => bus_clk,
--
strt => tsb_sop,
data => tsb_data,
dval => tsb_dval
);
bus_reset <= '0';
BUS_INST_0 : entity work.unici_core
port map (
-- global signals
reset_n => pll_rst_n,
pcie_compiler_0_pcie_core_clk_out => bus_clk,
/* -- the_avalon_export_0
ex_address_from_the_avalon_export_0 => bus_address,
ex_byteenable_from_the_avalon_export_0 => bus_byteenable,
ex_clk_from_the_avalon_export_0 => bus_clk,
ex_interrupt_to_the_avalon_export_0 => bus_interrupt,
ex_read_from_the_avalon_export_0 => bus_read,
ex_readdata_to_the_avalon_export_0 => bus_readdata,
ex_reset_from_the_avalon_export_0 => bus_reset,
ex_waitrequest_to_the_avalon_export_0 => bus_waitrequest,
ex_write_from_the_avalon_export_0 => bus_write,
ex_writedata_from_the_avalon_export_0 => bus_writedata,
*/ -- interrupt controller
avlm_irq_to_the_int_ctrl_0 => irq,
-- the_gpio_0
pins_from_the_gpout_0 => gpout,
-- spi_0
cs_n_from_the_spi_master_0 => FLASH_nCS,
sclk_from_the_spi_master_0 => FLASH_SCLK,
mosi_from_the_spi_master_0 => FLASH_MOSI,
miso_to_the_spi_master_0 => FLASH_MISO,
irq_from_the_spi_master_0 => irq_spi,
-- twi_0
irq_from_the_fifo_in_8b_sync_0 => irq_fifo_in_0,
sink_irq_to_the_twi_master_0 => irq_fifo_in_0,
irq_from_the_fifo_out_8b_sync_0 => irq_fifo_out_0,
source_irq_to_the_twi_master_0 => irq_fifo_out_0,
scl_in_to_the_twi_master_0 => IIC0_SCL,
scl_act_from_the_twi_master_0 => iic0_scl_act,
sda_in_to_the_twi_master_0 => IIC0_SDA,
sda_act_from_the_twi_master_0 => iic0_sda_act,
irq_from_the_twi_master_0 => irq_twi0,
-- twi_1
irq_from_the_fifo_in_8b_sync_1 => irq_fifo_in_1,
sink_irq_to_the_twi_master_1 => irq_fifo_in_1,
irq_from_the_fifo_out_8b_sync_1 => irq_fifo_out_1,
source_irq_to_the_twi_master_1 => irq_fifo_out_1,
scl_in_to_the_twi_master_1 => IIC1_SCL,
scl_act_from_the_twi_master_1 => iic1_scl_act,
sda_in_to_the_twi_master_1 => IIC1_SDA,
sda_act_from_the_twi_master_1 => iic1_sda_act,
irq_from_the_twi_master_1 => irq_twi1,
-- the_pcie_compiler_0
clk125_out_pcie_compiler_0 => open,
clk250_out_pcie_compiler_0 => open,
clk500_out_pcie_compiler_0 => open,
--
reconfig_clk_pcie_compiler_0 => gxb_reconfig_clk,
busy_altgxb_reconfig_pcie_compiler_0 => reconfig_busy,
reconfig_fromgxb_pcie_compiler_0 => reconfig_fromgxb,
reconfig_togxb_pcie_compiler_0 => reconfig_togxb,
--
fixedclk_serdes_pcie_compiler_0 => gxb_fixedclk,
gxb_powerdown_pcie_compiler_0 => '0',
pll_powerdown_pcie_compiler_0 => '0',
--
pcie_rstn_pcie_compiler_0 => nPERST,
refclk_pcie_compiler_0 => PCI_REFCLK,
rx_in0_pcie_compiler_0 => PCI_PER0,
tx_out0_pcie_compiler_0 => PCI_PET0,
--
powerdown_ext_pcie_compiler_0 => open,
rate_ext_pcie_compiler_0 => open,
phystatus_ext_pcie_compiler_0 => '0',
pipe_mode_pcie_compiler_0 => '0',
rxdata0_ext_pcie_compiler_0 => (others => '0'),
rxdatak0_ext_pcie_compiler_0 => '0',
rxelecidle0_ext_pcie_compiler_0 => '0',
rxpolarity0_ext_pcie_compiler_0 => open,
rxstatus0_ext_pcie_compiler_0 => (others => '0'),
rxvalid0_ext_pcie_compiler_0 => '0',
test_in_pcie_compiler_0 => (others => '0'),
txcompl0_ext_pcie_compiler_0 => open,
txdata0_ext_pcie_compiler_0 => open,
txdatak0_ext_pcie_compiler_0 => open,
txdetectrx_ext_pcie_compiler_0 => open,
txelecidle0_ext_pcie_compiler_0 => open,
-- DMA arbiter
dma0_wait_from_the_dma_arbiter_0 => dma0_wait,
dma0_addr_to_the_dma_arbiter_0 => dma0_addr,
dma0_byteen_to_the_dma_arbiter_0 => dma0_byteen,
dma0_size_to_the_dma_arbiter_0 => dma0_size,
dma0_wrdata_to_the_dma_arbiter_0 => dma0_wrdata,
dma0_write_to_the_dma_arbiter_0 => dma0_write,
dma1_wait_from_the_dma_arbiter_0 => dma1_wait,
dma1_addr_to_the_dma_arbiter_0 => dma1_addr,
dma1_byteen_to_the_dma_arbiter_0 => dma1_byteen,
dma1_size_to_the_dma_arbiter_0 => dma1_size,
dma1_wrdata_to_the_dma_arbiter_0 => dma1_wrdata,
dma1_write_to_the_dma_arbiter_0 => dma1_write,
-- dma #0 interface
dvb_data_to_the_dvb_dma_0 => dma0_data,
dvb_dval_to_the_dvb_dma_0 => dma0_dval,
dvb_sop_to_the_dvb_dma_0 => dma0_sop,
mem_addr_from_the_dvb_dma_0 => dma0_addr,
mem_byteen_from_the_dvb_dma_0 => dma0_byteen,
mem_size_from_the_dvb_dma_0 => dma0_size,
mem_wrdata_from_the_dvb_dma_0 => dma0_wrdata,
mem_write_from_the_dvb_dma_0 => dma0_write,
mem_waitreq_to_the_dvb_dma_0 => dma0_wait,
interrupt_from_the_dvb_dma_0 => irq_dma0,
-- dma #1 interface
dvb_data_to_the_dvb_dma_1 => dma1_data,
dvb_dval_to_the_dvb_dma_1 => dma1_dval,
dvb_sop_to_the_dvb_dma_1 => dma1_sop,
mem_addr_from_the_dvb_dma_1 => dma1_addr,
mem_byteen_from_the_dvb_dma_1 => dma1_byteen,
mem_size_from_the_dvb_dma_1 => dma1_size,
mem_wrdata_from_the_dvb_dma_1 => dma1_wrdata,
mem_write_from_the_dvb_dma_1 => dma1_write,
mem_waitreq_to_the_dvb_dma_1 => dma1_wait,
interrupt_from_the_dvb_dma_1 => irq_dma1,
-- CI bridge
ci_reg_n_from_the_ci_bridge_0 => CI_nREG,
ci_a_from_the_ci_bridge_0 => CI_ADDR,
ci_d_in_to_the_ci_bridge_0 => CI_DATA,
ci_d_out_from_the_ci_bridge_0 => ci_data_out,
ci_d_en_from_the_ci_bridge_0 => ci_data_out_en,
ci_iord_n_from_the_ci_bridge_0 => CI_nIORD,
ci_iowr_n_from_the_ci_bridge_0 => CI_nIOWR,
ci_oe_n_from_the_ci_bridge_0 => CI_nOE,
ci_we_n_from_the_ci_bridge_0 => CI_nWR,
ci_bus_dir_from_the_ci_bridge_0 => CI_BUS_DIR,
cia_ce_n_from_the_ci_bridge_0 => CIA_nCE1,
cia_data_buf_oe_n_from_the_ci_bridge_0 => CIA_nBUS_OE,
cia_reset_buf_oe_n_from_the_ci_bridge_0 => CIA_nRSTEN,
cia_reset_from_the_ci_bridge_0 => CIA_RST,
cib_ce_n_from_the_ci_bridge_0 => CIB_nCE1,
cib_data_buf_oe_n_from_the_ci_bridge_0 => CIB_nBUS_OE,
cib_reset_buf_oe_n_from_the_ci_bridge_0 => CIB_nRSTEN,
cib_reset_from_the_ci_bridge_0 => CIB_RST,
cia_cd_n_to_the_ci_bridge_0 => CIA_nCD1 & CIA_nCD2,
cia_ireq_n_to_the_ci_bridge_0 => CIA_nIREQ,
cia_overcurrent_n_to_the_ci_bridge_0 => SW_nOC(0),
cia_wait_n_to_the_ci_bridge_0 => CIA_nWAIT,
cib_cd_n_to_the_ci_bridge_0 => CIB_nCD1 & CIB_nCD2,
cib_ireq_n_to_the_ci_bridge_0 => CIB_nIREQ,
cib_overcurrent_n_to_the_ci_bridge_0 => SW_nOC(1),
cib_wait_n_to_the_ci_bridge_0 => CIB_nWAIT,
interrupt_from_the_ci_bridge_0 => irq_ci_stat,
cam0_bypass_from_the_ci_bridge_0 => cam0_bypass,
cam0_ready_from_the_ci_bridge_0 => cam0_ready,
cam0_fail_from_the_ci_bridge_0 => cam0_fail,
cam1_bypass_from_the_ci_bridge_0 => cam1_bypass,
cam1_ready_from_the_ci_bridge_0 => cam1_ready,
cam1_fail_from_the_ci_bridge_0 => cam1_fail,
cam_interrupts_from_the_ci_bridge_0 => irq_cam,
cam_readdata_from_the_ci_bridge_0 => cam_readdata,
cam_waitreq_from_the_ci_bridge_0 => cam_waitreq,
cam_address_to_the_ci_bridge_0 => cam_address,
cam_read_to_the_ci_bridge_0 => cam_read,
cam_write_to_the_ci_bridge_0 => cam_write,
cam_writedata_to_the_ci_bridge_0 => cam_writedata,
-- DVB TS 0
cam_mclki_from_the_dvb_ts_0 => CIA_MCLKI,
cam_mdi_from_the_dvb_ts_0 => CIA_MDI,
cam_mistrt_from_the_dvb_ts_0 => CIA_MISTRT,
cam_mival_from_the_dvb_ts_0 => CIA_MIVAL,
dvb_out_data_from_the_dvb_ts_0 => dma0_data,
dvb_out_dsop_from_the_dvb_ts_0 => dma0_sop,
dvb_out_dval_from_the_dvb_ts_0 => dma0_dval,
interrupt_from_the_dvb_ts_0 => irq_ts(0),
cam_baseclk_to_the_dvb_ts_0 => dvb_clk,
cam_bypass_to_the_dvb_ts_0 => cam0_bypass,
cam_mclko_to_the_dvb_ts_0 => CIA_MCLKO,
cam_mdo_to_the_dvb_ts_0 => CIA_MDO,
cam_mostrt_to_the_dvb_ts_0 => CIA_MOSTRT,
cam_moval_to_the_dvb_ts_0 => CIA_MOVAL,
dvb_in0_data_to_the_dvb_ts_0 => tsa_data,
dvb_in0_dsop_to_the_dvb_ts_0 => tsa_sop,
dvb_in0_dval_to_the_dvb_ts_0 => tsa_dval,
dvb_in1_data_to_the_dvb_ts_0 => tsb_data,
dvb_in1_dsop_to_the_dvb_ts_0 => tsb_sop,
dvb_in1_dval_to_the_dvb_ts_0 => tsb_dval,
dvb_in2_data_to_the_dvb_ts_0 => dma1_data,
dvb_in2_dsop_to_the_dvb_ts_0 => dma1_sop,
dvb_in2_dval_to_the_dvb_ts_0 => dma1_dval,
-- DVB TS 1
cam_mclki_from_the_dvb_ts_1 => CIB_MCLKI,
cam_mdi_from_the_dvb_ts_1 => CIB_MDI,
cam_mistrt_from_the_dvb_ts_1 => CIB_MISTRT,
cam_mival_from_the_dvb_ts_1 => CIB_MIVAL,
dvb_out_data_from_the_dvb_ts_1 => dma1_data,
dvb_out_dsop_from_the_dvb_ts_1 => dma1_sop,
dvb_out_dval_from_the_dvb_ts_1 => dma1_dval,
interrupt_from_the_dvb_ts_1 => irq_ts(1),
cam_baseclk_to_the_dvb_ts_1 => dvb_clk,
cam_bypass_to_the_dvb_ts_1 => cam1_bypass,
cam_mclko_to_the_dvb_ts_1 => CIB_MCLKO,
cam_mdo_to_the_dvb_ts_1 => CIB_MDO,
cam_mostrt_to_the_dvb_ts_1 => CIB_MOSTRT,
cam_moval_to_the_dvb_ts_1 => CIB_MOVAL,
dvb_in0_data_to_the_dvb_ts_1 => tsb_data,
dvb_in0_dsop_to_the_dvb_ts_1 => tsb_sop,
dvb_in0_dval_to_the_dvb_ts_1 => tsb_dval,
dvb_in1_data_to_the_dvb_ts_1 => tsa_data,
dvb_in1_dsop_to_the_dvb_ts_1 => tsa_sop,
dvb_in1_dval_to_the_dvb_ts_1 => tsa_dval,
dvb_in2_data_to_the_dvb_ts_1 => dma0_data,
dvb_in2_dsop_to_the_dvb_ts_1 => dma0_sop,
dvb_in2_dval_to_the_dvb_ts_1 => dma0_dval,
-- BAR1 adapter
out_address_from_the_avalon64_to_avalon8_0 => cam_address,
out_readdata_to_the_avalon64_to_avalon8_0 => cam_readdata,
out_read_from_the_avalon64_to_avalon8_0 => cam_read,
out_writedata_from_the_avalon64_to_avalon8_0 => cam_writedata,
out_write_from_the_avalon64_to_avalon8_0 => cam_write,
out_waitrequest_to_the_avalon64_to_avalon8_0 => cam_waitreq
);
irq <= (
0 => irq_spi,
1 => irq_twi0,
2 => irq_twi1,
4 => irq_fea0,
5 => irq_fea1,
6 => irq_feb0,
7 => irq_feb1,
8 => irq_dma0,
9 => irq_dma1,
10 => irq_ci_stat,
11 => irq_cam(0),
12 => irq_cam(1),
13 => irq_ts(0),
14 => irq_ts(1),
--
others => '0'
);
GX_RECONFIG_0 : altpcie_reconfig_3cgx
port map (
offset_cancellation_reset => not gxb_pll_locked,
reconfig_clk => gxb_reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
busy => reconfig_busy,
reconfig_togxb => reconfig_togxb
);
process (bus_clk, bus_reset)
begin
if rising_edge(bus_clk) then
irq_fea0_meta <= not FEA_nIRQ0;
irq_fea0 <= irq_fea0_meta;
irq_fea1_meta <= not FEA_nIRQ1;
irq_fea1 <= irq_fea1_meta;
irq_feb0_meta <= not FEB_nIRQ0;
irq_feb0 <= irq_feb0_meta;
irq_feb1_meta <= not FEB_nIRQ1;
irq_feb1 <= irq_feb1_meta;
--
LED0_GRN <= not cam0_ready;
LED0_RED <= not cam0_fail;
LED1_GRN <= not cam1_ready;
LED1_RED <= not cam1_fail;
end if;
if bus_reset then
irq_fea0_meta <= '0';
irq_fea0 <= '0';
irq_fea1_meta <= '0';
irq_fea1 <= '0';
irq_feb0_meta <= '0';
irq_feb0 <= '0';
irq_feb1_meta <= '0';
irq_feb1 <= '0';
--
LED0_GRN <= '0';
LED0_RED <= '0';
LED1_GRN <= '0';
LED1_RED <= '0';
end if;
end process;
IIC0_SCL <= '0' when iic0_scl_act else 'Z';
IIC0_SDA <= '0' when iic0_sda_act else 'Z';
IIC1_SCL <= '0' when iic1_scl_act else 'Z';
IIC1_SDA <= '0' when iic1_sda_act else 'Z';
FEA_nRST <= gpout(0);
FEB_nRST <= gpout(1);
RFA_CTL <= gpout(2);
RFB_CTL <= gpout(3);
FEA_TU_nRST <= gpout(4);
FEB_TU_nRST <= gpout(5);
CI_DATA <= ci_data_out when ci_data_out_en else (others => 'Z');
end;
|
gpl-3.0
|
6a88195e74d3c5ea15fa5a17af756717
| 0.633281 | 2.249335 | false | false | false | false |
wyvernSemi/vproc
|
makefile.vhd
| 1 | 4,820 |
###################################################################
# Makefile for Virtual Processor testcode in Modelsim
#
# Copyright (c) 2005-2021 Simon Southwell.
#
# This file is part of VProc.
#
# VProc is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# VProc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with VProc. If not, see <http://www.gnu.org/licenses/>.
#
# $Id: makefile.vhd,v 1.2 2021/05/05 08:07:40 simon Exp $
# $Source: /home/simon/CVS/src/HDL/VProc/makefile.vhd,v $
#
###################################################################
# MODELSIM and MODEL_TECH environment variables must be set
# Define the maximum number of supported VProcs in the compile pli library
MAX_NUM_VPROC = 64
SRCDIR = code
USRCDIR = usercode
VOBJDIR = obj
# VPROC C source code
VPROC_C = VSched.c \
VUser.c
# Test user code
USER_C = VUserMain0.c VUserMain1.c
VOBJS = ${addprefix ${VOBJDIR}/, ${VPROC_C:%.c=%.o} ${USER_C:%.c=%.o}}
# Generated PLI C library
VPROC_PLI = VProc.so
VLIB = libvproc.a
VPROC_TOP = test
# Get OS type
OSTYPE:=$(shell uname)
# Set OS specific variables between Linux and Windows (MinGW)
ifeq (${OSTYPE}, Linux)
CFLAGS_SO = -shared -lpthread -lrt -rdynamic
CPPSTD = -std=c++11
else
CFLAGS_SO = -shared -Wl,-export-all-symbols
CPPSTD =
endif
CC = gcc
C++ = g++
CFLAGS = -fPIC \
-m32 \
-g \
-I${SRCDIR} \
-I${USRCDIR} \
-I${MODEL_TECH}/../include \
-DVP_MAX_NODES=${MAX_NUM_VPROC} \
-DMODELSIM \
-DVPROC_VHDL \
-D_REENTRANT
# Comman flags for vsim
VSIMFLAGS = -pli ${VPROC_PLI} ${VPROC_TOP}
#------------------------------------------------------
# BUILD RULES
#------------------------------------------------------
all: ${VPROC_PLI} vhdl
${VOBJDIR}/%.o: ${SRCDIR}/%.c
@${CC} -c ${CFLAGS} $< -o $@
${VOBJDIR}/%.o: ${USRCDIR}/%.c
@${CC} -Wno-write-strings -c ${CFLAGS} $< -o $@
${VOBJDIR}/%.o: ${USRCDIR}/%.cpp
@${C++} ${CPPSTD} -Wno-write-strings -c ${CFLAGS} $< -o $@
${VLIB} : ${VOBJS} ${VOBJDIR}
@ar cr ${VLIB} ${VOBJS}
${VOBJS}: | ${VOBJDIR}
${VOBJDIR}:
@mkdir ${VOBJDIR}
${VPROC_PLI}: ${VLIB} ${VOBJDIR}/veriuser.o ${USER_C:%.c=${VOBJDIR}/%.o}
@${C++} ${CPPSTD} \
${CFLAGS_SO} \
${CFLAGS} \
-Wl,-whole-archive \
${VOBJDIR}/veriuser.o \
-lpthread \
-L${MODEL_TECH} \
-lmtipli \
-L. -lvproc \
-Wl,-no-whole-archive \
-o $@
# Let modelsim decide what's changed in the VHDL
.PHONY: vhdl
vhdl: ${VPROC_PLI}
@if [ ! -d "./work" ]; then \
vlib work; \
fi
@vcom -quiet -2008 -f files.tcl -work work
#------------------------------------------------------
# EXECUTION RULES
#------------------------------------------------------
run: vhdl
@vsim -c ${VSIMFLAGS}
rungui: vhdl
@if [ -e wave.do ]; then \
vsim -gui -do wave.do ${VSIMFLAGS}; \
else \
vsim -gui ${VSIMFLAGS}; \
fi
gui: rungui
#------------------------------------------------------
# CLEANING RULES
#------------------------------------------------------
clean:
@rm -rf ${VPROC_PLI} ${VLIB} ${VOBJS} ${VOBJDIR}/* *.wlf
@if [ -d "./work" ]; then \
vdel -all; \
fi
|
gpl-3.0
|
535ef5e3dbcc584c4b08980660f0f67f
| 0.401867 | 3.883965 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/main_pack.vhd
| 1 | 67,089 |
library ieee;
use ieee.std_logic_1164.all;
package main_pack is
constant cpu_width : integer := 32;
constant ram_size : integer := 1935;
subtype word_type is std_logic_vector(cpu_width-1 downto 0);
type ram_type is array(0 to ram_size-1) of word_type;
function load_hex return ram_type;
end package;
package body main_pack is
function load_hex return ram_type is
variable ram_buffer : ram_type := (others=>(others=>'0'));
begin
ram_buffer(0) := X"3C1C1001";
ram_buffer(1) := X"279C9E30";
ram_buffer(2) := X"3C1D1000";
ram_buffer(3) := X"27BD1E88";
ram_buffer(4) := X"0C000110";
ram_buffer(5) := X"00000000";
ram_buffer(6) := X"00000000";
ram_buffer(7) := X"00000000";
ram_buffer(8) := X"00000000";
ram_buffer(9) := X"00000000";
ram_buffer(10) := X"00000000";
ram_buffer(11) := X"00000000";
ram_buffer(12) := X"00000000";
ram_buffer(13) := X"00000000";
ram_buffer(14) := X"00000000";
ram_buffer(15) := X"23BDFF98";
ram_buffer(16) := X"AFA10010";
ram_buffer(17) := X"AFA20014";
ram_buffer(18) := X"AFA30018";
ram_buffer(19) := X"AFA4001C";
ram_buffer(20) := X"AFA50020";
ram_buffer(21) := X"AFA60024";
ram_buffer(22) := X"AFA70028";
ram_buffer(23) := X"AFA8002C";
ram_buffer(24) := X"AFA90030";
ram_buffer(25) := X"AFAA0034";
ram_buffer(26) := X"AFAB0038";
ram_buffer(27) := X"AFAC003C";
ram_buffer(28) := X"AFAD0040";
ram_buffer(29) := X"AFAE0044";
ram_buffer(30) := X"AFAF0048";
ram_buffer(31) := X"AFB8004C";
ram_buffer(32) := X"AFB90050";
ram_buffer(33) := X"AFBF0054";
ram_buffer(34) := X"401A7000";
ram_buffer(35) := X"235AFFFC";
ram_buffer(36) := X"AFBA0058";
ram_buffer(37) := X"0000D810";
ram_buffer(38) := X"AFBB005C";
ram_buffer(39) := X"0000D812";
ram_buffer(40) := X"AFBB0060";
ram_buffer(41) := X"0C0000E6";
ram_buffer(42) := X"23A50000";
ram_buffer(43) := X"8FA10010";
ram_buffer(44) := X"8FA20014";
ram_buffer(45) := X"8FA30018";
ram_buffer(46) := X"8FA4001C";
ram_buffer(47) := X"8FA50020";
ram_buffer(48) := X"8FA60024";
ram_buffer(49) := X"8FA70028";
ram_buffer(50) := X"8FA8002C";
ram_buffer(51) := X"8FA90030";
ram_buffer(52) := X"8FAA0034";
ram_buffer(53) := X"8FAB0038";
ram_buffer(54) := X"8FAC003C";
ram_buffer(55) := X"8FAD0040";
ram_buffer(56) := X"8FAE0044";
ram_buffer(57) := X"8FAF0048";
ram_buffer(58) := X"8FB8004C";
ram_buffer(59) := X"8FB90050";
ram_buffer(60) := X"8FBF0054";
ram_buffer(61) := X"8FBA0058";
ram_buffer(62) := X"8FBB005C";
ram_buffer(63) := X"03600011";
ram_buffer(64) := X"8FBB0060";
ram_buffer(65) := X"03600013";
ram_buffer(66) := X"23BD0068";
ram_buffer(67) := X"341B0001";
ram_buffer(68) := X"03400008";
ram_buffer(69) := X"409B6000";
ram_buffer(70) := X"40026000";
ram_buffer(71) := X"03E00008";
ram_buffer(72) := X"40846000";
ram_buffer(73) := X"3C051000";
ram_buffer(74) := X"24A50150";
ram_buffer(75) := X"8CA60000";
ram_buffer(76) := X"AC06003C";
ram_buffer(77) := X"8CA60004";
ram_buffer(78) := X"AC060040";
ram_buffer(79) := X"8CA60008";
ram_buffer(80) := X"AC060044";
ram_buffer(81) := X"8CA6000C";
ram_buffer(82) := X"03E00008";
ram_buffer(83) := X"AC060048";
ram_buffer(84) := X"3C1A1000";
ram_buffer(85) := X"375A003C";
ram_buffer(86) := X"03400008";
ram_buffer(87) := X"00000000";
ram_buffer(88) := X"00850019";
ram_buffer(89) := X"00001012";
ram_buffer(90) := X"00002010";
ram_buffer(91) := X"03E00008";
ram_buffer(92) := X"ACC40000";
ram_buffer(93) := X"0000000C";
ram_buffer(94) := X"03E00008";
ram_buffer(95) := X"00000000";
ram_buffer(96) := X"AC900000";
ram_buffer(97) := X"AC910004";
ram_buffer(98) := X"AC920008";
ram_buffer(99) := X"AC93000C";
ram_buffer(100) := X"AC940010";
ram_buffer(101) := X"AC950014";
ram_buffer(102) := X"AC960018";
ram_buffer(103) := X"AC97001C";
ram_buffer(104) := X"AC9E0020";
ram_buffer(105) := X"AC9C0024";
ram_buffer(106) := X"AC9D0028";
ram_buffer(107) := X"AC9F002C";
ram_buffer(108) := X"03E00008";
ram_buffer(109) := X"34020000";
ram_buffer(110) := X"8C900000";
ram_buffer(111) := X"8C910004";
ram_buffer(112) := X"8C920008";
ram_buffer(113) := X"8C93000C";
ram_buffer(114) := X"8C940010";
ram_buffer(115) := X"8C950014";
ram_buffer(116) := X"8C960018";
ram_buffer(117) := X"8C97001C";
ram_buffer(118) := X"8C9E0020";
ram_buffer(119) := X"8C9C0024";
ram_buffer(120) := X"8C9D0028";
ram_buffer(121) := X"8C9F002C";
ram_buffer(122) := X"03E00008";
ram_buffer(123) := X"34A20000";
ram_buffer(124) := X"27BDFFE0";
ram_buffer(125) := X"AFBF001C";
ram_buffer(126) := X"AFB10018";
ram_buffer(127) := X"0C000610";
ram_buffer(128) := X"AFB00014";
ram_buffer(129) := X"0C0006BF";
ram_buffer(130) := X"24040001";
ram_buffer(131) := X"3C041000";
ram_buffer(132) := X"0C000701";
ram_buffer(133) := X"2484028C";
ram_buffer(134) := X"3C041000";
ram_buffer(135) := X"24840264";
ram_buffer(136) := X"3C101000";
ram_buffer(137) := X"0C000704";
ram_buffer(138) := X"3C111000";
ram_buffer(139) := X"26101D50";
ram_buffer(140) := X"263102D4";
ram_buffer(141) := X"2404000C";
ram_buffer(142) := X"0C000180";
ram_buffer(143) := X"AE110004";
ram_buffer(144) := X"2404000C";
ram_buffer(145) := X"0C000180";
ram_buffer(146) := X"AE110008";
ram_buffer(147) := X"8FBF001C";
ram_buffer(148) := X"8FB10018";
ram_buffer(149) := X"8FB00014";
ram_buffer(150) := X"00001025";
ram_buffer(151) := X"03E00008";
ram_buffer(152) := X"27BD0020";
ram_buffer(153) := X"3C02F000";
ram_buffer(154) := X"8C420004";
ram_buffer(155) := X"3C031000";
ram_buffer(156) := X"24631D5C";
ram_buffer(157) := X"00021080";
ram_buffer(158) := X"00431021";
ram_buffer(159) := X"8C420000";
ram_buffer(160) := X"24030001";
ram_buffer(161) := X"03E00008";
ram_buffer(162) := X"AC430000";
ram_buffer(163) := X"3C02F000";
ram_buffer(164) := X"8C430004";
ram_buffer(165) := X"24020001";
ram_buffer(166) := X"10620003";
ram_buffer(167) := X"00000000";
ram_buffer(168) := X"03E00008";
ram_buffer(169) := X"00000000";
ram_buffer(170) := X"27BDFFE8";
ram_buffer(171) := X"AFBF0014";
ram_buffer(172) := X"0C0006C8";
ram_buffer(173) := X"00000000";
ram_buffer(174) := X"8FBF0014";
ram_buffer(175) := X"24060004";
ram_buffer(176) := X"27858020";
ram_buffer(177) := X"24040004";
ram_buffer(178) := X"27BD0018";
ram_buffer(179) := X"0800016A";
ram_buffer(180) := X"AF828020";
ram_buffer(181) := X"27BDFFE8";
ram_buffer(182) := X"AFBF0014";
ram_buffer(183) := X"0C00065A";
ram_buffer(184) := X"00000000";
ram_buffer(185) := X"3C02F000";
ram_buffer(186) := X"8C430004";
ram_buffer(187) := X"24020001";
ram_buffer(188) := X"10620016";
ram_buffer(189) := X"00000000";
ram_buffer(190) := X"3C02F000";
ram_buffer(191) := X"8C430004";
ram_buffer(192) := X"24020002";
ram_buffer(193) := X"10620005";
ram_buffer(194) := X"00000000";
ram_buffer(195) := X"8FBF0014";
ram_buffer(196) := X"00000000";
ram_buffer(197) := X"03E00008";
ram_buffer(198) := X"27BD0018";
ram_buffer(199) := X"0C000190";
ram_buffer(200) := X"00000000";
ram_buffer(201) := X"8F848020";
ram_buffer(202) := X"0C0006BF";
ram_buffer(203) := X"00000000";
ram_buffer(204) := X"0C000190";
ram_buffer(205) := X"00000000";
ram_buffer(206) := X"8F848020";
ram_buffer(207) := X"0C0006BF";
ram_buffer(208) := X"00000000";
ram_buffer(209) := X"1000FFF5";
ram_buffer(210) := X"00000000";
ram_buffer(211) := X"0C0006C8";
ram_buffer(212) := X"00000000";
ram_buffer(213) := X"24060004";
ram_buffer(214) := X"27858020";
ram_buffer(215) := X"24040004";
ram_buffer(216) := X"0C00016A";
ram_buffer(217) := X"AF828020";
ram_buffer(218) := X"1000FFE3";
ram_buffer(219) := X"00000000";
ram_buffer(220) := X"3C02F000";
ram_buffer(221) := X"8C420004";
ram_buffer(222) := X"3C031000";
ram_buffer(223) := X"24631D5C";
ram_buffer(224) := X"00021080";
ram_buffer(225) := X"00431021";
ram_buffer(226) := X"8C420000";
ram_buffer(227) := X"24030002";
ram_buffer(228) := X"03E00008";
ram_buffer(229) := X"AC430000";
ram_buffer(230) := X"27BDFFE0";
ram_buffer(231) := X"AFBF001C";
ram_buffer(232) := X"AFB20018";
ram_buffer(233) := X"AFB10014";
ram_buffer(234) := X"AFB00010";
ram_buffer(235) := X"3C02F000";
ram_buffer(236) := X"8C420004";
ram_buffer(237) := X"00000000";
ram_buffer(238) := X"00028100";
ram_buffer(239) := X"02028021";
ram_buffer(240) := X"00108080";
ram_buffer(241) := X"26120004";
ram_buffer(242) := X"3C111000";
ram_buffer(243) := X"26311D68";
ram_buffer(244) := X"02308021";
ram_buffer(245) := X"8E020000";
ram_buffer(246) := X"00000000";
ram_buffer(247) := X"8C420004";
ram_buffer(248) := X"00000000";
ram_buffer(249) := X"2C430008";
ram_buffer(250) := X"1060000F";
ram_buffer(251) := X"00000000";
ram_buffer(252) := X"000210C0";
ram_buffer(253) := X"00521021";
ram_buffer(254) := X"02221021";
ram_buffer(255) := X"8C430000";
ram_buffer(256) := X"8C440004";
ram_buffer(257) := X"0060F809";
ram_buffer(258) := X"00000000";
ram_buffer(259) := X"8E020000";
ram_buffer(260) := X"00000000";
ram_buffer(261) := X"8C420004";
ram_buffer(262) := X"00000000";
ram_buffer(263) := X"2C430008";
ram_buffer(264) := X"1460FFF3";
ram_buffer(265) := X"00000000";
ram_buffer(266) := X"8FBF001C";
ram_buffer(267) := X"8FB20018";
ram_buffer(268) := X"8FB10014";
ram_buffer(269) := X"8FB00010";
ram_buffer(270) := X"03E00008";
ram_buffer(271) := X"27BD0020";
ram_buffer(272) := X"27BDFFE0";
ram_buffer(273) := X"AFBF001C";
ram_buffer(274) := X"AFB20018";
ram_buffer(275) := X"AFB10014";
ram_buffer(276) := X"AFB00010";
ram_buffer(277) := X"3C05F000";
ram_buffer(278) := X"8CA20004";
ram_buffer(279) := X"00000000";
ram_buffer(280) := X"00021240";
ram_buffer(281) := X"244301E8";
ram_buffer(282) := X"3C021000";
ram_buffer(283) := X"24421EA0";
ram_buffer(284) := X"00431021";
ram_buffer(285) := X"0040E825";
ram_buffer(286) := X"8CB00004";
ram_buffer(287) := X"8CA60004";
ram_buffer(288) := X"00000000";
ram_buffer(289) := X"00062100";
ram_buffer(290) := X"8CA50004";
ram_buffer(291) := X"00861021";
ram_buffer(292) := X"3C031000";
ram_buffer(293) := X"3C071000";
ram_buffer(294) := X"00021080";
ram_buffer(295) := X"24631D68";
ram_buffer(296) := X"24E71D5C";
ram_buffer(297) := X"00052880";
ram_buffer(298) := X"00624021";
ram_buffer(299) := X"00A72821";
ram_buffer(300) := X"24420004";
ram_buffer(301) := X"3C09F002";
ram_buffer(302) := X"00621021";
ram_buffer(303) := X"ACA90000";
ram_buffer(304) := X"25070044";
ram_buffer(305) := X"3C05F001";
ram_buffer(306) := X"AD050000";
ram_buffer(307) := X"10470004";
ram_buffer(308) := X"00402825";
ram_buffer(309) := X"24A50008";
ram_buffer(310) := X"14E5FFFE";
ram_buffer(311) := X"ACA0FFF8";
ram_buffer(312) := X"3C051000";
ram_buffer(313) := X"24A5180C";
ram_buffer(314) := X"AC450000";
ram_buffer(315) := X"AC400004";
ram_buffer(316) := X"00861021";
ram_buffer(317) := X"00021080";
ram_buffer(318) := X"00621821";
ram_buffer(319) := X"8C620000";
ram_buffer(320) := X"24030001";
ram_buffer(321) := X"AC430000";
ram_buffer(322) := X"1600000F";
ram_buffer(323) := X"2783800C";
ram_buffer(324) := X"278288B4";
ram_buffer(325) := X"10620008";
ram_buffer(326) := X"24660004";
ram_buffer(327) := X"00463023";
ram_buffer(328) := X"00063082";
ram_buffer(329) := X"24C60001";
ram_buffer(330) := X"00063080";
ram_buffer(331) := X"00002825";
ram_buffer(332) := X"0C000707";
ram_buffer(333) := X"2784800C";
ram_buffer(334) := X"0C00007C";
ram_buffer(335) := X"00000000";
ram_buffer(336) := X"1000FFFF";
ram_buffer(337) := X"00000000";
ram_buffer(338) := X"0C000180";
ram_buffer(339) := X"2404000C";
ram_buffer(340) := X"00101080";
ram_buffer(341) := X"3C101000";
ram_buffer(342) := X"26101D50";
ram_buffer(343) := X"02028021";
ram_buffer(344) := X"02008825";
ram_buffer(345) := X"2412FFFF";
ram_buffer(346) := X"24060004";
ram_buffer(347) := X"02002825";
ram_buffer(348) := X"0C00016A";
ram_buffer(349) := X"00002025";
ram_buffer(350) := X"8E220000";
ram_buffer(351) := X"00000000";
ram_buffer(352) := X"1052FFFA";
ram_buffer(353) := X"24060004";
ram_buffer(354) := X"0C000190";
ram_buffer(355) := X"00000000";
ram_buffer(356) := X"8E220000";
ram_buffer(357) := X"00000000";
ram_buffer(358) := X"0040F809";
ram_buffer(359) := X"00000000";
ram_buffer(360) := X"1000FFE7";
ram_buffer(361) := X"00000000";
ram_buffer(362) := X"10C00013";
ram_buffer(363) := X"00C51821";
ram_buffer(364) := X"2406FFF0";
ram_buffer(365) := X"00661024";
ram_buffer(366) := X"0043182B";
ram_buffer(367) := X"00031900";
ram_buffer(368) := X"24420010";
ram_buffer(369) := X"00A62824";
ram_buffer(370) := X"00431821";
ram_buffer(371) := X"40076000";
ram_buffer(372) := X"40806000";
ram_buffer(373) := X"10A30007";
ram_buffer(374) := X"2484FF00";
ram_buffer(375) := X"00A61024";
ram_buffer(376) := X"AC820000";
ram_buffer(377) := X"AC400000";
ram_buffer(378) := X"24A50010";
ram_buffer(379) := X"14A3FFFC";
ram_buffer(380) := X"00A61024";
ram_buffer(381) := X"40876000";
ram_buffer(382) := X"03E00008";
ram_buffer(383) := X"00000000";
ram_buffer(384) := X"40066000";
ram_buffer(385) := X"40806000";
ram_buffer(386) := X"00001025";
ram_buffer(387) := X"2483FF00";
ram_buffer(388) := X"24050200";
ram_buffer(389) := X"AC620000";
ram_buffer(390) := X"AC400000";
ram_buffer(391) := X"34440200";
ram_buffer(392) := X"AC640000";
ram_buffer(393) := X"AC800000";
ram_buffer(394) := X"24420010";
ram_buffer(395) := X"1445FFF9";
ram_buffer(396) := X"00000000";
ram_buffer(397) := X"40866000";
ram_buffer(398) := X"03E00008";
ram_buffer(399) := X"00000000";
ram_buffer(400) := X"40066000";
ram_buffer(401) := X"40806000";
ram_buffer(402) := X"00000000";
ram_buffer(403) := X"40076000";
ram_buffer(404) := X"40806000";
ram_buffer(405) := X"00001025";
ram_buffer(406) := X"2403FF0C";
ram_buffer(407) := X"24050200";
ram_buffer(408) := X"AC620000";
ram_buffer(409) := X"AC400000";
ram_buffer(410) := X"34440200";
ram_buffer(411) := X"AC640000";
ram_buffer(412) := X"AC800000";
ram_buffer(413) := X"24420010";
ram_buffer(414) := X"1445FFF9";
ram_buffer(415) := X"00000000";
ram_buffer(416) := X"40876000";
ram_buffer(417) := X"00000000";
ram_buffer(418) := X"40076000";
ram_buffer(419) := X"40806000";
ram_buffer(420) := X"00001025";
ram_buffer(421) := X"2403FF08";
ram_buffer(422) := X"24050200";
ram_buffer(423) := X"AC620000";
ram_buffer(424) := X"AC400000";
ram_buffer(425) := X"34440200";
ram_buffer(426) := X"AC640000";
ram_buffer(427) := X"AC800000";
ram_buffer(428) := X"24420010";
ram_buffer(429) := X"1445FFF9";
ram_buffer(430) := X"00000000";
ram_buffer(431) := X"40876000";
ram_buffer(432) := X"00000000";
ram_buffer(433) := X"40866000";
ram_buffer(434) := X"03E00008";
ram_buffer(435) := X"00000000";
ram_buffer(436) := X"27BDFFB8";
ram_buffer(437) := X"AFB60038";
ram_buffer(438) := X"AFB50034";
ram_buffer(439) := X"AFB40030";
ram_buffer(440) := X"AFB20028";
ram_buffer(441) := X"AFB10024";
ram_buffer(442) := X"AFB00020";
ram_buffer(443) := X"AFBF0044";
ram_buffer(444) := X"AFBE0040";
ram_buffer(445) := X"AFB7003C";
ram_buffer(446) := X"AFB3002C";
ram_buffer(447) := X"00809025";
ram_buffer(448) := X"00A08825";
ram_buffer(449) := X"00C08025";
ram_buffer(450) := X"00E0A025";
ram_buffer(451) := X"24150025";
ram_buffer(452) := X"24160030";
ram_buffer(453) := X"82050000";
ram_buffer(454) := X"00000000";
ram_buffer(455) := X"10A00009";
ram_buffer(456) := X"00000000";
ram_buffer(457) := X"10B50013";
ram_buffer(458) := X"02402025";
ram_buffer(459) := X"0220F809";
ram_buffer(460) := X"26100001";
ram_buffer(461) := X"82050000";
ram_buffer(462) := X"00000000";
ram_buffer(463) := X"14A0FFF9";
ram_buffer(464) := X"00000000";
ram_buffer(465) := X"8FBF0044";
ram_buffer(466) := X"8FBE0040";
ram_buffer(467) := X"8FB7003C";
ram_buffer(468) := X"8FB60038";
ram_buffer(469) := X"8FB50034";
ram_buffer(470) := X"8FB40030";
ram_buffer(471) := X"8FB3002C";
ram_buffer(472) := X"8FB20028";
ram_buffer(473) := X"8FB10024";
ram_buffer(474) := X"8FB00020";
ram_buffer(475) := X"03E00008";
ram_buffer(476) := X"27BD0048";
ram_buffer(477) := X"82040001";
ram_buffer(478) := X"00000000";
ram_buffer(479) := X"10960094";
ram_buffer(480) := X"24060001";
ram_buffer(481) := X"26100002";
ram_buffer(482) := X"00003025";
ram_buffer(483) := X"2482FFD0";
ram_buffer(484) := X"304200FF";
ram_buffer(485) := X"2C42000A";
ram_buffer(486) := X"14400073";
ram_buffer(487) := X"00001025";
ram_buffer(488) := X"24030063";
ram_buffer(489) := X"10830080";
ram_buffer(490) := X"28830064";
ram_buffer(491) := X"1460005F";
ram_buffer(492) := X"24030073";
ram_buffer(493) := X"108300C7";
ram_buffer(494) := X"28830074";
ram_buffer(495) := X"14600090";
ram_buffer(496) := X"24030075";
ram_buffer(497) := X"148300F0";
ram_buffer(498) := X"24030078";
ram_buffer(499) := X"8E840000";
ram_buffer(500) := X"00000000";
ram_buffer(501) := X"2C83000A";
ram_buffer(502) := X"146001A7";
ram_buffer(503) := X"26940004";
ram_buffer(504) := X"24030001";
ram_buffer(505) := X"00032880";
ram_buffer(506) := X"00A31821";
ram_buffer(507) := X"00031840";
ram_buffer(508) := X"14600002";
ram_buffer(509) := X"0083001B";
ram_buffer(510) := X"0007000D";
ram_buffer(511) := X"00002812";
ram_buffer(512) := X"2CA5000A";
ram_buffer(513) := X"10A0FFF8";
ram_buffer(514) := X"00032880";
ram_buffer(515) := X"1060001F";
ram_buffer(516) := X"27AB0010";
ram_buffer(517) := X"27A80010";
ram_buffer(518) := X"00005025";
ram_buffer(519) := X"240C000A";
ram_buffer(520) := X"15800002";
ram_buffer(521) := X"006C001B";
ram_buffer(522) := X"0007000D";
ram_buffer(523) := X"250B0001";
ram_buffer(524) := X"24050057";
ram_buffer(525) := X"00004812";
ram_buffer(526) := X"00000000";
ram_buffer(527) := X"00000000";
ram_buffer(528) := X"14600002";
ram_buffer(529) := X"0083001B";
ram_buffer(530) := X"0007000D";
ram_buffer(531) := X"00002010";
ram_buffer(532) := X"00003812";
ram_buffer(533) := X"15400003";
ram_buffer(534) := X"01201825";
ram_buffer(535) := X"18E0005F";
ram_buffer(536) := X"00000000";
ram_buffer(537) := X"28ED000A";
ram_buffer(538) := X"11A00003";
ram_buffer(539) := X"00A72821";
ram_buffer(540) := X"24050030";
ram_buffer(541) := X"00A72821";
ram_buffer(542) := X"254A0001";
ram_buffer(543) := X"11200003";
ram_buffer(544) := X"A1050000";
ram_buffer(545) := X"1000FFE6";
ram_buffer(546) := X"01604025";
ram_buffer(547) := X"14C0012D";
ram_buffer(548) := X"A1600000";
ram_buffer(549) := X"24170020";
ram_buffer(550) := X"83B30010";
ram_buffer(551) := X"00000000";
ram_buffer(552) := X"1260017F";
ram_buffer(553) := X"00000000";
ram_buffer(554) := X"10400015";
ram_buffer(555) := X"27A30011";
ram_buffer(556) := X"10000004";
ram_buffer(557) := X"24630001";
ram_buffer(558) := X"10A00011";
ram_buffer(559) := X"00A01025";
ram_buffer(560) := X"24630001";
ram_buffer(561) := X"8064FFFF";
ram_buffer(562) := X"00000000";
ram_buffer(563) := X"1480FFFA";
ram_buffer(564) := X"2445FFFF";
ram_buffer(565) := X"10A0000A";
ram_buffer(566) := X"245EFFFE";
ram_buffer(567) := X"02E02825";
ram_buffer(568) := X"02402025";
ram_buffer(569) := X"0220F809";
ram_buffer(570) := X"27DEFFFF";
ram_buffer(571) := X"27C20001";
ram_buffer(572) := X"1C40FFFB";
ram_buffer(573) := X"02E02825";
ram_buffer(574) := X"1260FF86";
ram_buffer(575) := X"00000000";
ram_buffer(576) := X"27B70011";
ram_buffer(577) := X"02602825";
ram_buffer(578) := X"02402025";
ram_buffer(579) := X"0220F809";
ram_buffer(580) := X"26F70001";
ram_buffer(581) := X"82F3FFFF";
ram_buffer(582) := X"00000000";
ram_buffer(583) := X"1660FFFA";
ram_buffer(584) := X"02602825";
ram_buffer(585) := X"1000FF7B";
ram_buffer(586) := X"00000000";
ram_buffer(587) := X"109500FE";
ram_buffer(588) := X"24030058";
ram_buffer(589) := X"10830096";
ram_buffer(590) := X"00000000";
ram_buffer(591) := X"1080FF81";
ram_buffer(592) := X"00000000";
ram_buffer(593) := X"1000FF73";
ram_buffer(594) := X"00000000";
ram_buffer(595) := X"2485FFD0";
ram_buffer(596) := X"00021880";
ram_buffer(597) := X"00621021";
ram_buffer(598) := X"26100001";
ram_buffer(599) := X"00021040";
ram_buffer(600) := X"8204FFFF";
ram_buffer(601) := X"00451021";
ram_buffer(602) := X"308300FF";
ram_buffer(603) := X"2465FFD0";
ram_buffer(604) := X"2467FF9F";
ram_buffer(605) := X"2CA5000A";
ram_buffer(606) := X"14A0FFF4";
ram_buffer(607) := X"2CE70006";
ram_buffer(608) := X"2463FFBF";
ram_buffer(609) := X"10E0000E";
ram_buffer(610) := X"2C630006";
ram_buffer(611) := X"2485FFA9";
ram_buffer(612) := X"28A3000B";
ram_buffer(613) := X"1460FFEF";
ram_buffer(614) := X"00021880";
ram_buffer(615) := X"24030063";
ram_buffer(616) := X"1483FF82";
ram_buffer(617) := X"28830064";
ram_buffer(618) := X"82850003";
ram_buffer(619) := X"02402025";
ram_buffer(620) := X"0220F809";
ram_buffer(621) := X"26940004";
ram_buffer(622) := X"1000FF56";
ram_buffer(623) := X"00000000";
ram_buffer(624) := X"1060FF78";
ram_buffer(625) := X"24030063";
ram_buffer(626) := X"1000FFF1";
ram_buffer(627) := X"2485FFC9";
ram_buffer(628) := X"82040002";
ram_buffer(629) := X"1000FF6D";
ram_buffer(630) := X"26100003";
ram_buffer(631) := X"152000D7";
ram_buffer(632) := X"01005825";
ram_buffer(633) := X"24E50030";
ram_buffer(634) := X"250B0001";
ram_buffer(635) := X"A1050000";
ram_buffer(636) := X"10C0FFA8";
ram_buffer(637) := X"A1600000";
ram_buffer(638) := X"1000FFA7";
ram_buffer(639) := X"24170030";
ram_buffer(640) := X"24030064";
ram_buffer(641) := X"1483FF43";
ram_buffer(642) := X"00000000";
ram_buffer(643) := X"8E850000";
ram_buffer(644) := X"00000000";
ram_buffer(645) := X"04A0010D";
ram_buffer(646) := X"26940004";
ram_buffer(647) := X"27A80010";
ram_buffer(648) := X"28A3000A";
ram_buffer(649) := X"14600110";
ram_buffer(650) := X"00A03825";
ram_buffer(651) := X"24030001";
ram_buffer(652) := X"00032080";
ram_buffer(653) := X"00831821";
ram_buffer(654) := X"00031840";
ram_buffer(655) := X"14600002";
ram_buffer(656) := X"00A3001B";
ram_buffer(657) := X"0007000D";
ram_buffer(658) := X"00002012";
ram_buffer(659) := X"2C84000A";
ram_buffer(660) := X"1080FFF8";
ram_buffer(661) := X"00032080";
ram_buffer(662) := X"106000BE";
ram_buffer(663) := X"01005825";
ram_buffer(664) := X"00005025";
ram_buffer(665) := X"240C000A";
ram_buffer(666) := X"15800002";
ram_buffer(667) := X"006C001B";
ram_buffer(668) := X"0007000D";
ram_buffer(669) := X"250B0001";
ram_buffer(670) := X"24040057";
ram_buffer(671) := X"00004812";
ram_buffer(672) := X"00000000";
ram_buffer(673) := X"00000000";
ram_buffer(674) := X"14600002";
ram_buffer(675) := X"00E3001B";
ram_buffer(676) := X"0007000D";
ram_buffer(677) := X"00003810";
ram_buffer(678) := X"00002812";
ram_buffer(679) := X"15400003";
ram_buffer(680) := X"01201825";
ram_buffer(681) := X"18A000D3";
ram_buffer(682) := X"00000000";
ram_buffer(683) := X"28AD000A";
ram_buffer(684) := X"11A00003";
ram_buffer(685) := X"00852021";
ram_buffer(686) := X"24040030";
ram_buffer(687) := X"00852021";
ram_buffer(688) := X"254A0001";
ram_buffer(689) := X"112000A3";
ram_buffer(690) := X"A1040000";
ram_buffer(691) := X"1000FFE6";
ram_buffer(692) := X"01604025";
ram_buffer(693) := X"8E970000";
ram_buffer(694) := X"26940004";
ram_buffer(695) := X"82E50000";
ram_buffer(696) := X"00000000";
ram_buffer(697) := X"10A000EA";
ram_buffer(698) := X"26F30001";
ram_buffer(699) := X"10400017";
ram_buffer(700) := X"02601825";
ram_buffer(701) := X"10000004";
ram_buffer(702) := X"24630001";
ram_buffer(703) := X"10C00013";
ram_buffer(704) := X"00C01025";
ram_buffer(705) := X"24630001";
ram_buffer(706) := X"8064FFFF";
ram_buffer(707) := X"00000000";
ram_buffer(708) := X"1480FFFA";
ram_buffer(709) := X"2446FFFF";
ram_buffer(710) := X"10C0000C";
ram_buffer(711) := X"245EFFFE";
ram_buffer(712) := X"24050020";
ram_buffer(713) := X"02402025";
ram_buffer(714) := X"0220F809";
ram_buffer(715) := X"27DEFFFF";
ram_buffer(716) := X"27C20001";
ram_buffer(717) := X"1C40FFFB";
ram_buffer(718) := X"24050020";
ram_buffer(719) := X"82E50000";
ram_buffer(720) := X"00000000";
ram_buffer(721) := X"10A0FEF3";
ram_buffer(722) := X"00000000";
ram_buffer(723) := X"02402025";
ram_buffer(724) := X"0220F809";
ram_buffer(725) := X"26730001";
ram_buffer(726) := X"8265FFFF";
ram_buffer(727) := X"00000000";
ram_buffer(728) := X"10A0FEEC";
ram_buffer(729) := X"02402025";
ram_buffer(730) := X"0220F809";
ram_buffer(731) := X"26730001";
ram_buffer(732) := X"8265FFFF";
ram_buffer(733) := X"00000000";
ram_buffer(734) := X"14A0FFF5";
ram_buffer(735) := X"02402025";
ram_buffer(736) := X"1000FEE4";
ram_buffer(737) := X"00000000";
ram_buffer(738) := X"1483FEE2";
ram_buffer(739) := X"00000000";
ram_buffer(740) := X"8E850000";
ram_buffer(741) := X"00000000";
ram_buffer(742) := X"2CA30010";
ram_buffer(743) := X"146000B4";
ram_buffer(744) := X"26940004";
ram_buffer(745) := X"24030001";
ram_buffer(746) := X"00031900";
ram_buffer(747) := X"14600002";
ram_buffer(748) := X"00A3001B";
ram_buffer(749) := X"0007000D";
ram_buffer(750) := X"00003812";
ram_buffer(751) := X"2CE70010";
ram_buffer(752) := X"10E0FFF9";
ram_buffer(753) := X"00000000";
ram_buffer(754) := X"106000A5";
ram_buffer(755) := X"00000000";
ram_buffer(756) := X"24070058";
ram_buffer(757) := X"27A90010";
ram_buffer(758) := X"10870019";
ram_buffer(759) := X"00005025";
ram_buffer(760) := X"14600002";
ram_buffer(761) := X"00A3001B";
ram_buffer(762) := X"0007000D";
ram_buffer(763) := X"00002810";
ram_buffer(764) := X"00004012";
ram_buffer(765) := X"15400003";
ram_buffer(766) := X"00031902";
ram_buffer(767) := X"19000082";
ram_buffer(768) := X"00000000";
ram_buffer(769) := X"290B000A";
ram_buffer(770) := X"25240001";
ram_buffer(771) := X"11600002";
ram_buffer(772) := X"24070057";
ram_buffer(773) := X"24070030";
ram_buffer(774) := X"00E83821";
ram_buffer(775) := X"254A0001";
ram_buffer(776) := X"10600019";
ram_buffer(777) := X"A1270000";
ram_buffer(778) := X"1000FFED";
ram_buffer(779) := X"00804825";
ram_buffer(780) := X"10600078";
ram_buffer(781) := X"25070030";
ram_buffer(782) := X"01202025";
ram_buffer(783) := X"00804825";
ram_buffer(784) := X"14600002";
ram_buffer(785) := X"00A3001B";
ram_buffer(786) := X"0007000D";
ram_buffer(787) := X"00002810";
ram_buffer(788) := X"00004012";
ram_buffer(789) := X"15400003";
ram_buffer(790) := X"00031902";
ram_buffer(791) := X"1900FFF4";
ram_buffer(792) := X"00000000";
ram_buffer(793) := X"290B000A";
ram_buffer(794) := X"25240001";
ram_buffer(795) := X"11600002";
ram_buffer(796) := X"24070037";
ram_buffer(797) := X"24070030";
ram_buffer(798) := X"00E83821";
ram_buffer(799) := X"254A0001";
ram_buffer(800) := X"1460FFEE";
ram_buffer(801) := X"A1270000";
ram_buffer(802) := X"14C00030";
ram_buffer(803) := X"A0800000";
ram_buffer(804) := X"24170020";
ram_buffer(805) := X"83B30010";
ram_buffer(806) := X"00000000";
ram_buffer(807) := X"12600084";
ram_buffer(808) := X"00000000";
ram_buffer(809) := X"10400015";
ram_buffer(810) := X"27A30011";
ram_buffer(811) := X"10000004";
ram_buffer(812) := X"24630001";
ram_buffer(813) := X"10A00011";
ram_buffer(814) := X"00A01025";
ram_buffer(815) := X"24630001";
ram_buffer(816) := X"8064FFFF";
ram_buffer(817) := X"00000000";
ram_buffer(818) := X"1480FFFA";
ram_buffer(819) := X"2445FFFF";
ram_buffer(820) := X"10A0000A";
ram_buffer(821) := X"245EFFFE";
ram_buffer(822) := X"02E02825";
ram_buffer(823) := X"02402025";
ram_buffer(824) := X"0220F809";
ram_buffer(825) := X"27DEFFFF";
ram_buffer(826) := X"27C20001";
ram_buffer(827) := X"1C40FFFB";
ram_buffer(828) := X"02E02825";
ram_buffer(829) := X"1260FE87";
ram_buffer(830) := X"00000000";
ram_buffer(831) := X"27B70011";
ram_buffer(832) := X"02602825";
ram_buffer(833) := X"02402025";
ram_buffer(834) := X"0220F809";
ram_buffer(835) := X"26F70001";
ram_buffer(836) := X"82F3FFFF";
ram_buffer(837) := X"00000000";
ram_buffer(838) := X"1660FFFA";
ram_buffer(839) := X"02602825";
ram_buffer(840) := X"1000FE7C";
ram_buffer(841) := X"00000000";
ram_buffer(842) := X"24050025";
ram_buffer(843) := X"0220F809";
ram_buffer(844) := X"02402025";
ram_buffer(845) := X"1000FE77";
ram_buffer(846) := X"00000000";
ram_buffer(847) := X"1000FEB8";
ram_buffer(848) := X"01604025";
ram_buffer(849) := X"1000FED4";
ram_buffer(850) := X"24170030";
ram_buffer(851) := X"1000FFD1";
ram_buffer(852) := X"24170030";
ram_buffer(853) := X"10C00039";
ram_buffer(854) := X"A1600000";
ram_buffer(855) := X"24170030";
ram_buffer(856) := X"83B30010";
ram_buffer(857) := X"00000000";
ram_buffer(858) := X"12600045";
ram_buffer(859) := X"00000000";
ram_buffer(860) := X"10400015";
ram_buffer(861) := X"27A30011";
ram_buffer(862) := X"10000004";
ram_buffer(863) := X"24630001";
ram_buffer(864) := X"10A00011";
ram_buffer(865) := X"00A01025";
ram_buffer(866) := X"24630001";
ram_buffer(867) := X"8064FFFF";
ram_buffer(868) := X"00000000";
ram_buffer(869) := X"1480FFFA";
ram_buffer(870) := X"2445FFFF";
ram_buffer(871) := X"10A0000A";
ram_buffer(872) := X"245EFFFE";
ram_buffer(873) := X"02E02825";
ram_buffer(874) := X"02402025";
ram_buffer(875) := X"0220F809";
ram_buffer(876) := X"27DEFFFF";
ram_buffer(877) := X"27C20001";
ram_buffer(878) := X"1C40FFFB";
ram_buffer(879) := X"02E02825";
ram_buffer(880) := X"1260FE54";
ram_buffer(881) := X"00000000";
ram_buffer(882) := X"27B70011";
ram_buffer(883) := X"02602825";
ram_buffer(884) := X"02402025";
ram_buffer(885) := X"0220F809";
ram_buffer(886) := X"26F70001";
ram_buffer(887) := X"82F3FFFF";
ram_buffer(888) := X"00000000";
ram_buffer(889) := X"1660FFFA";
ram_buffer(890) := X"02602825";
ram_buffer(891) := X"1000FE49";
ram_buffer(892) := X"00000000";
ram_buffer(893) := X"1120000D";
ram_buffer(894) := X"24A40030";
ram_buffer(895) := X"01005825";
ram_buffer(896) := X"1000FF19";
ram_buffer(897) := X"01604025";
ram_buffer(898) := X"1460000E";
ram_buffer(899) := X"01202025";
ram_buffer(900) := X"25070030";
ram_buffer(901) := X"25240001";
ram_buffer(902) := X"A1270000";
ram_buffer(903) := X"10C0FF9C";
ram_buffer(904) := X"A0800000";
ram_buffer(905) := X"1000FF9B";
ram_buffer(906) := X"24170030";
ram_buffer(907) := X"250B0001";
ram_buffer(908) := X"A1040000";
ram_buffer(909) := X"14C0FFC9";
ram_buffer(910) := X"A1600000";
ram_buffer(911) := X"1000FFC8";
ram_buffer(912) := X"24170020";
ram_buffer(913) := X"1000FF66";
ram_buffer(914) := X"00804825";
ram_buffer(915) := X"2403002D";
ram_buffer(916) := X"00052823";
ram_buffer(917) := X"A3A30010";
ram_buffer(918) := X"1000FEF1";
ram_buffer(919) := X"27A80011";
ram_buffer(920) := X"1000FF89";
ram_buffer(921) := X"27A40010";
ram_buffer(922) := X"1000FEFD";
ram_buffer(923) := X"24030001";
ram_buffer(924) := X"1000FF57";
ram_buffer(925) := X"24030001";
ram_buffer(926) := X"1000FE66";
ram_buffer(927) := X"24030001";
ram_buffer(928) := X"1040FE24";
ram_buffer(929) := X"245EFFFF";
ram_buffer(930) := X"1000FFC7";
ram_buffer(931) := X"02E02825";
ram_buffer(932) := X"1040FE20";
ram_buffer(933) := X"245EFFFF";
ram_buffer(934) := X"1000FF22";
ram_buffer(935) := X"24050020";
ram_buffer(936) := X"1040FE1C";
ram_buffer(937) := X"245EFFFF";
ram_buffer(938) := X"1000FE8D";
ram_buffer(939) := X"02E02825";
ram_buffer(940) := X"1040FE18";
ram_buffer(941) := X"245EFFFF";
ram_buffer(942) := X"1000FF88";
ram_buffer(943) := X"02E02825";
ram_buffer(944) := X"AF858010";
ram_buffer(945) := X"03E00008";
ram_buffer(946) := X"AF84800C";
ram_buffer(947) := X"27BDFFE0";
ram_buffer(948) := X"27A20024";
ram_buffer(949) := X"AFA50024";
ram_buffer(950) := X"AFA60028";
ram_buffer(951) := X"8F858010";
ram_buffer(952) := X"00803025";
ram_buffer(953) := X"8F84800C";
ram_buffer(954) := X"AFA7002C";
ram_buffer(955) := X"00403825";
ram_buffer(956) := X"AFBF001C";
ram_buffer(957) := X"0C0001B4";
ram_buffer(958) := X"AFA20010";
ram_buffer(959) := X"8FBF001C";
ram_buffer(960) := X"00000000";
ram_buffer(961) := X"03E00008";
ram_buffer(962) := X"27BD0020";
ram_buffer(963) := X"27BDFFC0";
ram_buffer(964) := X"AFB50034";
ram_buffer(965) := X"27B50048";
ram_buffer(966) := X"AFB3002C";
ram_buffer(967) := X"AFB20028";
ram_buffer(968) := X"AFB10024";
ram_buffer(969) := X"AFBF003C";
ram_buffer(970) := X"AFB60038";
ram_buffer(971) := X"AFB40030";
ram_buffer(972) := X"AFB00020";
ram_buffer(973) := X"00801825";
ram_buffer(974) := X"00A08825";
ram_buffer(975) := X"AFA60048";
ram_buffer(976) := X"AFA7004C";
ram_buffer(977) := X"AFB5001C";
ram_buffer(978) := X"24120025";
ram_buffer(979) := X"24130030";
ram_buffer(980) := X"82220000";
ram_buffer(981) := X"00000000";
ram_buffer(982) := X"10400009";
ram_buffer(983) := X"00000000";
ram_buffer(984) := X"10520012";
ram_buffer(985) := X"00000000";
ram_buffer(986) := X"A0620000";
ram_buffer(987) := X"26310001";
ram_buffer(988) := X"82220000";
ram_buffer(989) := X"00000000";
ram_buffer(990) := X"1440FFF9";
ram_buffer(991) := X"24630001";
ram_buffer(992) := X"A0600000";
ram_buffer(993) := X"8FBF003C";
ram_buffer(994) := X"8FB60038";
ram_buffer(995) := X"8FB50034";
ram_buffer(996) := X"8FB40030";
ram_buffer(997) := X"8FB3002C";
ram_buffer(998) := X"8FB20028";
ram_buffer(999) := X"8FB10024";
ram_buffer(1000) := X"8FB00020";
ram_buffer(1001) := X"03E00008";
ram_buffer(1002) := X"27BD0040";
ram_buffer(1003) := X"82240001";
ram_buffer(1004) := X"00000000";
ram_buffer(1005) := X"10930090";
ram_buffer(1006) := X"24070001";
ram_buffer(1007) := X"26310002";
ram_buffer(1008) := X"00003825";
ram_buffer(1009) := X"2482FFD0";
ram_buffer(1010) := X"304200FF";
ram_buffer(1011) := X"2C42000A";
ram_buffer(1012) := X"14400043";
ram_buffer(1013) := X"00008025";
ram_buffer(1014) := X"24020063";
ram_buffer(1015) := X"10820050";
ram_buffer(1016) := X"28820064";
ram_buffer(1017) := X"1440007C";
ram_buffer(1018) := X"24020073";
ram_buffer(1019) := X"108200C3";
ram_buffer(1020) := X"28820074";
ram_buffer(1021) := X"1440008C";
ram_buffer(1022) := X"24020075";
ram_buffer(1023) := X"148200ED";
ram_buffer(1024) := X"24020078";
ram_buffer(1025) := X"8EA40000";
ram_buffer(1026) := X"00000000";
ram_buffer(1027) := X"2C82000A";
ram_buffer(1028) := X"144001AA";
ram_buffer(1029) := X"26B50004";
ram_buffer(1030) := X"24020001";
ram_buffer(1031) := X"00022880";
ram_buffer(1032) := X"00A21021";
ram_buffer(1033) := X"00021040";
ram_buffer(1034) := X"14400002";
ram_buffer(1035) := X"0082001B";
ram_buffer(1036) := X"0007000D";
ram_buffer(1037) := X"00002812";
ram_buffer(1038) := X"2CA5000A";
ram_buffer(1039) := X"10A0FFF8";
ram_buffer(1040) := X"00022880";
ram_buffer(1041) := X"1040003B";
ram_buffer(1042) := X"27AB0010";
ram_buffer(1043) := X"27A80010";
ram_buffer(1044) := X"00005025";
ram_buffer(1045) := X"240C000A";
ram_buffer(1046) := X"15800002";
ram_buffer(1047) := X"004C001B";
ram_buffer(1048) := X"0007000D";
ram_buffer(1049) := X"250B0001";
ram_buffer(1050) := X"24050057";
ram_buffer(1051) := X"00004812";
ram_buffer(1052) := X"00000000";
ram_buffer(1053) := X"00000000";
ram_buffer(1054) := X"14400002";
ram_buffer(1055) := X"0082001B";
ram_buffer(1056) := X"0007000D";
ram_buffer(1057) := X"00002010";
ram_buffer(1058) := X"00003012";
ram_buffer(1059) := X"15400003";
ram_buffer(1060) := X"01201025";
ram_buffer(1061) := X"18C0005B";
ram_buffer(1062) := X"00000000";
ram_buffer(1063) := X"28CD000A";
ram_buffer(1064) := X"11A00003";
ram_buffer(1065) := X"00A62821";
ram_buffer(1066) := X"24050030";
ram_buffer(1067) := X"00A62821";
ram_buffer(1068) := X"254A0001";
ram_buffer(1069) := X"1120001F";
ram_buffer(1070) := X"A1050000";
ram_buffer(1071) := X"1000FFE6";
ram_buffer(1072) := X"01604025";
ram_buffer(1073) := X"2485FFD0";
ram_buffer(1074) := X"00101080";
ram_buffer(1075) := X"00508021";
ram_buffer(1076) := X"26310001";
ram_buffer(1077) := X"00108040";
ram_buffer(1078) := X"8224FFFF";
ram_buffer(1079) := X"02058021";
ram_buffer(1080) := X"308200FF";
ram_buffer(1081) := X"2445FFD0";
ram_buffer(1082) := X"2446FF9F";
ram_buffer(1083) := X"2CA5000A";
ram_buffer(1084) := X"14A0FFF4";
ram_buffer(1085) := X"2CC60006";
ram_buffer(1086) := X"2442FFBF";
ram_buffer(1087) := X"10C00032";
ram_buffer(1088) := X"2C420006";
ram_buffer(1089) := X"2485FFA9";
ram_buffer(1090) := X"28A2000B";
ram_buffer(1091) := X"1440FFEF";
ram_buffer(1092) := X"00101080";
ram_buffer(1093) := X"24020063";
ram_buffer(1094) := X"1482FFB2";
ram_buffer(1095) := X"28820064";
ram_buffer(1096) := X"8EA20000";
ram_buffer(1097) := X"24630001";
ram_buffer(1098) := X"A062FFFF";
ram_buffer(1099) := X"1000FF88";
ram_buffer(1100) := X"26B50004";
ram_buffer(1101) := X"14E00109";
ram_buffer(1102) := X"A1600000";
ram_buffer(1103) := X"24050020";
ram_buffer(1104) := X"83B40010";
ram_buffer(1105) := X"00000000";
ram_buffer(1106) := X"1280014A";
ram_buffer(1107) := X"00000000";
ram_buffer(1108) := X"12000013";
ram_buffer(1109) := X"27A20011";
ram_buffer(1110) := X"10000004";
ram_buffer(1111) := X"24420001";
ram_buffer(1112) := X"10C0000F";
ram_buffer(1113) := X"00C08025";
ram_buffer(1114) := X"24420001";
ram_buffer(1115) := X"8044FFFF";
ram_buffer(1116) := X"00000000";
ram_buffer(1117) := X"1480FFFA";
ram_buffer(1118) := X"2606FFFF";
ram_buffer(1119) := X"10C00008";
ram_buffer(1120) := X"2610FFFE";
ram_buffer(1121) := X"06000145";
ram_buffer(1122) := X"00000000";
ram_buffer(1123) := X"26100001";
ram_buffer(1124) := X"00602025";
ram_buffer(1125) := X"0C000707";
ram_buffer(1126) := X"02003025";
ram_buffer(1127) := X"00501821";
ram_buffer(1128) := X"27A20011";
ram_buffer(1129) := X"24630001";
ram_buffer(1130) := X"24420001";
ram_buffer(1131) := X"A074FFFF";
ram_buffer(1132) := X"8054FFFF";
ram_buffer(1133) := X"00000000";
ram_buffer(1134) := X"1680FFFB";
ram_buffer(1135) := X"24630001";
ram_buffer(1136) := X"1000FF63";
ram_buffer(1137) := X"2463FFFF";
ram_buffer(1138) := X"1040FF84";
ram_buffer(1139) := X"24020063";
ram_buffer(1140) := X"1000FFCD";
ram_buffer(1141) := X"2485FFC9";
ram_buffer(1142) := X"109200DB";
ram_buffer(1143) := X"24020058";
ram_buffer(1144) := X"10820076";
ram_buffer(1145) := X"00000000";
ram_buffer(1146) := X"1080FF65";
ram_buffer(1147) := X"00000000";
ram_buffer(1148) := X"1000FF57";
ram_buffer(1149) := X"00000000";
ram_buffer(1150) := X"82240002";
ram_buffer(1151) := X"1000FF71";
ram_buffer(1152) := X"26310003";
ram_buffer(1153) := X"152000D3";
ram_buffer(1154) := X"01005825";
ram_buffer(1155) := X"24C50030";
ram_buffer(1156) := X"250B0001";
ram_buffer(1157) := X"A1050000";
ram_buffer(1158) := X"10E0FFC8";
ram_buffer(1159) := X"A1600000";
ram_buffer(1160) := X"1000FFC7";
ram_buffer(1161) := X"24050030";
ram_buffer(1162) := X"24020064";
ram_buffer(1163) := X"1482FF48";
ram_buffer(1164) := X"00000000";
ram_buffer(1165) := X"8EA50000";
ram_buffer(1166) := X"00000000";
ram_buffer(1167) := X"04A00106";
ram_buffer(1168) := X"26B50004";
ram_buffer(1169) := X"27A80010";
ram_buffer(1170) := X"28A2000A";
ram_buffer(1171) := X"14400117";
ram_buffer(1172) := X"00A03025";
ram_buffer(1173) := X"24020001";
ram_buffer(1174) := X"00022080";
ram_buffer(1175) := X"00821021";
ram_buffer(1176) := X"00021040";
ram_buffer(1177) := X"14400002";
ram_buffer(1178) := X"00A2001B";
ram_buffer(1179) := X"0007000D";
ram_buffer(1180) := X"00002012";
ram_buffer(1181) := X"2C84000A";
ram_buffer(1182) := X"1080FFF8";
ram_buffer(1183) := X"00022080";
ram_buffer(1184) := X"104000BA";
ram_buffer(1185) := X"01005825";
ram_buffer(1186) := X"00005025";
ram_buffer(1187) := X"240C000A";
ram_buffer(1188) := X"15800002";
ram_buffer(1189) := X"004C001B";
ram_buffer(1190) := X"0007000D";
ram_buffer(1191) := X"250B0001";
ram_buffer(1192) := X"24040057";
ram_buffer(1193) := X"00004812";
ram_buffer(1194) := X"00000000";
ram_buffer(1195) := X"00000000";
ram_buffer(1196) := X"14400002";
ram_buffer(1197) := X"00C2001B";
ram_buffer(1198) := X"0007000D";
ram_buffer(1199) := X"00003010";
ram_buffer(1200) := X"00002812";
ram_buffer(1201) := X"15400003";
ram_buffer(1202) := X"01201025";
ram_buffer(1203) := X"18A000CC";
ram_buffer(1204) := X"00000000";
ram_buffer(1205) := X"28AD000A";
ram_buffer(1206) := X"11A00003";
ram_buffer(1207) := X"00852021";
ram_buffer(1208) := X"24040030";
ram_buffer(1209) := X"00852021";
ram_buffer(1210) := X"254A0001";
ram_buffer(1211) := X"1120009F";
ram_buffer(1212) := X"A1040000";
ram_buffer(1213) := X"1000FFE6";
ram_buffer(1214) := X"01604025";
ram_buffer(1215) := X"8EB60000";
ram_buffer(1216) := X"26B50004";
ram_buffer(1217) := X"82C20000";
ram_buffer(1218) := X"00000000";
ram_buffer(1219) := X"104000ED";
ram_buffer(1220) := X"26D40001";
ram_buffer(1221) := X"12000018";
ram_buffer(1222) := X"02802025";
ram_buffer(1223) := X"10000004";
ram_buffer(1224) := X"24840001";
ram_buffer(1225) := X"10C00014";
ram_buffer(1226) := X"00C08025";
ram_buffer(1227) := X"24840001";
ram_buffer(1228) := X"8085FFFF";
ram_buffer(1229) := X"00000000";
ram_buffer(1230) := X"14A0FFFA";
ram_buffer(1231) := X"2606FFFF";
ram_buffer(1232) := X"10C0000D";
ram_buffer(1233) := X"2610FFFE";
ram_buffer(1234) := X"060000D0";
ram_buffer(1235) := X"00000000";
ram_buffer(1236) := X"26100001";
ram_buffer(1237) := X"00602025";
ram_buffer(1238) := X"02003025";
ram_buffer(1239) := X"0C000707";
ram_buffer(1240) := X"24050020";
ram_buffer(1241) := X"00401825";
ram_buffer(1242) := X"82C20000";
ram_buffer(1243) := X"00000000";
ram_buffer(1244) := X"1040FEF7";
ram_buffer(1245) := X"00701821";
ram_buffer(1246) := X"24630001";
ram_buffer(1247) := X"A062FFFF";
ram_buffer(1248) := X"26940001";
ram_buffer(1249) := X"8282FFFF";
ram_buffer(1250) := X"00000000";
ram_buffer(1251) := X"1040FEF0";
ram_buffer(1252) := X"26940001";
ram_buffer(1253) := X"24630001";
ram_buffer(1254) := X"A062FFFF";
ram_buffer(1255) := X"8282FFFF";
ram_buffer(1256) := X"00000000";
ram_buffer(1257) := X"1440FFF5";
ram_buffer(1258) := X"24630001";
ram_buffer(1259) := X"1000FEE8";
ram_buffer(1260) := X"2463FFFF";
ram_buffer(1261) := X"1482FEE6";
ram_buffer(1262) := X"00000000";
ram_buffer(1263) := X"8EA50000";
ram_buffer(1264) := X"00000000";
ram_buffer(1265) := X"2CA20010";
ram_buffer(1266) := X"144000BA";
ram_buffer(1267) := X"26B50004";
ram_buffer(1268) := X"24020001";
ram_buffer(1269) := X"00021100";
ram_buffer(1270) := X"14400002";
ram_buffer(1271) := X"00A2001B";
ram_buffer(1272) := X"0007000D";
ram_buffer(1273) := X"00003012";
ram_buffer(1274) := X"2CC60010";
ram_buffer(1275) := X"10C0FFF9";
ram_buffer(1276) := X"00000000";
ram_buffer(1277) := X"1040009D";
ram_buffer(1278) := X"00000000";
ram_buffer(1279) := X"24060058";
ram_buffer(1280) := X"27A90010";
ram_buffer(1281) := X"10860019";
ram_buffer(1282) := X"00005025";
ram_buffer(1283) := X"14400002";
ram_buffer(1284) := X"00A2001B";
ram_buffer(1285) := X"0007000D";
ram_buffer(1286) := X"00002810";
ram_buffer(1287) := X"00004012";
ram_buffer(1288) := X"15400003";
ram_buffer(1289) := X"00021102";
ram_buffer(1290) := X"19000080";
ram_buffer(1291) := X"00000000";
ram_buffer(1292) := X"290B000A";
ram_buffer(1293) := X"25240001";
ram_buffer(1294) := X"11600002";
ram_buffer(1295) := X"24060057";
ram_buffer(1296) := X"24060030";
ram_buffer(1297) := X"00C83021";
ram_buffer(1298) := X"254A0001";
ram_buffer(1299) := X"10400019";
ram_buffer(1300) := X"A1260000";
ram_buffer(1301) := X"1000FFED";
ram_buffer(1302) := X"00804825";
ram_buffer(1303) := X"10400076";
ram_buffer(1304) := X"25060030";
ram_buffer(1305) := X"01202025";
ram_buffer(1306) := X"00804825";
ram_buffer(1307) := X"14400002";
ram_buffer(1308) := X"00A2001B";
ram_buffer(1309) := X"0007000D";
ram_buffer(1310) := X"00002810";
ram_buffer(1311) := X"00004012";
ram_buffer(1312) := X"15400003";
ram_buffer(1313) := X"00021102";
ram_buffer(1314) := X"1900FFF4";
ram_buffer(1315) := X"00000000";
ram_buffer(1316) := X"290B000A";
ram_buffer(1317) := X"25240001";
ram_buffer(1318) := X"11600002";
ram_buffer(1319) := X"24060037";
ram_buffer(1320) := X"24060030";
ram_buffer(1321) := X"00C83021";
ram_buffer(1322) := X"254A0001";
ram_buffer(1323) := X"1440FFEE";
ram_buffer(1324) := X"A1260000";
ram_buffer(1325) := X"14E0002B";
ram_buffer(1326) := X"A0800000";
ram_buffer(1327) := X"24050020";
ram_buffer(1328) := X"83B40010";
ram_buffer(1329) := X"00000000";
ram_buffer(1330) := X"1280006A";
ram_buffer(1331) := X"00000000";
ram_buffer(1332) := X"12000013";
ram_buffer(1333) := X"27A20011";
ram_buffer(1334) := X"10000004";
ram_buffer(1335) := X"24420001";
ram_buffer(1336) := X"10C0000F";
ram_buffer(1337) := X"00C08025";
ram_buffer(1338) := X"24420001";
ram_buffer(1339) := X"8044FFFF";
ram_buffer(1340) := X"00000000";
ram_buffer(1341) := X"1480FFFA";
ram_buffer(1342) := X"2606FFFF";
ram_buffer(1343) := X"10C00008";
ram_buffer(1344) := X"2610FFFE";
ram_buffer(1345) := X"06000063";
ram_buffer(1346) := X"00000000";
ram_buffer(1347) := X"26100001";
ram_buffer(1348) := X"00602025";
ram_buffer(1349) := X"0C000707";
ram_buffer(1350) := X"02003025";
ram_buffer(1351) := X"00501821";
ram_buffer(1352) := X"27A20011";
ram_buffer(1353) := X"24630001";
ram_buffer(1354) := X"24420001";
ram_buffer(1355) := X"A074FFFF";
ram_buffer(1356) := X"8054FFFF";
ram_buffer(1357) := X"00000000";
ram_buffer(1358) := X"1680FFFB";
ram_buffer(1359) := X"24630001";
ram_buffer(1360) := X"1000FE83";
ram_buffer(1361) := X"2463FFFF";
ram_buffer(1362) := X"A0720000";
ram_buffer(1363) := X"1000FE80";
ram_buffer(1364) := X"24630001";
ram_buffer(1365) := X"1000FEC0";
ram_buffer(1366) := X"01604025";
ram_buffer(1367) := X"1000FEF8";
ram_buffer(1368) := X"24050030";
ram_buffer(1369) := X"1000FFD6";
ram_buffer(1370) := X"24050030";
ram_buffer(1371) := X"10E0002D";
ram_buffer(1372) := X"A1600000";
ram_buffer(1373) := X"24050030";
ram_buffer(1374) := X"83B40010";
ram_buffer(1375) := X"00000000";
ram_buffer(1376) := X"1280003C";
ram_buffer(1377) := X"00000000";
ram_buffer(1378) := X"12000013";
ram_buffer(1379) := X"27A20011";
ram_buffer(1380) := X"10000004";
ram_buffer(1381) := X"24420001";
ram_buffer(1382) := X"10C0000F";
ram_buffer(1383) := X"00C08025";
ram_buffer(1384) := X"24420001";
ram_buffer(1385) := X"8044FFFF";
ram_buffer(1386) := X"00000000";
ram_buffer(1387) := X"1480FFFA";
ram_buffer(1388) := X"2606FFFF";
ram_buffer(1389) := X"10C00008";
ram_buffer(1390) := X"2610FFFE";
ram_buffer(1391) := X"06000039";
ram_buffer(1392) := X"00000000";
ram_buffer(1393) := X"26100001";
ram_buffer(1394) := X"00602025";
ram_buffer(1395) := X"0C000707";
ram_buffer(1396) := X"02003025";
ram_buffer(1397) := X"00501821";
ram_buffer(1398) := X"27A20011";
ram_buffer(1399) := X"24630001";
ram_buffer(1400) := X"24420001";
ram_buffer(1401) := X"A074FFFF";
ram_buffer(1402) := X"8054FFFF";
ram_buffer(1403) := X"00000000";
ram_buffer(1404) := X"1680FFFB";
ram_buffer(1405) := X"24630001";
ram_buffer(1406) := X"1000FE55";
ram_buffer(1407) := X"2463FFFF";
ram_buffer(1408) := X"11200004";
ram_buffer(1409) := X"24A40030";
ram_buffer(1410) := X"01005825";
ram_buffer(1411) := X"1000FF20";
ram_buffer(1412) := X"01604025";
ram_buffer(1413) := X"250B0001";
ram_buffer(1414) := X"A1040000";
ram_buffer(1415) := X"14E0FFD5";
ram_buffer(1416) := X"A1600000";
ram_buffer(1417) := X"1000FFD4";
ram_buffer(1418) := X"24050020";
ram_buffer(1419) := X"14400008";
ram_buffer(1420) := X"01202025";
ram_buffer(1421) := X"25060030";
ram_buffer(1422) := X"25240001";
ram_buffer(1423) := X"A1260000";
ram_buffer(1424) := X"10E0FF9E";
ram_buffer(1425) := X"A0800000";
ram_buffer(1426) := X"1000FF9D";
ram_buffer(1427) := X"24050030";
ram_buffer(1428) := X"1000FF6E";
ram_buffer(1429) := X"00804825";
ram_buffer(1430) := X"2402002D";
ram_buffer(1431) := X"00052823";
ram_buffer(1432) := X"A3A20010";
ram_buffer(1433) := X"1000FEF8";
ram_buffer(1434) := X"27A80011";
ram_buffer(1435) := X"1000FF91";
ram_buffer(1436) := X"27A40010";
ram_buffer(1437) := X"1200FE36";
ram_buffer(1438) := X"00602025";
ram_buffer(1439) := X"0C000707";
ram_buffer(1440) := X"02003025";
ram_buffer(1441) := X"1000FE32";
ram_buffer(1442) := X"00501821";
ram_buffer(1443) := X"1000FF30";
ram_buffer(1444) := X"00008025";
ram_buffer(1445) := X"1000FF9D";
ram_buffer(1446) := X"00008025";
ram_buffer(1447) := X"1000FEBB";
ram_buffer(1448) := X"00008025";
ram_buffer(1449) := X"1000FFC7";
ram_buffer(1450) := X"00008025";
ram_buffer(1451) := X"1000FEF6";
ram_buffer(1452) := X"24020001";
ram_buffer(1453) := X"1000FF51";
ram_buffer(1454) := X"24020001";
ram_buffer(1455) := X"1000FE63";
ram_buffer(1456) := X"24020001";
ram_buffer(1457) := X"1200FE22";
ram_buffer(1458) := X"2610FFFF";
ram_buffer(1459) := X"1000FF1E";
ram_buffer(1460) := X"00000000";
ram_buffer(1461) := X"03E00008";
ram_buffer(1462) := X"00000000";
ram_buffer(1463) := X"27BDFFE0";
ram_buffer(1464) := X"AFBF001C";
ram_buffer(1465) := X"AFB10018";
ram_buffer(1466) := X"AFB00014";
ram_buffer(1467) := X"3C111000";
ram_buffer(1468) := X"8E2226A0";
ram_buffer(1469) := X"00000000";
ram_buffer(1470) := X"8C420004";
ram_buffer(1471) := X"00000000";
ram_buffer(1472) := X"2C430008";
ram_buffer(1473) := X"1060000F";
ram_buffer(1474) := X"3C101000";
ram_buffer(1475) := X"261026A4";
ram_buffer(1476) := X"000210C0";
ram_buffer(1477) := X"02021021";
ram_buffer(1478) := X"8C430000";
ram_buffer(1479) := X"8C440004";
ram_buffer(1480) := X"0060F809";
ram_buffer(1481) := X"00000000";
ram_buffer(1482) := X"8E2226A0";
ram_buffer(1483) := X"00000000";
ram_buffer(1484) := X"8C420004";
ram_buffer(1485) := X"00000000";
ram_buffer(1486) := X"2C430008";
ram_buffer(1487) := X"1460FFF4";
ram_buffer(1488) := X"00000000";
ram_buffer(1489) := X"8FBF001C";
ram_buffer(1490) := X"8FB10018";
ram_buffer(1491) := X"8FB00014";
ram_buffer(1492) := X"03E00008";
ram_buffer(1493) := X"27BD0020";
ram_buffer(1494) := X"8F82802C";
ram_buffer(1495) := X"00000000";
ram_buffer(1496) := X"8C430004";
ram_buffer(1497) := X"8F82801C";
ram_buffer(1498) := X"8F848018";
ram_buffer(1499) := X"24420001";
ram_buffer(1500) := X"304201FF";
ram_buffer(1501) := X"10440008";
ram_buffer(1502) := X"00000000";
ram_buffer(1503) := X"8F84801C";
ram_buffer(1504) := X"3C051000";
ram_buffer(1505) := X"24A524A0";
ram_buffer(1506) := X"306300FF";
ram_buffer(1507) := X"00852021";
ram_buffer(1508) := X"A0830000";
ram_buffer(1509) := X"AF82801C";
ram_buffer(1510) := X"03E00008";
ram_buffer(1511) := X"00000000";
ram_buffer(1512) := X"8F828028";
ram_buffer(1513) := X"24030003";
ram_buffer(1514) := X"AC430000";
ram_buffer(1515) := X"8F998004";
ram_buffer(1516) := X"00000000";
ram_buffer(1517) := X"03200008";
ram_buffer(1518) := X"00000000";
ram_buffer(1519) := X"8F83802C";
ram_buffer(1520) := X"00000000";
ram_buffer(1521) := X"8C620000";
ram_buffer(1522) := X"00000000";
ram_buffer(1523) := X"30420002";
ram_buffer(1524) := X"1040FFFC";
ram_buffer(1525) := X"00000000";
ram_buffer(1526) := X"AC650008";
ram_buffer(1527) := X"03E00008";
ram_buffer(1528) := X"00000000";
ram_buffer(1529) := X"8F828024";
ram_buffer(1530) := X"24030007";
ram_buffer(1531) := X"AC430000";
ram_buffer(1532) := X"8F828014";
ram_buffer(1533) := X"24060004";
ram_buffer(1534) := X"24420001";
ram_buffer(1535) := X"27858014";
ram_buffer(1536) := X"24040004";
ram_buffer(1537) := X"0800016A";
ram_buffer(1538) := X"AF828014";
ram_buffer(1539) := X"3C02F000";
ram_buffer(1540) := X"8C420004";
ram_buffer(1541) := X"3C031000";
ram_buffer(1542) := X"24631D5C";
ram_buffer(1543) := X"00021080";
ram_buffer(1544) := X"00431021";
ram_buffer(1545) := X"8C420000";
ram_buffer(1546) := X"24030002";
ram_buffer(1547) := X"AC430000";
ram_buffer(1548) := X"8F998008";
ram_buffer(1549) := X"00000000";
ram_buffer(1550) := X"03200008";
ram_buffer(1551) := X"00000000";
ram_buffer(1552) := X"3C022000";
ram_buffer(1553) := X"AF828030";
ram_buffer(1554) := X"3C022002";
ram_buffer(1555) := X"AF828024";
ram_buffer(1556) := X"3C051000";
ram_buffer(1557) := X"3C022004";
ram_buffer(1558) := X"27BDFFE8";
ram_buffer(1559) := X"AF82802C";
ram_buffer(1560) := X"24A517BC";
ram_buffer(1561) := X"3C022003";
ram_buffer(1562) := X"AF828028";
ram_buffer(1563) := X"AFBF0014";
ram_buffer(1564) := X"0C0003B0";
ram_buffer(1565) := X"00002025";
ram_buffer(1566) := X"8F828024";
ram_buffer(1567) := X"3403C350";
ram_buffer(1568) := X"AC430004";
ram_buffer(1569) := X"8F838028";
ram_buffer(1570) := X"24050001";
ram_buffer(1571) := X"AC650000";
ram_buffer(1572) := X"3C041000";
ram_buffer(1573) := X"3C032001";
ram_buffer(1574) := X"AC8326A0";
ram_buffer(1575) := X"3C031000";
ram_buffer(1576) := X"248226A0";
ram_buffer(1577) := X"24631758";
ram_buffer(1578) := X"AC430014";
ram_buffer(1579) := X"3C031000";
ram_buffer(1580) := X"246317E4";
ram_buffer(1581) := X"AC430004";
ram_buffer(1582) := X"3C031000";
ram_buffer(1583) := X"246317A0";
ram_buffer(1584) := X"AC40001C";
ram_buffer(1585) := X"AC400024";
ram_buffer(1586) := X"AC40002C";
ram_buffer(1587) := X"AC400034";
ram_buffer(1588) := X"AC40003C";
ram_buffer(1589) := X"AC400018";
ram_buffer(1590) := X"AC400008";
ram_buffer(1591) := X"AC43000C";
ram_buffer(1592) := X"AC400010";
ram_buffer(1593) := X"3C06F000";
ram_buffer(1594) := X"8CC30004";
ram_buffer(1595) := X"3C051000";
ram_buffer(1596) := X"00031100";
ram_buffer(1597) := X"00431021";
ram_buffer(1598) := X"00021080";
ram_buffer(1599) := X"3C031000";
ram_buffer(1600) := X"24631D68";
ram_buffer(1601) := X"24420004";
ram_buffer(1602) := X"00621021";
ram_buffer(1603) := X"24A516DC";
ram_buffer(1604) := X"AC450038";
ram_buffer(1605) := X"AC40003C";
ram_buffer(1606) := X"8CC50004";
ram_buffer(1607) := X"00000000";
ram_buffer(1608) := X"00051100";
ram_buffer(1609) := X"00451021";
ram_buffer(1610) := X"00021080";
ram_buffer(1611) := X"00431021";
ram_buffer(1612) := X"8C420000";
ram_buffer(1613) := X"24030081";
ram_buffer(1614) := X"AC430000";
ram_buffer(1615) := X"8C8226A0";
ram_buffer(1616) := X"24030007";
ram_buffer(1617) := X"AC430000";
ram_buffer(1618) := X"8F828024";
ram_buffer(1619) := X"24030003";
ram_buffer(1620) := X"0C000049";
ram_buffer(1621) := X"AC430000";
ram_buffer(1622) := X"8FBF0014";
ram_buffer(1623) := X"24040001";
ram_buffer(1624) := X"08000046";
ram_buffer(1625) := X"27BD0018";
ram_buffer(1626) := X"3C02F000";
ram_buffer(1627) := X"8C430004";
ram_buffer(1628) := X"00000000";
ram_buffer(1629) := X"00031100";
ram_buffer(1630) := X"00431021";
ram_buffer(1631) := X"3C031000";
ram_buffer(1632) := X"24631D68";
ram_buffer(1633) := X"00021080";
ram_buffer(1634) := X"00431021";
ram_buffer(1635) := X"8C430000";
ram_buffer(1636) := X"24040001";
ram_buffer(1637) := X"8C620000";
ram_buffer(1638) := X"00000000";
ram_buffer(1639) := X"34420001";
ram_buffer(1640) := X"08000046";
ram_buffer(1641) := X"AC620000";
ram_buffer(1642) := X"8F83802C";
ram_buffer(1643) := X"00000000";
ram_buffer(1644) := X"8C620000";
ram_buffer(1645) := X"00000000";
ram_buffer(1646) := X"30420002";
ram_buffer(1647) := X"1040FFFC";
ram_buffer(1648) := X"00000000";
ram_buffer(1649) := X"AC640008";
ram_buffer(1650) := X"03E00008";
ram_buffer(1651) := X"00000000";
ram_buffer(1652) := X"10000003";
ram_buffer(1653) := X"00000000";
ram_buffer(1654) := X"40836000";
ram_buffer(1655) := X"00000000";
ram_buffer(1656) := X"40036000";
ram_buffer(1657) := X"40806000";
ram_buffer(1658) := X"8F84801C";
ram_buffer(1659) := X"8F828018";
ram_buffer(1660) := X"00000000";
ram_buffer(1661) := X"1082FFF8";
ram_buffer(1662) := X"00000000";
ram_buffer(1663) := X"8F828018";
ram_buffer(1664) := X"3C041000";
ram_buffer(1665) := X"248424A0";
ram_buffer(1666) := X"00441021";
ram_buffer(1667) := X"90420000";
ram_buffer(1668) := X"8F848018";
ram_buffer(1669) := X"304200FF";
ram_buffer(1670) := X"24840001";
ram_buffer(1671) := X"308401FF";
ram_buffer(1672) := X"AF848018";
ram_buffer(1673) := X"40836000";
ram_buffer(1674) := X"03E00008";
ram_buffer(1675) := X"00000000";
ram_buffer(1676) := X"24050004";
ram_buffer(1677) := X"8F83802C";
ram_buffer(1678) := X"308600FF";
ram_buffer(1679) := X"8C620000";
ram_buffer(1680) := X"00000000";
ram_buffer(1681) := X"30420002";
ram_buffer(1682) := X"1040FFFC";
ram_buffer(1683) := X"00000000";
ram_buffer(1684) := X"24A5FFFF";
ram_buffer(1685) := X"AC660008";
ram_buffer(1686) := X"14A0FFF6";
ram_buffer(1687) := X"00042202";
ram_buffer(1688) := X"03E00008";
ram_buffer(1689) := X"00000000";
ram_buffer(1690) := X"3C071000";
ram_buffer(1691) := X"00003025";
ram_buffer(1692) := X"00001025";
ram_buffer(1693) := X"24E724A0";
ram_buffer(1694) := X"24080020";
ram_buffer(1695) := X"40036000";
ram_buffer(1696) := X"40806000";
ram_buffer(1697) := X"8F85801C";
ram_buffer(1698) := X"8F848018";
ram_buffer(1699) := X"00000000";
ram_buffer(1700) := X"14A4000A";
ram_buffer(1701) := X"00000000";
ram_buffer(1702) := X"40836000";
ram_buffer(1703) := X"00000000";
ram_buffer(1704) := X"40036000";
ram_buffer(1705) := X"40806000";
ram_buffer(1706) := X"8F85801C";
ram_buffer(1707) := X"8F848018";
ram_buffer(1708) := X"00000000";
ram_buffer(1709) := X"10A4FFF8";
ram_buffer(1710) := X"00000000";
ram_buffer(1711) := X"8F848018";
ram_buffer(1712) := X"00000000";
ram_buffer(1713) := X"00E42021";
ram_buffer(1714) := X"90840000";
ram_buffer(1715) := X"8F858018";
ram_buffer(1716) := X"308400FF";
ram_buffer(1717) := X"24A50001";
ram_buffer(1718) := X"30A501FF";
ram_buffer(1719) := X"AF858018";
ram_buffer(1720) := X"40836000";
ram_buffer(1721) := X"00C41804";
ram_buffer(1722) := X"24C60008";
ram_buffer(1723) := X"14C8FFE3";
ram_buffer(1724) := X"00431025";
ram_buffer(1725) := X"03E00008";
ram_buffer(1726) := X"00000000";
ram_buffer(1727) := X"8F828028";
ram_buffer(1728) := X"00000000";
ram_buffer(1729) := X"03E00008";
ram_buffer(1730) := X"AC440008";
ram_buffer(1731) := X"8F828028";
ram_buffer(1732) := X"00000000";
ram_buffer(1733) := X"8C420008";
ram_buffer(1734) := X"03E00008";
ram_buffer(1735) := X"00000000";
ram_buffer(1736) := X"8F828028";
ram_buffer(1737) := X"00000000";
ram_buffer(1738) := X"8C420004";
ram_buffer(1739) := X"03E00008";
ram_buffer(1740) := X"00000000";
ram_buffer(1741) := X"3C03F000";
ram_buffer(1742) := X"8C620004";
ram_buffer(1743) := X"00000000";
ram_buffer(1744) := X"24420001";
ram_buffer(1745) := X"8F848030";
ram_buffer(1746) := X"00000000";
ram_buffer(1747) := X"AC820000";
ram_buffer(1748) := X"8C620004";
ram_buffer(1749) := X"8F848030";
ram_buffer(1750) := X"24420001";
ram_buffer(1751) := X"8C840000";
ram_buffer(1752) := X"00000000";
ram_buffer(1753) := X"1444FFF4";
ram_buffer(1754) := X"00000000";
ram_buffer(1755) := X"08000190";
ram_buffer(1756) := X"00000000";
ram_buffer(1757) := X"27BDFFE8";
ram_buffer(1758) := X"AFBF0014";
ram_buffer(1759) := X"0C000190";
ram_buffer(1760) := X"00000000";
ram_buffer(1761) := X"3C02F000";
ram_buffer(1762) := X"8C420004";
ram_buffer(1763) := X"00000000";
ram_buffer(1764) := X"24420001";
ram_buffer(1765) := X"8FBF0014";
ram_buffer(1766) := X"8F838030";
ram_buffer(1767) := X"00000000";
ram_buffer(1768) := X"AC620000";
ram_buffer(1769) := X"03E00008";
ram_buffer(1770) := X"27BD0018";
ram_buffer(1771) := X"27BDFFE8";
ram_buffer(1772) := X"AFB00010";
ram_buffer(1773) := X"AFBF0014";
ram_buffer(1774) := X"00808025";
ram_buffer(1775) := X"0C000190";
ram_buffer(1776) := X"00000000";
ram_buffer(1777) := X"8F828014";
ram_buffer(1778) := X"00000000";
ram_buffer(1779) := X"1602FFFB";
ram_buffer(1780) := X"00000000";
ram_buffer(1781) := X"8FBF0014";
ram_buffer(1782) := X"8FB00010";
ram_buffer(1783) := X"03E00008";
ram_buffer(1784) := X"27BD0018";
ram_buffer(1785) := X"27BDFFE8";
ram_buffer(1786) := X"AFBF0014";
ram_buffer(1787) := X"0C000190";
ram_buffer(1788) := X"00000000";
ram_buffer(1789) := X"8FBF0014";
ram_buffer(1790) := X"8F828014";
ram_buffer(1791) := X"03E00008";
ram_buffer(1792) := X"27BD0018";
ram_buffer(1793) := X"AF848008";
ram_buffer(1794) := X"03E00008";
ram_buffer(1795) := X"00000000";
ram_buffer(1796) := X"AF848004";
ram_buffer(1797) := X"03E00008";
ram_buffer(1798) := X"00000000";
ram_buffer(1799) := X"28CA0008";
ram_buffer(1800) := X"1540003E";
ram_buffer(1801) := X"00801025";
ram_buffer(1802) := X"10A00007";
ram_buffer(1803) := X"00043823";
ram_buffer(1804) := X"00000000";
ram_buffer(1805) := X"30A500FF";
ram_buffer(1806) := X"00055200";
ram_buffer(1807) := X"00AA2825";
ram_buffer(1808) := X"00055400";
ram_buffer(1809) := X"00AA2825";
ram_buffer(1810) := X"30EA0003";
ram_buffer(1811) := X"11400003";
ram_buffer(1812) := X"00CA3023";
ram_buffer(1813) := X"A8850000";
ram_buffer(1814) := X"008A2021";
ram_buffer(1815) := X"30EA0004";
ram_buffer(1816) := X"11400003";
ram_buffer(1817) := X"00CA3023";
ram_buffer(1818) := X"AC850000";
ram_buffer(1819) := X"008A2021";
ram_buffer(1820) := X"30D8003F";
ram_buffer(1821) := X"10D80016";
ram_buffer(1822) := X"00D83823";
ram_buffer(1823) := X"00873821";
ram_buffer(1824) := X"AC850000";
ram_buffer(1825) := X"AC850004";
ram_buffer(1826) := X"AC850008";
ram_buffer(1827) := X"AC85000C";
ram_buffer(1828) := X"AC850010";
ram_buffer(1829) := X"AC850014";
ram_buffer(1830) := X"AC850018";
ram_buffer(1831) := X"AC85001C";
ram_buffer(1832) := X"AC850020";
ram_buffer(1833) := X"AC850024";
ram_buffer(1834) := X"AC850028";
ram_buffer(1835) := X"AC85002C";
ram_buffer(1836) := X"AC850030";
ram_buffer(1837) := X"AC850034";
ram_buffer(1838) := X"AC850038";
ram_buffer(1839) := X"AC85003C";
ram_buffer(1840) := X"24840040";
ram_buffer(1841) := X"1487FFEE";
ram_buffer(1842) := X"00000000";
ram_buffer(1843) := X"03003025";
ram_buffer(1844) := X"30D8001F";
ram_buffer(1845) := X"10D8000A";
ram_buffer(1846) := X"00000000";
ram_buffer(1847) := X"AC850000";
ram_buffer(1848) := X"AC850004";
ram_buffer(1849) := X"AC850008";
ram_buffer(1850) := X"AC85000C";
ram_buffer(1851) := X"AC850010";
ram_buffer(1852) := X"AC850014";
ram_buffer(1853) := X"AC850018";
ram_buffer(1854) := X"AC85001C";
ram_buffer(1855) := X"24840020";
ram_buffer(1856) := X"33060003";
ram_buffer(1857) := X"10D80005";
ram_buffer(1858) := X"03063823";
ram_buffer(1859) := X"00873821";
ram_buffer(1860) := X"24840004";
ram_buffer(1861) := X"1487FFFE";
ram_buffer(1862) := X"AC85FFFC";
ram_buffer(1863) := X"18C00004";
ram_buffer(1864) := X"00863821";
ram_buffer(1865) := X"24840001";
ram_buffer(1866) := X"1487FFFE";
ram_buffer(1867) := X"A085FFFF";
ram_buffer(1868) := X"03E00008";
ram_buffer(1869) := X"00000000";
ram_buffer(1870) := X"00000100";
ram_buffer(1871) := X"01010001";
ram_buffer(1872) := X"00000000";
ram_buffer(1873) := X"00000000";
ram_buffer(1874) := X"00000000";
ram_buffer(1875) := X"00000000";
ram_buffer(1876) := X"FFFFFFFF";
ram_buffer(1877) := X"FFFFFFFF";
ram_buffer(1878) := X"FFFFFFFF";
ram_buffer(1879) := X"FFFFFFFF";
ram_buffer(1880) := X"FFFFFFFF";
ram_buffer(1881) := X"FFFFFFFF";
ram_buffer(1882) := X"FFFFFFFF";
ram_buffer(1883) := X"00000000";
ram_buffer(1884) := X"00000000";
ram_buffer(1885) := X"00000000";
ram_buffer(1886) := X"00000000";
ram_buffer(1887) := X"00000000";
ram_buffer(1888) := X"00000000";
ram_buffer(1889) := X"00000000";
ram_buffer(1890) := X"00000000";
ram_buffer(1891) := X"00000000";
ram_buffer(1892) := X"00000000";
ram_buffer(1893) := X"00000000";
ram_buffer(1894) := X"00000000";
ram_buffer(1895) := X"00000000";
ram_buffer(1896) := X"00000000";
ram_buffer(1897) := X"00000000";
ram_buffer(1898) := X"00000000";
ram_buffer(1899) := X"FFFFFFFF";
ram_buffer(1900) := X"00000000";
ram_buffer(1901) := X"00000000";
ram_buffer(1902) := X"00000000";
ram_buffer(1903) := X"00000000";
ram_buffer(1904) := X"00000000";
ram_buffer(1905) := X"00000000";
ram_buffer(1906) := X"00000000";
ram_buffer(1907) := X"00000000";
ram_buffer(1908) := X"00000000";
ram_buffer(1909) := X"00000000";
ram_buffer(1910) := X"00000000";
ram_buffer(1911) := X"00000000";
ram_buffer(1912) := X"00000000";
ram_buffer(1913) := X"00000000";
ram_buffer(1914) := X"00000000";
ram_buffer(1915) := X"00000000";
ram_buffer(1916) := X"FFFFFFFF";
ram_buffer(1917) := X"00000000";
ram_buffer(1918) := X"00000000";
ram_buffer(1919) := X"00000000";
ram_buffer(1920) := X"00000000";
ram_buffer(1921) := X"00000000";
ram_buffer(1922) := X"00000000";
ram_buffer(1923) := X"00000000";
ram_buffer(1924) := X"00000000";
ram_buffer(1925) := X"00000000";
ram_buffer(1926) := X"00000000";
ram_buffer(1927) := X"00000000";
ram_buffer(1928) := X"00000000";
ram_buffer(1929) := X"00000000";
ram_buffer(1930) := X"00000000";
ram_buffer(1931) := X"00000000";
ram_buffer(1932) := X"00000000";
ram_buffer(1933) := X"100016D4";
ram_buffer(1934) := X"100016D4";
return ram_buffer;
end;
end;
|
mit
|
0897d0783883fa3e6a8ad33f693d5d9b
| 0.623038 | 2.381661 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/PulseGenerator.vhd
| 1 | 4,486 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Provides a pulse generator controlled by values specifying the number of
-- clock cycles to hold the signal in high or low state.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PulseGenerator is
generic
(
-- The width of the internal clock cycle counter.
counter_width: natural := 32
);
port
(
-- The system clock.
clk: in std_logic;
-- The duration of the pulse´s high or low phase in clock cycles.
high_duration, low_duration: in unsigned(counter_width-1 downto 0);
-- The generated signal.
pulse_signal: out std_logic
);
end entity;
architecture stdarch of PulseGenerator is
signal reg_high_duration, reg_low_duration: unsigned(counter_width-1 downto 0)
:= (others => '0');
type reg_type is record
phase: std_logic;
counter: unsigned(counter_width-1 downto 0);
old_high_duration, old_low_duration: unsigned(counter_width-1 downto 0);
end record;
signal state, next_state: reg_type :=
(
phase => '0',
counter => (others => '0'),
old_high_duration => (others => '0'),
old_low_duration => (others => '0')
);
begin
-- Adds one clock cycle latency for all input signals to satisfy the timing
-- constraints.
register_inputs: process is
begin
wait until rising_edge(clk);
reg_high_duration <= high_duration;
reg_low_duration <= low_duration;
end process;
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, reg_low_duration, reg_high_duration) is
begin
-- Defaults.
next_state <= state;
if state.counter = (counter_width-1 downto 0 => '0') then
if state.phase = '1' then
next_state.counter <= reg_low_duration - 1;
else
next_state.counter <= reg_high_duration - 1;
end if;
next_state.phase <= not state.phase;
else
if (reg_low_duration /= state.old_low_duration or
reg_high_duration /= state.old_high_duration) then
-- The duration vales have been changed, reset the counter for immediate
-- response (otherwise a delay up to a complete counter cycle might occur).
next_state.counter <= (next_state.counter'range => '0');
else
next_state.counter <= state.counter - 1;
end if;
end if;
next_state.old_low_duration <= reg_low_duration;
next_state.old_high_duration <= reg_high_duration;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
pulse_signal <= state.phase;
end architecture;
|
gpl-3.0
|
c9804ce287728189934322fd28342813
| 0.491083 | 5.046119 | false | false | false | false |
rinatzakirov/vhdl
|
stream_to_avalon.vhd
| 1 | 8,901 |
use work.all;
use work.util.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity stream_to_avalon is
generic
(
STREAM_BW: integer := 32
);
port
(
stream_clk : in std_logic ;
stream_rst : in std_logic ;
stream_valid : in std_logic ;
stream_ready : out std_logic ;
stream_data : in std_logic_vector(STREAM_BW - 1 downto 0);
clk: in std_logic;
rst: in std_logic;
ctl_write : in std_logic ;
ctl_read : in std_logic ;
ctl_address : in std_logic_vector(3 downto 0) ;
ctl_writedata : in std_logic_vector(31 downto 0) ;
ctl_readdata : out std_logic_vector(31 downto 0) ;
ctl_waitrequest : out std_logic ;
ctl_readdatavalid : out std_logic ;
writer_write : out std_logic ;
writer_waitrequest : in std_logic ;
writer_address : out std_logic_vector(31 downto 0) ;
writer_burstcount : out std_logic_vector(9 downto 0) ;
writer_writedata : out std_logic_vector(127 downto 0)
);
end entity;
architecture syn of stream_to_avalon is
constant write_little_endian: boolean := true;
constant burst_size: integer := 256;
constant avalon_bw: integer := writer_writedata'length;
signal stream_wideData, out_data: std_ulogic_vector(avalon_bw - 1 downto 0);
signal stream_was_full, stream_we, reset_stream_was_full, stream_start, writer_valid, writer_ready, ws_stream_start, stream_start_r, ws_stream_stop, stream_stop_r, stream_stop, writer_fifo_rst,
stream_ready_i, writer_write_i, ws_almost_empty, zero_fill, fifo_empty, keep_going, ws_stream_was_full, ws_stream_was_full_r,
writer_enough_data, writer_start, writer_busy, ws_stream_busy, ws_stream_busy_r, stream_busy, burst_active, ws_fifo_reset, rs_fifo_reset_r, rs_fifo_reset, stream_fifo_rst: std_ulogic;
signal writer_burstWritten: integer range 0 to burst_size - 1;
signal sample_count: integer range 0 to (avalon_bw / stream_bw) - 1;
signal writer_nextAddress, writer_startAddress, writer_totalWords, writer_wordsToGo: unsigned(31 downto 0);
begin
stream_fifo_rst <= stream_rst or rs_fifo_reset;
writer_fifo_rst <= rst or rs_fifo_reset;
writer_enough_data <= '0' when ws_almost_empty = '1' or fifo_empty = '1' else '1';
stream_ready <= stream_ready_i;
writer_writedata <= toSlv(out_data) when zero_fill = '0' else (others => '0');
fifo_inst: entity work.TwoClockStreamFifo
generic map
(
MEM_SIZE => burst_size * 2
)
port map
(
in_clk => stream_clk ,
in_rst => stream_fifo_rst ,
in_data => stream_wideData ,
in_valid => stream_we ,
in_ready => stream_ready_i ,
out_clk => clk ,
out_rst => writer_fifo_rst ,
out_data => out_data ,
out_valid => writer_valid ,
out_ready => writer_ready ,
almost_empty_thresh => burst_size,
almost_empty => ws_almost_empty,
empty => fifo_empty
);
process (stream_clk)
begin
if rising_edge(stream_clk) then
if stream_rst = '1' then
stream_wideData <= (others => '0');
sample_count <= 0;
stream_we <= '0';
stream_was_full <= '0';
else
rs_fifo_reset_r <= ws_fifo_reset;
rs_fifo_reset <= rs_fifo_reset_r;
stream_start_r <= ws_stream_start;
stream_start <= stream_start_r;
stream_stop_r <= ws_stream_stop;
stream_stop <= stream_stop_r;
if reset_stream_was_full = '1' then
stream_was_full <= '0';
end if;
if stream_ready_i = '0' then
stream_was_full <= '1';
end if;
if stream_busy = '0' then
if stream_start = '1' then
stream_busy <= '1';
end if;
--
sample_count <= 0;
stream_we <= '0';
else
if stream_stop = '1' then
stream_busy <= '0';
end if;
--
if stream_ready_i = '1' then
stream_we <= '0';
end if;
if stream_valid = '1' and stream_ready_i = '1' then
if write_little_endian then
stream_wideData <= toSuv(stream_data) & stream_wideData(avalon_bw - 1 downto stream_bw);
else
stream_wideData <= stream_wideData(avalon_bw - 1 - stream_bw downto 0) & toSuv(stream_data);
end if;
if sample_count = (avalon_bw / stream_bw) - 1 then
sample_count <= 0;
stream_we <= '1';
else
sample_count <= sample_count + 1;
end if;
end if;
end if;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
ctl_waitrequest <= '0';
ctl_readdatavalid <= '0';
writer_start <= '0';
writer_totalWords <= toUns(0, writer_totalWords);
writer_startAddress <= toUns(0, writer_startAddress);
ws_stream_start <= '0';
ws_stream_stop <= '0';
ws_fifo_reset <= '0';
zero_fill <= '0';
keep_going <= '0';
else
ws_stream_was_full_r <= stream_was_full;
ws_stream_was_full <= ws_stream_was_full_r;
if keep_going = '0' then
writer_start <= '0';
end if;
if ctl_write = '1' then
case ctl_address is
when "0000" =>
writer_start <= ctl_writedata(0);
ws_stream_start <= ctl_writedata(1);
ws_stream_stop <= ctl_writedata(2);
ws_fifo_reset <= ctl_writedata(3);
reset_stream_was_full <= ctl_writedata(4);
zero_fill <= ctl_writedata(5);
keep_going <= ctl_writedata(6);
when "0001" =>
writer_startAddress <= unsigned(ctl_writedata);
when "0010" =>
writer_totalWords <= unsigned(ctl_writedata);
when others =>
end case;
end if;
ctl_readdatavalid <= ctl_read;
if ctl_read = '1' then
case ctl_address is
when "0000" =>
ctl_readdata <= (others => '0');
ctl_readdata(0) <= writer_busy;
ctl_readdata(1) <= ws_stream_busy;
ctl_readdata(2) <= ws_stream_was_full;
when "0001" =>
ctl_readdata <= unsToSlv(writer_nextAddress);
when "0010" =>
ctl_readdata <= unsToSlv(writer_wordsToGo);
when others =>
end case;
end if;
end if;
end if;
end process;
writer_write <= writer_write_i;
writer_ready <= writer_write_i and not writer_waitrequest;
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
writer_write_i <= '0';
writer_burstcount <= (others => '0');
writer_busy <= '0';
burst_active <= '0';
else
ws_stream_busy_r <= stream_busy;
ws_stream_busy <= ws_stream_busy_r;
if writer_busy = '0' then
if writer_start = '1' then
writer_busy <= '1';
writer_nextAddress <= writer_startAddress;
writer_wordsToGo <= writer_totalWords;
burst_active <= '0';
end if;
else
if burst_active = '1' then
if writer_waitrequest = '0' then
writer_wordsToGo <= writer_wordsToGo - 1;
writer_nextAddress <= writer_nextAddress + avalon_bw / 8;
if writer_burstWritten = burst_size - 1 then
writer_write_i <= '0';
writer_burstcount <= (others => '0');
burst_active <= '0';
else
writer_burstWritten <= writer_burstWritten + 1;
end if;
end if;
else
if writer_wordsToGo < burst_size then
writer_busy <= '0';
else
if writer_enough_data = '1' or zero_fill = '1' then
burst_active <= '1';
writer_address <= unsToSlv(writer_nextAddress);
writer_burstWritten <= 0;
writer_burstcount <= toSlv(burst_size, writer_burstcount'length);
writer_write_i <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
end process;
end architecture;
|
lgpl-2.1
|
761d04401f4fa42577dc4cf4a07bd421
| 0.507583 | 3.794118 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/audioDac/ipcore_dir/rom_memory/example_design/rom_memory_exdes.vhd
| 1 | 4,344 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rom_memory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rom_memory_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END rom_memory_exdes;
ARCHITECTURE xilinx OF rom_memory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT rom_memory IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : rom_memory
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
16f36efa145bdc0612e6126844e1222f
| 0.575506 | 4.810631 | false | false | false | false |
arthurTemporim/SD_SS
|
rel/5/projetos/projeto1/projeto1.vhd
| 1 | 503 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto1 is
port (
e : in std_logic_vector (1 downto 0) := "00";
c : in std_logic := '0';
s : out std_logic
);
end projeto1;
architecture Behavioral of projeto1 is
signal multiplex : std_logic;
begin
process (multiplex, e, c)
begin
if(e = "00") then
multiplex <= '0';
elsif (e = "01") then
multiplex <= '1';
elsif (e = "10") then
multiplex <= '0';
else
multiplex <= c;
end if;
end process;
s <= multiplex;
end Behavioral;
|
mit
|
f7fa0f8e4e488df492855a73d340105e
| 0.626243 | 2.68984 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/koc/koc_lock_axi4_read_cntrl.vhd
| 1 | 3,160 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_gpio_pack.all;
entity koc_lock_axi4_read_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000"
);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
reg_control : in std_logic_vector(axi_data_width-1 downto 0)
);
end koc_lock_axi4_read_cntrl;
architecture Behavioral of koc_lock_axi4_read_cntrl is
type state_type is (state_wait,state_read);
signal state : state_type := state_wait;
signal axi_arready_buff : std_logic := '0';
signal axi_rvalid_buff : std_logic := '0';
signal axi_araddr_buff : std_logic_vector(axi_address_width-1 downto 0);
begin
axi_arready <= axi_arready_buff;
axi_rvalid <= axi_rvalid_buff;
axi_rresp <= axi_resp_okay;
process (aclk)
begin
if rising_edge(aclk) then
if aresetn='0' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '0';
state <= state_wait;
else
case state is
when state_wait=>
if axi_arvalid='1' and axi_arready_buff='1' then
axi_arready_buff <= '0';
axi_rvalid_buff <= '1';
state <= state_read;
if axi_araddr=reg_control_offset then
axi_rdata <= reg_control;
else
axi_rdata <= (others=>'0');
end if;
else
axi_arready_buff <= '1';
end if;
when state_read=>
if axi_rvalid_buff='1' and axi_rready='1' then
axi_rvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
cfb9be0e0cbf521315b52aa6dd7b06e8
| 0.45443 | 4.41958 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/serial_out/tb_rx.vhd
| 1 | 5,156 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:34:16 02/23/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/FPGA_temp/serial_out/tb_rx.vhd
-- Project Name: serial_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: uart_rx
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_rx IS
END tb_rx;
ARCHITECTURE behavior OF tb_rx IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT uart_rx
PORT(
clk : IN std_logic;
rx : IN std_logic;
rx_data : OUT std_logic_vector(7 downto 0);
rx_ready : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rx : std_logic := '1';
--Outputs
signal rx_data : std_logic_vector(7 downto 0);
signal rx_ready : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
constant bit_period : time := 8.68 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: uart_rx PORT MAP (
clk => clk,
rx => rx,
rx_data => rx_data,
rx_ready => rx_ready
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait for 10 us;
-- send '0000000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11111111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11110000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '00001111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '10101010'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 200 us;
end process;
END;
|
gpl-3.0
|
5879477a6bcea07f178790f1c993b9f1
| 0.552172 | 2.954728 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/PhaseGenerator.vhd
| 1 | 3,230 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Provides a phase generator controlled by a phase accumulator. It is
-- recommended to use increments only up to the half of the accumulator´s
-- capacity (MSB=1, all others 0). This ensures a duty cycle of 50% in the MSB
-- of the phase when it is used as a frequency signal. The current phase might
-- be used for DDS signal generation.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PhaseGenerator is
generic
(
-- The width of the phase values.
phase_width: natural := 32
);
port
(
-- The system clock.
clk: in std_logic;
-- The increment to be added to the phase accumulator in each clock cycle.
phase_increment: in unsigned (phase_width-1 downto 0);
-- A signal used to reset the generator´s phase.
reset_phase: in std_logic;
-- The current phase value.
phase: out unsigned (phase_width-1 downto 0) := (others => '0')
);
end entity;
architecture stdarch of PhaseGenerator is
type reg_type is record
phase_accumulator: unsigned (phase_width-1 downto 0);
end record;
signal state, next_state: reg_type := (phase_accumulator => (others => '0'));
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state.phase_accumulator <=
(next_state.phase_accumulator'range => '0') when reset_phase = '1'
else state.phase_accumulator + phase_increment;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
phase <= state.phase_accumulator;
end architecture;
|
gpl-3.0
|
1c7263d61fd11610c01acc0776c02bf5
| 0.486687 | 5.401338 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/Common/Source/Counter.vhd
| 1 | 2,880 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Provides a simple counter with a synchronous clear.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity Counter is
generic
(
width: natural
);
port
(
-- The system clock.
clk: in std_logic;
-- The synchronous clear.
clear: in std_logic;
-- The counter enable.
ce: in std_logic;
-- The counter´s value.
value: out unsigned (width-1 downto 0)
);
end entity;
architecture stdarch of Counter is
type reg_type is record
value: unsigned (width-1 downto 0);
end record;
signal state, next_state: reg_type := (value => (others => '0'));
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, ce, clear) is
begin
-- Defaults.
next_state <= state;
-- Clear or increment.
if (clear = '1') then
next_state <= (value => (others => '0'));
elsif (ce = '1') then
next_state.value <= state.value + 1;
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
value <= state.value;
end architecture;
|
gpl-3.0
|
478c812019ebf3e5008055b534d5ad22
| 0.422917 | 5.549133 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/flashyLights/ipcore_dir/memmory/simulation/bmg_stim_gen.vhd
| 1 | 12,570 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= hex_to_std_logic_vector("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (1023 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"memmory.mif",
DEFAULT_DATA,
8,
1024);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
gpl-3.0
|
946c3e928a86f02819a49e08e72af8c2
| 0.547414 | 3.685136 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/CounterClockDivider.vhd
| 1 | 5,707 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generates the universal counter´s internal pulse or gate signal by dividing
-- the system clock.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library Common;
use work.Globals.all;
entity CounterClockDivider is
generic
(
-- The width of the internal clock divider.
clock_divider_width: integer := 32;
-- '0' for normal operation, '1' to ignore the real system clock
-- frequency when dividing the clock frequency.
clock_divider_test_mode: boolean := false
);
port
(
-- The system clock.
clk: in std_logic;
-- A value indicating the clock division mode.
clk_division_mode: in std_logic_vector (3 downto 0);
-- Gets active for one clock cycle every time the clock division value
-- has been reached.
divider_tick: out std_logic
);
end entity;
architecture stdarch of CounterClockDivider is
constant clock_frequency: natural := 50 * 10**6;
-- Clock divider.
type reg_type is record
division_counter: unsigned (clock_divider_width-1 downto 0);
divider_tick: std_logic;
end record;
signal state, next_state: reg_type :=
(
division_counter => (others => '0'),
divider_tick => '0'
);
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, clk_division_mode) is
variable clock_divider: unsigned (clock_divider_width-1 downto 0);
begin
-- Defaults.
next_state <= state;
next_state.divider_tick <= '0';
-- Select the clock division value.
if (clock_divider_test_mode) then
-- Special value for test purposes, don't divide by real system clock frequency.
clock_divider := to_unsigned(10, clock_divider_width);
else
case clk_division_mode is
-- Frequency measurement.
when "0000" => -- 1 s gate signal
clock_divider := to_unsigned(1 * clock_frequency, clock_divider_width);
when "0001" => -- 0.1 s gate signal
clock_divider := to_unsigned(10 * clock_frequency, clock_divider_width);
when "0010" => -- 10 s gate signal
clock_divider := to_unsigned(clock_frequency / 10, clock_divider_width);
-- Period measurement.
when "0100" => -- 10 MHz pulse signal
clock_divider := to_unsigned(clock_frequency/10**7, clock_divider_width);
when "0101" => -- 1 MHz pulse signal
clock_divider := to_unsigned(clock_frequency/10**6, clock_divider_width);
when "0110" => -- 100 kHz pulse signal
clock_divider := to_unsigned(clock_frequency/10**5, clock_divider_width);
when "0111" => -- 10 kHz pulse signal
clock_divider := to_unsigned(clock_frequency/10**4, clock_divider_width);
when others =>
clock_divider := to_unsigned(1 * clock_frequency, clock_divider_width);
end case;
end if;
-- Check the clock division counter and, if it has reached the division value, raise
-- the divider tick signal for one clock cycle. Ensure that the clock division counter
-- is reset if it reaches or exceeds the division value (exceeding might happen after
-- changing the division value).
if (state.division_counter >= clock_divider-1) then
next_state.division_counter <= (others => '0');
if (state.division_counter = clock_divider-1) then
next_state.divider_tick <= '1';
end if;
else
next_state.division_counter <= state.division_counter + 1;
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
divider_tick <= state.divider_tick;
end architecture;
|
gpl-3.0
|
9d27e2e07e298ce183290137b7842159
| 0.507973 | 5.086453 | false | false | false | false |
Daverball/reconos
|
pcores/reconos_proc_control_v1_00_a/hdl/vhdl/reconos_proc_control.vhd
| 2 | 11,364 |
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - PROC_CONTROL - Proc control implementation
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The Proc Conrol is used to control the different
-- hardware parts through a single interface. It allows
-- to reset the HWTs seperately and asynchronously and
-- configures the MMU. To provide its functionality it
-- has several registers.
-- Register Definition (as seen from Bus):
-- Reg0: Number of HWT-Slots (OSIFS) - Read only
-- # all MMU related stuff
-- Reg1: PGD address - Read / Write
-- Reg2: Page fault address (only valid on interrupt)
-- read to clear interrupt, write after handling
-- Reg3: TLB hits - Read only
-- Reg4: TLB misses - Read only
-- # resets
-- Reg5: ReconOS reset (reset everything) - Write only
-- Reg6: HWT reset (multiple registers) - Write only
-- | x , x-1, ... | x-32 , x-33, ... 0 |
--
-- Page fault handling works the following:
-- 1.) MMU raises MMU_Pgf
-- 2.) Proc control raises PROC_Pgf_Int
-- 3.) CPU clears interrupt by reading register 2
-- 4.) CPU handles page fault and acknowledges this
-- by writing to register 2
-- 5.) Proc control informs MMU by raising MMU_Ready
-- that the page fault has been handled
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library reconos_proc_control_v1_00_a;
use reconos_proc_control_v1_00_a.user_logic;
entity reconos_proc_control is
generic (
-- Proc Control paramters
C_NUM_HWTS : integer := 1;
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port (
-- Proc control ports
PROC_Clk : in std_logic;
PROC_Rst : in std_logic;
-- BEGIN GENERATE LOOP
PROC_Hwt_Rst_#i# : out std_logic;
-- END GENERATE LOOP
PROC_Sys_Rst : out std_logic;
PROC_Pgf_Int : out std_logic;
-- MMU related ports
MMU_Pgf : in std_logic;
MMU_Fault_Addr : in std_logic_vector(31 downto 0);
MMU_Retry : out std_logic;
MMU_Pgd : out std_logic_vector(31 downto 0);
MMU_Tlb_Hits : in std_logic_vector(31 downto 0);
MMU_Tlb_Misses : in std_logic_vector(31 downto 0);
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of PROC_Clk : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
attribute SIGIS of PROC_Rst : signal is "Rst";
-- BEGIN GENERATE LOOP
attribute SIGIS of PROC_Hwt_Rst_#i# : signal is "Rst";
-- END GENERATE LOOP
attribute SIGIS of PROC_Sys_Rst : signal is "Rst";
attribute SIGIS of PROC_Pgf_Int : signal is "Intr_Level_High";
end entity reconos_proc_control;
architecture implementation of reconos_proc_control is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := C_NUM_HWTS / C_SLV_DWIDTH + 7;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
-- Index for CS/CE
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
-- IP Interconnect (IPIC) signal declarations
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal hwt_rst : std_logic_vector(C_NUM_HWTS - 1 downto 0);
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : entity reconos_proc_control_v1_00_a.user_logic
generic map (
-- Proc Control parameters
C_NUM_HWTS => C_NUM_HWTS,
-- Bus protocol parameters
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map (
-- Proc Control ports
PROC_Clk => PROC_Clk,
PROC_Rst => not PROC_Rst,
PROC_Hwt_Rst => hwt_rst,
PROC_Sys_Rst => PROC_Sys_Rst,
PROC_Pgf_Int => PROC_Pgf_Int,
-- MMU related ports
MMU_Pgf => MMU_Pgf,
MMU_Fault_Addr => MMU_Fault_Addr,
MMU_Retry => MMU_Retry,
MMU_Pgd => MMU_Pgd,
MMU_Tlb_Hits => MMU_Tlb_Hits,
MMU_Tlb_Misses => MMU_Tlb_Misses,
-- Bus protocol ports
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
-- connect internal signals
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
-- BEGIN GENERATE LOOP
PROC_Hwt_Rst_#i# <= hwt_rst(#i#);
-- END GENERATE LOOP
end implementation;
|
gpl-2.0
|
d6fffbc38729a02ccef59e2b18d39d85
| 0.574584 | 2.983198 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/3/projetos/sumSub.vhd
| 1 | 3,690 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.ALL;
entity sumSub is
Port (
entrada1 : in std_logic_vector (2 downto 0) := "000";
entrada2 : in std_logic_vector (2 downto 0) := "000";
sel : in Std_logic;
saida : out std_logic_vector (2 downto 0);
cout : out std_logic;
E : out std_logic
);
end sumSub;
architecture Behavioral of sumSub is
signal cin0 : std_logic;
signal cin1 : std_logic;
signal cin2 : std_logic;
signal complemento1 : std_logic_vector (2 downto 0);
signal complemento2 : std_logic_vector (2 downto 0);
begin
process (entrada1, entrada2, sel)
begin
if (sel = '0') then
--saida <= entrada1 + entrada2;
if(entrada1(2) = '1') then
--inverte a
complemento1 <= entrada1 xor "111";
complemento2(0) <= entrada1(0) xor '1';
cin0 <= entrada1(0) and '1';
complemento2(1) <= entrada1(1) xor '1' xor cin0;
cin1 <= (entrada1(1) and cin0) or (entrada1(1) and '1') or ('1' and cin0);
complemento2(2) <= entrada1(2) xor '1' xor cin1;
cin2 <= (entrada1(1) and cin1) or (entrada1(1) and '1') or ('1' and cin1);
elsif (entrada2(2) = '1') then
--inverte b
complemento1 <= entrada2 xor "111";
complemento2(0) <= entrada2(0) xor '1';
cin0 <= entrada2(0) and '1';
complemento2(1) <= entrada2(1) xor '1' xor cin0;
cin1 <= (entrada2(1) and cin0) or (entrada2(1) and '1') or ('1' and cin0);
complemento2(2) <= entrada2(2) xor '1' xor cin1;
cin2 <= (entrada2(1) and cin1) or (entrada2(1) and '1') or ('1' and cin1);
end if;
saida(0) <= entrada1(0) xor entrada2(0);
cin0 <= entrada1(0) and entrada2(0);
saida(1) <= entrada1(1) xor entrada2(1) xor cin0;
cout <= (entrada1(1) and cin0) or (entrada1(1) and entrada2(1)) or (entrada2(1) and cin0);
saida(2) <= '0';
else
--saida <= entrada1 - entrada2;
if(entrada1(2) = '1') then
--inverte a
complemento1 <= entrada1 xor "111";
complemento2(0) <= entrada1(0) xor '1';
cin0 <= entrada1(0) and '1';
complemento2(1) <= entrada1(1) xor '1' xor cin0;
cin1 <= (entrada1(1) and cin0) or (entrada1(1) and '1') or ('1' and cin0);
complemento2(2) <= entrada1(2) xor '1' xor cin1;
cin2 <= (entrada1(1) and cin1) or (entrada1(1) and '1') or ('1' and cin1);
elsif (entrada2(2) = '1') then
--inverte b
complemento1 <= entrada2 xor "111";
complemento2(0) <= entrada2(0) xor '1';
cin0 <= entrada2(0) and '1';
complemento2(1) <= entrada2(1) xor '1' xor cin0;
cin1 <= (entrada2(1) and cin0) or (entrada2(1) and '1') or ('1' and cin0);
complemento2(2) <= entrada2(2) xor '1' xor cin1;
cin2 <= (entrada2(1) and cin1) or (entrada2(1) and '1') or ('1' and cin1);
end if;
-- Aplica o complemento no B
-----------------------------------------------------------------------------
complemento1 <= entrada2 xor "111";
complemento2(0) <= entrada2(0) xor '1';
cin0 <= entrada2(0) and '1';
complemento2(1) <= entrada2(1) xor '1' xor cin0;
cin1 <= (entrada2(1) and cin0) or (entrada2(1) and '1') or ('1' and cin0);
complemento2(2) <= entrada2(2) xor '1' xor cin1;
cin2 <= (entrada2(1) and cin1) or (entrada2(1) and '1') or ('1' and cin1);
-----------------------------------------------------------------------------
saida(0) <= entrada1(0) xor entrada2(0);
cin0 <= entrada1(0) and entrada2(0);
saida(1) <= entrada1(1) xor entrada2(1) xor cin0;
cout <= (entrada1(1) and cin0) or (entrada1(1) and entrada2(1)) or (entrada2(1) and cin0);
saida(2) <= '0';
end if;
end process;
end Behavioral;
|
mit
|
405d25e8a6b914847a7ddd02c2bd6ca8
| 0.562331 | 2.753731 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Testbenches/SPI_SlaveTransmitterSerializerTester.vhd
| 1 | 4,004 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the SPI slave transmitter serializer.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.TestTools.all;
entity SPI_SlaveTransmitterSerializer_Tester is
end entity;
architecture stdarch of SPI_SlaveTransmitterSerializer_Tester is
-- Constants
constant test_delay: time := 1ps;
constant data_width: positive := 32;
constant sclk_period: time := 91ns; -- about 11 MHz serial clock
constant test_value_0: std_logic_vector(data_width-1 downto 0) := x"12345678";
constant test_value_1: std_logic_vector(data_width-1 downto 0) := x"FEDCBA98";
-- Inputs
signal sclk: std_logic := '1';
signal ss: std_logic := '1';
signal data: std_logic_vector(data_width-1 downto 0) := (others => '0');
-- Outputs
signal miso: std_logic;
signal deserialized_data: std_logic_vector(data_width-1 downto 0) := (others => '0');
-- Internals
-------------------------------------------------------------------------
-- Passes a test value through the transmitter and deserialize it again.
-------------------------------------------------------------------------
procedure deserialize_data(test_value: std_logic_vector(data_width-1 downto 0))
is
begin
deserialized_data <= (deserialized_data'range => '0');
ss <= '0';
data <= test_value;
wait for test_delay;
deserialize_longword(sclk_period, miso, sclk, deserialized_data);
ss <= '1';
end procedure;
begin
--------------------------------------------------------------------------------
-- Instantiate the UUT(s).
--------------------------------------------------------------------------------
uut: entity work.SPI_SlaveTransmitterSerializer
generic map
(
width => data_width
)
port map
(
ss => ss,
sclk => sclk,
data => data,
miso => miso
);
--------------------------------------------------------------------------------
-- Stimulate the UUT.
--------------------------------------------------------------------------------
stimulus: process is
begin
-- Pass several values through the transmitter and check whether they arrive
-- at its output output.
wait for sclk_period; -- for a better readable timing diagram
deserialize_data(test_value_0);
assert (deserialized_data = test_value_0) report "Data not correctly transmitted." severity error;
wait for sclk_period; -- for a better readable timing diagram
deserialize_data(test_value_1);
assert (deserialized_data = test_value_1) report "Data not correctly transmitted." severity error;
wait for sclk_period; -- for a better readable timing diagram
wait;
end process;
end architecture;
|
gpl-3.0
|
401771280107ceabd34d27c2c3f550a4
| 0.504995 | 5.139923 | false | true | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
testbench/dvb_ts_filter_tb.vhd
| 1 | 2,238 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_ts_filter_tb is
end;
architecture sym of dvb_ts_filter_tb is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal addr : std_logic_vector(7 downto 0) := (others => '0');
signal be : std_logic_vector(3 downto 0) := (others => '1');
signal wrdata : std_logic_vector(31 downto 0) := (others => '0');
signal write : std_logic := '0';
signal rddata : std_logic_vector(31 downto 0);
signal read : std_logic := '0';
signal waitreq : std_logic;
signal src_dsop : std_logic;
signal src_data : std_logic_vector(7 downto 0);
signal src_dval : std_logic;
signal dvb_dsop : std_logic;
signal dvb_data : std_logic_vector(7 downto 0);
signal dvb_dval : std_logic;
begin
DVB_SRC_0 : entity work.dvb_source
generic map (
CLOCK_RATE_MHZ => 125,
INTERPACKET_GAP => 0,
INTEROCTET_GAP => 0
)
port map (
ts_clk => clk,
ts_strt => src_dsop,
ts_dval => src_dval,
ts_data => src_data
);
FILTER_0 : entity work.dvb_ts_filter
port map (
rst => rst,
clk => clk,
--
pid_tbl_addr => addr,
pid_tbl_be => be,
pid_tbl_wrdata => wrdata,
pid_tbl_write => write,
pid_tbl_rddata => rddata,
pid_tbl_read => read,
pid_tbl_waitreq => waitreq,
--
dvb_in_dsop => src_dsop,
dvb_in_data => src_data,
dvb_in_dval => src_dval,
--
dvb_out_dsop => dvb_dsop,
dvb_out_data => dvb_data,
dvb_out_dval => dvb_dval
);
process
begin
wait until rising_edge(clk);
rst <= '0';
--
wait until rising_edge(clk);
wait until rising_edge(clk);
addr <= std_logic_vector(to_unsigned(255, addr'length));
wrdata <= X"80000000";
write <= '1';
read <= '0';
wait until rising_edge(clk);
addr <= std_logic_vector(to_unsigned(0, addr'length));
write <= '0';
wait until rising_edge(clk);
addr <= std_logic_vector(to_unsigned(255, addr'length));
read <= '1';
wait until rising_edge(clk) and waitreq = '0';
read <= '0';
--
wait;
end process;
end;
|
gpl-3.0
|
7c4b252b28551afff48f5077e75c61a7
| 0.617516 | 2.578341 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_ts_0.vhd
| 1 | 8,154 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- dvb_ts_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dvb_ts_0 is
port (
address : in std_logic_vector(8 downto 0) := (others => '0'); -- avalon_slave_0.address
byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(31 downto 0); -- .readdata
read : in std_logic := '0'; -- .read
waitrequest : out std_logic; -- .waitrequest
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
interrupt : out std_logic; -- conduit_end.export
cam_bypass : in std_logic := '0'; -- .export
dvb_in0_dsop : in std_logic := '0'; -- .export
dvb_in0_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_in0_dval : in std_logic := '0'; -- .export
dvb_in1_dsop : in std_logic := '0'; -- .export
dvb_in1_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_in1_dval : in std_logic := '0'; -- .export
dvb_in2_dsop : in std_logic := '0'; -- .export
dvb_in2_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_in2_dval : in std_logic := '0'; -- .export
cam_baseclk : in std_logic := '0'; -- .export
cam_mclki : out std_logic; -- .export
cam_mdi : out std_logic_vector(7 downto 0); -- .export
cam_mival : out std_logic; -- .export
cam_mistrt : out std_logic; -- .export
cam_mclko : in std_logic := '0'; -- .export
cam_mdo : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
cam_mostrt : in std_logic := '0'; -- .export
cam_moval : in std_logic := '0'; -- .export
dvb_out_dsop : out std_logic; -- .export
dvb_out_dval : out std_logic; -- .export
dvb_out_data : out std_logic_vector(7 downto 0) -- .export
);
end entity dvb_ts_0;
architecture rtl of dvb_ts_0 is
component dvb_ts is
port (
address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
read : in std_logic := 'X'; -- read
waitrequest : out std_logic; -- waitrequest
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
interrupt : out std_logic; -- export
cam_bypass : in std_logic := 'X'; -- export
dvb_in0_dsop : in std_logic := 'X'; -- export
dvb_in0_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_in0_dval : in std_logic := 'X'; -- export
dvb_in1_dsop : in std_logic := 'X'; -- export
dvb_in1_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_in1_dval : in std_logic := 'X'; -- export
dvb_in2_dsop : in std_logic := 'X'; -- export
dvb_in2_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_in2_dval : in std_logic := 'X'; -- export
cam_baseclk : in std_logic := 'X'; -- export
cam_mclki : out std_logic; -- export
cam_mdi : out std_logic_vector(7 downto 0); -- export
cam_mival : out std_logic; -- export
cam_mistrt : out std_logic; -- export
cam_mclko : in std_logic := 'X'; -- export
cam_mdo : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
cam_mostrt : in std_logic := 'X'; -- export
cam_moval : in std_logic := 'X'; -- export
dvb_out_dsop : out std_logic; -- export
dvb_out_dval : out std_logic; -- export
dvb_out_data : out std_logic_vector(7 downto 0) -- export
);
end component dvb_ts;
begin
dvb_ts_0 : component dvb_ts
port map (
address => address, -- avalon_slave_0.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
read => read, -- .read
waitrequest => waitrequest, -- .waitrequest
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
interrupt => interrupt, -- conduit_end.export
cam_bypass => cam_bypass, -- .export
dvb_in0_dsop => dvb_in0_dsop, -- .export
dvb_in0_data => dvb_in0_data, -- .export
dvb_in0_dval => dvb_in0_dval, -- .export
dvb_in1_dsop => dvb_in1_dsop, -- .export
dvb_in1_data => dvb_in1_data, -- .export
dvb_in1_dval => dvb_in1_dval, -- .export
dvb_in2_dsop => dvb_in2_dsop, -- .export
dvb_in2_data => dvb_in2_data, -- .export
dvb_in2_dval => dvb_in2_dval, -- .export
cam_baseclk => cam_baseclk, -- .export
cam_mclki => cam_mclki, -- .export
cam_mdi => cam_mdi, -- .export
cam_mival => cam_mival, -- .export
cam_mistrt => cam_mistrt, -- .export
cam_mclko => cam_mclko, -- .export
cam_mdo => cam_mdo, -- .export
cam_mostrt => cam_mostrt, -- .export
cam_moval => cam_moval, -- .export
dvb_out_dsop => dvb_out_dsop, -- .export
dvb_out_dval => dvb_out_dval, -- .export
dvb_out_data => dvb_out_data -- .export
);
end architecture rtl; -- of dvb_ts_0
|
gpl-3.0
|
cc1f552d6c5a109edb87736796a90fc1
| 0.395021 | 3.806723 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/bd/ip/bd_proc_sys_reset_1_0/bd_proc_sys_reset_1_0_sim_netlist.vhdl
| 1 | 31,530 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Apr 14 18:32:23 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top bd_proc_sys_reset_1_0 -prefix
-- bd_proc_sys_reset_1_0_ bd_proc_sys_reset_0_0_sim_netlist.vhdl
-- Design : bd_proc_sys_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_cdc_sync is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
slowest_sync_clk : in STD_LOGIC
);
end bd_proc_sys_reset_1_0_cdc_sync;
architecture STRUCTURE of bd_proc_sys_reset_1_0_cdc_sync is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ext_reset_in,
I1 => mb_debug_sys_rst,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_cdc_sync_0 is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_proc_sys_reset_1_0_cdc_sync_0 : entity is "cdc_sync";
end bd_proc_sys_reset_1_0_cdc_sync_0;
architecture STRUCTURE of bd_proc_sys_reset_1_0_cdc_sync_0 is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end bd_proc_sys_reset_1_0_upcnt_n;
architecture STRUCTURE of bd_proc_sys_reset_1_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
end bd_proc_sys_reset_1_0_lpf;
architecture STRUCTURE of bd_proc_sys_reset_1_0_lpf is
signal \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_HIGH_EXT.ACT_HI_EXT\: entity work.bd_proc_sys_reset_1_0_cdc_sync
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.bd_proc_sys_reset_1_0_cdc_sync_0
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end bd_proc_sys_reset_1_0_sequence_psr;
architecture STRUCTURE of bd_proc_sys_reset_1_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.bd_proc_sys_reset_1_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of bd_proc_sys_reset_1_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of bd_proc_sys_reset_1_0_proc_sys_reset : entity is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of bd_proc_sys_reset_1_0_proc_sys_reset : entity is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of bd_proc_sys_reset_1_0_proc_sys_reset : entity is 1;
end bd_proc_sys_reset_1_0_proc_sys_reset;
architecture STRUCTURE of bd_proc_sys_reset_1_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.bd_proc_sys_reset_1_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.bd_proc_sys_reset_1_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_proc_sys_reset_1_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bd_proc_sys_reset_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bd_proc_sys_reset_1_0 : entity is "bd_proc_sys_reset_0_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bd_proc_sys_reset_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bd_proc_sys_reset_1_0 : entity is "proc_sys_reset,Vivado 2016.4";
end bd_proc_sys_reset_1_0;
architecture STRUCTURE of bd_proc_sys_reset_1_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.bd_proc_sys_reset_1_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
mit
|
2c3f6bbef528ebeaff94b0f93c8c4557
| 0.56746 | 2.853394 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/tb_ms_clock.vhd
| 2 | 1,008 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_ms_clock IS
END tb_ms_clock;
ARCHITECTURE behavior OF tb_ms_clock IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ms_timer
PORT(
clk : IN std_logic;
clk_1ms : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--Outputs
signal clk_1ms : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ms_timer PORT MAP (
clk => clk,
clk_1ms => clk_1ms
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
46e4458a9408e10784713e50a16ed6a3
| 0.583333 | 3.612903 | false | false | false | false |
phil91stud/protocol_hdl
|
SPI_master/hdl/spi_master.vhd
| 1 | 3,774 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
generic(
clk_freq : natural := 50000000; -- 50 MHz
spi_freq : natural := 1000000; -- 1 MHz
pre_delay : natural := 10; -- us
post_delay : natural := 10;
wordlength : natural := 16
);
port (
clk : in std_logic;
start_tx : in std_logic;
tx_done : out std_logic;
rx_data : out std_logic_vector(wordlength-1 downto 0);
tx_data : in std_logic_vector(wordlength-1 downto 0);
-- spi mode configuration
cpol : in std_logic;
cpha : in std_logic;
-- spi pins
mosi : out std_logic;
miso : in std_logic;
sclk : out std_logic;
ss : out std_logic -- more cs via demux
);
end entity spi_master;
architecture behavorial of spi_master is
constant clk_delay : natural := (clk_freq/(2*spi_freq))-1;
signal delay : natural range 0 to clk_delay + 1;
signal delay_pre : natural range 0 to (pre_delay*(clk_freq/1000))/1000;
signal delay_post : natural range 0 to (post_delay*(clk_freq/1000))/1000;
type tx_state_t is (spi_stx, del_pre, spi_active, del_post, spi_etx);
signal spistate : tx_state_t := spi_stx;
type clockstate_t is (propagate, capture);
signal clockstate : clockstate_t;
signal bits_to_transmit : natural range 0 to wordlength;
signal tx_reg : std_logic_vector(wordlength-1 downto 0) := (others => '0');
signal rx_reg : std_logic_vector(wordlength-1 downto 0) := (others => '0');
begin
main_proc:
process(clk,start_tx,tx_data,cpol,cpha)
begin
if rising_edge(clk) then
MOSI <= tx_reg(tx_reg'left); -- msb in register
if(delay > 0) then
delay <= delay - 1; -- counter for sclk generation
else
delay <= clk_delay;
end if;
case spistate is
when spi_stx =>
delay_post <= (post_delay*(clk_freq/1000))/1000;
delay_pre <= (pre_delay*(clk_freq/1000))/1000;
ss <= '1';
tx_done <= '0';
sclk <= cpol;
bits_to_transmit <= wordlength;
if start_tx = '1' then
spistate <= del_pre;
end if;
when del_pre =>
ss <= '0';
sclk <= cpol;
delay <= 0;
if delay_pre > 0 then
delay_pre <= delay_pre - 1;
else
spistate <= spi_active;
end if;
case cpha is
when '1' => clockstate <= propagate;
when '0' => clockstate <= capture;
when others => clockstate <= capture;
end case;
when spi_active =>
-- TODO
case clockstate is
when capture =>
sclk <= (cpol xor cpha);
if delay = 0 then
clockstate <= propagate;
if cpha = '1' then
bits_to_transmit <= bits_to_transmit - 1;
end if;
end if;
when propagate =>
sclk <= not (cpol xor cpha);
if delay = 0 then
clockstate <= capture;
if cpha = '0' then
bits_to_transmit <= bits_to_transmit - 1;
end if;
end if;
end case;
if delay = 0 and bits_to_transmit = 0 then
spistate <= del_post;
sclk <= cpol;
end if;
when del_post =>
sclk <= cpol;
if (delay_post > 0) then
delay_post <= delay_post - 1;
else
spistate <= spi_etx;
ss <= '1';
end if;
when spi_etx =>
tx_done <= '1';
rx_data <= rx_reg;
if start_tx = '0' then
spistate <= spi_stx;
end if;
end case;
end if;
end process main_proc;
shift_proc:
process(clk,spistate,rx_reg,tx_reg,miso)
begin
if rising_edge(clk) then
if spistate = spi_active and clockstate = capture and delay = 0 and bits_to_transmit /= 0 then
rx_reg <= rx_reg(rx_reg'left-1 downto 0) & miso;
end if;
if spistate = spi_active and clockstate = propagate and delay = 0 and bits_to_transmit /= 0 then
tx_reg <= tx_reg(tx_reg'left-1 downto 0) & '1';
end if;
if spistate = spi_stx then
tx_reg <= tx_data;
end if;
end if;
end process shift_proc;
end architecture behavorial;
|
gpl-2.0
|
e7786e1916ea2d3346a2a3adef5f79fa
| 0.612083 | 2.854766 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/vga800x600.vhd
| 1 | 2,114 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga800x600 is Port (
clk : in std_logic; -- 40 MHz
-- input
color : in std_logic_vector(11 downto 0);
-- logical interface
h : out std_logic_vector(10 downto 0);
v : out std_logic_vector(9 downto 0);
-- physical interface
red : out std_logic_vector(3 downto 0);
green : out std_logic_vector(3 downto 0);
blue : out std_logic_vector(3 downto 0);
hsync: out std_logic;
vsync: out std_logic);
end vga800x600;
architecture Behavioral of vga800x600 is
signal hcount : std_logic_vector(10 downto 0) := (others =>'0');
signal vcount : std_logic_vector(9 downto 0) := (others =>'0');
-- SVGA timing 800x600@60Hz pixel freq 40Mhz - http://tinyvga.com/vga-timing/800x600@60Hz
constant h_visible : integer := 800;
constant h_front : integer := 40;
constant h_sync : integer := 128;
constant h_total : integer := 1056;
constant v_visible : integer := 600;
constant v_front : integer := 1;
constant v_sync : integer := 4;
constant v_total : integer := 628;
constant pipeline_delay : integer := 12;
begin
h <= hcount;
v <= vcount;
counters : process(clk) begin
if rising_edge(clk) then
-- Counters
if hcount = (h_total-1) then
hcount <= (others =>'0');
if vcount = (v_total-1) then
vcount <= (others =>'0');
else
vcount <= vcount + 1;
end if;
else
hcount <= hcount + 1;
end if;
-- Hsync
if hcount >= (h_visible+h_front+ pipeline_delay) and hcount < (h_visible+h_front+h_sync + pipeline_delay) then
hsync <= '0';
else
hsync <= '1';
end if;
-- Vsync
if vcount >= (v_visible+v_front+ pipeline_delay) and vcount < (v_visible+v_front+v_sync + pipeline_delay) then
vsync <= '0';
else
vsync <= '1';
end if;
-- Colors
if hcount < h_visible and vcount < v_visible then
red <= color(11 downto 8);
green <= color( 7 downto 4);
blue <= color( 3 downto 0);
else
red <= "0000";
green <= "0000";
blue <= "0000";
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
e9a41c20cb03832305f89c3d8887fa79
| 0.617313 | 2.940195 | false | false | false | false |
rinatzakirov/vhdl
|
fifos.vhdl
| 1 | 27,320 |
--------------------------------------------------------------------
-- _ __ __ __ ____ __ = --
-- | | / // / / // __ \ / / = --
-- | | / // /_/ // / / // / = .__ |/ _/_ .__ .__ __ --
-- | |/ // __ // /_/ // /___ = /___) | / / ) / ) (_ ` --
-- |___//_/ /_//_____//_____/ = (___ /| (_ / (___(_ (__) --
-- ===== / --
-- === --
----------------------------- = ----------------------------------
--# fifos.vhdl - FIFOs
--# $Id$
--# Freely available from VHDL-extras (http://code.google.com/p/vhdl-extras)
--#
--# Copyright � 2014 Kevin Thibedeau
--# (kevin 'period' thibedeau 'at' gmail 'punto' com)
--#
--# Permission is hereby granted, free of charge, to any person obtaining a
--# copy of this software and associated documentation files (the "Software"),
--# to deal in the Software without restriction, including without limitation
--# the rights to use, copy, modify, merge, publish, distribute, sublicense,
--# and/or sell copies of the Software, and to permit persons to whom the
--# Software is furnished to do so, subject to the following conditions:
--#
--# The above copyright notice and this permission notice shall be included in
--# all copies or substantial portions of the Software.
--#
--# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
--# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
--# DEALINGS IN THE SOFTWARE.
--#
--# DEPENDENCIES: memory, sizing, synchronizing
--#
--# DESCRIPTION:
--# This package implements a set of generic FIFO components. There are three
--# variants. All use the same basic interface for the read/write ports and
--# status flags. The FIFOs have the following differences:
--#
--# * simple_fifo - Basic minimal FIFO for use in a single clock domain. This
--# component lacks the synchronizing logic needed for the
--# other two FIFOs and will synthesize more compactly.
--# * fifo - General FIFO with separate domains for read and write ports.
--# * packet_fifo - Extension of fifo component with ability to discard
--# written data before it is read. Useful for managing
--# packetized protocols with error detection at the end.
--#
--# All of these FIFOs use the dual_port_ram component from the memory package.
--# Reads can be performed concurrently with writes. The dual_port_ram
--# SYNC_READ generic is provided on the FIFO components to select between
--# synchronous or asynchronous read ports. When SYNC_READ is false,
--# distributed memory will be synthesized rather than RAM primitives. The
--# read port will update one cycle earlier than when SYNC_READ is true.
--#
--# The MEM_SIZE generic is used to set the number of words stored in the
--# FIFO. The read and write ports are unconstrained arrays. The size of
--# the words is established by the signals attached to the ports.
--#
--# The FIFOs have the following status flags:
--# * Empty - '1' when FIFO is empty
--# * Full - '1' when FIFO is full
--# * Almost_empty - '1' when there are less than Almost_empty_thresh
--# words in the FIFO. '0' when completely empty.
--# * Almost_full - '1' when there are less than Almost_full_thresh
--# unused words in the FIFO. '0' when completely full.
--#
--# Note that the almost empty and full flags are kept inactive when the
--# empty or full conditions are true.
--#
--# For the dual clock domain FIFOs, the Full and Almost_full flags are
--# registered on the write port clock domain. The Empty and Almost_empty
--# flags are registered on the read port clock domain. If the Almost_*
--# thresholds are connected to signals they will need to be registered
--# in their corresponding domains.
--#
--# Writes and reads can be performed continuously on successive cycles
--# until the Full or Empty flags become active. No effort is made to detect
--# overflow or underflow conditions. External logic can be used to check for
--# writes when full or reads when empty if necessary.
--#
--# The dual clock domain FIFOs use four-phase synchronization to pass
--# internal address pointers across domains. This results in delayed
--# updating of the status flags after writes and reads are performed.
--# Proper operation is guaranteed but you will see behavior such as the
--# full condition persisting for a few cycles after space has been freed by
--# a read. This will add some latency in the flow of data through these FIFOs
--# but will not cause overflow or underflow to occur. This only affects
--# cross-domain flag updates that *deassert* the flags. Assertion of the
--# flags will not be delayed. i.e. a read when the FIFO contains one entry
--# will assert the Empty flag one cycle later. Likewise, a write when the
--# FIFO has one empty entry left will assert the Full flag one cycle later.
--#
--# The simple_fifo component always updates all of its status flags on the
--# cycle after a read or write regardless of whether thay are asserted or
--# deasserted.
--#
--# The Almost_* flags use more complex comparison logic than the Full and
--# Empty flags. You can save some synthesized logic and boost clock speeds by
--# leaving them unconnected (open) if they are not needed in a design.
--# Similarly, if the thresholds are connected to constants rather than
--# signals, the comparison logic will be reduced during synthesis.
--#
--# The packet_fifo component has two additional control signals Keep and
--# Discard. When writing to the FIFO, the internal address pointers are
--# not updated on the read port domain until Keep is pulsed high. If written
--# data is not needed it can be dropped by pulsing Discard high. It is not
--# possible to discard data once Keep has been applied. Reads can be
--# performed concurrently with writes but the Empty flag will activate if
--# previously kept data is consumed even if new data has been written but
--# not yet retained with Keep.
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package fifos is
component simple_fifo is
generic (
RESET_ACTIVE_LEVEL : std_ulogic := '1';
MEM_SIZE : positive;
SYNC_READ : boolean := true
);
port (
Clock : in std_ulogic;
Reset : in std_ulogic;
We : in std_ulogic;
Wr_data : in std_ulogic_vector;
Re : in std_ulogic;
Rd_data : out std_ulogic_vector;
Empty : out std_ulogic;
Full : out std_ulogic;
Almost_empty_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_full_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_empty : out std_ulogic;
Almost_full : out std_ulogic
);
end component;
component fifo is
generic (
RESET_ACTIVE_LEVEL : std_ulogic := '1';
MEM_SIZE : positive;
SYNC_READ : boolean := true
);
port (
Wr_clock : in std_ulogic;
Wr_reset : in std_ulogic;
We : in std_ulogic;
Wr_data : in std_ulogic_vector;
Rd_clock : in std_ulogic;
Rd_reset : in std_ulogic;
Re : in std_ulogic;
Rd_data : out std_ulogic_vector;
Empty : out std_ulogic;
Full : out std_ulogic;
Almost_empty_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_full_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_empty : out std_ulogic;
Almost_full : out std_ulogic
);
end component;
component packet_fifo is
generic (
RESET_ACTIVE_LEVEL : std_ulogic := '1';
MEM_SIZE : positive;
SYNC_READ : boolean := true
);
port (
Wr_clock : in std_ulogic;
Wr_reset : in std_ulogic;
We : in std_ulogic;
Wr_data : in std_ulogic_vector;
Keep : in std_ulogic;
Discard : in std_ulogic;
Rd_clock : in std_ulogic;
Rd_reset : in std_ulogic;
Re : in std_ulogic;
Rd_data : out std_ulogic_vector;
Empty : out std_ulogic;
Full : out std_ulogic;
Almost_empty_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_full_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_empty : out std_ulogic;
Almost_full : out std_ulogic
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.memory.dual_port_ram;
entity simple_fifo is
generic (
RESET_ACTIVE_LEVEL : std_ulogic := '1';
MEM_SIZE : positive;
SYNC_READ : boolean := true
);
port (
Clock : in std_ulogic;
Reset : in std_ulogic;
We : in std_ulogic;
Wr_data : in std_ulogic_vector;
Re : in std_ulogic;
Rd_data : out std_ulogic_vector;
Empty : out std_ulogic;
Full : out std_ulogic;
Almost_empty_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_full_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_empty : out std_ulogic;
Almost_full : out std_ulogic
);
end entity;
architecture rtl of simple_fifo is
signal head, tail : natural range 0 to MEM_SIZE-1;
signal dpr_we : std_ulogic;
signal wraparound : boolean;
signal empty_loc, full_loc : std_ulogic;
begin
dpr : dual_port_ram
generic map (
MEM_SIZE => MEM_SIZE,
SYNC_READ => SYNC_READ
)
port map (
Wr_clock => Clock,
We => dpr_we,
Wr_addr => head,
Wr_data => Wr_data,
Rd_clock => Clock,
Re => Re,
Rd_addr => tail,
Rd_data => Rd_data
);
dpr_we <= '1' when we = '1' and full_loc = '0' else '0';
wr_rd : process(Clock, Reset) is
variable head_v, tail_v : natural range 0 to MEM_SIZE-1;
variable wraparound_v : boolean;
begin
if Reset = RESET_ACTIVE_LEVEL then
head <= 0;
tail <= 0;
full_loc <= '0';
empty_loc <= '1';
Almost_full <= '0';
Almost_empty <= '0';
wraparound <= false;
elsif rising_edge(Clock) then
head_v := head;
tail_v := tail;
wraparound_v := wraparound;
if We = '1' and (wraparound = false or head /= tail) then
if head_v = MEM_SIZE-1 then
head_v := 0;
wraparound_v := true;
else
head_v := head_v + 1;
end if;
end if;
if Re = '1' and (wraparound = true or head /= tail) then
if tail_v = MEM_SIZE-1 then
tail_v := 0;
wraparound_v := false;
else
tail_v := tail_v + 1;
end if;
end if;
if head_v /= tail_v then
empty_loc <= '0';
full_loc <= '0';
else
if wraparound_v then
full_loc <= '1';
empty_loc <= '0';
else
full_loc <= '0';
empty_loc <= '1';
end if;
end if;
Almost_full <= '0';
Almost_empty <= '0';
if head_v /= tail_v then
if head_v > tail_v then
if Almost_full_thresh >= MEM_SIZE - (head_v - tail_v) then
Almost_full <= '1';
end if;
if Almost_empty_thresh >= head_v - tail_v then
Almost_empty <= '1';
end if;
else
if Almost_full_thresh >= tail_v - head_v then
Almost_full <= '1';
end if;
if Almost_empty_thresh >= MEM_SIZE - (tail_v - head_v) then
Almost_empty <= '1';
end if;
end if;
end if;
head <= head_v;
tail <= tail_v;
wraparound <= wraparound_v;
end if;
end process;
Empty <= empty_loc;
Full <= full_loc;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.sizing.bit_size;
use work.synchronizing.all;
use work.memory.dual_port_ram;
entity fifo is
generic (
RESET_ACTIVE_LEVEL : std_ulogic := '1';
MEM_SIZE : positive;
SYNC_READ : boolean := true;
READ_AHEAD : boolean := true
);
port (
Wr_clock : in std_ulogic;
Wr_reset : in std_ulogic;
We : in std_ulogic;
Wr_data : in std_ulogic_vector;
Rd_clock : in std_ulogic;
Rd_reset : in std_ulogic;
Re : in std_ulogic;
Rd_data : out std_ulogic_vector;
Empty : out std_ulogic;
Full : out std_ulogic;
Almost_empty_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_full_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_empty : out std_ulogic;
Almost_full : out std_ulogic
);
end entity;
architecture rtl of fifo is
signal head, tail, head_rd, tail_wr : natural range 0 to MEM_SIZE-1;
signal dpr_we : std_ulogic;
signal wraparound_wr, wraparound_rd : boolean;
signal wrap_set, wrap_clr, wrap_set_rd, wrap_clr_wr : std_ulogic;
signal empty_loc, full_loc : std_ulogic;
constant ADDR_SIZE : natural := bit_size(MEM_SIZE-1);
signal head_sulv, head_rd_sulv : std_ulogic_vector(ADDR_SIZE-1 downto 0);
signal tail_sulv, tail_wr_sulv : std_ulogic_vector(ADDR_SIZE-1 downto 0);
signal ReadAhead: std_ulogic;
begin
ReadAhead <= '1' when READ_AHEAD else Re;
dpr : dual_port_ram
generic map (
MEM_SIZE => MEM_SIZE,
SYNC_READ => SYNC_READ
)
port map (
Wr_clock => Wr_clock,
We => dpr_we,
Wr_addr => head,
Wr_data => Wr_data,
Rd_clock => Rd_clock,
Re => ReadAhead,
Rd_addr => tail,
Rd_data => Rd_data
);
dpr_we <= '1' when we = '1' and full_loc = '0' else '0';
wr : process(Wr_clock, Wr_reset) is
variable head_v : natural range 0 to MEM_SIZE-1;
variable wraparound_v : boolean;
begin
if Wr_reset = RESET_ACTIVE_LEVEL then
head <= 0;
full_loc <= '0';
Almost_full <= '0';
wraparound_wr <= false;
wrap_set <= '0';
elsif rising_edge(Wr_clock) then
wrap_set <= '0';
head_v := head;
wraparound_v := wraparound_wr;
if We = '1' and (wraparound_v = false or head_v /= tail_wr) then
if head_v = MEM_SIZE-1 then
head_v := 0;
wraparound_v := true;
wrap_set <= '1';
else
head_v := head_v + 1;
end if;
end if;
-- Update full flag
if head_v /= tail_wr then
full_loc <= '0';
else
if wraparound_v then
full_loc <= '1';
else
full_loc <= '0';
end if;
end if;
-- Update almost full flag
Almost_full <= '0';
if head_v /= tail_wr then
if head_v > tail_wr then
if Almost_full_thresh >= MEM_SIZE - (head_v - tail_wr) then
Almost_full <= '1';
end if;
else
if Almost_full_thresh >= tail_wr - head_v then
Almost_full <= '1';
end if;
end if;
end if;
head <= head_v;
if wrap_clr_wr = '0' then
wraparound_wr <= wraparound_v;
else
wraparound_wr <= false;
end if;
end if;
end process;
rd : process(Rd_clock, Rd_reset) is
variable tail_v : natural range 0 to MEM_SIZE-1;
variable wraparound_v : boolean;
begin
if Rd_reset = RESET_ACTIVE_LEVEL then
tail <= 0;
empty_loc <= '1';
Almost_empty <= '0';
wraparound_rd <= false;
wrap_clr <= '0';
elsif rising_edge(Rd_clock) then
wrap_clr <= '0';
tail_v := tail;
wraparound_v := wraparound_rd;
if Re = '1' and (wraparound_v = true or head_rd /= tail_v) then
if tail_v = MEM_SIZE-1 then
tail_v := 0;
wraparound_v := false;
wrap_clr <= '1';
else
tail_v := tail_v + 1;
end if;
end if;
-- Update empty flag
if head_rd /= tail_v then
empty_loc <= '0';
else
if not wraparound_v then
empty_loc <= '1';
else
empty_loc <= '0';
end if;
end if;
-- Update almost empty flag
Almost_empty <= '0';
if head_rd /= tail_v then
if head_rd > tail_v then
if Almost_empty_thresh >= head_rd - tail_v then
Almost_empty <= '1';
end if;
else
if Almost_empty_thresh >= MEM_SIZE - (tail_v - head_rd) then
Almost_empty <= '1';
end if;
end if;
end if;
tail <= tail_v;
if wrap_set_rd = '0' then
wraparound_rd <= wraparound_v;
else
wraparound_rd <= true;
end if;
end if;
end process;
Empty <= empty_loc;
Full <= full_loc;
-- Synchronize head and tail pointers across domains
hs_head : handshake_synchronizer
generic map (
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock_tx => Wr_clock,
Reset_tx => Wr_reset,
Clock_rx => Rd_clock,
Reset_rx => Rd_reset,
Tx_data => head_sulv,
Send_data => '1',
Sending => open,
Data_sent => open,
Rx_data => head_rd_sulv,
New_data => open
);
head_sulv <= to_stdulogicvector(std_logic_vector(to_unsigned(head, head_sulv'length)));
head_rd <= to_integer(unsigned(to_stdlogicvector(head_rd_sulv)));
hs_tail : handshake_synchronizer
generic map (
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock_tx => Rd_clock,
Reset_tx => Rd_reset,
Clock_rx => Wr_clock,
Reset_rx => Wr_reset,
Tx_data => tail_sulv,
Send_data => '1',
Sending => open,
Data_sent => open,
Rx_data => tail_wr_sulv,
New_data => open
);
tail_sulv <= to_stdulogicvector(std_logic_vector(to_unsigned(tail, tail_sulv'length)));
tail_wr <= to_integer(unsigned(to_stdlogicvector(tail_wr_sulv)));
-- Synchronize wraparound control flags
wc_wr : bit_synchronizer
generic map (
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock => Wr_clock,
Reset => Wr_reset,
Bit_in => wrap_clr,
Sync => wrap_clr_wr
);
ws_rd : bit_synchronizer
generic map (
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock => Rd_clock,
Reset => Rd_reset,
Bit_in => wrap_set,
Sync => wrap_set_rd
);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.sizing.bit_size;
use work.synchronizing.all;
use work.memory.dual_port_ram;
entity packet_fifo is
generic (
RESET_ACTIVE_LEVEL : std_ulogic := '1';
MEM_SIZE : positive;
SYNC_READ : boolean := true
);
port (
Wr_clock : in std_ulogic;
Wr_reset : in std_ulogic;
We : in std_ulogic;
Wr_data : in std_ulogic_vector;
Keep : in std_ulogic;
Discard : in std_ulogic;
Rd_clock : in std_ulogic;
Rd_reset : in std_ulogic;
Re : in std_ulogic;
Rd_data : out std_ulogic_vector;
Empty : out std_ulogic;
Full : out std_ulogic;
Almost_empty_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_full_thresh : in natural range 0 to MEM_SIZE-1 := 1;
Almost_empty : out std_ulogic;
Almost_full : out std_ulogic
);
end entity;
architecture rtl of packet_fifo is
signal head, tail, head_rd, tail_wr : natural range 0 to MEM_SIZE-1;
signal dpr_we : std_ulogic;
signal wraparound_wr, wraparound_rd : boolean;
signal wrap_set, wrap_clr, wrap_set_rd, wrap_clr_wr : std_ulogic;
signal pkt_head : natural range 0 to MEM_SIZE-1;
signal pkt_wraparound : boolean;
signal empty_loc, full_loc : std_ulogic;
constant ADDR_SIZE : natural := bit_size(MEM_SIZE-1);
signal head_sulv, head_rd_sulv : std_ulogic_vector(ADDR_SIZE-1 downto 0);
signal tail_sulv, tail_wr_sulv : std_ulogic_vector(ADDR_SIZE-1 downto 0);
begin
dpr : dual_port_ram
generic map (
MEM_SIZE => MEM_SIZE,
SYNC_READ => SYNC_READ
)
port map (
Wr_clock => Wr_clock,
We => dpr_we,
Wr_addr => pkt_head,
Wr_data => Wr_data,
Rd_clock => Rd_clock,
Re => Re,
Rd_addr => tail,
Rd_data => Rd_data
);
dpr_we <= '1' when we = '1' and full_loc = '0' else '0';
wr : process(Wr_clock, Wr_reset) is
variable head_v : natural range 0 to MEM_SIZE-1;
variable wraparound_v : boolean;
begin
if Wr_reset = RESET_ACTIVE_LEVEL then
head <= 0;
full_loc <= '0';
Almost_full <= '0';
wraparound_wr <= false;
wrap_set <= '0';
pkt_head <= 0;
pkt_wraparound <= false;
elsif rising_edge(Wr_clock) then
wrap_set <= '0';
head_v := pkt_head;
wraparound_v := pkt_wraparound;
if We = '1' and (wraparound_v = false or head_v /= tail_wr) then
if head_v = MEM_SIZE-1 then
head_v := 0;
wraparound_v := true;
wrap_set <= '1';
else
head_v := head_v + 1;
end if;
end if;
-- Update full flag
if head_v /= tail_wr then
full_loc <= '0';
else
if wraparound_v then
full_loc <= '1';
else
full_loc <= '0';
end if;
end if;
-- Update almost full flag
Almost_full <= '0';
if head_v /= tail_wr then
if head_v > tail_wr then
if Almost_full_thresh >= MEM_SIZE - (head_v - tail_wr) then
Almost_full <= '1';
end if;
else
if Almost_full_thresh >= tail_wr - head_v then
Almost_full <= '1';
end if;
end if;
end if;
pkt_head <= head_v;
if wrap_clr_wr = '0' then
pkt_wraparound <= wraparound_v;
else
pkt_wraparound <= false;
end if;
if Discard = '1' then
pkt_head <= head;
pkt_wraparound <= wraparound_wr;
elsif Keep = '1' then
head <= pkt_head;
wraparound_wr <= pkt_wraparound;
end if;
end if;
end process;
rd : process(Rd_clock, Rd_reset) is
variable tail_v : natural range 0 to MEM_SIZE-1;
variable wraparound_v : boolean;
begin
if Rd_reset = RESET_ACTIVE_LEVEL then
tail <= 0;
empty_loc <= '1';
Almost_empty <= '0';
wraparound_rd <= false;
wrap_clr <= '0';
elsif rising_edge(Rd_clock) then
wrap_clr <= '0';
tail_v := tail;
wraparound_v := wraparound_rd;
if Re = '1' and (wraparound_v = true or head_rd /= tail_v) then
if tail_v = MEM_SIZE-1 then
tail_v := 0;
wraparound_v := false;
wrap_clr <= '1';
else
tail_v := tail_v + 1;
end if;
end if;
-- Update empty flag
if head_rd /= tail_v then
empty_loc <= '0';
else
if not wraparound_v then
empty_loc <= '1';
else
empty_loc <= '0';
end if;
end if;
-- Update almost empty flag
Almost_empty <= '0';
if head_rd /= tail_v then
if head_rd > tail_v then
if Almost_empty_thresh >= head_rd - tail_v then
Almost_empty <= '1';
end if;
else
if Almost_empty_thresh >= MEM_SIZE - (tail_v - head_rd) then
Almost_empty <= '1';
end if;
end if;
end if;
tail <= tail_v;
if wrap_set_rd = '0' then
wraparound_rd <= wraparound_v;
else
wraparound_rd <= true;
end if;
end if;
end process;
Empty <= empty_loc;
Full <= full_loc;
-- Synchronize head and tail pointers across domains
hs_head : handshake_synchronizer
generic map (
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock_tx => Wr_clock,
Reset_tx => Wr_reset,
Clock_rx => Rd_clock,
Reset_rx => Rd_reset,
Tx_data => head_sulv,
Send_data => '1',
Sending => open,
Data_sent => open,
Rx_data => head_rd_sulv,
New_data => open
);
head_sulv <= to_stdulogicvector(std_logic_vector(to_unsigned(head, head_sulv'length)));
head_rd <= to_integer(unsigned(to_stdlogicvector(head_rd_sulv)));
hs_tail : handshake_synchronizer
generic map (
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock_tx => Rd_clock,
Reset_tx => Rd_reset,
Clock_rx => Wr_clock,
Reset_rx => Wr_reset,
Tx_data => tail_sulv,
Send_data => '1',
Sending => open,
Data_sent => open,
Rx_data => tail_wr_sulv,
New_data => open
);
tail_sulv <= to_stdulogicvector(std_logic_vector(to_unsigned(tail, tail_sulv'length)));
tail_wr <= to_integer(unsigned(to_stdlogicvector(tail_wr_sulv)));
-- Synchronize wraparound control flags
wc_wr : bit_synchronizer
generic map (
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock => Wr_clock,
Reset => Wr_reset,
Bit_in => wrap_clr,
Sync => wrap_clr_wr
);
ws_rd : bit_synchronizer
generic map (
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock => Rd_clock,
Reset => Rd_reset,
Bit_in => wrap_set,
Sync => wrap_set_rd
);
end architecture;
|
lgpl-2.1
|
0f0191b390610cf08640be592c2cce94
| 0.532286 | 3.756084 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/clock_24h_7seg.vhd
| 2 | 1,368 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_24h_7seg is
Port (
CLK : in std_logic;
SEVENSEG_SEG : out std_logic_vector(7 downto 0);
SEVENSEG_AN : out std_logic_vector(4 downto 0)
);
end clock_24h_7seg;
architecture Behavioral of clock_24h_7seg is
signal clk_1ms : std_logic;
signal clk_1s : std_logic;
signal display_hex : std_logic_vector (15 downto 0);
COMPONENT seven_seg
PORT(
display_hex : IN std_logic_vector(15 downto 0);
clk : IN std_logic;
double_dot : IN std_logic;
anodes : OUT std_logic_vector(4 downto 0);
sevenseg : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT ms_timer
PORT(
clk : IN std_logic;
clk_1ms : OUT std_logic
);
END COMPONENT;
COMPONENT clock24h_bcd
PORT(
clk_1ms : IN std_logic;
hour_bcd : OUT std_logic_vector(7 downto 0);
minute_bcd : OUT std_logic_vector(7 downto 0);
clk_1s : OUT std_logic
);
END COMPONENT;
begin
Inst_seven_seg: seven_seg PORT MAP(
display_hex => display_hex,
clk => clk_1ms,
double_dot => clk_1s,
anodes => SEVENSEG_AN,
sevenseg => SEVENSEG_SEG
);
Inst_clock24h_bcd: clock24h_bcd PORT MAP(
clk_1ms => clk_1ms,
hour_bcd => display_hex(15 downto 8),
minute_bcd => display_hex(7 downto 0),
clk_1s => clk_1s
);
Inst_ms_timer: ms_timer PORT MAP(
clk => CLK,
clk_1ms => clk_1ms
);
end Behavioral;
|
gpl-3.0
|
14812203e285632efca6991c9d634513
| 0.662281 | 2.677104 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/audioDac/topModule.vhd
| 1 | 1,170 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity topModule is Port (
CLK : in STD_LOGIC;
AUDIO1_RIGHT : out STD_LOGIC;
AUDIO1_LEFT : out STD_LOGIC);
end topModule;
architecture Behavioral of topModule is
signal count : STD_LOGIC_VECTOR(27 downto 0);
signal audio_data : STD_LOGIC_VECTOR(8 downto 0);
signal audio_out : STD_LOGIC;
COMPONENT counter PORT ( -- max count of 236646400
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(27 DOWNTO 0));
END COMPONENT;
COMPONENT rom_memory PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END COMPONENT;
COMPONENT audio_dac_8bit PORT(
clk : IN std_logic;
data : IN std_logic_vector(8 downto 0);
pulseStream : OUT std_logic);
END COMPONENT;
begin
AUDIO1_RIGHT <= audio_out;
AUDIO1_LEFT <= audio_out;
addr_counter : counter PORT MAP (
clk => CLK,
q => count
);
waveform_rom : rom_memory
PORT MAP (
clka => CLK,
addra => count(27 downto 12),
douta => audio_data
);
Inst_audio_dac_8bit: audio_dac_8bit PORT MAP(
clk => CLK,
data => audio_data,
pulseStream => audio_out
);
end Behavioral;
|
gpl-3.0
|
40c76539197ae0ca872df1154cf5c3f0
| 0.668376 | 2.962025 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/tb_scaler.vhd
| 1 | 1,463 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_scaler IS
END tb_scaler;
ARCHITECTURE behavior OF tb_scaler IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pixel_scaling
PORT(
x_pixel : IN std_logic_vector(10 downto 0);
y_pixel : IN std_logic_vector(9 downto 0);
x0 : OUT std_logic_vector(17 downto 0);
y0 : OUT std_logic_vector(17 downto 0)
);
END COMPONENT;
--Inputs
signal x_pixel : std_logic_vector(10 downto 0) := (others => '0');
signal y_pixel : std_logic_vector(9 downto 0) := (others => '0');
--Outputs
signal x0 : std_logic_vector(17 downto 0);
signal y0 : std_logic_vector(17 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pixel_scaling PORT MAP (
x_pixel => x_pixel,
y_pixel => y_pixel,
x0 => x0,
y0 => y0
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
stimloop : for i in 0 to 799 loop
wait for period;
x_pixel <= std_logic_vector(to_unsigned(i, x_pixel'length));
y_pixel <= std_logic_vector(to_unsigned(i, y_pixel'length));
wait for period;
end loop stimloop;
wait;
end process;
END;
|
gpl-3.0
|
582ef63c43d09b0feacd605252e5427f
| 0.60082 | 3.434272 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Source/SPI_SlaveTransmitterSerializer.vhd
| 1 | 3,960 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides an SPI slave transmitter serializer operating in SPI 3. This means
-- that the outgoing serial data are shifted at the leading (falling) SCLK edges
-- and thus can be sampled at the trailing (rising) edge by the SPI master´s
-- receiver.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPI_SlaveTransmitterSerializer is
generic
(
-- The width of the data.
width: positive
);
port
(
-- The clock controlling the serial data transmission.
sclk: in std_logic;
-- The slave select (low during transmission).
ss: in std_logic;
-- The parallel input used to get the data to be sent from.
data: in std_logic_vector(width-1 downto 0) := (others => '0');
-- The serial output.
miso: out std_logic
);
end entity;
architecture stdarch of SPI_SlaveTransmitterSerializer is
type reg_type is record
ss: std_logic;
data: std_logic_vector(width-1 downto 0);
end record;
signal state, next_state: reg_type :=
(
ss => '1',
data => (others => '0')
);
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process(sclk, ss) is
begin
if ss = '1' then
-- We must reset asynchronously here because SS changes while SCLK is
-- stopped (SCLK is only active when transferring data).
state <=
(
ss => '1',
data => (others => '0')
);
elsif falling_edge(sclk) then
state <= next_state;
end if;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, ss, data) is
begin
-- Defaults.
next_state <= state;
-- For SS edge detection.
next_state.ss <= ss;
-- Load serializer on first falling SCLK edge since SS has become active,
-- this also provides the first bit (MSB) at the serial output. Serialize
-- on all following falling SCLK edges providing the remaining bits.
if (state.ss = '1' and ss = '0') then
next_state.data <= data;
else
next_state.data <= state.data(width-2 downto 0) & '0';
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
miso <= state.data(width-1);
end architecture;
|
gpl-3.0
|
664717f3d0abd9436718e47ae1687601
| 0.470707 | 5.245033 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/VGA1/ipcore_dir/clock_manager/simulation/clock_manager_tb.vhd
| 1 | 6,160 |
-- file: clock_manager_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clock_manager_tb is
end clock_manager_tb;
architecture test of clock_manager_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clock_manager_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clock_manager_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
gpl-3.0
|
5d03670b271e53e0452ba0bd55845025
| 0.639773 | 4.301676 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/koc/koc_signal_pack.vhd
| 1 | 3,382 |
library ieee;
use ieee.std_logic_1164.all;
package koc_signal_pack is
constant axi_resp_okay : std_logic_vector := "00";
component koc_signal is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32;
axi_control_offset : integer := 0;
axi_control_signal_bit_loc : integer := 0;
axi_control_status_bit_loc : integer := 1);
port (
-- Global Interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0);
-- Events.
sig_out : out std_logic;
sig_in : in std_logic;
int : out std_logic);
end component;
end package;
|
mit
|
de62ca6122fe28a33f3834fbd84c4161
| 0.44175 | 4.915698 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
testbench/dvb_ts_shaper_tb.vhd
| 1 | 1,522 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_ts_shaper_tb is
end;
architecture sym of dvb_ts_shaper_tb is
signal rst : std_logic := '1';
signal clk : std_logic;
signal src_ready : std_logic;
signal src_dsop : std_logic;
signal src_data : std_logic_vector(7 downto 0);
signal src_dval : std_logic;
signal dvb_clk : std_logic;
signal dvb_dsop : std_logic;
signal dvb_data : std_logic_vector(7 downto 0);
signal dvb_dval : std_logic;
signal dvb_src_clk : std_logic := '0';
begin
DVB_SRC_0 : entity work.dvb_source
generic map (
CLOCK_RATE_MHZ => 125,
INTERPACKET_GAP => 300,
INTEROCTET_GAP => 0
)
port map (
ts_clk => clk,
ts_strt => src_dsop,
ts_dval => src_dval,
ts_data => src_data
);
SHAPER_0 : entity work.dvb_ts_shaper
port map (
rst => rst,
clk => clk,
--
clkdiv => (others => '0'),
--
dvb_indrdy => src_ready,
dvb_indata => src_data,
dvb_indsop => src_dsop,
dvb_indval => src_dval,
--
dvb_clk => dvb_src_clk,
--
dvb_out_clk => dvb_clk,
dvb_out_dsop => dvb_dsop,
dvb_out_data => dvb_data,
dvb_out_dval => dvb_dval
);
process
begin
wait until rising_edge(clk);
rst <= '0';
--
wait;
end process;
process
begin
dvb_src_clk <= not dvb_src_clk;
wait for 4.63 ns;
end process;
end;
|
gpl-3.0
|
b268db319d45fdc6a48a94b8498b7305
| 0.615637 | 2.450886 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/numeric_bit.vhd
| 6 | 32,869 |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
package NUMERIC_BIT is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits, except ARG'LEFT, are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
end NUMERIC_BIT;
|
mit
|
58bda0d3ec095372f0b43fb7b1282ef8
| 0.566096 | 4.211275 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/SynchronizedGatedCounter.vhd
| 1 | 5,687 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Counts a pulse signal using a gate signal that might be asynchronous. Counting
-- is done using a gated counter that runs in the clock domain of the pulse
-- signal. The gate signal is synchronized to the pulse signal. The outputs also
-- belong to the pulse signal´s clock domain.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library Common;
use work.Globals.all;
entity SynchronizedGatedCounter is
generic
(
-- The width of the measured frequency or period value.
counter_width: natural := 32
);
port
(
-- The signal to measure the frequency or the period from.
pulse_signal: in std_logic;
-- The gate signal used control the counter. Both edges of this signal
-- are treated as gate events.
toggled_gate_signal: in std_logic;
-- '0' to hold output values, '1' to update them.
update_output: in std_logic;
-- The counted value.
value: out unsigned (counter_width-1 downto 0);
-- '1' if an overflow has occurred in the current counting period.
overflow: out std_logic;
-- Toggles each time a gate event has been successfully detected which
-- indicates that there are proper gate and pulse signals.
toggled_gate_detected: out std_logic
);
end entity;
architecture stdarch of SynchronizedGatedCounter is
-- Internal and registered output values.
type output_reg_type is record
value: unsigned (counter_width-1 downto 0);
overflow: std_logic;
end record;
signal output_state, next_output_state: output_reg_type :=
(
value => (others => '0'),
overflow => '0'
);
-- Miscellaneous control signals.
signal toggled_gate_signal_synced_to_pulse, gate_edge: std_logic := '0';
signal update_output_synced_to_pulse: std_logic := '0';
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
-- Synchronizes the toggled counter gate signal to the counter pulse signal.
gate_synchronizer: entity Common.Synchronizer
generic map
(
pulse_stretcher => false,
nr_of_stages => 2
)
port map
(
clk => pulse_signal,
in_async => toggled_gate_signal,
out_sync => toggled_gate_signal_synced_to_pulse
);
-- Detects both edges of the toggled gate signal to reconstruct a real gate
-- signal for the counter.
toggling_gate_edge_detector: entity Common.EdgeDetector
generic map
(
detect_rising_edges => true,
detect_falling_edges => true
)
port map
(
clk => pulse_signal,
sigin => toggled_gate_signal_synced_to_pulse,
edge => gate_edge
);
-- Counts a pulse signal with respect to the gate signal. This counter runs in
-- the clock domain of the pulse signal, all in- and output signals belong to
-- the corresponding clock domain.
counter: entity work.GatedCounter
generic map
(
counter_width => counter_width
)
port map
(
pulse_signal => pulse_signal,
gate_signal => gate_edge,
value => next_output_state.value,
overflow => next_output_state.overflow
);
-- Synchronizes the update output signal to the counter pulse signal.
update_output_synchronizer: entity Common.Synchronizer
generic map
(
pulse_stretcher => true,
nr_of_stages => 2
)
port map
(
clk => pulse_signal,
in_async => update_output,
out_sync => update_output_synced_to_pulse
);
--------------------------------------------------------------------------------
-- State and data register.
--------------------------------------------------------------------------------
pulse_state_register: process is
begin
wait until rising_edge(pulse_signal);
if (update_output_synced_to_pulse = '1') then
output_state <= next_output_state;
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
value <= output_state.value;
overflow <= output_state.overflow;
toggled_gate_detected <= toggled_gate_signal_synced_to_pulse;
end architecture;
|
gpl-3.0
|
4c255892f50d40e42ed8755adaf319b1
| 0.537718 | 4.992976 | false | false | false | false |
arthurTemporim/SD_SS
|
rel/final/Projeto/Main.vhd
| 1 | 3,493 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Main is
port(
modo : in std_logic := '0'; -- Gera / Valida. [sel 1]
k : in std_logic_vector (3 downto 0) := "1000"; -- Seleciona um grupo de até 16 bits. [sel 2~5]
s : in std_logic_vector (3 downto 0) := "0000"; -- Seleciona um valor. [sel 6~9]
hab_clk : in std_logic := '1'; -- Habilitador de clock. [sel 10]
but_clk : in std_logic := '0'; -- Botão pra trabalhar como clock. [sel 11]
clk : in std_logic := '0'; -- Clock do circuito.
display : out std_logic_vector (6 to 0); -- Display usado para mostrar estatisticas.
leds : out std_logic_vector (15 downto 0) -- LEDs de saída do circuito.
);
end Main;
architecture Behavioral of Main is
-- Vetor usado para deslocamento de bits.
signal vetor : std_logic_vector (15 downto 0) := "0000000000000010";
-- Guarda quantas vezes o valor de 'S' aparece.
signal estatistica : std_logic_vector (3 downto 0) := "0000";
-- Sinal para conectar estatística com display.
signal bcd : std_logic_vector (6 to 0);
-- Conta quantas vezes o valor de 'S' aparece no vetor.
signal conta_s : integer range 0 to 15;
begin
process (vetor, clk, modo)
-- Transforma o valor binário do grupo 'k' em inteiro.
variable grupo : integer range 0 to 15;
begin
-- Função GERA e VALIDA implementadas juntas.
if (modo = '0') then
-- Variável que contém tamanho do grupo.
grupo := to_integer(unsigned(k));
-- Aplica a geração aleatória.
vetor(grupo) <= vetor(0) xor vetor(1);
-- Da o shift nos bits em borda de subida.
if (clk'event and clk = '1' and hab_clk = '1') then
vetor <= std_logic_vector(unsigned(vetor) srl 1);
elsif (but_clk'event and but_clk = '1') then
vetor <= std_logic_vector(unsigned(vetor) srl 1);
end if;
-- VALIDA
-- Se os 4 últimos digitos do vetor foram iguais ao valor de 'S' então conta.
if (vetor(0) = s(0) and vetor(1) = s(1) and vetor(2) = s(2) and vetor(3) = s(3)) then
conta_s <= conta_s + 1;
end if;
end if;
end process;
-- Atribui valor inteiro da contagem para sinal.
estatistica <= std_logic_vector(to_unsigned(conta_s, 4));
-- BCD.
process (estatistica, clk)
begin
if (estatistica = "0000") then -- 0
bcd <= "1111110";
elsif (estatistica = "0001") then -- 1
bcd <= "0110000";
elsif (estatistica = "0010") then -- 2
bcd <= "1101101";
elsif (estatistica = "0011") then -- 3
bcd <= "1111001";
elsif (estatistica = "0100") then -- 4
bcd <= "0110010";
elsif (estatistica = "0101") then -- 5
bcd <= "1011010";
elsif (estatistica = "0110") then -- 6
bcd <= "1011111";
elsif (estatistica = "0111") then -- 7
bcd <= "1110000";
elsif (estatistica = "1000") then -- 8
bcd <= "1111111";
elsif (estatistica = "1001") then -- 9
bcd <= "1111011";
elsif (estatistica = "1010") then -- A
bcd <= "1110111";
elsif (estatistica = "1011") then -- B
bcd <= "0011111";
elsif (estatistica = "1100") then -- C
bcd <= "1001110";
elsif (estatistica = "1101") then -- D
bcd <= "0111101";
elsif (estatistica = "1110") then -- E
bcd <= "1001111";
else
bcd <= "1000111"; -- Caso defaul -> 'F'
end if;
end process;
-- Inverte os valores do display pois é anodo.
display <= not bcd;
-- Atribui o valor do vetor deslocado aos LEDs de saida.
leds <= vetor;
end Behavioral;
|
mit
|
c7cb171da68dc93fb782649886582ec9
| 0.607533 | 2.982847 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/LookupTableContainer.vhd
| 1 | 5,033 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Provides lookup tables for periodic signals, e.g. sine.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.globals.all;
entity LookupTableContainer is
generic
(
-- The width of the phase values.
phase_width: natural := 12;
-- The width of the sample values.
sample_width: natural := 16
);
port
(
-- The system clock.
clk: in std_logic;
-- The current phase value.
phase: in unsigned (phase_width-1 downto 0);
-- The sample value according to the current phase.
sample: out signed (sample_width-1 downto 0)
);
end entity;
architecture stdarch of LookupTableContainer is
-- Lookup tables in general.
signal lookup_sample: signed (sample_width-1 downto 0) :=
(others => '0');
-- Quarter period lookup tables (0..Pi/2), e.g. for sine or cosine.
constant lookup_length: natural := (2**phase_width)/4;
type quarter_period_lookup_type is array (0 to lookup_length-1) of
signed (sample_width-1 downto 0);
signal quarter_period_lookup_address: unsigned (phase_width-3 downto 0) :=
(others => '0');
signal invert_lookup_sample: std_logic := '0';
-- Sine wave lookup table (for 0..Pi/2).
signal sine_lookup: quarter_period_lookup_type;
begin
--------------------------------------------------------------------------------
-- Lookup tables used for waveform generation.
--------------------------------------------------------------------------------
-- Creates the address used to read a sample value from a quarter period lookup
-- table. This includes switching the address to backward counting when
-- necessary. Also detects whether the read sample value must be inverted.
create_quarter_period_lookup_address: process is
begin
wait until rising_edge(clk);
-- Depending on the quadrant, determine the lookup table address.
if phase(phase'left-1) = '0' then
-- First or third quadrant, read forward.
quarter_period_lookup_address <=
phase(phase'left-2 downto 0);
else
-- Second or fourth quadrant, read backwards.
quarter_period_lookup_address <= (lookup_length-1) -
phase(phase'left-2 downto 0);
end if;
-- Mark to invert the value read from the lookup table for the second
-- half period (third or fourth quadrant).
invert_lookup_sample <= phase(phase'left);
end process;
-- Initializes the sine lookup table for the first quarter (0..Pi/2).
fill_sine_lookup_table: for i in 0 to lookup_length-1 generate
sine_lookup(i) <=
to_signed
(
integer
(
sin
(
-- Each item reflects the center of the interval,
-- not the beginning. Doing so, we can use the table
-- for all quarters in a completely symmetric way.
(real(i) + 0.5) * (MATH_PI/2.0) / real(lookup_length)
)
* ((real(2**sample_width)/2.0)-1.0)
),
sample_width
);
end generate;
-- Reads the value from the lookup table.
-- Note: The lookup table address must be synchronized to get a block RAM
-- inferred, check synthesis report.
lookup_sample <= sine_lookup(to_integer(quarter_period_lookup_address));
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
sample <= lookup_sample when invert_lookup_sample = '0' else
-lookup_sample;
end architecture;
|
gpl-3.0
|
3555bfb2c4e57fe12be7f7ba454ad9d9
| 0.520167 | 4.900682 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/plasoc_cpu_0_crossbar_wrap_pack.vhd
| 1 | 14,838 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_cpu_0_crossbar_wrap_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_cpu_0_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 5;
axi_slave_amount : integer := 1;
axi_master_base_address : std_logic_vector := X"f0030000f0020000f0010000f000000000000000";
axi_master_high_address : std_logic_vector := X"f003fffff002fffff001fffff000ffffefffffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
ip_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_awlen : out std_logic_vector(7 downto 0);
ip_m_axi_awsize : out std_logic_vector(2 downto 0);
ip_m_axi_awburst : out std_logic_vector(1 downto 0);
ip_m_axi_awlock : out std_logic;
ip_m_axi_awcache : out std_logic_vector(3 downto 0);
ip_m_axi_awprot : out std_logic_vector(2 downto 0);
ip_m_axi_awqos : out std_logic_vector(3 downto 0);
ip_m_axi_awregion : out std_logic_vector(3 downto 0);
ip_m_axi_awvalid : out std_logic;
ip_m_axi_awready : in std_logic;
ip_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ip_m_axi_wlast : out std_logic;
ip_m_axi_wvalid : out std_logic;
ip_m_axi_wready : in std_logic;
ip_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_bresp : in std_logic_vector(1 downto 0);
ip_m_axi_bvalid : in std_logic;
ip_m_axi_bready : out std_logic;
ip_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_arlen : out std_logic_vector(7 downto 0);
ip_m_axi_arsize : out std_logic_vector(2 downto 0);
ip_m_axi_arburst : out std_logic_vector(1 downto 0);
ip_m_axi_arlock : out std_logic;
ip_m_axi_arcache : out std_logic_vector(3 downto 0);
ip_m_axi_arprot : out std_logic_vector(2 downto 0);
ip_m_axi_arqos : out std_logic_vector(3 downto 0);
ip_m_axi_arregion : out std_logic_vector(3 downto 0);
ip_m_axi_arvalid : out std_logic;
ip_m_axi_arready : in std_logic;
ip_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_rresp : in std_logic_vector(1 downto 0);
ip_m_axi_rlast : in std_logic;
ip_m_axi_rvalid : in std_logic;
ip_m_axi_rready : out std_logic;
cpuid_gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_awlock : out std_logic;
cpuid_gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awvalid : out std_logic;
cpuid_gpio_m_axi_awready : in std_logic;
cpuid_gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cpuid_gpio_m_axi_wlast : out std_logic;
cpuid_gpio_m_axi_wvalid : out std_logic;
cpuid_gpio_m_axi_wready : in std_logic;
cpuid_gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_bvalid : in std_logic;
cpuid_gpio_m_axi_bready : out std_logic;
cpuid_gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_arlock : out std_logic;
cpuid_gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arvalid : out std_logic;
cpuid_gpio_m_axi_arready : in std_logic;
cpuid_gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_rlast : in std_logic;
cpuid_gpio_m_axi_rvalid : in std_logic;
cpuid_gpio_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
signal_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_awlen : out std_logic_vector(7 downto 0);
signal_m_axi_awsize : out std_logic_vector(2 downto 0);
signal_m_axi_awburst : out std_logic_vector(1 downto 0);
signal_m_axi_awlock : out std_logic;
signal_m_axi_awcache : out std_logic_vector(3 downto 0);
signal_m_axi_awprot : out std_logic_vector(2 downto 0);
signal_m_axi_awqos : out std_logic_vector(3 downto 0);
signal_m_axi_awregion : out std_logic_vector(3 downto 0);
signal_m_axi_awvalid : out std_logic;
signal_m_axi_awready : in std_logic;
signal_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
signal_m_axi_wlast : out std_logic;
signal_m_axi_wvalid : out std_logic;
signal_m_axi_wready : in std_logic;
signal_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_bresp : in std_logic_vector(1 downto 0);
signal_m_axi_bvalid : in std_logic;
signal_m_axi_bready : out std_logic;
signal_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_arlen : out std_logic_vector(7 downto 0);
signal_m_axi_arsize : out std_logic_vector(2 downto 0);
signal_m_axi_arburst : out std_logic_vector(1 downto 0);
signal_m_axi_arlock : out std_logic;
signal_m_axi_arcache : out std_logic_vector(3 downto 0);
signal_m_axi_arprot : out std_logic_vector(2 downto 0);
signal_m_axi_arqos : out std_logic_vector(3 downto 0);
signal_m_axi_arregion : out std_logic_vector(3 downto 0);
signal_m_axi_arvalid : out std_logic;
signal_m_axi_arready : in std_logic;
signal_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_rresp : in std_logic_vector(1 downto 0);
signal_m_axi_rlast : in std_logic;
signal_m_axi_rvalid : in std_logic;
signal_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end component;
end;
package body plasoc_cpu_0_crossbar_wrap_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
mit
|
845e864779f96c7a66ba50b8ae92135d
| 0.677517 | 2.489597 | false | false | false | false |
Anding/DDR2_memory_interface
|
rtl/system/SDRAM_CTRL.vhd
| 1 | 6,031 |
-- DDR2 memory interface
-- Andrew Read, March 2016
-- This project is based on a working DDR2 interface very kindly donated by a friend
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_textio.all;
entity SDRAM_CTRL is
port (
CLK : in std_logic; -- 125MHz clock
CLK_130 : in std_logic; -- 125MHz clock 130 degree phase shift
reset : in std_logic;
wrrd_ba_add : in std_logic_vector(2 downto 0); -- bank address
wrrd_ras_add : in std_logic_vector(12 downto 0); -- row address
wrrd_cas_add : in std_logic_vector(8 downto 0); -- column address
-- this is technically a 16-bit word address but SDRAM_PHY ignores the least significant bit of the column address
-- so the address space is effectively 32-bit word addressable
wr_we : in std_logic_vector(3 downto 0);
wr_add : in std_logic_vector(25 downto 0); -- not used
wr_dat : in std_logic_vector(31 downto 0);
wr_ack : out std_logic;
rd_re : in std_logic;
rd_add : in std_logic_vector(25 downto 0); -- not used
rd_dat : out std_logic_vector(31 downto 0);
rd_ack : out std_logic;
rd_valid : out std_logic;
SDRAM_A : out std_logic_vector(13 downto 0);
SDRAM_BA : out std_logic_vector(2 downto 0);
SDRAM_CKE : out std_logic;
SDRAM_CK : out std_logic;
SDRAM_nCK : out std_logic;
SDRAM_DQ : inout std_logic_vector(15 downto 0);
SDRAM_DQS : inout std_logic_vector(1 downto 0);
--SDRAM_nDQS : inout std_logic_vector(1 downto 0);
SDRAM_DM : out std_logic_vector(1 downto 0);
SDRAM_nCAS : out std_logic;
SDRAM_nCS : out std_logic;
SDRAM_nRAS : out std_logic;
SDRAM_nWE : out std_logic);
end SDRAM_CTRL;
architecture Struct of SDRAM_CTRL is
component SDRAM_PHYIO is
port (
CLK : in std_logic;
CLK_130 : in std_logic;
reset : in std_logic;
wrrd_ba_add : in std_logic_vector(2 downto 0);
wrrd_ras_add : in std_logic_vector(12 downto 0);
wrrd_cas_add : in std_logic_vector(8 downto 0);
wr_we : in std_logic_vector(3 downto 0);
wr_add : in std_logic_vector(25 downto 0);
wr_dat : in std_logic_vector(31 downto 0);
wr_ack : out std_logic;
rd_re : in std_logic;
rd_add : in std_logic_vector(25 downto 0);
rd_dat : out std_logic_vector(31 downto 0);
rd_ack : out std_logic;
rd_valid : out std_logic;
refresh : in std_logic;
ref_ack : out std_logic;
SDRAM_A : out std_logic_vector(13 downto 0);
SDRAM_BA : out std_logic_vector(2 downto 0);
SDRAM_CKE : out std_logic;
SDRAM_CK : out std_logic;
SDRAM_nCK : out std_logic;
SDRAM_DQ : inout std_logic_vector(15 downto 0);
SDRAM_DQS : inout std_logic_vector(1 downto 0);
--SDRAM_nDQS : inout std_logic_vector(1 downto 0);
SDRAM_DM : out std_logic_vector(1 downto 0);
SDRAM_nCAS : out std_logic;
SDRAM_nCS : out std_logic;
SDRAM_nRAS : out std_logic;
SDRAM_nWE : out std_logic);
end component;
----------------------------------------------------
-- Refresh parameters
----------------------------------------------------
-- This module, SDRAM_CTRL, raises a refresh request each refreshInterval clock cycles
-- SDRAM_PHY issues refreshCount consecutive REFRESH commands in response to each refresh request
-- Each REFRESH command takes at least tRFC = 127.5 ns
-- The refresh period of the MT47H64M16HR-25E is 64ms, thus to comply with the specification
-- refreshInterval * ( refreshCount [defined in SDRAM_PHYIO.vhd] + 1 ) * clock_period <= 64ms
-- Example refresh strategies at 125MHz (based on a 7.2us clock period including allowance)
-- 1. Refresh the entire SDRAM once each 64ms, blocking the device for 1ms each time
-- constant refreshInterval : integer range 0 to 16777215 := 8888888;
-- constant refreshCount : integer range 0 to 8191 := 8191;
--
-- 2. Refresh the entire SDRAM once each 0.75ms, blocking the device for 12.5us each time
-- constant refreshInterval : integer range 0 to 16777215 := 54000;
-- constant refreshCount : integer range 0 to 8191 := 95;
--
-- 3. Refresh the SRDRAM once each 62.5us, blocking the device for 1us each time
-- constant refreshInterval : integer range 0 to 16777215 := 4500;
-- constant refreshCount : integer range 0 to 8191 := 7;
constant refreshInterval : integer range 0 to 16777215 := 4500; -- number of clock cycles between each refresh request
signal refresh_time_cnt : integer range 0 to 16777215;
signal refresh : std_logic;
signal ref_ack : std_logic;
begin
-----------------------------------------------------
-- Refresh Mechanism
-----------------------------------------------------
refresh_gen : process (CLK, reset)
begin
if (reset='1') then
refresh_time_cnt <= 0;
refresh <= '0';
elsif (CLK'event and CLK='1') then
-- free running timer/counter
if (refresh_time_cnt = refreshInterval) then
refresh_time_cnt <= 0;
else
refresh_time_cnt <= refresh_time_cnt + 1;
end if;
-- refresh request signal
if (refresh_time_cnt = refreshInterval) then
refresh <= '1';
elsif (ref_ack = '1') then
refresh <= '0';
end if;
end if;
end process;
-- instantiate SDRAM_PHYIO
SDRAM_PHYIOi : SDRAM_PHYIO
port map (
CLK => CLK,
CLK_130 => CLK_130,
reset => reset,
wrrd_ba_add => wrrd_ba_add,
wrrd_ras_add => wrrd_ras_add,
wrrd_cas_add => wrrd_cas_add,
wr_we => wr_we,
wr_add => wr_add,
wr_dat => wr_dat,
wr_ack => wr_ack,
rd_re => rd_re,
rd_add => rd_add,
rd_dat => rd_dat,
rd_ack => rd_ack,
rd_valid => rd_valid,
refresh => refresh,
ref_ack => ref_ack,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CK => SDRAM_CK,
SDRAM_nCK => SDRAM_nCK,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS,
--SDRAM_nDQS => SDRAM_nDQS,
SDRAM_DM => SDRAM_DM,
SDRAM_nCAS => SDRAM_nCAS,
SDRAM_nCS => SDRAM_nCS,
SDRAM_nRAS => SDRAM_nRAS,
SDRAM_nWE => SDRAM_nWE);
end Struct;
|
gpl-2.0
|
c70defb624f535754a7c6d41ee789db4
| 0.63041 | 3.091235 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/audioDac/ipcore_dir/counter.vhd
| 2 | 4,061 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file counter.vhd when simulating
-- the core, counter. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY counter IS
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(27 DOWNTO 0)
);
END counter;
ARCHITECTURE counter_a OF counter IS
-- synthesis translate_off
COMPONENT wrapped_counter
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(27 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_counter USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1110000110101110111111111111",
c_fb_latency => 0,
c_has_ce => 0,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 1,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 28,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_counter
PORT MAP (
clk => clk,
q => q
);
-- synthesis translate_on
END counter_a;
|
gpl-3.0
|
423d1251d6ca33ad23b64d7f9cfd0d8c
| 0.537306 | 4.800236 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/mandelbrot_iteration.vhd
| 1 | 2,901 |
--
-- Iteration of one run of the mandelbrot function
--
-- * data is stored in Q+2.15 (as the spartan 6 DSP blocks can do 18x18 multiplication)
-- * latency of 7 cycles
--
-- The pseudo-code for each iteration is:
-- xout = x*x - y*y + x0
-- yout = 2*x*y + y0
-- overflow = x*x + y*y > 2*2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity mandelbrot_iteration is port(
clk : in std_logic;
-- inputs
ov_in : in std_logic;
x,y,x0,y0 : in std_logic_vector (17 downto 0);
-- outputs
x_out,y_out,x0_out,y0_out : out std_logic_vector (17 downto 0);
ov : out std_logic);
end mandelbrot_iteration;
architecture Behavioral of mandelbrot_iteration is
component multiplier port (
clk: in std_logic;
ar,ai,br,bi: in std_logic_vector(17 downto 0); -- Q+2.15
pr,pi: out std_logic_vector(21 downto 0)); -- Q+6.15
end component;
-- local signals
signal mulx,muly: std_logic_vector(17 downto 0);
signal px,py: std_logic_vector (21 downto 0); -- Q+6.15
signal ov_x,ov_y : std_logic;
constant escape : signed (18 downto 0) := to_signed(+2*(2**15),19); -- Q+3.15
-- pipeline signals
signal x_1,x0_1,x0_2,x0_3,x0_4,x0_5,x0_6,x0_7 :std_logic_vector(17 downto 0):=(others =>'0');
signal y_1,y0_1,y0_2,y0_3,y0_4,y0_5,y0_6,y0_7 :std_logic_vector(17 downto 0):=(others =>'0');
signal ov_in_1,ov_in_2,ov_in_3,ov_in_4,ov_in_5,ov_in_6,ov_in_7 : std_logic :='0';
signal sumx_6,sumy_6 : signed (18 downto 0):=(others =>'0'); -- Q+3.15
begin
-- overflow check per channel
ov_x <= '1' when sumx_6 > escape else '1' when sumx_6 < -escape else '0';
ov_y <= '1' when sumy_6 > escape else '1' when sumy_6 < -escape else '0';
mul1 : multiplier port map ( -- latency of 4 clock
clk => clk,
ar => mulx, ai => muly, br => mulx, bi => muly,
pr => px, pi => py
);
processing_pipeline :process (clk) begin
if rising_edge(clk) then
-- cycle 1 - receive
ov_in_1 <= ov_in;
x0_1 <= x0; y0_1 <= y0;
x_1 <= x; y_1 <= y;
mulx <= x_1; muly <= y_1;
-- cycle 2 - multiply1
ov_in_2 <= ov_in_1;
x0_2 <= x0_1; y0_2 <= y0_1;
-- cycle 3 - multiply2
ov_in_3 <= ov_in_2;
x0_3 <= x0_2; y0_3 <= y0_2;
-- cycle 4 - multiply3
ov_in_4 <= ov_in_3;
x0_4 <= x0_3; y0_4 <= y0_3;
-- cycle 5 - multiply4
ov_in_5 <= ov_in_4;
x0_5 <= x0_4; y0_5 <= y0_4;
-- cycle 6 - sum
x0_6<= x0_5; y0_6 <= y0_5;
ov_in_6 <= ov_in_5;
sumx_6 <= signed(px(18 downto 0)) + signed(x0_6(17) & x0_6); -- extended x0 to Q+3.15
sumy_6 <= signed(py(18 downto 0)) + signed(y0_6(17) & y0_6);
-- cycle 7 - overflow check / output
x0_7<= x0_6; y0_7 <= y0_6;
ov_in_7 <= ov_in_6;
x0_out<= x0_7;y0_out<= y0_7;
x_out <= std_logic_vector(sumx_6(17 downto 0)); -- constrain to Q+2.15
y_out <= std_logic_vector(sumy_6(17 downto 0));
ov <= ov_x or ov_y or ov_in_7;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
f7b138425ffd8eda736eaea22366c7c1
| 0.588073 | 2.254079 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
int_ctrl.vhd
| 1 | 2,579 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity int_ctrl is
port (
rst : in std_logic;
clk : in std_logic;
-- Avalon-MM slave
avls_address : in std_logic_vector(12 downto 0);
avls_byteenable : in std_logic_vector(3 downto 0);
avls_writedata : in std_logic_vector(31 downto 0);
avls_write : in std_logic;
avls_readdata : out std_logic_vector(31 downto 0);
avls_read : in std_logic;
avls_waitrequest : out std_logic;
avls_irq : out std_logic;
-- Avalon-MM master
avlm_address : out std_logic_vector(14 downto 0);
avlm_byteenable : out std_logic_vector(3 downto 0);
avlm_writedata : out std_logic_vector(31 downto 0);
avlm_write : out std_logic;
avlm_readdata : in std_logic_vector(31 downto 0);
avlm_read : out std_logic;
avlm_waitrequest : in std_logic;
avlm_irq : in std_logic_vector(15 downto 0);
-- control registers port
address : in std_logic_vector(1 downto 0);
byteenable : in std_logic_vector(1 downto 0);
writedata : in std_logic_vector(15 downto 0);
write : in std_logic;
readdata : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of int_ctrl is
constant REG_ISR : std_logic_vector(address'range) := "00";
constant REG_ISR_MASKED : std_logic_vector(address'range) := "01";
constant REG_IMASK_SET : std_logic_vector(address'range) := "10";
constant REG_IMASK_CLEAR : std_logic_vector(address'range) := "11";
signal imask : std_logic_vector(15 downto 0);
signal irq_masked : std_logic_vector(15 downto 0);
signal irq_status : std_logic_vector(15 downto 0);
begin
irq_masked <= avlm_irq and imask;
irq_status <= avlm_irq;
process (rst, clk)
begin
if rising_edge(clk) then
for i in imask'range loop
if address(1) and write and byteenable(i / 8) and writedata(i) then
imask(i) <= not address(0);
end if;
end loop;
end if;
if rst then
imask <= (others => '0');
end if;
end process;
with address select
readdata <= irq_status when REG_ISR,
irq_masked when REG_ISR_MASKED,
imask when others;
avls_irq <= '0' when unsigned(irq_masked) = 0 else '1';
avlm_address <= avls_address & "00";
avlm_byteenable <= avls_byteenable;
avlm_writedata <= avls_writedata;
avlm_write <= avls_write;
avls_readdata <= avlm_readdata;
avlm_read <= avls_read;
avls_waitrequest <= avlm_waitrequest;
end architecture;
|
gpl-3.0
|
a35b90e6d2e4c7bdf351f4e682bdeb42
| 0.676619 | 2.859202 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
testbench/ci_bridge_tb.vhd
| 1 | 4,475 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity ci_bridge_tb is
end;
architecture sym of ci_bridge_tb is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal address : std_logic_vector(14 downto 0) := (others => '0');
signal byteenable : std_logic_vector(7 downto 0) := (others => '0');
signal writedata : std_logic_vector(63 downto 0) := (others => '0');
signal write : std_logic := '0';
signal readdata : std_logic_vector(63 downto 0);
signal read : std_logic := '0';
signal waitrequest : std_logic;
signal cam_address : std_logic_vector(17 downto 0);
signal cam_writedata : std_logic_vector(7 downto 0);
signal cam_write : std_logic;
signal cam_readdata : std_logic_vector(7 downto 0);
signal cam_read : std_logic;
signal cam_waitreq : std_logic;
signal cia_ce_n : std_logic;
signal cib_ce_n : std_logic;
signal ci_reg_n : std_logic;
signal ci_a : std_logic_vector(14 downto 0);
signal ci_d_out : std_logic_vector(7 downto 0);
signal ci_d_out_en : std_logic;
signal ci_we_n : std_logic;
signal ci_oe_n : std_logic;
signal ci_iowr_n : std_logic;
signal ci_iord_n : std_logic;
signal cia_wait_n : std_logic := '1';
signal cib_wait_n : std_logic := '1';
signal cia_data_buf_oe_n : std_logic;
signal cib_data_buf_oe_n : std_logic;
signal ci_bus_dir : std_logic;
signal cia_data : std_logic_vector(7 downto 0) := (others => 'Z');
signal cib_data : std_logic_vector(7 downto 0) := (others => 'Z');
signal ci_data : std_logic_vector(7 downto 0) := (others => 'Z');
begin
cia_data <= (others => 'L') when cia_data_buf_oe_n or ci_bus_dir else ci_data;
cib_data <= (others => 'H') when cib_data_buf_oe_n or ci_bus_dir else ci_data;
ci_data <= ci_d_out when ci_d_out_en else
cia_data when not cia_data_buf_oe_n and ci_bus_dir else
cib_data when not cib_data_buf_oe_n and ci_bus_dir else
(others => 'Z');
ADAPTER_0 : entity work.avalon64_to_avalon8
generic map(
OUT_ADDR_WIDTH => 18
)
port map (
rst => rst,
clk => clk,
address => address,
byteenable => byteenable,
writedata => writedata,
write => write,
readdata => readdata,
read => read,
waitrequest => waitrequest,
out_address => cam_address,
out_writedata => cam_writedata,
out_write => cam_write,
out_readdata => cam_readdata,
out_read => cam_read,
out_waitrequest => cam_waitreq
);
BRIDGE_0 : entity work.ci_bridge
port map (
clk => clk,
rst => rst,
address => (others => '0'),
byteenable => (others => '0'),
writedata => (others => '0'),
write => '0',
readdata => open,
interrupt => open,
cam_address => cam_address,
cam_writedata => cam_writedata,
cam_write => cam_write,
cam_readdata => cam_readdata,
cam_read => cam_read,
cam_waitreq => cam_waitreq,
cam_interrupts => open,
cia_reset => open,
cib_reset => open,
cia_ce_n => cia_ce_n,
cib_ce_n => cib_ce_n,
ci_reg_n => ci_reg_n,
ci_a => ci_a,
ci_d_in => ci_data,
ci_d_out => ci_d_out,
ci_d_en => ci_d_out_en,
ci_we_n => ci_we_n,
ci_oe_n => ci_oe_n,
ci_iowr_n => ci_iowr_n,
ci_iord_n => ci_iord_n,
cia_wait_n => cia_wait_n,
cib_wait_n => cib_wait_n,
cia_ireq_n => '1',
cib_ireq_n => '1',
cia_cd_n => "00",
cib_cd_n => "00",
cia_overcurrent_n => '1',
cib_overcurrent_n => '1',
cia_reset_buf_oe_n => open,
cib_reset_buf_oe_n => open,
cia_data_buf_oe_n => cia_data_buf_oe_n,
cib_data_buf_oe_n => cib_data_buf_oe_n,
ci_bus_dir => ci_bus_dir
);
process
begin
wait for 8 ns;
clk <= not clk;
end process;
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
--
wait until rising_edge(clk);
address <= std_logic_vector(to_unsigned(0, 15));
byteenable <= "11111111";
read <= '1';
wait until rising_edge(clk) and waitrequest = '0';
--
address <= std_logic_vector(to_unsigned(2, 15));
byteenable <= "00110000";
read <= '1';
wait until rising_edge(clk) and waitrequest = '0';
read <= '0';
--
wait until rising_edge(clk);
--
wait;
end process;
end;
|
gpl-3.0
|
af1361f8c63851d5018dbe301b01fb54
| 0.605363 | 2.481974 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dma_arbiter.vhd
| 1 | 3,136 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dma_arbiter is
generic (
MEM_ADDR_WIDTH : natural := 31
);
port (
rst : in std_logic;
clk : in std_logic;
-- dma port #0
dma0_addr : in std_logic_vector(63 downto 3);
dma0_byteen : in std_logic_vector(7 downto 0);
dma0_size : in std_logic_vector(6 downto 0);
dma0_wrdata : in std_logic_vector(63 downto 0);
dma0_write : in std_logic;
dma0_wait : out std_logic;
-- dma port #1
dma1_addr : in std_logic_vector(63 downto 3);
dma1_byteen : in std_logic_vector(7 downto 0);
dma1_size : in std_logic_vector(6 downto 0);
dma1_wrdata : in std_logic_vector(63 downto 0);
dma1_write : in std_logic;
dma1_wait : out std_logic;
-- memory port
mem_addr : out std_logic_vector(MEM_ADDR_WIDTH - 1 downto 0);
mem_byteen : out std_logic_vector(7 downto 0);
mem_size : out std_logic_vector(6 downto 0);
mem_wrdata : out std_logic_vector(63 downto 0);
mem_write : out std_logic;
mem_waitreq : in std_logic
);
end;
architecture rtl of dma_arbiter is
signal burst_cnt : signed(mem_size'left + 1 downto 0);
signal mem_addr_i : std_logic_vector(63 downto 3);
signal secondary : std_logic;
signal dma0_grant : std_logic;
signal dma1_grant : std_logic;
alias burst : std_logic is burst_cnt(burst_cnt'left);
begin
dma0_grant <= burst and not secondary;
dma1_grant <= burst and secondary;
dma0_wait <= mem_waitreq or not dma0_grant;
dma1_wait <= mem_waitreq or not dma1_grant;
mem_wrdata <= (dma0_wrdata and (dma0_wrdata'range => dma0_grant)) or (dma1_wrdata and (dma1_wrdata'range => dma1_grant));
mem_write <= (dma0_write and dma0_grant) or (dma1_write and dma1_grant);
mem_size <= (dma0_size and (dma0_size'range => dma0_grant)) or (dma1_size and (dma1_size'range => dma1_grant));
mem_addr_i <= (dma0_addr and (dma0_addr'range => dma0_grant)) or (dma1_addr and (dma1_addr'range => dma1_grant));
mem_byteen <= (dma0_byteen and (dma0_byteen'range => dma0_grant)) or (dma1_byteen and (dma1_byteen'range => dma1_grant));
mem_addr <= mem_addr_i(mem_addr'left downto 3) & "000";
process (rst, clk)
variable burst_step : std_logic;
variable burst_en0 : std_logic;
variable burst_en1 : std_logic;
begin
if rising_edge(clk) then
burst_step := burst and ((dma0_write and not secondary) or (dma1_write and secondary)) and not mem_waitreq;
burst_en0 := not burst and dma0_write and (not dma1_write or secondary);
burst_en1 := not burst and dma1_write and (dma0_write nand secondary);
--
if burst_en0 then
burst_cnt <= signed('1' & not dma0_size) + 1;
elsif burst_en1 then
burst_cnt <= signed('1' & not dma1_size) + 1;
elsif burst_step then
burst_cnt <= burst_cnt + 1;
end if;
--
if burst_en1 then
secondary <= '1';
elsif burst_en0 then
secondary <= '0';
end if;
end if;
if rst then
burst_cnt <= (others => '0');
secondary <= '0';
end if;
end process;
end;
|
gpl-3.0
|
9fc118eb675edc9e3f98694e37b77a26
| 0.665816 | 2.694158 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/4/projetos/projeto1/projeto1.vhd
| 1 | 619 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto1 is
port (
e : in std_logic_vector (3 downto 0):= "0100";
s: out std_logic_vector (6 downto 0)
);
end projeto1;
architecture Behavioral of projeto1 is
begin
-- Alteração feita para relatório.
s <= "1111110" when e = "0000" else
"0110000" when e = "0001" else
"1101101" when e = "0010" else
"1111001" when e = "0011" else
"0110010" when e = "0100" else
"1011010" when e = "0101" else
"1011111" when e = "0110" else
"1110000" when e = "0111" else
"1111111" when e = "1000" else
"1111011" when e = "1001";
end Behavioral;
|
mit
|
6a278db15e13b2b1055b23667cc703f3
| 0.641234 | 2.975845 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/FunctionGenerator.vhd
| 1 | 5,389 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Creates sine, square, triangle, and sawtooth function values from an exter-
-- nally supplied phase value (i.e. no time-related signal is generated here).
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FunctionGenerator_Declarations.all;
entity FunctionGenerator is
generic
(
-- The width of the phase values.
phase_width: natural := 32;
-- The width of the phase values of the waveform lookup table (must not
-- exceed phase_width).
lookup_table_phase_width: natural := 12;
-- The width of the sample values.
sample_width: natural := 16
);
port
(
-- The system clock.
clk: in std_logic;
-- The configuration (e.g. waveforms).
config: in generator_config;
-- The current phase value.
phase: in unsigned (phase_width-1 downto 0);
-- The sample value according to the current phase.
sample: out signed (sample_width-1 downto 0) := (others => '0')
);
end entity;
architecture stdarch of FunctionGenerator is
type reg_type is record
sample: signed(sample_width-1 downto 0);
end record;
signal state, next_state: reg_type :=
(
sample => (others => '0')
);
signal lookup_sample: signed (sample_width-1 downto 0);
begin
--------------------------------------------------------------------------------
-- Component instantiation.
--------------------------------------------------------------------------------
lookup_table: entity work.LookupTableContainer
generic map
(
phase_width => lookup_table_phase_width,
sample_width => sample_width
)
port map
(
clk => clk,
phase => phase(phase'left downto phase_width-lookup_table_phase_width),
sample => lookup_sample
);
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, config, phase) is
constant width_difference: integer := sample_width - phase_width;
begin
-- Defaults.
next_state <= state;
-- Create the next sample according to the selected waveform. Note that
-- the sample is signed and thus uses two´s complement. Samples read from
-- a lookup table are not handled here.
case config.waveform is
when waveform_square =>
-- Derive the square signal from the phase´s MSB.
next_state.sample(next_state.sample'high) <= phase(phase'high);
next_state.sample(next_state.sample'high-1 downto 0) <= (others => not phase(phase'high));
when waveform_sawtooth =>
-- Derive the sawtooth signal from the phase (pad or truncate LSBs
-- when widths are different).
next_state.sample <= (others => '0');
if (width_difference >= 0) then
next_state.sample(next_state.sample'high downto width_difference) <= signed(phase);
else
next_state.sample <= signed(phase(phase'high downto -width_difference));
end if;
when others =>
end case;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
select_sample: process(state.sample, lookup_sample) is
begin
sample <= state.sample;
-- Select whether to use samples created here or those read from a lookup
-- table.
if config.waveform = waveform_sine then
sample <= lookup_sample;
end if;
end process;
end architecture;
|
gpl-3.0
|
4bbe7701cb79e23056f99f7dcd1e560b
| 0.488031 | 5.325099 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/pixel_gen.vhd
| 1 | 2,266 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pixel_gen is port (
clk : in std_logic;
x0,y0 : in std_logic_vector(17 downto 0);
overflow_bits : out std_logic_vector(19 downto 0));
end pixel_gen;
architecture Behavioral of pixel_gen is
type pipe_state is (s1,s2,s3);
signal state : pipe_state := s1;
component mandelbrot_pipeline4 port(
clk : IN std_logic;
ov_in : in std_logic;
x,y,x0,y0 : IN std_logic_vector(17 downto 0);
x_out,y_out,x0_out,y0_out : OUT std_logic_vector(17 downto 0);
ov : out std_logic_vector (3 downto 0));
end component;
signal x_in,y_in,x0_in,y0_in : std_logic_vector(17 downto 0);
signal x_out,y_out,x0_out,y0_out : std_logic_vector(17 downto 0);
signal ov_in : std_logic;
signal ov_out : std_logic_vector (3 downto 0);
-- latches
signal x_out1, y_out1, x0_out1, y0_out1 : std_logic_vector(17 downto 0);
signal x_out2, y_out2, x0_out2, y0_out2 : std_logic_vector(17 downto 0);
signal x_out3, y_out3, x0_out3, y0_out3 : std_logic_vector(17 downto 0);
signal x_out4, y_out4, x0_out4, y0_out4 : std_logic_vector(17 downto 0);
signal ov1, ov2, ov3, ov4 : std_logic_vector (3 downto 0);
signal overflow : std_logic_vector (19 downto 0);
begin
overflow_bits <= overflow;
pipeline : mandelbrot_pipeline4 port map(
clk => clk,
ov_in => ov_in,
x => x_in, y => y_in, x0 => x0_in, y0 => y0_in, -- inputs
x_out => x_out, y_out => y_out, ov => ov_out, -- outputs
x0_out=> x0_out, y0_out => y0_out
);
piped : process (clk) begin
if rising_edge(clk) then
case state is
when s1 =>
x_in <= x0; y_in <= y0; x0_in <= x0; y0_in <= y0; ov_in <= '0';
x_out1 <= x_out; y_out1 <= y_out; x0_out1 <= x0_out; y0_out1 <= y0_out;
ov1 <= ov_out;
state <= s2;
when s2 =>
x_in <= x_out1; y_in <= y_out1; x0_in <= x0_out1; y0_in <= y0_out1; ov_in <= ov1(0);
x_out2<= x_out; y_out2 <= y_out; x0_out2 <= x0_out;y0_out2 <= y0_out;
ov2 <= ov_out;
state <= s3;
when s3 =>
x_in <= x_out2; y_in <= y_out2; x0_in <= x0_out2; y0_in <= y0_out2; ov_in <= ov2(0);
overflow <= ov1 & ov2 & ov_out & x"00";
state <= s1;
end case;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
21bb6ed4e3ee42e4943059c1d8c6a7e6
| 0.59797 | 2.331276 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/3/projetos/somadorSubtrator.vhd
| 1 | 1,422 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity somadorSubtrator is
Port ( a0 : in STD_LOGIC;
a1 : in STD_LOGIC;
a2 : in STD_LOGIC;
b0 : in STD_LOGIC;
b1 : in STD_LOGIC;
b2 : in STD_LOGIC;
sel : in STD_LOGIC;
s0 : out STD_LOGIC;
s1 : out STD_LOGIC;
s2 : out STD_LOGIC;
cout0 : out STD_LOGIC;
cout1 : out STD_LOGIC;
E : out STD_LOGIC);
end somadorSubtrator;
architecture Behavioral of somadorSubtrator is
signal caux : std_logic;
signal comp0 : std_logic;
signal comp1 : std_logic;
signal comp2 : std_logic;
signal compdois0 : std_logic;
signal compdois1 : std_logic;
signal compdois2 : std_logic;
begin
process (a0,a1,a2,b0,b1,b2, sel)
begin
if (sel = '0') then
--soma
if (a2 = '0') and (b2 = '0') then
s0 <= (a0 xor (b0 xor '0'));
caux <= a0 and b0;
s1 <= (a1 xor (b1 xor caux));
cout1 <= (a0 and b0) or (a0 and caux) or (b0 and caux);
s2 <= a2;
elsif (a2 = '1') then
-- a é negativo
comp0 = (a0 xor '1');
comp1 = (a1 xor '1');
comp2 = (a2 xor '1');
compdois0 <= (a0 xor '1');
caux <= a0 and '1';
compdois1 <= (a1 xor ('1' xor caux));
cout1 <= (a0 and '1') or (a0 and caux) or ('1' and caux);
s2 <= a2;
elsif (b2 = '1') then
-- b é negativo
end if;
else
--subtrai
end if;
end process;
end Behavioral;
|
mit
|
4378928a03f19050a5b05b9cf102d169
| 0.547183 | 2.544803 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/numeric_std-body.vhd
| 7 | 83,076 |
-- --------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_STD)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_STD. The NUMERIC_STD package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
--
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- Version: 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
--==============================================================================
--============================= Package Body ===================================
--==============================================================================
package body NUMERIC_STD is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: STD_LOGIC) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: STD_LOGIC) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
-----------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
-----------------Local Subprograms - Relational ops---------------------------
--
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) = STD_LOGIC_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) = STD_LOGIC_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) < STD_LOGIC_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_LOGIC_VECTOR(INTERN_L) < STD_LOGIC_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) <= STD_LOGIC_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_LOGIC_VECTOR(INTERN_L) <= STD_LOGIC_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--=========================Exported Functions ==========================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := TO_01(XARG, 'X');
if (RESULT(RESULT'LEFT)='X') then return RESULT;
end if;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT, XARG01 : SIGNED(ARG_LEFT downto 0);
variable CBIT: STD_LOGIC := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
XARG01 := TO_01(ARG, 'X');
if (XARG01(XARG01'LEFT)='X') then return XARG01;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG01(I)) xor CBIT;
CBIT := CBIT and not(XARG01(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_UNSIGNED(L01, R01, '0');
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_SIGNED(L01, R01, '0');
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_UNSIGNED(L01, not(R01), '1');
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_SIGNED(L01, not(R01), '1');
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) :=
(others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := TO_01(L, 'X');
XR := TO_01(R, 'X');
if ((XL(L_LEFT)='X') or (XR(R_LEFT)='X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FQUOT := (others => 'X');
return FQUOT;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: SIGNED(L_LEFT downto 0) is L;
alias XXR: SIGNED(R_LEFT downto 0) is R;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FQUOT := (others => 'X');
return SIGNED(FQUOT);
end if;
if XL(XL'LEFT)='1' then
XNUM := UNSIGNED(-XL);
QNEG := TRUE;
else
XNUM := UNSIGNED(XL);
end if;
if XR(XR'LEFT)='1' then
XDENOM := UNSIGNED(-XR);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(0)/='X'
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(0)/='X'
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: SIGNED(L_LEFT downto 0) is L;
alias XXR: SIGNED(R_LEFT downto 0) is R;
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
XNUM := UNSIGNED(TO_01(XXL, 'X'));
XDENOM := UNSIGNED(TO_01(XXR, 'X'));
if ((XNUM(XNUM'LEFT)='X') or (XDENOM(XDENOM'LEFT)='X')) then
FREMAIN := (others => 'X');
return SIGNED(FREMAIN);
end if;
if XNUM(XNUM'LEFT)='1' then
XNUM := UNSIGNED(-SIGNED(XNUM));
RNEG := TRUE;
else
XNUM := UNSIGNED(XNUM);
end if;
if XDENOM(XDENOM'LEFT)='1' then
XDENOM := UNSIGNED(-SIGNED(XDENOM));
else
XDENOM := UNSIGNED(XDENOM);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := L rem XR;
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := XL rem R;
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: SIGNED(L_LEFT downto 0) is L;
alias XXR: SIGNED(R_LEFT downto 0) is R;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FREMAIN := (others => 'X');
return SIGNED(FREMAIN);
end if;
if XL(XL'LEFT)='1' then
XNUM := UNSIGNED(-XL);
else
XNUM := UNSIGNED(XL);
end if;
if XR(XR'LEFT)='1' then
XDENOM := UNSIGNED(-XR);
RNEG := TRUE;
else
XDENOM := UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'LENGTH), R01);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R01'LENGTH), R01);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R01'LENGTH), R01);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L01, TO_SIGNED(R, L01'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'LENGTH), R01);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'LENGTH), R01);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R01'LENGTH), R01);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L01, TO_SIGNED(R, L01'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R01'LENGTH), R01);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R01'LENGTH), R01));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
--START-V93
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--END-V93
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XXARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable XARG: UNSIGNED(ARG_LEFT downto 0);
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
XARG := TO_01(XXARG, 'X');
if (XARG(XARG'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
variable XARG: SIGNED(ARG'LENGTH-1 downto 0);
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
XARG := TO_01(ARG, 'X');
if (XARG(XARG'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity WARNING;
return 0;
end if;
if XARG(XARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(XARG));
else
return (- (TO_INTEGER(UNSIGNED(- (XARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: STD_LOGIC := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_STD.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(STD_LOGIC_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(STD_LOGIC_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
--============================================================================
-- support constants for STD_MATCH:
type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN;
constant MATCH_TABLE: BOOLEAN_TABLE := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | U |
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | X |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | 0 |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | 1 |
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | Z |
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | W |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | L |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | H |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE) -- | - |
);
-- Id: M.1
function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN is
variable VALUE: STD_ULOGIC;
begin
return MATCH_TABLE(L, R);
end STD_MATCH;
-- Id: M.2
function STD_MATCH (L, R: UNSIGNED) return BOOLEAN is
alias LV: UNSIGNED(1 to L'LENGTH) is L;
alias RV: UNSIGNED(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
-- Id: M.3
function STD_MATCH (L, R: SIGNED) return BOOLEAN is
alias LV: SIGNED(1 to L'LENGTH) is L;
alias RV: SIGNED(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
-- Id: M.4
function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN is
alias LV: STD_LOGIC_VECTOR(1 to L'LENGTH) is L;
alias RV: STD_LOGIC_VECTOR(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
-- Id: M.5
function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN is
alias LV: STD_ULOGIC_VECTOR(1 to L'LENGTH) is L;
alias RV: STD_ULOGIC_VECTOR(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED is
variable RESULT: UNSIGNED(S'LENGTH-1 downto 0);
variable BAD_ELEMENT: BOOLEAN := FALSE;
alias XS: UNSIGNED(S'LENGTH-1 downto 0) is S;
begin
if (S'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAU"
severity WARNING;
return NAU;
end if;
for I in RESULT'RANGE loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := TRUE;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'RANGE loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end TO_01;
-- Id: T.2
function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED is
variable RESULT: SIGNED(S'LENGTH-1 downto 0);
variable BAD_ELEMENT: BOOLEAN := FALSE;
alias XS: SIGNED(S'LENGTH-1 downto 0) is S;
begin
if (S'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAS"
severity WARNING;
return NAS;
end if;
for I in RESULT'RANGE loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := TRUE;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'RANGE loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end TO_01;
--============================================================================
end NUMERIC_STD;
|
mit
|
86db40bcdb14dd17216b01bdef2cc3eb
| 0.57061 | 3.631738 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
pcie_compiler_0_core.vhd
| 1 | 45,150 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- Generated by IP Compiler for PCI Express 11.1 [Altera, IP Toolbench 1.3.0 Build 259]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2014 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY pcie_compiler_0_core IS
PORT (
AvlClk_i : IN STD_LOGIC;
CraAddress_i : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
CraByteEnable_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CraChipSelect_i : IN STD_LOGIC;
CraRead : IN STD_LOGIC;
CraWrite : IN STD_LOGIC;
CraWriteData_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
Rstn_i : IN STD_LOGIC;
RxmIrqNum_i : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
RxmIrq_i : IN STD_LOGIC;
RxmReadDataValid_i : IN STD_LOGIC;
RxmReadData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
RxmWaitRequest_i : IN STD_LOGIC;
TxsAddress_i : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
TxsBurstCount_i : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
TxsByteEnable_i : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
TxsChipSelect_i : IN STD_LOGIC;
TxsRead_i : IN STD_LOGIC;
TxsWriteData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
TxsWrite_i : IN STD_LOGIC;
aer_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
app_int_sts : IN STD_LOGIC;
app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
app_msi_req : IN STD_LOGIC;
app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
core_clk_in : IN STD_LOGIC;
cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
cpl_pending : IN STD_LOGIC;
crst : IN STD_LOGIC;
hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
lmi_rden : IN STD_LOGIC;
lmi_wren : IN STD_LOGIC;
npor : IN STD_LOGIC;
pclk_central : IN STD_LOGIC;
pclk_ch0 : IN STD_LOGIC;
pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
pld_clk : IN STD_LOGIC;
pll_fixed_clk : IN STD_LOGIC;
pm_auxpwr : IN STD_LOGIC;
pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
pm_event : IN STD_LOGIC;
pme_to_cr : IN STD_LOGIC;
rc_areset : IN STD_LOGIC;
rc_inclk_eq_125mhz : IN STD_LOGIC;
rc_pll_locked : IN STD_LOGIC;
rc_rx_pll_locked_one : IN STD_LOGIC;
rx_st_mask0 : IN STD_LOGIC;
rx_st_ready0 : IN STD_LOGIC;
srst : IN STD_LOGIC;
test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_data0_p1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_eop0 : IN STD_LOGIC;
tx_st_eop0_p1 : IN STD_LOGIC;
tx_st_err0 : IN STD_LOGIC;
tx_st_sop0 : IN STD_LOGIC;
tx_st_sop0_p1 : IN STD_LOGIC;
tx_st_valid0 : IN STD_LOGIC;
phystatus0_ext : IN STD_LOGIC;
rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak0_ext : IN STD_LOGIC;
rxelecidle0_ext : IN STD_LOGIC;
rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid0_ext : IN STD_LOGIC;
CraIrq_o : OUT STD_LOGIC;
CraReadData_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
CraWaitRequest_o : OUT STD_LOGIC;
RxmAddress_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
RxmBurstCount_o : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
RxmByteEnable_o : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
RxmRead_o : OUT STD_LOGIC;
RxmWriteData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
RxmWrite_o : OUT STD_LOGIC;
TxsReadDataValid_o : OUT STD_LOGIC;
TxsReadData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
TxsWaitRequest_o : OUT STD_LOGIC;
app_int_ack : OUT STD_LOGIC;
app_msi_ack : OUT STD_LOGIC;
avs_pcie_reconfig_readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
avs_pcie_reconfig_readdatavalid : OUT STD_LOGIC;
avs_pcie_reconfig_waitrequest : OUT STD_LOGIC;
core_clk_out : OUT STD_LOGIC;
derr_cor_ext_rcv0 : OUT STD_LOGIC;
derr_cor_ext_rpl : OUT STD_LOGIC;
derr_rpl : OUT STD_LOGIC;
dl_ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
dlup_exit : OUT STD_LOGIC;
eidle_infer_sel : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
ev_128ns : OUT STD_LOGIC;
ev_1us : OUT STD_LOGIC;
hip_extraclkout : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
hotrst_exit : OUT STD_LOGIC;
int_status : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
l2_exit : OUT STD_LOGIC;
lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
lmi_ack : OUT STD_LOGIC;
lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
npd_alloc_1cred_vc0 : OUT STD_LOGIC;
npd_cred_vio_vc0 : OUT STD_LOGIC;
nph_alloc_1cred_vc0 : OUT STD_LOGIC;
nph_cred_vio_vc0 : OUT STD_LOGIC;
pme_to_sr : OUT STD_LOGIC;
r2c_err0 : OUT STD_LOGIC;
rate_ext : OUT STD_LOGIC;
rc_gxb_powerdown : OUT STD_LOGIC;
rc_rx_analogreset : OUT STD_LOGIC;
rc_rx_digitalreset : OUT STD_LOGIC;
rc_tx_digitalreset : OUT STD_LOGIC;
reset_status : OUT STD_LOGIC;
rx_fifo_empty0 : OUT STD_LOGIC;
rx_fifo_full0 : OUT STD_LOGIC;
rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be0_p1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_data0_p1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_eop0 : OUT STD_LOGIC;
rx_st_eop0_p1 : OUT STD_LOGIC;
rx_st_err0 : OUT STD_LOGIC;
rx_st_sop0 : OUT STD_LOGIC;
rx_st_sop0_p1 : OUT STD_LOGIC;
rx_st_valid0 : OUT STD_LOGIC;
serr_out : OUT STD_LOGIC;
suc_spd_neg : OUT STD_LOGIC;
swdn_wake : OUT STD_LOGIC;
swup_hotrst : OUT STD_LOGIC;
test_out : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
tl_cfg_ctl_wr : OUT STD_LOGIC;
tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
tl_cfg_sts_wr : OUT STD_LOGIC;
tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
tx_deemph : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
tx_fifo_empty0 : OUT STD_LOGIC;
tx_fifo_full0 : OUT STD_LOGIC;
tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_margin : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
tx_st_ready0 : OUT STD_LOGIC;
use_pcie_reconfig : OUT STD_LOGIC;
wake_oen : OUT STD_LOGIC;
powerdown0_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity0_ext : OUT STD_LOGIC;
txcompl0_ext : OUT STD_LOGIC;
txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak0_ext : OUT STD_LOGIC;
txdetectrx0_ext : OUT STD_LOGIC;
txelecidle0_ext : OUT STD_LOGIC
);
END pcie_compiler_0_core;
ARCHITECTURE SYN OF pcie_compiler_0_core IS
SIGNAL signal_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire1 : STD_LOGIC;
SIGNAL signal_wire2 : STD_LOGIC;
SIGNAL signal_wire3 : STD_LOGIC;
SIGNAL signal_wire4 : STD_LOGIC;
SIGNAL signal_wire5 : STD_LOGIC;
SIGNAL signal_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL signal_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL signal_wire8 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire9 : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL signal_wire10 : STD_LOGIC;
SIGNAL signal_wire11 : STD_LOGIC;
SIGNAL signal_wire12 : STD_LOGIC;
SIGNAL signal_wire13 : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL signal_wire14 : STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL signal_wire15 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire16 : STD_LOGIC;
SIGNAL signal_wire17 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire18 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL signal_wire19 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL signal_wire20 : STD_LOGIC;
SIGNAL signal_wire21 : STD_LOGIC;
SIGNAL signal_wire22 : STD_LOGIC;
SIGNAL signal_wire23 : STD_LOGIC;
SIGNAL signal_wire24 : STD_LOGIC;
SIGNAL signal_wire25 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire26 : STD_LOGIC;
SIGNAL signal_wire27 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL signal_wire28 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire29 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL signal_wire30 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire31 : STD_LOGIC;
SIGNAL signal_wire32 : STD_LOGIC;
SIGNAL signal_wire33 : STD_LOGIC_VECTOR (63 DOWNTO 0);
SIGNAL signal_wire34 : STD_LOGIC_VECTOR (63 DOWNTO 0);
SIGNAL signal_wire35 : STD_LOGIC;
SIGNAL signal_wire36 : STD_LOGIC;
SIGNAL signal_wire37 : STD_LOGIC;
SIGNAL signal_wire38 : STD_LOGIC;
SIGNAL signal_wire39 : STD_LOGIC;
SIGNAL signal_wire40 : STD_LOGIC;
SIGNAL signal_wire41 : STD_LOGIC;
SIGNAL signal_wire42 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire43 : STD_LOGIC;
SIGNAL signal_wire44 : STD_LOGIC;
SIGNAL signal_wire45 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire46 : STD_LOGIC;
SIGNAL signal_wire47 : STD_LOGIC;
SIGNAL signal_wire48 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire49 : STD_LOGIC;
SIGNAL signal_wire50 : STD_LOGIC;
SIGNAL signal_wire51 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire52 : STD_LOGIC;
SIGNAL signal_wire53 : STD_LOGIC;
SIGNAL signal_wire54 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire55 : STD_LOGIC;
SIGNAL signal_wire56 : STD_LOGIC;
SIGNAL signal_wire57 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire58 : STD_LOGIC;
SIGNAL signal_wire59 : STD_LOGIC;
SIGNAL signal_wire60 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire61 : STD_LOGIC;
SIGNAL signal_wire62 : STD_LOGIC;
SIGNAL signal_wire63 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire64 : STD_LOGIC;
SIGNAL signal_wire65 : STD_LOGIC;
SIGNAL signal_wire66 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire67 : STD_LOGIC;
SIGNAL signal_wire68 : STD_LOGIC;
SIGNAL signal_wire69 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire70 : STD_LOGIC;
SIGNAL signal_wire71 : STD_LOGIC;
SIGNAL signal_wire72 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire73 : STD_LOGIC;
SIGNAL signal_wire74 : STD_LOGIC;
SIGNAL signal_wire75 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire76 : STD_LOGIC;
SIGNAL signal_wire77 : STD_LOGIC;
SIGNAL signal_wire78 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL signal_wire79 : STD_LOGIC;
SIGNAL signal_wire80 : STD_LOGIC;
SIGNAL signal_wire81 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL signal_wire82 : STD_LOGIC;
COMPONENT altpcie_hip_pipen1b
GENERIC (
tx_cdc_full_value : NATURAL;
CB_PCIE_MODE : NATURAL;
CG_AVALON_S_ADDR_WIDTH : NATURAL;
CG_COMMON_CLOCK_MODE : NATURAL;
CG_IMPL_CRA_AV_SLAVE_PORT : NATURAL;
INTENDED_DEVICE_FAMILY : STRING;
CB_A2P_ADDR_MAP_NUM_ENTRIES : NATURAL;
CB_A2P_ADDR_MAP_PASS_THRU_BITS : NATURAL;
CB_A2P_ADDR_MAP_IS_FIXED : NATURAL;
CB_A2P_ADDR_MAP_FIXED_TABLE : STD_LOGIC_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000";
CB_P2A_AVALON_ADDR_B0 : STD_LOGIC_VECTOR := X"00000000";
CB_P2A_AVALON_ADDR_B1 : STD_LOGIC_VECTOR := X"00040000";
CB_P2A_AVALON_ADDR_B2 : STD_LOGIC_VECTOR := X"00000000";
CB_P2A_AVALON_ADDR_B3 : STD_LOGIC_VECTOR := X"00000000";
CB_P2A_AVALON_ADDR_B4 : STD_LOGIC_VECTOR := X"00000000";
CB_P2A_AVALON_ADDR_B5 : STD_LOGIC_VECTOR := X"00000000";
TL_SELECTION : NATURAL;
bypass_tl : STRING;
AST_LITE : NATURAL;
p_pcie_hip_type : STRING;
retry_buffer_last_active_address : STRING;
advanced_errors : STRING;
bar0_io_space : STRING;
bar0_64bit_mem_space : STRING;
bar0_prefetchable : STRING;
bar0_size_mask : NATURAL;
bar1_io_space : STRING;
bar1_64bit_mem_space : STRING;
bar1_prefetchable : STRING;
bar1_size_mask : NATURAL;
enable_ecrc_check : STRING;
enable_ecrc_gen : STRING;
enable_l1_aspm : STRING;
l01_entry_latency : NATURAL;
core_clk_source : STRING;
pcie_mode : STRING;
expansion_base_address_register : NATURAL;
extend_tag_field : STRING;
bypass_cdc : STRING;
vc_arbitration : NATURAL;
no_soft_reset : STRING;
enable_ch0_pclk_out : STRING;
core_clk_divider : NATURAL;
millisecond_cycle_count : NATURAL;
single_rx_detect : NATURAL;
enable_coreclk_out_half_rate : STRING;
enable_gen2_core : STRING;
gen2_lane_rate_mode : STRING;
lane_mask : STD_LOGIC_VECTOR := B"11111110";
max_link_width : NATURAL;
vendor_id : NATURAL;
device_id : NATURAL;
revision_id : NATURAL;
class_code : NATURAL;
subsystem_vendor_id : NATURAL;
subsystem_device_id : NATURAL;
port_link_number : NATURAL;
vc_enable : STD_LOGIC_VECTOR := B"0000000";
vc1_clk_enable : STRING;
low_priority_vc : NATURAL;
max_payload_size : NATURAL;
msi_function_count : NATURAL;
endpoint_l0_latency : NATURAL;
endpoint_l1_latency : NATURAL;
diffclock_nfts_count : NATURAL;
sameclock_nfts_count : NATURAL;
l1_exit_latency_sameclock : NATURAL;
l1_exit_latency_diffclock : NATURAL;
l0_exit_latency_sameclock : NATURAL;
l0_exit_latency_diffclock : NATURAL;
enable_msi_64bit_addressing : STRING;
gen2_diffclock_nfts_count : NATURAL;
gen2_sameclock_nfts_count : NATURAL;
enable_function_msix_support : STRING;
credit_buffer_allocation_aux : STRING;
eie_before_nfts_count : NATURAL;
enable_completion_timeout_disable : STRING;
completion_timeout : STRING;
enable_adapter_half_rate_mode : STRING;
msix_pba_bir : NATURAL;
msix_pba_offset : NATURAL;
msix_table_bir : NATURAL;
msix_table_offset : NATURAL;
msix_table_size : NATURAL;
use_crc_forwarding : STRING;
surprise_down_error_support : STRING;
dll_active_report_support : STRING;
bar_io_window_size : STRING;
bar_prefetchable : NATURAL;
hot_plug_support : STD_LOGIC_VECTOR := B"0000000";
no_command_completed : STRING;
slot_power_limit : NATURAL;
slot_power_scale : NATURAL;
slot_number : NATURAL;
enable_slot_register : STRING;
vc0_rx_flow_ctrl_posted_header : NATURAL;
vc0_rx_flow_ctrl_posted_data : NATURAL;
vc0_rx_flow_ctrl_nonposted_header : NATURAL;
vc0_rx_flow_ctrl_nonposted_data : NATURAL;
vc0_rx_flow_ctrl_compl_header : NATURAL;
vc0_rx_flow_ctrl_compl_data : NATURAL;
RX_BUF : NATURAL;
RH_NUM : NATURAL;
G_TAG_NUM0 : NATURAL
);
PORT (
AvlClk_i : IN STD_LOGIC;
CraAddress_i : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
CraByteEnable_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CraChipSelect_i : IN STD_LOGIC;
CraRead : IN STD_LOGIC;
CraWrite : IN STD_LOGIC;
CraWriteData_i : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
Rstn_i : IN STD_LOGIC;
RxmIrqNum_i : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
RxmIrq_i : IN STD_LOGIC;
RxmReadDataValid_i : IN STD_LOGIC;
RxmReadData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
RxmWaitRequest_i : IN STD_LOGIC;
TxsAddress_i : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
TxsBurstCount_i : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
TxsByteEnable_i : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
TxsChipSelect_i : IN STD_LOGIC;
TxsRead_i : IN STD_LOGIC;
TxsWriteData_i : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
TxsWrite_i : IN STD_LOGIC;
aer_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
app_int_sts : IN STD_LOGIC;
app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
app_msi_req : IN STD_LOGIC;
app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
avs_pcie_reconfig_address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
avs_pcie_reconfig_chipselect : IN STD_LOGIC;
avs_pcie_reconfig_clk : IN STD_LOGIC;
avs_pcie_reconfig_read : IN STD_LOGIC;
avs_pcie_reconfig_rstn : IN STD_LOGIC;
avs_pcie_reconfig_write : IN STD_LOGIC;
avs_pcie_reconfig_writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
core_clk_in : IN STD_LOGIC;
cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
cpl_pending : IN STD_LOGIC;
crst : IN STD_LOGIC;
hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
lmi_rden : IN STD_LOGIC;
lmi_wren : IN STD_LOGIC;
mode : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
npor : IN STD_LOGIC;
pclk_central : IN STD_LOGIC;
pclk_ch0 : IN STD_LOGIC;
pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
pld_clk : IN STD_LOGIC;
pll_fixed_clk : IN STD_LOGIC;
pm_auxpwr : IN STD_LOGIC;
pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
pm_event : IN STD_LOGIC;
pme_to_cr : IN STD_LOGIC;
rc_areset : IN STD_LOGIC;
rc_inclk_eq_125mhz : IN STD_LOGIC;
rc_pll_locked : IN STD_LOGIC;
rc_rx_pll_locked_one : IN STD_LOGIC;
rx_st_mask0 : IN STD_LOGIC;
rx_st_ready0 : IN STD_LOGIC;
srst : IN STD_LOGIC;
swdn_in : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
swup_in : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
tl_slotclk_cfg : IN STD_LOGIC;
tlbp_dl_aspm_cr0 : IN STD_LOGIC;
tlbp_dl_comclk_reg : IN STD_LOGIC;
tlbp_dl_ctrl_link2 : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
tlbp_dl_data_upfc : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
tlbp_dl_hdr_upfc : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
tlbp_dl_inh_dllp : IN STD_LOGIC;
tlbp_dl_maxpload_dcr : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tlbp_dl_req_phycfg : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
tlbp_dl_req_phypm : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
tlbp_dl_req_upfc : IN STD_LOGIC;
tlbp_dl_req_wake : IN STD_LOGIC;
tlbp_dl_rx_ecrcchk : IN STD_LOGIC;
tlbp_dl_snd_upfc : IN STD_LOGIC;
tlbp_dl_tx_reqpm : IN STD_LOGIC;
tlbp_dl_tx_typpm : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tlbp_dl_txcfg_extsy : IN STD_LOGIC;
tlbp_dl_typ_upfc : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
tlbp_dl_vc_ctrl : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
tlbp_dl_vcid_map : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
tlbp_dl_vcid_upfc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_data0_p1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_eop0 : IN STD_LOGIC;
tx_st_eop0_p1 : IN STD_LOGIC;
tx_st_err0 : IN STD_LOGIC;
tx_st_sop0 : IN STD_LOGIC;
tx_st_sop0_p1 : IN STD_LOGIC;
tx_st_valid0 : IN STD_LOGIC;
rx_st_mask1 : IN STD_LOGIC;
rx_st_ready1 : IN STD_LOGIC;
tx_st_data1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_data1_p1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
tx_st_eop1 : IN STD_LOGIC;
tx_st_eop1_p1 : IN STD_LOGIC;
tx_st_err1 : IN STD_LOGIC;
tx_st_sop1 : IN STD_LOGIC;
tx_st_sop1_p1 : IN STD_LOGIC;
tx_st_valid1 : IN STD_LOGIC;
phystatus0_ext : IN STD_LOGIC;
rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak0_ext : IN STD_LOGIC;
rxelecidle0_ext : IN STD_LOGIC;
rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid0_ext : IN STD_LOGIC;
phystatus1_ext : IN STD_LOGIC;
rxdata1_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak1_ext : IN STD_LOGIC;
rxelecidle1_ext : IN STD_LOGIC;
rxstatus1_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid1_ext : IN STD_LOGIC;
phystatus2_ext : IN STD_LOGIC;
rxdata2_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak2_ext : IN STD_LOGIC;
rxelecidle2_ext : IN STD_LOGIC;
rxstatus2_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid2_ext : IN STD_LOGIC;
phystatus3_ext : IN STD_LOGIC;
rxdata3_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak3_ext : IN STD_LOGIC;
rxelecidle3_ext : IN STD_LOGIC;
rxstatus3_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid3_ext : IN STD_LOGIC;
phystatus4_ext : IN STD_LOGIC;
rxdata4_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak4_ext : IN STD_LOGIC;
rxelecidle4_ext : IN STD_LOGIC;
rxstatus4_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid4_ext : IN STD_LOGIC;
phystatus5_ext : IN STD_LOGIC;
rxdata5_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak5_ext : IN STD_LOGIC;
rxelecidle5_ext : IN STD_LOGIC;
rxstatus5_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid5_ext : IN STD_LOGIC;
phystatus6_ext : IN STD_LOGIC;
rxdata6_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak6_ext : IN STD_LOGIC;
rxelecidle6_ext : IN STD_LOGIC;
rxstatus6_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid6_ext : IN STD_LOGIC;
phystatus7_ext : IN STD_LOGIC;
rxdata7_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rxdatak7_ext : IN STD_LOGIC;
rxelecidle7_ext : IN STD_LOGIC;
rxstatus7_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
rxvalid7_ext : IN STD_LOGIC;
CraIrq_o : OUT STD_LOGIC;
CraReadData_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
CraWaitRequest_o : OUT STD_LOGIC;
RxmAddress_o : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
RxmBurstCount_o : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
RxmByteEnable_o : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
RxmRead_o : OUT STD_LOGIC;
RxmWriteData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
RxmWrite_o : OUT STD_LOGIC;
TxsReadDataValid_o : OUT STD_LOGIC;
TxsReadData_o : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
TxsWaitRequest_o : OUT STD_LOGIC;
app_int_ack : OUT STD_LOGIC;
app_msi_ack : OUT STD_LOGIC;
avs_pcie_reconfig_readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
avs_pcie_reconfig_readdatavalid : OUT STD_LOGIC;
avs_pcie_reconfig_waitrequest : OUT STD_LOGIC;
core_clk_out : OUT STD_LOGIC;
derr_cor_ext_rcv0 : OUT STD_LOGIC;
derr_cor_ext_rpl : OUT STD_LOGIC;
derr_rpl : OUT STD_LOGIC;
dl_ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
dlup_exit : OUT STD_LOGIC;
eidle_infer_sel : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
ev_128ns : OUT STD_LOGIC;
ev_1us : OUT STD_LOGIC;
hip_extraclkout : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
hotrst_exit : OUT STD_LOGIC;
int_status : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
l2_exit : OUT STD_LOGIC;
lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
lmi_ack : OUT STD_LOGIC;
lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
npd_alloc_1cred_vc0 : OUT STD_LOGIC;
npd_cred_vio_vc0 : OUT STD_LOGIC;
nph_alloc_1cred_vc0 : OUT STD_LOGIC;
nph_cred_vio_vc0 : OUT STD_LOGIC;
pme_to_sr : OUT STD_LOGIC;
r2c_err0 : OUT STD_LOGIC;
rate_ext : OUT STD_LOGIC;
rc_gxb_powerdown : OUT STD_LOGIC;
rc_rx_analogreset : OUT STD_LOGIC;
rc_rx_digitalreset : OUT STD_LOGIC;
rc_tx_digitalreset : OUT STD_LOGIC;
reset_status : OUT STD_LOGIC;
rx_fifo_empty0 : OUT STD_LOGIC;
rx_fifo_full0 : OUT STD_LOGIC;
rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be0_p1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_data0_p1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_eop0 : OUT STD_LOGIC;
rx_st_eop0_p1 : OUT STD_LOGIC;
rx_st_err0 : OUT STD_LOGIC;
rx_st_sop0 : OUT STD_LOGIC;
rx_st_sop0_p1 : OUT STD_LOGIC;
rx_st_valid0 : OUT STD_LOGIC;
serr_out : OUT STD_LOGIC;
suc_spd_neg : OUT STD_LOGIC;
swdn_wake : OUT STD_LOGIC;
swup_hotrst : OUT STD_LOGIC;
test_out : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
tl_cfg_ctl_wr : OUT STD_LOGIC;
tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
tl_cfg_sts_wr : OUT STD_LOGIC;
tlbp_dl_ack_phypm : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
tlbp_dl_ack_requpfc : OUT STD_LOGIC;
tlbp_dl_ack_sndupfc : OUT STD_LOGIC;
tlbp_dl_current_deemp : OUT STD_LOGIC;
tlbp_dl_currentspeed : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
tlbp_dl_dll_req : OUT STD_LOGIC;
tlbp_dl_err_dll : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
tlbp_dl_errphy : OUT STD_LOGIC;
tlbp_dl_link_autobdw_status : OUT STD_LOGIC;
tlbp_dl_link_bdwmng_status : OUT STD_LOGIC;
tlbp_dl_rpbuf_emp : OUT STD_LOGIC;
tlbp_dl_rst_enter_comp_bit : OUT STD_LOGIC;
tlbp_dl_rst_tx_margin_field : OUT STD_LOGIC;
tlbp_dl_rx_typ_pm : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
tlbp_dl_rx_valpm : OUT STD_LOGIC;
tlbp_dl_tx_ackpm : OUT STD_LOGIC;
tlbp_dl_up : OUT STD_LOGIC;
tlbp_dl_vc_status : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
tlbp_link_up : OUT STD_LOGIC;
tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
tx_deemph : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
tx_fifo_empty0 : OUT STD_LOGIC;
tx_fifo_full0 : OUT STD_LOGIC;
tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_margin : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
tx_st_ready0 : OUT STD_LOGIC;
use_pcie_reconfig : OUT STD_LOGIC;
wake_oen : OUT STD_LOGIC;
derr_cor_ext_rcv1 : OUT STD_LOGIC;
npd_alloc_1cred_vc1 : OUT STD_LOGIC;
npd_cred_vio_vc1 : OUT STD_LOGIC;
nph_alloc_1cred_vc1 : OUT STD_LOGIC;
nph_cred_vio_vc1 : OUT STD_LOGIC;
r2c_err1 : OUT STD_LOGIC;
rx_fifo_empty1 : OUT STD_LOGIC;
rx_fifo_full1 : OUT STD_LOGIC;
rx_st_bardec1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_be1_p1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_st_data1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_data1_p1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
rx_st_eop1 : OUT STD_LOGIC;
rx_st_eop1_p1 : OUT STD_LOGIC;
rx_st_err1 : OUT STD_LOGIC;
rx_st_sop1 : OUT STD_LOGIC;
rx_st_sop1_p1 : OUT STD_LOGIC;
rx_st_valid1 : OUT STD_LOGIC;
tx_cred1 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
tx_fifo_empty1 : OUT STD_LOGIC;
tx_fifo_full1 : OUT STD_LOGIC;
tx_fifo_rdptr1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_fifo_wrptr1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_st_ready1 : OUT STD_LOGIC;
powerdown0_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity0_ext : OUT STD_LOGIC;
txcompl0_ext : OUT STD_LOGIC;
txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak0_ext : OUT STD_LOGIC;
txdetectrx0_ext : OUT STD_LOGIC;
txelecidle0_ext : OUT STD_LOGIC;
powerdown1_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity1_ext : OUT STD_LOGIC;
txcompl1_ext : OUT STD_LOGIC;
txdata1_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak1_ext : OUT STD_LOGIC;
txdetectrx1_ext : OUT STD_LOGIC;
txelecidle1_ext : OUT STD_LOGIC;
powerdown2_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity2_ext : OUT STD_LOGIC;
txcompl2_ext : OUT STD_LOGIC;
txdata2_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak2_ext : OUT STD_LOGIC;
txdetectrx2_ext : OUT STD_LOGIC;
txelecidle2_ext : OUT STD_LOGIC;
powerdown3_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity3_ext : OUT STD_LOGIC;
txcompl3_ext : OUT STD_LOGIC;
txdata3_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak3_ext : OUT STD_LOGIC;
txdetectrx3_ext : OUT STD_LOGIC;
txelecidle3_ext : OUT STD_LOGIC;
powerdown4_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity4_ext : OUT STD_LOGIC;
txcompl4_ext : OUT STD_LOGIC;
txdata4_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak4_ext : OUT STD_LOGIC;
txdetectrx4_ext : OUT STD_LOGIC;
txelecidle4_ext : OUT STD_LOGIC;
powerdown5_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity5_ext : OUT STD_LOGIC;
txcompl5_ext : OUT STD_LOGIC;
txdata5_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak5_ext : OUT STD_LOGIC;
txdetectrx5_ext : OUT STD_LOGIC;
txelecidle5_ext : OUT STD_LOGIC;
powerdown6_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity6_ext : OUT STD_LOGIC;
txcompl6_ext : OUT STD_LOGIC;
txdata6_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak6_ext : OUT STD_LOGIC;
txdetectrx6_ext : OUT STD_LOGIC;
txelecidle6_ext : OUT STD_LOGIC;
powerdown7_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rxpolarity7_ext : OUT STD_LOGIC;
txcompl7_ext : OUT STD_LOGIC;
txdata7_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
txdatak7_ext : OUT STD_LOGIC;
txdetectrx7_ext : OUT STD_LOGIC;
txelecidle7_ext : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
signal_wire0 <= (others => '0');
signal_wire1 <= '0';
signal_wire2 <= '0';
signal_wire3 <= '0';
signal_wire4 <= '0';
signal_wire5 <= '0';
signal_wire6 <= (others => '0');
signal_wire7 <= (others => '0');
signal_wire8 <= (others => '0');
signal_wire9 <= (others => '0');
signal_wire10 <= '1';
signal_wire11 <= '0';
signal_wire12 <= '0';
signal_wire13 <= (others => '0');
signal_wire14 <= (others => '0');
signal_wire15 <= (others => '0');
signal_wire16 <= '0';
signal_wire17 <= (others => '0');
signal_wire18 <= (others => '0');
signal_wire19 <= (others => '0');
signal_wire20 <= '0';
signal_wire21 <= '0';
signal_wire22 <= '0';
signal_wire23 <= '0';
signal_wire24 <= '0';
signal_wire25 <= (others => '0');
signal_wire26 <= '0';
signal_wire27 <= (others => '0');
signal_wire28 <= (others => '0');
signal_wire29 <= (others => '0');
signal_wire30 <= (others => '0');
signal_wire31 <= '0';
signal_wire32 <= '0';
signal_wire33 <= (others => '0');
signal_wire34 <= (others => '0');
signal_wire35 <= '0';
signal_wire36 <= '0';
signal_wire37 <= '0';
signal_wire38 <= '0';
signal_wire39 <= '0';
signal_wire40 <= '0';
signal_wire41 <= '0';
signal_wire42 <= (others => '0');
signal_wire43 <= '0';
signal_wire44 <= '0';
signal_wire45 <= (others => '0');
signal_wire46 <= '0';
signal_wire47 <= '0';
signal_wire48 <= (others => '0');
signal_wire49 <= '0';
signal_wire50 <= '0';
signal_wire51 <= (others => '0');
signal_wire52 <= '0';
signal_wire53 <= '0';
signal_wire54 <= (others => '0');
signal_wire55 <= '0';
signal_wire56 <= '0';
signal_wire57 <= (others => '0');
signal_wire58 <= '0';
signal_wire59 <= '0';
signal_wire60 <= (others => '0');
signal_wire61 <= '0';
signal_wire62 <= '0';
signal_wire63 <= (others => '0');
signal_wire64 <= '0';
signal_wire65 <= '0';
signal_wire66 <= (others => '0');
signal_wire67 <= '0';
signal_wire68 <= '0';
signal_wire69 <= (others => '0');
signal_wire70 <= '0';
signal_wire71 <= '0';
signal_wire72 <= (others => '0');
signal_wire73 <= '0';
signal_wire74 <= '0';
signal_wire75 <= (others => '0');
signal_wire76 <= '0';
signal_wire77 <= '0';
signal_wire78 <= (others => '0');
signal_wire79 <= '0';
signal_wire80 <= '0';
signal_wire81 <= (others => '0');
signal_wire82 <= '0';
altpcie_hip_pipen1b_inst : altpcie_hip_pipen1b
GENERIC MAP (
tx_cdc_full_value => 12,
CB_PCIE_MODE => 0,
CG_AVALON_S_ADDR_WIDTH => 31,
CG_COMMON_CLOCK_MODE => 1,
CG_IMPL_CRA_AV_SLAVE_PORT => 1,
INTENDED_DEVICE_FAMILY => "Cyclone IV GX",
CB_A2P_ADDR_MAP_NUM_ENTRIES => 2,
CB_A2P_ADDR_MAP_PASS_THRU_BITS => 30,
CB_A2P_ADDR_MAP_IS_FIXED => 0,
CB_A2P_ADDR_MAP_FIXED_TABLE => X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000000000000000000",
CB_P2A_AVALON_ADDR_B0 => X"00000000",
CB_P2A_AVALON_ADDR_B1 => X"00040000",
CB_P2A_AVALON_ADDR_B2 => X"00000000",
CB_P2A_AVALON_ADDR_B3 => X"00000000",
CB_P2A_AVALON_ADDR_B4 => X"00000000",
CB_P2A_AVALON_ADDR_B5 => X"00000000",
TL_SELECTION => 1,
bypass_tl => "true",
AST_LITE => 0,
p_pcie_hip_type => "2",
retry_buffer_last_active_address => "255",
advanced_errors => "false",
bar0_io_space => "false",
bar0_64bit_mem_space => "false",
bar0_prefetchable => "false",
bar0_size_mask => 15,
bar1_io_space => "false",
bar1_64bit_mem_space => "false",
bar1_prefetchable => "false",
bar1_size_mask => 18,
enable_ecrc_check => "false",
enable_ecrc_gen => "false",
enable_l1_aspm => "false",
l01_entry_latency => 31,
core_clk_source => "pclk",
pcie_mode => "SHARED_MODE",
expansion_base_address_register => 0,
extend_tag_field => "false",
bypass_cdc => "false",
vc_arbitration => 0,
no_soft_reset => "false",
enable_ch0_pclk_out => "true",
core_clk_divider => 4,
millisecond_cycle_count => 125000,
single_rx_detect => 1,
enable_coreclk_out_half_rate => "false",
enable_gen2_core => "false",
gen2_lane_rate_mode => "false",
lane_mask => B"11111110",
max_link_width => 1,
vendor_id => 6997,
device_id => 6390,
revision_id => 2,
class_code => 294912,
subsystem_vendor_id => 6997,
subsystem_device_id => 6390,
port_link_number => 1,
vc_enable => B"0000000",
vc1_clk_enable => "false",
low_priority_vc => 0,
max_payload_size => 1,
msi_function_count => 0,
endpoint_l0_latency => 0,
endpoint_l1_latency => 0,
diffclock_nfts_count => 255,
sameclock_nfts_count => 255,
l1_exit_latency_sameclock => 7,
l1_exit_latency_diffclock => 7,
l0_exit_latency_sameclock => 7,
l0_exit_latency_diffclock => 7,
enable_msi_64bit_addressing => "true",
gen2_diffclock_nfts_count => 255,
gen2_sameclock_nfts_count => 255,
enable_function_msix_support => "false",
credit_buffer_allocation_aux => "ABSOLUTE",
eie_before_nfts_count => 4,
enable_completion_timeout_disable => "false",
completion_timeout => "NONE",
enable_adapter_half_rate_mode => "false",
msix_pba_bir => 0,
msix_pba_offset => 0,
msix_table_bir => 0,
msix_table_offset => 0,
msix_table_size => 0,
use_crc_forwarding => "false",
surprise_down_error_support => "false",
dll_active_report_support => "false",
bar_io_window_size => "32BIT",
bar_prefetchable => 32,
hot_plug_support => B"0000000",
no_command_completed => "true",
slot_power_limit => 0,
slot_power_scale => 0,
slot_number => 0,
enable_slot_register => "false",
vc0_rx_flow_ctrl_posted_header => 28,
vc0_rx_flow_ctrl_posted_data => 198,
vc0_rx_flow_ctrl_nonposted_header => 30,
vc0_rx_flow_ctrl_nonposted_data => 0,
vc0_rx_flow_ctrl_compl_header => 0,
vc0_rx_flow_ctrl_compl_data => 0,
RX_BUF => 10,
RH_NUM => 7,
G_TAG_NUM0 => 32
)
PORT MAP (
AvlClk_i => AvlClk_i,
CraAddress_i => CraAddress_i,
CraByteEnable_i => CraByteEnable_i,
CraChipSelect_i => CraChipSelect_i,
CraRead => CraRead,
CraWrite => CraWrite,
CraWriteData_i => CraWriteData_i,
Rstn_i => Rstn_i,
RxmIrqNum_i => RxmIrqNum_i,
RxmIrq_i => RxmIrq_i,
RxmReadDataValid_i => RxmReadDataValid_i,
RxmReadData_i => RxmReadData_i,
RxmWaitRequest_i => RxmWaitRequest_i,
TxsAddress_i => TxsAddress_i,
TxsBurstCount_i => TxsBurstCount_i,
TxsByteEnable_i => TxsByteEnable_i,
TxsChipSelect_i => TxsChipSelect_i,
TxsRead_i => TxsRead_i,
TxsWriteData_i => TxsWriteData_i,
TxsWrite_i => TxsWrite_i,
aer_msi_num => aer_msi_num,
app_int_sts => app_int_sts,
app_msi_num => app_msi_num,
app_msi_req => app_msi_req,
app_msi_tc => app_msi_tc,
avs_pcie_reconfig_address => signal_wire0,
avs_pcie_reconfig_chipselect => signal_wire1,
avs_pcie_reconfig_clk => signal_wire2,
avs_pcie_reconfig_read => signal_wire3,
avs_pcie_reconfig_rstn => signal_wire4,
avs_pcie_reconfig_write => signal_wire5,
avs_pcie_reconfig_writedata => signal_wire6,
core_clk_in => core_clk_in,
cpl_err => cpl_err,
cpl_pending => cpl_pending,
crst => crst,
hpg_ctrler => hpg_ctrler,
lmi_addr => lmi_addr,
lmi_din => lmi_din,
lmi_rden => lmi_rden,
lmi_wren => lmi_wren,
mode => signal_wire7,
npor => npor,
pclk_central => pclk_central,
pclk_ch0 => pclk_ch0,
pex_msi_num => pex_msi_num,
pld_clk => pld_clk,
pll_fixed_clk => pll_fixed_clk,
pm_auxpwr => pm_auxpwr,
pm_data => pm_data,
pm_event => pm_event,
pme_to_cr => pme_to_cr,
rc_areset => rc_areset,
rc_inclk_eq_125mhz => rc_inclk_eq_125mhz,
rc_pll_locked => rc_pll_locked,
rc_rx_pll_locked_one => rc_rx_pll_locked_one,
rx_st_mask0 => rx_st_mask0,
rx_st_ready0 => rx_st_ready0,
srst => srst,
swdn_in => signal_wire8,
swup_in => signal_wire9,
test_in => test_in,
tl_slotclk_cfg => signal_wire10,
tlbp_dl_aspm_cr0 => signal_wire11,
tlbp_dl_comclk_reg => signal_wire12,
tlbp_dl_ctrl_link2 => signal_wire13,
tlbp_dl_data_upfc => signal_wire14,
tlbp_dl_hdr_upfc => signal_wire15,
tlbp_dl_inh_dllp => signal_wire16,
tlbp_dl_maxpload_dcr => signal_wire17,
tlbp_dl_req_phycfg => signal_wire18,
tlbp_dl_req_phypm => signal_wire19,
tlbp_dl_req_upfc => signal_wire20,
tlbp_dl_req_wake => signal_wire21,
tlbp_dl_rx_ecrcchk => signal_wire22,
tlbp_dl_snd_upfc => signal_wire23,
tlbp_dl_tx_reqpm => signal_wire24,
tlbp_dl_tx_typpm => signal_wire25,
tlbp_dl_txcfg_extsy => signal_wire26,
tlbp_dl_typ_upfc => signal_wire27,
tlbp_dl_vc_ctrl => signal_wire28,
tlbp_dl_vcid_map => signal_wire29,
tlbp_dl_vcid_upfc => signal_wire30,
tx_st_data0 => tx_st_data0,
tx_st_data0_p1 => tx_st_data0_p1,
tx_st_eop0 => tx_st_eop0,
tx_st_eop0_p1 => tx_st_eop0_p1,
tx_st_err0 => tx_st_err0,
tx_st_sop0 => tx_st_sop0,
tx_st_sop0_p1 => tx_st_sop0_p1,
tx_st_valid0 => tx_st_valid0,
rx_st_mask1 => signal_wire31,
rx_st_ready1 => signal_wire32,
tx_st_data1 => signal_wire33,
tx_st_data1_p1 => signal_wire34,
tx_st_eop1 => signal_wire35,
tx_st_eop1_p1 => signal_wire36,
tx_st_err1 => signal_wire37,
tx_st_sop1 => signal_wire38,
tx_st_sop1_p1 => signal_wire39,
tx_st_valid1 => signal_wire40,
phystatus0_ext => phystatus0_ext,
rxdata0_ext => rxdata0_ext,
rxdatak0_ext => rxdatak0_ext,
rxelecidle0_ext => rxelecidle0_ext,
rxstatus0_ext => rxstatus0_ext,
rxvalid0_ext => rxvalid0_ext,
phystatus1_ext => signal_wire41,
rxdata1_ext => signal_wire42,
rxdatak1_ext => signal_wire43,
rxelecidle1_ext => signal_wire44,
rxstatus1_ext => signal_wire45,
rxvalid1_ext => signal_wire46,
phystatus2_ext => signal_wire47,
rxdata2_ext => signal_wire48,
rxdatak2_ext => signal_wire49,
rxelecidle2_ext => signal_wire50,
rxstatus2_ext => signal_wire51,
rxvalid2_ext => signal_wire52,
phystatus3_ext => signal_wire53,
rxdata3_ext => signal_wire54,
rxdatak3_ext => signal_wire55,
rxelecidle3_ext => signal_wire56,
rxstatus3_ext => signal_wire57,
rxvalid3_ext => signal_wire58,
phystatus4_ext => signal_wire59,
rxdata4_ext => signal_wire60,
rxdatak4_ext => signal_wire61,
rxelecidle4_ext => signal_wire62,
rxstatus4_ext => signal_wire63,
rxvalid4_ext => signal_wire64,
phystatus5_ext => signal_wire65,
rxdata5_ext => signal_wire66,
rxdatak5_ext => signal_wire67,
rxelecidle5_ext => signal_wire68,
rxstatus5_ext => signal_wire69,
rxvalid5_ext => signal_wire70,
phystatus6_ext => signal_wire71,
rxdata6_ext => signal_wire72,
rxdatak6_ext => signal_wire73,
rxelecidle6_ext => signal_wire74,
rxstatus6_ext => signal_wire75,
rxvalid6_ext => signal_wire76,
phystatus7_ext => signal_wire77,
rxdata7_ext => signal_wire78,
rxdatak7_ext => signal_wire79,
rxelecidle7_ext => signal_wire80,
rxstatus7_ext => signal_wire81,
rxvalid7_ext => signal_wire82,
CraIrq_o => CraIrq_o,
CraReadData_o => CraReadData_o,
CraWaitRequest_o => CraWaitRequest_o,
RxmAddress_o => RxmAddress_o,
RxmBurstCount_o => RxmBurstCount_o,
RxmByteEnable_o => RxmByteEnable_o,
RxmRead_o => RxmRead_o,
RxmWriteData_o => RxmWriteData_o,
RxmWrite_o => RxmWrite_o,
TxsReadDataValid_o => TxsReadDataValid_o,
TxsReadData_o => TxsReadData_o,
TxsWaitRequest_o => TxsWaitRequest_o,
app_int_ack => app_int_ack,
app_msi_ack => app_msi_ack,
avs_pcie_reconfig_readdata => avs_pcie_reconfig_readdata,
avs_pcie_reconfig_readdatavalid => avs_pcie_reconfig_readdatavalid,
avs_pcie_reconfig_waitrequest => avs_pcie_reconfig_waitrequest,
core_clk_out => core_clk_out,
derr_cor_ext_rcv0 => derr_cor_ext_rcv0,
derr_cor_ext_rpl => derr_cor_ext_rpl,
derr_rpl => derr_rpl,
dl_ltssm => dl_ltssm,
dlup_exit => dlup_exit,
eidle_infer_sel => eidle_infer_sel,
ev_128ns => ev_128ns,
ev_1us => ev_1us,
hip_extraclkout => hip_extraclkout,
hotrst_exit => hotrst_exit,
int_status => int_status,
l2_exit => l2_exit,
lane_act => lane_act,
lmi_ack => lmi_ack,
lmi_dout => lmi_dout,
npd_alloc_1cred_vc0 => npd_alloc_1cred_vc0,
npd_cred_vio_vc0 => npd_cred_vio_vc0,
nph_alloc_1cred_vc0 => nph_alloc_1cred_vc0,
nph_cred_vio_vc0 => nph_cred_vio_vc0,
pme_to_sr => pme_to_sr,
r2c_err0 => r2c_err0,
rate_ext => rate_ext,
rc_gxb_powerdown => rc_gxb_powerdown,
rc_rx_analogreset => rc_rx_analogreset,
rc_rx_digitalreset => rc_rx_digitalreset,
rc_tx_digitalreset => rc_tx_digitalreset,
reset_status => reset_status,
rx_fifo_empty0 => rx_fifo_empty0,
rx_fifo_full0 => rx_fifo_full0,
rx_st_bardec0 => rx_st_bardec0,
rx_st_be0 => rx_st_be0,
rx_st_be0_p1 => rx_st_be0_p1,
rx_st_data0 => rx_st_data0,
rx_st_data0_p1 => rx_st_data0_p1,
rx_st_eop0 => rx_st_eop0,
rx_st_eop0_p1 => rx_st_eop0_p1,
rx_st_err0 => rx_st_err0,
rx_st_sop0 => rx_st_sop0,
rx_st_sop0_p1 => rx_st_sop0_p1,
rx_st_valid0 => rx_st_valid0,
serr_out => serr_out,
suc_spd_neg => suc_spd_neg,
swdn_wake => swdn_wake,
swup_hotrst => swup_hotrst,
test_out => test_out,
tl_cfg_add => tl_cfg_add,
tl_cfg_ctl => tl_cfg_ctl,
tl_cfg_ctl_wr => tl_cfg_ctl_wr,
tl_cfg_sts => tl_cfg_sts,
tl_cfg_sts_wr => tl_cfg_sts_wr,
tlbp_dl_ack_phypm => open,
tlbp_dl_ack_requpfc => open,
tlbp_dl_ack_sndupfc => open,
tlbp_dl_current_deemp => open,
tlbp_dl_currentspeed => open,
tlbp_dl_dll_req => open,
tlbp_dl_err_dll => open,
tlbp_dl_errphy => open,
tlbp_dl_link_autobdw_status => open,
tlbp_dl_link_bdwmng_status => open,
tlbp_dl_rpbuf_emp => open,
tlbp_dl_rst_enter_comp_bit => open,
tlbp_dl_rst_tx_margin_field => open,
tlbp_dl_rx_typ_pm => open,
tlbp_dl_rx_valpm => open,
tlbp_dl_tx_ackpm => open,
tlbp_dl_up => open,
tlbp_dl_vc_status => open,
tlbp_link_up => open,
tx_cred0 => tx_cred0,
tx_deemph => tx_deemph,
tx_fifo_empty0 => tx_fifo_empty0,
tx_fifo_full0 => tx_fifo_full0,
tx_fifo_rdptr0 => tx_fifo_rdptr0,
tx_fifo_wrptr0 => tx_fifo_wrptr0,
tx_margin => tx_margin,
tx_st_ready0 => tx_st_ready0,
use_pcie_reconfig => use_pcie_reconfig,
wake_oen => wake_oen,
derr_cor_ext_rcv1 => open,
npd_alloc_1cred_vc1 => open,
npd_cred_vio_vc1 => open,
nph_alloc_1cred_vc1 => open,
nph_cred_vio_vc1 => open,
r2c_err1 => open,
rx_fifo_empty1 => open,
rx_fifo_full1 => open,
rx_st_bardec1 => open,
rx_st_be1 => open,
rx_st_be1_p1 => open,
rx_st_data1 => open,
rx_st_data1_p1 => open,
rx_st_eop1 => open,
rx_st_eop1_p1 => open,
rx_st_err1 => open,
rx_st_sop1 => open,
rx_st_sop1_p1 => open,
rx_st_valid1 => open,
tx_cred1 => open,
tx_fifo_empty1 => open,
tx_fifo_full1 => open,
tx_fifo_rdptr1 => open,
tx_fifo_wrptr1 => open,
tx_st_ready1 => open,
powerdown0_ext => powerdown0_ext,
rxpolarity0_ext => rxpolarity0_ext,
txcompl0_ext => txcompl0_ext,
txdata0_ext => txdata0_ext,
txdatak0_ext => txdatak0_ext,
txdetectrx0_ext => txdetectrx0_ext,
txelecidle0_ext => txelecidle0_ext,
powerdown1_ext => open,
rxpolarity1_ext => open,
txcompl1_ext => open,
txdata1_ext => open,
txdatak1_ext => open,
txdetectrx1_ext => open,
txelecidle1_ext => open,
powerdown2_ext => open,
rxpolarity2_ext => open,
txcompl2_ext => open,
txdata2_ext => open,
txdatak2_ext => open,
txdetectrx2_ext => open,
txelecidle2_ext => open,
powerdown3_ext => open,
rxpolarity3_ext => open,
txcompl3_ext => open,
txdata3_ext => open,
txdatak3_ext => open,
txdetectrx3_ext => open,
txelecidle3_ext => open,
powerdown4_ext => open,
rxpolarity4_ext => open,
txcompl4_ext => open,
txdata4_ext => open,
txdatak4_ext => open,
txdetectrx4_ext => open,
txelecidle4_ext => open,
powerdown5_ext => open,
rxpolarity5_ext => open,
txcompl5_ext => open,
txdata5_ext => open,
txdatak5_ext => open,
txdetectrx5_ext => open,
txelecidle5_ext => open,
powerdown6_ext => open,
rxpolarity6_ext => open,
txcompl6_ext => open,
txdata6_ext => open,
txdatak6_ext => open,
txdetectrx6_ext => open,
txelecidle6_ext => open,
powerdown7_ext => open,
rxpolarity7_ext => open,
txcompl7_ext => open,
txdata7_ext => open,
txdatak7_ext => open,
txdetectrx7_ext => open,
txelecidle7_ext => open
);
END SYN;
|
gpl-3.0
|
7aefd3e2a53d95438080d98deeb15f25
| 0.662525 | 2.499723 | false | false | false | false |
Anding/DDR2_memory_interface
|
rtl/testbench/test_fpga_top.vhd
| 1 | 5,104 |
--------------------------------------------------------------
-- Simple testbench for DDR2 controller
--------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_textio.all;
USE std.textio.all;
USE WORK.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
entity test_fpga_top is
end test_fpga_top;
architecture behavioral of test_fpga_top is
signal clk : std_logic;
signal nrst : std_logic;
signal led : std_logic_vector(1 downto 0);
signal SDRAM_A : std_logic_vector(13 downto 0);
signal SDRAM_BA : std_logic_vector(2 downto 0);
signal SDRAM_CLK : std_logic;
signal SDRAM_nCLK : std_logic;
signal SDRAM_DQ : std_logic_vector(15 downto 0);
signal SDRAM_DM : std_logic_vector(1 downto 0);
signal SDRAM_DQS : std_logic_vector(1 downto 0);
signal SDRAM_nDQS : std_logic_vector(1 downto 0);
signal SDRAM_nRDQS : std_logic_vector(1 downto 0);
signal SDRAM_UDQM : std_logic;
signal SDRAM_LDQM : std_logic;
signal SDRAM_nCAS : std_logic;
signal SDRAM_nCS : std_logic;
signal SDRAM_nRAS : std_logic;
signal SDRAM_nWE : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_ODT : std_logic;
component fpga_top is port(
clk : in std_logic;
nrst : in std_logic;
led : out std_logic_vector(1 downto 0);
sevenseg : out STD_LOGIC_VECTOR (6 downto 0);
anode : out STD_LOGIC_VECTOR (7 downto 0);
SDRAM_A : out std_logic_vector(13 downto 0);
SDRAM_BA : out std_logic_vector(2 downto 0);
SDRAM_CKE : out std_logic;
SDRAM_CK : out std_logic;
SDRAM_nCK : out std_logic;
SDRAM_DQ : inout std_logic_vector(15 downto 0);
SDRAM_DQS : inout std_logic_vector(1 downto 0);
--SDRAM_nDQS : inout std_logic_vector(1 downto 0);
SDRAM_LDQM : out std_logic;
SDRAM_UDQM : out std_logic;
SDRAM_nCAS : out std_logic;
SDRAM_nCS : out std_logic;
SDRAM_nRAS : out std_logic;
SDRAM_nWE : out std_logic;
SDRAM_ODT : out std_logic);
end component;
component ddr2 is port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_rdqs : inout std_logic_vector(1 downto 0);
ba : in std_logic_vector(2 downto 0);
addr : in std_logic_vector(13 downto 0);
dq : inout std_logic_vector(15 downto 0);
dqs : inout std_logic_vector(1 downto 0);
dqs_n : inout std_logic_vector(1 downto 0);
rdqs_n : inout std_logic_vector(1 downto 0);
odt : in std_logic
);
end component;
BEGIN
------------------------------------------------------------------------
-- all test pass
------------------------------------------------------------------------
stop_test_pass_gen:PROCESS
BEGIN
WAIT FOR 10 ns;
if (led = "11") then
ASSERT false REPORT "test passed" severity warning;
elsif (led = "01") then
ASSERT false REPORT "test failed" severity failure;
end if;
END PROCESS;
------------------------------------------------------------------------
-- clk
------------------------------------------------------------------------
clk_gen:PROCESS
BEGIN
clk <= '0';
WAIT FOR 5000 ps;
clk <= '1';
WAIT FOR 5000 ps;
END PROCESS;
------------------------------------------------------------------------
-- nrst
------------------------------------------------------------------------
reset_gen:PROCESS
BEGIN
nrst <= '1';
WAIT FOR 600 ns;
nrst <= '1' ;
WAIT FOR 10100 ns;
ASSERT false REPORT "test done" severity warning;
END PROCESS;
------------------------------------------------------------------------
-- FPGA
------------------------------------------------------------------------
UUT : fpga_top port map (
clk => clk,
nrst => nrst,
led => led,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CK => SDRAM_CLK,
SDRAM_nCK => SDRAM_nCLK,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS,
--SDRAM_nDQS => SDRAM_nDQS,
SDRAM_LDQM => SDRAM_LDQM,
SDRAM_UDQM => SDRAM_UDQM,
SDRAM_nCAS => SDRAM_nCAS,
SDRAM_nCS => SDRAM_nCS,
SDRAM_nRAS => SDRAM_nRAS,
SDRAM_nWE => SDRAM_nWE,
SDRAM_ODT => SDRAM_ODT);
------------------------------------------------------------------------
-- Memory
------------------------------------------------------------------------
SDRAM_DM(0) <= SDRAM_LDQM;
SDRAM_DM(1) <= SDRAM_UDQM;
--SDRAM_ODT <= '0';
SDRAM_nDQS <= "ZZ";
sdramddr2 : ddr2 port map (
ck => SDRAM_CLK,
ck_n => SDRAM_nCLK,
cke => SDRAM_CKE,
cs_n => SDRAM_nCS,
ras_n => SDRAM_nRAS,
cas_n => SDRAM_nCAS,
we_n => SDRAM_nWE,
dm_rdqs => SDRAM_DM,
ba => SDRAM_BA,
addr => SDRAM_A,
dq => SDRAM_DQ,
dqs => SDRAM_DQS,
dqs_n => SDRAM_nDQS,
rdqs_n => SDRAM_nRDQS,
odt => SDRAM_ODT
);
end behavioral;
|
gpl-2.0
|
1516e4f4e0cdbba08dc9997ec961791a
| 0.497257 | 3.549374 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
spi_ram_buffer.vhd
| 1 | 11,777 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: spi_ram_buffer.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY spi_ram_buffer IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END spi_ram_buffer;
ARCHITECTURE SYN OF spi_ram_buffer IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
read_during_write_mode_mixed_ports : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_b : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 512,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
read_during_write_mode_mixed_ports => "DONT_CARE",
read_during_write_mode_port_a => "OLD_DATA",
read_during_write_mode_port_b => "OLD_DATA",
widthad_a => 9,
widthad_b => 10,
width_a => 16,
width_b => 8,
width_byteena_a => 2,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
byteena_a => byteena_a,
clock0 => clock,
wren_a => wren_a,
address_b => address_b,
data_b => data_b,
wren_b => wren_b,
address_a => address_a,
data_a => data_a,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC "byteena_a[1..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
-- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL spi_ram_buffer.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL spi_ram_buffer.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL spi_ram_buffer.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL spi_ram_buffer.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL spi_ram_buffer_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-3.0
|
ee0e0d970dce0cba57a5f885b1eeb6c5
| 0.677762 | 3.240782 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
fifo_in_8b_sync_0.vhd
| 1 | 3,852 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- fifo_in_8b_sync_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fifo_in_8b_sync_0 is
port (
byte_en : in std_logic_vector(3 downto 0) := (others => '0'); -- avalon_slave_0.byteenable
in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(31 downto 0); -- .readdata
rd_en : in std_logic := '0'; -- .read
wait_req : out std_logic; -- .waitrequest
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- .address
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
st_data : in std_logic_vector(7 downto 0) := (others => '0'); -- avalon_streaming_sink.data
st_valid : in std_logic := '0'; -- .valid
st_ready : out std_logic; -- .ready
irq : out std_logic -- conduit_end.export
);
end entity fifo_in_8b_sync_0;
architecture rtl of fifo_in_8b_sync_0 is
component fifo_in_8b_sync is
generic (
FIFO_DEPTH : integer := 16;
BUS_WIDTH : integer := 32
);
port (
byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(31 downto 0); -- readdata
rd_en : in std_logic := 'X'; -- read
wait_req : out std_logic; -- waitrequest
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
st_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
st_valid : in std_logic := 'X'; -- valid
st_ready : out std_logic; -- ready
irq : out std_logic -- export
);
end component fifo_in_8b_sync;
begin
fifo_in_8b_sync_0 : component fifo_in_8b_sync
generic map (
FIFO_DEPTH => 16,
BUS_WIDTH => 32
)
port map (
byte_en => byte_en, -- avalon_slave_0.byteenable
in_data => in_data, -- .writedata
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
rd_en => rd_en, -- .read
wait_req => wait_req, -- .waitrequest
addr => addr, -- .address
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
st_data => st_data, -- avalon_streaming_sink.data
st_valid => st_valid, -- .valid
st_ready => st_ready, -- .ready
irq => irq -- conduit_end.export
);
end architecture rtl; -- of fifo_in_8b_sync_0
|
gpl-3.0
|
c9519d5c467a636321d092439e55d24e
| 0.424455 | 3.589935 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/3/projetos/complemento1/complemento1.vhd
| 1 | 509 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity complemento1 is
Port ( entrada : in STD_LOGIC_VECTOR (2 downto 0) := "000";
sel : in STD_LOGIC := '1';
saida : out STD_LOGIC_VECTOR (2 downto 0)
);
end complemento1;
architecture Behavioral of complemento1 is
signal aux : STD_LOGIC_VECTOR (2 downto 0);
begin
process (entrada,sel,aux)
begin
if (sel = '1') then
aux <= entrada xor "111";
else
aux <= entrada;
end if;
end process;
saida <= aux;
end Behavioral;
|
mit
|
5be29b41931150867cab9920cdcf6a72
| 0.638507 | 3.103659 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/tb_clock24h_bdc.vhd
| 2 | 1,348 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_clock24h_bdc IS
END tb_clock24h_bdc;
ARCHITECTURE behavior OF tb_clock24h_bdc IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clock24h_bcd
PORT(
clk_1ms : IN std_logic;
hour_bcd : OUT std_logic_vector(7 downto 0);
minute_bcd : OUT std_logic_vector(7 downto 0);
clk_1s : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk_1ms : std_logic := '0';
--Outputs
signal hour_bcd : std_logic_vector(7 downto 0);
signal minute_bcd : std_logic_vector(7 downto 0);
signal clk_1s : std_logic;
-- Clock period definitions
constant clk_1ms_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: clock24h_bcd PORT MAP (
clk_1ms => clk_1ms,
hour_bcd => hour_bcd,
minute_bcd => minute_bcd,
clk_1s => clk_1s
);
-- Clock process definitions
clk_1ms_process :process
begin
clk_1ms <= '0';
wait for clk_1ms_period/2;
clk_1ms <= '1';
wait for clk_1ms_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_1ms_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
3a5cbec6b4c06f5008e5e13e2d7bbd00
| 0.596439 | 3.328395 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Source/SPI_SlaveAddressDecoder.vhd
| 1 | 2,237 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides an SPI slave address decoder for addressing a data buffer used for
-- receiving or sending data.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPI_SlaveAddressDecoder is
generic
(
-- The width of the address.
address_width: positive
);
port
(
-- The enable signal.
buffer_enable: in std_logic;
-- The selected data buffer address.
address: in unsigned(address_width-1 downto 0);
-- The output buffer enable signal for each address.
buffer_enable_x: out std_logic_vector((2**address_width)-1 downto 0) := (others => '0')
);
end entity;
architecture stdarch of SPI_SlaveAddressDecoder is
begin
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
output_logic: process(buffer_enable, address) is
begin
buffer_enable_x <= (others => '1');
if (buffer_enable = '0') then
buffer_enable_x(to_integer(address)) <= '0';
end if;
end process;
end architecture;
|
gpl-3.0
|
4c35c255c5acda5850dd8b8c7c27a1a2
| 0.510505 | 5.038288 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
twi_master.vhd
| 1 | 13,032 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity twi_master is
port (
rst : in std_logic;
clk : in std_logic;
-- Avalon-MM 32-bits slave
addr : in std_logic_vector(1 downto 0);
byte_en : in std_logic_vector(1 downto 0) := (others => '1');
in_data : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
out_data : out std_logic_vector(15 downto 0);
--
source_irq : in std_logic;
sink_irq : in std_logic;
irq : out std_logic;
-- DATA source
in_octet : in std_logic_vector(7 downto 0);
in_valid : in std_logic;
in_ready : out std_logic;
-- DATA sink
out_octet : out std_logic_vector(7 downto 0);
out_valid : out std_logic;
out_ready : in std_logic;
-- TWI bus (export)
scl_in : in std_logic;
scl_act : out std_logic;
sda_in : in std_logic;
sda_act : out std_logic
);
end entity;
architecture RTL of twi_master is
-- registers addresses
constant REG_PRESC : std_logic_vector(1 downto 0) := "00";
constant REG_INT_CTRLSTAT : std_logic_vector(1 downto 0) := "01";
constant REG_TWI_CTRL : std_logic_vector(1 downto 0) := "10";
constant REG_DATA_LEN : std_logic_vector(1 downto 0) := "11";
-- int control register bits
constant TWI_COMPL_MASK : natural := 0;
constant TWI_ANACK_MASK : natural := 1;
constant TWI_DNACK_MASK : natural := 2;
-- int status register bits
constant TWI_COMPL : natural := 8;
constant TWI_ANACK : natural := 9;
constant TWI_DNACK : natural := 10;
constant TWI_SOURCE_REQ : natural := 11;
constant TWI_SINK_REQ : natural := 12;
constant TWI_SDA_SENSE : natural := 14;
constant TWI_SCL_SENSE : natural := 15;
-- TWI control register bits
constant TWI_TRANSFER : natural := 8;
constant TWI_NOSTOP : natural := 9;
constant TWI_NOSTART : natural := 10;
constant TWI_SOFT_RESET : natural := 13;
constant TWI_SDA_OVERRIDE : natural := 14;
constant TWI_SCL_OVERRIDE : natural := 15;
signal int_ctrlstat_reg : std_logic_vector(15 downto 0);
signal twi_control_reg : std_logic_vector(15 downto 8);
signal presc_div : unsigned(15 downto 0);
signal compl_mask : std_logic;
signal anack_mask : std_logic;
signal dnack_mask : std_logic;
signal compl : std_logic;
signal anack : std_logic;
signal dnack : std_logic;
signal slave_addr : std_logic_vector(7 downto 0);
signal transfer : std_logic;
signal nostop : std_logic;
signal nostart : std_logic;
signal sda_ovr : std_logic;
signal scl_ovr : std_logic;
signal scl_sen_meta : std_logic;
signal scl_sen : std_logic;
signal sda_sen_meta : std_logic;
signal sda_sen : std_logic;
signal data_len : unsigned(15 downto 0);
signal prescl_wren : std_logic;
signal presch_wren : std_logic;
signal int_ctrl_wren : std_logic;
signal int_stat_wren : std_logic;
signal twi_ctrl_wren : std_logic;
signal slave_addr_wren : std_logic;
signal dlenl_wren : std_logic;
signal dlenh_wren : std_logic;
signal soft_reset : std_logic;
signal start_transfer : std_logic;
signal end_transfer : std_logic;
signal presc_cntr : unsigned(15 downto 0);
signal tick_en : std_logic;
signal phase_tick_en : std_logic;
signal bit_tick_en : std_logic;
signal symbol_tick_en : std_logic;
signal state_tick_en : std_logic;
signal scl_tick_en : std_logic;
signal symbol_pending : std_logic;
signal bit_cntr_en : std_logic;
signal shift_reg : std_logic_vector(8 downto 0);
signal shift_reg_ld_addr : std_logic;
signal shift_reg_ld_data : std_logic;
signal shift_reg_ld_dummy : std_logic;
signal shift_reg_ack_bit : std_logic;
signal bit_phase : unsigned(1 downto 0);
signal bit_cntr : unsigned(3 downto 0);
type twi_state_t is (twi_st_idle, twi_st_start, twi_st_addr, twi_st_data, twi_st_stop, twi_st_end);
signal twi_state : twi_state_t;
signal twi_next_state : twi_state_t;
signal slave_nack : std_logic;
signal anack_i : std_logic;
signal dnack_i : std_logic;
signal scl_i : std_logic;
signal sda_i : std_logic;
signal in_ready_i : std_logic;
signal out_valid_i : std_logic;
signal in_stall : std_logic;
signal out_stall : std_logic;
begin
int_ctrlstat_reg <= (
TWI_COMPL_MASK => compl_mask,
TWI_ANACK_MASK => anack_mask,
TWI_DNACK_MASK => dnack_mask,
--
TWI_COMPL => compl,
TWI_ANACK => anack,
TWI_DNACK => dnack,
TWI_SOURCE_REQ => source_irq,
TWI_SINK_REQ => sink_irq,
TWI_SDA_SENSE => not sda_sen,
TWI_SCL_SENSE => not scl_sen,
--
others => '0'
);
twi_control_reg <= (
TWI_SCL_OVERRIDE => scl_ovr,
TWI_SDA_OVERRIDE => sda_ovr,
TWI_NOSTOP => nostop,
TWI_NOSTART => nostart,
TWI_TRANSFER => transfer,
--
others => '0'
);
with addr select
out_data <= std_logic_vector(presc_div) when REG_PRESC,
int_ctrlstat_reg when REG_INT_CTRLSTAT,
twi_control_reg & slave_addr when REG_TWI_CTRL,
std_logic_vector(data_len) when REG_DATA_LEN,
(others => '0') when others;
prescl_wren <= wr_en and byte_en(0) and not transfer when addr = REG_PRESC else '0';
presch_wren <= wr_en and byte_en(1) and not transfer when addr = REG_PRESC else '0';
int_ctrl_wren <= wr_en and byte_en(0) when addr = REG_INT_CTRLSTAT else '0';
int_stat_wren <= wr_en and byte_en(1) when addr = REG_INT_CTRLSTAT else '0';
slave_addr_wren <= wr_en and byte_en(0) and not transfer when addr = REG_TWI_CTRL else '0';
twi_ctrl_wren <= wr_en and byte_en(1) when addr = REG_TWI_CTRL else '0';
dlenl_wren <= wr_en and byte_en(0) when addr = REG_DATA_LEN else '0';
dlenh_wren <= wr_en and byte_en(1) when addr = REG_DATA_LEN else '0';
soft_reset <= twi_ctrl_wren and in_data(TWI_SOFT_RESET);
start_transfer <= twi_ctrl_wren and in_data(TWI_TRANSFER) and not transfer;
tick_en <= '1' when presc_div = presc_cntr else '0';
process (rst, clk)
begin
if rising_edge(clk) then
-- resync input pins
scl_sen_meta <= scl_in;
scl_sen <= scl_sen_meta;
sda_sen_meta <= sda_in;
sda_sen <= sda_sen_meta;
-- clock divider register
if prescl_wren = '1' then
presc_div(7 downto 0) <= unsigned(in_data(7 downto 0));
end if;
if presch_wren = '1' then
presc_div(15 downto 8) <= unsigned(in_data(15 downto 8));
end if;
-- slave address register
if slave_addr_wren = '1' then
slave_addr <= in_data(7 downto 0);
end if;
-- TWI control register
if twi_ctrl_wren = '1' then
scl_ovr <= in_data(TWI_SCL_OVERRIDE);
sda_ovr <= in_data(TWI_SDA_OVERRIDE);
end if;
if (twi_ctrl_wren and not transfer) = '1' then
nostop <= in_data(TWI_NOSTOP);
nostart <= in_data(TWI_NOSTART);
end if;
if (soft_reset or end_transfer) = '1' then
transfer <= '0';
elsif start_transfer = '1' then
transfer <= '1';
end if;
-- int control register
if int_ctrl_wren = '1' then
compl_mask <= in_data(TWI_COMPL_MASK);
anack_mask <= in_data(TWI_ANACK_MASK);
dnack_mask <= in_data(TWI_DNACK_MASK);
end if;
-- int status register
if ((int_stat_wren and in_data(TWI_COMPL)) or start_transfer or soft_reset) = '1' then
compl <= '0';
elsif end_transfer = '1' then
compl <= anack_i nor dnack_i;
end if;
if ((int_stat_wren and in_data(TWI_ANACK)) or start_transfer or soft_reset) = '1' then
anack <= '0';
elsif end_transfer = '1' then
anack <= anack_i;
end if;
if ((int_stat_wren and in_data(TWI_DNACK)) or start_transfer or soft_reset) = '1' then
dnack <= '0';
elsif end_transfer = '1' then
dnack <= dnack_i;
end if;
-- data length register
if (transfer and (shift_reg_ld_data or shift_reg_ld_dummy)) = '1' then
data_len <= data_len - 1;
else
if dlenl_wren = '1' then
data_len(7 downto 0) <= unsigned(in_data(7 downto 0));
end if;
if dlenh_wren = '1' then
data_len(15 downto 8) <= unsigned(in_data(15 downto 8));
end if;
end if;
-- clock_processing
if (tick_en or prescl_wren or presch_wren) = '1' then
presc_cntr <= (others => '0');
else
presc_cntr <= presc_cntr + 1;
end if;
end if;
if rst = '1' then
scl_sen_meta <= '0';
scl_sen <= '0';
sda_sen_meta <= '0';
sda_sen <= '0';
scl_ovr <= '0';
sda_ovr <= '0';
transfer <= '0';
nostart <= '0';
nostop <= '0';
compl <= '0';
anack <= '0';
dnack <= '0';
compl_mask <= '0';
anack_mask <= '0';
dnack_mask <= '0';
data_len <= (others => '0');
presc_div <= (others => '0');
presc_cntr <= (others => '0');
slave_addr <= (others => '0');
end if;
end process;
slave_nack <= (sda_sen and symbol_tick_en) when twi_state = twi_st_addr else (sda_sen and symbol_tick_en and not slave_addr(0));
shift_reg_ld_addr <= bit_tick_en when twi_state = twi_st_start else '0';
shift_reg_ld_data <= state_tick_en and not slave_addr(0) and in_valid when twi_next_state = twi_st_data else '0';
shift_reg_ld_dummy <= state_tick_en and slave_addr(0) when twi_next_state = twi_st_data else '0';
shift_reg_ack_bit <= not nostop when data_len = 1 else '0';
in_ready_i <= tick_en and not slave_addr(0) when bit_phase = 0 and bit_cntr = 8 and data_len /= 0 else '0';
out_stall <= out_valid_i and not out_ready;
in_stall <= in_ready_i and not in_valid;
phase_tick_en <= tick_en and (out_stall nor in_stall) when bit_phase /= 3 or scl_sen = '1' else '0';
bit_tick_en <= phase_tick_en when bit_phase = 0 else '0';
symbol_tick_en <= bit_tick_en when bit_cntr = 8 else '0';
with twi_state select
state_tick_en <= bit_tick_en when twi_st_idle | twi_st_start | twi_st_stop,
symbol_tick_en when twi_st_addr | twi_st_data,
'0' when others;
scl_tick_en <= '0' when bit_phase = 1 else phase_tick_en;
bit_cntr_en <= bit_tick_en when twi_state = twi_st_addr or twi_state = twi_st_data else '0';
symbol_pending <= slave_addr(0) and bit_tick_en when twi_state = twi_st_data and bit_cntr = 7 else '0';
end_transfer <= phase_tick_en when twi_state = twi_st_end else '0';
process (rst, transfer, clk)
begin
if rising_edge(clk) then
-- upstream state machine
if (out_valid_i and out_ready) = '1' then
out_valid_i <= '0';
elsif symbol_pending = '1' then
out_valid_i <= '1';
end if;
-- bit phase processing
if phase_tick_en = '1' then
bit_phase <= bit_phase + 1;
end if;
-- SDA state machine
if soft_reset = '1' then
sda_i <= '0';
elsif phase_tick_en = '1' then
case twi_state is
when twi_st_start =>
sda_i <= bit_phase(0) xnor bit_phase(1);
when twi_st_data | twi_st_addr =>
sda_i <= not shift_reg(8);
when twi_st_stop =>
sda_i <= bit_phase(0) xor bit_phase(1);
when others =>
null;
end case;
end if;
-- SCL state machine
if soft_reset = '1' then
scl_i <= '0';
elsif scl_tick_en = '1' then
case twi_state is
when twi_st_start | twi_st_addr | twi_st_data =>
scl_i <= not bit_phase(1);
when twi_st_stop =>
scl_i <= '0';
when others =>
null;
end case;
end if;
-- bit counter
if bit_cntr_en = '1' then
if symbol_tick_en = '1' then
bit_cntr <= (others => '0');
else
bit_cntr <= bit_cntr + 1;
end if;
end if;
-- TWI state machine
if state_tick_en = '1' then
twi_state <= twi_next_state;
end if;
-- shift register process
if shift_reg_ld_addr = '1' then -- load shift register with slave address
shift_reg <= slave_addr & '1';
elsif shift_reg_ld_data = '1' then -- load shift register with next data octet
shift_reg <= in_octet & '1';
elsif shift_reg_ld_dummy = '1' then -- load shift register with dummy value
shift_reg <= (0 => shift_reg_ack_bit, others => '1');
elsif bit_tick_en = '1' then -- shift register and load next bit
shift_reg <= shift_reg(7 downto 0) & sda_sen;
end if;
-- remember ack bit
if symbol_tick_en = '1' and twi_state = twi_st_addr then
anack_i <= sda_sen;
end if;
if symbol_tick_en = '1' and twi_state = twi_st_data then
dnack_i <= sda_sen and not slave_addr(0);
end if;
end if;
if transfer = '0' then
twi_state <= twi_st_idle;
out_valid_i <= '0';
anack_i <= '0';
dnack_i <= '0';
bit_phase <= (others => '0');
bit_cntr <= (others => '0');
shift_reg <= (others => '0');
end if;
if rst = '1' then
scl_i <= '0';
sda_i <= '0';
end if;
end process;
twi_next_state <= twi_st_start when twi_state = twi_st_idle and nostart = '0' else
twi_st_addr when twi_state = twi_st_start else
twi_st_data when twi_state /= twi_st_stop and data_len /= 0 and slave_nack = '0' else
twi_st_stop when twi_state /= twi_st_stop and twi_state /= twi_st_end and nostop = '0' else
twi_st_end;
scl_act <= scl_i or scl_ovr;
sda_act <= sda_i or scl_ovr;
in_ready <= in_ready_i;
out_valid <= out_valid_i;
out_octet <= shift_reg(7 downto 0);
irq <= source_irq or sink_irq or (compl and compl_mask) or (anack and anack_mask) or (dnack and dnack_mask);
end architecture;
|
gpl-3.0
|
d21b584d35bdae7e44de2e0e8f6d00ed
| 0.625614 | 2.653635 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/flashyLights/ipcore_dir/memmory.vhd
| 1 | 5,373 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file memmory.vhd when simulating
-- the core, memmory. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY memmory IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END memmory;
ARCHITECTURE memmory_a OF memmory IS
-- synthesis translate_off
COMPONENT wrapped_memmory
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_memmory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 10,
c_addrb_width => 10,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "memmory.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 1024,
c_read_depth_b => 1024,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 1024,
c_write_depth_b => 1024,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_memmory
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END memmory_a;
|
gpl-3.0
|
da0f6bad720bdbf08a94ba7c8330138b
| 0.529127 | 4.033784 | false | false | false | false |
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