repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
missatisfaction/fpu
|
VHDL/fsqrt.vhd
| 1 | 2,571 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fsqrt is
Port (
clk: in STD_LOGIC;
f1 : in STD_LOGIC_VECTOR (31 downto 0);
ans: out STD_LOGIC_VECTOR (31 downto 0));
end fsqrt;
architecture fsqrt of fsqrt is
component table_sqrt is
port ( clk: in std_logic;
addrb: in std_logic_vector(9 downto 0);
doutb: out std_logic_vector(35 downto 0));
end component;
signal exp : std_logic_vector(7 downto 0);
signal fr : std_logic_vector(22 downto 0);
signal key : std_logic_vector(9 downto 0);
signal tb : std_logic_vector(35 downto 0);
signal e1,e2 : std_logic_vector(7 downto 0);
signal low : std_logic_vector(14 downto 0);
signal z1,z2 : std_logic;
signal val : std_logic_vector(22 downto 0);
signal comp,comp1 : std_logic_vector(13 downto 0);
signal flag : std_logic;
signal low_t : std_logic_vector(14 downto 0); --step1
signal e_t : std_logic_vector(7 downto 0); --step1
signal comp_t : std_logic_vector(27 downto 0); --step2
signal comp_l : std_logic_vector(13 downto 0); --step3
begin
tb_ram : table_sqrt
PORT MAP (
clk => clk,
addrb => key,
doutb => tb);
ans <= '0'&exp&fr;
step1 : process(clk,f1,low_t,e_t,key)
begin
if f1(23) = '1' then
key <= "00"&f1(22 downto 15);
low_t <= f1(14 downto 0);
e_t <= f1(30)&(not f1(30))&f1(29 downto 24);
else
key <= f1(22)&(not f1(22))&f1(21 downto 14);
low_t <= f1(13 downto 0)&'0';
e_t <= (('0'&f1(30 downto 24)) + 63);
end if;
if rising_edge(clk) then
e1 <= e_t;
low <= low_t;
if (f1(30 downto 0) = "000"&x"0000000") then
z1 <= '1';
else
z1 <= '0';
end if;
end if;
end process;
step2 : process(clk,z1,e1,low,tb,comp_t)
begin
if rising_edge(clk) then
comp_t <= low * tb(12 downto 0);
val <= tb(35 downto 13);
z2 <= z1;
e2 <= e1;
end if;
end process;
step3 : process(e2,z2,val,comp,comp1,flag,comp_t,comp_l)
begin
comp <= comp_t(27 downto 14);
comp1 <= comp_t(27 downto 14) + 1;
if (comp_t(13 downto 12) = "11" or (comp_t(13 downto 12) = "10" and ((comp_t(14) xor val(0)) = '1' or (not (comp_t(11 downto 0) = x"000"))))) then
flag <= '1';
else
flag <= '0';
end if;
if (flag = '1') then
comp_l <= comp1;
else
comp_l <= comp;
end if;
if z2 = '1' then
exp <= x"00";
fr <= "000"&x"00000";
else
exp <= e2;
fr <= val + comp_l;
end if;
end process;
end fsqrt;
|
apache-2.0
|
bf05e8d9fdf303fd25108595728f2885
| 0.563983 | 2.847176 | false | false | false | false |
mithro/soft-utmi
|
hdl/serdes/serdes_top.vhd
| 1 | 4,366 |
-- Recommended reading
-- This is called asynchronous communication or self-synchronous, also known as data and/or clock recovery
--
-- 1) XAPP224 (v2.5) July 11, 2005 -- Data Recovery -- Author: Nick Sawyer
-- 2) XAPP250 (v1.3.2) May 2, 2007 -- Clock and Data Recovery with Coded Data Streams -- Author: Leonard Dieguez
-- 3) XAPP861 (v1.1) July 20, 2007 -- Efficient 8X Oversampling Asynchronous Serial Data Recovery Using IDELAY -- Author: John F. Snow
-- 4) **** XAPP523 (v1.0) April 6, 2012 -- LVDS 4x Asynchronous Oversampling Using 7 Series FPGAs -- Author: Marc Defossez
-- 5) XAPP1064 (v1.2) November 19, 2013 -- Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s) -- Author: NIck Sawyer
-- CDC - clock-domain crossing circuit
-- http://forums.xilinx.com/t5/7-Series-FPGAs/7-series-ISERDES-OVERSAMPLE-bit-order-output/m-p/365627#M2455
-- *) UG381 (v1.6) February 14, 2014 -- Spartan-6 FPGA SelectIO Resources User Guide
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
library XAPP1064_serdes_macros;
use XAPP1064_serdes_macros.all;
entity serdes_top is port (
reset : in std_logic ; -- reset (active high)
d_p, d_n : in std_logic ;
ioclk : out std_logic ;
dummy_out : out std_logic_vector(7 downto 0)) ;
end serdes_top ;
architecture arch_serdes_top of serdes_top is
component serdes_1_to_n_clk_pll_s8_diff generic (
PLLD : integer := 4 ; -- Parameter to set division for PLL
PLLX : integer := 4 ; -- Parameter to set multiplier for PLL (7 for video links, 2 for DDR etc)
CLKIN_PERIOD : real := 2.0833333333333335 ; -- clock period (ns) of input clock on clkin_p
S : integer := 7 ; -- Parameter to set the serdes factor 1..8
BS : boolean := TRUE ; -- Parameter to enable bitslip TRUE or FALSE
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic ; -- Input from LVDS receiver pin
clkin_n : in std_logic ; -- Input from LVDS receiver pin
reset : in std_logic ; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0) ; -- Data to define pattern that bitslip should search for
pattern2 : in std_logic_vector(S-1 downto 0) ; -- Data to define alternate pattern that bitslip should search for
rxioclk : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_pll_x1 : out std_logic ; -- Global clock
bitslip : out std_logic ; -- Bitslip control line
datain : out std_logic_vector(S-1 downto 0) ; -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end component ;
-- Parameters for serdes factor and number of IO pins
constant S : integer := 7 ; -- Set the serdes factor to be 4
signal clk_iserdes_data : std_logic_vector(6 downto 0) ;
signal rx_bufg_x1 : std_logic ;
signal rxd : std_logic_vector(7 downto 0) ;
signal bitslip : std_logic ;
signal rst : std_logic ;
signal rx_serdesstrobe : std_logic ;
signal rx_bufpll_clk_xn : std_logic ;
signal rx_bufpll_lckd : std_logic ;
signal not_bufpll_lckd : std_logic ;
begin
rst <= reset ; -- active high reset pin
ioclk <= rx_bufpll_clk_xn ;
-- The source of the packet signals the Start of Packet (SOP) in high-speed mode by driving the D+ and D- lines
-- from the high-speed Idle state to the K state. This K is the first symbol of the SYNC pattern (NRZI sequence
-- KJKJKJKJ KJKJKJKJ KJKJKJKJ KJKJKJKK) as described in Section 7.1.10.
clkin : serdes_1_to_n_clk_pll_s8_diff generic map(
CLKIN_PERIOD => 2.0833333333333335,
PLLD => 1,
PLLX => 2,
S => S,
BS => TRUE) -- Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
port map (
clkin_p => d_p,
clkin_n => d_n,
rxioclk => rx_bufpll_clk_xn,
pattern1 => "1010100", -- default values for 7:1 video applications
pattern2 => "1010100",
rx_serdesstrobe => rx_serdesstrobe,
rx_bufg_pll_x1 => rx_bufg_x1,
bitslip => bitslip,
reset => rst,
datain => clk_iserdes_data,
rx_bufpll_lckd => rx_bufpll_lckd) ;
-- 6 Video Data Inputs
not_bufpll_lckd <= not rx_bufpll_lckd ;
end arch_serdes_top ;
|
apache-2.0
|
ed3e4e5a2fa3fb3cf6afe880c00d6eb2
| 0.666056 | 3.02984 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/uart/reciever.vhd
| 1 | 9,255 |
-- Reciever
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reciever is
port(
en: in std_logic;
clk: in std_logic;
res: in std_logic;
rx: in std_logic;
baud16_clk_en: in std_logic;
rx_data: out unsigned(7 downto 0);
rx_done: out std_logic
);
end entity reciever;
architecture reciever_arch of reciever is
type rx_state_type is (idle, start_sync, wait_for_sync, sync, wait_b0, get_b0, wait_b1, get_b1,wait_b2, get_b2,
wait_b3, get_b3,wait_b4, get_b4,wait_b5, get_b5,wait_b6, get_b6,wait_b7, get_b7,
wait_stopbit, store_data_0, store_data_1);
signal state: rx_state_type; -- state for RX FSM
signal sipo_val: unsigned(7 downto 0);
signal rx_rec_com, res_counter, shift_sipo_reg: std_logic; -- control signals for RX FSM
signal baud_clk_en: std_logic; -- this is an baud clock
signal count: unsigned(3 downto 0); -- this is rx counter value
begin
sipo_reg:
process(res, clk, rx, shift_sipo_reg) is
variable sipo_var: unsigned(7 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
sipo_var := (others => '0');
elsif shift_sipo_reg = '1' then
sipo_var(6 downto 0) := sipo_var(7 downto 1);
sipo_var(7) := rx;
end if;
end if;
sipo_val <= sipo_var;
end process;
rx_out_reg:
process(res, clk, rx_rec_com) is
variable out_reg: unsigned(7 downto 0);
begin
if rising_edge(clk) then
if(res = '1') then
out_reg := (others => '0');
elsif rx_rec_com = '1' then
out_reg := sipo_val;
end if;
end if;
rx_data <= out_reg;
end process;
rxcounter:
process(clk, res) is
variable counter: unsigned(3 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
counter := (others => '0');
elsif res_counter = '1' then
counter := (others => '0');
elsif baud16_clk_en = '1' then
counter := counter + 1;
end if;
end if;
count <= counter;
end process;
process(count, baud16_clk_en) is
begin
if count = x"F" then
baud_clk_en <= baud16_clk_en;
else
baud_clk_en <= '0';
end if;
end process;
process(clk, res, count, baud_clk_en, rx) is
begin
if rising_edge(clk) then
if res = '1' then
state <= idle;
else
case state is
when idle =>
if ((rx = '0') and (en = '1')) then
state <= start_sync;
else
state <= idle;
end if;
when start_sync => state <= wait_for_sync;
when wait_for_sync =>
if count = "0111" then
state <= sync;
else
state <= wait_for_sync;
end if;
when sync => state <= wait_b0;
when wait_b0 =>
if baud_clk_en = '1' then
state <= get_b0;
else
state <= wait_b0;
end if;
when get_b0 => state <= wait_b1;
when wait_b1 =>
if baud_clk_en = '1' then
state <= get_b1;
else
state <= wait_b1;
end if;
when get_b1 => state <= wait_b2;
when wait_b2 =>
if baud_clk_en = '1' then
state <= get_b2;
else
state <= wait_b2;
end if;
when get_b2 => state <= wait_b3;
when wait_b3 =>
if baud_clk_en = '1' then
state <= get_b3;
else
state <= wait_b3;
end if;
when get_b3 => state <= wait_b4;
when wait_b4 =>
if baud_clk_en = '1' then
state <= get_b4;
else
state <= wait_b4;
end if;
when get_b4 => state <= wait_b5;
when wait_b5 =>
if baud_clk_en = '1' then
state <= get_b5;
else
state <= wait_b5;
end if;
when get_b5 => state <= wait_b6;
when wait_b6 =>
if baud_clk_en = '1' then
state <= get_b6;
else
state <= wait_b6;
end if;
when get_b6 => state <= wait_b7;
when wait_b7 =>
if baud_clk_en = '1' then
state <= get_b7;
else
state <= wait_b7;
end if;
when get_b7 => state <= wait_stopbit;
when wait_stopbit =>
if baud_clk_en = '1' then
state <= store_data_0;
else
state <= wait_stopbit;
end if;
when store_data_0 => state <= store_data_1;
when store_data_1 => state <= idle;
end case;
end if;
end if;
end process;
process(state) is
begin
case state is
when idle => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when start_sync => rx_rec_com <= '0'; res_counter <= '1'; shift_sipo_reg <= '0'; rx_done <= '0';
when wait_for_sync => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when sync => rx_rec_com <= '0'; res_counter <= '1'; shift_sipo_reg <= '0'; rx_done <= '0';
when wait_b0 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b0 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b2 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b2 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b3 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b3 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b4 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b4 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b5 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b5 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b6 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b6 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b7 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b7 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_stopbit => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when store_data_0 => rx_rec_com <= '1'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when store_data_1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '1';
end case;
end process;
end architecture reciever_arch;
|
mit
|
552604fb600fbd7918834debf9858099
| 0.397342 | 3.867112 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/alt_dspbuilder_delay.vhd
| 4 | 1,878 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector(8-1 downto 0);
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
begin
alt_dspbuilder_delay_GNVTJPHWYT_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_0: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
54c5f50d3592ccbc8ab31794171c9f2d
| 0.680511 | 3.277487 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/sdram/sdram_driver.vhd
| 1 | 41,949 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdram_driver is
port(
clk_100: in std_logic;
res: in std_logic;
address: in std_logic_vector(22 downto 0);
data_in: in std_logic_vector(31 downto 0);
data_out: out std_logic_vector(31 downto 0);
busy: out std_logic;
wr_req: in std_logic;
rd_req: in std_logic;
data_out_ready: out std_logic;
ack: out std_logic;
sdram_ras_n: out std_logic;
sdram_cas_n: out std_logic;
sdram_we_n: out std_logic;
sdram_addr: out std_logic_vector(12 downto 0);
sdram_ba: out std_logic_vector(1 downto 0);
sdram_data: inout std_logic_vector(7 downto 0)
);
end entity sdram_driver;
architecture sdram_driver_arch of sdram_driver is
component data_io_buff is
port(
datain: in std_logic_vector (15 downto 0);
oe: in std_logic_vector (15 downto 0);
dataio: inout std_logic_vector (15 downto 0);
dataout: out std_logic_vector (15 downto 0)
);
end component;
--data from sdram (registered)
signal captured_data: std_logic_vector(7 downto 0);
--oe control signal for bidir buff
signal bidir_buff_oe, bidir_buff_oe_buff: std_logic;
--datainput to bidir buff
signal bidir_buff_datain, bidir_buff_datain_buff: std_logic_vector(7 downto 0);
--unregistered output from bidirbuff
signal sdram_dataout: std_logic_vector(7 downto 0);
--these signals are controling control outputs for sdram
signal sdram_addr_unbuff: std_logic_vector(12 downto 0);
signal sdram_ba_unbuff: std_logic_vector(1 downto 0);
signal sdram_control: std_logic_vector(2 downto 0);
--comands for sdram maped into vectors
constant com_device_deselect: std_logic_vector(2 downto 0):= "000";
constant com_no_operation: std_logic_vector(2 downto 0):= "111";
constant com_burst_stop: std_logic_vector(2 downto 0):= "110";
constant com_read: std_logic_vector(2 downto 0):= "101"; --bank and A0..A9 must be valid; A10 must be low
constant com_read_precharge: std_logic_vector(2 downto 0):= "101"; --A10 must be high
constant com_write: std_logic_vector(2 downto 0):= "100"; --A10 must be low
constant com_write_precharge: std_logic_vector(2 downto 0):= "100";--A10 must be high
constant com_bank_active: std_logic_vector(2 downto 0):= "011"; --bank and addr must be valid
constant com_precharge_select_bank: std_logic_vector(2 downto 0):= "010";--bank valid and A10 low; rest of addr dont care
constant com_precharge_all_banks: std_logic_vector(2 downto 0):= "010"; --A10 high; others dont care
constant com_cbr_auto_refresh: std_logic_vector(2 downto 0):= "001"; --everything dont care
constant com_mode_reg_set: std_logic_vector(2 downto 0):= "000"; --bank low; A10 low; A0..A9 valid
--put this constant on address bus it is configuration register
-- CAS = 2; burst = 4 words;
constant mode_register: std_logic_vector(12 downto 0) := "0000000100010";
--this signal is we into output register
signal write_input_data_reg: std_logic;
--clean refresh counter
signal refresh_counter_clean: std_logic;
--signalize refresh need
signal force_refresh: std_logic;
--for init seq
signal init_counter_val: unsigned(17 downto 0);
signal init_counter_clean: std_logic; -- clean startup counter
--main sdram FSM
type sdram_fsm_state_type is (
init_delay, init_precharge, init_precharge_wait,
init_refresh_0, init_refresh_1,
init_refresh_2, init_refresh_3,
init_refresh_4, init_refresh_5,
init_refresh_6, init_refresh_7,
init_refresh_0_wait, init_refresh_1_wait,
init_refresh_2_wait, init_refresh_3_wait,
init_refresh_4_wait, init_refresh_5_wait,
init_refresh_6_wait, init_refresh_7_wait,
init_mode_reg, init_mode_reg_wait, idle,
autorefresh, autorefresh_wait,
bank_active, bank_active_nop0, bank_active_nop1,
write_data, write_nop_0, write_nop_1, write_nop_2, write_nop_3, write_nop_4, write_nop_5, write_nop_6,
read_command, read_nop_0, read_nop_1, read_nop_2, read_nop_3, read_nop_4, read_nop_5, read_nop_6, read_completed
);
signal fsm_state: sdram_fsm_state_type := init_delay;
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of fsm_state : signal is "ONE-HOT";
--address parts
signal address_ba: std_logic_vector(1 downto 0);
signal address_row: std_logic_vector(12 downto 0);
signal address_col: std_logic_vector(9 downto 0);
--signals from command register
signal cmd_wr_req: std_logic;
--~ signal cmd_rd_req: std_logic;
signal cmd_address: std_logic_vector(22 downto 0);
signal cmd_data_in: std_logic_vector(31 downto 0);
signal write_cmd_reg: std_logic;
begin
--split address into multiple parts
address_ba <= cmd_address(22 downto 21);
address_row <= cmd_address(20 downto 8);
address_col <= cmd_address(7 downto 0) & "00";
--bidirectional buffer for DQ pins
sdram_dataout <= sdram_data;
sdram_data <= bidir_buff_datain_buff when bidir_buff_oe_buff = '1' else (others => 'Z');
process(clk_100) is
variable bidir_buff_oe_var: std_logic := '0';
begin
if rising_edge(clk_100) then
if res = '1' then
bidir_buff_oe_var := '0';
else
bidir_buff_oe_var := bidir_buff_oe;
end if;
end if;
bidir_buff_oe_buff <= bidir_buff_oe_var;
end process;
process(clk_100) is
variable bidir_buff_datain_var: std_logic_vector(7 downto 0) := x"00";
begin
if rising_edge(clk_100) then
if res = '1' then
bidir_buff_datain_var := (others => '0');
else
bidir_buff_datain_var := bidir_buff_datain;
end if;
end if;
bidir_buff_datain_buff <= bidir_buff_datain_var;
end process;
--register input data from sdram
process(clk_100) is
variable captured_data_var: std_logic_vector(7 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
captured_data_var := (others => '0');
else
captured_data_var := sdram_dataout;
end if;
end if;
captured_data <= captured_data_var;
end process;
--this is register for dataout
process(clk_100) is
variable input_data_register_var_low: std_logic_vector(7 downto 0) := (others => '0');
variable input_data_register_var_mlow: std_logic_vector(7 downto 0) := (others => '0');
variable input_data_register_var_mhigh: std_logic_vector(7 downto 0) := (others => '0');
variable input_data_register_var_high: std_logic_vector(7 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
input_data_register_var_low := (others => '0');
input_data_register_var_mlow := (others => '0');
input_data_register_var_mhigh := (others => '0');
input_data_register_var_high := (others => '0');
elsif write_input_data_reg = '1' then
input_data_register_var_high := input_data_register_var_mhigh;
input_data_register_var_mhigh := input_data_register_var_mlow;
input_data_register_var_mlow := input_data_register_var_low;
input_data_register_var_low := captured_data;
end if;
end if;
data_out <= input_data_register_var_high & input_data_register_var_mhigh & input_data_register_var_mlow & input_data_register_var_low;
end process;
--register all outputs
process(clk_100) is
variable sdram_ras_n_var: std_logic := '1';
variable sdram_cas_n_var: std_logic := '1';
variable sdram_we_n_var: std_logic := '1';
variable sdram_addr_var: std_logic_vector(12 downto 0) := (others => '0');
variable sdram_ba_var: std_logic_vector(1 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
sdram_ras_n_var := '1';
sdram_cas_n_var := '1';
sdram_we_n_var := '1';
sdram_addr_var := (others => '0');
sdram_ba_var := (others => '0');
else
sdram_addr_var := sdram_addr_unbuff;
sdram_ba_var := sdram_ba_unbuff;
sdram_ras_n_var := sdram_control(2);
sdram_cas_n_var := sdram_control(1);
sdram_we_n_var := sdram_control(0);
end if;
end if;
sdram_ras_n <= sdram_ras_n_var;
sdram_cas_n <= sdram_cas_n_var;
sdram_we_n <= sdram_we_n_var;
sdram_addr <= sdram_addr_var;
sdram_ba <= sdram_ba_var;
end process;
--refresh counter
process(clk_100) is
variable counter_var: unsigned(12 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' or refresh_counter_clean = '1' then
counter_var := (others => '0');
else
counter_var := counter_var + 1;
end if;
end if;
--refresh is needed each 7.8125 us
--this call it each 4.096 us
force_refresh <= counter_var(12);
end process;
--startup counter
process(clk_100) is
variable counter_var: unsigned(17 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' or init_counter_clean = '1' then
counter_var := (others => '0');
else
counter_var := counter_var + 1;
end if;
end if;
init_counter_val <= counter_var;
end process;
--register for command
process(clk_100) is
variable wr_req_var: std_logic := '0';
--~ variable rd_req_var: std_logic := '0';
variable address_var: std_logic_vector(22 downto 0) := (others => '0');
variable data_in_var: std_logic_vector(31 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
wr_req_var := '0';
--~ rd_req_var := '0';
address_var := (others => '0');
data_in_var := (others => '0');
elsif write_cmd_reg = '1' then
wr_req_var := wr_req;
--~ rd_req_var := rd_req;
address_var := address;
data_in_var := data_in;
end if;
end if;
cmd_wr_req <= wr_req_var;
--~ cmd_rd_req <= rd_req_var;
cmd_address <= address_var;
cmd_data_in <= data_in_var;
end process;
--main fsm
process(clk_100) is
begin
if rising_edge(clk_100) then
if res = '1' then
fsm_state <= init_delay;
else
case fsm_state is
when init_delay =>
if init_counter_val = 200000 then
fsm_state <= init_precharge;
else
fsm_state <= init_delay;
end if;
when init_precharge =>
fsm_state <= init_precharge_wait;
when init_precharge_wait =>
if init_counter_val = 2 then
fsm_state <= init_refresh_0;
else
fsm_state <= init_precharge_wait;
end if;
when init_refresh_0 =>
fsm_state <= init_refresh_0_wait;
when init_refresh_0_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_1;
else
fsm_state <= init_refresh_0_wait;
end if;
when init_refresh_1 =>
fsm_state <= init_refresh_1_wait;
when init_refresh_1_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_2;
else
fsm_state <= init_refresh_1_wait;
end if;
when init_refresh_2 =>
fsm_state <= init_refresh_2_wait;
when init_refresh_2_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_3;
else
fsm_state <= init_refresh_2_wait;
end if;
when init_refresh_3 =>
fsm_state <= init_refresh_3_wait;
when init_refresh_3_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_4;
else
fsm_state <= init_refresh_3_wait;
end if;
when init_refresh_4 =>
fsm_state <= init_refresh_4_wait;
when init_refresh_4_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_5;
else
fsm_state <= init_refresh_4_wait;
end if;
when init_refresh_5 =>
fsm_state <= init_refresh_5_wait;
when init_refresh_5_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_6;
else
fsm_state <= init_refresh_5_wait;
end if;
when init_refresh_6 =>
fsm_state <= init_refresh_6_wait;
when init_refresh_6_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_7;
else
fsm_state <= init_refresh_6_wait;
end if;
when init_refresh_7 =>
fsm_state <= init_refresh_7_wait;
when init_refresh_7_wait =>
if init_counter_val = 7 then
fsm_state <= init_mode_reg;
else
fsm_state <= init_refresh_7_wait;
end if;
when init_mode_reg =>
fsm_state <= init_mode_reg_wait;
when init_mode_reg_wait =>
if init_counter_val = 7 then
fsm_state <= idle;
else
fsm_state <= init_mode_reg_wait;
end if;
--there is idle process
when idle =>
if force_refresh = '1' then
fsm_state <= autorefresh;
elsif wr_req = '1' or rd_req = '1' then
fsm_state <= bank_active;
else
fsm_state <= idle;
end if;
--autorefresh stage
when autorefresh =>
fsm_state <= autorefresh_wait;
when autorefresh_wait =>
if init_counter_val = 7 then
fsm_state <= idle;
else
fsm_state <= autorefresh_wait;
end if;
--active bank and row
when bank_active =>
fsm_state <= bank_active_nop0;
when bank_active_nop0 =>
fsm_state <= bank_active_nop1;
when bank_active_nop1 =>
if cmd_wr_req = '1' then
fsm_state <= write_data;
else
fsm_state <= read_command;
end if;
-- write data into sdram
when write_data =>
fsm_state <= write_nop_0;
when write_nop_0 =>
fsm_state <= write_nop_1;
when write_nop_1 =>
fsm_state <= write_nop_2;
when write_nop_2 =>
fsm_state <= write_nop_3;
when write_nop_3 =>
fsm_state <= write_nop_4;
when write_nop_4 =>
fsm_state <= write_nop_5;
when write_nop_5 =>
fsm_state <= write_nop_6;
when write_nop_6 =>
fsm_state <= idle;
--read data block
when read_command =>
fsm_state <= read_nop_0;
when read_nop_0 =>
fsm_state <= read_nop_1;
when read_nop_1 =>
fsm_state <= read_nop_2;
when read_nop_2 =>
fsm_state <= read_nop_3;
when read_nop_3 =>
fsm_state <= read_nop_4;
when read_nop_4 =>
fsm_state <= read_nop_5;
when read_nop_5 =>
fsm_state <= read_nop_6;
when read_nop_6 =>
fsm_state <= read_completed;
when read_completed =>
fsm_state <= idle;
end case;
end if;
end if;
end process;
process(fsm_state, address_row, address_ba, address_col, cmd_data_in) is
begin
case fsm_state is
when init_delay =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_precharge =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_precharge_all_banks;
sdram_addr_unbuff <= "0010000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_precharge_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_0 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_0_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_1 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_1_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_2 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_2_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_3 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_3_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_4 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_4_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_5 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_5_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_6 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_6_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_7 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_7_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_mode_reg =>
init_counter_clean <= '1';
refresh_counter_clean <= '1';
bidir_buff_oe <= '0';
sdram_control <= com_mode_reg_set;
sdram_addr_unbuff <= mode_register;
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_mode_reg_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when idle =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '0';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '1';
ack <= '0';
when autorefresh =>
init_counter_clean <= '1';
refresh_counter_clean <= '1';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when autorefresh_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when bank_active =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_bank_active;
sdram_addr_unbuff <= address_row;
sdram_ba_unbuff <= address_ba;
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '1';
when bank_active_nop0 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when bank_active_nop1 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_data =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_write_precharge;
sdram_addr_unbuff <= "001" & address_col;
sdram_ba_unbuff <= address_ba;
bidir_buff_datain <= cmd_data_in(31 downto 24);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_0 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= cmd_data_in(23 downto 16);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_1 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= cmd_data_in(15 downto 8);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_2 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= cmd_data_in(7 downto 0);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_3 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_4 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_5 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_6 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_command =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_read_precharge;
sdram_addr_unbuff <= "001" & address_col;
sdram_ba_unbuff <= address_ba;
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_0 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_1 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_2 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_3 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_4 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_5 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_6 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_completed =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '1';
write_cmd_reg <= '0';
ack <= '0';
end case;
end process;
end architecture sdram_driver_arch;
|
mit
|
c9989065a62972d75bc9822d3f88f232
| 0.430451 | 4.189454 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/sdram/bus_interface.vhd
| 1 | 3,941 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bus_interface is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--fifos
wrfifo_datain: out std_logic_vector(54 downto 0);
wrfifo_write: out std_logic;
wrfifo_wrempty: in std_logic;
rdfifo_address_datain: out std_logic_vector(22 downto 0);
rdfifo_address_we: out std_logic;
rdfifo_address_wrempty: in std_logic;
rdfifo_data_rdreq: out std_logic;
rdfifo_data_dataout: in std_logic_vector(31 downto 0);
rdfifo_data_rdempty: in std_logic
);
end entity bus_interface;
architecture bus_interface_arch of bus_interface is
signal miso_en, cs: std_logic;
type fsm_state_type is (idle, rd_state, wr_state, wait_for_data,read_data, ack_state);
signal fsm_state: fsm_state_type;
begin
wrfifo_datain <= address(22 downto 0) & data_mosi;
rdfifo_address_datain <= address(22 downto 0);
data_miso <= rdfifo_data_dataout when miso_en = '1' else (others => 'Z');
process(address) is begin
if (unsigned(address) >= BASE_ADDRESS and unsigned(address) <= (BASE_ADDRESS + (2**23)-1)) then
cs <= '1';
else
cs <= '0';
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
if res = '1' then
fsm_state <= idle;
else
case fsm_state is
when idle =>
if (RD = '1') and (cs = '1') and (rdfifo_address_wrempty = '1') then
fsm_state <= rd_state;
elsif (WR = '1') and (cs = '1') and (wrfifo_wrempty = '1') then
fsm_state <= wr_state;
else
fsm_state <= idle;
end if;
when rd_state =>
fsm_state <= wait_for_data;
when wr_state =>
fsm_state <= ack_state;
when wait_for_data =>
if rdfifo_data_rdempty = '0' then
fsm_state <= read_data;
else
fsm_state <= wait_for_data;
end if;
when read_data =>
fsm_state <= ack_state;
when ack_state =>
fsm_state <= idle;
end case;
end if;
end if;
end process;
process(fsm_state) is
begin
case fsm_state is
when idle =>
rdfifo_data_rdreq <= '0'; rdfifo_address_we <= '0'; wrfifo_write <= '0'; ack <= '0';
when rd_state =>
rdfifo_data_rdreq <= '0'; rdfifo_address_we <= '1'; wrfifo_write <= '0'; ack <= '0';
when wr_state =>
rdfifo_data_rdreq <= '0'; rdfifo_address_we <= '0'; wrfifo_write <= '1'; ack <= '0';
when wait_for_data =>
rdfifo_data_rdreq <= '0'; rdfifo_address_we <= '0'; wrfifo_write <= '0'; ack <= '0';
when read_data =>
rdfifo_data_rdreq <= '1'; rdfifo_address_we <= '0'; wrfifo_write <= '0'; ack <= '0';
when ack_state =>
rdfifo_data_rdreq <= '0'; rdfifo_address_we <= '0'; wrfifo_write <= '0'; ack <= '1';
end case;
end process;
miso_en <= '1' when (cs = '1') and (RD = '1') else '0';
end architecture bus_interface_arch;
|
mit
|
5091d992645ad908cdf0acf0a941e106
| 0.47526 | 3.960804 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/showcase0.vhd
| 1 | 5,141 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Every HW component class has to be derived from :class:`hwt.synthesizer.unit.Unit` class
--
-- .. hwt-autodoc::
--
ENTITY Showcase0 IS
PORT(
a : IN UNSIGNED(31 DOWNTO 0);
b : IN SIGNED(31 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clk : IN STD_LOGIC;
cmp_0 : OUT STD_LOGIC;
cmp_1 : OUT STD_LOGIC;
cmp_2 : OUT STD_LOGIC;
cmp_3 : OUT STD_LOGIC;
cmp_4 : OUT STD_LOGIC;
cmp_5 : OUT STD_LOGIC;
contOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
e : IN STD_LOGIC;
f : OUT STD_LOGIC;
fitted : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
g : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
h : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
j : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
k : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_0 : OUT STD_LOGIC;
output : OUT STD_LOGIC;
rst_n : IN STD_LOGIC;
sc_signal : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF Showcase0 IS
TYPE arr_t_0 IS ARRAY (3 DOWNTO 0) OF SIGNED(7 DOWNTO 0);
TYPE arr_t_1 IS ARRAY (3 DOWNTO 0) OF UNSIGNED(7 DOWNTO 0);
CONSTANT const_private_signal : UNSIGNED(31 DOWNTO 0) := UNSIGNED'(X"0000007B");
SIGNAL fallingEdgeRam : arr_t_0;
SIGNAL r : STD_LOGIC := '0';
SIGNAL r_0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
SIGNAL r_1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
SIGNAL r_next : STD_LOGIC;
SIGNAL r_next_0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL r_next_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
CONSTANT rom : arr_t_1 := (
UNSIGNED'(X"00"),
UNSIGNED'(X"01"),
UNSIGNED'(X"02"),
UNSIGNED'(X"03"));
BEGIN
assig_process_c: PROCESS(a, b)
VARIABLE tmpCastExpr_0 : UNSIGNED(31 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a + UNSIGNED(b);
c <= STD_LOGIC_VECTOR(tmpCastExpr_0);
END PROCESS;
cmp_0 <= '1' WHEN (a < UNSIGNED'(X"00000004")) ELSE '0';
cmp_1 <= '1' WHEN (a > UNSIGNED'(X"00000004")) ELSE '0';
cmp_2 <= '1' WHEN (b <= SIGNED'(X"00000004")) ELSE '0';
cmp_3 <= '1' WHEN (b >= SIGNED'(X"00000004")) ELSE '0';
cmp_4 <= '1' WHEN (b /= SIGNED'(X"00000004")) ELSE '0';
cmp_5 <= '1' WHEN (b = SIGNED'(X"00000004")) ELSE '0';
contOut <= STD_LOGIC_VECTOR(const_private_signal);
f <= r;
assig_process_fallingEdgeRam: PROCESS(clk)
VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
VARIABLE tmpCastExpr_2 : SIGNED(7 DOWNTO 0);
VARIABLE tmpCastExpr_1 : UNSIGNED(7 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a(7 DOWNTO 0);
tmpCastExpr_2 := fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1)));
tmpCastExpr_1 := UNSIGNED(tmpCastExpr_2);
IF FALLING_EDGE(clk) THEN
fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1))) <= SIGNED(tmpCastExpr_0);
k <= X"000000" & STD_LOGIC_VECTOR(tmpCastExpr_1);
END IF;
END PROCESS;
assig_process_fitted: PROCESS(a)
VARIABLE tmpCastExpr_0 : UNSIGNED(15 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a(15 DOWNTO 0);
fitted <= STD_LOGIC_VECTOR(tmpCastExpr_0);
END PROCESS;
assig_process_g: PROCESS(a, b)
VARIABLE tmpCastExpr_0 : UNSIGNED(5 DOWNTO 0);
BEGIN
tmpCastExpr_0 := a(5 DOWNTO 0);
g <= (a(1) AND b(1)) & ((a(0) XOR b(0)) OR a(1)) & STD_LOGIC_VECTOR(tmpCastExpr_0);
END PROCESS;
assig_process_h: PROCESS(a, r)
BEGIN
IF a(2) = '1' THEN
IF r = '1' THEN
h <= X"00";
ELSIF a(1) = '1' THEN
h <= X"01";
ELSE
h <= X"02";
END IF;
END IF;
END PROCESS;
assig_process_j: PROCESS(clk)
VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
BEGIN
tmpCastExpr_0 := rom(TO_INTEGER(UNSIGNED(r_1)));
IF RISING_EDGE(clk) THEN
j <= STD_LOGIC_VECTOR(tmpCastExpr_0);
END IF;
END PROCESS;
out_0 <= '0';
output <= 'X';
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r_1 <= "00";
r_0 <= "00";
r <= '0';
ELSE
r_1 <= r_next_1;
r_0 <= r_next_0;
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next_0 <= i;
r_next_1 <= r_0;
assig_process_r_next_1: PROCESS(e, r)
BEGIN
IF NOT r = '1' THEN
r_next <= e;
ELSE
r_next <= r;
END IF;
END PROCESS;
assig_process_sc_signal: PROCESS(a)
BEGIN
CASE a IS
WHEN UNSIGNED'(X"00000001") =>
sc_signal <= X"00";
WHEN UNSIGNED'(X"00000002") =>
sc_signal <= X"01";
WHEN UNSIGNED'(X"00000003") =>
sc_signal <= X"03";
WHEN OTHERS =>
sc_signal <= X"04";
END CASE;
END PROCESS;
END ARCHITECTURE;
|
mit
|
3a645bb3adb4c198a707cfbd01c44e9e
| 0.529274 | 3.411413 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_mul/fp_mul_sim/dspba_library_package.vhd
| 12 | 2,231 |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
mit
|
3af7930e4a0b1813035da6814f0a5c35
| 0.590318 | 4.249524 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/clock_generator_ddr_s8_diff.vhd
| 1 | 6,667 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: clock_generator_ddr_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: BUFIO2 Based DDR clock generator. Takes in a differential clock
-- and instantiates two sets of 2 BUFIO2s, one for each half bank
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity clock_generator_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclkap : out std_logic ; -- A P ioclock from BUFIO2
ioclkan : out std_logic ; -- A N ioclock from BUFIO2
serdesstrobea : out std_logic ; -- A serdes strobe from BUFIO2
ioclkbp : out std_logic ; -- B P ioclock from BUFIO2 - leave open if not required
ioclkbn : out std_logic ; -- B N ioclock from BUFIO2 - leave open if not required
serdesstrobeb : out std_logic ; -- B serdes strobe from BUFIO2 - leave open if not required
gclk : out std_logic) ; -- global clock output from BUFIO2
end clock_generator_ddr_s8_diff ;
architecture arch_clock_generator_ddr_s8_diff of clock_generator_ddr_s8_diff is
signal clkint : std_logic ; --
signal gclk_int : std_logic ; --
signal freqgen_in_p : std_logic ; --
signal tx_bufio2_x1 : std_logic ; --
begin
gclk <= gclk_int ;
iob_freqgen_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => freqgen_in_p);
bufio2_inst1 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => FALSE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => TRUE) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclkap, -- Output Clock for IO
DIVCLK => tx_bufio2_x1, -- Output Divided Clock
SERDESSTROBE => serdesstrobea) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst2 : BUFIO2 generic map(
I_INVERT => TRUE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => FALSE) --
port map (
I => freqgen_in_p, -- N_clk input from IDELAY
IOCLK => ioclkan, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst3 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => FALSE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => TRUE) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclkbp, -- Output Clock for IO
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => serdesstrobeb) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst4 : BUFIO2 generic map(
I_INVERT => TRUE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => FALSE) --
port map (
I => freqgen_in_p, -- N_clk input from IDELAY
IOCLK => ioclkbn, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
bufg_tx : BUFG port map (I => tx_bufio2_x1, O => gclk_int) ;
end arch_clock_generator_ddr_s8_diff ;
|
apache-2.0
|
427887f409bcd643052077efe577b8d3
| 0.568172 | 3.931014 | false | false | false | false |
tec499-20142/t01-warmup
|
sim/tb/uartb.vhd
| 1 | 3,456 |
----------------------------------------------------------------------------------
-- Creation Date: 13:07:48 27/03/2011
-- Module Name: RS232/UART Interface - Testbench
-- Used TAB of 4 Spaces
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity uart_tb is
end uart_tb;
architecture Behavioral of uart_tb is
----------------------------------------------
-- Constants
----------------------------------------------
constant MAIN_CLK_PER : time := 20 ns; -- 50 MHz
constant MAIN_CLK : integer := 50;
constant BAUD_RATE : integer := 9600; -- Bits per Second
constant RST_LVL : std_logic := '1'; -- Active Level of Reset
constant TEST_RX : std_logic := '0';
----------------------------------------------
-- Signal Declaration
----------------------------------------------
-- Clock and reset Signals
signal clk_50m : std_logic := '0';
signal rst : std_logic;
signal test : std_logic;
-- Transceiver Interface
signal data_from_transceiver : std_logic := '1';
-- uPC Interface
signal rx_ready : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
-- Testbench Signals
signal uart_clk : std_logic := '0';
begin
----------------------------------------------
-- Components Instantiation
----------------------------------------------
uut:entity work.uart
generic map(
CLK_FREQ => MAIN_CLK, -- Main frequency (MHz)
SER_FREQ => BAUD_RATE -- Baud rate (bps)
)
port map(
-- Control
clk => clk_50m, -- Main clock
rst => rst, -- Main reset
-- External Interface
rx => data_from_transceiver, -- RS232 received serial data
-- uPC Interface
rx_ready => rx_ready, -- Received data ready to uPC read
rx_data => rx_data -- Received data
);
----------------------------------------------
-- Main Signals Generation
----------------------------------------------
-- Main Clock generation
main_clock_generation:process
begin
wait for MAIN_CLK_PER/2;
clk_50m <= not clk_50m;
end process;
-- UART Clock generation
uart_clock_generation:process
begin
wait for (MAIN_CLK_PER*5208)/2;
uart_clk <= not uart_clk;
end process;
-- RX Clock generation
rx_clock_generation:process
begin
wait for (MAIN_CLK_PER*5100*2);
data_from_transceiver <= not data_from_transceiver; -- start bit
wait for (MAIN_CLK_PER*5208);
data_from_transceiver <= not data_from_transceiver; --primeiro bit (1)
wait for (MAIN_CLK_PER*5208);
data_from_transceiver <= not data_from_transceiver; --segundo bit (0)
wait for (MAIN_CLK_PER*5208);
data_from_transceiver <= data_from_transceiver; --terceiro bit (0)
wait for (MAIN_CLK_PER*5208);
data_from_transceiver <= data_from_transceiver; -- quarto (0)
wait for (MAIN_CLK_PER*5208);
data_from_transceiver <= data_from_transceiver; -- quinto (0)
wait for (MAIN_CLK_PER*5208);
data_from_transceiver <= data_from_transceiver; -- sexto (0)
wait for (MAIN_CLK_PER*5208);
data_from_transceiver <= data_from_transceiver; -- setimo (0)
wait for (MAIN_CLK_PER*5208);
data_from_transceiver <= data_from_transceiver; -- oitavo (0)
wait for (MAIN_CLK_PER*5208);
data_from_transceiver <= not data_from_transceiver; --Stop bit
end process;
-- Reset generation
rst <= RST_LVL, not RST_LVL after MAIN_CLK_PER*5;
end Behavioral;
|
gpl-2.0
|
90f98a787264617d1e4abe2e9b4156eb
| 0.563947 | 3.358601 | false | false | false | false |
Godoakos/conway-vhdl
|
ipcore_dir/clkgen.vhd
| 2 | 3,174 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : clkgen.vhd
-- /___/ /\ Timestamp : 01/16/2015 21:46:51
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st D:\Docs\Xilinx\ConwayFinal\ipcore_dir\.\clkgen.xaw D:\Docs\Xilinx\ConwayFinal\ipcore_dir\.\clkgen
--Design Name: clkgen
--Device: xc3s500e-4fg320
--
-- Module clkgen
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.03 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity clkgen is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end clkgen;
architecture BEHAVIORAL of clkgen is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
mit
|
f7ed5c41df26fe5c0c6c7e4dc3ade38b
| 0.458412 | 3.801198 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/id.vhd
| 1 | 47,743 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity id is
port(
clk: in std_logic;
res: in std_logic;
instr_opcode: in std_logic_vector(7 downto 0);
flag: in std_logic;
ack: in std_logic;
int: in std_logic;
swirq: out std_logic;
we: out std_logic;
oe: out std_logic;
int_accept: out std_logic;
int_completed: out std_logic;
data_c_sel: out std_logic_vector(2 downto 0);
data_a_sel: out std_logic_vector(3 downto 0);
data_b_sel: out std_logic_vector(2 downto 0);
force_we_reg_14: out std_logic;
inc_r14: out std_logic;
inc_r15: out std_logic;
dec_r15: out std_logic;
instruction_we: out std_logic;
regfile_c_we: out std_logic
);
end entity id;
architecture id_arch of id is
type id_state_type is (
start, start_inc, start_inc_intcmp, start_dec, start_wait, start_decode, start_calli, start_call,
intrq, intrq_set, intrq_inc, intrq_inc_set, intrq_dec, intrq_dec_set, intrq_calli, intrq_call,
ret, reti, swi,
call, calli,
pop, push,
ld, ldi, st, sti,
bz_bnz_set, bzi_bnzi_set,
mvil, mvih, mvia, barrel, alu,
cmp,
div, div_w0, div_w1, div_w2, div_w3, div_w4, div_w5, div_w6, div_w7,
div_w8, div_w9, div_w10, div_w11, div_w12, div_w13, div_w14, div_done,
faddsub, faddsub_done,
fdiv, fdiv_w0, fdiv_w1, fdiv_w2, fdiv_w3, fdiv_w4, fdiv_w5, fdiv_w6, fdiv_done,
fmul, fmul_w0, fmul_done
);
signal id_state: id_state_type;
constant data_a_arg_mvia: std_logic_vector(3 downto 0) := "0000";
constant data_a_arg_branch: std_logic_vector(3 downto 0) := "0001";
constant data_a_arg_st: std_logic_vector(3 downto 0) := "0010";
constant data_a_arg_mvi: std_logic_vector(3 downto 0) := "0011";
constant data_a_int_addr: std_logic_vector(3 downto 0) := "0100";
constant data_a_pc: std_logic_vector(3 downto 0) := "0101";
constant data_a_sp: std_logic_vector(3 downto 0) := "0110";
constant data_a_sp_plus: std_logic_vector(3 downto 0) := "0111";
constant data_a_sp_minus: std_logic_vector(3 downto 0) := "1000";
constant data_a_regfile: std_logic_vector(3 downto 0) := "1001";
constant data_b_regfile: std_logic_vector(2 downto 0) := "000";
constant data_b_regfile_a: std_logic_vector(2 downto 0) := "001";
constant data_b_pc: std_logic_vector(2 downto 0) := "010";
constant data_b_arg_call: std_logic_vector(2 downto 0) := "011";
constant data_b_reg0: std_logic_vector(2 downto 0) := "100";
constant data_c_fpu: std_logic_vector(2 downto 0) := "000";
constant data_c_cmp: std_logic_vector(2 downto 0) := "001";
constant data_c_alu: std_logic_vector(2 downto 0) := "010";
constant data_c_barrel: std_logic_vector(2 downto 0) := "011";
constant data_c_miso: std_logic_vector(2 downto 0) := "100";
constant data_c_mvil: std_logic_vector(2 downto 0) := "101";
constant data_c_mvih: std_logic_vector(2 downto 0) := "110";
constant data_c_aorb: std_logic_vector(2 downto 0) := "111";
constant data_a_dontcare: std_logic_vector(3 downto 0) := "----";
constant data_b_dontcare: std_logic_vector(2 downto 0) := "---";
constant data_c_dontcare: std_logic_vector(2 downto 0) := "---";
begin
decoder: process(clk) is
begin
if rising_edge(clk) then
if res = '1' then
id_state <= start;
else
case id_state is
when start =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_inc =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_calli =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_call =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_inc_intcmp =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_dec =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_wait =>
case ack is
when '1' => id_state <= start_decode;
when others => id_state <= start_wait;
end case;
when start_decode =>
case instr_opcode(7) is
when '1' =>
case instr_opcode(6 downto 4) is
when "000" => id_state <= call;
when "001" => id_state <= ld;
when "010" => id_state <= st;
when "011" =>
case flag is
when '1' => id_state <= bz_bnz_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "100" =>
case flag is
when '0' => id_state <= bz_bnz_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "101" => id_state <= mvia;
when others => id_state <= start;
end case;
when others =>
case instr_opcode(4 downto 0) is
when "00001" => id_state <= ret;
when "00010" => id_state <= reti;
when "00011" => id_state <= calli;
when "00100" => id_state <= push;
when "00101" => id_state <= pop;
when "00110" => id_state <= ldi;
when "00111" => id_state <= sti;
when "01000" =>
case flag is
when '0' => id_state <= bzi_bnzi_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "01001" =>
case flag is
when '1' => id_state <= bzi_bnzi_set;
when others =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
when "01010" => id_state <= cmp;
when "01011" => id_state <= cmp;
when "01100" => id_state <= alu;
when "01101" => id_state <= div;
when "01110" => id_state <= barrel;
when "01111" => id_state <= faddsub;
when "10000" => id_state <= fmul;
when "10001" => id_state <= fdiv;
when "10010" => id_state <= mvil;
when "10011" => id_state <= mvih;
when "10100" => id_state <= swi;
when others => id_state <= start;
end case;
end case;
when intrq =>
case ack is
when '1' => id_state <= intrq_set;
when others => id_state <= intrq;
end case;
when intrq_set =>
id_state <= start;
when intrq_calli =>
case ack is
when '1' => id_state <= intrq_set;
when others => id_state <= intrq_calli;
end case;
when intrq_call =>
case ack is
when '1' => id_state <= intrq_set;
when others => id_state <= intrq_call;
end case;
when intrq_inc =>
case ack is
when '1' => id_state <= intrq_inc_set;
when others => id_state <= intrq_inc;
end case;
when intrq_inc_set =>
id_state <= start_inc;
when intrq_dec =>
case ack is
when '1' => id_state <= intrq_dec_set;
when others => id_state <= intrq_dec;
end case;
when intrq_dec_set =>
id_state <= start;
when ret =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_inc;
when others => id_state <= start_inc;
end case;
when others => id_state <= ret;
end case;
when reti =>
case ack is
when '1' => id_state <= start_inc_intcmp;
when others => id_state <= reti;
end case;
when call =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_call;
when others => id_state <= start_call;
end case;
when others => id_state <= call;
end case;
when calli =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_calli;
when others => id_state <= start_calli;
end case;
when others => id_state <= calli;
end case;
when pop =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_inc;
when others => id_state <= start_inc;
end case;
when others => id_state <= pop;
end case;
when push =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq_dec;
when others => id_state <= start_dec;
end case;
when others => id_state <= push;
end case;
when ld =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= ld;
end case;
when ldi =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= ldi;
end case;
when st =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= st;
end case;
when sti =>
case ack is
when '1' =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when others => id_state <= sti;
end case;
when bz_bnz_set =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when bzi_bnzi_set =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when mvil =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when mvih =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when mvia =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when barrel =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when alu =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when cmp =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when div => id_state <= div_w0;
when div_w0 => id_state <= div_w1;
when div_w1 => id_state <= div_w2;
when div_w2 => id_state <= div_w3;
when div_w3 => id_state <= div_w4;
when div_w4 => id_state <= div_w5;
when div_w5 => id_state <= div_w6;
when div_w6 => id_state <= div_w7;
when div_w7 => id_state <= div_w8;
when div_w8 => id_state <= div_w9;
when div_w9 => id_state <= div_w10;
when div_w10 => id_state <= div_w11;
when div_w11 => id_state <= div_w12;
when div_w12 => id_state <= div_w13;
when div_w13 => id_state <= div_w14;
when div_w14 => id_state <= div_done;
when div_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when faddsub => id_state <= faddsub_done;
when faddsub_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when fmul => id_state <= fmul_w0;
when fmul_w0 => id_state <= fmul_done;
when fmul_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when fdiv => id_state <= fdiv_w0;
when fdiv_w0 => id_state <= fdiv_w1;
when fdiv_w1 => id_state <= fdiv_w2;
when fdiv_w2 => id_state <= fdiv_w3;
when fdiv_w3 => id_state <= fdiv_w4;
when fdiv_w4 => id_state <= fdiv_w5;
when fdiv_w5 => id_state <= fdiv_w6;
when fdiv_w6 => id_state <= fdiv_done;
when fdiv_done =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
when swi =>
case int is
when '1' => id_state <= intrq;
when others => id_state <= start;
end case;
end case;
end if;
end if;
end process;
outputs: process(id_state) is begin
case id_state is
when start =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_inc =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '1'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_inc_intcmp =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '1';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '1'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_dec =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_wait =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_pc;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_decode =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '1'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_dontcare;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when start_calli =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when start_call =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '1'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_arg_mvia;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when ret =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '0';
when reti =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '0';
when call =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when calli =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when pop =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '1';
when push =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when ld =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvia;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '1';
when ldi =>
we <= '0'; oe <= '1'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_miso;
regfile_c_we <= '1';
when st =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_st;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when sti =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when bz_bnz_set =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_branch;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when bzi_bnzi_set =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when mvil =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvi;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_mvil;
regfile_c_we <= '1';
when mvih =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvi;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_mvih;
regfile_c_we <= '1';
when mvia =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_arg_mvia;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '1';
when barrel =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_barrel;
regfile_c_we <= '1';
when alu =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '1';
when cmp =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_cmp;
regfile_c_we <= '1';
when div =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w0 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w1 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w2 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w3 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w4 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w5 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w6 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w7 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w8 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w9 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w10 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w11 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w12 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w13 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_w14 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '0';
when div_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_alu;
regfile_c_we <= '1';
when faddsub =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when faddsub_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '1';
when fdiv =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w0 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w1 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w2 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w3 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w4 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w5 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_w6 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fdiv_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '1';
when fmul =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fmul_w0 =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '0';
when fmul_done =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_regfile;
data_b_sel <= data_b_regfile;
data_c_sel <= data_c_fpu;
regfile_c_we <= '1';
when intrq =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_set =>
we <= '0'; oe <= '0'; int_accept <= '1'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_int_addr;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when intrq_inc =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_plus;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_inc_set =>
we <= '0'; oe <= '0'; int_accept <= '1'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_int_addr;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when intrq_dec =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp_minus;
data_b_sel <= data_b_pc;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_dec_set =>
we <= '0'; oe <= '0'; int_accept <= '1'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '1';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '1';
data_a_sel <= data_a_int_addr;
data_b_sel <= data_b_reg0;
data_c_sel <= data_c_aorb;
regfile_c_we <= '0';
when intrq_call =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_arg_call;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when intrq_calli =>
we <= '1'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '0'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_sp;
data_b_sel <= data_b_regfile_a;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
when swi =>
we <= '0'; oe <= '0'; int_accept <= '0'; int_completed <= '0';
swirq <= '1'; instruction_we <= '0'; force_we_reg_14 <= '0';
inc_r14 <= '0'; inc_r15 <= '0'; dec_r15 <= '0';
data_a_sel <= data_a_dontcare;
data_b_sel <= data_b_dontcare;
data_c_sel <= data_c_dontcare;
regfile_c_we <= '0';
end case;
end process;
end architecture id_arch;
|
mit
|
23c1fdd90c4cef4182d43befef723f7a
| 0.363718 | 3.84064 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/arithmetic/VhdlVectorAutoCastExample.vhd
| 1 | 1,453 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY VhdlVectorAutoCastExample IS
PORT(
a : IN STD_LOGIC;
b : OUT STD_LOGIC;
c : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
e : OUT STD_LOGIC;
f : IN STD_LOGIC;
g : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
i : OUT STD_LOGIC;
j : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF VhdlVectorAutoCastExample IS
BEGIN
b <= a;
c(0) <= a;
e <= d(0);
assig_process_i: PROCESS(f, g)
VARIABLE tmp_std_logic2vector_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
VARIABLE tmpCastExpr_0 : UNSIGNED(0 DOWNTO 0);
VARIABLE tmpTypeConv_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
tmp_std_logic2vector_0(0) := f;
tmpCastExpr_0 := UNSIGNED(tmp_std_logic2vector_0) + UNSIGNED(g);
tmpTypeConv_0 := STD_LOGIC_VECTOR(tmpCastExpr_0);
i <= tmpTypeConv_0(0);
END PROCESS;
assig_process_j: PROCESS(f, g)
VARIABLE tmp_std_logic2vector_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
VARIABLE tmpCastExpr_0 : UNSIGNED(0 DOWNTO 0);
VARIABLE tmpTypeConv_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
tmp_std_logic2vector_0(0) := f;
tmpCastExpr_0 := UNSIGNED(g) + UNSIGNED(tmp_std_logic2vector_0);
tmpTypeConv_0 := STD_LOGIC_VECTOR(tmpCastExpr_0);
j <= tmpTypeConv_0(0);
END PROCESS;
END ARCHITECTURE;
|
mit
|
11647fa7b3ca99f33c4add08479dbb6b
| 0.610461 | 3.386946 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/hierarchy/netFilter.vhd
| 1 | 24,029 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY HeadFieldExtractor IS
PORT(
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_last : IN STD_LOGIC;
din_ready : OUT STD_LOGIC;
din_valid : IN STD_LOGIC;
dout_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dout_last : OUT STD_LOGIC;
dout_ready : IN STD_LOGIC;
dout_valid : OUT STD_LOGIC;
headers_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
headers_last : OUT STD_LOGIC;
headers_ready : IN STD_LOGIC;
headers_valid : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF HeadFieldExtractor IS
BEGIN
din_ready <= 'X';
dout_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
dout_last <= 'X';
dout_valid <= 'X';
headers_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
headers_last <= 'X';
headers_valid <= 'X';
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY PatternMatch IS
PORT(
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_last : IN STD_LOGIC;
din_ready : OUT STD_LOGIC;
din_valid : IN STD_LOGIC;
match_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
match_last : OUT STD_LOGIC;
match_ready : IN STD_LOGIC;
match_valid : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF PatternMatch IS
BEGIN
din_ready <= 'X';
match_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
match_last <= 'X';
match_valid <= 'X';
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Filter IS
PORT(
cfg_ar_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_ar_prot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_ar_ready : OUT STD_LOGIC;
cfg_ar_valid : IN STD_LOGIC;
cfg_aw_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_aw_prot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_aw_ready : OUT STD_LOGIC;
cfg_aw_valid : IN STD_LOGIC;
cfg_b_ready : IN STD_LOGIC;
cfg_b_resp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_b_valid : OUT STD_LOGIC;
cfg_r_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_r_ready : IN STD_LOGIC;
cfg_r_resp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_r_valid : OUT STD_LOGIC;
cfg_w_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_w_ready : OUT STD_LOGIC;
cfg_w_strb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_w_valid : IN STD_LOGIC;
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_last : IN STD_LOGIC;
din_ready : OUT STD_LOGIC;
din_valid : IN STD_LOGIC;
dout_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dout_last : OUT STD_LOGIC;
dout_ready : IN STD_LOGIC;
dout_valid : OUT STD_LOGIC;
headers_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
headers_last : IN STD_LOGIC;
headers_ready : OUT STD_LOGIC;
headers_valid : IN STD_LOGIC;
patternMatch_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
patternMatch_last : IN STD_LOGIC;
patternMatch_ready : OUT STD_LOGIC;
patternMatch_valid : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF Filter IS
BEGIN
cfg_ar_ready <= 'X';
cfg_aw_ready <= 'X';
cfg_b_resp <= "XX";
cfg_b_valid <= 'X';
cfg_r_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
cfg_r_resp <= "XX";
cfg_r_valid <= 'X';
cfg_w_ready <= 'X';
din_ready <= 'X';
dout_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
dout_last <= 'X';
dout_valid <= 'X';
headers_ready <= 'X';
patternMatch_ready <= 'X';
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Exporter IS
PORT(
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_last : IN STD_LOGIC;
din_ready : OUT STD_LOGIC;
din_valid : IN STD_LOGIC;
dout_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dout_last : OUT STD_LOGIC;
dout_ready : IN STD_LOGIC;
dout_valid : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF Exporter IS
BEGIN
din_ready <= 'X';
dout_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
dout_last <= 'X';
dout_valid <= 'X';
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Stream duplicator for AxiStream interfaces
--
-- :see: :class:`hwtLib.handshaked.splitCopy.HsSplitCopy`
--
-- .. hwt-autodoc::
--
ENTITY AxiSSplitCopy IS
GENERIC(
DATA_WIDTH : INTEGER := 64;
DEST_WIDTH : INTEGER := 0;
ID_WIDTH : INTEGER := 0;
INTF_CLS : STRING := "<class 'hwtLib.amba.axis.AxiStream'>";
IS_BIGENDIAN : BOOLEAN := FALSE;
OUTPUTS : INTEGER := 2;
USER_WIDTH : INTEGER := 0;
USE_KEEP : BOOLEAN := FALSE;
USE_STRB : BOOLEAN := FALSE
);
PORT(
dataIn_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
dataIn_last : IN STD_LOGIC;
dataIn_ready : OUT STD_LOGIC;
dataIn_valid : IN STD_LOGIC;
dataOut_0_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dataOut_0_last : OUT STD_LOGIC;
dataOut_0_ready : IN STD_LOGIC;
dataOut_0_valid : OUT STD_LOGIC;
dataOut_1_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dataOut_1_last : OUT STD_LOGIC;
dataOut_1_ready : IN STD_LOGIC;
dataOut_1_valid : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AxiSSplitCopy IS
BEGIN
dataIn_ready <= dataOut_0_ready AND dataOut_1_ready;
dataOut_0_data <= dataIn_data;
dataOut_0_last <= dataIn_last;
dataOut_0_valid <= dataIn_valid AND dataOut_1_ready;
dataOut_1_data <= dataIn_data;
dataOut_1_last <= dataIn_last;
dataOut_1_valid <= dataIn_valid AND dataOut_0_ready;
ASSERT DATA_WIDTH = 64 REPORT "Generated only for this value" SEVERITY failure;
ASSERT DEST_WIDTH = 0 REPORT "Generated only for this value" SEVERITY failure;
ASSERT ID_WIDTH = 0 REPORT "Generated only for this value" SEVERITY failure;
ASSERT INTF_CLS = "<class 'hwtLib.amba.axis.AxiStream'>" REPORT "Generated only for this value" SEVERITY failure;
ASSERT IS_BIGENDIAN = FALSE REPORT "Generated only for this value" SEVERITY failure;
ASSERT OUTPUTS = 2 REPORT "Generated only for this value" SEVERITY failure;
ASSERT USER_WIDTH = 0 REPORT "Generated only for this value" SEVERITY failure;
ASSERT USE_KEEP = FALSE REPORT "Generated only for this value" SEVERITY failure;
ASSERT USE_STRB = FALSE REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- This unit has actually no functionality it is just example
-- of hierarchical design.
--
-- .. hwt-autodoc::
--
ENTITY NetFilter IS
GENERIC(
DATA_WIDTH : INTEGER := 64
);
PORT(
cfg_ar_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_ar_prot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_ar_ready : OUT STD_LOGIC;
cfg_ar_valid : IN STD_LOGIC;
cfg_aw_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_aw_prot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_aw_ready : OUT STD_LOGIC;
cfg_aw_valid : IN STD_LOGIC;
cfg_b_ready : IN STD_LOGIC;
cfg_b_resp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_b_valid : OUT STD_LOGIC;
cfg_r_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_r_ready : IN STD_LOGIC;
cfg_r_resp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_r_valid : OUT STD_LOGIC;
cfg_w_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_w_ready : OUT STD_LOGIC;
cfg_w_strb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_w_valid : IN STD_LOGIC;
clk : IN STD_LOGIC;
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_last : IN STD_LOGIC;
din_ready : OUT STD_LOGIC;
din_valid : IN STD_LOGIC;
export_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
export_last : OUT STD_LOGIC;
export_ready : IN STD_LOGIC;
export_valid : OUT STD_LOGIC;
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF NetFilter IS
--
-- Stream duplicator for AxiStream interfaces
--
-- :see: :class:`hwtLib.handshaked.splitCopy.HsSplitCopy`
--
-- .. hwt-autodoc::
--
COMPONENT AxiSSplitCopy IS
GENERIC(
DATA_WIDTH : INTEGER := 64;
DEST_WIDTH : INTEGER := 0;
ID_WIDTH : INTEGER := 0;
INTF_CLS : STRING := "<class 'hwtLib.amba.axis.AxiStream'>";
IS_BIGENDIAN : BOOLEAN := FALSE;
OUTPUTS : INTEGER := 2;
USER_WIDTH : INTEGER := 0;
USE_KEEP : BOOLEAN := FALSE;
USE_STRB : BOOLEAN := FALSE
);
PORT(
dataIn_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
dataIn_last : IN STD_LOGIC;
dataIn_ready : OUT STD_LOGIC;
dataIn_valid : IN STD_LOGIC;
dataOut_0_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dataOut_0_last : OUT STD_LOGIC;
dataOut_0_ready : IN STD_LOGIC;
dataOut_0_valid : OUT STD_LOGIC;
dataOut_1_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dataOut_1_last : OUT STD_LOGIC;
dataOut_1_ready : IN STD_LOGIC;
dataOut_1_valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT Exporter IS
PORT(
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_last : IN STD_LOGIC;
din_ready : OUT STD_LOGIC;
din_valid : IN STD_LOGIC;
dout_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dout_last : OUT STD_LOGIC;
dout_ready : IN STD_LOGIC;
dout_valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT Filter IS
PORT(
cfg_ar_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_ar_prot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_ar_ready : OUT STD_LOGIC;
cfg_ar_valid : IN STD_LOGIC;
cfg_aw_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_aw_prot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_aw_ready : OUT STD_LOGIC;
cfg_aw_valid : IN STD_LOGIC;
cfg_b_ready : IN STD_LOGIC;
cfg_b_resp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_b_valid : OUT STD_LOGIC;
cfg_r_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_r_ready : IN STD_LOGIC;
cfg_r_resp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_r_valid : OUT STD_LOGIC;
cfg_w_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_w_ready : OUT STD_LOGIC;
cfg_w_strb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_w_valid : IN STD_LOGIC;
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_last : IN STD_LOGIC;
din_ready : OUT STD_LOGIC;
din_valid : IN STD_LOGIC;
dout_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dout_last : OUT STD_LOGIC;
dout_ready : IN STD_LOGIC;
dout_valid : OUT STD_LOGIC;
headers_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
headers_last : IN STD_LOGIC;
headers_ready : OUT STD_LOGIC;
headers_valid : IN STD_LOGIC;
patternMatch_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
patternMatch_last : IN STD_LOGIC;
patternMatch_ready : OUT STD_LOGIC;
patternMatch_valid : IN STD_LOGIC
);
END COMPONENT;
COMPONENT HeadFieldExtractor IS
PORT(
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_last : IN STD_LOGIC;
din_ready : OUT STD_LOGIC;
din_valid : IN STD_LOGIC;
dout_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dout_last : OUT STD_LOGIC;
dout_ready : IN STD_LOGIC;
dout_valid : OUT STD_LOGIC;
headers_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
headers_last : OUT STD_LOGIC;
headers_ready : IN STD_LOGIC;
headers_valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT PatternMatch IS
PORT(
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_last : IN STD_LOGIC;
din_ready : OUT STD_LOGIC;
din_valid : IN STD_LOGIC;
match_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
match_last : OUT STD_LOGIC;
match_ready : IN STD_LOGIC;
match_valid : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL sig_exporter_din_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_exporter_din_last : STD_LOGIC;
SIGNAL sig_exporter_din_ready : STD_LOGIC;
SIGNAL sig_exporter_din_valid : STD_LOGIC;
SIGNAL sig_exporter_dout_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_exporter_dout_last : STD_LOGIC;
SIGNAL sig_exporter_dout_ready : STD_LOGIC;
SIGNAL sig_exporter_dout_valid : STD_LOGIC;
SIGNAL sig_filter_cfg_ar_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL sig_filter_cfg_ar_prot : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL sig_filter_cfg_ar_ready : STD_LOGIC;
SIGNAL sig_filter_cfg_ar_valid : STD_LOGIC;
SIGNAL sig_filter_cfg_aw_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL sig_filter_cfg_aw_prot : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL sig_filter_cfg_aw_ready : STD_LOGIC;
SIGNAL sig_filter_cfg_aw_valid : STD_LOGIC;
SIGNAL sig_filter_cfg_b_ready : STD_LOGIC;
SIGNAL sig_filter_cfg_b_resp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL sig_filter_cfg_b_valid : STD_LOGIC;
SIGNAL sig_filter_cfg_r_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_filter_cfg_r_ready : STD_LOGIC;
SIGNAL sig_filter_cfg_r_resp : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL sig_filter_cfg_r_valid : STD_LOGIC;
SIGNAL sig_filter_cfg_w_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_filter_cfg_w_ready : STD_LOGIC;
SIGNAL sig_filter_cfg_w_strb : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sig_filter_cfg_w_valid : STD_LOGIC;
SIGNAL sig_filter_din_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_filter_din_last : STD_LOGIC;
SIGNAL sig_filter_din_ready : STD_LOGIC;
SIGNAL sig_filter_din_valid : STD_LOGIC;
SIGNAL sig_filter_dout_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_filter_dout_last : STD_LOGIC;
SIGNAL sig_filter_dout_ready : STD_LOGIC;
SIGNAL sig_filter_dout_valid : STD_LOGIC;
SIGNAL sig_filter_headers_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_filter_headers_last : STD_LOGIC;
SIGNAL sig_filter_headers_ready : STD_LOGIC;
SIGNAL sig_filter_headers_valid : STD_LOGIC;
SIGNAL sig_filter_patternMatch_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_filter_patternMatch_last : STD_LOGIC;
SIGNAL sig_filter_patternMatch_ready : STD_LOGIC;
SIGNAL sig_filter_patternMatch_valid : STD_LOGIC;
SIGNAL sig_gen_dout_splitCopy_0_dataIn_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_gen_dout_splitCopy_0_dataIn_last : STD_LOGIC;
SIGNAL sig_gen_dout_splitCopy_0_dataIn_ready : STD_LOGIC;
SIGNAL sig_gen_dout_splitCopy_0_dataIn_valid : STD_LOGIC;
SIGNAL sig_gen_dout_splitCopy_0_dataOut_0_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_gen_dout_splitCopy_0_dataOut_0_last : STD_LOGIC;
SIGNAL sig_gen_dout_splitCopy_0_dataOut_0_ready : STD_LOGIC;
SIGNAL sig_gen_dout_splitCopy_0_dataOut_0_valid : STD_LOGIC;
SIGNAL sig_gen_dout_splitCopy_0_dataOut_1_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_gen_dout_splitCopy_0_dataOut_1_last : STD_LOGIC;
SIGNAL sig_gen_dout_splitCopy_0_dataOut_1_ready : STD_LOGIC;
SIGNAL sig_gen_dout_splitCopy_0_dataOut_1_valid : STD_LOGIC;
SIGNAL sig_hfe_din_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_hfe_din_last : STD_LOGIC;
SIGNAL sig_hfe_din_ready : STD_LOGIC;
SIGNAL sig_hfe_din_valid : STD_LOGIC;
SIGNAL sig_hfe_dout_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_hfe_dout_last : STD_LOGIC;
SIGNAL sig_hfe_dout_ready : STD_LOGIC;
SIGNAL sig_hfe_dout_valid : STD_LOGIC;
SIGNAL sig_hfe_headers_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_hfe_headers_last : STD_LOGIC;
SIGNAL sig_hfe_headers_ready : STD_LOGIC;
SIGNAL sig_hfe_headers_valid : STD_LOGIC;
SIGNAL sig_patternMatch_din_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_patternMatch_din_last : STD_LOGIC;
SIGNAL sig_patternMatch_din_ready : STD_LOGIC;
SIGNAL sig_patternMatch_din_valid : STD_LOGIC;
SIGNAL sig_patternMatch_match_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_patternMatch_match_last : STD_LOGIC;
SIGNAL sig_patternMatch_match_ready : STD_LOGIC;
SIGNAL sig_patternMatch_match_valid : STD_LOGIC;
BEGIN
exporter_inst: Exporter PORT MAP(
din_data => sig_exporter_din_data,
din_last => sig_exporter_din_last,
din_ready => sig_exporter_din_ready,
din_valid => sig_exporter_din_valid,
dout_data => sig_exporter_dout_data,
dout_last => sig_exporter_dout_last,
dout_ready => sig_exporter_dout_ready,
dout_valid => sig_exporter_dout_valid
);
filter_inst: Filter PORT MAP(
cfg_ar_addr => sig_filter_cfg_ar_addr,
cfg_ar_prot => sig_filter_cfg_ar_prot,
cfg_ar_ready => sig_filter_cfg_ar_ready,
cfg_ar_valid => sig_filter_cfg_ar_valid,
cfg_aw_addr => sig_filter_cfg_aw_addr,
cfg_aw_prot => sig_filter_cfg_aw_prot,
cfg_aw_ready => sig_filter_cfg_aw_ready,
cfg_aw_valid => sig_filter_cfg_aw_valid,
cfg_b_ready => sig_filter_cfg_b_ready,
cfg_b_resp => sig_filter_cfg_b_resp,
cfg_b_valid => sig_filter_cfg_b_valid,
cfg_r_data => sig_filter_cfg_r_data,
cfg_r_ready => sig_filter_cfg_r_ready,
cfg_r_resp => sig_filter_cfg_r_resp,
cfg_r_valid => sig_filter_cfg_r_valid,
cfg_w_data => sig_filter_cfg_w_data,
cfg_w_ready => sig_filter_cfg_w_ready,
cfg_w_strb => sig_filter_cfg_w_strb,
cfg_w_valid => sig_filter_cfg_w_valid,
din_data => sig_filter_din_data,
din_last => sig_filter_din_last,
din_ready => sig_filter_din_ready,
din_valid => sig_filter_din_valid,
dout_data => sig_filter_dout_data,
dout_last => sig_filter_dout_last,
dout_ready => sig_filter_dout_ready,
dout_valid => sig_filter_dout_valid,
headers_data => sig_filter_headers_data,
headers_last => sig_filter_headers_last,
headers_ready => sig_filter_headers_ready,
headers_valid => sig_filter_headers_valid,
patternMatch_data => sig_filter_patternMatch_data,
patternMatch_last => sig_filter_patternMatch_last,
patternMatch_ready => sig_filter_patternMatch_ready,
patternMatch_valid => sig_filter_patternMatch_valid
);
gen_dout_splitCopy_0_inst: AxiSSplitCopy GENERIC MAP(
DATA_WIDTH => 64,
DEST_WIDTH => 0,
ID_WIDTH => 0,
INTF_CLS => "<class 'hwtLib.amba.axis.AxiStream'>",
IS_BIGENDIAN => FALSE,
OUTPUTS => 2,
USER_WIDTH => 0,
USE_KEEP => FALSE,
USE_STRB => FALSE
) PORT MAP(
dataIn_data => sig_gen_dout_splitCopy_0_dataIn_data,
dataIn_last => sig_gen_dout_splitCopy_0_dataIn_last,
dataIn_ready => sig_gen_dout_splitCopy_0_dataIn_ready,
dataIn_valid => sig_gen_dout_splitCopy_0_dataIn_valid,
dataOut_0_data => sig_gen_dout_splitCopy_0_dataOut_0_data,
dataOut_0_last => sig_gen_dout_splitCopy_0_dataOut_0_last,
dataOut_0_ready => sig_gen_dout_splitCopy_0_dataOut_0_ready,
dataOut_0_valid => sig_gen_dout_splitCopy_0_dataOut_0_valid,
dataOut_1_data => sig_gen_dout_splitCopy_0_dataOut_1_data,
dataOut_1_last => sig_gen_dout_splitCopy_0_dataOut_1_last,
dataOut_1_ready => sig_gen_dout_splitCopy_0_dataOut_1_ready,
dataOut_1_valid => sig_gen_dout_splitCopy_0_dataOut_1_valid
);
hfe_inst: HeadFieldExtractor PORT MAP(
din_data => sig_hfe_din_data,
din_last => sig_hfe_din_last,
din_ready => sig_hfe_din_ready,
din_valid => sig_hfe_din_valid,
dout_data => sig_hfe_dout_data,
dout_last => sig_hfe_dout_last,
dout_ready => sig_hfe_dout_ready,
dout_valid => sig_hfe_dout_valid,
headers_data => sig_hfe_headers_data,
headers_last => sig_hfe_headers_last,
headers_ready => sig_hfe_headers_ready,
headers_valid => sig_hfe_headers_valid
);
patternMatch_inst: PatternMatch PORT MAP(
din_data => sig_patternMatch_din_data,
din_last => sig_patternMatch_din_last,
din_ready => sig_patternMatch_din_ready,
din_valid => sig_patternMatch_din_valid,
match_data => sig_patternMatch_match_data,
match_last => sig_patternMatch_match_last,
match_ready => sig_patternMatch_match_ready,
match_valid => sig_patternMatch_match_valid
);
cfg_ar_ready <= sig_filter_cfg_ar_ready;
cfg_aw_ready <= sig_filter_cfg_aw_ready;
cfg_b_resp <= sig_filter_cfg_b_resp;
cfg_b_valid <= sig_filter_cfg_b_valid;
cfg_r_data <= sig_filter_cfg_r_data;
cfg_r_resp <= sig_filter_cfg_r_resp;
cfg_r_valid <= sig_filter_cfg_r_valid;
cfg_w_ready <= sig_filter_cfg_w_ready;
din_ready <= sig_hfe_din_ready;
export_data <= sig_exporter_dout_data;
export_last <= sig_exporter_dout_last;
export_valid <= sig_exporter_dout_valid;
sig_exporter_din_data <= sig_filter_dout_data;
sig_exporter_din_last <= sig_filter_dout_last;
sig_exporter_din_valid <= sig_filter_dout_valid;
sig_exporter_dout_ready <= export_ready;
sig_filter_cfg_ar_addr <= cfg_ar_addr;
sig_filter_cfg_ar_prot <= cfg_ar_prot;
sig_filter_cfg_ar_valid <= cfg_ar_valid;
sig_filter_cfg_aw_addr <= cfg_aw_addr;
sig_filter_cfg_aw_prot <= cfg_aw_prot;
sig_filter_cfg_aw_valid <= cfg_aw_valid;
sig_filter_cfg_b_ready <= cfg_b_ready;
sig_filter_cfg_r_ready <= cfg_r_ready;
sig_filter_cfg_w_data <= cfg_w_data;
sig_filter_cfg_w_strb <= cfg_w_strb;
sig_filter_cfg_w_valid <= cfg_w_valid;
sig_filter_din_data <= sig_gen_dout_splitCopy_0_dataOut_1_data;
sig_filter_din_last <= sig_gen_dout_splitCopy_0_dataOut_1_last;
sig_filter_din_valid <= sig_gen_dout_splitCopy_0_dataOut_1_valid;
sig_filter_dout_ready <= sig_exporter_din_ready;
sig_filter_headers_data <= sig_hfe_headers_data;
sig_filter_headers_last <= sig_hfe_headers_last;
sig_filter_headers_valid <= sig_hfe_headers_valid;
sig_filter_patternMatch_data <= sig_patternMatch_match_data;
sig_filter_patternMatch_last <= sig_patternMatch_match_last;
sig_filter_patternMatch_valid <= sig_patternMatch_match_valid;
sig_gen_dout_splitCopy_0_dataIn_data <= sig_hfe_dout_data;
sig_gen_dout_splitCopy_0_dataIn_last <= sig_hfe_dout_last;
sig_gen_dout_splitCopy_0_dataIn_valid <= sig_hfe_dout_valid;
sig_gen_dout_splitCopy_0_dataOut_0_ready <= sig_patternMatch_din_ready;
sig_gen_dout_splitCopy_0_dataOut_1_ready <= sig_filter_din_ready;
sig_hfe_din_data <= din_data;
sig_hfe_din_last <= din_last;
sig_hfe_din_valid <= din_valid;
sig_hfe_dout_ready <= sig_gen_dout_splitCopy_0_dataIn_ready;
sig_hfe_headers_ready <= sig_filter_headers_ready;
sig_patternMatch_din_data <= sig_gen_dout_splitCopy_0_dataOut_0_data;
sig_patternMatch_din_last <= sig_gen_dout_splitCopy_0_dataOut_0_last;
sig_patternMatch_din_valid <= sig_gen_dout_splitCopy_0_dataOut_0_valid;
sig_patternMatch_match_ready <= sig_filter_patternMatch_ready;
ASSERT DATA_WIDTH = 64 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
|
mit
|
d9c8a0cb91b52d894924ff8e69dab917
| 0.623455 | 3.386751 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/hierarchy/RippleAdder0.vhd
| 1 | 3,037 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY FullAdder IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
ci : IN STD_LOGIC;
co : OUT STD_LOGIC;
s : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF FullAdder IS
BEGIN
co <= (a AND b) OR (a AND ci) OR (b AND ci);
s <= a XOR b XOR ci;
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY RippleAdder0 IS
GENERIC(
p_wordlength : INTEGER := 4
);
PORT(
a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ci : IN STD_LOGIC;
co : OUT STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF RippleAdder0 IS
--
-- .. hwt-autodoc::
--
COMPONENT FullAdder IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
ci : IN STD_LOGIC;
co : OUT STD_LOGIC;
s : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL c : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sig_fa0_a : STD_LOGIC;
SIGNAL sig_fa0_b : STD_LOGIC;
SIGNAL sig_fa0_ci : STD_LOGIC;
SIGNAL sig_fa0_co : STD_LOGIC;
SIGNAL sig_fa0_s : STD_LOGIC;
SIGNAL sig_fa1_a : STD_LOGIC;
SIGNAL sig_fa1_b : STD_LOGIC;
SIGNAL sig_fa1_ci : STD_LOGIC;
SIGNAL sig_fa1_co : STD_LOGIC;
SIGNAL sig_fa1_s : STD_LOGIC;
SIGNAL sig_fa2_a : STD_LOGIC;
SIGNAL sig_fa2_b : STD_LOGIC;
SIGNAL sig_fa2_ci : STD_LOGIC;
SIGNAL sig_fa2_co : STD_LOGIC;
SIGNAL sig_fa2_s : STD_LOGIC;
SIGNAL sig_fa3_a : STD_LOGIC;
SIGNAL sig_fa3_b : STD_LOGIC;
SIGNAL sig_fa3_ci : STD_LOGIC;
SIGNAL sig_fa3_co : STD_LOGIC;
SIGNAL sig_fa3_s : STD_LOGIC;
BEGIN
fa0_inst: FullAdder PORT MAP(
a => sig_fa0_a,
b => sig_fa0_b,
ci => sig_fa0_ci,
co => sig_fa0_co,
s => sig_fa0_s
);
fa1_inst: FullAdder PORT MAP(
a => sig_fa1_a,
b => sig_fa1_b,
ci => sig_fa1_ci,
co => sig_fa1_co,
s => sig_fa1_s
);
fa2_inst: FullAdder PORT MAP(
a => sig_fa2_a,
b => sig_fa2_b,
ci => sig_fa2_ci,
co => sig_fa2_co,
s => sig_fa2_s
);
fa3_inst: FullAdder PORT MAP(
a => sig_fa3_a,
b => sig_fa3_b,
ci => sig_fa3_ci,
co => sig_fa3_co,
s => sig_fa3_s
);
c <= sig_fa0_co & sig_fa0_co & sig_fa0_co & sig_fa0_co & ci;
co <= c(4);
s <= sig_fa3_s & sig_fa2_s & sig_fa1_s & sig_fa0_s;
sig_fa0_a <= a(0);
sig_fa0_b <= a(0);
sig_fa0_ci <= c(0);
sig_fa1_a <= a(1);
sig_fa1_b <= a(1);
sig_fa1_ci <= c(1);
sig_fa2_a <= a(2);
sig_fa2_b <= a(2);
sig_fa2_ci <= c(2);
sig_fa3_a <= a(3);
sig_fa3_b <= a(3);
sig_fa3_ci <= c(3);
ASSERT p_wordlength = 4 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
|
mit
|
6d78b3f314e26dabca5440bcd509f56e
| 0.520909 | 2.79136 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/finalproject/altera_merlin_master_translator/_primary.vhd
| 1 | 4,417 |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_master_translator is
generic(
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
USE_BURSTCOUNT : integer := 1;
USE_BEGINBURSTTRANSFER: integer := 0;
USE_BEGINTRANSFER: integer := 0;
USE_CHIPSELECT : integer := 0;
USE_READ : integer := 1;
USE_READDATAVALID: integer := 1;
USE_WRITE : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_WRITERESPONSE: integer := 0;
USE_READRESPONSE: integer := 0;
AV_REGISTERINCOMINGSIGNALS: integer := 0;
AV_SYMBOLS_PER_WORD: integer := 4;
AV_ADDRESS_SYMBOLS: integer := 0;
AV_CONSTANT_BURST_BEHAVIOR: integer := 1;
AV_BURSTCOUNT_SYMBOLS: integer := 0;
AV_LINEWRAPBURSTS: integer := 0;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W: integer := 10;
UAV_CONSTANT_BURST_BEHAVIOR: integer := 0
);
port(
clk : in vl_logic;
reset : in vl_logic;
uav_write : out vl_logic;
uav_read : out vl_logic;
uav_address : out vl_logic_vector;
uav_burstcount : out vl_logic_vector;
uav_byteenable : out vl_logic_vector;
uav_writedata : out vl_logic_vector;
uav_lock : out vl_logic;
uav_debugaccess : out vl_logic;
uav_clken : out vl_logic;
uav_readdata : in vl_logic_vector;
uav_readdatavalid: in vl_logic;
uav_waitrequest : in vl_logic;
uav_response : in vl_logic_vector(1 downto 0);
uav_writeresponsevalid: in vl_logic;
av_write : in vl_logic;
av_read : in vl_logic;
av_address : in vl_logic_vector;
av_byteenable : in vl_logic_vector;
av_burstcount : in vl_logic_vector;
av_writedata : in vl_logic_vector;
av_begintransfer: in vl_logic;
av_beginbursttransfer: in vl_logic;
av_lock : in vl_logic;
av_chipselect : in vl_logic;
av_debugaccess : in vl_logic;
av_clken : in vl_logic;
av_readdata : out vl_logic_vector;
av_readdatavalid: out vl_logic;
av_waitrequest : out vl_logic;
av_response : out vl_logic_vector(1 downto 0);
av_writeresponsevalid: out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of AV_DATA_W : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of AV_BYTEENABLE_W : constant is 1;
attribute mti_svvh_generic_type of USE_BURSTCOUNT : constant is 1;
attribute mti_svvh_generic_type of USE_BEGINBURSTTRANSFER : constant is 1;
attribute mti_svvh_generic_type of USE_BEGINTRANSFER : constant is 1;
attribute mti_svvh_generic_type of USE_CHIPSELECT : constant is 1;
attribute mti_svvh_generic_type of USE_READ : constant is 1;
attribute mti_svvh_generic_type of USE_READDATAVALID : constant is 1;
attribute mti_svvh_generic_type of USE_WRITE : constant is 1;
attribute mti_svvh_generic_type of USE_WAITREQUEST : constant is 1;
attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1;
attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1;
attribute mti_svvh_generic_type of AV_REGISTERINCOMINGSIGNALS : constant is 1;
attribute mti_svvh_generic_type of AV_SYMBOLS_PER_WORD : constant is 1;
attribute mti_svvh_generic_type of AV_ADDRESS_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of AV_CONSTANT_BURST_BEHAVIOR : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of AV_LINEWRAPBURSTS : constant is 1;
attribute mti_svvh_generic_type of UAV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of UAV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of UAV_CONSTANT_BURST_BEHAVIOR : constant is 1;
end altera_merlin_master_translator;
|
apache-2.0
|
85f6a3eff5164b6d82aa8d4974035f1c
| 0.614897 | 3.775214 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_addsub/fp_addsub_sim/fp_addsub.vhd
| 1 | 147,264 |
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_addsub
-- VHDL created on Thu Feb 15 14:11:38 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_addsub is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(31 downto 0); -- float32_m23
s : out std_logic_vector(31 downto 0); -- float32_m23
clk : in std_logic;
areset : in std_logic
);
end fp_addsub;
architecture normal of fp_addsub is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal expFracX_uid6_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (30 downto 0);
signal expFracY_uid7_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (30 downto 0);
signal xGTEy_uid8_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (32 downto 0);
signal xGTEy_uid8_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (32 downto 0);
signal xGTEy_uid8_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (32 downto 0);
signal xGTEy_uid8_fpFusedAddSubTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal siga_uid9_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal siga_uid9_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal sigb_uid10_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal sigb_uid10_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal cstAllOWE_uid11_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid12_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid13_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal exp_siga_uid14_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (30 downto 0);
signal exp_siga_uid14_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_siga_uid15_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal frac_siga_uid15_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_siga_uid9_uid16_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid17_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid18_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid19_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_siga_uid20_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_siga_uid21_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid22_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid23_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_siga_uid24_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal exp_sigb_uid28_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (30 downto 0);
signal exp_sigb_uid28_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_sigb_uid29_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal frac_sigb_uid29_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_sigb_uid10_uid30_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid31_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid32_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid33_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_sigb_uid34_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_sigb_uid35_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid36_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid37_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_sigb_uid38_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sigA_uid43_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal sigB_uid44_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal effSub_uid45_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expAmExpB_uid48_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expAmExpB_uid48_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expAmExpB_uid48_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expAmExpB_uid48_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal cWFP1_uid49_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal shiftedOut_uid51_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (10 downto 0);
signal shiftedOut_uid51_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (10 downto 0);
signal shiftedOut_uid51_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (10 downto 0);
signal shiftedOut_uid51_fpFusedAddSubTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal shiftOutConst_uid52_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal expAmExpBShiftRange_uid53_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (4 downto 0);
signal expAmExpBShiftRange_uid53_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal shiftValue_uid54_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal shiftValue_uid54_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal oFracB_uid56_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal oFracA_uid57_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal oFracBR_uid58_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal fracAOp_uid61_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal fracBOp_uid62_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (26 downto 0);
signal fracResSub_uid63_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (27 downto 0);
signal fracResSub_uid63_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (27 downto 0);
signal fracResSub_uid63_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (27 downto 0);
signal fracResSub_uid63_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal fracResAdd_uid64_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (27 downto 0);
signal fracResAdd_uid64_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (27 downto 0);
signal fracResAdd_uid64_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (27 downto 0);
signal fracResAdd_uid64_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal fracResSubNoSignExt_uid65_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (25 downto 0);
signal fracResSubNoSignExt_uid65_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (25 downto 0);
signal fracResAddNoSignExt_uid66_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (25 downto 0);
signal fracResAddNoSignExt_uid66_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (25 downto 0);
signal cAmA_uid71_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal aMinusA_uid72_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expInc_uid73_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expInc_uid73_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expInc_uid73_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expInc_uid73_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal expPostNormSub_uid74_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormSub_uid74_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormSub_uid74_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormSub_uid74_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormAdd_uid75_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormAdd_uid75_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormAdd_uid75_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormAdd_uid75_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal fracPostNormSubRndRange_uid76_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal fracPostNormSubRndRange_uid76_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal expFracRSub_uid77_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal fracPostNormAddRndRange_uid78_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal fracPostNormAddRndRange_uid78_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal expFracRAdd_uid79_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal wEP2AllOwE_uid80_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal rndExp_uid81_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal rOvf_uid82_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signedExp_uid83_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal rUdf_uid84_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (11 downto 0);
signal rUdf_uid84_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal rUdf_uid84_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (11 downto 0);
signal rUdf_uid84_fpFusedAddSubTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPreExcSub_uid85_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExcSub_uid85_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcSub_uid86_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal expRPreExcSub_uid86_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal fracRPreExcAdd_uid88_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExcAdd_uid88_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcAdd_uid89_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal expRPreExcAdd_uid89_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal regInputs_uid91_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZeroVInC_uid92_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (5 downto 0);
signal excRZeroAdd_uid93_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZeroSub_uid94_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal regInAndOvf_uid95_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneIsInf_uid96_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneIsInfOrZero_uid97_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal addIsAlsoInf_uid98_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInfVInC_uid99_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (5 downto 0);
signal excRInfAdd_uid100_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInfAddFull_uid101_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInfSub_uid102_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInfSubFull_uid103_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal infMinf_uid104_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaNA_uid105_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invEffSub_uid106_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal infPinfForSub_uid107_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaNS_uid108_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal concExcSub_uid109_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal concExcAdd_uid110_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal excREncSub_uid111_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal excREncAdd_uid112_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPreExcAddition_uid113_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPreExcAddition_uid113_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcAddition_uid114_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal expRPreExcAddition_uid114_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal fracRPreExcSubtraction_uid115_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcSubtraction_uid116_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal expRPreExcSubtraction_uid116_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal oneFracRPostExc2_uid117_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracRPostExcAdd_uid120_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExcAdd_uid120_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExcAdd_uid124_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExcAdd_uid124_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal invXGTEy_uid125_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invSigA_uid126_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signInputsZeroSwap_uid127_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invSignInputsZeroSwap_uid128_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invSigB_uid129_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signInputsZeroNoSwap_uid130_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invSignInputsZeroNoSwap_uid131_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal aMa_uid132_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invAMA_uid133_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExcRNaNA_uid134_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExc_uid135_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal RSum_uid136_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal fracRPostExcSub_uid140_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExcSub_uid140_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExcSub_uid144_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExcSub_uid144_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal positiveExc_uid145_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invPositiveExc_uid146_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signInputsZeroForSub_uid147_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invSignInputsZeroForSub_uid148_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sigY_uid149_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal invSigY_uid150_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal yGTxYPos_uid152_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sigX_uid153_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal xGTyXNeg_uid154_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExcSub0_uid155_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExcRNaNS_uid156_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExcSub_uid157_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal RDiff_uid158_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (15 downto 0);
signal vCount_uid163_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal mO_uid164_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (5 downto 0);
signal vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (9 downto 0);
signal vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal cStage_uid166_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal vCount_uid171_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal vCount_uid177_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal vCount_uid183_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid188_lzCountValSub_uid67_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal vCount_uid189_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (15 downto 0);
signal vCount_uid194_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (9 downto 0);
signal vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal cStage_uid197_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal vCount_uid202_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal vCount_uid208_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal vCount_uid214_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid219_lzCountValAdd_uid69_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal vCount_uid220_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal rightShiftStage0Idx1Rng4_uid225_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (20 downto 0);
signal rightShiftStage0Idx1_uid227_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx2Rng8_uid228_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (16 downto 0);
signal rightShiftStage0Idx2_uid230_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx3Rng12_uid231_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (12 downto 0);
signal rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (11 downto 0);
signal rightShiftStage0Idx3_uid233_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx4Rng16_uid234_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal rightShiftStage0Idx4_uid236_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx5Rng20_uid237_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (19 downto 0);
signal rightShiftStage0Idx5_uid239_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx6Rng24_uid240_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal rightShiftStage0Idx6_uid242_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx7_uid243_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage1Idx1Rng1_uid246_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal rightShiftStage1Idx1_uid248_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage1Idx2Rng2_uid249_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal rightShiftStage1Idx2_uid251_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage1Idx3Rng3_uid252_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (21 downto 0);
signal rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal rightShiftStage1Idx3_uid254_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (21 downto 0);
signal leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (21 downto 0);
signal leftShiftStage0Idx1_uid262_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (17 downto 0);
signal leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal leftShiftStage0Idx2_uid265_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (13 downto 0);
signal leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal leftShiftStage0Idx3_uid268_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx4_uid271_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal leftShiftStage0Idx5_uid274_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0Idx6_uid277_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage1Idx1_uid283_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal leftShiftStage1Idx2_uid286_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal leftShiftStage1Idx3_uid289_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (21 downto 0);
signal leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (21 downto 0);
signal leftShiftStage0Idx1_uid297_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (17 downto 0);
signal leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal leftShiftStage0Idx2_uid300_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (13 downto 0);
signal leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal leftShiftStage0Idx3_uid303_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx4_uid306_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal leftShiftStage0Idx5_uid309_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0Idx6_uid312_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage1Idx1_uid318_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal leftShiftStage1Idx2_uid321_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal leftShiftStage1Idx3_uid324_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_s : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_s : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_s : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_s : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_s : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q : STD_LOGIC_VECTOR (25 downto 0);
signal rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (2 downto 0);
signal rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (7 downto 0);
signal rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (7 downto 0);
signal rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (3 downto 0);
signal rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (3 downto 0);
signal rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (2 downto 0);
signal leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (7 downto 0);
signal rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (7 downto 0);
signal rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (3 downto 0);
signal rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (3 downto 0);
signal rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (2 downto 0);
signal leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_c : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_c : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_c : STD_LOGIC_VECTOR (0 downto 0);
signal redist0_xIn_a_1_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist1_xIn_b_1_q : STD_LOGIC_VECTOR (31 downto 0);
begin
-- redist1_xIn_b_1(DELAY,355)
redist1_xIn_b_1 : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => b, xout => redist1_xIn_b_1_q, clk => clk, aclr => areset );
-- redist0_xIn_a_1(DELAY,354)
redist0_xIn_a_1 : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => a, xout => redist0_xIn_a_1_q, clk => clk, aclr => areset );
-- GND(CONSTANT,0)
GND_q <= "0";
-- expFracY_uid7_fpFusedAddSubTest(BITSELECT,6)@0
expFracY_uid7_fpFusedAddSubTest_b <= b(30 downto 0);
-- expFracX_uid6_fpFusedAddSubTest(BITSELECT,5)@0
expFracX_uid6_fpFusedAddSubTest_b <= a(30 downto 0);
-- xGTEy_uid8_fpFusedAddSubTest(COMPARE,7)@0 + 1
xGTEy_uid8_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("00" & expFracX_uid6_fpFusedAddSubTest_b);
xGTEy_uid8_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("00" & expFracY_uid7_fpFusedAddSubTest_b);
xGTEy_uid8_fpFusedAddSubTest_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xGTEy_uid8_fpFusedAddSubTest_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
xGTEy_uid8_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xGTEy_uid8_fpFusedAddSubTest_a) - UNSIGNED(xGTEy_uid8_fpFusedAddSubTest_b));
END IF;
END PROCESS;
xGTEy_uid8_fpFusedAddSubTest_n(0) <= not (xGTEy_uid8_fpFusedAddSubTest_o(32));
-- sigb_uid10_fpFusedAddSubTest(MUX,9)@1
sigb_uid10_fpFusedAddSubTest_s <= xGTEy_uid8_fpFusedAddSubTest_n;
sigb_uid10_fpFusedAddSubTest_combproc: PROCESS (sigb_uid10_fpFusedAddSubTest_s, redist0_xIn_a_1_q, redist1_xIn_b_1_q)
BEGIN
CASE (sigb_uid10_fpFusedAddSubTest_s) IS
WHEN "0" => sigb_uid10_fpFusedAddSubTest_q <= redist0_xIn_a_1_q;
WHEN "1" => sigb_uid10_fpFusedAddSubTest_q <= redist1_xIn_b_1_q;
WHEN OTHERS => sigb_uid10_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- sigB_uid44_fpFusedAddSubTest(BITSELECT,43)@1
sigB_uid44_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(sigb_uid10_fpFusedAddSubTest_q(31 downto 31));
-- siga_uid9_fpFusedAddSubTest(MUX,8)@1
siga_uid9_fpFusedAddSubTest_s <= xGTEy_uid8_fpFusedAddSubTest_n;
siga_uid9_fpFusedAddSubTest_combproc: PROCESS (siga_uid9_fpFusedAddSubTest_s, redist1_xIn_b_1_q, redist0_xIn_a_1_q)
BEGIN
CASE (siga_uid9_fpFusedAddSubTest_s) IS
WHEN "0" => siga_uid9_fpFusedAddSubTest_q <= redist1_xIn_b_1_q;
WHEN "1" => siga_uid9_fpFusedAddSubTest_q <= redist0_xIn_a_1_q;
WHEN OTHERS => siga_uid9_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- sigA_uid43_fpFusedAddSubTest(BITSELECT,42)@1
sigA_uid43_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(siga_uid9_fpFusedAddSubTest_q(31 downto 31));
-- cAmA_uid71_fpFusedAddSubTest(CONSTANT,70)
cAmA_uid71_fpFusedAddSubTest_q <= "11010";
-- zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest(CONSTANT,160)
zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q <= "0000000000000000";
-- rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest(CONSTANT,252)
rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest_q <= "000";
-- rightShiftStage1Idx3Rng3_uid252_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,251)@1
rightShiftStage1Idx3Rng3_uid252_alignmentShifter_uid59_fpFusedAddSubTest_b <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q(24 downto 3);
-- rightShiftStage1Idx3_uid254_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,253)@1
rightShiftStage1Idx3_uid254_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest_q & rightShiftStage1Idx3Rng3_uid252_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest(CONSTANT,180)
zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q <= "00";
-- rightShiftStage1Idx2Rng2_uid249_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,248)@1
rightShiftStage1Idx2Rng2_uid249_alignmentShifter_uid59_fpFusedAddSubTest_b <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q(24 downto 2);
-- rightShiftStage1Idx2_uid251_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,250)@1
rightShiftStage1Idx2_uid251_alignmentShifter_uid59_fpFusedAddSubTest_q <= zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q & rightShiftStage1Idx2Rng2_uid249_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage1Idx1Rng1_uid246_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,245)@1
rightShiftStage1Idx1Rng1_uid246_alignmentShifter_uid59_fpFusedAddSubTest_b <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q(24 downto 1);
-- rightShiftStage1Idx1_uid248_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,247)@1
rightShiftStage1Idx1_uid248_alignmentShifter_uid59_fpFusedAddSubTest_q <= GND_q & rightShiftStage1Idx1Rng1_uid246_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0Idx7_uid243_alignmentShifter_uid59_fpFusedAddSubTest(CONSTANT,242)
rightShiftStage0Idx7_uid243_alignmentShifter_uid59_fpFusedAddSubTest_q <= "0000000000000000000000000";
-- rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest(CONSTANT,240)
rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest_q <= "000000000000000000000000";
-- cstAllZWE_uid13_fpFusedAddSubTest(CONSTANT,12)
cstAllZWE_uid13_fpFusedAddSubTest_q <= "00000000";
-- exp_sigb_uid28_fpFusedAddSubTest(BITSELECT,27)@1
exp_sigb_uid28_fpFusedAddSubTest_in <= sigb_uid10_fpFusedAddSubTest_q(30 downto 0);
exp_sigb_uid28_fpFusedAddSubTest_b <= exp_sigb_uid28_fpFusedAddSubTest_in(30 downto 23);
-- excZ_sigb_uid10_uid30_fpFusedAddSubTest(LOGICAL,29)@1
excZ_sigb_uid10_uid30_fpFusedAddSubTest_q <= "1" WHEN exp_sigb_uid28_fpFusedAddSubTest_b = cstAllZWE_uid13_fpFusedAddSubTest_q ELSE "0";
-- InvExpXIsZero_uid37_fpFusedAddSubTest(LOGICAL,36)@1
InvExpXIsZero_uid37_fpFusedAddSubTest_q <= not (excZ_sigb_uid10_uid30_fpFusedAddSubTest_q);
-- frac_sigb_uid29_fpFusedAddSubTest(BITSELECT,28)@1
frac_sigb_uid29_fpFusedAddSubTest_in <= sigb_uid10_fpFusedAddSubTest_q(22 downto 0);
frac_sigb_uid29_fpFusedAddSubTest_b <= frac_sigb_uid29_fpFusedAddSubTest_in(22 downto 0);
-- oFracB_uid56_fpFusedAddSubTest(BITJOIN,55)@1
oFracB_uid56_fpFusedAddSubTest_q <= InvExpXIsZero_uid37_fpFusedAddSubTest_q & frac_sigb_uid29_fpFusedAddSubTest_b;
-- oFracBR_uid58_fpFusedAddSubTest(BITJOIN,57)@1
oFracBR_uid58_fpFusedAddSubTest_q <= oFracB_uid56_fpFusedAddSubTest_q & GND_q;
-- rightShiftStage0Idx6Rng24_uid240_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,239)@1
rightShiftStage0Idx6Rng24_uid240_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 24);
-- rightShiftStage0Idx6_uid242_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,241)@1
rightShiftStage0Idx6_uid242_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest_q & rightShiftStage0Idx6Rng24_uid240_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest(CONSTANT,237)
rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest_q <= "00000000000000000000";
-- rightShiftStage0Idx5Rng20_uid237_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,236)@1
rightShiftStage0Idx5Rng20_uid237_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 20);
-- rightShiftStage0Idx5_uid239_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,238)@1
rightShiftStage0Idx5_uid239_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest_q & rightShiftStage0Idx5Rng20_uid237_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0Idx4Rng16_uid234_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,233)@1
rightShiftStage0Idx4Rng16_uid234_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 16);
-- rightShiftStage0Idx4_uid236_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,235)@1
rightShiftStage0Idx4_uid236_alignmentShifter_uid59_fpFusedAddSubTest_q <= zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q & rightShiftStage0Idx4Rng16_uid234_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1(MUX,330)@1
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_s <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_combproc: PROCESS (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_s, rightShiftStage0Idx4_uid236_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage0Idx5_uid239_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage0Idx6_uid242_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage0Idx7_uid243_alignmentShifter_uid59_fpFusedAddSubTest_q)
BEGIN
CASE (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_s) IS
WHEN "00" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q <= rightShiftStage0Idx4_uid236_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "01" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q <= rightShiftStage0Idx5_uid239_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "10" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q <= rightShiftStage0Idx6_uid242_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "11" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q <= rightShiftStage0Idx7_uid243_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN OTHERS => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q <= (others => '0');
END CASE;
END PROCESS;
-- rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest(CONSTANT,231)
rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest_q <= "000000000000";
-- rightShiftStage0Idx3Rng12_uid231_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,230)@1
rightShiftStage0Idx3Rng12_uid231_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 12);
-- rightShiftStage0Idx3_uid233_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,232)@1
rightShiftStage0Idx3_uid233_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest_q & rightShiftStage0Idx3Rng12_uid231_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0Idx2Rng8_uid228_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,227)@1
rightShiftStage0Idx2Rng8_uid228_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 8);
-- rightShiftStage0Idx2_uid230_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,229)@1
rightShiftStage0Idx2_uid230_alignmentShifter_uid59_fpFusedAddSubTest_q <= cstAllZWE_uid13_fpFusedAddSubTest_q & rightShiftStage0Idx2Rng8_uid228_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest(CONSTANT,174)
zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q <= "0000";
-- rightShiftStage0Idx1Rng4_uid225_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,224)@1
rightShiftStage0Idx1Rng4_uid225_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 4);
-- rightShiftStage0Idx1_uid227_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,226)@1
rightShiftStage0Idx1_uid227_alignmentShifter_uid59_fpFusedAddSubTest_q <= zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q & rightShiftStage0Idx1Rng4_uid225_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0(MUX,329)@1
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_s <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_combproc: PROCESS (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_s, oFracBR_uid58_fpFusedAddSubTest_q, rightShiftStage0Idx1_uid227_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage0Idx2_uid230_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage0Idx3_uid233_alignmentShifter_uid59_fpFusedAddSubTest_q)
BEGIN
CASE (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_s) IS
WHEN "00" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q <= oFracBR_uid58_fpFusedAddSubTest_q;
WHEN "01" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q <= rightShiftStage0Idx1_uid227_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "10" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q <= rightShiftStage0Idx2_uid230_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "11" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q <= rightShiftStage0Idx3_uid233_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN OTHERS => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q <= (others => '0');
END CASE;
END PROCESS;
-- rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select(BITSELECT,351)@1
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_b <= rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_b(1 downto 0);
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_c <= rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_b(2 downto 2);
-- rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal(MUX,331)@1
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_s <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_c;
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_combproc: PROCESS (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_s, rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q, rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q)
BEGIN
CASE (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_s) IS
WHEN "0" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q;
WHEN "1" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q;
WHEN OTHERS => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q <= (others => '0');
END CASE;
END PROCESS;
-- shiftOutConst_uid52_fpFusedAddSubTest(CONSTANT,51)
shiftOutConst_uid52_fpFusedAddSubTest_q <= "11001";
-- exp_siga_uid14_fpFusedAddSubTest(BITSELECT,13)@1
exp_siga_uid14_fpFusedAddSubTest_in <= siga_uid9_fpFusedAddSubTest_q(30 downto 0);
exp_siga_uid14_fpFusedAddSubTest_b <= exp_siga_uid14_fpFusedAddSubTest_in(30 downto 23);
-- expAmExpB_uid48_fpFusedAddSubTest(SUB,47)@1
expAmExpB_uid48_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("0" & exp_siga_uid14_fpFusedAddSubTest_b);
expAmExpB_uid48_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("0" & exp_sigb_uid28_fpFusedAddSubTest_b);
expAmExpB_uid48_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expAmExpB_uid48_fpFusedAddSubTest_a) - UNSIGNED(expAmExpB_uid48_fpFusedAddSubTest_b));
expAmExpB_uid48_fpFusedAddSubTest_q <= expAmExpB_uid48_fpFusedAddSubTest_o(8 downto 0);
-- expAmExpBShiftRange_uid53_fpFusedAddSubTest(BITSELECT,52)@1
expAmExpBShiftRange_uid53_fpFusedAddSubTest_in <= expAmExpB_uid48_fpFusedAddSubTest_q(4 downto 0);
expAmExpBShiftRange_uid53_fpFusedAddSubTest_b <= expAmExpBShiftRange_uid53_fpFusedAddSubTest_in(4 downto 0);
-- cWFP1_uid49_fpFusedAddSubTest(CONSTANT,48)
cWFP1_uid49_fpFusedAddSubTest_q <= "11000";
-- shiftedOut_uid51_fpFusedAddSubTest(COMPARE,50)@1
shiftedOut_uid51_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("000000" & cWFP1_uid49_fpFusedAddSubTest_q);
shiftedOut_uid51_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("00" & expAmExpB_uid48_fpFusedAddSubTest_q);
shiftedOut_uid51_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftedOut_uid51_fpFusedAddSubTest_a) - UNSIGNED(shiftedOut_uid51_fpFusedAddSubTest_b));
shiftedOut_uid51_fpFusedAddSubTest_c(0) <= shiftedOut_uid51_fpFusedAddSubTest_o(10);
-- shiftValue_uid54_fpFusedAddSubTest(MUX,53)@1
shiftValue_uid54_fpFusedAddSubTest_s <= shiftedOut_uid51_fpFusedAddSubTest_c;
shiftValue_uid54_fpFusedAddSubTest_combproc: PROCESS (shiftValue_uid54_fpFusedAddSubTest_s, expAmExpBShiftRange_uid53_fpFusedAddSubTest_b, shiftOutConst_uid52_fpFusedAddSubTest_q)
BEGIN
CASE (shiftValue_uid54_fpFusedAddSubTest_s) IS
WHEN "0" => shiftValue_uid54_fpFusedAddSubTest_q <= expAmExpBShiftRange_uid53_fpFusedAddSubTest_b;
WHEN "1" => shiftValue_uid54_fpFusedAddSubTest_q <= shiftOutConst_uid52_fpFusedAddSubTest_q;
WHEN OTHERS => shiftValue_uid54_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select(BITSELECT,342)@1
rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_b <= shiftValue_uid54_fpFusedAddSubTest_q(4 downto 2);
rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_c <= shiftValue_uid54_fpFusedAddSubTest_q(1 downto 0);
-- rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest(MUX,255)@1
rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_s <= rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_c;
rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_combproc: PROCESS (rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_s, rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q, rightShiftStage1Idx1_uid248_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage1Idx2_uid251_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage1Idx3_uid254_alignmentShifter_uid59_fpFusedAddSubTest_q)
BEGIN
CASE (rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_s) IS
WHEN "00" => rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q;
WHEN "01" => rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage1Idx1_uid248_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "10" => rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage1Idx2_uid251_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "11" => rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage1Idx3_uid254_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN OTHERS => rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracBOp_uid62_fpFusedAddSubTest(BITJOIN,61)@1
fracBOp_uid62_fpFusedAddSubTest_q <= GND_q & GND_q & rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- frac_siga_uid15_fpFusedAddSubTest(BITSELECT,14)@1
frac_siga_uid15_fpFusedAddSubTest_in <= siga_uid9_fpFusedAddSubTest_q(22 downto 0);
frac_siga_uid15_fpFusedAddSubTest_b <= frac_siga_uid15_fpFusedAddSubTest_in(22 downto 0);
-- oFracA_uid57_fpFusedAddSubTest(BITJOIN,56)@1
oFracA_uid57_fpFusedAddSubTest_q <= VCC_q & frac_siga_uid15_fpFusedAddSubTest_b;
-- fracAOp_uid61_fpFusedAddSubTest(BITJOIN,60)@1
fracAOp_uid61_fpFusedAddSubTest_q <= oFracA_uid57_fpFusedAddSubTest_q & GND_q;
-- fracResSub_uid63_fpFusedAddSubTest(SUB,62)@1
fracResSub_uid63_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("000" & fracAOp_uid61_fpFusedAddSubTest_q);
fracResSub_uid63_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("0" & fracBOp_uid62_fpFusedAddSubTest_q);
fracResSub_uid63_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(fracResSub_uid63_fpFusedAddSubTest_a) - UNSIGNED(fracResSub_uid63_fpFusedAddSubTest_b));
fracResSub_uid63_fpFusedAddSubTest_q <= fracResSub_uid63_fpFusedAddSubTest_o(27 downto 0);
-- fracResSubNoSignExt_uid65_fpFusedAddSubTest(BITSELECT,64)@1
fracResSubNoSignExt_uid65_fpFusedAddSubTest_in <= fracResSub_uid63_fpFusedAddSubTest_q(25 downto 0);
fracResSubNoSignExt_uid65_fpFusedAddSubTest_b <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_in(25 downto 0);
-- rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest(BITSELECT,161)@1
rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest_b <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(25 downto 10);
-- vCount_uid163_lzCountValSub_uid67_fpFusedAddSubTest(LOGICAL,162)@1
vCount_uid163_lzCountValSub_uid67_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest_b = zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest(BITSELECT,164)@1
vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(9 downto 0);
vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_b <= vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_in(9 downto 0);
-- mO_uid164_lzCountValSub_uid67_fpFusedAddSubTest(CONSTANT,163)
mO_uid164_lzCountValSub_uid67_fpFusedAddSubTest_q <= "111111";
-- cStage_uid166_lzCountValSub_uid67_fpFusedAddSubTest(BITJOIN,165)@1
cStage_uid166_lzCountValSub_uid67_fpFusedAddSubTest_q <= vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_b & mO_uid164_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest(MUX,167)@1
vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_s <= vCount_uid163_lzCountValSub_uid67_fpFusedAddSubTest_q;
vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_s, rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest_b, cStage_uid166_lzCountValSub_uid67_fpFusedAddSubTest_q)
BEGIN
CASE (vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest_b;
WHEN "1" => vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q <= cStage_uid166_lzCountValSub_uid67_fpFusedAddSubTest_q;
WHEN OTHERS => vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select(BITSELECT,343)@1
rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q(15 downto 8);
rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q(7 downto 0);
-- vCount_uid171_lzCountValSub_uid67_fpFusedAddSubTest(LOGICAL,170)@1
vCount_uid171_lzCountValSub_uid67_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b = cstAllZWE_uid13_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest(MUX,173)@1
vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_s <= vCount_uid171_lzCountValSub_uid67_fpFusedAddSubTest_q;
vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_s, rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select(BITSELECT,344)@1
rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q(7 downto 4);
rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q(3 downto 0);
-- vCount_uid177_lzCountValSub_uid67_fpFusedAddSubTest(LOGICAL,176)@1
vCount_uid177_lzCountValSub_uid67_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b = zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest(MUX,179)@1
vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_s <= vCount_uid177_lzCountValSub_uid67_fpFusedAddSubTest_q;
vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_s, rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select(BITSELECT,345)@1
rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q(3 downto 2);
rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q(1 downto 0);
-- vCount_uid183_lzCountValSub_uid67_fpFusedAddSubTest(LOGICAL,182)@1
vCount_uid183_lzCountValSub_uid67_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b = zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest(MUX,185)@1
vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_s <= vCount_uid183_lzCountValSub_uid67_fpFusedAddSubTest_q;
vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_s, rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid188_lzCountValSub_uid67_fpFusedAddSubTest(BITSELECT,187)@1
rVStage_uid188_lzCountValSub_uid67_fpFusedAddSubTest_b <= vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_q(1 downto 1);
-- vCount_uid189_lzCountValSub_uid67_fpFusedAddSubTest(LOGICAL,188)@1
vCount_uid189_lzCountValSub_uid67_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid188_lzCountValSub_uid67_fpFusedAddSubTest_b = GND_q ELSE "0";
-- r_uid190_lzCountValSub_uid67_fpFusedAddSubTest(BITJOIN,189)@1
r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q <= vCount_uid163_lzCountValSub_uid67_fpFusedAddSubTest_q & vCount_uid171_lzCountValSub_uid67_fpFusedAddSubTest_q & vCount_uid177_lzCountValSub_uid67_fpFusedAddSubTest_q & vCount_uid183_lzCountValSub_uid67_fpFusedAddSubTest_q & vCount_uid189_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- aMinusA_uid72_fpFusedAddSubTest(LOGICAL,71)@1
aMinusA_uid72_fpFusedAddSubTest_q <= "1" WHEN r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q = cAmA_uid71_fpFusedAddSubTest_q ELSE "0";
-- cstAllOWE_uid11_fpFusedAddSubTest(CONSTANT,10)
cstAllOWE_uid11_fpFusedAddSubTest_q <= "11111111";
-- expXIsMax_uid17_fpFusedAddSubTest(LOGICAL,16)@1
expXIsMax_uid17_fpFusedAddSubTest_q <= "1" WHEN exp_siga_uid14_fpFusedAddSubTest_b = cstAllOWE_uid11_fpFusedAddSubTest_q ELSE "0";
-- invExpXIsMax_uid22_fpFusedAddSubTest(LOGICAL,21)@1
invExpXIsMax_uid22_fpFusedAddSubTest_q <= not (expXIsMax_uid17_fpFusedAddSubTest_q);
-- excZ_siga_uid9_uid16_fpFusedAddSubTest(LOGICAL,15)@1
excZ_siga_uid9_uid16_fpFusedAddSubTest_q <= "1" WHEN exp_siga_uid14_fpFusedAddSubTest_b = cstAllZWE_uid13_fpFusedAddSubTest_q ELSE "0";
-- InvExpXIsZero_uid23_fpFusedAddSubTest(LOGICAL,22)@1
InvExpXIsZero_uid23_fpFusedAddSubTest_q <= not (excZ_siga_uid9_uid16_fpFusedAddSubTest_q);
-- excR_siga_uid24_fpFusedAddSubTest(LOGICAL,23)@1
excR_siga_uid24_fpFusedAddSubTest_q <= InvExpXIsZero_uid23_fpFusedAddSubTest_q and invExpXIsMax_uid22_fpFusedAddSubTest_q;
-- positiveExc_uid145_fpFusedAddSubTest(LOGICAL,144)@1
positiveExc_uid145_fpFusedAddSubTest_q <= excR_siga_uid24_fpFusedAddSubTest_q and aMinusA_uid72_fpFusedAddSubTest_q and sigA_uid43_fpFusedAddSubTest_b and sigB_uid44_fpFusedAddSubTest_b;
-- invPositiveExc_uid146_fpFusedAddSubTest(LOGICAL,145)@1
invPositiveExc_uid146_fpFusedAddSubTest_q <= not (positiveExc_uid145_fpFusedAddSubTest_q);
-- signInputsZeroForSub_uid147_fpFusedAddSubTest(LOGICAL,146)@1
signInputsZeroForSub_uid147_fpFusedAddSubTest_q <= excZ_siga_uid9_uid16_fpFusedAddSubTest_q and excZ_sigb_uid10_uid30_fpFusedAddSubTest_q and sigA_uid43_fpFusedAddSubTest_b and sigB_uid44_fpFusedAddSubTest_b;
-- invSignInputsZeroForSub_uid148_fpFusedAddSubTest(LOGICAL,147)@1
invSignInputsZeroForSub_uid148_fpFusedAddSubTest_q <= not (signInputsZeroForSub_uid147_fpFusedAddSubTest_q);
-- sigY_uid149_fpFusedAddSubTest(BITSELECT,148)@1
sigY_uid149_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(redist1_xIn_b_1_q(31 downto 31));
-- invSigY_uid150_fpFusedAddSubTest(LOGICAL,149)@1
invSigY_uid150_fpFusedAddSubTest_q <= not (sigY_uid149_fpFusedAddSubTest_b);
-- invXGTEy_uid125_fpFusedAddSubTest(LOGICAL,124)@1
invXGTEy_uid125_fpFusedAddSubTest_q <= not (xGTEy_uid8_fpFusedAddSubTest_n);
-- yGTxYPos_uid152_fpFusedAddSubTest(LOGICAL,151)@1
yGTxYPos_uid152_fpFusedAddSubTest_q <= invXGTEy_uid125_fpFusedAddSubTest_q and invSigY_uid150_fpFusedAddSubTest_q;
-- sigX_uid153_fpFusedAddSubTest(BITSELECT,152)@1
sigX_uid153_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(redist0_xIn_a_1_q(31 downto 31));
-- xGTyXNeg_uid154_fpFusedAddSubTest(LOGICAL,153)@1
xGTyXNeg_uid154_fpFusedAddSubTest_q <= xGTEy_uid8_fpFusedAddSubTest_n and sigX_uid153_fpFusedAddSubTest_b;
-- signRPostExcSub0_uid155_fpFusedAddSubTest(LOGICAL,154)@1
signRPostExcSub0_uid155_fpFusedAddSubTest_q <= xGTyXNeg_uid154_fpFusedAddSubTest_q or yGTxYPos_uid152_fpFusedAddSubTest_q;
-- cstZeroWF_uid12_fpFusedAddSubTest(CONSTANT,11)
cstZeroWF_uid12_fpFusedAddSubTest_q <= "00000000000000000000000";
-- fracXIsZero_uid32_fpFusedAddSubTest(LOGICAL,31)@1
fracXIsZero_uid32_fpFusedAddSubTest_q <= "1" WHEN cstZeroWF_uid12_fpFusedAddSubTest_q = frac_sigb_uid29_fpFusedAddSubTest_b ELSE "0";
-- fracXIsNotZero_uid33_fpFusedAddSubTest(LOGICAL,32)@1
fracXIsNotZero_uid33_fpFusedAddSubTest_q <= not (fracXIsZero_uid32_fpFusedAddSubTest_q);
-- expXIsMax_uid31_fpFusedAddSubTest(LOGICAL,30)@1
expXIsMax_uid31_fpFusedAddSubTest_q <= "1" WHEN exp_sigb_uid28_fpFusedAddSubTest_b = cstAllOWE_uid11_fpFusedAddSubTest_q ELSE "0";
-- excN_sigb_uid35_fpFusedAddSubTest(LOGICAL,34)@1
excN_sigb_uid35_fpFusedAddSubTest_q <= expXIsMax_uid31_fpFusedAddSubTest_q and fracXIsNotZero_uid33_fpFusedAddSubTest_q;
-- fracXIsZero_uid18_fpFusedAddSubTest(LOGICAL,17)@1
fracXIsZero_uid18_fpFusedAddSubTest_q <= "1" WHEN cstZeroWF_uid12_fpFusedAddSubTest_q = frac_siga_uid15_fpFusedAddSubTest_b ELSE "0";
-- fracXIsNotZero_uid19_fpFusedAddSubTest(LOGICAL,18)@1
fracXIsNotZero_uid19_fpFusedAddSubTest_q <= not (fracXIsZero_uid18_fpFusedAddSubTest_q);
-- excN_siga_uid21_fpFusedAddSubTest(LOGICAL,20)@1
excN_siga_uid21_fpFusedAddSubTest_q <= expXIsMax_uid17_fpFusedAddSubTest_q and fracXIsNotZero_uid19_fpFusedAddSubTest_q;
-- effSub_uid45_fpFusedAddSubTest(LOGICAL,44)@1
effSub_uid45_fpFusedAddSubTest_q <= sigA_uid43_fpFusedAddSubTest_b xor sigB_uid44_fpFusedAddSubTest_b;
-- invEffSub_uid106_fpFusedAddSubTest(LOGICAL,105)@1
invEffSub_uid106_fpFusedAddSubTest_q <= not (effSub_uid45_fpFusedAddSubTest_q);
-- excI_sigb_uid34_fpFusedAddSubTest(LOGICAL,33)@1
excI_sigb_uid34_fpFusedAddSubTest_q <= expXIsMax_uid31_fpFusedAddSubTest_q and fracXIsZero_uid32_fpFusedAddSubTest_q;
-- excI_siga_uid20_fpFusedAddSubTest(LOGICAL,19)@1
excI_siga_uid20_fpFusedAddSubTest_q <= expXIsMax_uid17_fpFusedAddSubTest_q and fracXIsZero_uid18_fpFusedAddSubTest_q;
-- infPinfForSub_uid107_fpFusedAddSubTest(LOGICAL,106)@1
infPinfForSub_uid107_fpFusedAddSubTest_q <= excI_siga_uid20_fpFusedAddSubTest_q and excI_sigb_uid34_fpFusedAddSubTest_q and invEffSub_uid106_fpFusedAddSubTest_q;
-- excRNaNS_uid108_fpFusedAddSubTest(LOGICAL,107)@1
excRNaNS_uid108_fpFusedAddSubTest_q <= infPinfForSub_uid107_fpFusedAddSubTest_q or excN_siga_uid21_fpFusedAddSubTest_q or excN_sigb_uid35_fpFusedAddSubTest_q;
-- invExcRNaNS_uid156_fpFusedAddSubTest(LOGICAL,155)@1
invExcRNaNS_uid156_fpFusedAddSubTest_q <= not (excRNaNS_uid108_fpFusedAddSubTest_q);
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- signRPostExcSub_uid157_fpFusedAddSubTest(LOGICAL,156)@1
signRPostExcSub_uid157_fpFusedAddSubTest_q <= invExcRNaNS_uid156_fpFusedAddSubTest_q and signRPostExcSub0_uid155_fpFusedAddSubTest_q and invSignInputsZeroForSub_uid148_fpFusedAddSubTest_q and invPositiveExc_uid146_fpFusedAddSubTest_q;
-- fracResAdd_uid64_fpFusedAddSubTest(ADD,63)@1
fracResAdd_uid64_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("000" & fracAOp_uid61_fpFusedAddSubTest_q);
fracResAdd_uid64_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("0" & fracBOp_uid62_fpFusedAddSubTest_q);
fracResAdd_uid64_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(fracResAdd_uid64_fpFusedAddSubTest_a) + UNSIGNED(fracResAdd_uid64_fpFusedAddSubTest_b));
fracResAdd_uid64_fpFusedAddSubTest_q <= fracResAdd_uid64_fpFusedAddSubTest_o(27 downto 0);
-- fracResAddNoSignExt_uid66_fpFusedAddSubTest(BITSELECT,65)@1
fracResAddNoSignExt_uid66_fpFusedAddSubTest_in <= fracResAdd_uid64_fpFusedAddSubTest_q(25 downto 0);
fracResAddNoSignExt_uid66_fpFusedAddSubTest_b <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_in(25 downto 0);
-- rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest(BITSELECT,192)@1
rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest_b <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(25 downto 10);
-- vCount_uid194_lzCountValAdd_uid69_fpFusedAddSubTest(LOGICAL,193)@1
vCount_uid194_lzCountValAdd_uid69_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest_b = zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest(BITSELECT,195)@1
vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(9 downto 0);
vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_b <= vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_in(9 downto 0);
-- cStage_uid197_lzCountValAdd_uid69_fpFusedAddSubTest(BITJOIN,196)@1
cStage_uid197_lzCountValAdd_uid69_fpFusedAddSubTest_q <= vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_b & mO_uid164_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest(MUX,198)@1
vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_s <= vCount_uid194_lzCountValAdd_uid69_fpFusedAddSubTest_q;
vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_s, rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest_b, cStage_uid197_lzCountValAdd_uid69_fpFusedAddSubTest_q)
BEGIN
CASE (vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest_b;
WHEN "1" => vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q <= cStage_uid197_lzCountValAdd_uid69_fpFusedAddSubTest_q;
WHEN OTHERS => vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select(BITSELECT,347)@1
rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q(15 downto 8);
rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q(7 downto 0);
-- vCount_uid202_lzCountValAdd_uid69_fpFusedAddSubTest(LOGICAL,201)@1
vCount_uid202_lzCountValAdd_uid69_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b = cstAllZWE_uid13_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest(MUX,204)@1
vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_s <= vCount_uid202_lzCountValAdd_uid69_fpFusedAddSubTest_q;
vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_s, rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select(BITSELECT,348)@1
rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q(7 downto 4);
rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q(3 downto 0);
-- vCount_uid208_lzCountValAdd_uid69_fpFusedAddSubTest(LOGICAL,207)@1
vCount_uid208_lzCountValAdd_uid69_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b = zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest(MUX,210)@1
vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_s <= vCount_uid208_lzCountValAdd_uid69_fpFusedAddSubTest_q;
vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_s, rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select(BITSELECT,349)@1
rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q(3 downto 2);
rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q(1 downto 0);
-- vCount_uid214_lzCountValAdd_uid69_fpFusedAddSubTest(LOGICAL,213)@1
vCount_uid214_lzCountValAdd_uid69_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b = zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest(MUX,216)@1
vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_s <= vCount_uid214_lzCountValAdd_uid69_fpFusedAddSubTest_q;
vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_s, rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid219_lzCountValAdd_uid69_fpFusedAddSubTest(BITSELECT,218)@1
rVStage_uid219_lzCountValAdd_uid69_fpFusedAddSubTest_b <= vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_q(1 downto 1);
-- vCount_uid220_lzCountValAdd_uid69_fpFusedAddSubTest(LOGICAL,219)@1
vCount_uid220_lzCountValAdd_uid69_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid219_lzCountValAdd_uid69_fpFusedAddSubTest_b = GND_q ELSE "0";
-- r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest(BITJOIN,220)@1
r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest_q <= vCount_uid194_lzCountValAdd_uid69_fpFusedAddSubTest_q & vCount_uid202_lzCountValAdd_uid69_fpFusedAddSubTest_q & vCount_uid208_lzCountValAdd_uid69_fpFusedAddSubTest_q & vCount_uid214_lzCountValAdd_uid69_fpFusedAddSubTest_q & vCount_uid220_lzCountValAdd_uid69_fpFusedAddSubTest_q;
-- expInc_uid73_fpFusedAddSubTest(ADD,72)@1
expInc_uid73_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("0" & exp_siga_uid14_fpFusedAddSubTest_b);
expInc_uid73_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expInc_uid73_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expInc_uid73_fpFusedAddSubTest_a) + UNSIGNED(expInc_uid73_fpFusedAddSubTest_b));
expInc_uid73_fpFusedAddSubTest_q <= expInc_uid73_fpFusedAddSubTest_o(8 downto 0);
-- expPostNormAdd_uid75_fpFusedAddSubTest(SUB,74)@1
expPostNormAdd_uid75_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("0" & expInc_uid73_fpFusedAddSubTest_q);
expPostNormAdd_uid75_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("00000" & r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest_q);
expPostNormAdd_uid75_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expPostNormAdd_uid75_fpFusedAddSubTest_a) - UNSIGNED(expPostNormAdd_uid75_fpFusedAddSubTest_b));
expPostNormAdd_uid75_fpFusedAddSubTest_q <= expPostNormAdd_uid75_fpFusedAddSubTest_o(9 downto 0);
-- leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,322)@1
leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q(22 downto 0);
leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_in(22 downto 0);
-- leftShiftStage1Idx3_uid324_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,323)@1
leftShiftStage1Idx3_uid324_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_b & rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,319)@1
leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q(23 downto 0);
leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_in(23 downto 0);
-- leftShiftStage1Idx2_uid321_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,320)@1
leftShiftStage1Idx2_uid321_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_b & zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,316)@1
leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q(24 downto 0);
leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_in(24 downto 0);
-- leftShiftStage1Idx1_uid318_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,317)@1
leftShiftStage1Idx1_uid318_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_b & GND_q;
-- leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest(CONSTANT,277)
leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q <= "00000000000000000000000000";
-- leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,310)@1
leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(1 downto 0);
leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_in(1 downto 0);
-- leftShiftStage0Idx6_uid312_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,311)@1
leftShiftStage0Idx6_uid312_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_b & rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,307)@1
leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(5 downto 0);
leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_in(5 downto 0);
-- leftShiftStage0Idx5_uid309_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,308)@1
leftShiftStage0Idx5_uid309_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_b & rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx4_uid306_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,305)@1
leftShiftStage0Idx4_uid306_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_b & zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1(MUX,340)@1
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_s <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_combproc: PROCESS (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_s, leftShiftStage0Idx4_uid306_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage0Idx5_uid309_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage0Idx6_uid312_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_s) IS
WHEN "00" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx4_uid306_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "01" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx5_uid309_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx6_uid312_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,301)@1
leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(13 downto 0);
leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_in(13 downto 0);
-- leftShiftStage0Idx3_uid303_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,302)@1
leftShiftStage0Idx3_uid303_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_b & rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,298)@1
leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(17 downto 0);
leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_in(17 downto 0);
-- leftShiftStage0Idx2_uid300_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,299)@1
leftShiftStage0Idx2_uid300_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_b & cstAllZWE_uid13_fpFusedAddSubTest_q;
-- leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,295)@1
leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(21 downto 0);
leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_in(21 downto 0);
-- leftShiftStage0Idx1_uid297_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,296)@1
leftShiftStage0Idx1_uid297_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_b & zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0(MUX,339)@1
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_s <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_combproc: PROCESS (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_s, fracResAddNoSignExt_uid66_fpFusedAddSubTest_b, leftShiftStage0Idx1_uid297_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage0Idx2_uid300_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage0Idx3_uid303_fracPostNormAdd_uid70_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_s) IS
WHEN "00" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b;
WHEN "01" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx1_uid297_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx2_uid300_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx3_uid303_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select(BITSELECT,353)@1
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_b <= leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_b(1 downto 0);
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_c <= leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_b(2 downto 2);
-- leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal(MUX,341)@1
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_s <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_c;
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_combproc: PROCESS (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_s, leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q, leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q)
BEGIN
CASE (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_s) IS
WHEN "0" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q;
WHEN "1" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q;
WHEN OTHERS => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select(BITSELECT,350)@1
leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_b <= r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest_q(4 downto 2);
leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_c <= r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest_q(1 downto 0);
-- leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest(MUX,325)@1
leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_s <= leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_c;
leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_combproc: PROCESS (leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_s, leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q, leftShiftStage1Idx1_uid318_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage1Idx2_uid321_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage1Idx3_uid324_fracPostNormAdd_uid70_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_s) IS
WHEN "00" => leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q;
WHEN "01" => leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx1_uid318_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx2_uid321_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx3_uid324_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracPostNormAddRndRange_uid78_fpFusedAddSubTest(BITSELECT,77)@1
fracPostNormAddRndRange_uid78_fpFusedAddSubTest_in <= leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q(24 downto 0);
fracPostNormAddRndRange_uid78_fpFusedAddSubTest_b <= fracPostNormAddRndRange_uid78_fpFusedAddSubTest_in(24 downto 1);
-- expFracRAdd_uid79_fpFusedAddSubTest(BITJOIN,78)@1
expFracRAdd_uid79_fpFusedAddSubTest_q <= expPostNormAdd_uid75_fpFusedAddSubTest_q & fracPostNormAddRndRange_uid78_fpFusedAddSubTest_b;
-- expRPreExcAdd_uid89_fpFusedAddSubTest(BITSELECT,88)@1
expRPreExcAdd_uid89_fpFusedAddSubTest_in <= expFracRAdd_uid79_fpFusedAddSubTest_q(31 downto 0);
expRPreExcAdd_uid89_fpFusedAddSubTest_b <= expRPreExcAdd_uid89_fpFusedAddSubTest_in(31 downto 24);
-- expPostNormSub_uid74_fpFusedAddSubTest(SUB,73)@1
expPostNormSub_uid74_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("0" & expInc_uid73_fpFusedAddSubTest_q);
expPostNormSub_uid74_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("00000" & r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q);
expPostNormSub_uid74_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expPostNormSub_uid74_fpFusedAddSubTest_a) - UNSIGNED(expPostNormSub_uid74_fpFusedAddSubTest_b));
expPostNormSub_uid74_fpFusedAddSubTest_q <= expPostNormSub_uid74_fpFusedAddSubTest_o(9 downto 0);
-- leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,287)@1
leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_in <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q(22 downto 0);
leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_in(22 downto 0);
-- leftShiftStage1Idx3_uid289_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,288)@1
leftShiftStage1Idx3_uid289_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_b & rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,284)@1
leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_in <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q(23 downto 0);
leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_in(23 downto 0);
-- leftShiftStage1Idx2_uid286_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,285)@1
leftShiftStage1Idx2_uid286_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_b & zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,281)@1
leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_in <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q(24 downto 0);
leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_in(24 downto 0);
-- leftShiftStage1Idx1_uid283_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,282)@1
leftShiftStage1Idx1_uid283_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_b & GND_q;
-- leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,275)@1
leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(1 downto 0);
leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_in(1 downto 0);
-- leftShiftStage0Idx6_uid277_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,276)@1
leftShiftStage0Idx6_uid277_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_b & rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,272)@1
leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(5 downto 0);
leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_in(5 downto 0);
-- leftShiftStage0Idx5_uid274_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,273)@1
leftShiftStage0Idx5_uid274_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_b & rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx4_uid271_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,270)@1
leftShiftStage0Idx4_uid271_fracPostNormSub_uid68_fpFusedAddSubTest_q <= vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_b & zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1(MUX,335)@1
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_s <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_combproc: PROCESS (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_s, leftShiftStage0Idx4_uid271_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage0Idx5_uid274_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage0Idx6_uid277_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_s) IS
WHEN "00" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx4_uid271_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "01" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx5_uid274_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx6_uid277_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,266)@1
leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(13 downto 0);
leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_in(13 downto 0);
-- leftShiftStage0Idx3_uid268_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,267)@1
leftShiftStage0Idx3_uid268_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_b & rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,263)@1
leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(17 downto 0);
leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_in(17 downto 0);
-- leftShiftStage0Idx2_uid265_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,264)@1
leftShiftStage0Idx2_uid265_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_b & cstAllZWE_uid13_fpFusedAddSubTest_q;
-- leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,260)@1
leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(21 downto 0);
leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_in(21 downto 0);
-- leftShiftStage0Idx1_uid262_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,261)@1
leftShiftStage0Idx1_uid262_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_b & zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0(MUX,334)@1
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_s <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_combproc: PROCESS (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_s, fracResSubNoSignExt_uid65_fpFusedAddSubTest_b, leftShiftStage0Idx1_uid262_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage0Idx2_uid265_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage0Idx3_uid268_fracPostNormSub_uid68_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_s) IS
WHEN "00" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b;
WHEN "01" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx1_uid262_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx2_uid265_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx3_uid268_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select(BITSELECT,352)@1
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_b <= leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_b(1 downto 0);
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_c <= leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_b(2 downto 2);
-- leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal(MUX,336)@1
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_s <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_c;
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_combproc: PROCESS (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_s, leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q, leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q)
BEGIN
CASE (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_s) IS
WHEN "0" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q;
WHEN "1" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q;
WHEN OTHERS => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select(BITSELECT,346)@1
leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_b <= r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q(4 downto 2);
leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_c <= r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q(1 downto 0);
-- leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest(MUX,290)@1
leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_s <= leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_c;
leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_combproc: PROCESS (leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_s, leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q, leftShiftStage1Idx1_uid283_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage1Idx2_uid286_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage1Idx3_uid289_fracPostNormSub_uid68_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_s) IS
WHEN "00" => leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q;
WHEN "01" => leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx1_uid283_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx2_uid286_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx3_uid289_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracPostNormSubRndRange_uid76_fpFusedAddSubTest(BITSELECT,75)@1
fracPostNormSubRndRange_uid76_fpFusedAddSubTest_in <= leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q(24 downto 0);
fracPostNormSubRndRange_uid76_fpFusedAddSubTest_b <= fracPostNormSubRndRange_uid76_fpFusedAddSubTest_in(24 downto 1);
-- expFracRSub_uid77_fpFusedAddSubTest(BITJOIN,76)@1
expFracRSub_uid77_fpFusedAddSubTest_q <= expPostNormSub_uid74_fpFusedAddSubTest_q & fracPostNormSubRndRange_uid76_fpFusedAddSubTest_b;
-- expRPreExcSub_uid86_fpFusedAddSubTest(BITSELECT,85)@1
expRPreExcSub_uid86_fpFusedAddSubTest_in <= expFracRSub_uid77_fpFusedAddSubTest_q(31 downto 0);
expRPreExcSub_uid86_fpFusedAddSubTest_b <= expRPreExcSub_uid86_fpFusedAddSubTest_in(31 downto 24);
-- expRPreExcSubtraction_uid116_fpFusedAddSubTest(MUX,115)@1
expRPreExcSubtraction_uid116_fpFusedAddSubTest_s <= effSub_uid45_fpFusedAddSubTest_q;
expRPreExcSubtraction_uid116_fpFusedAddSubTest_combproc: PROCESS (expRPreExcSubtraction_uid116_fpFusedAddSubTest_s, expRPreExcSub_uid86_fpFusedAddSubTest_b, expRPreExcAdd_uid89_fpFusedAddSubTest_b)
BEGIN
CASE (expRPreExcSubtraction_uid116_fpFusedAddSubTest_s) IS
WHEN "0" => expRPreExcSubtraction_uid116_fpFusedAddSubTest_q <= expRPreExcSub_uid86_fpFusedAddSubTest_b;
WHEN "1" => expRPreExcSubtraction_uid116_fpFusedAddSubTest_q <= expRPreExcAdd_uid89_fpFusedAddSubTest_b;
WHEN OTHERS => expRPreExcSubtraction_uid116_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- wEP2AllOwE_uid80_fpFusedAddSubTest(CONSTANT,79)
wEP2AllOwE_uid80_fpFusedAddSubTest_q <= "0011111111";
-- rndExp_uid81_fpFusedAddSubTest(BITSELECT,80)@1
rndExp_uid81_fpFusedAddSubTest_b <= expFracRAdd_uid79_fpFusedAddSubTest_q(33 downto 24);
-- rOvf_uid82_fpFusedAddSubTest(LOGICAL,81)@1
rOvf_uid82_fpFusedAddSubTest_q <= "1" WHEN rndExp_uid81_fpFusedAddSubTest_b = wEP2AllOwE_uid80_fpFusedAddSubTest_q ELSE "0";
-- invExpXIsMax_uid36_fpFusedAddSubTest(LOGICAL,35)@1
invExpXIsMax_uid36_fpFusedAddSubTest_q <= not (expXIsMax_uid31_fpFusedAddSubTest_q);
-- excR_sigb_uid38_fpFusedAddSubTest(LOGICAL,37)@1
excR_sigb_uid38_fpFusedAddSubTest_q <= InvExpXIsZero_uid37_fpFusedAddSubTest_q and invExpXIsMax_uid36_fpFusedAddSubTest_q;
-- regInputs_uid91_fpFusedAddSubTest(LOGICAL,90)@1
regInputs_uid91_fpFusedAddSubTest_q <= excR_siga_uid24_fpFusedAddSubTest_q and excR_sigb_uid38_fpFusedAddSubTest_q;
-- regInAndOvf_uid95_fpFusedAddSubTest(LOGICAL,94)@1
regInAndOvf_uid95_fpFusedAddSubTest_q <= regInputs_uid91_fpFusedAddSubTest_q and rOvf_uid82_fpFusedAddSubTest_q;
-- excRInfVInC_uid99_fpFusedAddSubTest(BITJOIN,98)@1
excRInfVInC_uid99_fpFusedAddSubTest_q <= regInAndOvf_uid95_fpFusedAddSubTest_q & excZ_sigb_uid10_uid30_fpFusedAddSubTest_q & excZ_siga_uid9_uid16_fpFusedAddSubTest_q & excI_sigb_uid34_fpFusedAddSubTest_q & excI_siga_uid20_fpFusedAddSubTest_q & effSub_uid45_fpFusedAddSubTest_q;
-- excRInfSub_uid102_fpFusedAddSubTest(LOOKUP,101)@1
excRInfSub_uid102_fpFusedAddSubTest_combproc: PROCESS (excRInfVInC_uid99_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (excRInfVInC_uid99_fpFusedAddSubTest_q) IS
WHEN "000000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "001000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "001001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "001010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "001011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "001100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "001101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "001110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "001111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "010011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "010100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "100010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN OTHERS => -- unreachable
excRInfSub_uid102_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- oneIsInfOrZero_uid97_fpFusedAddSubTest(LOGICAL,96)@1
oneIsInfOrZero_uid97_fpFusedAddSubTest_q <= excR_siga_uid24_fpFusedAddSubTest_q or excR_sigb_uid38_fpFusedAddSubTest_q or excZ_siga_uid9_uid16_fpFusedAddSubTest_q or excZ_sigb_uid10_uid30_fpFusedAddSubTest_q;
-- oneIsInf_uid96_fpFusedAddSubTest(LOGICAL,95)@1
oneIsInf_uid96_fpFusedAddSubTest_q <= excI_siga_uid20_fpFusedAddSubTest_q or excI_sigb_uid34_fpFusedAddSubTest_q;
-- addIsAlsoInf_uid98_fpFusedAddSubTest(LOGICAL,97)@1
addIsAlsoInf_uid98_fpFusedAddSubTest_q <= oneIsInf_uid96_fpFusedAddSubTest_q and oneIsInfOrZero_uid97_fpFusedAddSubTest_q;
-- excRInfSubFull_uid103_fpFusedAddSubTest(LOGICAL,102)@1
excRInfSubFull_uid103_fpFusedAddSubTest_q <= addIsAlsoInf_uid98_fpFusedAddSubTest_q or excRInfSub_uid102_fpFusedAddSubTest_q;
-- signedExp_uid83_fpFusedAddSubTest(BITSELECT,82)@1
signedExp_uid83_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(expFracRSub_uid77_fpFusedAddSubTest_q(33 downto 24));
-- rUdf_uid84_fpFusedAddSubTest(COMPARE,83)@1
rUdf_uid84_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000000000" & GND_q));
rUdf_uid84_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((11 downto 10 => signedExp_uid83_fpFusedAddSubTest_b(9)) & signedExp_uid83_fpFusedAddSubTest_b));
rUdf_uid84_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(SIGNED(rUdf_uid84_fpFusedAddSubTest_a) - SIGNED(rUdf_uid84_fpFusedAddSubTest_b));
rUdf_uid84_fpFusedAddSubTest_n(0) <= not (rUdf_uid84_fpFusedAddSubTest_o(11));
-- excRZeroVInC_uid92_fpFusedAddSubTest(BITJOIN,91)@1
excRZeroVInC_uid92_fpFusedAddSubTest_q <= effSub_uid45_fpFusedAddSubTest_q & aMinusA_uid72_fpFusedAddSubTest_q & rUdf_uid84_fpFusedAddSubTest_n & regInputs_uid91_fpFusedAddSubTest_q & excZ_sigb_uid10_uid30_fpFusedAddSubTest_q & excZ_siga_uid9_uid16_fpFusedAddSubTest_q;
-- excRZeroSub_uid94_fpFusedAddSubTest(LOOKUP,93)@1
excRZeroSub_uid94_fpFusedAddSubTest_combproc: PROCESS (excRZeroVInC_uid92_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (excRZeroVInC_uid92_fpFusedAddSubTest_q) IS
WHEN "000000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "1";
WHEN "000100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "1";
WHEN "001101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "1";
WHEN "010101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "1";
WHEN "011101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN OTHERS => -- unreachable
excRZeroSub_uid94_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- concExcSub_uid109_fpFusedAddSubTest(BITJOIN,108)@1
concExcSub_uid109_fpFusedAddSubTest_q <= excRNaNS_uid108_fpFusedAddSubTest_q & excRInfSubFull_uid103_fpFusedAddSubTest_q & excRZeroSub_uid94_fpFusedAddSubTest_q;
-- excREncSub_uid111_fpFusedAddSubTest(LOOKUP,110)@1
excREncSub_uid111_fpFusedAddSubTest_combproc: PROCESS (concExcSub_uid109_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExcSub_uid109_fpFusedAddSubTest_q) IS
WHEN "000" => excREncSub_uid111_fpFusedAddSubTest_q <= "01";
WHEN "001" => excREncSub_uid111_fpFusedAddSubTest_q <= "00";
WHEN "010" => excREncSub_uid111_fpFusedAddSubTest_q <= "10";
WHEN "011" => excREncSub_uid111_fpFusedAddSubTest_q <= "00";
WHEN "100" => excREncSub_uid111_fpFusedAddSubTest_q <= "11";
WHEN "101" => excREncSub_uid111_fpFusedAddSubTest_q <= "00";
WHEN "110" => excREncSub_uid111_fpFusedAddSubTest_q <= "00";
WHEN "111" => excREncSub_uid111_fpFusedAddSubTest_q <= "00";
WHEN OTHERS => -- unreachable
excREncSub_uid111_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExcSub_uid144_fpFusedAddSubTest(MUX,143)@1
expRPostExcSub_uid144_fpFusedAddSubTest_s <= excREncSub_uid111_fpFusedAddSubTest_q;
expRPostExcSub_uid144_fpFusedAddSubTest_combproc: PROCESS (expRPostExcSub_uid144_fpFusedAddSubTest_s, cstAllZWE_uid13_fpFusedAddSubTest_q, expRPreExcSubtraction_uid116_fpFusedAddSubTest_q, cstAllOWE_uid11_fpFusedAddSubTest_q)
BEGIN
CASE (expRPostExcSub_uid144_fpFusedAddSubTest_s) IS
WHEN "00" => expRPostExcSub_uid144_fpFusedAddSubTest_q <= cstAllZWE_uid13_fpFusedAddSubTest_q;
WHEN "01" => expRPostExcSub_uid144_fpFusedAddSubTest_q <= expRPreExcSubtraction_uid116_fpFusedAddSubTest_q;
WHEN "10" => expRPostExcSub_uid144_fpFusedAddSubTest_q <= cstAllOWE_uid11_fpFusedAddSubTest_q;
WHEN "11" => expRPostExcSub_uid144_fpFusedAddSubTest_q <= cstAllOWE_uid11_fpFusedAddSubTest_q;
WHEN OTHERS => expRPostExcSub_uid144_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- oneFracRPostExc2_uid117_fpFusedAddSubTest(CONSTANT,116)
oneFracRPostExc2_uid117_fpFusedAddSubTest_q <= "00000000000000000000001";
-- fracRPreExcAdd_uid88_fpFusedAddSubTest(BITSELECT,87)@1
fracRPreExcAdd_uid88_fpFusedAddSubTest_in <= expFracRAdd_uid79_fpFusedAddSubTest_q(23 downto 0);
fracRPreExcAdd_uid88_fpFusedAddSubTest_b <= fracRPreExcAdd_uid88_fpFusedAddSubTest_in(23 downto 1);
-- fracRPreExcSub_uid85_fpFusedAddSubTest(BITSELECT,84)@1
fracRPreExcSub_uid85_fpFusedAddSubTest_in <= expFracRSub_uid77_fpFusedAddSubTest_q(23 downto 0);
fracRPreExcSub_uid85_fpFusedAddSubTest_b <= fracRPreExcSub_uid85_fpFusedAddSubTest_in(23 downto 1);
-- fracRPreExcSubtraction_uid115_fpFusedAddSubTest(MUX,114)@1
fracRPreExcSubtraction_uid115_fpFusedAddSubTest_s <= effSub_uid45_fpFusedAddSubTest_q;
fracRPreExcSubtraction_uid115_fpFusedAddSubTest_combproc: PROCESS (fracRPreExcSubtraction_uid115_fpFusedAddSubTest_s, fracRPreExcSub_uid85_fpFusedAddSubTest_b, fracRPreExcAdd_uid88_fpFusedAddSubTest_b)
BEGIN
CASE (fracRPreExcSubtraction_uid115_fpFusedAddSubTest_s) IS
WHEN "0" => fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q <= fracRPreExcSub_uid85_fpFusedAddSubTest_b;
WHEN "1" => fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q <= fracRPreExcAdd_uid88_fpFusedAddSubTest_b;
WHEN OTHERS => fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracRPostExcSub_uid140_fpFusedAddSubTest(MUX,139)@1
fracRPostExcSub_uid140_fpFusedAddSubTest_s <= excREncSub_uid111_fpFusedAddSubTest_q;
fracRPostExcSub_uid140_fpFusedAddSubTest_combproc: PROCESS (fracRPostExcSub_uid140_fpFusedAddSubTest_s, cstZeroWF_uid12_fpFusedAddSubTest_q, fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q, oneFracRPostExc2_uid117_fpFusedAddSubTest_q)
BEGIN
CASE (fracRPostExcSub_uid140_fpFusedAddSubTest_s) IS
WHEN "00" => fracRPostExcSub_uid140_fpFusedAddSubTest_q <= cstZeroWF_uid12_fpFusedAddSubTest_q;
WHEN "01" => fracRPostExcSub_uid140_fpFusedAddSubTest_q <= fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q;
WHEN "10" => fracRPostExcSub_uid140_fpFusedAddSubTest_q <= cstZeroWF_uid12_fpFusedAddSubTest_q;
WHEN "11" => fracRPostExcSub_uid140_fpFusedAddSubTest_q <= oneFracRPostExc2_uid117_fpFusedAddSubTest_q;
WHEN OTHERS => fracRPostExcSub_uid140_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- RDiff_uid158_fpFusedAddSubTest(BITJOIN,157)@1
RDiff_uid158_fpFusedAddSubTest_q <= signRPostExcSub_uid157_fpFusedAddSubTest_q & expRPostExcSub_uid144_fpFusedAddSubTest_q & fracRPostExcSub_uid140_fpFusedAddSubTest_q;
-- invSigA_uid126_fpFusedAddSubTest(LOGICAL,125)@1
invSigA_uid126_fpFusedAddSubTest_q <= not (sigA_uid43_fpFusedAddSubTest_b);
-- signInputsZeroSwap_uid127_fpFusedAddSubTest(LOGICAL,126)@1
signInputsZeroSwap_uid127_fpFusedAddSubTest_q <= excZ_siga_uid9_uid16_fpFusedAddSubTest_q and excZ_sigb_uid10_uid30_fpFusedAddSubTest_q and invSigA_uid126_fpFusedAddSubTest_q and sigB_uid44_fpFusedAddSubTest_b and invXGTEy_uid125_fpFusedAddSubTest_q;
-- invSignInputsZeroSwap_uid128_fpFusedAddSubTest(LOGICAL,127)@1
invSignInputsZeroSwap_uid128_fpFusedAddSubTest_q <= not (signInputsZeroSwap_uid127_fpFusedAddSubTest_q);
-- invSigB_uid129_fpFusedAddSubTest(LOGICAL,128)@1
invSigB_uid129_fpFusedAddSubTest_q <= not (sigB_uid44_fpFusedAddSubTest_b);
-- signInputsZeroNoSwap_uid130_fpFusedAddSubTest(LOGICAL,129)@1
signInputsZeroNoSwap_uid130_fpFusedAddSubTest_q <= excZ_siga_uid9_uid16_fpFusedAddSubTest_q and excZ_sigb_uid10_uid30_fpFusedAddSubTest_q and sigA_uid43_fpFusedAddSubTest_b and invSigB_uid129_fpFusedAddSubTest_q and xGTEy_uid8_fpFusedAddSubTest_n;
-- invSignInputsZeroNoSwap_uid131_fpFusedAddSubTest(LOGICAL,130)@1
invSignInputsZeroNoSwap_uid131_fpFusedAddSubTest_q <= not (signInputsZeroNoSwap_uid130_fpFusedAddSubTest_q);
-- aMa_uid132_fpFusedAddSubTest(LOGICAL,131)@1
aMa_uid132_fpFusedAddSubTest_q <= aMinusA_uid72_fpFusedAddSubTest_q and effSub_uid45_fpFusedAddSubTest_q;
-- invAMA_uid133_fpFusedAddSubTest(LOGICAL,132)@1
invAMA_uid133_fpFusedAddSubTest_q <= not (aMa_uid132_fpFusedAddSubTest_q);
-- infMinf_uid104_fpFusedAddSubTest(LOGICAL,103)@1
infMinf_uid104_fpFusedAddSubTest_q <= excI_siga_uid20_fpFusedAddSubTest_q and excI_sigb_uid34_fpFusedAddSubTest_q and effSub_uid45_fpFusedAddSubTest_q;
-- excRNaNA_uid105_fpFusedAddSubTest(LOGICAL,104)@1
excRNaNA_uid105_fpFusedAddSubTest_q <= infMinf_uid104_fpFusedAddSubTest_q or excN_siga_uid21_fpFusedAddSubTest_q or excN_sigb_uid35_fpFusedAddSubTest_q;
-- invExcRNaNA_uid134_fpFusedAddSubTest(LOGICAL,133)@1
invExcRNaNA_uid134_fpFusedAddSubTest_q <= not (excRNaNA_uid105_fpFusedAddSubTest_q);
-- signRPostExc_uid135_fpFusedAddSubTest(LOGICAL,134)@1
signRPostExc_uid135_fpFusedAddSubTest_q <= invExcRNaNA_uid134_fpFusedAddSubTest_q and sigA_uid43_fpFusedAddSubTest_b and invAMA_uid133_fpFusedAddSubTest_q and invSignInputsZeroNoSwap_uid131_fpFusedAddSubTest_q and invSignInputsZeroSwap_uid128_fpFusedAddSubTest_q;
-- expRPreExcAddition_uid114_fpFusedAddSubTest(MUX,113)@1
expRPreExcAddition_uid114_fpFusedAddSubTest_s <= effSub_uid45_fpFusedAddSubTest_q;
expRPreExcAddition_uid114_fpFusedAddSubTest_combproc: PROCESS (expRPreExcAddition_uid114_fpFusedAddSubTest_s, expRPreExcAdd_uid89_fpFusedAddSubTest_b, expRPreExcSub_uid86_fpFusedAddSubTest_b)
BEGIN
CASE (expRPreExcAddition_uid114_fpFusedAddSubTest_s) IS
WHEN "0" => expRPreExcAddition_uid114_fpFusedAddSubTest_q <= expRPreExcAdd_uid89_fpFusedAddSubTest_b;
WHEN "1" => expRPreExcAddition_uid114_fpFusedAddSubTest_q <= expRPreExcSub_uid86_fpFusedAddSubTest_b;
WHEN OTHERS => expRPreExcAddition_uid114_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- excRInfAdd_uid100_fpFusedAddSubTest(LOOKUP,99)@1
excRInfAdd_uid100_fpFusedAddSubTest_combproc: PROCESS (excRInfVInC_uid99_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (excRInfVInC_uid99_fpFusedAddSubTest_q) IS
WHEN "000000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "000111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "001101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "001110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "010011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "010100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "100001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN OTHERS => -- unreachable
excRInfAdd_uid100_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- excRInfAddFull_uid101_fpFusedAddSubTest(LOGICAL,100)@1
excRInfAddFull_uid101_fpFusedAddSubTest_q <= addIsAlsoInf_uid98_fpFusedAddSubTest_q or excRInfAdd_uid100_fpFusedAddSubTest_q;
-- excRZeroAdd_uid93_fpFusedAddSubTest(LOOKUP,92)@1
excRZeroAdd_uid93_fpFusedAddSubTest_combproc: PROCESS (excRZeroVInC_uid92_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (excRZeroVInC_uid92_fpFusedAddSubTest_q) IS
WHEN "000000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "1";
WHEN "000100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "1";
WHEN "101101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "1";
WHEN "110101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "1";
WHEN "111101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN OTHERS => -- unreachable
excRZeroAdd_uid93_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- concExcAdd_uid110_fpFusedAddSubTest(BITJOIN,109)@1
concExcAdd_uid110_fpFusedAddSubTest_q <= excRNaNA_uid105_fpFusedAddSubTest_q & excRInfAddFull_uid101_fpFusedAddSubTest_q & excRZeroAdd_uid93_fpFusedAddSubTest_q;
-- excREncAdd_uid112_fpFusedAddSubTest(LOOKUP,111)@1
excREncAdd_uid112_fpFusedAddSubTest_combproc: PROCESS (concExcAdd_uid110_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExcAdd_uid110_fpFusedAddSubTest_q) IS
WHEN "000" => excREncAdd_uid112_fpFusedAddSubTest_q <= "01";
WHEN "001" => excREncAdd_uid112_fpFusedAddSubTest_q <= "00";
WHEN "010" => excREncAdd_uid112_fpFusedAddSubTest_q <= "10";
WHEN "011" => excREncAdd_uid112_fpFusedAddSubTest_q <= "00";
WHEN "100" => excREncAdd_uid112_fpFusedAddSubTest_q <= "11";
WHEN "101" => excREncAdd_uid112_fpFusedAddSubTest_q <= "00";
WHEN "110" => excREncAdd_uid112_fpFusedAddSubTest_q <= "00";
WHEN "111" => excREncAdd_uid112_fpFusedAddSubTest_q <= "00";
WHEN OTHERS => -- unreachable
excREncAdd_uid112_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExcAdd_uid124_fpFusedAddSubTest(MUX,123)@1
expRPostExcAdd_uid124_fpFusedAddSubTest_s <= excREncAdd_uid112_fpFusedAddSubTest_q;
expRPostExcAdd_uid124_fpFusedAddSubTest_combproc: PROCESS (expRPostExcAdd_uid124_fpFusedAddSubTest_s, cstAllZWE_uid13_fpFusedAddSubTest_q, expRPreExcAddition_uid114_fpFusedAddSubTest_q, cstAllOWE_uid11_fpFusedAddSubTest_q)
BEGIN
CASE (expRPostExcAdd_uid124_fpFusedAddSubTest_s) IS
WHEN "00" => expRPostExcAdd_uid124_fpFusedAddSubTest_q <= cstAllZWE_uid13_fpFusedAddSubTest_q;
WHEN "01" => expRPostExcAdd_uid124_fpFusedAddSubTest_q <= expRPreExcAddition_uid114_fpFusedAddSubTest_q;
WHEN "10" => expRPostExcAdd_uid124_fpFusedAddSubTest_q <= cstAllOWE_uid11_fpFusedAddSubTest_q;
WHEN "11" => expRPostExcAdd_uid124_fpFusedAddSubTest_q <= cstAllOWE_uid11_fpFusedAddSubTest_q;
WHEN OTHERS => expRPostExcAdd_uid124_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracRPreExcAddition_uid113_fpFusedAddSubTest(MUX,112)@1
fracRPreExcAddition_uid113_fpFusedAddSubTest_s <= effSub_uid45_fpFusedAddSubTest_q;
fracRPreExcAddition_uid113_fpFusedAddSubTest_combproc: PROCESS (fracRPreExcAddition_uid113_fpFusedAddSubTest_s, fracRPreExcAdd_uid88_fpFusedAddSubTest_b, fracRPreExcSub_uid85_fpFusedAddSubTest_b)
BEGIN
CASE (fracRPreExcAddition_uid113_fpFusedAddSubTest_s) IS
WHEN "0" => fracRPreExcAddition_uid113_fpFusedAddSubTest_q <= fracRPreExcAdd_uid88_fpFusedAddSubTest_b;
WHEN "1" => fracRPreExcAddition_uid113_fpFusedAddSubTest_q <= fracRPreExcSub_uid85_fpFusedAddSubTest_b;
WHEN OTHERS => fracRPreExcAddition_uid113_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracRPostExcAdd_uid120_fpFusedAddSubTest(MUX,119)@1
fracRPostExcAdd_uid120_fpFusedAddSubTest_s <= excREncAdd_uid112_fpFusedAddSubTest_q;
fracRPostExcAdd_uid120_fpFusedAddSubTest_combproc: PROCESS (fracRPostExcAdd_uid120_fpFusedAddSubTest_s, cstZeroWF_uid12_fpFusedAddSubTest_q, fracRPreExcAddition_uid113_fpFusedAddSubTest_q, oneFracRPostExc2_uid117_fpFusedAddSubTest_q)
BEGIN
CASE (fracRPostExcAdd_uid120_fpFusedAddSubTest_s) IS
WHEN "00" => fracRPostExcAdd_uid120_fpFusedAddSubTest_q <= cstZeroWF_uid12_fpFusedAddSubTest_q;
WHEN "01" => fracRPostExcAdd_uid120_fpFusedAddSubTest_q <= fracRPreExcAddition_uid113_fpFusedAddSubTest_q;
WHEN "10" => fracRPostExcAdd_uid120_fpFusedAddSubTest_q <= cstZeroWF_uid12_fpFusedAddSubTest_q;
WHEN "11" => fracRPostExcAdd_uid120_fpFusedAddSubTest_q <= oneFracRPostExc2_uid117_fpFusedAddSubTest_q;
WHEN OTHERS => fracRPostExcAdd_uid120_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- RSum_uid136_fpFusedAddSubTest(BITJOIN,135)@1
RSum_uid136_fpFusedAddSubTest_q <= signRPostExc_uid135_fpFusedAddSubTest_q & expRPostExcAdd_uid124_fpFusedAddSubTest_q & fracRPostExcAdd_uid120_fpFusedAddSubTest_q;
-- xOut(GPOUT,4)@1
q <= RSum_uid136_fpFusedAddSubTest_q;
s <= RDiff_uid158_fpFusedAddSubTest_q;
END normal;
|
mit
|
a4a10cd11679f0a3209e71d4718a6144
| 0.760403 | 4.039278 | false | true | false | false |
lnls-dig/bpm-gw
|
hdl/modules/position_calc/position_calc.vhd
| 1 | 44,346 |
-------------------------------------------------------------------------------
-- Title : Position calc, no sysgen generator
-- Project :
-------------------------------------------------------------------------------
-- File : position_calc.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-06
-- Last update: 2016-05-02
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Position calculation with no sysgen parts
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-06 1.0 aylons Created
-- 2014-10-06 2.0 vfinotti CreatedHotfix
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.dsp_cores_pkg.all;
use work.genram_pkg.all;
use work.bpm_cores_pkg.all;
entity position_calc is
generic(
-- selection of position_calc stages
g_with_downconv : boolean := true;
-- input sizes
g_input_width : natural := 16;
g_mixed_width : natural := 16;
g_adc_ratio : natural := 1;
-- mixer
g_dds_width : natural := 16;
g_dds_points : natural := 35;
g_sin_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_sin.nif";
g_cos_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_cos.nif";
-- desync counter width. Tied to register width
g_tbt_tag_desync_cnt_width : natural := 14;
-- width of CIC mask number of samples
g_tbt_cic_mask_samples_width : natural := 16;
-- CIC setup
g_tbt_cic_delay : natural := 1;
g_tbt_cic_stages : natural := 2;
g_tbt_ratio : natural := 35; -- ratio between
g_tbt_decim_width : natural := 32;
g_fofb_cic_delay : natural := 1;
g_fofb_cic_stages : natural := 2;
g_fofb_ratio : natural := 980; -- ratio between adc and fofb rates
g_fofb_decim_width : natural := 32;
-- desync counter width. Tied to register width
g_fofb_decim_desync_cnt_width : natural := 14;
-- width of CIC mask number of samples
g_fofb_cic_mask_samples_width : natural := 16;
g_monit1_cic_delay : natural := 1;
g_monit1_cic_stages : natural := 1;
g_monit1_ratio : natural := 100; --ratio between fofb and monit 1
g_monit1_cic_ratio : positive := 8;
-- desync counter width. Tied to register width
g_monit1_tag_desync_cnt_width : natural := 14;
-- width of CIC mask number of samples
g_monit1_cic_mask_samples_width : natural := 16;
g_monit2_cic_delay : natural := 1;
g_monit2_cic_stages : natural := 1;
g_monit2_ratio : natural := 100; -- ratio between monit 1 and 2
g_monit2_cic_ratio : positive := 8;
-- desync counter width. Tied to register width
g_monit2_tag_desync_cnt_width : natural := 14;
-- width of CIC mask number of samples
g_monit2_cic_mask_samples_width : natural := 16;
g_monit_decim_width : natural := 32;
-- Cordic setup
g_tbt_cordic_stages : positive := 12;
g_tbt_cordic_iter_per_clk : positive := 3;
g_tbt_cordic_ratio : positive := 4;
g_fofb_cordic_stages : positive := 15;
g_fofb_cordic_iter_per_clk : positive := 3;
g_fofb_cordic_ratio : positive := 4;
-- width of K constants
g_k_width : natural := 25;
-- width of offset constants
g_offset_width : natural := 32;
--width for IQ output
g_IQ_width : natural := 32
);
port(
adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch2_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch3_i : in std_logic_vector(g_input_width-1 downto 0);
adc_tag_i : in std_logic_vector(0 downto 0);
adc_tag_en_i : in std_logic := '0';
adc_valid_i : in std_logic;
clk_i : in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
rst_i : in std_logic; -- clear signal
ksum_i : in std_logic_vector(g_k_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
offset_x_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
offset_y_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_valid_o : out std_logic;
mix_ce_o : out std_logic;
tbt_tag_i : in std_logic_vector(0 downto 0);
tbt_tag_en_i : in std_logic := '0';
tbt_tag_desync_cnt_rst_i : in std_logic := '0';
tbt_tag_desync_cnt_o : out std_logic_vector(g_tbt_tag_desync_cnt_width-1 downto 0);
tbt_decim_mask_en_i : in std_logic := '0';
tbt_decim_mask_num_samples_beg_i : in unsigned(g_tbt_cic_mask_samples_width-1 downto 0) := (others => '0');
tbt_decim_mask_num_samples_end_i : in unsigned(g_tbt_cic_mask_samples_width-1 downto 0) := (others => '0');
tbt_decim_ch0_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_decim_ce_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_amp_ce_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_valid_o : out std_logic;
tbt_pha_ce_o : out std_logic;
fofb_decim_desync_cnt_rst_i : in std_logic := '0';
fofb_decim_desync_cnt_o : out std_logic_vector(g_fofb_decim_desync_cnt_width-1 downto 0);
fofb_decim_mask_en_i : in std_logic := '0';
fofb_decim_mask_num_samples_i : in unsigned(g_fofb_cic_mask_samples_width-1 downto 0) := (others => '0');
fofb_decim_ch0_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_decim_ce_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_amp_ce_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_valid_o : out std_logic;
fofb_pha_ce_o : out std_logic;
monit1_tag_i : in std_logic_vector(0 downto 0);
monit1_tag_en_i : in std_logic := '0';
monit1_tag_desync_cnt_rst_i : in std_logic := '0';
monit1_tag_desync_cnt_o : out std_logic_vector(g_monit1_tag_desync_cnt_width-1 downto 0);
monit1_decim_mask_en_i : in std_logic := '0';
monit1_decim_mask_num_samples_beg_i : in unsigned(g_monit1_cic_mask_samples_width-1 downto 0) := (others => '0');
monit1_decim_mask_num_samples_end_i : in unsigned(g_monit1_cic_mask_samples_width-1 downto 0) := (others => '0');
monit1_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_valid_o : out std_logic;
monit1_amp_ce_o : out std_logic;
monit_tag_i : in std_logic_vector(0 downto 0);
monit_tag_en_i : in std_logic := '0';
monit_tag_desync_cnt_rst_i : in std_logic := '0';
monit_tag_desync_cnt_o : out std_logic_vector(g_monit2_tag_desync_cnt_width-1 downto 0);
monit_decim_mask_en_i : in std_logic := '0';
monit_decim_mask_num_samples_beg_i : in unsigned(g_monit2_cic_mask_samples_width-1 downto 0) := (others => '0');
monit_decim_mask_num_samples_end_i : in unsigned(g_monit2_cic_mask_samples_width-1 downto 0) := (others => '0');
monit_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_valid_o : out std_logic;
monit_amp_ce_o : out std_logic;
tbt_pos_x_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_y_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_sum_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_valid_o : out std_logic;
tbt_pos_ce_o : out std_logic;
fofb_pos_x_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_y_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_sum_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_valid_o : out std_logic;
fofb_pos_ce_o : out std_logic;
monit1_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_valid_o : out std_logic;
monit1_pos_ce_o : out std_logic;
monit_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_valid_o : out std_logic;
monit_pos_ce_o : out std_logic
);
end position_calc;
architecture rtl of position_calc is
-------------
--Constants--
-------------
constant c_cic_round_convergent : natural := 1;
constant c_adc_tag_width : natural := 1;
constant c_tbt_tag_width : natural := 1;
constant c_monit1_tag_width : natural := 1;
constant c_monit2_tag_width : natural := 1;
-- full ratio is the accumulated ratio between data and clock.
constant c_adc_ratio_full : natural := g_adc_ratio;
constant c_tbt_ratio_full : natural := g_tbt_ratio*c_adc_ratio_full;
constant c_fofb_ratio_full : natural := g_fofb_ratio*c_adc_ratio_full;
constant c_monit1_ratio_full : natural := g_monit1_ratio*c_fofb_ratio_full;
constant c_monit2_ratio_full : natural := g_monit2_ratio*c_monit1_ratio_full;
-- width for decimation counters
constant c_adc_width : natural := f_log2_size(g_adc_ratio+1);
constant c_cic_tbt_width : natural := f_log2_size(g_tbt_ratio+1);
constant c_cic_fofb_width : natural := f_log2_size(g_fofb_ratio+1);
constant c_cic_monit1_width : natural := f_log2_size(g_monit1_ratio+1);
constant c_cic_monit2_width : natural := f_log2_size(g_monit2_ratio+1);
-- width for ce counters
constant c_adc_ce_width : natural := f_log2_size(c_adc_ratio_full+1);
constant c_tbt_ce_width : natural := f_log2_size(c_tbt_ratio_full+1);
constant c_fofb_ce_width : natural := f_log2_size(c_fofb_ratio_full+1);
constant c_monit1_ce_width : natural := f_log2_size(c_monit1_ratio_full+1);
constant c_monit2_ce_width : natural := f_log2_size(c_monit2_ratio_full+1);
constant c_tbt_cordic_ce_width : natural := f_log2_size(g_tbt_cordic_ratio+1);
constant c_fofb_cordic_ce_width : natural := f_log2_size(g_fofb_cordic_ratio+1);
constant c_monit1_cic_ce_width : natural := f_log2_size(g_monit1_cic_ratio+1);
constant c_monit2_cic_ce_width : natural := f_log2_size(g_monit2_cic_ratio+1);
constant c_fofb_ratio_slv : std_logic_vector(c_cic_fofb_width-1 downto 0)
:= std_logic_vector(to_unsigned(g_fofb_ratio, c_cic_fofb_width));
constant c_tbt_ratio_slv : std_logic_vector(c_cic_tbt_width-1 downto 0)
:= std_logic_vector(to_unsigned(g_tbt_ratio, c_cic_tbt_width));
constant c_monit1_ratio_slv : std_logic_vector(c_cic_monit1_width-1 downto 0)
:= std_logic_vector(to_unsigned(g_monit1_ratio, c_cic_monit1_width));
constant c_monit2_ratio_slv : std_logic_vector(c_cic_monit2_width-1 downto 0)
:= std_logic_vector(to_unsigned(g_monit2_ratio, c_cic_monit2_width));
constant c_adc_ratio_slv : std_logic_vector(c_adc_width-1 downto 0)
:= std_logic_vector(to_unsigned(g_adc_ratio, c_adc_width));
constant c_adc_ratio_slv_full : std_logic_vector(c_adc_ce_width-1 downto 0)
:= std_logic_vector(to_unsigned(c_adc_ratio_full, c_adc_ce_width));
constant c_tbt_ratio_slv_full : std_logic_vector(c_tbt_ce_width-1 downto 0)
:= std_logic_vector(to_unsigned(c_tbt_ratio_full, c_tbt_ce_width));
constant c_fofb_ratio_slv_full : std_logic_vector(c_fofb_ce_width-1 downto 0)
:= std_logic_vector(to_unsigned(c_fofb_ratio_full, c_fofb_ce_width));
constant c_monit1_ratio_slv_full : std_logic_vector(c_monit1_ce_width-1 downto 0)
:= std_logic_vector(to_unsigned(c_monit1_ratio_full, c_monit1_ce_width));
constant c_monit2_ratio_slv_full : std_logic_vector(c_monit2_ce_width-1 downto 0)
:= std_logic_vector(to_unsigned(c_monit2_ratio_full, c_monit2_ce_width));
constant c_tbt_cordic_ratio_slv : std_logic_vector(c_tbt_cordic_ce_width-1 downto 0)
:= std_logic_vector(to_unsigned(g_tbt_cordic_ratio, c_tbt_cordic_ce_width));
constant c_fofb_cordic_ratio_slv : std_logic_vector(c_fofb_cordic_ce_width-1 downto 0)
:= std_logic_vector(to_unsigned(g_fofb_cordic_ratio, c_fofb_cordic_ce_width));
constant c_monit1_cic_ratio_slv : std_logic_vector(c_monit1_cic_ce_width-1 downto 0)
:= std_logic_vector(to_unsigned(g_monit1_cic_ratio, c_monit1_cic_ce_width));
constant c_monit2_cic_ratio_slv : std_logic_vector(c_monit2_cic_ce_width-1 downto 0)
:= std_logic_vector(to_unsigned(g_monit2_cic_ratio, c_monit2_cic_ce_width));
--Cordic
constant c_tbt_cordic_xy_width : natural := g_tbt_decim_width+f_log2_size(g_tbt_cordic_stages+1)+2; -- internal width of cordic: input_width + right padding + left padding
constant c_tbt_cordic_ph_width : natural := g_tbt_decim_width+f_log2_size(g_tbt_cordic_stages+1); -- right padding for cordic stages
constant c_fofb_cordic_xy_width : natural := g_fofb_decim_width+f_log2_size(g_fofb_cordic_stages+1)+2; -- internal width of cordic: input_width + right padding + left padding
constant c_fofb_cordic_ph_width : natural := g_fofb_decim_width+f_log2_size(g_fofb_cordic_stages+1); -- right padding for cordic stages
-----------
--Signals--
-----------
type t_input is array(3 downto 0) of std_logic_vector(g_input_width-1 downto 0);
signal adc_input : t_input := (others => (others => '0'));
type t_input_valid is array(3 downto 0) of std_logic;
signal adc_input_valid : t_input_valid := (others => '0');
signal iq_valid : t_input_valid := (others => '0');
type t_input_tag is array(3 downto 0) of std_logic_vector(c_adc_tag_width-1 downto 0);
signal adc_input_tag : t_input_tag := (others => (others => '0'));
type t_input_tag_en is array(3 downto 0) of std_logic;
signal input_tag_en : t_input_tag_en := (others => '0');
signal full_i_tag : t_input_tag := (others => (others => '0'));
signal full_q_tag : t_input_tag := (others => (others => '0'));
type t_mixed is array(3 downto 0) of std_logic_vector(g_mixed_width-1 downto 0);
signal full_i, full_q : t_mixed := (others => (others => '0'));
-- decimated data
type t_tbt_data is array(3 downto 0) of std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_i, tbt_q, tbt_mag, tbt_phase : t_tbt_data := (others => (others => '0'));
type t_tbt_signed is array (3 downto 0) of signed(g_tbt_decim_width-1 downto 0); -- for cordic output
signal tbt_signed_mag, tbt_signed_phase : t_tbt_signed := (others => (others => '0'));
type t_fofb_data is array(3 downto 0) of std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_i, fofb_q, fofb_mag, fofb_phase : t_fofb_data := (others => (others => '0'));
type t_fofb_signed is array (3 downto 0) of signed(g_fofb_decim_width-1 downto 0); -- for cordic output
signal fofb_signed_mag, fofb_signed_phase : t_fofb_signed := (others => (others => '0'));
type t_monit_data is array(3 downto 0) of std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_mag, monit2_mag : t_monit_data := (others => (others => '0'));
--after deltasigma
signal fofb_x_pre, fofb_y_pre, fofb_q_pre, fofb_sum_pre :
std_logic_vector(g_fofb_decim_width-1 downto 0) := (others => '0');
signal fofb_pos_x_int, fofb_pos_y_int, fofb_pos_q_int, fofb_pos_sum_int :
std_logic_vector(g_fofb_decim_width-1 downto 0) := (others => '0');
signal tbt_x_pre, tbt_y_pre, tbt_q_pre, tbt_sum_pre :
std_logic_vector(g_tbt_decim_width-1 downto 0) := (others => '0');
signal monit1_pos_x_int, monit1_pos_y_int, monit1_pos_q_int, monit1_pos_sum_int :
std_logic_vector(g_monit_decim_width-1 downto 0) := (others => '0');
signal monit_x_pre, monit_y_pre, monit_q_pre, monit_sum_pre :
std_logic_vector(g_monit_decim_width-1 downto 0) := (others => '0');
-- desync
type t_tbt_desync_cnt_array is array (3 downto 0) of std_logic_vector(g_tbt_tag_desync_cnt_width-1 downto 0);
type t_fofb_desync_cnt_array is array (3 downto 0) of std_logic_vector(g_fofb_decim_desync_cnt_width-1 downto 0);
type t_monit1_desync_cnt_array is array (3 downto 0) of std_logic_vector(g_monit1_tag_desync_cnt_width-1 downto 0);
type t_monit2_desync_cnt_array is array (3 downto 0) of std_logic_vector(g_monit2_tag_desync_cnt_width-1 downto 0);
signal tbt_tag_desync_cnt : t_tbt_desync_cnt_array := (others => (others => '0'));
signal fofb_tag_desync_cnt : t_fofb_desync_cnt_array := (others => (others => '0'));
signal monit1_tag_desync_cnt : t_monit1_desync_cnt_array := (others => (others => '0'));
signal monit2_tag_desync_cnt : t_monit2_desync_cnt_array := (others => (others => '0'));
----------------------------
--Clocks and clock enables--
----------------------------
type ce_sl is array(3 downto 0) of std_logic;
signal valid_tbt, valid_tbt_cordic, valid_fofb, valid_fofb_cordic, valid_monit1, valid_monit2 : ce_sl := (others => '0');
signal ce_adc, ce_monit1, ce_monit2, ce_tbt_cordic, ce_fofb_cordic : ce_sl := (others => '0');
signal valid_monit1_pds, valid_fofb_pds, valid_tbt_ds : std_logic;
attribute max_fanout : string;
attribute max_fanout of ce_adc, ce_monit1, ce_monit2 : signal is "50";
begin
adc_input(0) <= adc_ch0_i;
adc_input(1) <= adc_ch1_i;
adc_input(2) <= adc_ch2_i;
adc_input(3) <= adc_ch3_i;
adc_input_valid(0) <= adc_valid_i;
adc_input_valid(1) <= adc_valid_i;
adc_input_valid(2) <= adc_valid_i;
adc_input_valid(3) <= adc_valid_i;
adc_input_tag(0) <= adc_tag_i;
adc_input_tag(1) <= adc_tag_i;
adc_input_tag(2) <= adc_tag_i;
adc_input_tag(3) <= adc_tag_i;
input_tag_en(0) <= adc_tag_en_i;
input_tag_en(1) <= adc_tag_en_i;
input_tag_en(2) <= adc_tag_en_i;
input_tag_en(3) <= adc_tag_en_i;
-- Reset fof TBT rates sync'ed with external signal
gen_ddc : for chan in 3 downto 0 generate
-- Generate clock enable
cmp_ce_adc : strobe_gen
generic map (
g_maxrate => g_adc_ratio,
g_bus_width => c_adc_ce_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => '1',
ratio_i => c_adc_ratio_slv_full,
strobe_o => ce_adc(chan));
cmp_ce_tbt_cordic : strobe_gen
generic map (
g_maxrate => g_tbt_cordic_ratio,
g_bus_width => c_tbt_cordic_ce_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => '1',
ratio_i => c_tbt_cordic_ratio_slv,
strobe_o => ce_tbt_cordic(chan));
cmp_ce_fofb_cordic : strobe_gen
generic map (
g_maxrate => g_fofb_cordic_ratio,
g_bus_width => c_fofb_cordic_ce_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => '1',
ratio_i => c_fofb_cordic_ratio_slv,
strobe_o => ce_fofb_cordic(chan));
cmp_ce_monit1 : strobe_gen
generic map (
g_maxrate => g_monit1_cic_ratio,
g_bus_width => c_monit1_cic_ce_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => '1',
ratio_i => c_monit1_cic_ratio_slv,
strobe_o => ce_monit1(chan));
cmp_ce_monit2 : strobe_gen
generic map (
g_maxrate => g_monit2_cic_ratio,
g_bus_width => c_monit2_cic_ce_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => '1',
ratio_i => c_monit2_cic_ratio_slv,
strobe_o => ce_monit2(chan));
-- Position calculation
gen_with_downconv : if (g_with_downconv) generate
cmp_mixer : mixer
generic map (
g_sin_file => g_sin_file,
g_cos_file => g_cos_file,
g_number_of_points => g_dds_points,
g_input_width => g_input_width,
g_dds_width => g_dds_width,
g_tag_width => c_adc_tag_width,
g_output_width => g_mixed_width)
port map (
rst_i => rst_i,
clk_i => clk_i,
ce_i => ce_adc(chan),
signal_i => adc_input(chan),
valid_i => adc_input_valid(chan),
tag_i => adc_input_tag(chan),
I_out => full_i(chan),
I_tag_out => full_i_tag(chan),
Q_out => full_q(chan),
Q_tag_out => full_q_tag(chan),
valid_o => iq_valid(chan));
cmp_tbt_cic : cic_dual
generic map (
g_input_width => g_mixed_width,
g_output_width => g_tbt_decim_width,
g_stages => g_tbt_cic_stages,
g_delay => g_tbt_cic_delay,
g_max_rate => g_tbt_ratio,
g_bus_width => c_cic_tbt_width,
g_tag_desync_cnt_width => g_tbt_tag_desync_cnt_width,
g_tag_width => c_tbt_tag_width,
g_data_mask_width => g_tbt_cic_mask_samples_width,
g_round_convergent => c_cic_round_convergent)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_adc(chan),
valid_i => iq_valid(chan),
I_i => full_i(chan),
I_tag_i => tbt_tag_i,
I_tag_en_i => tbt_tag_en_i,
I_tag_desync_cnt_rst_i => tbt_tag_desync_cnt_rst_i,
I_tag_desync_cnt_o => tbt_tag_desync_cnt(chan),
I_mask_num_samples_beg_i => tbt_decim_mask_num_samples_beg_i,
I_mask_num_samples_end_i => tbt_decim_mask_num_samples_end_i,
I_mask_en_i => tbt_decim_mask_en_i,
Q_i => full_q(chan),
Q_tag_i => tbt_tag_i,
Q_tag_en_i => tbt_tag_en_i,
Q_mask_num_samples_beg_i => tbt_decim_mask_num_samples_beg_i,
Q_mask_num_samples_end_i => tbt_decim_mask_num_samples_end_i,
Q_mask_en_i => tbt_decim_mask_en_i,
ratio_i => c_tbt_ratio_slv,
I_o => tbt_i(chan),
Q_o => tbt_q(chan),
valid_o => valid_tbt(chan));
cmp_tbt_cordic : cordic_iter_slv
generic map (
g_input_width => g_tbt_decim_width,
g_xy_calc_width => c_tbt_cordic_xy_width,
g_x_output_width => g_tbt_decim_width,
g_phase_calc_width => c_tbt_cordic_ph_width,
g_phase_output_width => g_tbt_decim_width,
g_stages => g_tbt_cordic_stages,
g_iter_per_clk => g_tbt_cordic_iter_per_clk,
g_rounding => true)
port map (
clk_i => clk_i,
ce_data_i => ce_adc(chan),
valid_i => valid_tbt(chan),
ce_i => ce_tbt_cordic(chan),
x_i => tbt_i(chan),
y_i => tbt_q(chan),
mag_o => tbt_mag(chan),
phase_o => tbt_phase(chan),
valid_o => valid_tbt_cordic(chan));
cmp_fofb_cic : cic_dual
generic map (
g_input_width => g_mixed_width,
g_output_width => g_fofb_decim_width,
g_stages => g_fofb_cic_stages,
g_delay => g_fofb_cic_delay,
g_max_rate => g_fofb_ratio,
g_bus_width => c_cic_fofb_width,
g_tag_desync_cnt_width => g_fofb_decim_desync_cnt_width,
g_tag_width => c_adc_tag_width,
g_data_mask_width => g_fofb_cic_mask_samples_width,
g_round_convergent => c_cic_round_convergent)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_adc(chan),
valid_i => iq_valid(chan),
I_i => full_i(chan),
I_tag_i => full_i_tag(chan),
I_tag_en_i => input_tag_en(chan),
I_tag_desync_cnt_rst_i => fofb_decim_desync_cnt_rst_i,
I_tag_desync_cnt_o => fofb_tag_desync_cnt(chan),
I_mask_num_samples_beg_i => fofb_decim_mask_num_samples_i,
I_mask_en_i => fofb_decim_mask_en_i,
Q_i => full_q(chan),
Q_tag_i => full_q_tag(chan),
Q_tag_en_i => input_tag_en(chan),
Q_mask_num_samples_beg_i => fofb_decim_mask_num_samples_i,
Q_mask_en_i => fofb_decim_mask_en_i,
ratio_i => c_fofb_ratio_slv,
I_o => fofb_i(chan),
Q_o => fofb_q(chan),
valid_o => valid_fofb(chan));
cmp_fofb_cordic : cordic_iter_slv
generic map (
g_input_width => g_fofb_decim_width,
g_xy_calc_width => c_fofb_cordic_xy_width,
g_x_output_width => g_fofb_decim_width,
g_phase_calc_width => c_fofb_cordic_ph_width,
g_phase_output_width => g_fofb_decim_width,
g_stages => g_fofb_cordic_stages,
g_iter_per_clk => g_fofb_cordic_iter_per_clk,
g_rounding => true)
port map (
clk_i => clk_i,
ce_data_i => ce_adc(chan),
valid_i => valid_fofb(chan),
ce_i => ce_fofb_cordic(chan),
x_i => fofb_i(chan),
y_i => fofb_q(chan),
mag_o => fofb_mag(chan),
phase_o => fofb_phase(chan),
valid_o => valid_fofb_cordic(chan));
end generate;
gen_without_downconv : if (not g_with_downconv) generate
cmp_tbt_cic : cic_dyn
generic map (
g_input_width => g_input_width,
g_output_width => g_tbt_decim_width,
g_stages => g_tbt_cic_stages,
g_delay => g_tbt_cic_delay,
g_max_rate => g_tbt_ratio,
g_bus_width => c_cic_tbt_width,
g_with_ce_synch => true,
g_tag_desync_cnt_width => g_tbt_tag_desync_cnt_width,
g_tag_width => c_tbt_tag_width,
g_data_mask_width => g_tbt_cic_mask_samples_width,
g_round_convergent => c_cic_round_convergent)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_adc(chan),
-- Synchronize the CE with the already in place
-- rate, so we don't have to
-- change them downstream
ce_out_i => ce_tbt_cordic(chan),
valid_i => adc_input_valid(chan),
data_i => adc_input(chan),
ratio_i => c_tbt_ratio_slv,
data_tag_i => tbt_tag_i,
data_tag_en_i => tbt_tag_en_i,
data_tag_desync_cnt_rst_i => tbt_tag_desync_cnt_rst_i,
data_tag_desync_cnt_o => tbt_tag_desync_cnt(chan),
data_mask_en_i => tbt_decim_mask_en_i,
data_mask_num_samples_beg_i => tbt_decim_mask_num_samples_beg_i,
data_mask_num_samples_end_i => tbt_decim_mask_num_samples_end_i,
-- Reuse signal names so we don't have to
-- change them downstream
data_o => tbt_mag(chan),
valid_o => valid_tbt_cordic(chan));
-- We don't have phase information for chains
-- without downconversion
tbt_phase(chan) <= (others => '0');
cmp_fofb_cic : cic_dyn
generic map (
g_input_width => g_input_width,
g_output_width => g_fofb_decim_width,
g_stages => g_fofb_cic_stages,
g_delay => g_fofb_cic_delay,
g_max_rate => g_fofb_ratio,
g_bus_width => c_cic_fofb_width,
g_with_ce_synch => true,
g_tag_width => c_adc_tag_width,
g_data_mask_width => g_fofb_cic_mask_samples_width,
g_round_convergent => c_cic_round_convergent)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_adc(chan),
ce_out_i => ce_fofb_cordic(chan),
valid_i => adc_input_valid(chan),
data_i => adc_input(chan),
data_tag_i => adc_input_tag(chan),
-- Don't use CIC synchronization feature
data_tag_en_i => '0',
data_mask_num_samples_beg_i => (others => '0'),
data_mask_en_i => '0',
ratio_i => c_fofb_ratio_slv,
-- Reuse signal names so we don't have to
-- change them downstream
data_o => fofb_mag(chan),
valid_o => valid_fofb_cordic(chan));
-- We don't have phase information for chains
-- without downconversion
fofb_phase(chan) <= (others => '0');
end generate;
cmp_monit1_cic : cic_dyn
generic map (
g_input_width => g_fofb_decim_width,
g_output_width => g_monit_decim_width,
g_stages => g_monit1_cic_stages,
g_delay => g_monit1_cic_delay,
g_max_rate => g_monit1_ratio,
g_bus_width => c_cic_monit1_width,
g_with_ce_synch => true,
g_tag_desync_cnt_width => g_monit1_tag_desync_cnt_width,
g_tag_width => c_monit1_tag_width,
g_data_mask_width => g_monit1_cic_mask_samples_width,
g_round_convergent => c_cic_round_convergent)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_fofb_cordic(chan),
ce_out_i => ce_monit1(chan),
valid_i => valid_fofb_cordic(chan),
data_i => fofb_mag(chan),
data_tag_i => monit1_tag_i,
data_tag_en_i => monit1_tag_en_i,
data_tag_desync_cnt_rst_i => monit1_tag_desync_cnt_rst_i,
data_tag_desync_cnt_o => monit1_tag_desync_cnt(chan),
data_mask_num_samples_beg_i => monit1_decim_mask_num_samples_beg_i,
data_mask_num_samples_end_i => monit1_decim_mask_num_samples_end_i,
data_mask_en_i => monit1_decim_mask_en_i,
ratio_i => c_monit1_ratio_slv,
data_o => monit1_mag(chan),
valid_o => valid_monit1(chan));
cmp_monit2_cic : cic_dyn
generic map (
g_input_width => g_monit_decim_width,
g_output_width => g_monit_decim_width,
g_stages => g_monit2_cic_stages,
g_delay => g_monit2_cic_delay,
g_max_rate => g_monit2_ratio,
g_bus_width => c_cic_monit2_width,
g_with_ce_synch => true,
g_tag_desync_cnt_width => g_monit2_tag_desync_cnt_width,
g_tag_width => c_monit2_tag_width,
g_data_mask_width => g_monit2_cic_mask_samples_width,
g_round_convergent => c_cic_round_convergent)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_monit1(chan),
ce_out_i => ce_monit2(chan),
valid_i => valid_monit1(chan),
data_i => monit1_mag(chan),
data_tag_i => monit_tag_i,
data_tag_en_i => monit_tag_en_i,
data_tag_desync_cnt_rst_i => monit_tag_desync_cnt_rst_i,
data_tag_desync_cnt_o => monit2_tag_desync_cnt(chan),
data_mask_num_samples_beg_i => monit_decim_mask_num_samples_beg_i,
data_mask_num_samples_end_i => monit_decim_mask_num_samples_end_i,
data_mask_en_i => monit_decim_mask_en_i,
ratio_i => c_monit2_ratio_slv,
data_o => monit2_mag(chan),
valid_o => valid_monit2(chan));
end generate gen_ddc;
-- x and y are fixed point with:
-- sign bit = MSB
-- word length = g_WIDTH
-- integer length = g_K_WIDTH
-- fractional length = g_WIDTH - g_K_WIDTH
cmp_fofb_pds : part_delta_sigma
generic map (
g_WIDTH => g_FOFB_DECIM_WIDTH,
g_K_WIDTH => g_K_WIDTH,
g_OFFSET_WIDTH => g_OFFSET_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i,
a_i => fofb_mag(0),
b_i => fofb_mag(1),
c_i => fofb_mag(2),
d_i => fofb_mag(3),
kx_i => kx_i,
ky_i => ky_i,
ksum_i => ksum_i,
offset_x_i => offset_x_i,
offset_y_i => offset_y_i,
ce_i => ce_fofb_cordic(0),
valid_i => valid_fofb_cordic(0),
x_o => fofb_pos_x_int,
y_o => fofb_pos_y_int,
q_o => fofb_pos_q_int,
sum_o => fofb_pos_sum_int,
valid_o => valid_fofb_pds
);
-- x and y are fixed point with:
-- sign bit = MSB
-- word length = g_WIDTH
-- integer length = g_K_WIDTH
-- fractional length = g_WIDTH - g_K_WIDTH
cmp_monit1_pds : part_delta_sigma
generic map (
g_WIDTH => g_MONIT_DECIM_WIDTH,
g_K_WIDTH => g_K_WIDTH,
g_OFFSET_WIDTH => g_OFFSET_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i,
a_i => monit1_mag(0),
b_i => monit1_mag(1),
c_i => monit1_mag(2),
d_i => monit1_mag(3),
kx_i => kx_i,
ky_i => ky_i,
ksum_i => ksum_i,
offset_x_i => offset_x_i,
offset_y_i => offset_y_i,
ce_i => ce_monit1(0),
valid_i => valid_monit1(0),
x_o => monit1_pos_x_int,
y_o => monit1_pos_y_int,
q_o => monit1_pos_q_int,
sum_o => monit1_pos_sum_int,
valid_o => valid_monit1_pds
);
-- desync counters. Use only one of the channels as a sample
tbt_tag_desync_cnt_o <= tbt_tag_desync_cnt(0);
fofb_decim_desync_cnt_o <= fofb_tag_desync_cnt(0);
monit1_tag_desync_cnt_o <= monit1_tag_desync_cnt(0);
monit_tag_desync_cnt_o <= monit2_tag_desync_cnt(0);
-- Wiring intermediate signals to outputs
mix_ch0_i_o <= std_logic_vector(resize(signed(full_i(0)), g_IQ_width));
mix_ch0_q_o <= std_logic_vector(resize(signed(full_q(0)), g_IQ_width));
mix_ch1_i_o <= std_logic_vector(resize(signed(full_i(1)), g_IQ_width));
mix_ch1_q_o <= std_logic_vector(resize(signed(full_q(1)), g_IQ_width));
mix_ch2_i_o <= std_logic_vector(resize(signed(full_i(2)), g_IQ_width));
mix_ch2_q_o <= std_logic_vector(resize(signed(full_q(2)), g_IQ_width));
mix_ch3_i_o <= std_logic_vector(resize(signed(full_i(3)), g_IQ_width));
mix_ch3_q_o <= std_logic_vector(resize(signed(full_q(3)), g_IQ_width));
mix_valid_o <= iq_valid(0);
mix_ce_o <= ce_adc(0);
tbt_decim_ch0_i_o <= tbt_i(0);
tbt_decim_ch0_q_o <= tbt_q(0);
tbt_decim_ch1_i_o <= tbt_i(1);
tbt_decim_ch1_q_o <= tbt_q(1);
tbt_decim_ch2_i_o <= tbt_i(2);
tbt_decim_ch2_q_o <= tbt_q(2);
tbt_decim_ch3_i_o <= tbt_i(3);
tbt_decim_ch3_q_o <= tbt_q(3);
tbt_decim_valid_o <= valid_tbt(0);
tbt_decim_ce_o <= ce_adc(0);
tbt_amp_ch0_o <= tbt_mag(0);
tbt_amp_ch1_o <= tbt_mag(1);
tbt_amp_ch2_o <= tbt_mag(2);
tbt_amp_ch3_o <= tbt_mag(3);
tbt_amp_valid_o <= valid_tbt_cordic(0);
tbt_amp_ce_o <= ce_tbt_cordic(0);
tbt_pha_ch0_o <= tbt_phase(0);
tbt_pha_ch1_o <= tbt_phase(1);
tbt_pha_ch2_o <= tbt_phase(2);
tbt_pha_ch3_o <= tbt_phase(3);
tbt_pha_valid_o <= valid_tbt_cordic(0);
tbt_pha_ce_o <= ce_tbt_cordic(0);
fofb_decim_ch0_i_o <= fofb_i(0);
fofb_decim_ch0_q_o <= fofb_q(0);
fofb_decim_ch1_i_o <= fofb_i(1);
fofb_decim_ch1_q_o <= fofb_q(1);
fofb_decim_ch2_i_o <= fofb_i(2);
fofb_decim_ch2_q_o <= fofb_q(2);
fofb_decim_ch3_i_o <= fofb_i(3);
fofb_decim_ch3_q_o <= fofb_q(3);
fofb_decim_valid_o <= valid_fofb(0);
fofb_decim_ce_o <= ce_adc(0);
fofb_amp_ch0_o <= fofb_mag(0);
fofb_amp_ch1_o <= fofb_mag(1);
fofb_amp_ch2_o <= fofb_mag(2);
fofb_amp_ch3_o <= fofb_mag(3);
fofb_amp_valid_o <= valid_fofb_cordic(0);
fofb_amp_ce_o <= ce_fofb_cordic(0);
fofb_pha_ch0_o <= fofb_phase(0);
fofb_pha_ch1_o <= fofb_phase(1);
fofb_pha_ch2_o <= fofb_phase(2);
fofb_pha_ch3_o <= fofb_phase(3);
fofb_pha_valid_o <= valid_fofb_cordic(0);
fofb_pha_ce_o <= ce_fofb_cordic(0);
monit1_amp_ch0_o <= monit1_mag(0);
monit1_amp_ch1_o <= monit1_mag(1);
monit1_amp_ch2_o <= monit1_mag(2);
monit1_amp_ch3_o <= monit1_mag(3);
monit1_amp_valid_o <= valid_monit1(0);
monit1_amp_ce_o <= ce_monit1(0);
monit_amp_ch0_o <= monit2_mag(0);
monit_amp_ch1_o <= monit2_mag(1);
monit_amp_ch2_o <= monit2_mag(2);
monit_amp_ch3_o <= monit2_mag(3);
monit_amp_valid_o <= valid_monit2(0);
monit_amp_ce_o <= ce_monit2(0);
fofb_pos_valid_o <= valid_fofb_pds;
fofb_pos_ce_o <= ce_fofb_cordic(0);
fofb_pos_x_o <= std_logic_vector(shift_right(signed(fofb_pos_x_int), g_fofb_decim_width-g_k_width));
fofb_pos_y_o <= std_logic_vector(shift_right(signed(fofb_pos_y_int), g_fofb_decim_width-g_k_width));
fofb_pos_q_o <= std_logic_vector(shift_right(signed(fofb_pos_q_int), g_fofb_decim_width-g_k_width));
fofb_pos_sum_o <= fofb_pos_sum_int;
-- Removed to speed synthesis during test
tbt_pos_valid_o <= '0';
tbt_pos_ce_o <= '0';
tbt_pos_x_o <= (others => '0');
tbt_pos_y_o <= (others => '0');
tbt_pos_q_o <= (others => '0');
tbt_pos_sum_o <= (others => '0');
monit1_pos_valid_o <= valid_monit1_pds;
monit1_pos_ce_o <= ce_monit1(0);
monit1_pos_x_o <= std_logic_vector(shift_right(signed(monit1_pos_x_int), g_monit_decim_width-g_k_width));
monit1_pos_y_o <= std_logic_vector(shift_right(signed(monit1_pos_y_int), g_monit_decim_width-g_k_width));
monit1_pos_q_o <= std_logic_vector(shift_right(signed(monit1_pos_q_int), g_monit_decim_width-g_k_width));
monit1_pos_sum_o <= monit1_pos_sum_int;
monit_pos_valid_o <= '0';
monit_pos_ce_o <= '0';
monit_pos_x_o <= (others => '0');
monit_pos_y_o <= (others => '0');
monit_pos_q_o <= (others => '0');
monit_pos_sum_o <= (others => '0');
end rtl;
|
lgpl-3.0
|
686d4f83ae2b684f687fcf0e9a812495
| 0.53626 | 3.014479 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/synthesizer/interfaceLevel/UnitWithGenericOfChild.vhd
| 1 | 1,415 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY UnitWithGenericOnPort IS
GENERIC(
NESTED_PARAM : INTEGER := 123
);
PORT(
a : IN STD_LOGIC_VECTOR(122 DOWNTO 0);
b : OUT STD_LOGIC_VECTOR(122 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF UnitWithGenericOnPort IS
SIGNAL tmp : STD_LOGIC_VECTOR(122 DOWNTO 0);
BEGIN
b <= tmp;
tmp <= a;
ASSERT NESTED_PARAM = 123 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY UnitWithGenericOfChild IS
PORT(
a : IN STD_LOGIC_VECTOR(122 DOWNTO 0);
b : OUT STD_LOGIC_VECTOR(122 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF UnitWithGenericOfChild IS
COMPONENT UnitWithGenericOnPort IS
GENERIC(
NESTED_PARAM : INTEGER := 123
);
PORT(
a : IN STD_LOGIC_VECTOR(122 DOWNTO 0);
b : OUT STD_LOGIC_VECTOR(122 DOWNTO 0)
);
END COMPONENT;
SIGNAL sig_ch_a : STD_LOGIC_VECTOR(122 DOWNTO 0);
SIGNAL sig_ch_b : STD_LOGIC_VECTOR(122 DOWNTO 0);
SIGNAL tmp : STD_LOGIC_VECTOR(122 DOWNTO 0);
BEGIN
ch_inst: UnitWithGenericOnPort GENERIC MAP(
NESTED_PARAM => 123
) PORT MAP(
a => sig_ch_a,
b => sig_ch_b
);
b <= tmp;
sig_ch_a <= a;
tmp <= b;
END ARCHITECTURE;
|
mit
|
b3a7914be6f6bd4ca9fcfa3933d31d50
| 0.621908 | 3.511166 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_orbit_intlk/orbit_intlk_pkg.vhd
| 1 | 25,386 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
package orbit_intlk_pkg is
-------------------------------------------------------------------------------
-- Types
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant c_CHAN_X_IDX : natural := 0;
constant c_CHAN_Y_IDX : natural := 1;
constant c_CHAN_Q_IDX : natural := 2;
constant c_CHAN_SUM_IDX : natural := 3;
constant c_CHAN_A_IDX : natural := 0;
constant c_CHAN_B_IDX : natural := 1;
constant c_CHAN_C_IDX : natural := 2;
constant c_CHAN_D_IDX : natural := 3;
constant c_NUM_CHANNELS : natural := 4;
constant c_BPM_DS_IDX : natural := 0;
constant c_BPM_US_IDX : natural := 1;
constant c_NUM_BPMS : natural := 2;
-- generate interlock logic up to which channel?
constant c_INTLK_GEN_UPTO_CHANNEL : natural := c_CHAN_Y_IDX;
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component orbit_intlk
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Interlock enable and limits signals
-----------------------------
intlk_en_i : in std_logic;
intlk_clr_i : in std_logic;
-- Minimum threshold interlock on/off
intlk_min_sum_en_i : in std_logic;
-- Minimum threshold to interlock
intlk_min_sum_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-- Translation interlock on/off
intlk_trans_en_i : in std_logic;
-- Translation interlock clear
intlk_trans_clr_i : in std_logic;
intlk_trans_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-- Angular interlock on/off
intlk_ang_en_i : in std_logic;
-- Angular interlock clear
intlk_ang_clr_i : in std_logic;
intlk_ang_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_trans_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_trans_o : out std_logic;
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ang_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_ang_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_o : out std_logic
);
end component;
component orbit_intlk_trans is
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Interlock enable and limits signals
-----------------------------
-- Translation interlock on/off
intlk_trans_en_i : in std_logic;
-- Translation interlock clear
intlk_trans_clr_i : in std_logic;
intlk_trans_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-----------------------------
-- Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic
);
end component;
component orbit_intlk_ang is
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Interlock enable and limits signals
-----------------------------
-- Angular interlock on/off
intlk_ang_en_i : in std_logic;
-- Angular interlock clear
intlk_ang_clr_i : in std_logic;
intlk_ang_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-----------------------------
-- Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic
);
end component;
component orbit_intlk_cdc_fifo
generic
(
g_data_width : natural;
g_size : natural
);
port
(
clk_wr_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
valid_i : in std_logic;
clk_rd_i : in std_logic;
rd_i : in std_logic;
data_o : out std_logic_vector(g_data_width-1 downto 0);
valid_o : out std_logic;
empty_o : out std_logic
);
end component;
component orbit_intlk_cdc
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Synched Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_o : out std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_o : out std_logic := '0';
decim_ds_pos_x_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_o : out std_logic;
-----------------------------
-- Synched Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_o : out std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_o : out std_logic := '0';
decim_us_pos_x_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_o : out std_logic
);
end component;
constant c_xwb_orbit_intlk_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"87efeda8",
version => x"00000001",
date => x"20200612",
name => "LNLS_INTLK_REGS ")));
end orbit_intlk_pkg;
package body orbit_intlk_pkg is
end orbit_intlk_pkg;
|
lgpl-3.0
|
9dc52902a9971e52a45e265b6c7bd5f3
| 0.441976 | 3.81687 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASlice2.vhd
| 1 | 965 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Vector parts driven from multi branch statement
--
ENTITY AssignToASlice2 IS
PORT(
clk : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
rst_n : IN STD_LOGIC;
swap : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASlice2 IS
SIGNAL data_out_0 : STD_LOGIC;
SIGNAL data_out_1 : STD_LOGIC;
SIGNAL data_out_2 : STD_LOGIC;
BEGIN
data_out <= data_out_2 & data_out_1 & data_out_0;
assig_process_data_out_0: PROCESS(data_in, swap)
BEGIN
IF swap = '1' THEN
data_out_0 <= data_in(1);
data_out_1 <= data_in(0);
data_out_2 <= data_in(0);
ELSE
data_out_0 <= data_in(0);
data_out_1 <= data_in(1);
data_out_2 <= data_in(1);
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
4087007ece10306a232ff5883b44f3d3
| 0.565803 | 3.195364 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASliceOfReg1b.vhd
| 1 | 1,897 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Register where slices of next signal are set conditionally in multiple branches, nested
--
ENTITY AssignToASliceOfReg1b IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg1b IS
SIGNAL r : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL r_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"0000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_15downto8 & r_next_7downto0;
assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, data_in_vld, r)
BEGIN
IF data_in_vld = '1' THEN
IF data_in_addr = "0" THEN
r_next_7downto0 <= data_in_data(7 DOWNTO 0);
r_next_15downto8 <= data_in_data(15 DOWNTO 8);
ELSIF data_in_addr = "1" THEN
r_next_7downto0 <= data_in_data(15 DOWNTO 8);
r_next_15downto8 <= data_in_data(7 DOWNTO 0);
ELSE
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_7downto0 <= r(7 DOWNTO 0);
END IF;
ELSE
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_7downto0 <= r(7 DOWNTO 0);
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
9042ab8b7d0467f548bdf171133ef4b2
| 0.558777 | 3.32807 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module.vhd
| 2 | 9,927 |
-- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module is
port (
data_out : out std_logic_vector(23 downto 0); -- data_out.wire
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
thr : in std_logic_vector(7 downto 0) := (others => '0') -- thr.wire
);
end entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module;
architecture rtl of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_multiplexer_GNCALBUTDR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNCALBUTDR;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNA5S4SQDN is
port (
input : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_port_GNA5S4SQDN;
component alt_dspbuilder_if_statement_GNYT6HZJI5 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(7 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNYT6HZJI5;
component alt_dspbuilder_constant_GNLMV7GZFA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNLMV7GZFA;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_cast_GNKXX25S2S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKXX25S2S;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> Bus_Conversion:input
signal bus_conversion_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion:output -> If_Statement:a
signal thr_0_output_wire : std_logic_vector(7 downto 0); -- thr_0:output -> If_Statement:b
signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Multiplexer1:in0
signal constant2_output_wire : std_logic_vector(23 downto 0); -- Constant2:output -> Multiplexer1:in1
signal multiplexer1_result_wire : std_logic_vector(23 downto 0); -- Multiplexer1:result -> data_out_0:input
signal if_statement_true_wire : std_logic; -- If_Statement:true -> cast0:input
signal cast0_output_wire : std_logic_vector(0 downto 0); -- cast0:output -> Multiplexer1:sel
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> Multiplexer1:aclr
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> Multiplexer1:clock
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => cast0_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => constant1_output_wire, -- in0.wire
in1 => constant2_output_wire -- in1.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
thr_0 : component alt_dspbuilder_port_GNA5S4SQDN
port map (
input => thr, -- input.wire
output => thr_0_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNYT6HZJI5
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a>b",
number_inputs => 2,
width => 8
)
port map (
true => if_statement_true_wire, -- true.wire
a => bus_conversion_output_wire, -- a.wire
b => thr_0_output_wire -- b.wire
);
constant2 : component alt_dspbuilder_constant_GNLMV7GZFA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "111111111111111111111111",
width => 24
)
port map (
output => constant2_output_wire -- output.wire
);
constant1 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant1_output_wire -- output.wire
);
bus_conversion : component alt_dspbuilder_cast_GNKXX25S2S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => multiplexer1_result_wire, -- input.wire
output => data_out -- output.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
cast0 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => if_statement_true_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
end architecture rtl; -- of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module
|
mit
|
c1248e78eef3231e6919317bd44200a4
| 0.579128 | 3.341299 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/afc_v3/dbe_bpm2_with_dcc_rtm/dbe_bpm2_with_dcc_rtm.vhd
| 1 | 38,137 |
------------------------------------------------------------------------------
-- Title : Top FMC250M design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC250M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-19 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- IP cores constants
use work.ipcores_pkg.all;
-- AFC definitions
use work.afc_base_pkg.all;
entity dbe_bpm2_with_dcc_rtm is
generic (
-- Number of RTM SFP GTs
g_NUM_SFPS : integer := 4;
-- Start index of the RTM SFP GTs
g_SFP_START_ID : integer := 4;
-- Number of P2P GTs
g_NUM_P2P_GTS : integer := 8;
-- Start index of the P2P GTs
g_P2P_GT_START_ID : integer := 0
);
port(
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;
afc_fp2_clk1_p_i : in std_logic;
afc_fp2_clk1_n_i : in std_logic;
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0);
trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0);
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i : in std_logic := '0';
diag_spi_si_i : in std_logic := '0';
diag_spi_so_o : out std_logic;
diag_spi_clk_i : in std_logic := '0';
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o : out std_logic;
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b : inout std_logic;
afc_si57x_sda_b : inout std_logic;
-- Si57x oscillator output enable
afc_si57x_oe_o : out std_logic;
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b : inout std_logic;
board_i2c_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o : out std_logic;
-- spi_cs_n_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic := '0';
---------------------------------------------------------------------------
-- P2P GT pins
---------------------------------------------------------------------------
-- P2P
p2p_gt_rx_p_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '0');
p2p_gt_rx_n_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '1');
p2p_gt_tx_p_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
p2p_gt_tx_n_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
-----------------------------
-- FMC1_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc1_adc_clk_div_rst_p_o : out std_logic;
fmc1_adc_clk_div_rst_n_o : out std_logic;
fmc1_adc_ext_rst_n_o : out std_logic;
fmc1_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc1_adc_clk0_p_i : in std_logic := '0';
fmc1_adc_clk0_n_i : in std_logic := '0';
fmc1_adc_clk1_p_i : in std_logic := '0';
fmc1_adc_clk1_n_i : in std_logic := '0';
fmc1_adc_clk2_p_i : in std_logic := '0';
fmc1_adc_clk2_n_i : in std_logic := '0';
fmc1_adc_clk3_p_i : in std_logic := '0';
fmc1_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc1_adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc1_prsnt_i : in std_logic;
--fmc1_pg_m2c_i : in std_logic;
--fmc1_clk_dir_i : in std_logic;
-- Trigger
fmc1_trig_dir_o : out std_logic;
fmc1_trig_term_o : out std_logic;
fmc1_trig_val_p_b : inout std_logic;
fmc1_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc1_adc_spi_clk_o : out std_logic;
fmc1_adc_spi_mosi_o : out std_logic;
fmc1_adc_spi_miso_i : in std_logic;
fmc1_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc1_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc1_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc1_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc1_si571_scl_pad_b : inout std_logic;
fmc1_si571_sda_pad_b : inout std_logic;
fmc1_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc1_spi_ad9510_cs_o : out std_logic;
fmc1_spi_ad9510_sclk_o : out std_logic;
fmc1_spi_ad9510_mosi_o : out std_logic;
fmc1_spi_ad9510_miso_i : in std_logic;
fmc1_pll_function_o : out std_logic;
fmc1_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc1_fpga_clk_p_i : in std_logic;
fmc1_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc1_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc1_amc7823_spi_cs_o : out std_logic;
fmc1_amc7823_spi_sclk_o : out std_logic;
fmc1_amc7823_spi_mosi_o : out std_logic;
fmc1_amc7823_spi_miso_i : in std_logic;
fmc1_amc7823_davn_i : in std_logic;
-- FMC LEDs
fmc1_led1_o : out std_logic;
fmc1_led2_o : out std_logic;
fmc1_led3_o : out std_logic;
-----------------------------
-- FMC2_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc2_adc_clk_div_rst_p_o : out std_logic;
fmc2_adc_clk_div_rst_n_o : out std_logic;
fmc2_adc_ext_rst_n_o : out std_logic;
fmc2_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc2_adc_clk0_p_i : in std_logic := '0';
fmc2_adc_clk0_n_i : in std_logic := '0';
fmc2_adc_clk1_p_i : in std_logic := '0';
fmc2_adc_clk1_n_i : in std_logic := '0';
fmc2_adc_clk2_p_i : in std_logic := '0';
fmc2_adc_clk2_n_i : in std_logic := '0';
fmc2_adc_clk3_p_i : in std_logic := '0';
fmc2_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc2_adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc2_prsnt_i : in std_logic;
--fmc2_pg_m2c_i : in std_logic;
--fmc2_clk_dir_i : in std_logic;
-- Trigger
fmc2_trig_dir_o : out std_logic;
fmc2_trig_term_o : out std_logic;
fmc2_trig_val_p_b : inout std_logic;
fmc2_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc2_adc_spi_clk_o : out std_logic;
fmc2_adc_spi_mosi_o : out std_logic;
fmc2_adc_spi_miso_i : in std_logic;
fmc2_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc2_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc2_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc2_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc2_si571_scl_pad_b : inout std_logic;
fmc2_si571_sda_pad_b : inout std_logic;
fmc2_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc2_spi_ad9510_cs_o : out std_logic;
fmc2_spi_ad9510_sclk_o : out std_logic;
fmc2_spi_ad9510_mosi_o : out std_logic;
fmc2_spi_ad9510_miso_i : in std_logic;
fmc2_pll_function_o : out std_logic;
fmc2_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc2_fpga_clk_p_i : in std_logic;
fmc2_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc2_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc2_amc7823_spi_cs_o : out std_logic;
fmc2_amc7823_spi_sclk_o : out std_logic;
fmc2_amc7823_spi_mosi_o : out std_logic;
fmc2_amc7823_spi_miso_i : in std_logic;
fmc2_amc7823_davn_i : in std_logic;
-- FMC LEDs
fmc2_led1_o : out std_logic;
fmc2_led2_o : out std_logic;
fmc2_led3_o : out std_logic;
---------------------------------------------------------------------------
-- RTM board pins
---------------------------------------------------------------------------
-- SFP
rtm_sfp_rx_p_i : in std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID) := (others => '0');
rtm_sfp_rx_n_i : in std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID) := (others => '1');
rtm_sfp_tx_p_o : out std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID);
rtm_sfp_tx_n_o : out std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID);
-- RTM I2C.
-- SFP configuration pins, behind a I2C MAX7356. I2C addr = 1110_100 & '0' = 0xE8
-- Si570 oscillator. Input 0 of CDCLVD1212. I2C addr = 1010101 & '0' = 0x55
rtm_scl_b : inout std_logic;
rtm_sda_b : inout std_logic;
-- Si570 oscillator output enable
rtm_si570_oe_o : out std_logic;
---- Clock to RTM connector. Input 1 of CDCLVD1212. Not connected directly to
-- AFC
--rtm_rtm_sync_clk_p_o : out std_logic;
--rtm_rtm_sync_clk_n_o : out std_logic;
-- Select between input 0 or 1 or CDCLVD1212. 0 is Si570, 1 is RTM sync clock
rtm_clk_in_sel_o : out std_logic;
-- FPGA clocks from CDCLVD1212
rtm_fpga_clk1_p_i : in std_logic := '0';
rtm_fpga_clk1_n_i : in std_logic := '0';
rtm_fpga_clk2_p_i : in std_logic := '0';
rtm_fpga_clk2_n_i : in std_logic := '0';
-- SFP status bits. Behind 4 74HC165, 8-parallel-in/serial-out. 4 x 8 bits.
-- The PISO chips are organized like this:
--
-- Parallel load
rtm_sfp_status_reg_pl_o : out std_logic;
-- Clock N
rtm_sfp_status_reg_clk_n_o : out std_logic;
-- Serial output
rtm_sfp_status_reg_out_i : in std_logic := '0';
-- SFP control bits. Behind 4 74HC4094D, serial-in/8-parallel-out. 5 x 8 bits.
-- The SIPO chips are organized like this:
--
-- Strobe
rtm_sfp_ctl_str_n_o : out std_logic;
-- Data input
rtm_sfp_ctl_din_n_o : out std_logic;
-- Parallel output enable
rtm_sfp_ctl_oe_n_o : out std_logic;
-- External clock from RTM to FPGA
rtm_ext_clk_p_i : in std_logic := '0';
rtm_ext_clk_n_i : in std_logic := '0'
);
end dbe_bpm2_with_dcc_rtm;
architecture rtl of dbe_bpm2_with_dcc_rtm is
begin
cmp_dbe_bpm_gen : entity work.dbe_bpm_gen
generic map (
g_fmc_adc_type => "FMC250M",
g_WITH_RTM_SFP => true,
g_NUM_SFPS => g_NUM_SFPS,
g_SFP_START_ID => g_SFP_START_ID,
g_WITH_RTM_SFP_FOFB_DCC => true,
g_NUM_P2P_GTS => g_NUM_P2P_GTS,
g_P2P_GT_START_ID => g_P2P_GT_START_ID,
g_WITH_P2P_FOFB_DCC => true
)
port map (
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
aux_clk_p_i => aux_clk_p_i,
aux_clk_n_i => aux_clk_n_i,
afc_fp2_clk1_p_i => afc_fp2_clk1_p_i,
afc_fp2_clk1_n_i => afc_fp2_clk1_n_i,
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i => sys_rst_button_n_i,
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o => trig_dir_o,
trig_b => trig_b,
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i => diag_spi_cs_i,
diag_spi_si_i => diag_spi_si_i,
diag_spi_so_o => diag_spi_so_o,
diag_spi_clk_i => diag_spi_clk_i,
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o => adn4604_vadj2_clk_updt_n_o,
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b => afc_si57x_scl_b,
afc_si57x_sda_b => afc_si57x_sda_b,
-- Si57x oscillator output enable
afc_si57x_oe_o => afc_si57x_oe_o,
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- PCI clock and reset signals
pcie_clk_p_i => pcie_clk_p_i,
pcie_clk_n_i => pcie_clk_n_i,
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o => leds_o,
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b => board_i2c_scl_b,
board_i2c_sda_b => board_i2c_sda_b,
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o => spi_sclk_o,
-- spi_cs_n_o => spi_cs_n_o,
-- spi_mosi_o => spi_mosi_o,
-- spi_miso_i => spi_miso_i,
---------------------------------------------------------------------------
-- P2P GT pins
---------------------------------------------------------------------------
-- P2P
p2p_gt_rx_p_i => p2p_gt_rx_p_i,
p2p_gt_rx_n_i => p2p_gt_rx_n_i,
p2p_gt_tx_p_o => p2p_gt_tx_p_o,
p2p_gt_tx_n_o => p2p_gt_tx_n_o,
-----------------------------
-- FMC1_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_1_adc_clk_div_rst_p_o => fmc1_adc_clk_div_rst_p_o,
fmc250_1_adc_clk_div_rst_n_o => fmc1_adc_clk_div_rst_n_o,
fmc250_1_adc_ext_rst_n_o => fmc1_adc_ext_rst_n_o,
fmc250_1_adc_sleep_o => fmc1_adc_sleep_o,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_1_adc_clk0_p_i => fmc1_adc_clk0_p_i,
fmc250_1_adc_clk0_n_i => fmc1_adc_clk0_n_i,
fmc250_1_adc_clk1_p_i => fmc1_adc_clk1_p_i,
fmc250_1_adc_clk1_n_i => fmc1_adc_clk1_n_i,
fmc250_1_adc_clk2_p_i => fmc1_adc_clk2_p_i,
fmc250_1_adc_clk2_n_i => fmc1_adc_clk2_n_i,
fmc250_1_adc_clk3_p_i => fmc1_adc_clk3_p_i,
fmc250_1_adc_clk3_n_i => fmc1_adc_clk3_n_i,
-- DDR ADC data channels.
fmc250_1_adc_data_ch0_p_i => fmc1_adc_data_ch0_p_i,
fmc250_1_adc_data_ch0_n_i => fmc1_adc_data_ch0_n_i,
fmc250_1_adc_data_ch1_p_i => fmc1_adc_data_ch1_p_i,
fmc250_1_adc_data_ch1_n_i => fmc1_adc_data_ch1_n_i,
fmc250_1_adc_data_ch2_p_i => fmc1_adc_data_ch2_p_i,
fmc250_1_adc_data_ch2_n_i => fmc1_adc_data_ch2_n_i,
fmc250_1_adc_data_ch3_p_i => fmc1_adc_data_ch3_p_i,
fmc250_1_adc_data_ch3_n_i => fmc1_adc_data_ch3_n_i,
---- FMC General Status
--fmc250_1_prsnt_i : in std_logic := '0';
--fmc250_1_pg_m2c_i : in std_logic := '0';
--fmc250_1_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_1_trig_dir_o => fmc1_trig_dir_o,
fmc250_1_trig_term_o => fmc1_trig_term_o,
fmc250_1_trig_val_p_b => fmc1_trig_val_p_b,
fmc250_1_trig_val_n_b => fmc1_trig_val_n_b,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_1_adc_spi_clk_o => fmc1_adc_spi_clk_o,
fmc250_1_adc_spi_mosi_o => fmc1_adc_spi_mosi_o,
fmc250_1_adc_spi_miso_i => fmc1_adc_spi_miso_i,
fmc250_1_adc_spi_cs_adc0_n_o => fmc1_adc_spi_cs_adc0_n_o,
fmc250_1_adc_spi_cs_adc1_n_o => fmc1_adc_spi_cs_adc1_n_o,
fmc250_1_adc_spi_cs_adc2_n_o => fmc1_adc_spi_cs_adc2_n_o,
fmc250_1_adc_spi_cs_adc3_n_o => fmc1_adc_spi_cs_adc3_n_o,
-- Si571 clock gen
fmc250_1_si571_scl_pad_b => fmc1_si571_scl_pad_b,
fmc250_1_si571_sda_pad_b => fmc1_si571_sda_pad_b,
fmc250_1_si571_oe_o => fmc1_si571_oe_o,
-- AD9510 clock distribution PLL
fmc250_1_spi_ad9510_cs_o => fmc1_spi_ad9510_cs_o,
fmc250_1_spi_ad9510_sclk_o => fmc1_spi_ad9510_sclk_o,
fmc250_1_spi_ad9510_mosi_o => fmc1_spi_ad9510_mosi_o,
fmc250_1_spi_ad9510_miso_i => fmc1_spi_ad9510_miso_i,
fmc250_1_pll_function_o => fmc1_pll_function_o,
fmc250_1_pll_status_i => fmc1_pll_status_i,
-- AD9510 clock copy
fmc250_1_fpga_clk_p_i => fmc1_fpga_clk_p_i,
fmc250_1_fpga_clk_n_i => fmc1_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc250_1_clk_sel_o => fmc1_clk_sel_o,
-- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_1_amc7823_spi_cs_o => fmc1_amc7823_spi_cs_o,
fmc250_1_amc7823_spi_sclk_o => fmc1_amc7823_spi_sclk_o,
fmc250_1_amc7823_spi_mosi_o => fmc1_amc7823_spi_mosi_o,
fmc250_1_amc7823_spi_miso_i => fmc1_amc7823_spi_miso_i,
fmc250_1_amc7823_davn_i => fmc1_amc7823_davn_i,
-- FMC LEDs
fmc250_1_led1_o => fmc1_led1_o,
fmc250_1_led2_o => fmc1_led2_o,
fmc250_1_led3_o => fmc1_led3_o,
-----------------------------
-- FMC2_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_2_adc_clk_div_rst_p_o => fmc2_adc_clk_div_rst_p_o,
fmc250_2_adc_clk_div_rst_n_o => fmc2_adc_clk_div_rst_n_o,
fmc250_2_adc_ext_rst_n_o => fmc2_adc_ext_rst_n_o,
fmc250_2_adc_sleep_o => fmc2_adc_sleep_o,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_2_adc_clk0_p_i => fmc2_adc_clk0_p_i,
fmc250_2_adc_clk0_n_i => fmc2_adc_clk0_n_i,
fmc250_2_adc_clk1_p_i => fmc2_adc_clk1_p_i,
fmc250_2_adc_clk1_n_i => fmc2_adc_clk1_n_i,
fmc250_2_adc_clk2_p_i => fmc2_adc_clk2_p_i,
fmc250_2_adc_clk2_n_i => fmc2_adc_clk2_n_i,
fmc250_2_adc_clk3_p_i => fmc2_adc_clk3_p_i,
fmc250_2_adc_clk3_n_i => fmc2_adc_clk3_n_i,
-- DDR ADC data channels.
fmc250_2_adc_data_ch0_p_i => fmc2_adc_data_ch0_p_i,
fmc250_2_adc_data_ch0_n_i => fmc2_adc_data_ch0_n_i,
fmc250_2_adc_data_ch1_p_i => fmc2_adc_data_ch1_p_i,
fmc250_2_adc_data_ch1_n_i => fmc2_adc_data_ch1_n_i,
fmc250_2_adc_data_ch2_p_i => fmc2_adc_data_ch2_p_i,
fmc250_2_adc_data_ch2_n_i => fmc2_adc_data_ch2_n_i,
fmc250_2_adc_data_ch3_p_i => fmc2_adc_data_ch3_p_i,
fmc250_2_adc_data_ch3_n_i => fmc2_adc_data_ch3_n_i,
---- FMC General Status
--fmc250_2_prsnt_i : in std_logic := '0';
--fmc250_2_pg_m2c_i : in std_logic := '0';
--fmc250_2_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_2_trig_dir_o => fmc2_trig_dir_o,
fmc250_2_trig_term_o => fmc2_trig_term_o,
fmc250_2_trig_val_p_b => fmc2_trig_val_p_b,
fmc250_2_trig_val_n_b => fmc2_trig_val_n_b,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_2_adc_spi_clk_o => fmc2_adc_spi_clk_o,
fmc250_2_adc_spi_mosi_o => fmc2_adc_spi_mosi_o,
fmc250_2_adc_spi_miso_i => fmc2_adc_spi_miso_i,
fmc250_2_adc_spi_cs_adc0_n_o => fmc2_adc_spi_cs_adc0_n_o,
fmc250_2_adc_spi_cs_adc1_n_o => fmc2_adc_spi_cs_adc1_n_o,
fmc250_2_adc_spi_cs_adc2_n_o => fmc2_adc_spi_cs_adc2_n_o,
fmc250_2_adc_spi_cs_adc3_n_o => fmc2_adc_spi_cs_adc3_n_o,
-- Si571 clock gen
fmc250_2_si571_scl_pad_b => fmc2_si571_scl_pad_b,
fmc250_2_si571_sda_pad_b => fmc2_si571_sda_pad_b,
fmc250_2_si571_oe_o => fmc2_si571_oe_o,
-- AD9510 clock distribution PLL
fmc250_2_spi_ad9510_cs_o => fmc2_spi_ad9510_cs_o,
fmc250_2_spi_ad9510_sclk_o => fmc2_spi_ad9510_sclk_o,
fmc250_2_spi_ad9510_mosi_o => fmc2_spi_ad9510_mosi_o,
fmc250_2_spi_ad9510_miso_i => fmc2_spi_ad9510_miso_i,
fmc250_2_pll_function_o => fmc2_pll_function_o,
fmc250_2_pll_status_i => fmc2_pll_status_i,
-- AD9510 clock copy
fmc250_2_fpga_clk_p_i => fmc2_fpga_clk_p_i,
fmc250_2_fpga_clk_n_i => fmc2_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc250_2_clk_sel_o => fmc2_clk_sel_o,
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_2_amc7823_spi_cs_o => fmc2_amc7823_spi_cs_o,
fmc250_2_amc7823_spi_sclk_o => fmc2_amc7823_spi_sclk_o,
fmc250_2_amc7823_spi_mosi_o => fmc2_amc7823_spi_mosi_o,
fmc250_2_amc7823_spi_miso_i => fmc2_amc7823_spi_miso_i,
fmc250_2_amc7823_davn_i => fmc2_amc7823_davn_i,
-- FMC LEDs
fmc250_2_led1_o => fmc2_led1_o,
fmc250_2_led2_o => fmc2_led2_o,
fmc250_2_led3_o => fmc2_led3_o,
---------------------------------------------------------------------------
-- RTM board pins
---------------------------------------------------------------------------
-- SFP
rtm_sfp_rx_p_i => rtm_sfp_rx_p_i,
rtm_sfp_rx_n_i => rtm_sfp_rx_n_i,
rtm_sfp_tx_p_o => rtm_sfp_tx_p_o,
rtm_sfp_tx_n_o => rtm_sfp_tx_n_o,
-- RTM I2C.
-- SFP configuration pins, behind a I2C MAX7356. I2C addr = 1110_100 & '0' = 0xE8
-- Si570 oscillator. Input 0 of CDCLVD1212. I2C addr = 1010101 & '0' = 0x55
rtm_scl_b => rtm_scl_b,
rtm_sda_b => rtm_sda_b,
-- Si570 oscillator output enable
rtm_si570_oe_o => rtm_si570_oe_o,
---- Clock to RTM connector. Input 1 of CDCLVD1212. Not connected to FPGA
-- rtm_sync_clk_p_o => rtm_sync_clk_p_o,
-- rtm_sync_clk_n_o => rtm_sync_clk_n_o,
-- Select between input 0 or 1 or CDCLVD1212. 0 is Si570, 1 is RTM sync clock
rtm_clk_in_sel_o => rtm_clk_in_sel_o,
-- FPGA clocks from CDCLVD1212
rtm_fpga_clk1_p_i => rtm_fpga_clk1_p_i,
rtm_fpga_clk1_n_i => rtm_fpga_clk1_n_i,
rtm_fpga_clk2_p_i => rtm_fpga_clk2_p_i,
rtm_fpga_clk2_n_i => rtm_fpga_clk2_n_i,
-- SFP status bits. Behind 4 74HC165, 8-parallel-in/serial-out. 4 x 8 bits.
--
-- Parallel load
rtm_sfp_status_reg_pl_o => rtm_sfp_status_reg_pl_o,
-- Clock N
rtm_sfp_status_reg_clk_n_o => rtm_sfp_status_reg_clk_n_o,
-- Serial output
rtm_sfp_status_reg_out_i => rtm_sfp_status_reg_out_i,
-- SFP control bits. Behind 4 74HC4094D, serial-in/8-parallel-out. 5 x 8 bits.
--
-- Strobe
rtm_sfp_ctl_str_n_o => rtm_sfp_ctl_str_n_o,
-- Data input
rtm_sfp_ctl_din_n_o => rtm_sfp_ctl_din_n_o,
-- Parallel output enable
rtm_sfp_ctl_oe_n_o => rtm_sfp_ctl_oe_n_o,
-- External clock from RTM to FPGA
rtm_ext_clk_p_i => rtm_ext_clk_p_i,
rtm_ext_clk_n_i => rtm_ext_clk_n_i
);
end rtl;
|
lgpl-3.0
|
07f2cc7c23eb4cedbf7ba960f1e7ae31
| 0.396806 | 3.543343 | false | false | false | false |
mithro/soft-utmi
|
hdl/serdes/tests/usbgen.vhd
| 1 | 2,722 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:44:27 06/21/2014
-- Design Name:
-- Module Name: usbgen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity usbgen is generic (
bitclk_period : time := 1 ns );
PORT(
go : in std_logic := '0';
d_p : out std_logic := '0';
d_n : out std_logic := '1';
dummy_clk : out std_logic;
dummy_idle : out std_logic;
dummy_in_sop : out std_logic;
dummy_in_pid : out std_logic);
end usbgen;
architecture arch_usbgen of usbgen is
signal in_sop : std_logic := '1';
signal in_pid : std_logic := '1';
signal idle : std_logic := '1';
-- The source of the packet signals the Start of Packet (SOP) in high-speed mode by driving the D+ and D- lines
-- from the high-speed Idle state to the K state. This K is the first symbol of the SYNC pattern (NRZI sequence
-- KJKJKJKJ KJKJKJKJ KJKJKJKJ KJKJKJKK) as described in Section 7.1.10.
constant sop : std_logic_vector(31 downto 0) := "10101010101010101010101010101000";
constant pid : std_logic_vector(7 downto 0) := "11010111";
begin
idle <= not (not in_sop or not in_pid);
dummy_idle <= idle;
dummy_in_sop <= in_sop;
dummy_in_pid <= in_pid;
dummy_clk_process :process
begin
wait until (go'event and go = '1');
while go = '1' loop
dummy_clk <= '0';
wait for bitclk_period/2;
dummy_clk <= '1';
wait for bitclk_period/2;
end loop;
end process;
data_process: process
begin
wait until (go'event and go = '1');
wait for bitclk_period*10;
-- start of packet / sync period
in_sop <= '0';
for i in sop'low to sop'high loop
d_p <= sop(sop'high - i);
d_n <= not sop(sop'high - i);
wait for bitclk_period;
end loop;
in_sop <= '1';
-- PID data
in_pid <= '0';
for i in pid'low to pid'high loop
d_p <= pid(pid'high - i);
d_n <= not pid(pid'high - i);
wait for bitclk_period;
end loop;
in_pid <= '1';
end process;
end arch_usbgen;
|
apache-2.0
|
ee7c60cff30b14631991500599372422
| 0.570904 | 3.507732 | false | false | false | false |
nanomolina/MIPS
|
prueba/regfile.vhd
| 2 | 1,098 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity regfile is
port (
--revisar las imputs son 5 BITS para MIPS??
ra1, ra2, wa3: in std_logic_vector(4 downto 0);
wd3: in std_logic_vector(31 downto 0);
we3, clk: in std_logic;
rd1, rd2: out std_logic_vector(31 downto 0)
);
end entity;
architecture BH of regfile is
constant ZERO : std_logic_vector (4 downto 0) := "00000";
--memoria: 64 palabras de 32 bits--
type mem_reg is array (63 downto 0) of std_logic_vector(31 downto 0);
signal mem_r : mem_reg := (OTHERS => x"00000000");
--signal
begin
process (ra1, ra2, clk, mem_r)
-- variable temp1, temp2, temp3 : integer;
-- variable mem_r : mem_reg := (OTHERS => x"00000000");
begin
if (clk'event and clk='1'and we3='1') then
mem_r(conv_integer(wa3)) <= wd3;
end if;
if (ra1 = ZERO ) then rd1 <= x"00000000";
else rd1 <= mem_r(conv_integer(ra1));
end if;
if (ra2 = ZERO) then rd2 <= x"00000000";
else rd2 <= mem_r(conv_integer(ra2));
end if;
end process;
end BH;
|
gpl-3.0
|
033b43f15d710e12950c0d20585e1475
| 0.655738 | 2.633094 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/usb_system/altera_reset_controller/_primary.vhd
| 2 | 4,647 |
library verilog;
use verilog.vl_types.all;
entity altera_reset_controller is
generic(
NUM_RESET_INPUTS: integer := 6;
USE_RESET_REQUEST_IN0: integer := 0;
USE_RESET_REQUEST_IN1: integer := 0;
USE_RESET_REQUEST_IN2: integer := 0;
USE_RESET_REQUEST_IN3: integer := 0;
USE_RESET_REQUEST_IN4: integer := 0;
USE_RESET_REQUEST_IN5: integer := 0;
USE_RESET_REQUEST_IN6: integer := 0;
USE_RESET_REQUEST_IN7: integer := 0;
USE_RESET_REQUEST_IN8: integer := 0;
USE_RESET_REQUEST_IN9: integer := 0;
USE_RESET_REQUEST_IN10: integer := 0;
USE_RESET_REQUEST_IN11: integer := 0;
USE_RESET_REQUEST_IN12: integer := 0;
USE_RESET_REQUEST_IN13: integer := 0;
USE_RESET_REQUEST_IN14: integer := 0;
USE_RESET_REQUEST_IN15: integer := 0;
OUTPUT_RESET_SYNC_EDGES: string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT: integer := 0;
RESET_REQ_WAIT_TIME: integer := 3;
MIN_RST_ASSERTION_TIME: integer := 11;
RESET_REQ_EARLY_DSRT_TIME: integer := 4;
ADAPT_RESET_REQUEST: integer := 0
);
port(
reset_in0 : in vl_logic;
reset_in1 : in vl_logic;
reset_in2 : in vl_logic;
reset_in3 : in vl_logic;
reset_in4 : in vl_logic;
reset_in5 : in vl_logic;
reset_in6 : in vl_logic;
reset_in7 : in vl_logic;
reset_in8 : in vl_logic;
reset_in9 : in vl_logic;
reset_in10 : in vl_logic;
reset_in11 : in vl_logic;
reset_in12 : in vl_logic;
reset_in13 : in vl_logic;
reset_in14 : in vl_logic;
reset_in15 : in vl_logic;
reset_req_in0 : in vl_logic;
reset_req_in1 : in vl_logic;
reset_req_in2 : in vl_logic;
reset_req_in3 : in vl_logic;
reset_req_in4 : in vl_logic;
reset_req_in5 : in vl_logic;
reset_req_in6 : in vl_logic;
reset_req_in7 : in vl_logic;
reset_req_in8 : in vl_logic;
reset_req_in9 : in vl_logic;
reset_req_in10 : in vl_logic;
reset_req_in11 : in vl_logic;
reset_req_in12 : in vl_logic;
reset_req_in13 : in vl_logic;
reset_req_in14 : in vl_logic;
reset_req_in15 : in vl_logic;
clk : in vl_logic;
reset_out : out vl_logic;
reset_req : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of NUM_RESET_INPUTS : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN0 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN1 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN2 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN3 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN4 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN5 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN6 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN7 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN8 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN9 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN10 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN11 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN12 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN13 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN14 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN15 : constant is 1;
attribute mti_svvh_generic_type of OUTPUT_RESET_SYNC_EDGES : constant is 1;
attribute mti_svvh_generic_type of SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of RESET_REQUEST_PRESENT : constant is 1;
attribute mti_svvh_generic_type of RESET_REQ_WAIT_TIME : constant is 1;
attribute mti_svvh_generic_type of MIN_RST_ASSERTION_TIME : constant is 1;
attribute mti_svvh_generic_type of RESET_REQ_EARLY_DSRT_TIME : constant is 1;
attribute mti_svvh_generic_type of ADAPT_RESET_REQUEST : constant is 1;
end altera_reset_controller;
|
apache-2.0
|
f84b04cb0d5d8b0d2c569a8b125f46f3
| 0.602754 | 3.335966 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/statements/FsmExample.vhd
| 1 | 1,852 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY FsmExample IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
clk : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF FsmExample IS
TYPE st_t IS (a_0, b_0, aAndB);
SIGNAL st : st_t := a_0;
SIGNAL st_next : st_t;
BEGIN
assig_process_dout: PROCESS(st)
BEGIN
CASE st IS
WHEN a_0 =>
dout <= "001";
WHEN b_0 =>
dout <= "010";
WHEN OTHERS =>
dout <= "011";
END CASE;
END PROCESS;
assig_process_st: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
st <= a_0;
ELSE
st <= st_next;
END IF;
END IF;
END PROCESS;
assig_process_st_next: PROCESS(a, b, st)
BEGIN
CASE st IS
WHEN a_0 =>
IF (a AND b) = '1' THEN
st_next <= aandb;
ELSIF b = '1' THEN
st_next <= b_0;
ELSE
st_next <= st;
END IF;
WHEN b_0 =>
IF (a AND b) = '1' THEN
st_next <= aandb;
ELSIF a = '1' THEN
st_next <= a_0;
ELSE
st_next <= st;
END IF;
WHEN OTHERS =>
IF (a AND NOT b) = '1' THEN
st_next <= a_0;
ELSIF (NOT a AND b) = '1' THEN
st_next <= b_0;
ELSE
st_next <= st;
END IF;
END CASE;
END PROCESS;
END ARCHITECTURE;
|
mit
|
5acd1f4d779400a6ce5372022bed0d59
| 0.391469 | 3.858333 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/TmpVarSignCast.vhd
| 1 | 1,093 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TmpVarSignCast IS
PORT(
a : IN STD_LOGIC;
b : IN UNSIGNED(0 DOWNTO 0);
c : OUT UNSIGNED(0 DOWNTO 0);
d : OUT UNSIGNED(0 DOWNTO 0);
e : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
i : IN STD_LOGIC;
o : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF TmpVarSignCast IS
BEGIN
assig_process_c: PROCESS(a, b)
VARIABLE tmp_std_logic2vector_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
tmp_std_logic2vector_0(0) := a;
c <= UNSIGNED(tmp_std_logic2vector_0) + b;
END PROCESS;
assig_process_d: PROCESS(a, b)
VARIABLE tmp_std_logic2vector_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
tmp_std_logic2vector_0(0) := a;
d <= b + UNSIGNED(tmp_std_logic2vector_0);
END PROCESS;
assig_process_o: PROCESS(e, i)
VARIABLE tmp1bToUnsigned_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
tmp1bToUnsigned_0(0) := i;
o <= e(TO_INTEGER(UNSIGNED(tmp1bToUnsigned_0)));
END PROCESS;
END ARCHITECTURE;
|
mit
|
7162f5c566506bd05ae1967db440bf10
| 0.610247 | 3.205279 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/usb_system/altera_merlin_slave_translator/_primary.vhd
| 1 | 5,001 |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_slave_translator is
generic(
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W: integer := 4;
AV_READLATENCY : integer := 1;
AV_READ_WAIT_CYCLES: integer := 0;
AV_WRITE_WAIT_CYCLES: integer := 0;
AV_SETUP_WAIT_CYCLES: integer := 0;
AV_DATA_HOLD_CYCLES: integer := 0;
USE_READDATAVALID: integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE: integer := 0;
USE_WRITERESPONSE: integer := 0;
AV_SYMBOLS_PER_WORD: integer := 4;
AV_ADDRESS_SYMBOLS: integer := 0;
AV_BURSTCOUNT_SYMBOLS: integer := 0;
BITS_PER_WORD : vl_notype;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W: integer := 10;
UAV_DATA_W : integer := 32;
AV_CONSTANT_BURST_BEHAVIOR: integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR: integer := 0;
CHIPSELECT_THROUGH_READLATENCY: integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES: integer := 0
);
port(
clk : in vl_logic;
reset : in vl_logic;
uav_address : in vl_logic_vector;
uav_writedata : in vl_logic_vector;
uav_write : in vl_logic;
uav_read : in vl_logic;
uav_burstcount : in vl_logic_vector;
uav_byteenable : in vl_logic_vector;
uav_lock : in vl_logic;
uav_debugaccess : in vl_logic;
uav_clken : in vl_logic;
uav_readdatavalid: out vl_logic;
uav_waitrequest : out vl_logic;
uav_readdata : out vl_logic_vector;
uav_response : out vl_logic_vector(1 downto 0);
uav_writeresponserequest: in vl_logic;
uav_writeresponsevalid: out vl_logic;
av_address : out vl_logic_vector;
av_writedata : out vl_logic_vector;
av_write : out vl_logic;
av_read : out vl_logic;
av_burstcount : out vl_logic_vector;
av_byteenable : out vl_logic_vector;
av_writebyteenable: out vl_logic_vector;
av_begintransfer: out vl_logic;
av_chipselect : out vl_logic;
av_beginbursttransfer: out vl_logic;
av_lock : out vl_logic;
av_clken : out vl_logic;
av_debugaccess : out vl_logic;
av_outputenable : out vl_logic;
av_readdata : in vl_logic_vector;
av_readdatavalid: in vl_logic;
av_waitrequest : in vl_logic;
av_response : in vl_logic_vector(1 downto 0);
av_writeresponserequest: out vl_logic;
av_writeresponsevalid: in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of AV_DATA_W : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of AV_BYTEENABLE_W : constant is 1;
attribute mti_svvh_generic_type of UAV_BYTEENABLE_W : constant is 1;
attribute mti_svvh_generic_type of AV_READLATENCY : constant is 1;
attribute mti_svvh_generic_type of AV_READ_WAIT_CYCLES : constant is 1;
attribute mti_svvh_generic_type of AV_WRITE_WAIT_CYCLES : constant is 1;
attribute mti_svvh_generic_type of AV_SETUP_WAIT_CYCLES : constant is 1;
attribute mti_svvh_generic_type of AV_DATA_HOLD_CYCLES : constant is 1;
attribute mti_svvh_generic_type of USE_READDATAVALID : constant is 1;
attribute mti_svvh_generic_type of USE_WAITREQUEST : constant is 1;
attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1;
attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1;
attribute mti_svvh_generic_type of AV_SYMBOLS_PER_WORD : constant is 1;
attribute mti_svvh_generic_type of AV_ADDRESS_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_WORD : constant is 3;
attribute mti_svvh_generic_type of UAV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of UAV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of UAV_DATA_W : constant is 1;
attribute mti_svvh_generic_type of AV_CONSTANT_BURST_BEHAVIOR : constant is 1;
attribute mti_svvh_generic_type of UAV_CONSTANT_BURST_BEHAVIOR : constant is 1;
attribute mti_svvh_generic_type of CHIPSELECT_THROUGH_READLATENCY : constant is 1;
attribute mti_svvh_generic_type of USE_UAV_CLKEN : constant is 1;
attribute mti_svvh_generic_type of AV_REQUIRE_UNALIGNED_ADDRESSES : constant is 1;
end altera_merlin_slave_translator;
|
apache-2.0
|
bdb4833669208a90f4a1668b122d7527
| 0.620076 | 3.698964 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/alt_dspbuilder_cast_GNLF52SJQ3.vhd
| 4 | 877 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNLF52SJQ3 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(7 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNLF52SJQ3 is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 8,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture;
|
mit
|
d732376ff730fb378d12fcb05371a2bd
| 0.648803 | 3.066434 | false | false | false | false |
Jawanga/ece385final
|
usb_system/usb_system_inst.vhd
| 1 | 3,579 |
component usb_system is
port (
clk_clk : in std_logic := 'X'; -- clk
keycode_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_out_clk_clk : out std_logic; -- clk
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_wire_cas_n : out std_logic; -- cas_n
sdram_wire_cke : out std_logic; -- cke
sdram_wire_cs_n : out std_logic; -- cs_n
sdram_wire_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- dq
sdram_wire_dqm : out std_logic_vector(3 downto 0); -- dqm
sdram_wire_ras_n : out std_logic; -- ras_n
sdram_wire_we_n : out std_logic; -- we_n
usb_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
usb_ADDR : out std_logic_vector(1 downto 0); -- ADDR
usb_RD_N : out std_logic; -- RD_N
usb_WR_N : out std_logic; -- WR_N
usb_CS_N : out std_logic; -- CS_N
usb_RST_N : out std_logic; -- RST_N
usb_INT : in std_logic := 'X'; -- INT
usb_out_clk_clk : out std_logic -- clk
);
end component usb_system;
u0 : component usb_system
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
keycode_export => CONNECTED_TO_keycode_export, -- keycode.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_out_clk_clk => CONNECTED_TO_sdram_out_clk_clk, -- sdram_out_clk.clk
sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
usb_DATA => CONNECTED_TO_usb_DATA, -- usb.DATA
usb_ADDR => CONNECTED_TO_usb_ADDR, -- .ADDR
usb_RD_N => CONNECTED_TO_usb_RD_N, -- .RD_N
usb_WR_N => CONNECTED_TO_usb_WR_N, -- .WR_N
usb_CS_N => CONNECTED_TO_usb_CS_N, -- .CS_N
usb_RST_N => CONNECTED_TO_usb_RST_N, -- .RST_N
usb_INT => CONNECTED_TO_usb_INT, -- .INT
usb_out_clk_clk => CONNECTED_TO_usb_out_clk_clk -- usb_out_clk.clk
);
|
apache-2.0
|
2eaa5a64dedb5f0ed1751c05f9d548b5
| 0.412406 | 3.447977 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/peripheral/displays/Segment7.vhd
| 1 | 1,555 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- 7-segment display decoder
--
-- :note: led in display becomes active when output = 0
--
-- Display pin connection on image below.
--
-- .. code-block:: raw
--
-- -------------
-- | 0 |
-- -------------
-- | 5 | | 1 |
-- -------------
-- | 6 |
-- -------------
-- | 4 | | 2 |
-- -------------
-- | 3 |
-- -------------
--
-- .. hwt-autodoc::
--
ENTITY Segment7 IS
PORT(
dataIn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dataOut : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF Segment7 IS
BEGIN
assig_process_dataOut: PROCESS(dataIn)
BEGIN
CASE dataIn IS
WHEN X"0" =>
dataOut <= "0000001";
WHEN X"1" =>
dataOut <= "1001111";
WHEN X"2" =>
dataOut <= "0010010";
WHEN X"3" =>
dataOut <= "0000110";
WHEN X"4" =>
dataOut <= "1001100";
WHEN X"5" =>
dataOut <= "0100100";
WHEN X"6" =>
dataOut <= "0100000";
WHEN X"7" =>
dataOut <= "0001111";
WHEN X"8" =>
dataOut <= "0000000";
WHEN X"9" =>
dataOut <= "0000100";
WHEN OTHERS =>
dataOut <= "1111111";
END CASE;
END PROCESS;
END ARCHITECTURE;
|
mit
|
236007820168bb43dfa6249972eadff7
| 0.388424 | 4.092105 | false | false | false | false |
tec499-20142/t01-warmup
|
rtl/uart.vhd
| 1 | 3,886 |
----------------------------------------------------------------------------------
-- Creation Date: 21:12:48 05/06/2010
-- Module Name: RS232/UART Interface - Behavioral
-- Used TAB of 4 Spaces
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity uart is
generic (
CLK_FREQ : integer := 50; -- Main frequency (MHz)
SER_FREQ : integer := 9600 -- Baud rate (bps)
);
port (
-- Control
clk : in std_logic; -- Main clock
rst : in std_logic; -- Main reset
-- External Interface
rx : in std_logic; -- RS232 received serial data
-- uPC Interface
rx_ready : out std_logic; -- Received data ready to uPC read
rx_data : out std_logic_vector(7 downto 0) -- Received data
);
end uart;
architecture Behavioral of uart is
-- Constants
constant UART_IDLE : std_logic := '1';
constant UART_START : std_logic := '0';
constant RST_LVL : std_logic := '0';
-- Types
type state is (idle,data); -- Stop1 and Stop2 are inter frame gap signals
-- RX Signals
signal rx_fsm : state; -- Control of reception
signal rx_clk_en : std_logic; -- Received clock enable
signal rx_rcv_init : std_logic; -- Start of reception
signal rx_data_deb : std_logic; -- Debounce RX data
signal rx_data_tmp : std_logic_vector(7 downto 0); -- Serial to parallel converter
signal rx_data_cnt : std_logic_vector(2 downto 0); -- Count received bits
begin
rx_debounceer:process(clk) --controle que estabiliza
variable deb_buf : std_logic_vector(3 downto 0);
begin
if clk'event and clk = '1' then
-- Debounce logic
if deb_buf = "0000" then
rx_data_deb <= '0';
elsif deb_buf = "1111" then
rx_data_deb <= '1';
end if;
-- Data storage to debounce
deb_buf := deb_buf(2 downto 0) & rx;
end if;
end process;
rx_start_detect:process(clk)
variable rx_data_old : std_logic;
begin
if clk'event and clk = '1' then
-- Falling edge detection
if rx_data_old = '1' and rx_data_deb = '0' and rx_fsm = idle then
rx_rcv_init <= '1';
else
rx_rcv_init <= '0';
end if;
-- Default assignments
rx_data_old := rx_data_deb;
-- Reset condition
if rst = RST_LVL then
rx_data_old := '0';
rx_rcv_init <= '0';
end if;
end if;
end process;
rx_clk_gen:process(clk)
variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
begin
if clk'event and clk = '1' then
-- Normal Operation
if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 or rx_rcv_init = '1' then
rx_clk_en <= '1';
counter := 0;
else
rx_clk_en <= '0';
counter := counter + 1;
end if;
-- Reset condition
if rst = RST_LVL then
rx_clk_en <= '0';
counter := 0;
end if;
end if;
end process;
rx_proc:process(clk)
begin
if clk'event and clk = '1' then
-- Default values
rx_ready <= '0';
-- Enable on UART rate
if rx_clk_en = '1' then
-- FSM description
case rx_fsm is
-- Wait to transfer data
when idle =>
if rx_data_deb = UART_START then
rx_fsm <= data;
end if;
rx_data_cnt <= (others=>'0');
-- Data receive
when data =>
if rx_data_cnt = 7 then
-- Data path
rx_data(7) <= rx;
for i in 0 to 6 loop
rx_data(i) <= rx_data_tmp(6-i);
end loop;
rx_ready <= '1';
rx_fsm <= idle;
end if;
rx_data_tmp <= rx_data_tmp(6 downto 0) & rx;
rx_data_cnt <= rx_data_cnt + 1;
when others => null;
end case;
-- Reset condition
if rst = RST_LVL then
rx_fsm <= idle;
rx_ready <= '0';
rx_data <= (others=>'0');
rx_data_tmp <= (others=>'0');
rx_data_cnt <= (others=>'0');
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
fbc476c91a6a879f1342190527b5b59a
| 0.566907 | 2.738548 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASliceOfReg0.vhd
| 1 | 1,711 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Register where slices of next signal are set conditionally
--
ENTITY AssignToASliceOfReg0 IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg0 IS
SIGNAL r : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL r_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"0000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_15downto8 & r_next_7downto0;
assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, data_in_vld, r)
BEGIN
IF data_in_vld = '1' AND data_in_addr = "1" THEN
r_next_15downto8 <= data_in_data;
ELSE
r_next_15downto8 <= r(15 DOWNTO 8);
END IF;
END PROCESS;
assig_process_r_next_7downto0: PROCESS(data_in_addr, data_in_data, data_in_vld, r)
BEGIN
IF data_in_vld = '1' AND data_in_addr = "0" THEN
r_next_7downto0 <= data_in_data;
ELSE
r_next_7downto0 <= r(7 DOWNTO 0);
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
357b980cfa1b80f0bed086ecb31203d5
| 0.578609 | 3.192164 | false | false | false | false |
nanomolina/MIPS
|
PIPELINE/datapath.vhd
| 1 | 5,014 |
library ieee;
use ieee.std_logic_1164.all;
entity datapath is
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
AluSrc : in std_logic;
RegDst : in std_logic;
RegWrite : in std_logic;
Jump : in std_logic;
AluControl : in std_logic_vector(2 downto 0);
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic);
end entity;
architecture arq_datapath of datapath is
component fetch
port(
jumpM, PcSrcM, clk, reset: in std_logic;
PcBranchM: in std_logic_vector(31 downto 0);
InstrF, PCF, PCPlus4F: out std_logic_vector(31 downto 0));
end component;
component decode
port(
A3: in std_logic_vector(4 downto 0);
InstrD, Wd3: in std_logic_vector(31 downto 0);
RegWrite, clk: in std_logic;
RtD, RdD: out std_logic_vector(4 downto 0);
SignImmD, RD1D, RD2D: out std_logic_vector(31 downto 0));
end component;
component execute
port(
RD1E, RD2E, PCPlus4E, SignImmE: in std_logic_vector(31 downto 0);
RtE, RdE: in std_logic_vector(4 downto 0);
RegDst, AluSrc : in std_logic;
AluControl: in std_logic_vector(2 downto 0);
WriteRegE: out std_logic_vector(4 downto 0);
ZeroE: out std_logic;
AluOutE, WriteDataE, PCBranchE: out std_logic_vector(31 downto 0));
end component;
component memory
port(
AluOutM, WriteDataM: in std_logic_vector(31 downto 0);
ZeroM, MemWrite, Branch, clk, dump: in std_logic;
ReadDataM: out std_logic_vector(31 downto 0);
PCSrcM: out std_logic);
end component;
component writeback
port(
AluOutW, ReadDataW: in std_logic_vector(31 downto 0);
MemToReg: in std_logic;
ResultW: out std_logic_vector(31 downto 0));
end component;
signal PcBranchM_s, InstrF_s, PCF_s, PCPlus4F_s,
InstrD_s,RD2E_s, RD1E_s, SignImmE_s,
AluOutM_s, WriteDataM_s, ReadDataW_s,
ResultW_s : std_logic_vector(31 downto 0);
signal ZeroM_s, PcSrcM_s : std_logic;
signal A3_s, RtE_s, RdE_s : std_logic_vector(4 downto 0);
begin
Fetch1: fetch port map(
jumpM => Jump,
PcSrcM => PCSrcM_s, --changing
clk => clk,
reset => reset,
PcBranchM => PCBranchM_s,
InstrF => InstrD_s, --changing
PCF => pc,
PCPlus4F => PCPlus4F_s --changing
);
Decode1: decode port map(
A3 => A3_s, --changing
InstrD => InstrD_s, --changing
Wd3 => ResultW_s,
RegWrite => RegWrite,
clk => clk,
RtD => RtE_s,
RdD => RdE_s,
SignImmD => SignImmE_s,
RD1D => RD1E_s,
RD2D => RD2E_s
);
Execute1: execute port map(
RD1E => RD1E_s, --changing
RD2E => RD2E_s,
PCPlus4E => PCPlus4F_s,
SignImmE => SignImmE_s, --changing
RtE => RtE_s, --changing
RdE => RdE_s,
RegDst => RegDst,
AluSrc => AluSrc,
AluControl => AluControl,
WriteRegE => A3_s,
ZeroE => ZeroM_s,
AluOutE => AluOutM_s,
WriteDataE => WriteDataM_s,
PCBranchE => PCBranchM_s
);
Memory1: memory port map(
AluOutM => AluOutM_s, --changing
WriteDataM => WriteDataM_s, --changing
ZeroM => ZeroM_s, --changing
MemWrite => MemWrite,
Branch => Branch,
clk => clk,
dump => dump,
ReadDataM => ReadDataW_s,
PCSrcM => PCSrcM_s --Posee el mismo nombre (posible conflicto futuro) illak:Para nada!
);
WriteBack1: writeback port map(
AluOutW => AluOutM_s, --changing
ReadDataW => ReadDataW_s, --changing
MemToReg => MemToReg,
ResultW => ResultW_s --changing
);
instr <= instrD_s;
end arq_datapath;
|
gpl-3.0
|
87bb146add2cfee2a4d4bc28c2e5569a
| 0.454926 | 4.480786 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/finalproject/altera_merlin_master_agent/_primary.vhd
| 1 | 8,144 |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_master_agent is
generic(
PKT_QOS_H : integer := 109;
PKT_QOS_L : integer := 106;
PKT_DATA_SIDEBAND_H: integer := 105;
PKT_DATA_SIDEBAND_L: integer := 98;
PKT_ADDR_SIDEBAND_H: integer := 97;
PKT_ADDR_SIDEBAND_L: integer := 93;
PKT_CACHE_H : integer := 92;
PKT_CACHE_L : integer := 89;
PKT_THREAD_ID_H : integer := 88;
PKT_THREAD_ID_L : integer := 87;
PKT_BEGIN_BURST : integer := 81;
PKT_PROTECTION_H: integer := 80;
PKT_PROTECTION_L: integer := 80;
PKT_BURSTWRAP_H : integer := 79;
PKT_BURSTWRAP_L : integer := 77;
PKT_BYTE_CNT_H : integer := 76;
PKT_BYTE_CNT_L : integer := 74;
PKT_ADDR_H : integer := 73;
PKT_ADDR_L : integer := 42;
PKT_BURST_SIZE_H: integer := 86;
PKT_BURST_SIZE_L: integer := 84;
PKT_BURST_TYPE_H: integer := 94;
PKT_BURST_TYPE_L: integer := 93;
PKT_TRANS_EXCLUSIVE: integer := 83;
PKT_TRANS_LOCK : integer := 82;
PKT_TRANS_COMPRESSED_READ: integer := 41;
PKT_TRANS_POSTED: integer := 40;
PKT_TRANS_WRITE : integer := 39;
PKT_TRANS_READ : integer := 38;
PKT_DATA_H : integer := 37;
PKT_DATA_L : integer := 6;
PKT_BYTEEN_H : integer := 5;
PKT_BYTEEN_L : integer := 2;
PKT_SRC_ID_H : integer := 1;
PKT_SRC_ID_L : integer := 1;
PKT_DEST_ID_H : integer := 0;
PKT_DEST_ID_L : integer := 0;
PKT_RESPONSE_STATUS_L: integer := 110;
PKT_RESPONSE_STATUS_H: integer := 111;
PKT_ORI_BURST_SIZE_L: integer := 112;
PKT_ORI_BURST_SIZE_H: integer := 114;
ST_DATA_W : integer := 115;
ST_CHANNEL_W : integer := 1;
AV_BURSTCOUNT_W : integer := 3;
ID : integer := 1;
SUPPRESS_0_BYTEEN_RSP: integer := 1;
BURSTWRAP_VALUE : integer := 4;
CACHE_VALUE : integer := 0;
SECURE_ACCESS_BIT: integer := 1;
USE_READRESPONSE: integer := 0;
USE_WRITERESPONSE: integer := 0;
PKT_BURSTWRAP_W : vl_notype;
PKT_BYTE_CNT_W : vl_notype;
PKT_PROTECTION_W: vl_notype;
PKT_ADDR_W : vl_notype;
PKT_DATA_W : vl_notype;
PKT_BYTEEN_W : vl_notype;
PKT_SRC_ID_W : vl_notype;
PKT_DEST_ID_W : vl_notype;
PKT_BURST_SIZE_W: vl_notype
);
port(
clk : in vl_logic;
reset : in vl_logic;
av_address : in vl_logic_vector;
av_write : in vl_logic;
av_read : in vl_logic;
av_writedata : in vl_logic_vector;
av_readdata : out vl_logic_vector;
av_waitrequest : out vl_logic;
av_readdatavalid: out vl_logic;
av_byteenable : in vl_logic_vector;
av_burstcount : in vl_logic_vector;
av_debugaccess : in vl_logic;
av_lock : in vl_logic;
av_response : out vl_logic_vector(1 downto 0);
av_writeresponsevalid: out vl_logic;
cp_valid : out vl_logic;
cp_data : out vl_logic_vector;
cp_startofpacket: out vl_logic;
cp_endofpacket : out vl_logic;
cp_ready : in vl_logic;
rp_valid : in vl_logic;
rp_data : in vl_logic_vector;
rp_channel : in vl_logic_vector;
rp_startofpacket: in vl_logic;
rp_endofpacket : in vl_logic;
rp_ready : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of PKT_QOS_H : constant is 1;
attribute mti_svvh_generic_type of PKT_QOS_L : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_SIDEBAND_H : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_SIDEBAND_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_SIDEBAND_H : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_SIDEBAND_L : constant is 1;
attribute mti_svvh_generic_type of PKT_CACHE_H : constant is 1;
attribute mti_svvh_generic_type of PKT_CACHE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_THREAD_ID_H : constant is 1;
attribute mti_svvh_generic_type of PKT_THREAD_ID_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BEGIN_BURST : constant is 1;
attribute mti_svvh_generic_type of PKT_PROTECTION_H : constant is 1;
attribute mti_svvh_generic_type of PKT_PROTECTION_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BURSTWRAP_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BURSTWRAP_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTE_CNT_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTE_CNT_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_H : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_SIZE_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_SIZE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_TYPE_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_TYPE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_EXCLUSIVE : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_LOCK : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_COMPRESSED_READ : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_POSTED : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_WRITE : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_READ : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_H : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTEEN_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTEEN_L : constant is 1;
attribute mti_svvh_generic_type of PKT_SRC_ID_H : constant is 1;
attribute mti_svvh_generic_type of PKT_SRC_ID_L : constant is 1;
attribute mti_svvh_generic_type of PKT_DEST_ID_H : constant is 1;
attribute mti_svvh_generic_type of PKT_DEST_ID_L : constant is 1;
attribute mti_svvh_generic_type of PKT_RESPONSE_STATUS_L : constant is 1;
attribute mti_svvh_generic_type of PKT_RESPONSE_STATUS_H : constant is 1;
attribute mti_svvh_generic_type of PKT_ORI_BURST_SIZE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ORI_BURST_SIZE_H : constant is 1;
attribute mti_svvh_generic_type of ST_DATA_W : constant is 1;
attribute mti_svvh_generic_type of ST_CHANNEL_W : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of ID : constant is 1;
attribute mti_svvh_generic_type of SUPPRESS_0_BYTEEN_RSP : constant is 1;
attribute mti_svvh_generic_type of BURSTWRAP_VALUE : constant is 1;
attribute mti_svvh_generic_type of CACHE_VALUE : constant is 1;
attribute mti_svvh_generic_type of SECURE_ACCESS_BIT : constant is 1;
attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1;
attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1;
attribute mti_svvh_generic_type of PKT_BURSTWRAP_W : constant is 3;
attribute mti_svvh_generic_type of PKT_BYTE_CNT_W : constant is 3;
attribute mti_svvh_generic_type of PKT_PROTECTION_W : constant is 3;
attribute mti_svvh_generic_type of PKT_ADDR_W : constant is 3;
attribute mti_svvh_generic_type of PKT_DATA_W : constant is 3;
attribute mti_svvh_generic_type of PKT_BYTEEN_W : constant is 3;
attribute mti_svvh_generic_type of PKT_SRC_ID_W : constant is 3;
attribute mti_svvh_generic_type of PKT_DEST_ID_W : constant is 3;
attribute mti_svvh_generic_type of PKT_BURST_SIZE_W : constant is 3;
end altera_merlin_master_agent;
|
apache-2.0
|
e25d0b0aead0f8ba1961e8a71b688b12
| 0.62279 | 3.450847 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/statements/SwitchStmUnit.vhd
| 1 | 774 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Example which is using switch statement to create multiplexer
--
-- .. hwt-autodoc::
--
ENTITY SwitchStmUnit IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
out_0 : OUT STD_LOGIC;
sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF SwitchStmUnit IS
BEGIN
assig_process_out_0: PROCESS(a, b, c, sel)
BEGIN
CASE sel IS
WHEN "000" =>
out_0 <= a;
WHEN "001" =>
out_0 <= b;
WHEN "010" =>
out_0 <= c;
WHEN OTHERS =>
out_0 <= '0';
END CASE;
END PROCESS;
END ARCHITECTURE;
|
mit
|
875d65ac36daef0757f3788f1bf06459
| 0.501292 | 3.6 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_addsub/fp_addsub.vhd
| 1 | 6,065 |
-- megafunction wizard: %ALTERA_FP_FUNCTIONS v17.0%
-- GENERATION: XML
-- fp_addsub.vhd
-- Generated using ACDS version 17.0 595
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fp_addsub is
port (
clk : in std_logic := '0'; -- clk.clk
areset : in std_logic := '0'; -- areset.reset
a : in std_logic_vector(31 downto 0) := (others => '0'); -- a.a
b : in std_logic_vector(31 downto 0) := (others => '0'); -- b.b
q : out std_logic_vector(31 downto 0); -- q.q
s : out std_logic_vector(31 downto 0) -- s.s
);
end entity fp_addsub;
architecture rtl of fp_addsub is
component fp_addsub_0002 is
port (
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(31 downto 0); -- q
s : out std_logic_vector(31 downto 0) -- s
);
end component fp_addsub_0002;
begin
fp_addsub_inst : component fp_addsub_0002
port map (
clk => clk, -- clk.clk
areset => areset, -- areset.reset
a => a, -- a.a
b => b, -- b.b
q => q, -- q.q
s => s -- s.s
);
end architecture rtl; -- of fp_addsub
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_fp_functions" version="17.0" >
-- Retrieval info: <generic name="FUNCTION_FAMILY" value="ARITH" />
-- Retrieval info: <generic name="ARITH_function" value="ADDSUB" />
-- Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
-- Retrieval info: <generic name="ALL_function" value="ADD" />
-- Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
-- Retrieval info: <generic name="TRIG_function" value="SIN" />
-- Retrieval info: <generic name="COMPARE_function" value="MIN" />
-- Retrieval info: <generic name="ROOTS_function" value="SQRT" />
-- Retrieval info: <generic name="fp_format" value="single" />
-- Retrieval info: <generic name="fp_exp" value="8" />
-- Retrieval info: <generic name="fp_man" value="23" />
-- Retrieval info: <generic name="exponent_width" value="23" />
-- Retrieval info: <generic name="frequency_target" value="25" />
-- Retrieval info: <generic name="latency_target" value="2" />
-- Retrieval info: <generic name="performance_goal" value="frequency" />
-- Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
-- Retrieval info: <generic name="faithful_rounding" value="true" />
-- Retrieval info: <generic name="gen_enable" value="false" />
-- Retrieval info: <generic name="divide_type" value="0" />
-- Retrieval info: <generic name="select_signal_enable" value="false" />
-- Retrieval info: <generic name="scale_by_pi" value="false" />
-- Retrieval info: <generic name="number_of_inputs" value="2" />
-- Retrieval info: <generic name="trig_no_range_reduction" value="false" />
-- Retrieval info: <generic name="report_resources_to_xml" value="false" />
-- Retrieval info: <generic name="fxpt_width" value="32" />
-- Retrieval info: <generic name="fxpt_fraction" value="0" />
-- Retrieval info: <generic name="fxpt_sign" value="1" />
-- Retrieval info: <generic name="fp_out_format" value="single" />
-- Retrieval info: <generic name="fp_out_exp" value="8" />
-- Retrieval info: <generic name="fp_out_man" value="23" />
-- Retrieval info: <generic name="fp_in_format" value="single" />
-- Retrieval info: <generic name="fp_in_exp" value="8" />
-- Retrieval info: <generic name="fp_in_man" value="23" />
-- Retrieval info: <generic name="enable_hard_fp" value="true" />
-- Retrieval info: <generic name="manual_dsp_planning" value="true" />
-- Retrieval info: <generic name="forceRegisters" value="1111" />
-- Retrieval info: <generic name="selected_device_family" value="MAX 10" />
-- Retrieval info: <generic name="selected_device_speedgrade" value="6" />
-- Retrieval info: </instance>
-- IPFS_FILES : fp_addsub.vho
-- RELATED_FILES: fp_addsub.vhd, dspba_library_package.vhd, dspba_library.vhd, fp_addsub_0002.vhd
|
mit
|
8abb9145a62b88b161b0032d55c5608e
| 0.635614 | 3.509838 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/clock_generator_sdr_s8_diff.vhd
| 1 | 6,489 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: clock_generator_sdr_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: BUFIO2 Based SDR clock generator. Takes in a differential clock
-- and instantiates two sets of 2 BUFIO2s, one for data transmission
-- at input clock rate for one half bank using one BUFIO2, and one for
-- clock transmission at double the input clock rate (to get the
-- original clock back) using 2 BUFIO2 in the other half bank
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity clock_generator_sdr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclka : out std_logic ; -- A ioclock from BUFIO2 for data transmission
serdesstrobea : out std_logic ; -- A serdes strobe from BUFIO2 for data transmission
ioclkbp : out std_logic ; -- B P ioclock from BUFIO2 - for clock transmission
ioclkbn : out std_logic ; -- B N ioclock from BUFIO2 - for clock transmission
serdesstrobeb : out std_logic ; -- B serdes strobe from BUFIO2 - for clock transmission
gclk : out std_logic) ; -- global clock output from BUFIO2
end clock_generator_sdr_s8_diff ;
architecture arch_clock_generator_sdr_s8_diff of clock_generator_sdr_s8_diff is
signal clkint : std_logic ; --
signal gclk_int : std_logic ; --
signal freqgen_in_p : std_logic ; --
signal tx_bufio2_x1 : std_logic ; --
begin
gclk <= gclk_int ;
iob_freqgen_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => freqgen_in_p);
bufio2_inst1 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => FALSE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => FALSE) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclka, -- Output Clock for IO
DIVCLK => tx_bufio2_x1, -- Output Divided Clock
SERDESSTROBE => serdesstrobea) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst2 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => FALSE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => TRUE) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclkbp, -- Output Clock for IO
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => serdesstrobeb) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst3 : BUFIO2 generic map(
I_INVERT => TRUE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => FALSE) --
port map (
I => freqgen_in_p, -- N_clk input from IDELAY
IOCLK => ioclkbn, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
bufg_tx : BUFG port map (I => tx_bufio2_x1, O => gclk_int) ;
end arch_clock_generator_sdr_s8_diff ;
|
apache-2.0
|
b177988e822dd8742c6325400b8cb17a
| 0.575127 | 4.020446 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/reports/Gray_Binarization/Gray_Binarization_example.vhd
| 1 | 2,480 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Gray_Binarization_example is
port(
Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Sink_endofpacket : in STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_ST_Sink_valid : in STD_LOGIC;
Clock : in STD_LOGIC;
Avalon_ST_Source_endofpacket : out STD_LOGIC;
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
Avalon_ST_Sink_ready : out STD_LOGIC;
Avalon_ST_Sink_startofpacket : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0));
end entity;
architecture rtl of Gray_Binarization_example is
component Gray_Binarization
port(
Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Sink_endofpacket : in STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_ST_Sink_valid : in STD_LOGIC;
Clock : in STD_LOGIC;
Avalon_ST_Source_endofpacket : out STD_LOGIC;
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
Avalon_ST_Sink_ready : out STD_LOGIC;
Avalon_ST_Sink_startofpacket : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0));
end component;
begin
Gray_Binarization_instance :
component Gray_Binarization
port map(
Avalon_ST_Sink_data => Avalon_ST_Sink_data,
Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket,
Avalon_MM_Slave_address => Avalon_MM_Slave_address,
Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata,
Avalon_ST_Source_valid => Avalon_ST_Source_valid,
Avalon_ST_Sink_valid => Avalon_ST_Sink_valid,
Clock => Clock,
Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket,
Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket,
Avalon_MM_Slave_write => Avalon_MM_Slave_write,
aclr => aclr,
Avalon_ST_Source_ready => Avalon_ST_Source_ready,
Avalon_ST_Sink_ready => Avalon_ST_Sink_ready,
Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket,
Avalon_ST_Source_data => Avalon_ST_Source_data);
end architecture rtl;
|
mit
|
e109cec54025d7aa3e84b2cae6502386
| 0.720565 | 3.050431 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/ram/ram.vhd
| 1 | 2,941 |
-- Signle port RAM based on Quartus II VHDL Template
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"; --base address of the RAM
ADDRESS_WIDE: natural := 8 --default address range
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic
);
end entity ram;
architecture ram_arch of ram is
-- Build a 2-D array type for the RAM
subtype word_t is unsigned(31 downto 0);
type memory_t is array((2**ADDRESS_WIDE)-1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
--register for address
signal reg_address: unsigned(ADDRESS_WIDE-1 downto 0);
--select this block, from address decoder
signal cs: std_logic;
type ack_fsm is (idle, set);
signal ack_fsm_state: ack_fsm;
begin
process(address) is begin
if (unsigned(address) >= BASE_ADDRESS and unsigned(address) <= (BASE_ADDRESS + (2**ADDRESS_WIDE)-1)) then
cs <= '1';
else
cs <= '0';
end if;
end process;
process(clk, WR, address, data_mosi, cs) begin
if(rising_edge(clk)) then
if(WR = '1' and cs = '1') then
ram(to_integer(unsigned(address))) <= unsigned(data_mosi);
end if;
reg_address <= unsigned(address(ADDRESS_WIDE-1 downto 0));
end if;
end process;
--output from ram
data_miso <= std_logic_vector(ram(to_integer(reg_address))) when ((RD = '1') and (cs = '1')) else (others => 'Z');
process(clk) is
begin
if rising_edge(clk) then
if res = '1' then
ack_fsm_state <= idle;
else
case ack_fsm_state is
when idle =>
if ((WR = '1' and cs = '1') or (RD = '1' and cs = '1')) then
ack_fsm_state <= set;
else
ack_fsm_state <= idle;
end if;
when set =>
ack_fsm_state <= idle;
end case;
end if;
end if;
end process;
process(ack_fsm_state) is
begin
case ack_fsm_state is
when idle =>
ack <= '0';
when set =>
ack <= '1';
end case;
end process;
end architecture ram_arch;
|
mit
|
a52d9959735ca8a5818251eaf475ddf3
| 0.509864 | 3.935743 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_n_to_1_s8_diff.vhd
| 1 | 9,379 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_n_to_1_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic n:1 transmitter module
-- Takes in n bits of data and serialises this to 1 bit
-- data is transmitted LSB first
-- Parallel input word
-- DS, DS-1 ..... 1, 0
-- Serial output words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Data inversion can be accomplished via the TX_SWAP_MASK
-- parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_n_to_1_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end serdes_n_to_1_s8_diff ;
architecture arch_serdes_n_to_1_s8_diff of serdes_n_to_1_s8_diff is
signal cascade_di : std_logic_vector(D-1 downto 0) ;
signal cascade_do : std_logic_vector(D-1 downto 0) ;
signal cascade_ti : std_logic_vector(D-1 downto 0) ;
signal cascade_to : std_logic_vector(D-1 downto 0) ;
signal mdataina : std_logic_vector(D*8 downto 0) ;
signal mdatainb : std_logic_vector(D*4 downto 0) ;
signal tx_data_out : std_logic_vector(D-1 downto 0) ;
constant TX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
loop0 : for i in 0 to (D - 1) generate
io_clk_out : obufds port map (
O => dataout_p(i),
OB => dataout_n(i),
I => tx_data_out(i));
loop1 : if (S > 4) generate -- Two oserdes are needed
loop2 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdataina((8*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+7),
D3 => mdataina((8*i)+6),
D2 => mdataina((8*i)+5),
D1 => mdataina((8*i)+4),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- Dummy input in Master
SHIFTIN2 => '1', -- Dummy input in Master
SHIFTIN3 => cascade_do(i), -- Cascade output D data from slave
SHIFTIN4 => cascade_to(i), -- Cascade output T data from slave
SHIFTOUT1 => cascade_di(i), -- Cascade input D data to slave
SHIFTOUT2 => cascade_ti(i), -- Cascade input T data to slave
SHIFTOUT3 => open, -- Dummy output in Master
SHIFTOUT4 => open) ; -- Dummy output in Master
oserdes_s : OSERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => open,
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+3),
D3 => mdataina((8*i)+2),
D2 => mdataina((8*i)+1),
D1 => mdataina((8*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => cascade_di(i), -- Cascade input D from Master
SHIFTIN2 => cascade_ti(i), -- Cascade input T from Master
SHIFTIN3 => '1', -- Dummy input in Slave
SHIFTIN4 => '1', -- Dummy input in Slave
SHIFTOUT1 => open, -- Dummy output in Slave
SHIFTOUT2 => open, -- Dummy output in Slave
SHIFTOUT3 => cascade_do(i), -- Cascade output D data to Master
SHIFTOUT4 => cascade_to(i)) ; -- Cascade output T data to Master
end generate ;
loop3 : if (S < 5) generate -- Only one oserdes needed
loop4 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdatainb((4*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR") -- <SDR>, DDR
-- SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
-- OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdatainb((4*i)+3),
D3 => mdatainb((4*i)+2),
D2 => mdatainb((4*i)+1),
D1 => mdatainb((4*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- No cascades needed
SHIFTIN2 => '1', -- No cascades needed
SHIFTIN3 => '1', -- No cascades needed
SHIFTIN4 => '1', -- No cascades needed
SHIFTOUT1 => open, -- No cascades needed
SHIFTOUT2 => open, -- No cascades needed
SHIFTOUT3 => open, -- No cascades needed
SHIFTOUT4 => open) ; -- No cascades needed
end generate ;
end generate ;
end arch_serdes_n_to_1_s8_diff ;
|
apache-2.0
|
74a0ab8c9470a036f400a5a8c9c5ef7f
| 0.589935 | 3.116982 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_cmp_gt/fp_cmp_gt.vhd
| 1 | 5,883 |
-- megafunction wizard: %ALTERA_FP_FUNCTIONS v17.0%
-- GENERATION: XML
-- fp_cmp_gt.vhd
-- Generated using ACDS version 17.0 595
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fp_cmp_gt is
port (
clk : in std_logic := '0'; -- clk.clk
areset : in std_logic := '0'; -- areset.reset
a : in std_logic_vector(31 downto 0) := (others => '0'); -- a.a
b : in std_logic_vector(31 downto 0) := (others => '0'); -- b.b
q : out std_logic_vector(0 downto 0) -- q.q
);
end entity fp_cmp_gt;
architecture rtl of fp_cmp_gt is
component fp_cmp_gt_0002 is
port (
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(0 downto 0) -- q
);
end component fp_cmp_gt_0002;
begin
fp_cmp_gt_inst : component fp_cmp_gt_0002
port map (
clk => clk, -- clk.clk
areset => areset, -- areset.reset
a => a, -- a.a
b => b, -- b.b
q => q -- q.q
);
end architecture rtl; -- of fp_cmp_gt
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_fp_functions" version="17.0" >
-- Retrieval info: <generic name="FUNCTION_FAMILY" value="COMPARE" />
-- Retrieval info: <generic name="ARITH_function" value="ADD" />
-- Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
-- Retrieval info: <generic name="ALL_function" value="ADD" />
-- Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
-- Retrieval info: <generic name="TRIG_function" value="SIN" />
-- Retrieval info: <generic name="COMPARE_function" value="GT" />
-- Retrieval info: <generic name="ROOTS_function" value="SQRT" />
-- Retrieval info: <generic name="fp_format" value="single" />
-- Retrieval info: <generic name="fp_exp" value="8" />
-- Retrieval info: <generic name="fp_man" value="23" />
-- Retrieval info: <generic name="exponent_width" value="23" />
-- Retrieval info: <generic name="frequency_target" value="25" />
-- Retrieval info: <generic name="latency_target" value="2" />
-- Retrieval info: <generic name="performance_goal" value="frequency" />
-- Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
-- Retrieval info: <generic name="faithful_rounding" value="false" />
-- Retrieval info: <generic name="gen_enable" value="false" />
-- Retrieval info: <generic name="divide_type" value="0" />
-- Retrieval info: <generic name="select_signal_enable" value="false" />
-- Retrieval info: <generic name="scale_by_pi" value="false" />
-- Retrieval info: <generic name="number_of_inputs" value="2" />
-- Retrieval info: <generic name="trig_no_range_reduction" value="false" />
-- Retrieval info: <generic name="report_resources_to_xml" value="false" />
-- Retrieval info: <generic name="fxpt_width" value="32" />
-- Retrieval info: <generic name="fxpt_fraction" value="0" />
-- Retrieval info: <generic name="fxpt_sign" value="1" />
-- Retrieval info: <generic name="fp_out_format" value="single" />
-- Retrieval info: <generic name="fp_out_exp" value="8" />
-- Retrieval info: <generic name="fp_out_man" value="23" />
-- Retrieval info: <generic name="fp_in_format" value="single" />
-- Retrieval info: <generic name="fp_in_exp" value="8" />
-- Retrieval info: <generic name="fp_in_man" value="23" />
-- Retrieval info: <generic name="enable_hard_fp" value="true" />
-- Retrieval info: <generic name="manual_dsp_planning" value="true" />
-- Retrieval info: <generic name="forceRegisters" value="1111" />
-- Retrieval info: <generic name="selected_device_family" value="MAX 10" />
-- Retrieval info: <generic name="selected_device_speedgrade" value="6" />
-- Retrieval info: </instance>
-- IPFS_FILES : fp_cmp_gt.vho
-- RELATED_FILES: fp_cmp_gt.vhd, dspba_library_package.vhd, dspba_library.vhd, fp_cmp_gt_0002.vhd
|
mit
|
ddebbdd77fcaa08b160ef01f9abe994c
| 0.642359 | 3.464664 | false | false | false | false |
nanomolina/MIPS
|
prueba/MEM_WB.vhd
| 1 | 957 |
library ieee;
use ieee.std_logic_1164.all;
entity MEM_WB is
port (
AluOut_in : in std_logic_vector(31 downto 0);
ReadData_in : in std_logic_vector(31 downto 0);
WriteReg_in : in std_logic_vector(4 downto 0);
RegWrite_in: in std_logic;
MemToReg_in: in std_logic;
clk : in std_logic;
RegWrite_out: out std_logic;
MemToReg_out: out std_logic;
AluOut_out : out std_logic_vector(31 downto 0);
ReadData_out : out std_logic_vector(31 downto 0);
WriteReg_out : out std_logic_vector(4 downto 0)
);
end entity;
architecture BH of MEM_WB is
begin
process (clk) begin
if (clk'event and clk = '1') then
RegWrite_out <= RegWrite_in;
MemToReg_out <= MemToReg_in;
AluOut_out <= AluOut_in;
ReadData_out <= ReadData_in;
WriteReg_out <= WriteReg_in;
end if;
end process;
end BH;
|
gpl-3.0
|
42bd0867bead14d974f7d9b6e3ce3bdd
| 0.575758 | 3.638783 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/machine/sirius_bo_250M/machine_pkg.vhd
| 1 | 4,437 |
-------------------------------------------------------------------------------
-- Title : Machine parameters for Sirius with 250MSps ADC
-- Project :
-------------------------------------------------------------------------------
-- File : machine_pkg.vhd<sirius_250M>
-- Author : <aylons@dig-jobs>
-- Company :
-- Created : 2016-04-04
-- Last update: 2016-04-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Machine parameters for Sirius with 250MSps ADC
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-04 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package machine_pkg is
constant c_pos_calc_with_downconv : boolean := true;
constant c_pos_calc_adc_freq : real := 221.644e6;
constant c_pos_calc_input_width : natural := 16;
constant c_pos_calc_mixed_width : natural := 16;
constant c_pos_calc_adc_ratio : natural := 1;
constant c_pos_calc_dds_width : natural := 16;
constant c_pos_calc_dds_points : natural := 181;
constant c_pos_calc_sin_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_sin.nif";
constant c_pos_calc_cos_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_cos.nif";
constant c_pos_calc_tbt_cic_delay : natural := 1;
constant c_pos_calc_tbt_cic_stages : natural := 1;
constant c_pos_calc_tbt_ratio : natural := 362;
constant c_pos_calc_tbt_decim_width : natural := 32;
constant c_pos_calc_fofb_cic_delay : natural := 1;
constant c_pos_calc_fofb_cic_stages : natural := 1;
constant c_pos_calc_fofb_ratio : natural := 8688;
constant c_pos_calc_fofb_decim_width : natural := 32;
constant c_pos_calc_monit1_cic_delay : natural := 1;
constant c_pos_calc_monit1_cic_stages : natural := 1;
constant c_pos_calc_monit1_ratio : natural := 25; --ratio between fofb and monit 1
constant c_pos_calc_monit1_cic_ratio : natural := 8;
constant c_pos_calc_monit2_cic_delay : natural := 1;
constant c_pos_calc_monit2_cic_stages : natural := 1;
constant c_pos_calc_monit2_ratio : natural := 100; -- ratio between monit 1 and 2
constant c_pos_calc_monit2_cic_ratio : natural := 8;
constant c_pos_calc_monit_decim_width : natural := 32;
constant c_pos_calc_tbt_cordic_stages : positive := 12;
constant c_pos_calc_tbt_cordic_iter_per_clk : positive := 3;
constant c_pos_calc_tbt_cordic_ratio : positive := 8;
constant c_pos_calc_fofb_cordic_stages : positive := 15;
constant c_pos_calc_fofb_cordic_iter_per_clk : positive := 3;
constant c_pos_calc_fofb_cordic_ratio : positive := 8;
constant c_pos_calc_k_width : natural := 25;
constant c_pos_calc_offset_width : natural := 32;
constant c_pos_calc_IQ_width : natural := c_pos_calc_mixed_width;
constant c_pos_calc_k_sum : natural := 85e5;
constant c_pos_calc_k_x : natural := 85e5;
constant c_pos_calc_k_y : natural := 85e5;
end machine_pkg;
|
lgpl-3.0
|
724534974ec2bc6010cb978fa6805ad2
| 0.54316 | 3.937001 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/testbench/fixed_dds/dds_bench.vhd
| 1 | 4,742 |
-------------------------------------------------------------------------------
-- Title : Fixed DDS testbench
-- Project :
-------------------------------------------------------------------------------
-- File : dds_bench.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2015-03-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Testbench for the fixed-frequency DDS
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dds_bench is
end entity dds_bench;
architecture test of dds_bench is
constant input_freq : real := 1.1742939e08;
constant sw_freq : real := input_freq/1000.0;
constant clock_period : time := 1.0 sec /(2.0*input_freq);
constant cycles_to_reset : natural := 4;
constant data_width : natural := 16;
constant number_of_points : natural := 35;
constant c_phase_bus_size : natural := 0;
-- constant sin_file : string := "./dds_sin.nif";
-- constant cos_file : string := "./dds_cos.nif";
signal clock : std_logic := '0';
signal rst_n : std_logic := '0';
signal ce : std_logic := '1';
signal cur_phase : signed(c_phase_bus_size-1 downto 0) := (others => '0');
constant phase_delay : natural := 1;
type delay_line_type is array (phase_delay downto 0) of std_logic_vector(c_phase_bus_size-1 downto 0);
signal delayed_cur_phase : delay_line_type := (others => (others => '0'));
signal delayed_cur_sample : delay_line_type := (others => (others => '0'));
signal sin_out : std_logic_vector(data_width-1 downto 0);
signal cos_out : std_logic_vector(data_width-1 downto 0);
component fixed_dds is
generic (
g_number_of_points : natural;
g_output_width : natural;
g_phase_bus_size : natural;
g_sin_file : string;
g_cos_file : string);
port (
clk_i : in std_logic;
ce_i : in std_logic;
rst_n_i : in std_logic;
phase_sel_i : in std_logic_vector(g_phase_bus_size-1 downto 0);
sin_o : out std_logic_vector(g_output_width-1 downto 0);
cos_o : out std_logic_vector(g_output_width-1 downto 0));
end component fixed_dds;
begin
clk_gen : process
begin
clock <= '0';
wait for clock_period;
clock <= '1';
wait for clock_period;
end process;
rst_gen : process(clock)
variable clock_count : natural := cycles_to_reset;
begin
if rising_edge(clock) and clock_count /= 0 then
clock_count := clock_count - 1;
if clock_count = 0 then
rst_n <= '1';
end if;
end if;
end process;
varying_phase : process(clock)
variable cur_sample : natural range 0 to number_of_points := 0;
file ouput_file : text open write_mode is "dds_out.samples";
variable cur_line : line;
begin
if rising_edge(clock) then
if rst_n = '0' then
cur_sample := 0;
cur_phase <= (others => '0');
else
if cur_sample = number_of_points-1 then
cur_sample := 0;
cur_phase <= cur_phase + to_signed(1, c_phase_bus_size);
else
cur_sample := cur_sample+1;
end if;
for n in phase_delay downto 1 loop
delayed_cur_phase(n) <= delayed_cur_phase(n-1);
delayed_cur_sample(n) <= delayed_cur_sample(n-1);
end loop;
delayed_cur_sample(0) <= std_logic_vector(to_signed(cur_sample, c_phase_bus_size));
delayed_cur_phase(0) <= std_logic_vector(cur_phase);
end if; --rst_n = '0'
end if;
end process;
uut : fixed_dds
generic map (
g_number_of_points => number_of_points,
g_output_width => data_width,
g_phase_bus_size => c_phase_bus_size,
g_sin_file => sin_file,
g_cos_file => cos_file)
port map (
clk_i => clock,
ce_i => ce,
rst_n_i => rst_n,
phase_sel_i => std_logic_vector(cur_phase),
sin_o => sin_out,
cos_o => cos_out);
end architecture test;
|
lgpl-3.0
|
d5a8c619bd9a77bb1e7bfd146e537aad
| 0.510122 | 3.586989 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_clk_ddr_s8_se.vhd
| 1 | 8,906 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_ddr_s8_se.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n DDR clock receiver module for serdes factors from 2 to 8 with differential inputs
-- Instantiates necessary BUFIO2 clock buffers
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_clk_ddr_s8_se is generic (
S : integer := 8) ; -- Parameter to set the serdes factor 1..8
port (
clkin1 : in std_logic ; -- Input from se receiver pin
clkin2 : in std_logic ; -- Input from se receiver pin
rxioclkp : out std_logic ; -- IO Clock network
rxioclkn : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_x1 : out std_logic) ; -- Global clock
end serdes_1_to_n_clk_ddr_s8_se ;
architecture arch_serdes_1_to_n_clk_ddr_s8_se of serdes_1_to_n_clk_ddr_s8_se is
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal rx_clk_in : std_logic; --
signal iob_data_in_p : std_logic; --
signal iob_data_in_n : std_logic; --
signal rx_clk_in_p : std_logic; --
signal rx_clk_in_n : std_logic; --
signal rx_bufio2_x1 : std_logic; --
constant RX_SWAP_CLK : std_logic := '0' ; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
iob_clk_in1 : IBUFG port map (
I => clkin1,
O => rx_clk_in_p) ;
iob_clk_in2 : IBUFG port map (
I => clkin2,
O => rx_clk_in_n) ;
iob_data_in_p <= rx_clk_in_p xor RX_SWAP_CLK ; -- Invert clock as required
iob_data_in_n <= not rx_clk_in_n xor RX_SWAP_CLK ; -- Invert clock as required, remembering the 2nd parallle clock input needs to be inverted
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 49, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in_p, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line to 1/2 max in this case
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 49, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in_n, -- data from slave IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate control signal, never needed as the slave supplies the clock input to the PLL
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
bufg_pll_x1 : BUFG port map (I => rx_bufio2_x1, O => rx_bufg_x1) ;
bufio2_2clk_inst : BUFIO2_2CLK generic map(
DIVIDE => S) -- The DIVCLK divider divide-by value; default 1
port map (
I => ddly_m, -- Input source clock 0 degrees
IB => ddly_s, -- Input source clock 0 degrees
IOCLK => rxioclkp, -- Output Clock for IO
DIVCLK => rx_bufio2_x1, -- Output Divided Clock
SERDESSTROBE => rx_serdesstrobe) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst : BUFIO2 generic map(
I_INVERT => FALSE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => FALSE) --
port map (
I => ddly_s, -- N_clk input from IDELAY
IOCLK => rxioclkn, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
end arch_serdes_1_to_n_clk_ddr_s8_se ;
|
apache-2.0
|
9db42ea1f8bcc2c09897633af8cf2dfb
| 0.587694 | 3.376042 | false | false | false | false |
nanomolina/MIPS
|
prueba/pipeline_tb.vhd
| 2 | 1,102 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pipeline_tb is
end entity;
architecture TB of pipeline_tb is
component pipeline
port(
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic
);
end component;
signal pc, instr: std_logic_vector(31 downto 0);
signal dump, reset, clk: std_logic;
begin
dut: pipeline port map(
dump => dump,
pc => pc,
instr => instr,
reset => reset,
clk => clk
);
process begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;
process begin
--01094020 (add $t0 $t0 $t1)
--en binario:
--0000 0001 0000 1001 0100 0000 0010 0000
dump <= '0';
reset <= '1';
wait for 20 ns;
reset <= '0';
wait for 170 ns;
dump <= '1';
wait for 30 ns;
dump <= '0';
end process;
-- process begin
-- wait for 170 ns;
-- dump <= '1';
-- wait for ns;
-- dump <= '0';
-- end process;
end TB;
|
gpl-3.0
|
b35a8afa9913180c6a95dde215581c7c
| 0.601633 | 2.707617 | false | false | false | false |
nanomolina/MIPS
|
DATAPATH/datapath.vhd
| 1 | 3,065 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.components.all;
entity datapath is
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
AluSrc : in std_logic;
RegDst : in std_logic;
RegWrite : in std_logic;
Jump : in std_logic;
AluControl : in std_logic_vector(2 downto 0);
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic
);
end entity;
architecture BH of datapath is
signal DUMPS, PCSrc, ZEROs : std_logic;
signal PC1, PCNext, PC_T, PCOut, INSTRUCTION,
PCPlus4, SrcA, PCJump, QUATRO,
PCBranch, SignImm, SrcB, Result,
RD1, RD2, AD1, AD2, ReadData, WriteData, ALUResult : std_logic_vector(31 downto 0);
signal SIGNIN : std_logic_vector(15 downto 0);
signal A1, A2, A3, IMEMIN : std_logic_vector(5 downto 0);
signal instr5_1, instr5_2, instr5_3, instr5_4, WriteReg : std_logic_vector(4 downto 0);
begin
ADDER1: adder port map(
a => PCOut,
b => QUATRO,
y => PCPlus4
);
ADDER2: adder port map(
a => AD1 ,
b => PCPlus4,
y => PCBranch
);
FLOPR1: flopr port map(
d => PC1 ,
rst => reset,
clk => clk,
q => PCOut
);
MUX2_1: mux2 port map(
d0 => PCPlus4,
d1 => PCBranch,
s => PCSrc,
y => PCNext
);
MUX2_2: mux2 port map(
d0 => PCNext,
d1 => PCJump,
s => Jump,
y => PC1
);
MUX2_3: mux2 port map(
d0 => WriteData,
d1 => SignImm,
s => AluSrc,
y => SrcB
);
MUX2_4: mux2 port map(
d0 => ALUResult,
d1 => ReadData,
s => MemToReg,
y => Result
);
MUX2_5: mux2 generic map(
MAX => 5
)
port map(
d0 => instr5_1,
d1 => instr5_2,
s => RegDst,
y => WriteReg
);
IMEM1: imem port map(
a => IMEMIN,
rd => INSTRUCTION
);
REGFILE1: regfile port map(
ra1 => instr5_3,
ra2 => instr5_4,
wa3 => WriteReg,
wd3 => Result,
we3 => RegWrite,
clk => clk,
rd1 => SrcA,
rd2 => WriteData
);
SIGNEXT: sign port map(
a => SIGNIN,
y => SignImm
);
ALU1: alu port map(
a => SrcA,
b => SrcB,
alucontrol => AluControl,
result => ALUResult,
zero => ZEROs
);
SL2a: sl2 port map(
a => SignImm,
y => AD1
);
DMEM1: dmem port map(
a => ALUResult,
wd => WriteData,
clk => clk,
we => MemWrite,
rd => ReadData,
dump => DUMPS
);
QUATRO <= x"00000004"; --REVISAR!!!
PCJump <= PCPlus4(31 downto 28) & INSTRUCTION(25 downto 0) & "00";
PCSrc <= Branch and ZEROs;
IMEMIN <= PCOut(7 downto 2);
instr5_1 <= INSTRUCTION(20 downto 16);
instr5_2 <= INSTRUCTION(15 downto 11);
instr5_3 <= INSTRUCTION(25 downto 21);
instr5_4 <= INSTRUCTION(20 downto 16);
SIGNIN <= INSTRUCTION(15 downto 0);
instr <= INSTRUCTION;
pc <= PCOut;
end architecture;
|
gpl-3.0
|
f212c0922bf3f723316d53789e6d4e5c
| 0.546166 | 2.902462 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/ps2/ps2core.vhd
| 1 | 8,134 |
-- Core of PS2 driver
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ps2core is
port(
clk: in std_logic;
res: in std_logic;
byte_out: out unsigned(7 downto 0);
byte_recieved: out std_logic;
ps2clk: in std_logic;
ps2dat: in std_logic
);
end entity ps2core;
architecture ps2core_arch of ps2core is
type statetype is (
idle, start_bit, wait0, sample0, wait1, sample1, wait2, sample2, wait3, sample3,
wait4, sample4, wait5, sample5, wait6, sample6, wait7, sample7, wait_parity, sample_parity, interrupt
);
signal ps2_state: statetype;
signal ps2clk_synch, ps2dat_synch: std_logic;
signal sample_dat: std_logic;
signal ps2clk_fall: std_logic;
begin
process(clk, res, ps2clk, ps2dat) is
variable ps2clk_var: std_logic_vector(1 downto 0);
variable ps2dat_var: std_logic_vector(1 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
ps2clk_var := "11";
ps2dat_var := "11";
else
ps2dat_var(1) := ps2dat_var(0);
ps2dat_var(0) := ps2dat;
ps2clk_var(1) := ps2clk_var(0);
ps2clk_var(0) := ps2clk;
end if;
end if;
ps2clk_synch <= ps2clk_var(1);
ps2dat_synch <= ps2dat_var(1);
end process;
sipo_shift_reg:
process(clk, res, ps2dat_synch, sample_dat) is
variable data_reg: unsigned(8 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
data_reg := (others => '0');
elsif sample_dat = '1' then
data_reg(7 downto 0) := data_reg(8 downto 1);
data_reg(8) := ps2dat_synch;
end if;
end if;
byte_out <= data_reg(7 downto 0);
end process;
ps2clk_fall_detec:
process(clk, res, ps2clk_synch) is
variable counter: std_logic_vector(1 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
counter := "00";
else
counter(1) := counter(0);
counter(0) := ps2clk_synch;
end if;
end if;
ps2clk_fall <= counter(1) and not(counter(0));
end process;
FSM_transit_functions:
process(clk, res, ps2dat_synch, ps2clk_fall) is
begin
if rising_edge(clk) then
if res = '1' then
ps2_state <= idle;
else
case ps2_state is
when idle =>
if ps2clk_fall = '1' and ps2dat_synch = '0' then
ps2_state <= start_bit;
else
ps2_state <= idle;
end if;
when start_bit =>
ps2_state <= wait0;
when wait0 =>
if ps2clk_fall = '1' then
ps2_state <= sample0;
else
ps2_state <= wait0;
end if;
when sample0 =>
ps2_state <= wait1;
when wait1 =>
if ps2clk_fall = '1' then
ps2_state <= sample1;
else
ps2_state <= wait1;
end if;
when sample1 =>
ps2_state <= wait2;
when wait2 =>
if ps2clk_fall = '1' then
ps2_state <= sample2;
else
ps2_state <= wait2;
end if;
when sample2 =>
ps2_state <= wait3;
when wait3 =>
if ps2clk_fall = '1' then
ps2_state <= sample3;
else
ps2_state <= wait3;
end if;
when sample3 =>
ps2_state <= wait4;
when wait4 =>
if ps2clk_fall = '1' then
ps2_state <= sample4;
else
ps2_state <= wait4;
end if;
when sample4 =>
ps2_state <= wait5;
when wait5 =>
if ps2clk_fall = '1' then
ps2_state <= sample5;
else
ps2_state <= wait5;
end if;
when sample5 =>
ps2_state <= wait6;
when wait6 =>
if ps2clk_fall = '1' then
ps2_state <= sample6;
else
ps2_state <= wait6;
end if;
when sample6 =>
ps2_state <= wait7;
when wait7 =>
if ps2clk_fall = '1' then
ps2_state <= sample7;
else
ps2_state <= wait7;
end if;
when sample7 =>
ps2_state <= wait_parity;
when wait_parity =>
if ps2clk_fall = '1' then
ps2_state <= sample_parity;
else
ps2_state <= wait_parity;
end if;
when sample_parity =>
ps2_state <= interrupt;
when interrupt =>
ps2_state <= idle;
end case;
end if;
end if;
end process;
FSM_output_functions:
process(ps2_state) is
begin
case ps2_state is
when idle => byte_recieved <= '0'; sample_dat <= '0';
when start_bit => byte_recieved <= '0'; sample_dat <= '0';
when wait0 => byte_recieved <= '0'; sample_dat <= '0';
when sample0 => byte_recieved <= '0'; sample_dat <= '1';
when wait1 => byte_recieved <= '0'; sample_dat <= '0';
when sample1 => byte_recieved <= '0'; sample_dat <= '1';
when wait2 => byte_recieved <= '0'; sample_dat <= '0';
when sample2 => byte_recieved <= '0'; sample_dat <= '1';
when wait3 => byte_recieved <= '0'; sample_dat <= '0';
when sample3 => byte_recieved <= '0'; sample_dat <= '1';
when wait4 => byte_recieved <= '0'; sample_dat <= '0';
when sample4 => byte_recieved <= '0'; sample_dat <= '1';
when wait5 => byte_recieved <= '0'; sample_dat <= '0';
when sample5 => byte_recieved <= '0'; sample_dat <= '1';
when wait6 => byte_recieved <= '0'; sample_dat <= '0';
when sample6 => byte_recieved <= '0'; sample_dat <= '1';
when wait7 => byte_recieved <= '0'; sample_dat <= '0';
when sample7 => byte_recieved <= '0'; sample_dat <= '1';
when wait_parity => byte_recieved <= '0'; sample_dat <= '0';
when sample_parity => byte_recieved <= '0'; sample_dat <= '1';
when interrupt => byte_recieved <= '1'; sample_dat <= '0';
end case;
end process;
end architecture ps2core_arch;
|
mit
|
582f8e77fd70b5162775da091f40b7c0
| 0.400467 | 4.356186 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/hpf_adcinput/mac1reg.vhd
| 1 | 3,817 |
------------------------------------------------------------------------------
-- Title : DSP48E1-based MAC and data registered data propagation (1 stage)
------------------------------------------------------------------------------
-- Author : Daniel Tavares
-- Company : CNPEM LNLS-DIG
-- Created : 2019-11-23
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Elementary mulitply-accumulate block for systolic FIR filter
-- implementation. Use 1 pipeline stage at the input data.
-- Reference: "DSP: Designing for Optimal Results"
-------------------------------------------------------------------------------
-- Copyright (c) 2019 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-11-23 1.0 daniel.tavares Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity mac1reg is
port
(
clk_i : in std_logic;
data_i : in std_logic_vector (17 downto 0);
coef_i : in std_logic_vector (24 downto 0);
data_o : out std_logic_vector (17 downto 0);
mac_o : out std_logic_vector (47 downto 0);
casc_o : out std_logic_vector (47 downto 0)
);
end mac1reg;
architecture rtl of mac1reg is
signal coef : std_logic_vector(29 downto 0);
begin
DSP48E1_inst : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT",
B_INPUT => "DIRECT",
USE_DPORT => FALSE,
USE_MULT => "MULTIPLY",
USE_SIMD => "ONE48",
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET",
MASK => X"3fffffffffff",
PATTERN => X"000000000000",
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_PATTERN_DETECT => "NO_PATDET",
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 1,
AREG => 1,
BCASCREG => 1,
BREG => 1,
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MREG => 1,
OPMODEREG => 0,
PREG => 1
)
port map (
CLK => clk_i,
A => coef,
B => data_i,
BCOUT => data_o,
PCOUT => casc_o,
P => mac_o,
BCIN => (others => '0'),
PCIN => (others => '0'),
INMODE => "10001",
OPMODE => "0000101",
ALUMODE => "0000",
-- Reset/Clock Enable Inputs
CEA1 => '1',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '1',
CEB1 => '1',
CEB2 => '1',
CEC => '0',
CECARRYIN => '0',
CECTRL => '1',
CED => '0',
CEINMODE => '0',
CEM => '1',
CEP => '1',
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
-- Unused port
ACOUT => open,
CARRYCASCOUT => open,
MULTSIGNOUT => open,
OVERFLOW => open,
PATTERNBDETECT => open,
PATTERNDETECT => open,
UNDERFLOW => open,
CARRYOUT => open,
ACIN => (others => '0'),
CARRYCASCIN => '0',
MULTSIGNIN => '0',
CARRYINSEL => "000",
C => (others => '0'),
CARRYIN => '0',
D => (others => '0')
);
-- Sign extension - DSP48E1 expects 30 bits on port A but multiplier uses only 25 bits
coef(24 downto 0) <= coef_i;
coef(29 downto 25) <= (others => coef_i(24));
end rtl;
|
lgpl-3.0
|
900c3f4881a706b001583117dd5b5aba
| 0.481792 | 4.01367 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/hierarchy/UnitWithParams_in_wrap.vhd
| 1 | 2,006 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY UnitWithParams_0 IS
GENERIC(
DATA_WIDTH : INTEGER := 64
);
PORT(
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_vld : IN STD_LOGIC;
dout_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dout_vld : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF UnitWithParams_0 IS
BEGIN
dout_data <= din_data;
dout_vld <= din_vld;
ASSERT DATA_WIDTH = 64 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY UnitWithParams IS
PORT(
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_vld : IN STD_LOGIC;
dout_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dout_vld : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF UnitWithParams IS
--
-- .. hwt-autodoc::
--
COMPONENT UnitWithParams_0 IS
GENERIC(
DATA_WIDTH : INTEGER := 64
);
PORT(
din_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
din_vld : IN STD_LOGIC;
dout_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
dout_vld : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL sig_baseUnit_din_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_baseUnit_din_vld : STD_LOGIC;
SIGNAL sig_baseUnit_dout_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_baseUnit_dout_vld : STD_LOGIC;
BEGIN
baseUnit_inst: UnitWithParams_0 GENERIC MAP(
DATA_WIDTH => 64
) PORT MAP(
din_data => sig_baseUnit_din_data,
din_vld => sig_baseUnit_din_vld,
dout_data => sig_baseUnit_dout_data,
dout_vld => sig_baseUnit_dout_vld
);
dout_data <= sig_baseUnit_dout_data;
dout_vld <= sig_baseUnit_dout_vld;
sig_baseUnit_din_data <= din_data;
sig_baseUnit_din_vld <= din_vld;
END ARCHITECTURE;
|
mit
|
306903e28f35cd8984cdaab6562dbc56
| 0.60319 | 3.470588 | false | false | false | false |
nanomolina/MIPS
|
prueba/execute.vhd
| 2 | 2,329 |
library ieee;
use ieee.std_logic_1164.all;
entity execute is
port(
RD1E, RD2E, PCPlus4E, SignImmE: in std_logic_vector(31 downto 0);
RtE, RdE: in std_logic_vector(4 downto 0);
RegDst, AluSrc: in std_logic;
AluControl: in std_logic_vector(2 downto 0);
WriteRegE: out std_logic_vector(4 downto 0);
ZeroE: out std_logic;
AluOutE, WriteDataE, PCBranchE: out std_logic_vector(31 downto 0));
end entity;
architecture e_arq of execute is
component adder
port (
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
y : out std_logic_vector(31 downto 0));
end component;
component mux2
generic (MAX : integer := 32);
port (
d0, d1: in std_logic_vector((MAX-1) downto 0);
s: in std_logic;
y: out std_logic_vector((MAX-1) downto 0));
end component;
component sl2
port (
a: in std_logic_vector (31 downto 0);
y: out std_logic_vector (31 downto 0));
end component;
component alu
port (
a, b: in std_logic_vector(31 downto 0);
alucontrol: in std_logic_vector(2 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic);
end component;
signal sl2_out: std_logic_vector(31 downto 0);
signal SrcBE: std_logic_vector(31 downto 0);
begin
mux2_1: mux2 generic map (MAX=>5) port map (d0=>RtE,
d1=>RdE,
s=>RegDst,
y=>WriteRegE); --salida
sl21: sl2 port map(
a => SignImmE,
y => sl2_out);
adder1: adder port map(
a => sl2_out,
b => PCPlus4E,
y => PCBranchE); --salida
mux2_21: mux2 port map(
d0 => RD2E,
d1 => SignImmE,
s => AluSrc,
y => SrcBE);
WriteDataE <= RD2E; --salida
Alu1: alu port map(
a => RD1E,
b => SrcBE,
alucontrol => AluControl,
result => AluOutE, --salida
zero => ZeroE); --salida
end architecture;
|
gpl-3.0
|
24a0e50b74eee8fb8e7b2b8e7cc6f74b
| 0.492486 | 3.981197 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_data_ddr_s8_diff.vhd
| 1 | 16,555 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_data_ddr_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic 1:n data receiver module with differential inputs for DDR systems
-- Takes in 1 bit of differential data and deserialises this to n bits
-- data is received LSB first
-- Serial input words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line(D) : D-1, ...... DS
-- Parallel output word
-- DS, DS-1 ..... 1, 0
--
-- Includes state machine to control calibration only
-- Data inversion can be accomplished via the RX_RX_SWAP_MASK parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_data_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16 ; -- Set the number of inputs and outputs
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
use_phase_detector : in std_logic ; -- '1' enables the phase detector logic if USE_PD = TRUE
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclkp : in std_logic ; -- IO Clock network
rxioclkn : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug_in : in std_logic_vector(1 downto 0) ; -- Debug Inputs, set to '0' if not required
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug output bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end serdes_1_to_n_data_ddr_s8_diff ;
architecture arch_serdes_1_to_n_data_ddr_s8_diff of serdes_1_to_n_data_ddr_s8_diff is
signal ddly_m : std_logic_vector(D-1 downto 0) ; -- Master output from IODELAY1
signal ddly_s : std_logic_vector(D-1 downto 0) ; -- Slave output from IODELAY1
signal mdataout : std_logic_vector((8*D)-1 downto 0) ;
signal cascade : std_logic_vector(D-1 downto 0) ;
signal pd_edge : std_logic_vector(D-1 downto 0) ;
signal busys : std_logic_vector(D-1 downto 0) ;
signal busym : std_logic_vector(D-1 downto 0) ;
signal rx_data_in : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_fix : std_logic_vector(D-1 downto 0) ;
signal state : integer range 0 to 8 ;
signal busy_data_d : std_logic ;
signal busy_data : std_logic_vector(D-1 downto 0) ;
signal inc_data : std_logic ;
signal ce_data : std_logic_vector(D-1 downto 0) ;
signal incdec_data_d : std_logic ;
signal valid_data_d : std_logic ;
signal counter : std_logic_vector(8 downto 0) ;
signal enable : std_logic ;
signal cal_data_master : std_logic ;
signal rst_data : std_logic ;
signal pdcounter : std_logic_vector(4 downto 0) ;
signal ce_data_int : std_logic_vector(D-1 downto 0) ;
signal inc_data_int : std_logic ;
signal incdec_data : std_logic_vector(D-1 downto 0) ;
signal cal_data_slave : std_logic ;
signal valid_data : std_logic_vector(D-1 downto 0) ;
signal mux : std_logic_vector(D-1 downto 0) ;
signal ce_data_inta : std_logic ;
signal flag : std_logic ;
signal cal_data_sint : std_logic ;
signal incdec_data_or : std_logic_vector(D downto 0) ;
signal incdec_data_im : std_logic_vector(D-1 downto 0) ;
signal valid_data_or : std_logic_vector(D downto 0) ;
signal valid_data_im : std_logic_vector(D-1 downto 0) ;
signal busy_data_or : std_logic_vector(D downto 0) ;
signal all_ce : std_logic_vector(D-1 downto 0) ;
constant RX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
cal_data_slave <= cal_data_sint ;
debug <= mux & cal_data_master & rst_data & cal_data_slave & busy_data_d & inc_data & ce_data & valid_data_d & incdec_data_d ;
process (gclk, reset)
begin
if reset = '1' then
state <= 0 ;
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
counter <= (others => '0') ;
enable <= '0' ;
counter <= (others => '0') ;
mux <= (0 => '1', others => '0') ;
elsif gclk'event and gclk = '1' then
counter <= counter + 1 ;
if counter(8) = '1' then
counter <= "000000000" ;
end if ;
if counter(5) = '1' then
enable <= '1' ;
end if ;
if state = 0 and enable = '1' then -- Wait for all IODELAYs to be available
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 1 ;
end if ;
elsif state = 1 then -- Issue calibrate command to both master and slave
cal_data_master <= '1' ;
cal_data_sint <= '1' ;
if busy_data_d = '1' then -- and wait for command to be accepted
state <= 2 ;
end if ;
elsif state = 2 then -- Now RST all master and slave IODELAYs
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
if busy_data_d = '0' then
rst_data <= '1' ;
state <= 3 ;
end if ;
elsif state = 3 then -- Wait for all IODELAYs to be available
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
elsif state = 4 then -- Hang around
if counter(8) = '1' then
state <= 5 ;
end if ;
elsif state = 5 then -- Calibrate slave only
if busy_data_d = '0' then
cal_data_sint <= '1' ;
state <= 6 ;
if D /= 1 then
mux <= mux(D-2 downto 0) & mux(D-1) ;
end if ;
end if ;
elsif state = 6 then -- Wait for command to be accepted
if busy_data_d = '1' then
cal_data_sint <= '0' ;
state <= 7 ;
end if ;
elsif state = 7 then -- Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
end if ;
end if ;
end process ;
process (gclk, reset)
begin
if reset = '1' then
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
flag <= '0' ;
elsif gclk'event and gclk = '1' then
busy_data_d <= busy_data_or(D) ;
if use_phase_detector = '1' then -- decide whther pd is used
incdec_data_d <= incdec_data_or(D) ;
valid_data_d <= valid_data_or(D) ;
if ce_data_inta = '1' then
ce_data <= mux ;
else
ce_data <= (others => '0') ;
end if ;
if state = 7 then
flag <= '0' ;
elsif state /= 4 or busy_data_d = '1' then -- Reset filter if state machine issues a cal command or unit is busy
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
elsif pdcounter = "11111" and flag = '0' then -- Filter has reached positive max - increment the tap count
ce_data_inta <= '1' ;
inc_data_int <= '1' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif pdcounter = "00000" and flag = '0' then -- Filter has reached negative max - decrement the tap count
ce_data_inta <= '1' ;
inc_data_int <= '0' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif valid_data_d = '1' then -- increment filter
ce_data_inta <= '0' ;
if incdec_data_d = '1' and pdcounter /= "11111" then
pdcounter <= pdcounter + 1 ;
elsif incdec_data_d = '0' and pdcounter /= "00000" then -- decrement filter
pdcounter <= pdcounter - 1 ;
end if ;
else
ce_data_inta <= '0' ;
end if ;
else
ce_data <= all_ce ;
inc_data_int <= debug_in(1) ;
end if ;
end if ;
end process ;
inc_data <= inc_data_int ;
incdec_data_or(0) <= '0' ; -- Input Mux - Initialise generate loop OR gates
valid_data_or(0) <= '0' ;
busy_data_or(0) <= '0' ;
loop0 : for i in 0 to (D - 1) generate
busy_data(i) <= busys(i) ;
incdec_data_im(i) <= incdec_data(i) and mux(i) ; -- Input muxes
incdec_data_or(i+1) <= incdec_data_im(i) or incdec_data_or(i) ; -- AND gates to allow just one signal through at a tome
valid_data_im(i) <= valid_data(i) and mux(i) ; -- followed by an OR
valid_data_or(i+1) <= valid_data_im(i) or valid_data_or(i) ; -- for the three inputs from each PD
busy_data_or(i+1) <= busy_data(i) or busy_data_or(i) ; -- The busy signals just need an OR gate
all_ce(i) <= debug_in(0) ;
rx_data_in_fix(i) <= rx_data_in(i) xor RX_SWAP_MASK(i) ; -- Invert signals as required
iob_clk_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => datain_p(i),
IB => datain_n(i),
O => rx_data_in(i));
iodelay_m : IODELAY2 generic map(
DATA_RATE => "DDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclkp, -- High speed clock for calibration
IOCLK1 => rxioclkn, -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "DDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclkp, -- High speed clock for calibration
IOCLK1 => rxioclkn, -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_slave, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busys(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "DDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m(i),
CE0 => '1',
CLK0 => rxioclkp,
CLK1 => rxioclkn,
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => pd_edge(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open, -- are these the same as above? These were in Johns design
CFB0 => open,
CFB1 => open,
VALID => valid_data(i),
INCDEC => incdec_data(i),
SHIFTOUT => cascade(i));
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "DDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s(i),
CE0 => '1',
CLK0 => rxioclkp,
CLK1 => rxioclkn,
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => cascade(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+3),
Q3 => mdataout((8*i)+2),
Q2 => mdataout((8*i)+1),
Q1 => mdataout((8*i)+0),
DFB => open, -- are these the same as above? These were in Johns design
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge(i));
loop1 : for j in 7 downto (8-S) generate
data_out(((D*(j+S-8))+i)) <= mdataout((8*i)+j) ;
end generate ;
end generate ;
end arch_serdes_1_to_n_data_ddr_s8_diff ;
|
apache-2.0
|
c524d9cd9d24b2bd2a8dfae617d3a26d
| 0.592691 | 2.992048 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/hpf_adcinput/hpf_adcinput.vhd
| 1 | 4,311 |
------------------------------------------------------------------------------
-- Title : Systolic High Pass FIR Filter
------------------------------------------------------------------------------
-- Author : Daniel Tavares
-- Company : CNPEM LNLS-DIG
-- Created : 2019-11-23
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Systolic FIR for high pass filter.
-- Coefficients are calculated to meet the specification:
-- - Stopband norm. frequency: 0.04545
-- - Passband norm. frequency: 0.4545
-- - Attenuation at stopband: 60 dB
-- - Attenuation ripple at passband: +/- 0.1 dB
-------------------------------------------------------------------------------
-- Copyright (c) 2019 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-11-23 1.0 daniel.tavares Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity hpf_adcinput is
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
data_i : in std_logic_vector (15 downto 0);
data_o : out std_logic_vector (15 downto 0)
);
end hpf_adcinput;
architecture rtl of hpf_adcinput is
type t_coef is array(12 downto 0) of std_logic_vector(24 downto 0);
signal coef : t_coef;
type t_cascade is array(11 downto 0) of std_logic_vector(47 downto 0);
signal cascade : t_cascade;
type t_data_io is array(12 downto 0) of std_logic_vector(17 downto 0);
signal data : t_data_io;
signal data_full : std_logic_vector(47 downto 0);
component mac1reg is
port
(
clk_i : in std_logic;
data_i : in std_logic_vector (17 downto 0);
coef_i : in std_logic_vector (24 downto 0);
data_o : out std_logic_vector (17 downto 0);
mac_o : out std_logic_vector (47 downto 0);
casc_o : out std_logic_vector (47 downto 0)
);
end component;
component mac2reg is
port
(
clk_i : in std_logic;
data_i : in std_logic_vector (17 downto 0);
coef_i : in std_logic_vector (24 downto 0);
casc_i : in std_logic_vector (47 downto 0);
data_o : out std_logic_vector (17 downto 0);
mac_o : out std_logic_vector (47 downto 0);
casc_o : out std_logic_vector (47 downto 0)
);
end component;
signal data_se : std_logic_vector(17 downto 0);
signal data_int : std_logic_vector(data_o'range);
begin
coef <= (
0 => conv_std_logic_vector( 186968, 25),
1 => conv_std_logic_vector( 363532, 25),
2 => conv_std_logic_vector( 192469, 25),
3 => conv_std_logic_vector( -714736, 25),
4 => conv_std_logic_vector( -2294800, 25),
5 => conv_std_logic_vector( -3865066, 25),
6 => conv_std_logic_vector( 12250263, 25),
7 => conv_std_logic_vector( -3865066, 25),
8 => conv_std_logic_vector( -2294800, 25),
9 => conv_std_logic_vector( -714736, 25),
10 => conv_std_logic_vector( 192469, 25),
11 => conv_std_logic_vector( 363532, 25),
12 => conv_std_logic_vector( 186968, 25)
);
cmp_mac_first : mac1reg
port map
(
clk_i => clk_i,
data_i => data_se,
coef_i => coef(0),
data_o => data(0),
casc_o => cascade(0)
);
gen_mac_cascade : for i in 1 to 11 generate
cmp_mac : mac2reg
port map
(
clk_i => clk_i,
data_i => data(i-1),
coef_i => coef(i),
casc_i => cascade(i-1),
data_o => data(i),
mac_o => open,
casc_o => cascade(i)
);
end generate;
cmp_mac_last : mac2reg
port map
(
clk_i => clk_i,
data_i => data(11),
coef_i => coef(12),
casc_i => cascade(11),
data_o => open,
mac_o => data_full,
casc_o => open
);
data_se(15 downto 0) <= data_i;
data_se(17 downto 16) <= (others => data_i(15));
-- Truncate 7 MSB and 25 LSB to achieve better precision at the output
-- TODO: verify if this is the optimal solution
data_o <= data_full(40 downto 25);
end rtl;
|
lgpl-3.0
|
43033d57bca86e447f15e64ff5c5a8d8
| 0.528648 | 3.394488 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/machine/sirius_bo_250M/dds_cos_lut.vhd
| 1 | 2,363 |
-------------------------------------------------------------------------------
-- Title : Vivado DDS cos lut for SIRIUS 250M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_cos_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-04-15
-- Last update: 2016-04-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Temporary cosine lut for SIRIUS machine with 250M ADC generated
-- through Vivado.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-04 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
entity dds_cos_lut is
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end entity dds_cos_lut;
architecture str of dds_cos_lut is
component generic_rom
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
begin
cmp_cos_lut_sirius_52_181_1 : generic_rom
generic map (
g_data_width => 16,
g_size => 181,
g_init_file => "cos_lut_sirius_52_181.mif",
g_fail_if_file_not_found => true
)
port map (
rst_n_i => '1',
clk_i => clka,
a_i => addra,
q_o => douta
);
end architecture str;
|
lgpl-3.0
|
85146e45bf4c042d49be9339243933c7
| 0.404994 | 4.319927 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/rtlLvl/arithmetic/Counter.vhd
| 1 | 998 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Counter IS
PORT(
clk : IN STD_LOGIC;
en : IN STD_LOGIC;
rst : IN STD_LOGIC;
s_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF Counter IS
SIGNAL cnt : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"00";
SIGNAL cnt_next : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
assig_process_cnt: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
cnt <= X"00";
ELSE
cnt <= cnt_next;
END IF;
END IF;
END PROCESS;
assig_process_cnt_next: PROCESS(cnt, en)
VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
BEGIN
tmpCastExpr_0 := UNSIGNED(cnt) + UNSIGNED'(X"01");
IF en = '1' THEN
cnt_next <= STD_LOGIC_VECTOR(tmpCastExpr_0);
ELSE
cnt_next <= cnt;
END IF;
END PROCESS;
s_out <= cnt;
END ARCHITECTURE;
|
mit
|
f04a721fe9ca4cb69feb8bd2092460cd
| 0.547094 | 3.602888 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_n_to_1_ddr_s8_se.vhd
| 1 | 9,381 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_n_to_1_ddr_s8_se.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic DDR n:1 transmitter module
-- Takes in n bits of data and serialises this to 1 bit
-- data is transmitted LSB first. Single ended version
-- Parallel input word
-- DS, DS-1 ..... 1, 0
-- Serial output words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Data inversion can be accomplished via the TX_SWAP_MASK parameter if required
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_n_to_1_ddr_s8_se is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclkp : in std_logic ; -- IO Clock network
txioclkn : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout : out std_logic_vector(D-1 downto 0)) ; -- output
end serdes_n_to_1_ddr_s8_se ;
architecture arch_serdes_n_to_1_ddr_s8_se of serdes_n_to_1_ddr_s8_se is
signal cascade_di : std_logic_vector(D-1 downto 0) ;
signal cascade_do : std_logic_vector(D-1 downto 0) ;
signal cascade_ti : std_logic_vector(D-1 downto 0) ;
signal cascade_to : std_logic_vector(D-1 downto 0) ;
signal mdataina : std_logic_vector(D*8 downto 0) ;
signal mdatainb : std_logic_vector(D*4 downto 0) ;
signal tx_data_out : std_logic_vector(D downto 0) ;
constant TX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
loop0 : for i in 0 to (D - 1) generate
io_clk_out : obuf port map (
O => dataout(i),
I => tx_data_out(i));
loop1 : if (S > 4) generate -- Two oserdes are needed
loop2 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdataina((8*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "DDR", -- <SDR>, DDR
DATA_RATE_OT => "DDR", -- <SDR>, DDR
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclkp,
CLK1 => txioclkn,
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+7),
D3 => mdataina((8*i)+6),
D2 => mdataina((8*i)+5),
D1 => mdataina((8*i)+4),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- Dummy input in Master
SHIFTIN2 => '1', -- Dummy input in Master
SHIFTIN3 => cascade_do(i), -- Cascade output D data from slave
SHIFTIN4 => cascade_to(i), -- Cascade output T data from slave
SHIFTOUT1 => cascade_di(i), -- Cascade input D data to slave
SHIFTOUT2 => cascade_ti(i), -- Cascade input T data to slave
SHIFTOUT3 => open, -- Dummy output in Master
SHIFTOUT4 => open) ; -- Dummy output in Master
oserdes_s : OSERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "DDR", -- <SDR>, DDR
DATA_RATE_OT => "DDR", -- <SDR>, DDR
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => open,
OCE => '1',
CLK0 => txioclkp,
CLK1 => txioclkn,
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+3),
D3 => mdataina((8*i)+2),
D2 => mdataina((8*i)+1),
D1 => mdataina((8*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => cascade_di(i), -- Cascade input D from Master
SHIFTIN2 => cascade_ti(i), -- Cascade input T from Master
SHIFTIN3 => '1', -- Dummy input in Slave
SHIFTIN4 => '1', -- Dummy input in Slave
SHIFTOUT1 => open, -- Dummy output in Slave
SHIFTOUT2 => open, -- Dummy output in Slave
SHIFTOUT3 => cascade_do(i), -- Cascade output D data to Master
SHIFTOUT4 => cascade_to(i)) ; -- Cascade output T data to Master
end generate ;
loop3 : if (S < 5) generate -- Only one oserdes needed
loop4 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdatainb((4*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "DDR", -- <SDR>, DDR
DATA_RATE_OT => "DDR") -- <SDR>, DDR
-- SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
-- OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclkp,
CLK1 => txioclkn,
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdatainb((4*i)+3),
D3 => mdatainb((4*i)+2),
D2 => mdatainb((4*i)+1),
D1 => mdatainb((4*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- No cascades needed
SHIFTIN2 => '1', -- No cascades needed
SHIFTIN3 => '1', -- No cascades needed
SHIFTIN4 => '1', -- No cascades needed
SHIFTOUT1 => open, -- No cascades needed
SHIFTOUT2 => open, -- No cascades needed
SHIFTOUT3 => open, -- No cascades needed
SHIFTOUT4 => open) ; -- No cascades needed
end generate ;
end generate ;
end arch_serdes_n_to_1_ddr_s8_se ;
|
apache-2.0
|
31aa0cefb2c4bd4dbdaeb3b92cc37ca8
| 0.592794 | 3.137458 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/sdram/sdram.vhd
| 1 | 11,455 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
entity sdram is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
--bus interface
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
-- device specific interface
clk_sdram: in std_logic;
-- sdram interface
sdram_a: out std_logic_vector(12 downto 0);
sdram_ba: out std_logic_vector(1 downto 0);
sdram_dq: inout std_logic_vector(7 downto 0);
sdram_ras: out std_logic;
sdram_cas: out std_logic;
sdram_we: out std_logic
);
end entity sdram;
architecture rtl of sdram is
component sdram_driver
port(
clk_100: in std_logic;
res: in std_logic;
address: in std_logic_vector(22 downto 0);
data_in: in std_logic_vector(31 downto 0);
data_out: out std_logic_vector(31 downto 0);
busy: out std_logic;
wr_req: in std_logic;
rd_req: in std_logic;
data_out_ready: out std_logic;
ack: out std_logic;
sdram_ras_n: out std_logic;
sdram_cas_n: out std_logic;
sdram_we_n: out std_logic;
sdram_addr: out std_logic_vector(12 downto 0);
sdram_ba: out std_logic_vector(1 downto 0);
sdram_data: inout std_logic_vector(7 downto 0)
);
end component;
component dcfifo
generic (
lpm_numwords: natural;
lpm_showahead: string := "OFF";
lpm_width: natural;
lpm_widthu: natural := 1;
overflow_checking: string := "ON";
read_aclr_synch: string := "OFF";
underflow_checking: string := "ON";
use_eab: string := "ON";
write_aclr_synch: string := "OFF";
clocks_are_synchronized: string := "FALSE";
lpm_type: string := "dcfifo"
);
port(
aclr: in std_logic := '0';
data: in std_logic_vector(lpm_width-1 downto 0);
rdclk: in std_logic;
rdreq: in std_logic;
wrclk: in std_logic;
wrreq: in std_logic;
q: out std_logic_vector(lpm_width-1 downto 0);
rdempty: out std_logic;
wrempty: out std_logic
);
end component;
component bus_interface is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--fifos
wrfifo_datain: out std_logic_vector(54 downto 0);
wrfifo_write: out std_logic;
wrfifo_wrempty: in std_logic;
rdfifo_address_datain: out std_logic_vector(22 downto 0);
rdfifo_address_we: out std_logic;
rdfifo_address_wrempty: in std_logic;
rdfifo_data_rdreq: out std_logic;
rdfifo_data_dataout: in std_logic_vector(31 downto 0);
rdfifo_data_rdempty: in std_logic
);
end component bus_interface;
--control signals for sdram driver
signal cmd_address: std_logic_vector(22 downto 0); -- address to read/write
signal cmd_data_in: std_logic_vector(31 downto 0); -- data for the write command
signal cmd_data_out: std_logic_vector(31 downto 0); -- word read from sdram
signal cmd_data_out_ready: std_logic; -- is new data ready?
signal cmd_busy: std_logic;
signal cmd_wr_req: std_logic;
signal cmd_rd_req: std_logic;
signal cmd_ack: std_logic;
-- following six signals are used for crossing clk domain in data write path
-- these signals are come from writefifo into sdram clk domain
signal wrfifo_dataout: std_logic_vector(54 downto 0);
signal wrfifo_read: std_logic;
signal wrfifo_rdempty: std_logic;
-- these signals are come from fifo into sys clk domain
signal wrfifo_datain: std_logic_vector(54 downto 0);
signal wrfifo_write: std_logic;
signal wrfifo_wrempty: std_logic;
-- these signals are come from fifo into sdram clk domain
signal rdfifo_address_q: std_logic_vector(22 downto 0);
signal rdfifo_address_rdempty: std_logic;
signal rdfifo_address_rdreq: std_logic;
-- these signal are come from rdfifo into system clk domain
signal rdfifo_address_datain: std_logic_vector(22 downto 0);
signal rdfifo_address_we: std_logic;
signal rdfifo_address_wrempty: std_logic;
-- these signlas are come from sdram clk domain into fifo
signal rdfifo_data_datain: std_logic_vector(31 downto 0);
signal rdfifo_data_wrreq: std_logic;
signal rdfifo_data_wremty: std_logic;
-- these signals are come from system clk domain into fifo
signal rdfifo_data_dataout: std_logic_vector(31 downto 0);
signal rdfifo_data_rdreq: std_logic;
signal rdfifo_data_rdempty: std_logic;
type fsm_state_type is (idle, wrcmd_fifo, wrcmd_write, wrcmd_wait, rdcmd_fiforead, rdcmd_read, rdcmd_wait, rdcmd_fifowrite);
signal fsm_state: fsm_state_type;
begin
----------------------------
-- SDRAM CLK domain
dram_driver0: sdram_driver
port map(
clk_sdram, res,
cmd_address, cmd_data_in, cmd_data_out, cmd_busy, cmd_wr_req, cmd_rd_req, cmd_data_out_ready, cmd_ack,
sdram_ras, sdram_cas, sdram_we, sdram_a, sdram_ba, sdram_dq
);
rdfifo_data_datain <= cmd_data_out;
cmd_data_in <= wrfifo_dataout(31 downto 0);
cmd_address <= wrfifo_dataout(54 downto 32) when cmd_wr_req = '1' else rdfifo_address_q;
process(clk_sdram) is
begin
if rising_edge(clk_sdram) then
if res = '1' then
fsm_state <= idle;
else
case fsm_state is
when idle =>
if cmd_busy = '0' then
if wrfifo_rdempty = '0' then
fsm_state <= wrcmd_fifo;
elsif rdfifo_address_rdempty = '0' then
fsm_state <= rdcmd_fiforead;
else
fsm_state <= idle;
end if;
else
fsm_state <= idle;
end if;
when wrcmd_fifo =>
fsm_state <= wrcmd_write;
when wrcmd_write =>
if cmd_ack = '1' then
fsm_state <= wrcmd_wait;
else
fsm_state <= wrcmd_write;
end if;
when wrcmd_wait =>
if cmd_busy = '0' then
fsm_state <= idle;
else
fsm_state <= wrcmd_wait;
end if;
when rdcmd_fiforead =>
fsm_state <= rdcmd_read;
when rdcmd_read =>
if cmd_ack = '1' then
fsm_state <= rdcmd_wait;
else
fsm_state <= rdcmd_read;
end if;
when rdcmd_wait =>
if cmd_data_out_ready = '1' then
if rdfifo_data_wremty = '1' then
fsm_state <= rdcmd_fifowrite;
else
fsm_state <= rdcmd_wait;
end if;
else
fsm_state <= rdcmd_wait;
end if;
when rdcmd_fifowrite =>
fsm_state <= idle;
end case;
end if;
end if;
end process;
process(fsm_state) is
begin
case fsm_state is
when idle =>
cmd_wr_req <= '0'; cmd_rd_req <= '0'; rdfifo_address_rdreq <= '0'; rdfifo_data_wrreq <= '0'; wrfifo_read <= '0';
when wrcmd_fifo =>
cmd_wr_req <= '0'; cmd_rd_req <= '0'; rdfifo_address_rdreq <= '0'; rdfifo_data_wrreq <= '0'; wrfifo_read <= '1';
when wrcmd_write =>
cmd_wr_req <= '1'; cmd_rd_req <= '0'; rdfifo_address_rdreq <= '0'; rdfifo_data_wrreq <= '0'; wrfifo_read <= '0';
when wrcmd_wait =>
cmd_wr_req <= '0'; cmd_rd_req <= '0'; rdfifo_address_rdreq <= '0'; rdfifo_data_wrreq <= '0'; wrfifo_read <= '0';
when rdcmd_fiforead =>
cmd_wr_req <= '0'; cmd_rd_req <= '0'; rdfifo_address_rdreq <= '1'; rdfifo_data_wrreq <= '0'; wrfifo_read <= '0';
when rdcmd_read =>
cmd_wr_req <= '0'; cmd_rd_req <= '1'; rdfifo_address_rdreq <= '0'; rdfifo_data_wrreq <= '0'; wrfifo_read <= '0';
when rdcmd_wait =>
cmd_wr_req <= '0'; cmd_rd_req <= '0'; rdfifo_address_rdreq <= '0'; rdfifo_data_wrreq <= '0'; wrfifo_read <= '0';
when rdcmd_fifowrite =>
cmd_wr_req <= '0'; cmd_rd_req <= '0'; rdfifo_address_rdreq <= '0'; rdfifo_data_wrreq <= '1'; wrfifo_read <= '0';
end case;
end process;
----------------------------
-- CLK domain crossing
wrfifo0: dcfifo
generic map(
4, "OFF", 55, 2, "ON", "ON", "ON", "OFF", "ON", "TRUE", "dcfifo"
)
port map(
res, wrfifo_datain, clk_sdram, wrfifo_read, clk,
wrfifo_write, wrfifo_dataout, wrfifo_rdempty,
wrfifo_wrempty
);
rdfifo_address0: dcfifo
generic map(
4, "OFF", 23, 2, "ON", "ON", "ON", "OFF", "ON", "TRUE", "dcfifo"
)
port map(
res, rdfifo_address_datain, clk_sdram, rdfifo_address_rdreq, clk,
rdfifo_address_we, rdfifo_address_q, rdfifo_address_rdempty,
rdfifo_address_wrempty
);
rdfifo_data0: dcfifo
generic map(
4, "OFF", 32, 2, "ON", "ON", "ON", "OFF", "ON", "TRUE", "dcfifo"
)
port map(
res, rdfifo_data_datain, clk, rdfifo_data_rdreq, clk_sdram,
rdfifo_data_wrreq, rdfifo_data_dataout, rdfifo_data_rdempty,
rdfifo_data_wremty
);
----------------------------
-- System CLK domain
bi0: bus_interface
generic map(
BASE_ADDRESS
)
port map(
clk, res, address, data_mosi, data_miso, WR, RD, ack,
wrfifo_datain, wrfifo_write, wrfifo_wrempty,
rdfifo_address_datain, rdfifo_address_we,
rdfifo_address_wrempty, rdfifo_data_rdreq,
rdfifo_data_dataout, rdfifo_data_rdempty
);
end architecture rtl;
|
mit
|
a2b3577ebaa18c54c377c1512c5e1e33
| 0.506242 | 4.001048 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/testbench/mixer/mixer_bench.vhd
| 1 | 4,523 |
-------------------------------------------------------------------------------
-- Title : Mixer testbench
-- Project :
-------------------------------------------------------------------------------
-- File : mixer_bench.vhd
-- Author : Gustavo BM Bruno
-- Company : LNLS
-- Created : 2014-01-21
-- Last update: 2015-03-13
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Tests the mixer stage of the BPM DSP chain.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-21 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity mixer_bench is
end mixer_bench;
architecture test of mixer_bench is
constant c_input_freq : real := 112.8e6;
-- constant c_mixer_freq : real := 20.0e6;
constant c_sin_file : string := "./dds_sin.nif";
constant c_cos_file : string := "./dds_cos.nif";
constant c_number_of_points : natural := 35;
constant c_input_width : natural := 16;
constant c_dds_width : natural := 16;
constant c_output_width : natural := 31;
constant clock_period : time := 1.0 sec / (2.0 * c_input_freq);
signal clock : std_logic := '0';
signal adc_data : std_logic_vector(c_input_width-1 downto 0);
signal endoffile : bit := '0';
signal reset : std_logic := '1';
signal I_sig : std_logic_vector(c_output_width-1 downto 0);
signal Q_sig : std_logic_vector(c_output_width-1 downto 0);
component mixer is
generic (
g_sin_file : string;
g_cos_file : string;
g_number_of_points : natural;
g_input_width : natural;
g_dds_width : natural;
g_output_width : natural);
port (
rst_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
signal_i : in std_logic_vector(g_input_width-1 downto 0);
I_out : out std_logic_vector(g_output_width-1 downto 0);
Q_out : out std_logic_vector(g_output_width-1 downto 0));
end component mixer;
begin
clk_gen : process
begin
clock <= '0';
wait for clock_period;
clock <= '1';
wait for clock_period;
end process;
rst_gen : process(clock)
variable clock_count : natural := 4;
begin
if rising_edge(clock) and clock_count /= 0 then
clock_count := clock_count - 1;
if clock_count = 0 then
reset <= '0';
end if;
end if;
end process;
adc_read : process(clock)
file adc_file : text open read_mode is "mixer.samples";
variable cur_line : line;
variable datain : real;
begin
if rising_edge(clock) and reset = '0' then
if not endfile(adc_file) then
readline(adc_file, cur_line);
read(cur_line, datain);
adc_data <= std_logic_vector(to_signed(integer(datain*(2.0**(real(c_input_width)-1.0))-1.0), c_input_width));
else
endoffile <= '1';
end if;
end if;
end process adc_read;
uut : mixer
generic map (
g_sin_file => c_sin_file,
g_cos_file => c_cos_file,
g_number_of_points => c_number_of_points,
g_input_width => c_input_width,
g_dds_width => c_dds_width,
g_output_width => c_output_width)
port map (
rst_i => reset,
clk_i => clock,
ce_i => '1',
signal_i => adc_data,
I_out => I_sig,
Q_out => Q_sig);
signal_write : process(clock)
file mixer_file : text open write_mode is "mixer_out.samples";
variable cur_line : line;
variable I, Q : integer;
begin
if rising_edge(clock) then
if(endoffile = '0') then
I := to_integer(signed(I_sig));
write(cur_line, I);
write(cur_line, string'(" "));
Q := to_integer(signed(Q_sig));
write(cur_line, Q);
writeline(mixer_file, cur_line);
else
assert (false) report "Input file finished." severity failure;
end if;
end if;
end process;
end test;
|
lgpl-3.0
|
8facf1b90be1ae1799ac22c7cd66a62d
| 0.50807 | 3.6184 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/usb_system/altera_avalon_dc_fifo/_primary.vhd
| 2 | 3,665 |
library verilog;
use verilog.vl_types.all;
entity altera_avalon_dc_fifo is
generic(
SYMBOLS_PER_BEAT: integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_IN_FILL_LEVEL: integer := 0;
USE_OUT_FILL_LEVEL: integer := 0;
WR_SYNC_DEPTH : integer := 2;
RD_SYNC_DEPTH : integer := 2;
STREAM_ALMOST_FULL: integer := 0;
STREAM_ALMOST_EMPTY: integer := 0;
BACKPRESSURE_DURING_RESET: integer := 0;
LOOKAHEAD_POINTERS: integer := 0;
PIPELINE_POINTERS: integer := 0;
USE_SPACE_AVAIL_IF: integer := 0
);
port(
in_clk : in vl_logic;
in_reset_n : in vl_logic;
out_clk : in vl_logic;
out_reset_n : in vl_logic;
in_data : in vl_logic_vector;
in_valid : in vl_logic;
in_ready : out vl_logic;
in_startofpacket: in vl_logic;
in_endofpacket : in vl_logic;
in_empty : in vl_logic_vector;
in_error : in vl_logic_vector;
in_channel : in vl_logic_vector;
out_data : out vl_logic_vector;
out_valid : out vl_logic;
out_ready : in vl_logic;
out_startofpacket: out vl_logic;
out_endofpacket : out vl_logic;
out_empty : out vl_logic_vector;
out_error : out vl_logic_vector;
out_channel : out vl_logic_vector;
in_csr_address : in vl_logic;
in_csr_write : in vl_logic;
in_csr_read : in vl_logic;
in_csr_readdata : out vl_logic_vector(31 downto 0);
in_csr_writedata: in vl_logic_vector(31 downto 0);
out_csr_address : in vl_logic;
out_csr_write : in vl_logic;
out_csr_read : in vl_logic;
out_csr_readdata: out vl_logic_vector(31 downto 0);
out_csr_writedata: in vl_logic_vector(31 downto 0);
almost_full_valid: out vl_logic;
almost_full_data: out vl_logic;
almost_empty_valid: out vl_logic;
almost_empty_data: out vl_logic;
space_avail_data: out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of SYMBOLS_PER_BEAT : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_SYMBOL : constant is 1;
attribute mti_svvh_generic_type of FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of CHANNEL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of ERROR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of USE_PACKETS : constant is 1;
attribute mti_svvh_generic_type of USE_IN_FILL_LEVEL : constant is 1;
attribute mti_svvh_generic_type of USE_OUT_FILL_LEVEL : constant is 1;
attribute mti_svvh_generic_type of WR_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of RD_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of STREAM_ALMOST_FULL : constant is 1;
attribute mti_svvh_generic_type of STREAM_ALMOST_EMPTY : constant is 1;
attribute mti_svvh_generic_type of BACKPRESSURE_DURING_RESET : constant is 1;
attribute mti_svvh_generic_type of LOOKAHEAD_POINTERS : constant is 1;
attribute mti_svvh_generic_type of PIPELINE_POINTERS : constant is 1;
attribute mti_svvh_generic_type of USE_SPACE_AVAIL_IF : constant is 1;
end altera_avalon_dc_fifo;
|
apache-2.0
|
e82f47735875d63ce802a1fd36e02d62
| 0.588813 | 3.534233 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/TmpVarExample2.vhd
| 1 | 1,147 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TmpVarExample2 IS
PORT(
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF TmpVarExample2 IS
BEGIN
assig_process_b: PROCESS(a)
VARIABLE tmpBool2std_logic_0 : STD_LOGIC;
VARIABLE tmpBool2std_logic_1 : STD_LOGIC;
VARIABLE tmpCastExpr_0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE tmpTypeConv_0 : UNSIGNED(1 DOWNTO 0);
BEGIN
IF a(31 DOWNTO 16) = X"0001" THEN
tmpBool2std_logic_0 := '1';
ELSE
tmpBool2std_logic_0 := '0';
END IF;
IF a(15 DOWNTO 0) = X"0001" THEN
tmpBool2std_logic_1 := '1';
ELSE
tmpBool2std_logic_1 := '0';
END IF;
tmpCastExpr_0 := tmpBool2std_logic_0 & tmpBool2std_logic_1;
tmpTypeConv_0 := UNSIGNED(tmpCastExpr_0) + UNSIGNED'("01");
IF tmpTypeConv_0(1) = '0' AND tmpTypeConv_0(0) = '0' THEN
b <= X"00000000";
ELSE
b <= X"00000001";
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
f263461150df277185e552ea25dd4d21
| 0.576286 | 3.518405 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/rtlLvl/SwitchStatement.vhd
| 1 | 867 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SwitchStatement IS
PORT(
input : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF SwitchStatement IS
BEGIN
assig_process_output: PROCESS(input)
BEGIN
CASE input IS
WHEN X"00" =>
output <= X"01";
WHEN X"01" =>
output <= X"02";
WHEN X"02" =>
output <= X"03";
WHEN X"03" =>
output <= X"04";
WHEN X"04" =>
output <= X"05";
WHEN X"05" =>
output <= X"06";
WHEN X"06" =>
output <= X"07";
WHEN X"07" =>
output <= X"08";
END CASE;
END PROCESS;
END ARCHITECTURE;
|
mit
|
5f6e383fb75113e5b58fcae1095d0395
| 0.454441 | 3.958904 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/testbench/input_conditioner/conditioner_bench.vhd
| 1 | 4,832 |
-------------------------------------------------------------------------------
-- Title : Input Conditioner testbench
-- Project :
-------------------------------------------------------------------------------
-- File : conditioner_bench.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-02-01
-- Last update: 2014-02-25
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Input conditioner testbench
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-01 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity conditioner_bench is
end entity conditioner_bench;
architecture test of conditioner_bench is
constant input_freq : real := 1.1742939e08;
constant sw_freq : real := input_freq/1000.0;
constant clock_period : time := 1.0 sec /(2.0*input_freq);
signal clock : std_logic := '0';
signal adc_ch1 : std_logic_vector(15 downto 0); -- signal from the straight channel
signal adc_ch2 : std_logic_vector(15 downto 0); -- signal from the switched channel
signal adc_data : std_logic_vector(15 downto 0); -- signal to the uut
signal endoffile : bit := '0';
constant samples_to_switch : natural := 5;
signal switch_sel : std_logic := '0';
signal data_out : std_logic_vector(23 downto 0);
component input_conditioner is
generic (
g_clk_freq : real;
g_sw_freq : real);
port (
rst_n_i : in std_logic; -- Reset data
clk_i : in std_logic; -- Main clock
adc_data_i : in std_logic_vector(15 downto 0); -- Raw data from the ADC
switch_o : out std_logic; -- Switch position output
data_output_o : out std_logic_vector(23 downto 0)); -- Windowed output data
end component input_conditioner;
begin -- architecture test
clk_gen : process
begin
clock <= '0';
wait for clock_period;
clock <= '1';
wait for clock_period;
end process;
-- To simulate the different channels, the data file should have two columns
-- per line, each for a different datapath. The switching process is then
-- simulated by the testbench.
sample_read : process(clock)
file adc_file : text open read_mode is "amostras.dat";
variable cur_line : line;
variable datain1, datain2 : real;
begin
if rising_edge(clock) then
if not endfile(adc_file) then
readline(adc_file, cur_line);
read(cur_line, datain1);
adc_ch1 <= std_logic_vector(to_signed(integer(datain1*(2.0**15.0)), 16));
read(cur_line, datain2);
adc_ch2 <= std_logic_vector(to_signed(integer(datain2*(2.0**15.0)), 16));
else
endoffile <= '1';
end if;
end if;
end process sample_read;
adc_switch : process(clock, switch_sel)
variable samples_to_end : natural := samples_to_switch;
begin
if rising_edge(clock) then
if samples_to_end > 0 then
adc_data <= std_logic_vector(to_signed(0, 16));
samples_to_end := samples_to_end - 1;
elsif switch_sel = '0' then
adc_data <= adc_ch1;
else
adc_data <= adc_ch2;
end if;
end if;
if switch_sel'event then
samples_to_end := samples_to_switch;
end if;
end process adc_switch;
uut : input_conditioner
generic map(
g_clk_freq => input_freq,
g_sw_freq => sw_freq)
port map(
rst_n_i => '1',
clk_i => clock,
adc_data_i => adc_data,
switch_o => switch_sel,
data_output_o => data_out);
signal_write : process(clock)
file conditioner_file : text open write_mode is "conditioner_out.dat";
variable cur_line : line;
variable data_input, data_output : integer;
begin
if rising_edge(clock) then
if(endoffile = '0') then
data_input := to_integer(signed(adc_data));
write(cur_line, data_input);
write(cur_line, string'(" "));
data_output := to_integer(signed(data_out));
write(cur_line, data_output);
writeline(conditioner_file, cur_line);
else
assert (false) report "Input file finished." severity failure;
end if;
end if;
end process;
end architecture test;
|
lgpl-3.0
|
b2093baa540197ae2adc7823ecd890d8
| 0.540563 | 3.850199 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/mem/DReg.vhd
| 1 | 885 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Basic d flip flop
--
-- :attention: using this unit is pointless because HWToolkit can automatically
-- generate such a register for any interface and datatype
--
-- .. hwt-autodoc::
--
ENTITY DReg IS
PORT(
clk : IN STD_LOGIC;
din : IN STD_LOGIC;
dout : OUT STD_LOGIC;
rst : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF DReg IS
SIGNAL internReg : STD_LOGIC := '0';
SIGNAL internReg_next : STD_LOGIC;
BEGIN
dout <= internReg;
assig_process_internReg: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
internReg <= '0';
ELSE
internReg <= internReg_next;
END IF;
END IF;
END PROCESS;
internReg_next <= din;
END ARCHITECTURE;
|
mit
|
64bde5f90c268f016b3758acc1058ba4
| 0.578531 | 3.847826 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_bpm_swap/bpm_swap/swmode_sel.vhd
| 1 | 2,665 |
------------------------------------------------------------------------------
-- Title : BPM RF channels swapping and de-swapping mode selector
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Select among distinct swapping and de-swapping modes affecting
-- how the swap master clock is propagated to the swap and de-swap
-- output signals.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bpm_cores_pkg.all;
entity swmode_sel is
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
-- Swap master clock
clk_swap_i : in std_logic;
-- Swap and de-swap signals
swap_o : out std_logic;
deswap_o : out std_logic;
-- Swap mode setting
swap_mode_i : in t_swap_mode
);
end swmode_sel;
architecture rtl of swmode_sel is
signal swap : std_logic;
signal deswap : std_logic;
begin
p_swap_mode : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
swap <= '0';
deswap <= '0';
else
if en_i = '1' then
case swap_mode_i is
when c_swmode_swap_deswap =>
if clk_swap_i = '1' then
swap <= '1';
deswap <= '1';
else
swap <= '0';
deswap <= '0';
end if;
when c_swmode_static_direct =>
swap <= '0';
deswap <= '0';
when c_swmode_static_inverted =>
swap <= '1';
deswap <= '0';
when c_swmode_rffe_swap =>
if clk_swap_i = '1' then
swap <= '1';
else
swap <= '0';
end if;
deswap <= '0';
when others =>
swap <= '0';
deswap <= '0';
end case;
end if;
end if;
end if;
end process p_swap_mode;
swap_o <= swap;
deswap_o <= deswap;
end rtl;
|
lgpl-3.0
|
2ce3115982a690953ba9ec8fbf4ed3a4
| 0.396248 | 4.494098 | false | false | false | false |
nanomolina/MIPS
|
DATAPATH/alu.vhd
| 1 | 1,242 |
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity alu is
port(
a, b: in std_logic_vector(31 downto 0);
alucontrol: in std_logic_vector(2 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic
);
end entity;
architecture behavior of alu is
begin
process(a,b,alucontrol)
variable temp: std_logic_vector(31 downto 0);
begin
case alucontrol is
when "000" =>
temp := a and b;
when "001" =>
temp := a or b;
when "010" =>
temp := a + b;
when "011" =>
temp := x"00000000"; --preguntar
when "100" =>
temp := a and not(b);
when "101" =>
temp := a or not(b);
when "110" =>
temp := a - b;
when "111" =>
if (a < b) then
temp := (others => '1');
elsif (a > b) then
temp := (others => '0');
end if;
when others =>
temp := x"00000000";
end case;
if (temp = x"00000000") then
zero <= '1';
else
zero <= '0';
end if;
result <= temp;
end process;
end behavior;
|
gpl-3.0
|
206bd006a8d07ad394b97f3f3db18238
| 0.461353 | 3.740964 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/db/alt_dspbuilder_bus_concat.vhd
| 1 | 2,342 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_bus_concat is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
b : in std_logic_vector(widthB-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
a : in std_logic_vector(widthA-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
output : out std_logic_vector(widthA+widthB-1 downto 0)
);
end entity alt_dspbuilder_bus_concat;
architecture rtl of alt_dspbuilder_bus_concat is
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
a : in std_logic_vector(8-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(8-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(16-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
component alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic (
WIDTHB : natural := 16;
WIDTHA : natural := 8
);
port (
a : in std_logic_vector(8-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(16-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(24-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GN55ETJ4VI;
begin
alt_dspbuilder_bus_concat_GNIIOZRPJD_0: if ((WIDTHB = 8) and (WIDTHA = 8)) generate
inst_alt_dspbuilder_bus_concat_GNIIOZRPJD_0: alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map(WIDTHB => 8, WIDTHA => 8)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
alt_dspbuilder_bus_concat_GN55ETJ4VI_1: if ((WIDTHB = 16) and (WIDTHA = 8)) generate
inst_alt_dspbuilder_bus_concat_GN55ETJ4VI_1: alt_dspbuilder_bus_concat_GN55ETJ4VI
generic map(WIDTHB => 16, WIDTHA => 8)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
assert not (((WIDTHB = 8) and (WIDTHA = 8)) or ((WIDTHB = 16) and (WIDTHA = 8)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
6113a33339292b2b3cc1fe781dd8a90d
| 0.672929 | 3.021935 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/specialIntfTypes/InterfaceWithVHDLUnconstrainedArrayImportedType2.vhd
| 1 | 615 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY InterfaceWithVHDLUnconstrainedArrayImportedType2 IS
GENERIC(
SIZE_X : INTEGER := 3
);
PORT(
din_0 : IN UNSIGNED(7 DOWNTO 0);
din_1 : IN UNSIGNED(7 DOWNTO 0);
din_2 : IN UNSIGNED(7 DOWNTO 0);
dout : OUT mem(0 TO 3)(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF InterfaceWithVHDLUnconstrainedArrayImportedType2 IS
BEGIN
dout(0) <= din_0;
dout(1) <= din_1;
dout(2) <= din_2;
ASSERT SIZE_X = 3 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
|
mit
|
7a63b150a357e152efd4d2e23d28cada
| 0.653659 | 3.39779 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/fixed_dds/lut_sweep.vhd
| 1 | 2,566 |
-------------------------------------------------------------------------------
-- Title : Look-up table sweeper
-- Project :
-------------------------------------------------------------------------------
-- File : lut_sweep.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Swwep look-up table addresses for Phased DDS
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------
entity lut_sweep is
generic (
g_number_of_points : natural := 203;
g_bus_size : natural := 16 --must be
--ceil(log2(g_number_of_points)) +
--g_phase_bus_size
);
port (
rst_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
address_o : out std_logic_vector(g_bus_size-1 downto 0);
valid_o : out std_logic);
end entity lut_sweep;
-------------------------------------------------------------------------------
architecture behavioral of lut_sweep is
begin -- architecture behavioral
next_output : process(clk_i )
variable sample : natural range 0 to g_number_of_points;
begin
if rising_edge(clk_i ) then
if rst_i = '1' then
sample := 0;
address_o <= std_logic_vector(to_unsigned(0, g_bus_size));
valid_o <= '0';
elsif ce_i = '1' then
if valid_i = '1' then
if sample = g_number_of_points-1 then
sample := 0;
else
sample := sample + 1;
end if;
end if;
address_o <= std_logic_vector(to_unsigned(sample, g_bus_size));
valid_o <= valid_i;
end if; -- reset
end if; -- rising_edge
end process next_output;
end architecture behavioral;
-------------------------------------------------------------------------------
|
lgpl-3.0
|
2d4fc133d77cfa1db05148e641b8ada7
| 0.397896 | 4.509666 | false | false | false | false |
nanomolina/MIPS
|
prueba/dmem.vhd
| 2 | 2,380 |
-------------------------------------------------------------------------------
--
-- Title : dmem
-- Design : Mips
-- Author : Eduardo Sanchez
-- Company : Famaf
--
-------------------------------------------------------------------------------
--
-- File : dmem.vhd
--
-------------------------------------------------------------------------------
--
-- Description : Archivo con el diseño de la memoria RAM del procesador MIPS.
-- Para mantener un diseño corto, la memoria solo contiene 64 palabras de
-- 32 bits c/u (aunque podria direccionar mas memoria)
-- dump: si esta señal esta activa (1), se copia le contenido de la memoria
-- en el archivo de salida DUMP (para su posterior revision).
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_SIGNED.all;
use ieee.numeric_std.all;
--library WORK;
--use WORK.components.all;
entity dmem is -- data memory
port(clk, we: in STD_LOGIC;
a, wd: in STD_LOGIC_VECTOR(31 downto 0);
rd: out STD_LOGIC_VECTOR(31 downto 0);
dump: in STD_LOGIC
);
end;
architecture behave of dmem is
constant MEMORY_DUMP_FILE: string := "output.dump";
constant MAX_BOUND: Integer := 64;
type ramtype is array (MAX_BOUND-1 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
signal mem: ramtype;
procedure memDump is
file dumpfile : text open write_mode is MEMORY_DUMP_FILE;
variable dumpline : line;
variable i: natural := 0;
begin
write(dumpline, string'("Memoria RAM de Mips:"));
writeline(dumpfile,dumpline);
write(dumpline, string'("Address Data"));
writeline(dumpfile,dumpline);
while i <= MAX_BOUND-1 loop
write(dumpline, i);
write(dumpline, string'(" "));
write(dumpline, conv_integer(mem(i)));
writeline(dumpfile,dumpline);
i:=i+1;
end loop;
end procedure memDump;
begin
process(clk, a, mem)
--edit
variable pos_a : integer;
begin
if clk'event and clk = '1' and we = '1' then
mem(to_integer(unsigned(a(7 downto 2)))) <= wd;
end if;
if a = x"00000000" then rd <= x"00000000";
else
pos_a := to_integer(unsigned(a(7 downto 2)));
rd <= mem(pos_a); -- word aligned
end if;
end process;
process(dump)
begin
if dump = '1' then
memDump;
end if;
end process;
end;
|
gpl-3.0
|
ee004ec16d05406472ea5d1aac80808b
| 0.560924 | 3.712949 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/usb_system/altera_merlin_master_agent/_primary.vhd
| 1 | 8,194 |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_master_agent is
generic(
PKT_QOS_H : integer := 109;
PKT_QOS_L : integer := 106;
PKT_DATA_SIDEBAND_H: integer := 105;
PKT_DATA_SIDEBAND_L: integer := 98;
PKT_ADDR_SIDEBAND_H: integer := 97;
PKT_ADDR_SIDEBAND_L: integer := 93;
PKT_CACHE_H : integer := 92;
PKT_CACHE_L : integer := 89;
PKT_THREAD_ID_H : integer := 88;
PKT_THREAD_ID_L : integer := 87;
PKT_BEGIN_BURST : integer := 81;
PKT_PROTECTION_H: integer := 80;
PKT_PROTECTION_L: integer := 80;
PKT_BURSTWRAP_H : integer := 79;
PKT_BURSTWRAP_L : integer := 77;
PKT_BYTE_CNT_H : integer := 76;
PKT_BYTE_CNT_L : integer := 74;
PKT_ADDR_H : integer := 73;
PKT_ADDR_L : integer := 42;
PKT_BURST_SIZE_H: integer := 86;
PKT_BURST_SIZE_L: integer := 84;
PKT_BURST_TYPE_H: integer := 94;
PKT_BURST_TYPE_L: integer := 93;
PKT_TRANS_EXCLUSIVE: integer := 83;
PKT_TRANS_LOCK : integer := 82;
PKT_TRANS_COMPRESSED_READ: integer := 41;
PKT_TRANS_POSTED: integer := 40;
PKT_TRANS_WRITE : integer := 39;
PKT_TRANS_READ : integer := 38;
PKT_DATA_H : integer := 37;
PKT_DATA_L : integer := 6;
PKT_BYTEEN_H : integer := 5;
PKT_BYTEEN_L : integer := 2;
PKT_SRC_ID_H : integer := 1;
PKT_SRC_ID_L : integer := 1;
PKT_DEST_ID_H : integer := 0;
PKT_DEST_ID_L : integer := 0;
PKT_RESPONSE_STATUS_L: integer := 110;
PKT_RESPONSE_STATUS_H: integer := 111;
PKT_ORI_BURST_SIZE_L: integer := 112;
PKT_ORI_BURST_SIZE_H: integer := 114;
ST_DATA_W : integer := 115;
ST_CHANNEL_W : integer := 1;
AV_BURSTCOUNT_W : integer := 3;
ID : integer := 1;
SUPPRESS_0_BYTEEN_RSP: integer := 1;
BURSTWRAP_VALUE : integer := 4;
CACHE_VALUE : integer := 0;
SECURE_ACCESS_BIT: integer := 1;
USE_READRESPONSE: integer := 0;
USE_WRITERESPONSE: integer := 0;
PKT_BURSTWRAP_W : vl_notype;
PKT_BYTE_CNT_W : vl_notype;
PKT_PROTECTION_W: vl_notype;
PKT_ADDR_W : vl_notype;
PKT_DATA_W : vl_notype;
PKT_BYTEEN_W : vl_notype;
PKT_SRC_ID_W : vl_notype;
PKT_DEST_ID_W : vl_notype;
PKT_BURST_SIZE_W: vl_notype
);
port(
clk : in vl_logic;
reset : in vl_logic;
av_address : in vl_logic_vector;
av_write : in vl_logic;
av_read : in vl_logic;
av_writedata : in vl_logic_vector;
av_readdata : out vl_logic_vector;
av_waitrequest : out vl_logic;
av_readdatavalid: out vl_logic;
av_byteenable : in vl_logic_vector;
av_burstcount : in vl_logic_vector;
av_debugaccess : in vl_logic;
av_lock : in vl_logic;
av_response : out vl_logic_vector(1 downto 0);
av_writeresponserequest: in vl_logic;
av_writeresponsevalid: out vl_logic;
cp_valid : out vl_logic;
cp_data : out vl_logic_vector;
cp_startofpacket: out vl_logic;
cp_endofpacket : out vl_logic;
cp_ready : in vl_logic;
rp_valid : in vl_logic;
rp_data : in vl_logic_vector;
rp_channel : in vl_logic_vector;
rp_startofpacket: in vl_logic;
rp_endofpacket : in vl_logic;
rp_ready : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of PKT_QOS_H : constant is 1;
attribute mti_svvh_generic_type of PKT_QOS_L : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_SIDEBAND_H : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_SIDEBAND_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_SIDEBAND_H : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_SIDEBAND_L : constant is 1;
attribute mti_svvh_generic_type of PKT_CACHE_H : constant is 1;
attribute mti_svvh_generic_type of PKT_CACHE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_THREAD_ID_H : constant is 1;
attribute mti_svvh_generic_type of PKT_THREAD_ID_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BEGIN_BURST : constant is 1;
attribute mti_svvh_generic_type of PKT_PROTECTION_H : constant is 1;
attribute mti_svvh_generic_type of PKT_PROTECTION_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BURSTWRAP_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BURSTWRAP_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTE_CNT_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTE_CNT_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_H : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_SIZE_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_SIZE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_TYPE_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_TYPE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_EXCLUSIVE : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_LOCK : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_COMPRESSED_READ : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_POSTED : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_WRITE : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_READ : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_H : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTEEN_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTEEN_L : constant is 1;
attribute mti_svvh_generic_type of PKT_SRC_ID_H : constant is 1;
attribute mti_svvh_generic_type of PKT_SRC_ID_L : constant is 1;
attribute mti_svvh_generic_type of PKT_DEST_ID_H : constant is 1;
attribute mti_svvh_generic_type of PKT_DEST_ID_L : constant is 1;
attribute mti_svvh_generic_type of PKT_RESPONSE_STATUS_L : constant is 1;
attribute mti_svvh_generic_type of PKT_RESPONSE_STATUS_H : constant is 1;
attribute mti_svvh_generic_type of PKT_ORI_BURST_SIZE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ORI_BURST_SIZE_H : constant is 1;
attribute mti_svvh_generic_type of ST_DATA_W : constant is 1;
attribute mti_svvh_generic_type of ST_CHANNEL_W : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of ID : constant is 1;
attribute mti_svvh_generic_type of SUPPRESS_0_BYTEEN_RSP : constant is 1;
attribute mti_svvh_generic_type of BURSTWRAP_VALUE : constant is 1;
attribute mti_svvh_generic_type of CACHE_VALUE : constant is 1;
attribute mti_svvh_generic_type of SECURE_ACCESS_BIT : constant is 1;
attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1;
attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1;
attribute mti_svvh_generic_type of PKT_BURSTWRAP_W : constant is 3;
attribute mti_svvh_generic_type of PKT_BYTE_CNT_W : constant is 3;
attribute mti_svvh_generic_type of PKT_PROTECTION_W : constant is 3;
attribute mti_svvh_generic_type of PKT_ADDR_W : constant is 3;
attribute mti_svvh_generic_type of PKT_DATA_W : constant is 3;
attribute mti_svvh_generic_type of PKT_BYTEEN_W : constant is 3;
attribute mti_svvh_generic_type of PKT_SRC_ID_W : constant is 3;
attribute mti_svvh_generic_type of PKT_DEST_ID_W : constant is 3;
attribute mti_svvh_generic_type of PKT_BURST_SIZE_W : constant is 3;
end altera_merlin_master_agent;
|
apache-2.0
|
f7ac325e6b83d0533047f94cdcb815a8
| 0.622773 | 3.450105 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/afc_v3/dbe_bpm2_with_dcc/dbe_bpm2_with_dcc.vhd
| 1 | 32,496 |
------------------------------------------------------------------------------
-- Title : Top FMC250M design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC250M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-19 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- IP cores constants
use work.ipcores_pkg.all;
-- AFC definitions
use work.afc_base_pkg.all;
entity dbe_bpm2_with_dcc is
generic (
-- Number of P2P GTs
g_NUM_P2P_GTS : integer := 8;
-- Start index of the P2P GTs
g_P2P_GT_START_ID : integer := 0
);
port(
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;
afc_fp2_clk1_p_i : in std_logic;
afc_fp2_clk1_n_i : in std_logic;
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0);
trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0);
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i : in std_logic := '0';
diag_spi_si_i : in std_logic := '0';
diag_spi_so_o : out std_logic;
diag_spi_clk_i : in std_logic := '0';
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o : out std_logic;
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b : inout std_logic;
afc_si57x_sda_b : inout std_logic;
-- Si57x oscillator output enable
afc_si57x_oe_o : out std_logic;
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b : inout std_logic;
board_i2c_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o : out std_logic;
-- spi_cs_n_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic := '0';
---------------------------------------------------------------------------
-- P2P GT pins
---------------------------------------------------------------------------
-- P2P
p2p_gt_rx_p_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '0');
p2p_gt_rx_n_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '1');
p2p_gt_tx_p_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
p2p_gt_tx_n_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
-----------------------------
-- FMC1_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc1_adc_clk_div_rst_p_o : out std_logic;
fmc1_adc_clk_div_rst_n_o : out std_logic;
fmc1_adc_ext_rst_n_o : out std_logic;
fmc1_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc1_adc_clk0_p_i : in std_logic := '0';
fmc1_adc_clk0_n_i : in std_logic := '0';
fmc1_adc_clk1_p_i : in std_logic := '0';
fmc1_adc_clk1_n_i : in std_logic := '0';
fmc1_adc_clk2_p_i : in std_logic := '0';
fmc1_adc_clk2_n_i : in std_logic := '0';
fmc1_adc_clk3_p_i : in std_logic := '0';
fmc1_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc1_adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc1_prsnt_i : in std_logic;
--fmc1_pg_m2c_i : in std_logic;
--fmc1_clk_dir_i : in std_logic;
-- Trigger
fmc1_trig_dir_o : out std_logic;
fmc1_trig_term_o : out std_logic;
fmc1_trig_val_p_b : inout std_logic;
fmc1_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc1_adc_spi_clk_o : out std_logic;
fmc1_adc_spi_mosi_o : out std_logic;
fmc1_adc_spi_miso_i : in std_logic;
fmc1_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc1_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc1_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc1_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc1_si571_scl_pad_b : inout std_logic;
fmc1_si571_sda_pad_b : inout std_logic;
fmc1_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc1_spi_ad9510_cs_o : out std_logic;
fmc1_spi_ad9510_sclk_o : out std_logic;
fmc1_spi_ad9510_mosi_o : out std_logic;
fmc1_spi_ad9510_miso_i : in std_logic;
fmc1_pll_function_o : out std_logic;
fmc1_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc1_fpga_clk_p_i : in std_logic;
fmc1_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc1_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc1_amc7823_spi_cs_o : out std_logic;
fmc1_amc7823_spi_sclk_o : out std_logic;
fmc1_amc7823_spi_mosi_o : out std_logic;
fmc1_amc7823_spi_miso_i : in std_logic;
fmc1_amc7823_davn_i : in std_logic;
-- FMC LEDs
fmc1_led1_o : out std_logic;
fmc1_led2_o : out std_logic;
fmc1_led3_o : out std_logic;
-----------------------------
-- FMC2_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc2_adc_clk_div_rst_p_o : out std_logic;
fmc2_adc_clk_div_rst_n_o : out std_logic;
fmc2_adc_ext_rst_n_o : out std_logic;
fmc2_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc2_adc_clk0_p_i : in std_logic := '0';
fmc2_adc_clk0_n_i : in std_logic := '0';
fmc2_adc_clk1_p_i : in std_logic := '0';
fmc2_adc_clk1_n_i : in std_logic := '0';
fmc2_adc_clk2_p_i : in std_logic := '0';
fmc2_adc_clk2_n_i : in std_logic := '0';
fmc2_adc_clk3_p_i : in std_logic := '0';
fmc2_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc2_adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc2_prsnt_i : in std_logic;
--fmc2_pg_m2c_i : in std_logic;
--fmc2_clk_dir_i : in std_logic;
-- Trigger
fmc2_trig_dir_o : out std_logic;
fmc2_trig_term_o : out std_logic;
fmc2_trig_val_p_b : inout std_logic;
fmc2_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc2_adc_spi_clk_o : out std_logic;
fmc2_adc_spi_mosi_o : out std_logic;
fmc2_adc_spi_miso_i : in std_logic;
fmc2_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc2_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc2_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc2_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc2_si571_scl_pad_b : inout std_logic;
fmc2_si571_sda_pad_b : inout std_logic;
fmc2_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc2_spi_ad9510_cs_o : out std_logic;
fmc2_spi_ad9510_sclk_o : out std_logic;
fmc2_spi_ad9510_mosi_o : out std_logic;
fmc2_spi_ad9510_miso_i : in std_logic;
fmc2_pll_function_o : out std_logic;
fmc2_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc2_fpga_clk_p_i : in std_logic;
fmc2_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc2_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc2_amc7823_spi_cs_o : out std_logic;
fmc2_amc7823_spi_sclk_o : out std_logic;
fmc2_amc7823_spi_mosi_o : out std_logic;
fmc2_amc7823_spi_miso_i : in std_logic;
fmc2_amc7823_davn_i : in std_logic;
-- FMC LEDs
fmc2_led1_o : out std_logic;
fmc2_led2_o : out std_logic;
fmc2_led3_o : out std_logic
);
end dbe_bpm2_with_dcc;
architecture rtl of dbe_bpm2_with_dcc is
begin
cmp_dbe_bpm_gen : entity work.dbe_bpm_gen
generic map (
g_fmc_adc_type => "FMC250M",
g_NUM_P2P_GTS => g_NUM_P2P_GTS,
g_P2P_GT_START_ID => g_P2P_GT_START_ID,
g_WITH_P2P_FOFB_DCC => true
)
port map (
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
aux_clk_p_i => aux_clk_p_i,
aux_clk_n_i => aux_clk_n_i,
afc_fp2_clk1_p_i => afc_fp2_clk1_p_i,
afc_fp2_clk1_n_i => afc_fp2_clk1_n_i,
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i => sys_rst_button_n_i,
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o => trig_dir_o,
trig_b => trig_b,
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i => diag_spi_cs_i,
diag_spi_si_i => diag_spi_si_i,
diag_spi_so_o => diag_spi_so_o,
diag_spi_clk_i => diag_spi_clk_i,
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o => adn4604_vadj2_clk_updt_n_o,
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b => afc_si57x_scl_b,
afc_si57x_sda_b => afc_si57x_sda_b,
-- Si57x oscillator output enable
afc_si57x_oe_o => afc_si57x_oe_o,
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- PCI clock and reset signals
pcie_clk_p_i => pcie_clk_p_i,
pcie_clk_n_i => pcie_clk_n_i,
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o => leds_o,
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b => board_i2c_scl_b,
board_i2c_sda_b => board_i2c_sda_b,
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o => spi_sclk_o,
-- spi_cs_n_o => spi_cs_n_o,
-- spi_mosi_o => spi_mosi_o,
-- spi_miso_i => spi_miso_i,
---------------------------------------------------------------------------
-- P2P GT pins
---------------------------------------------------------------------------
-- P2P
p2p_gt_rx_p_i => p2p_gt_rx_p_i,
p2p_gt_rx_n_i => p2p_gt_rx_n_i,
p2p_gt_tx_p_o => p2p_gt_tx_p_o,
p2p_gt_tx_n_o => p2p_gt_tx_n_o,
-----------------------------
-- FMC1_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_1_adc_clk_div_rst_p_o => fmc1_adc_clk_div_rst_p_o,
fmc250_1_adc_clk_div_rst_n_o => fmc1_adc_clk_div_rst_n_o,
fmc250_1_adc_ext_rst_n_o => fmc1_adc_ext_rst_n_o,
fmc250_1_adc_sleep_o => fmc1_adc_sleep_o,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_1_adc_clk0_p_i => fmc1_adc_clk0_p_i,
fmc250_1_adc_clk0_n_i => fmc1_adc_clk0_n_i,
fmc250_1_adc_clk1_p_i => fmc1_adc_clk1_p_i,
fmc250_1_adc_clk1_n_i => fmc1_adc_clk1_n_i,
fmc250_1_adc_clk2_p_i => fmc1_adc_clk2_p_i,
fmc250_1_adc_clk2_n_i => fmc1_adc_clk2_n_i,
fmc250_1_adc_clk3_p_i => fmc1_adc_clk3_p_i,
fmc250_1_adc_clk3_n_i => fmc1_adc_clk3_n_i,
-- DDR ADC data channels.
fmc250_1_adc_data_ch0_p_i => fmc1_adc_data_ch0_p_i,
fmc250_1_adc_data_ch0_n_i => fmc1_adc_data_ch0_n_i,
fmc250_1_adc_data_ch1_p_i => fmc1_adc_data_ch1_p_i,
fmc250_1_adc_data_ch1_n_i => fmc1_adc_data_ch1_n_i,
fmc250_1_adc_data_ch2_p_i => fmc1_adc_data_ch2_p_i,
fmc250_1_adc_data_ch2_n_i => fmc1_adc_data_ch2_n_i,
fmc250_1_adc_data_ch3_p_i => fmc1_adc_data_ch3_p_i,
fmc250_1_adc_data_ch3_n_i => fmc1_adc_data_ch3_n_i,
---- FMC General Status
--fmc250_1_prsnt_i : in std_logic := '0';
--fmc250_1_pg_m2c_i : in std_logic := '0';
--fmc250_1_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_1_trig_dir_o => fmc1_trig_dir_o,
fmc250_1_trig_term_o => fmc1_trig_term_o,
fmc250_1_trig_val_p_b => fmc1_trig_val_p_b,
fmc250_1_trig_val_n_b => fmc1_trig_val_n_b,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_1_adc_spi_clk_o => fmc1_adc_spi_clk_o,
fmc250_1_adc_spi_mosi_o => fmc1_adc_spi_mosi_o,
fmc250_1_adc_spi_miso_i => fmc1_adc_spi_miso_i,
fmc250_1_adc_spi_cs_adc0_n_o => fmc1_adc_spi_cs_adc0_n_o,
fmc250_1_adc_spi_cs_adc1_n_o => fmc1_adc_spi_cs_adc1_n_o,
fmc250_1_adc_spi_cs_adc2_n_o => fmc1_adc_spi_cs_adc2_n_o,
fmc250_1_adc_spi_cs_adc3_n_o => fmc1_adc_spi_cs_adc3_n_o,
-- Si571 clock gen
fmc250_1_si571_scl_pad_b => fmc1_si571_scl_pad_b,
fmc250_1_si571_sda_pad_b => fmc1_si571_sda_pad_b,
fmc250_1_si571_oe_o => fmc1_si571_oe_o,
-- AD9510 clock distribution PLL
fmc250_1_spi_ad9510_cs_o => fmc1_spi_ad9510_cs_o,
fmc250_1_spi_ad9510_sclk_o => fmc1_spi_ad9510_sclk_o,
fmc250_1_spi_ad9510_mosi_o => fmc1_spi_ad9510_mosi_o,
fmc250_1_spi_ad9510_miso_i => fmc1_spi_ad9510_miso_i,
fmc250_1_pll_function_o => fmc1_pll_function_o,
fmc250_1_pll_status_i => fmc1_pll_status_i,
-- AD9510 clock copy
fmc250_1_fpga_clk_p_i => fmc1_fpga_clk_p_i,
fmc250_1_fpga_clk_n_i => fmc1_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc250_1_clk_sel_o => fmc1_clk_sel_o,
-- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_1_amc7823_spi_cs_o => fmc1_amc7823_spi_cs_o,
fmc250_1_amc7823_spi_sclk_o => fmc1_amc7823_spi_sclk_o,
fmc250_1_amc7823_spi_mosi_o => fmc1_amc7823_spi_mosi_o,
fmc250_1_amc7823_spi_miso_i => fmc1_amc7823_spi_miso_i,
fmc250_1_amc7823_davn_i => fmc1_amc7823_davn_i,
-- FMC LEDs
fmc250_1_led1_o => fmc1_led1_o,
fmc250_1_led2_o => fmc1_led2_o,
fmc250_1_led3_o => fmc1_led3_o,
-----------------------------
-- FMC2_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_2_adc_clk_div_rst_p_o => fmc2_adc_clk_div_rst_p_o,
fmc250_2_adc_clk_div_rst_n_o => fmc2_adc_clk_div_rst_n_o,
fmc250_2_adc_ext_rst_n_o => fmc2_adc_ext_rst_n_o,
fmc250_2_adc_sleep_o => fmc2_adc_sleep_o,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_2_adc_clk0_p_i => fmc2_adc_clk0_p_i,
fmc250_2_adc_clk0_n_i => fmc2_adc_clk0_n_i,
fmc250_2_adc_clk1_p_i => fmc2_adc_clk1_p_i,
fmc250_2_adc_clk1_n_i => fmc2_adc_clk1_n_i,
fmc250_2_adc_clk2_p_i => fmc2_adc_clk2_p_i,
fmc250_2_adc_clk2_n_i => fmc2_adc_clk2_n_i,
fmc250_2_adc_clk3_p_i => fmc2_adc_clk3_p_i,
fmc250_2_adc_clk3_n_i => fmc2_adc_clk3_n_i,
-- DDR ADC data channels.
fmc250_2_adc_data_ch0_p_i => fmc2_adc_data_ch0_p_i,
fmc250_2_adc_data_ch0_n_i => fmc2_adc_data_ch0_n_i,
fmc250_2_adc_data_ch1_p_i => fmc2_adc_data_ch1_p_i,
fmc250_2_adc_data_ch1_n_i => fmc2_adc_data_ch1_n_i,
fmc250_2_adc_data_ch2_p_i => fmc2_adc_data_ch2_p_i,
fmc250_2_adc_data_ch2_n_i => fmc2_adc_data_ch2_n_i,
fmc250_2_adc_data_ch3_p_i => fmc2_adc_data_ch3_p_i,
fmc250_2_adc_data_ch3_n_i => fmc2_adc_data_ch3_n_i,
---- FMC General Status
--fmc250_2_prsnt_i : in std_logic := '0';
--fmc250_2_pg_m2c_i : in std_logic := '0';
--fmc250_2_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_2_trig_dir_o => fmc2_trig_dir_o,
fmc250_2_trig_term_o => fmc2_trig_term_o,
fmc250_2_trig_val_p_b => fmc2_trig_val_p_b,
fmc250_2_trig_val_n_b => fmc2_trig_val_n_b,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_2_adc_spi_clk_o => fmc2_adc_spi_clk_o,
fmc250_2_adc_spi_mosi_o => fmc2_adc_spi_mosi_o,
fmc250_2_adc_spi_miso_i => fmc2_adc_spi_miso_i,
fmc250_2_adc_spi_cs_adc0_n_o => fmc2_adc_spi_cs_adc0_n_o,
fmc250_2_adc_spi_cs_adc1_n_o => fmc2_adc_spi_cs_adc1_n_o,
fmc250_2_adc_spi_cs_adc2_n_o => fmc2_adc_spi_cs_adc2_n_o,
fmc250_2_adc_spi_cs_adc3_n_o => fmc2_adc_spi_cs_adc3_n_o,
-- Si571 clock gen
fmc250_2_si571_scl_pad_b => fmc2_si571_scl_pad_b,
fmc250_2_si571_sda_pad_b => fmc2_si571_sda_pad_b,
fmc250_2_si571_oe_o => fmc2_si571_oe_o,
-- AD9510 clock distribution PLL
fmc250_2_spi_ad9510_cs_o => fmc2_spi_ad9510_cs_o,
fmc250_2_spi_ad9510_sclk_o => fmc2_spi_ad9510_sclk_o,
fmc250_2_spi_ad9510_mosi_o => fmc2_spi_ad9510_mosi_o,
fmc250_2_spi_ad9510_miso_i => fmc2_spi_ad9510_miso_i,
fmc250_2_pll_function_o => fmc2_pll_function_o,
fmc250_2_pll_status_i => fmc2_pll_status_i,
-- AD9510 clock copy
fmc250_2_fpga_clk_p_i => fmc2_fpga_clk_p_i,
fmc250_2_fpga_clk_n_i => fmc2_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc250_2_clk_sel_o => fmc2_clk_sel_o,
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_2_amc7823_spi_cs_o => fmc2_amc7823_spi_cs_o,
fmc250_2_amc7823_spi_sclk_o => fmc2_amc7823_spi_sclk_o,
fmc250_2_amc7823_spi_mosi_o => fmc2_amc7823_spi_mosi_o,
fmc250_2_amc7823_spi_miso_i => fmc2_amc7823_spi_miso_i,
fmc250_2_amc7823_davn_i => fmc2_amc7823_davn_i,
-- FMC LEDs
fmc250_2_led1_o => fmc2_led1_o,
fmc250_2_led2_o => fmc2_led2_o,
fmc250_2_led3_o => fmc2_led3_o
);
end rtl;
|
lgpl-3.0
|
f1cedd2cd2ab5a4c10d2608dca24b6f7
| 0.389556 | 3.558476 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module.vhd
| 2 | 52,787 |
-- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is
port (
sop : in std_logic := '0'; -- sop.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire
data_out : out std_logic_vector(23 downto 0); -- data_out.wire
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- addr.wire
eop : in std_logic := '0'; -- eop.wire
write : in std_logic := '0' -- write.wire
);
end entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module;
architecture rtl of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNLF52SJQ3 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLF52SJQ3;
component alt_dspbuilder_cast_GNJGR7GQ2L is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(17 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNJGR7GQ2L;
component alt_dspbuilder_cast_GNKXX25S2S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKXX25S2S;
component alt_dspbuilder_cast_GN6OMCQQS7 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN6OMCQQS7;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_multiplexer_GNCALBUTDR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNCALBUTDR;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GN6TDLHAW6 is
port (
input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_port_GN6TDLHAW6;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_constant_GNPXZ5JSVR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNPXZ5JSVR;
component alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN55ETJ4VI;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_if_statement_GNYT6HZJI5 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(7 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNYT6HZJI5;
component alt_dspbuilder_constant_GNLMV7GZFA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNLMV7GZFA;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_decoder_GNA3ETEQ66 is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNA3ETEQ66;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
a : in std_logic_vector(WIDTH-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
direction : in std_logic := 'X'; -- wire
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
r : out std_logic_vector(WIDTH-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
component alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic (
family : string := "Stratix";
direction : string := "AddAdd";
data3b_const : string := "00000000";
data2b_const : string := "00000000";
representation : string := "SIGNED";
dataWidth : integer := 8;
data4b_const : string := "00000000";
number_multipliers : integer := 2;
pipeline_register : string := "NoRegister";
use_dedicated_circuitry : integer := 0;
data1b_const : string := "00000000";
use_b_consts : natural := 0
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data1a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data2a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data3a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(17 downto 0); -- wire
user_aclr : in std_logic := 'X'; -- wire
ena : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiply_add_GNKLXFKAO3;
component alt_dspbuilder_delay_GND2PGZRBZ is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GND2PGZRBZ;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_if_statement_GN7VA7SRUP is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GN7VA7SRUP;
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
component alt_dspbuilder_cast_GNZ5LMFB5D is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNZ5LMFB5D;
component alt_dspbuilder_cast_GN7IAAYCSZ is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7IAAYCSZ;
component alt_dspbuilder_cast_GNSB3OXIQS is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_cast_GNSB3OXIQS;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal decoder2sclrgnd_output_wire : std_logic; -- Decoder2sclrGND:output -> Decoder2:sclr
signal decoder2enavcc_output_wire : std_logic; -- Decoder2enaVCC:output -> Decoder2:ena
signal decoder3sclrgnd_output_wire : std_logic; -- Decoder3sclrGND:output -> Decoder3:sclr
signal decoder3enavcc_output_wire : std_logic; -- Decoder3enaVCC:output -> Decoder3:ena
signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr
signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena
signal barrel_shifteruser_aclrgnd_output_wire : std_logic; -- Barrel_Shifteruser_aclrGND:output -> Barrel_Shifter:user_aclr
signal barrel_shifterenavcc_output_wire : std_logic; -- Barrel_ShifterenaVCC:output -> Barrel_Shifter:ena
signal multiply_adduser_aclrgnd_output_wire : std_logic; -- Multiply_Adduser_aclrGND:output -> Multiply_Add:user_aclr
signal multiply_addenavcc_output_wire : std_logic; -- Multiply_AddenaVCC:output -> Multiply_Add:ena
signal delay6sclrgnd_output_wire : std_logic; -- Delay6sclrGND:output -> Delay6:sclr
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr
signal delay4enavcc_output_wire : std_logic; -- Delay4enaVCC:output -> Delay4:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr
signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr
signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena
signal bus_concatenation_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation:output -> Bus_Concatenation1:b
signal bus_concatenation1_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation1:output -> [Bus_Conversion:input, Multiplexer2:in0]
signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> [Bus_Conversion1:input, Bus_Conversion6:input]
signal barrel_shifter_r_wire : std_logic_vector(17 downto 0); -- Barrel_Shifter:r -> Bus_Conversion2:input
signal bus_conversion2_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion2:output -> [Bus_Concatenation1:a, Bus_Concatenation:a, Bus_Concatenation:b]
signal constant5_output_wire : std_logic_vector(3 downto 0); -- Constant5:output -> Barrel_Shifter:distance
signal addr_0_output_wire : std_logic_vector(1 downto 0); -- addr_0:output -> [Decoder2:data, Decoder:data]
signal bus_conversion1_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion1:output -> Delay2:input
signal delay2_output_wire : std_logic_vector(7 downto 0); -- Delay2:output -> Delay3:input
signal delay4_output_wire : std_logic_vector(0 downto 0); -- Delay4:output -> [Delay:input, cast49:input]
signal bus_conversion6_output_wire : std_logic_vector(0 downto 0); -- Bus_Conversion6:output -> Delay5:input
signal delay5_output_wire : std_logic_vector(0 downto 0); -- Delay5:output -> Delay6:input
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Bus_Conversion3:input, Bus_Conversion4:input, Bus_Conversion5:input, Decoder1:data, Decoder3:data, If_Statement1:a, Multiplexer:in0]
signal bus_conversion_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion:output -> If_Statement:a
signal delay3_output_wire : std_logic_vector(7 downto 0); -- Delay3:output -> If_Statement:b
signal constant3_output_wire : std_logic_vector(23 downto 0); -- Constant3:output -> If_Statement1:b
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> If_Statement1:c
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Logical_Bit_Operator:data0
signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator3:data0, Logical_Bit_Operator5:data0, Logical_Bit_Operator:data1]
signal eop_0_output_wire : std_logic; -- eop_0:output -> Logical_Bit_Operator1:data0
signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator2:data0
signal write_0_output_wire : std_logic; -- write_0:output -> [Logical_Bit_Operator2:data1, Logical_Bit_Operator4:data1]
signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> Delay2:ena
signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay3:ena
signal decoder2_dec_wire : std_logic; -- Decoder2:dec -> Logical_Bit_Operator4:data0
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Delay5:ena
signal decoder3_dec_wire : std_logic; -- Decoder3:dec -> Logical_Bit_Operator5:data1
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> Delay6:ena
signal delay_output_wire : std_logic_vector(0 downto 0); -- Delay:output -> [Multiplexer:sel, cast51:input]
signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Multiplexer1:in0
signal constant2_output_wire : std_logic_vector(23 downto 0); -- Constant2:output -> Multiplexer1:in1
signal delay6_output_wire : std_logic_vector(0 downto 0); -- Delay6:output -> Multiplexer2:sel
signal multiplexer1_result_wire : std_logic_vector(23 downto 0); -- Multiplexer1:result -> Multiplexer2:in1
signal multiplexer2_result_wire : std_logic_vector(23 downto 0); -- Multiplexer2:result -> Multiplexer:in1
signal bus_conversion5_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion5:output -> Multiply_Add:data1a
signal bus_conversion4_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion4:output -> Multiply_Add:data2a
signal bus_conversion3_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion3:output -> Multiply_Add:data3a
signal multiply_add_result_wire : std_logic_vector(17 downto 0); -- Multiply_Add:result -> Barrel_Shifter:a
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> data_out_0:input
signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> cast48:input
signal cast48_output_wire : std_logic; -- cast48:output -> Delay:sclr
signal cast49_output_wire : std_logic; -- cast49:output -> Delay:ena
signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> cast50:input
signal cast50_output_wire : std_logic_vector(0 downto 0); -- cast50:output -> Delay4:input
signal cast51_output_wire : std_logic; -- cast51:output -> Logical_Bit_Operator1:data1
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> cast52:input
signal cast52_output_wire : std_logic_vector(0 downto 0); -- cast52:output -> Delay1:input
signal if_statement_true_wire : std_logic; -- If_Statement:true -> cast53:input
signal cast53_output_wire : std_logic_vector(0 downto 0); -- cast53:output -> Multiplexer1:sel
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Barrel_Shifter:aclr, Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Decoder1:aclr, Decoder2:aclr, Decoder3:aclr, Decoder:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay4:aclr, Delay5:aclr, Delay6:aclr, Delay:aclr, Multiplexer1:aclr, Multiplexer2:aclr, Multiplexer:aclr, Multiply_Add:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Barrel_Shifter:clock, Bus_Concatenation1:clock, Bus_Concatenation:clock, Decoder1:clock, Decoder2:clock, Decoder3:clock, Decoder:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay4:clock, Delay5:clock, Delay6:clock, Delay:clock, Multiplexer1:clock, Multiplexer2:clock, Multiplexer:clock, Multiply_Add:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GNLF52SJQ3
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
bus_conversion2 : component alt_dspbuilder_cast_GNJGR7GQ2L
generic map (
round => 0,
saturate => 0
)
port map (
input => barrel_shifter_r_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNKXX25S2S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
bus_conversion4 : component alt_dspbuilder_cast_GN6OMCQQS7
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion4_output_wire -- output.wire
);
writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => writedata, -- input.wire
output => writedata_0_output_wire -- output.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => delay_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => data_in_0_output_wire, -- in0.wire
in1 => multiplexer2_result_wire -- in1.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
bus_conversion : component alt_dspbuilder_cast_GNKXX25S2S
generic map (
round => 0,
saturate => 0
)
port map (
input => bus_concatenation1_output_wire, -- input.wire
output => bus_conversion_output_wire -- output.wire
);
addr_0 : component alt_dspbuilder_port_GN6TDLHAW6
port map (
input => addr, -- input.wire
output => addr_0_output_wire -- output.wire
);
constant4 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
constant5 : component alt_dspbuilder_constant_GNPXZ5JSVR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "1000",
width => 4
)
port map (
output => constant5_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN55ETJ4VI
generic map (
widthB => 16,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion2_output_wire, -- a.wire
b => bus_concatenation_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder3_dec_wire -- data1.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => decoder2_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion2_output_wire, -- a.wire
b => bus_conversion2_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
constant3 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant3_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNYT6HZJI5
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a>b",
number_inputs => 2,
width => 8
)
port map (
true => if_statement_true_wire, -- true.wire
a => bus_conversion_output_wire, -- a.wire
b => delay3_output_wire -- b.wire
);
constant2 : component alt_dspbuilder_constant_GNLMV7GZFA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "111111111111111111111111",
width => 24
)
port map (
output => constant2_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => delay4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => cast48_output_wire, -- sclr.wire
ena => cast49_output_wire -- ena.wire
);
constant1 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant1_output_wire -- output.wire
);
write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => write, -- input.wire
output => write_0_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder1_dec_wire -- data1.wire
);
logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator2_result_wire, -- result.wire
data0 => decoder_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => eop, -- input.wire
output => eop_0_output_wire -- output.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => eop_0_output_wire, -- data0.wire
data1 => cast51_output_wire -- data1.wire
);
decoder2 : component alt_dspbuilder_decoder_GNA3ETEQ66
generic map (
decode => "00",
pipeline => 1,
width => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder2_dec_wire, -- dec.wire
sclr => decoder2sclrgnd_output_wire, -- sclr.wire
ena => decoder2enavcc_output_wire -- ena.wire
);
decoder2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder2sclrgnd_output_wire -- output.wire
);
decoder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder2enavcc_output_wire -- output.wire
);
decoder3 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_in_0_output_wire, -- data.wire
dec => decoder3_dec_wire, -- dec.wire
sclr => decoder3sclrgnd_output_wire, -- sclr.wire
ena => decoder3enavcc_output_wire -- ena.wire
);
decoder3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder3sclrgnd_output_wire -- output.wire
);
decoder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder3enavcc_output_wire -- output.wire
);
decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_in_0_output_wire, -- data.wire
dec => decoder1_dec_wire, -- dec.wire
sclr => decoder1sclrgnd_output_wire, -- sclr.wire
ena => decoder1enavcc_output_wire -- ena.wire
);
decoder1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder1sclrgnd_output_wire -- output.wire
);
decoder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder1enavcc_output_wire -- output.wire
);
logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator_result_wire, -- result.wire
data0 => if_statement1_true_wire, -- data0.wire
data1 => sop_0_output_wire -- data1.wire
);
barrel_shifter : component alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map (
DISTANCE_WIDTH => 4,
NDIRECTION => 1,
SIGNED => 0,
use_dedicated_circuitry => "false",
PIPELINE => 0,
WIDTH => 18
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => multiply_add_result_wire, -- a.wire
r => barrel_shifter_r_wire, -- r.wire
distance => constant5_output_wire, -- distance.wire
ena => barrel_shifterenavcc_output_wire, -- ena.wire
user_aclr => barrel_shifteruser_aclrgnd_output_wire -- user_aclr.wire
);
barrel_shifteruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => barrel_shifteruser_aclrgnd_output_wire -- output.wire
);
barrel_shifterenavcc : component alt_dspbuilder_vcc_GN
port map (
output => barrel_shifterenavcc_output_wire -- output.wire
);
multiply_add : component alt_dspbuilder_multiply_add_GNKLXFKAO3
generic map (
family => "Cyclone V",
direction => "AddAdd",
data3b_const => "00011110",
data2b_const => "10010110",
representation => "UNSIGNED",
dataWidth => 8,
data4b_const => "01001100",
number_multipliers => 3,
pipeline_register => "NoRegister",
use_dedicated_circuitry => 1,
data1b_const => "01001100",
use_b_consts => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data1a => bus_conversion5_output_wire, -- data1a.wire
data2a => bus_conversion4_output_wire, -- data2a.wire
data3a => bus_conversion3_output_wire, -- data3a.wire
result => multiply_add_result_wire, -- result.wire
user_aclr => multiply_adduser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiply_addenavcc_output_wire -- ena.wire
);
multiply_adduser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiply_adduser_aclrgnd_output_wire -- output.wire
);
multiply_addenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiply_addenavcc_output_wire -- output.wire
);
delay6 : component alt_dspbuilder_delay_GND2PGZRBZ
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "1",
width => 1
)
port map (
input => delay5_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay6_output_wire, -- output.wire
sclr => delay6sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator5_result_wire -- ena.wire
);
delay6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay6sclrgnd_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GND2PGZRBZ
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "1",
width => 1
)
port map (
input => bus_conversion6_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator4_result_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay4 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast50_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay4_output_wire, -- output.wire
sclr => delay4sclrgnd_output_wire, -- sclr.wire
ena => delay4enavcc_output_wire -- ena.wire
);
delay4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay4sclrgnd_output_wire -- output.wire
);
delay4enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay4enavcc_output_wire -- output.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GN7VA7SRUP
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) and (a /= c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => data_in_0_output_wire, -- a.wire
b => constant3_output_wire, -- b.wire
c => constant4_output_wire -- c.wire
);
delay3 : component alt_dspbuilder_delay_GNVTJPHWYT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "01111111",
width => 8
)
port map (
input => delay2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator3_result_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => cast53_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => constant1_output_wire, -- in0.wire
in1 => constant2_output_wire -- in1.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast52_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
multiplexer2 : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => delay6_output_wire, -- sel.wire
result => multiplexer2_result_wire, -- result.wire
ena => multiplexer2enavcc_output_wire, -- ena.wire
user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire
in0 => bus_concatenation1_output_wire, -- in0.wire
in1 => multiplexer1_result_wire -- in1.wire
);
multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer2user_aclrgnd_output_wire -- output.wire
);
multiplexer2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer2enavcc_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNVTJPHWYT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "01111111",
width => 8
)
port map (
input => bus_conversion1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator2_result_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => multiplexer_result_wire, -- input.wire
output => data_out -- output.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
decoder : component alt_dspbuilder_decoder_GNM4LOIHXZ
generic map (
decode => "01",
pipeline => 1,
width => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder_dec_wire, -- dec.wire
sclr => decodersclrgnd_output_wire, -- sclr.wire
ena => decoderenavcc_output_wire -- ena.wire
);
decodersclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decodersclrgnd_output_wire -- output.wire
);
decoderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoderenavcc_output_wire -- output.wire
);
bus_conversion6 : component alt_dspbuilder_cast_GNZ5LMFB5D
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion6_output_wire -- output.wire
);
bus_conversion5 : component alt_dspbuilder_cast_GN7IAAYCSZ
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion5_output_wire -- output.wire
);
cast48 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast48_output_wire -- output.wire
);
cast49 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay4_output_wire, -- input.wire
output => cast49_output_wire -- output.wire
);
cast50 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator_result_wire, -- input.wire
output => cast50_output_wire -- output.wire
);
cast51 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay_output_wire, -- input.wire
output => cast51_output_wire -- output.wire
);
cast52 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator1_result_wire, -- input.wire
output => cast52_output_wire -- output.wire
);
cast53 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => if_statement_true_wire, -- input.wire
output => cast53_output_wire -- output.wire
);
end architecture rtl; -- of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module
|
mit
|
6efd9959f5e52e8ab68ab41e13295f09
| 0.559797 | 3.420398 | false | false | false | false |
TUCircle/homework
|
VHDL/Aufgabe2.4.vhdl
| 2 | 539 |
--Gatterschaltung zu Aufgabe 2.4
--Christian Rebischke 18.4.2014
-- x Eingänge, y Ausgang, z "zwischenstationen"
library IEEE;
use IEEE.std_logic_1164.all;
entity Gatterschaltung is
port(x: in STD_LOGIC_VECTOR(2 DOWNTO 0);
y: out STD_LOGIC);
end entity;
architecture test of Gatterschaltung is
signal z: STD_LOGIC_VECTOR(4 DOWNTO 0);
begin
z(0) <= not(x(1));
z(1) <= not(x(2));
z(2) <= x(0) nand x(1);
z(3) <= x(0) nand (z(0) and x(2));
z(4) <= x(0) nand z(1);
y <= z(2) nand (z(3) and z(4));
end architecture;
|
gpl-3.0
|
c2b47c1503d4a80a86503c98941430fd
| 0.630112 | 2.456621 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/usb_system/altera_avalon_st_clock_crosser/_primary.vhd
| 2 | 1,226 |
library verilog;
use verilog.vl_types.all;
entity altera_avalon_st_clock_crosser is
generic(
SYMBOLS_PER_BEAT: integer := 1;
BITS_PER_SYMBOL : integer := 8;
FORWARD_SYNC_DEPTH: integer := 2;
BACKWARD_SYNC_DEPTH: integer := 2;
USE_OUTPUT_PIPELINE: integer := 1
);
port(
in_clk : in vl_logic;
in_reset : in vl_logic;
in_ready : out vl_logic;
in_valid : in vl_logic;
in_data : in vl_logic_vector;
out_clk : in vl_logic;
out_reset : in vl_logic;
out_ready : in vl_logic;
out_valid : out vl_logic;
out_data : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of SYMBOLS_PER_BEAT : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_SYMBOL : constant is 1;
attribute mti_svvh_generic_type of FORWARD_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of BACKWARD_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of USE_OUTPUT_PIPELINE : constant is 1;
end altera_avalon_st_clock_crosser;
|
apache-2.0
|
d9325ab5b2cdeb969fe9c59ca32e0220
| 0.579119 | 3.595308 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/hierarchy/GroupOfBlockrams.vhd
| 1 | 8,858 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- RAM where each port has an independet clock.
-- It can be configured to true dual port RAM etc.
-- It can also be configured to have write mask or to be composed from multiple smaller memories.
--
-- :note: write-first variant
--
-- .. hwt-autodoc::
--
ENTITY RamMultiClock IS
GENERIC(
ADDR_WIDTH : INTEGER := 8;
DATA_WIDTH : INTEGER := 64;
HAS_BE : BOOLEAN := FALSE;
INIT_DATA : STRING := "None";
MAX_BLOCK_DATA_WIDTH : STRING := "None";
PORT_CNT : INTEGER := 2
);
PORT(
port_0_addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
port_0_clk : IN STD_LOGIC;
port_0_din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
port_0_dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
port_0_en : IN STD_LOGIC;
port_0_we : IN STD_LOGIC;
port_1_addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
port_1_clk : IN STD_LOGIC;
port_1_din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
port_1_dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
port_1_en : IN STD_LOGIC;
port_1_we : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF RamMultiClock IS
TYPE arr_t_0 IS ARRAY (255 DOWNTO 0) OF STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL ram_memory : arr_t_0;
BEGIN
assig_process_port_0_dout: PROCESS(port_0_clk)
BEGIN
IF RISING_EDGE(port_0_clk) THEN
IF port_0_en = '1' THEN
IF port_0_we = '1' THEN
ram_memory(TO_INTEGER(UNSIGNED(port_0_addr))) <= port_0_din;
END IF;
port_0_dout <= ram_memory(TO_INTEGER(UNSIGNED(port_0_addr)));
ELSE
port_0_dout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
END IF;
END IF;
END PROCESS;
assig_process_port_1_dout: PROCESS(port_1_clk)
BEGIN
IF RISING_EDGE(port_1_clk) THEN
IF port_1_en = '1' THEN
IF port_1_we = '1' THEN
ram_memory(TO_INTEGER(UNSIGNED(port_1_addr))) <= port_1_din;
END IF;
port_1_dout <= ram_memory(TO_INTEGER(UNSIGNED(port_1_addr)));
ELSE
port_1_dout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
END IF;
END IF;
END PROCESS;
ASSERT ADDR_WIDTH = 8 REPORT "Generated only for this value" SEVERITY failure;
ASSERT DATA_WIDTH = 64 REPORT "Generated only for this value" SEVERITY failure;
ASSERT HAS_BE = FALSE REPORT "Generated only for this value" SEVERITY failure;
ASSERT INIT_DATA = "None" REPORT "Generated only for this value" SEVERITY failure;
ASSERT MAX_BLOCK_DATA_WIDTH = "None" REPORT "Generated only for this value" SEVERITY failure;
ASSERT PORT_CNT = 2 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY GroupOfBlockrams IS
GENERIC(
ADDR_WIDTH : INTEGER := 8;
DATA_WIDTH : INTEGER := 64
);
PORT(
addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk : IN STD_LOGIC;
en : IN STD_LOGIC;
in_r_a : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
in_r_b : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
in_w_a : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
in_w_b : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
out_r_a : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
out_r_b : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
out_w_a : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
out_w_b : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
we : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF GroupOfBlockrams IS
--
-- RAM where each port has an independet clock.
-- It can be configured to true dual port RAM etc.
-- It can also be configured to have write mask or to be composed from multiple smaller memories.
--
-- :note: write-first variant
--
-- .. hwt-autodoc::
--
COMPONENT RamMultiClock IS
GENERIC(
ADDR_WIDTH : INTEGER := 8;
DATA_WIDTH : INTEGER := 64;
HAS_BE : BOOLEAN := FALSE;
INIT_DATA : STRING := "None";
MAX_BLOCK_DATA_WIDTH : STRING := "None";
PORT_CNT : INTEGER := 2
);
PORT(
port_0_addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
port_0_clk : IN STD_LOGIC;
port_0_din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
port_0_dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
port_0_en : IN STD_LOGIC;
port_0_we : IN STD_LOGIC;
port_1_addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
port_1_clk : IN STD_LOGIC;
port_1_din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
port_1_dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
port_1_en : IN STD_LOGIC;
port_1_we : IN STD_LOGIC
);
END COMPONENT;
SIGNAL sig_bramR_port_0_addr : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sig_bramR_port_0_clk : STD_LOGIC;
SIGNAL sig_bramR_port_0_din : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_bramR_port_0_dout : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_bramR_port_0_en : STD_LOGIC;
SIGNAL sig_bramR_port_0_we : STD_LOGIC;
SIGNAL sig_bramR_port_1_addr : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sig_bramR_port_1_clk : STD_LOGIC;
SIGNAL sig_bramR_port_1_din : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_bramR_port_1_dout : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_bramR_port_1_en : STD_LOGIC;
SIGNAL sig_bramR_port_1_we : STD_LOGIC;
SIGNAL sig_bramW_port_0_addr : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sig_bramW_port_0_clk : STD_LOGIC;
SIGNAL sig_bramW_port_0_din : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_bramW_port_0_dout : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_bramW_port_0_en : STD_LOGIC;
SIGNAL sig_bramW_port_0_we : STD_LOGIC;
SIGNAL sig_bramW_port_1_addr : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sig_bramW_port_1_clk : STD_LOGIC;
SIGNAL sig_bramW_port_1_din : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_bramW_port_1_dout : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL sig_bramW_port_1_en : STD_LOGIC;
SIGNAL sig_bramW_port_1_we : STD_LOGIC;
BEGIN
bramR_inst: RamMultiClock GENERIC MAP(
ADDR_WIDTH => 8,
DATA_WIDTH => 64,
HAS_BE => FALSE,
INIT_DATA => "None",
MAX_BLOCK_DATA_WIDTH => "None",
PORT_CNT => 2
) PORT MAP(
port_0_addr => sig_bramR_port_0_addr,
port_0_clk => sig_bramR_port_0_clk,
port_0_din => sig_bramR_port_0_din,
port_0_dout => sig_bramR_port_0_dout,
port_0_en => sig_bramR_port_0_en,
port_0_we => sig_bramR_port_0_we,
port_1_addr => sig_bramR_port_1_addr,
port_1_clk => sig_bramR_port_1_clk,
port_1_din => sig_bramR_port_1_din,
port_1_dout => sig_bramR_port_1_dout,
port_1_en => sig_bramR_port_1_en,
port_1_we => sig_bramR_port_1_we
);
bramW_inst: RamMultiClock GENERIC MAP(
ADDR_WIDTH => 8,
DATA_WIDTH => 64,
HAS_BE => FALSE,
INIT_DATA => "None",
MAX_BLOCK_DATA_WIDTH => "None",
PORT_CNT => 2
) PORT MAP(
port_0_addr => sig_bramW_port_0_addr,
port_0_clk => sig_bramW_port_0_clk,
port_0_din => sig_bramW_port_0_din,
port_0_dout => sig_bramW_port_0_dout,
port_0_en => sig_bramW_port_0_en,
port_0_we => sig_bramW_port_0_we,
port_1_addr => sig_bramW_port_1_addr,
port_1_clk => sig_bramW_port_1_clk,
port_1_din => sig_bramW_port_1_din,
port_1_dout => sig_bramW_port_1_dout,
port_1_en => sig_bramW_port_1_en,
port_1_we => sig_bramW_port_1_we
);
out_r_a <= sig_bramR_port_0_dout;
out_r_b <= sig_bramR_port_1_dout;
out_w_a <= sig_bramW_port_0_dout;
out_w_b <= sig_bramW_port_1_dout;
sig_bramR_port_0_addr <= addr;
sig_bramR_port_0_clk <= clk;
sig_bramR_port_0_din <= in_r_a;
sig_bramR_port_0_en <= en;
sig_bramR_port_0_we <= we;
sig_bramR_port_1_addr <= addr;
sig_bramR_port_1_clk <= clk;
sig_bramR_port_1_din <= in_r_b;
sig_bramR_port_1_en <= en;
sig_bramR_port_1_we <= we;
sig_bramW_port_0_addr <= addr;
sig_bramW_port_0_clk <= clk;
sig_bramW_port_0_din <= in_w_a;
sig_bramW_port_0_en <= en;
sig_bramW_port_0_we <= we;
sig_bramW_port_1_addr <= addr;
sig_bramW_port_1_clk <= clk;
sig_bramW_port_1_din <= in_w_b;
sig_bramW_port_1_en <= en;
sig_bramW_port_1_we <= we;
ASSERT ADDR_WIDTH = 8 REPORT "Generated only for this value" SEVERITY failure;
ASSERT DATA_WIDTH = 64 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
|
mit
|
6fc23014881fbd1f8e2fa8807a2e1c00
| 0.586476 | 3.194374 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_orbit_intlk/orbit_intlk_trans.vhd
| 1 | 21,913 |
------------------------------------------------------------------------------
-- Title : BPM orbit translation interlock
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2022-06-12
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Module for translation orbit interlock
-------------------------------------------------------------------------------
-- Copyright (c) 2020 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2020-06-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- General cores
use work.gencores_pkg.all;
-- Orbit interlock cores
use work.orbit_intlk_pkg.all;
entity orbit_intlk_trans is
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Interlock enable and limits signals
-----------------------------
-- Translation interlock on/off
intlk_trans_en_i : in std_logic;
-- Translation interlock clear
intlk_trans_clr_i : in std_logic;
intlk_trans_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-----------------------------
-- Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic
);
end orbit_intlk_trans;
architecture rtl of orbit_intlk_trans is
-- constants
constant c_ADC_WIDTH : natural := g_ADC_WIDTH;
constant c_DECIM_WIDTH : natural := g_DECIM_WIDTH;
constant c_INTLK_LMT_WIDTH : natural := g_INTLK_LMT_WIDTH;
-- types
type t_bit_array is array (natural range <>) of std_logic;
subtype t_adc_data is std_logic_vector(c_adc_width-1 downto 0);
type t_adc_data_array is array (natural range <>) of t_adc_data;
subtype t_adc_tag is std_logic_vector(0 downto 0);
type t_adc_tag_array is array (natural range <>) of t_adc_tag;
subtype t_decim_data is std_logic_vector(c_decim_width-1 downto 0);
type t_decim_data_array is array (natural range <>) of t_decim_data;
subtype t_intlk_lmt_data is std_logic_vector(c_intlk_lmt_width-1 downto 0);
type t_intlk_lmt_data_array is array (natural range <>) of t_intlk_lmt_data;
type t_adc_data_array2d is array (natural range <>, natural range <>) of t_adc_data;
type t_decim_data_array2d is array (natural range <>, natural range <>) of t_decim_data;
--signals
-- input mangling
signal adc_array : t_adc_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal adc_tag_array : t_adc_tag_array(c_NUM_BPMS-1 downto 0);
signal adc_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0);
signal decim_pos_array : t_decim_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal decim_pos_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0);
-- interlock limits
signal intlk_trans_max : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0);
signal intlk_trans_max_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal intlk_trans_max_n : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0);
signal intlk_trans_min : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0);
signal intlk_trans_min_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0);
-- valid AND
signal adc_valid_and : t_bit_array(c_NUM_BPMS downto 0);
signal adc_valid : std_logic;
signal decim_pos_valid_and : t_bit_array(c_NUM_BPMS downto 0);
signal decim_pos_valid : std_logic;
-- translation interlock
signal trans_sum : t_decim_data_array(c_NUM_CHANNELS-1 downto 0);
signal trans_sum_reg : t_decim_data_array(c_NUM_CHANNELS-1 downto 0);
signal trans_sum_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_sum_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans : t_decim_data_array(c_NUM_CHANNELS-1 downto 0);
signal trans_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_n : t_decim_data_array(c_NUM_CHANNELS-1 downto 0);
signal trans_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_bigger : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_bigger_comb : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_bigger_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_bigger_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_bigger_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_smaller : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_smaller_comb : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_smaller_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_smaller_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_smaller_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_intlk_det_bigger_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_intlk_bigger_ltc_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_intlk_bigger_or : t_bit_array(c_NUM_CHANNELS downto 0);
signal trans_intlk_bigger_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_intlk_bigger_ltc_or : t_bit_array(c_NUM_CHANNELS downto 0);
signal trans_intlk_bigger_ltc : std_logic;
signal trans_intlk_bigger_any : std_logic;
signal trans_intlk_bigger : std_logic;
signal trans_intlk_det_smaller_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_intlk_smaller_ltc_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_intlk_smaller_or : t_bit_array(c_NUM_CHANNELS downto 0);
signal trans_intlk_smaller_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal trans_intlk_smaller_ltc_or : t_bit_array(c_NUM_CHANNELS downto 0);
signal trans_intlk_smaller_ltc : std_logic;
signal trans_intlk_smaller_any : std_logic;
signal trans_intlk_smaller : std_logic;
begin
---------------------------------
-- Signal mangling
--------------------------------
-- Downstream
adc_array(c_BPM_DS_IDX, 0) <= adc_ds_ch0_swap_i;
adc_array(c_BPM_DS_IDX, 1) <= adc_ds_ch1_swap_i;
adc_array(c_BPM_DS_IDX, 2) <= adc_ds_ch2_swap_i;
adc_array(c_BPM_DS_IDX, 3) <= adc_ds_ch3_swap_i;
adc_tag_array(c_BPM_DS_IDX) <= adc_ds_tag_i;
adc_valid_array(c_BPM_DS_IDX) <= adc_ds_swap_valid_i;
decim_pos_array(c_BPM_DS_IDX, 0) <= decim_ds_pos_x_i;
decim_pos_array(c_BPM_DS_IDX, 1) <= decim_ds_pos_y_i;
decim_pos_array(c_BPM_DS_IDX, 2) <= decim_ds_pos_q_i;
decim_pos_array(c_BPM_DS_IDX, 3) <= decim_ds_pos_sum_i;
decim_pos_valid_array(c_BPM_DS_IDX) <= decim_ds_pos_valid_i;
-- Upwnstream
adc_array(c_BPM_US_IDX, 0) <= adc_us_ch0_swap_i;
adc_array(c_BPM_US_IDX, 1) <= adc_us_ch1_swap_i;
adc_array(c_BPM_US_IDX, 2) <= adc_us_ch2_swap_i;
adc_array(c_BPM_US_IDX, 3) <= adc_us_ch3_swap_i;
adc_tag_array(c_BPM_US_IDX) <= adc_us_tag_i;
adc_valid_array(c_BPM_US_IDX) <= adc_us_swap_valid_i;
decim_pos_array(c_BPM_US_IDX, 0) <= decim_us_pos_x_i;
decim_pos_array(c_BPM_US_IDX, 1) <= decim_us_pos_y_i;
decim_pos_array(c_BPM_US_IDX, 2) <= decim_us_pos_q_i;
decim_pos_array(c_BPM_US_IDX, 3) <= decim_us_pos_sum_i;
decim_pos_valid_array(c_BPM_US_IDX) <= decim_us_pos_valid_i;
-- Interlock limits
-- X limits
intlk_trans_max(0) <= intlk_trans_max_x_i;
intlk_trans_min(0) <= intlk_trans_min_x_i;
-- Y limits
intlk_trans_max(1) <= intlk_trans_max_y_i;
intlk_trans_min(1) <= intlk_trans_min_y_i;
----------------------------------
-- Calculate translation
----------------------------------
-- ANDing ADC valids
adc_valid_and(0) <= '1';
gen_adc_valid : for i in 0 to c_NUM_BPMS-1 generate
adc_valid_and(i+1) <= adc_valid_and(i) and adc_valid_array(i);
end generate;
adc_valid <= adc_valid_and(c_NUM_BPMS);
-- ANDing DECIM valids
decim_pos_valid_and(0) <= '1';
gen_decim_pos_valid : for i in 0 to c_NUM_BPMS-1 generate
decim_pos_valid_and(i+1) <= decim_pos_valid_and(i) and decim_pos_valid_array(i);
end generate;
decim_pos_valid <= decim_pos_valid_and(c_NUM_BPMS);
-------------------------------------------------------------------------
-- Translation interlock detector. Only for X and Y.
-- Calculation is a simple (us = upstream, ds = downstream):
-- x_trans = (x_us + x_ds) / 2
-- y_trans = (y_us + y_ds) / 2
-------------------------------------------------------------------------
gen_trans_intlk : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
----------------------------------
-- Calculate translation
----------------------------------
cmp_trans_adder : gc_big_adder2
generic map (
g_data_bits => c_DECIM_WIDTH
)
port map (
clk_i => fs_clk_i,
stall_i => '0',
valid_i => decim_pos_valid,
a_i => decim_pos_array(c_BPM_US_IDX, i),
b_i => decim_pos_array(c_BPM_DS_IDX, i),
x2_o => trans_sum(i),
c2x2_valid_o => trans_sum_valid(i)
);
-- gc_big_adder2 outputs are unregistered. So register them.
p_trans_reg : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
trans_sum_valid_reg(i) <= '0';
else
if trans_sum_valid(i) = '1' then
trans_sum_reg(i) <= trans_sum(i);
end if;
trans_sum_valid_reg(i) <= trans_sum_valid(i);
end if;
end if;
end process;
-- Divide by 2 and take absolute value for comparison
p_trans_divide : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
trans_valid(i) <= '0';
else
if trans_sum_valid_reg(i) = '1' then
trans(i) <= std_logic_vector(shift_right(signed(trans_sum_reg(i)), 1));
end if;
trans_valid(i) <= trans_sum_valid_reg(i);
end if;
end if;
end process;
----------------------------------
-- Detect position > Threshold
----------------------------------
-- Compare with threshold. Use the simple identity that:
-- A > B is the same as A + (-B) and we check if MSB Carry
-- is 1
cmp_trans_thold_bigger : gc_big_adder2
generic map (
g_data_bits => c_DECIM_WIDTH
)
port map (
clk_i => fs_clk_i,
stall_i => '0',
valid_i => trans_valid(i),
a_i => trans(i),
b_i => intlk_trans_max_n(i),
c_i => '1',
c2_o => trans_bigger_comb(i),
c2x2_valid_o => trans_bigger_valid(i)
);
intlk_trans_max_n(i) <= not intlk_trans_max(i);
-- comparison of different sign operands fails with the above method.
-- Just compare the sign bits, for these cases.
trans_high_bit(i) <= trans(i)(trans(i)'high);
intlk_trans_max_high_bit(i) <= intlk_trans_max(i)(intlk_trans_max(i)'high);
trans_bigger(i) <= trans_bigger_comb(i) when
(trans_high_bit(i) xnor intlk_trans_max_high_bit(i)) = '1' else
intlk_trans_max_high_bit(i);
-- gc_big_adder2 outputs are unregistered. So register them.
p_trans_thold_bigger_reg : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
trans_bigger_valid_reg(i) <= '0';
else
if trans_bigger_valid(i) = '1' then
trans_bigger_reg(i) <= trans_bigger(i);
end if;
trans_bigger_valid_reg(i) <= trans_bigger_valid(i);
end if;
end if;
end process;
----------------------------------
-- Detect position < Threshold
----------------------------------
-- Compare with threshold. Use the simple identity that:
-- A < B is the same as -A > -B = -A + B > 0 and we check
-- if MSB Carry is 1
cmp_trans_thold_smaller : gc_big_adder2
generic map (
g_data_bits => c_DECIM_WIDTH
)
port map (
clk_i => fs_clk_i,
stall_i => '0',
valid_i => trans_valid(i),
a_i => trans_n(i),
b_i => intlk_trans_min(i),
c_i => '1',
c2_o => trans_smaller_comb(i),
c2x2_valid_o => trans_smaller_valid(i)
);
trans_n(i) <= not trans(i);
-- comparison of different sign operands fails with the above method.
-- Just compare the sign bits, for these cases.
intlk_trans_min_high_bit(i) <= intlk_trans_min(i)(intlk_trans_min(i)'high);
trans_smaller(i) <= trans_smaller_comb(i) when
(trans_high_bit(i) xnor intlk_trans_min_high_bit(i)) = '1' else
trans_high_bit(i);
-- gc_big_adder2 outputs are unregistered. So register them.
p_trans_thold_smaller_reg : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
trans_smaller_valid_reg(i) <= '0';
else
if trans_smaller_valid(i) = '1' then
trans_smaller_reg(i) <= trans_smaller(i);
end if;
trans_smaller_valid_reg(i) <= trans_smaller_valid(i);
end if;
end if;
end process;
----------------------------------
-- Latch interlocks
----------------------------------
trans_intlk_det_bigger_all(i) <= trans_bigger_reg(i) and trans_bigger_valid_reg(i);
trans_intlk_det_smaller_all(i) <= trans_smaller_reg(i) and trans_smaller_valid_reg(i);
-- latch all interlocks
p_latch : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
trans_intlk_bigger_ltc_all(i) <= '0';
trans_intlk_smaller_ltc_all(i) <= '0';
else
-- latch up translation interlock status
-- only clear on "clear" signal
if intlk_trans_clr_i = '1' then
trans_intlk_bigger_ltc_all(i) <= '0';
elsif trans_intlk_det_bigger_all(i) = '1' and
intlk_trans_en_i = '1' then
trans_intlk_bigger_ltc_all(i) <= '1';
end if;
if intlk_trans_clr_i = '1' then
trans_intlk_smaller_ltc_all(i) <= '0';
elsif trans_intlk_det_smaller_all(i) = '1' and
intlk_trans_en_i = '1' then
trans_intlk_smaller_ltc_all(i) <= '1';
end if;
-- register translation interlock when active
if intlk_trans_clr_i = '1' or intlk_trans_en_i = '0' then
trans_intlk_bigger_all(i) <= '0';
else
trans_intlk_bigger_all(i) <= trans_intlk_det_bigger_all(i);
end if;
if intlk_trans_clr_i = '1' or intlk_trans_en_i = '0' then
trans_intlk_smaller_all(i) <= '0';
else
trans_intlk_smaller_all(i) <= trans_intlk_det_smaller_all(i);
end if;
end if;
end if;
end process;
end generate;
intlk_trans_bigger_ltc_x_o <= trans_intlk_bigger_ltc_all(c_CHAN_X_IDX);
intlk_trans_bigger_ltc_y_o <= trans_intlk_bigger_ltc_all(c_CHAN_Y_IDX);
intlk_trans_bigger_x_o <= trans_intlk_bigger_all(c_CHAN_X_IDX);
intlk_trans_bigger_y_o <= trans_intlk_bigger_all(c_CHAN_Y_IDX);
intlk_trans_smaller_ltc_x_o <= trans_intlk_smaller_ltc_all(c_CHAN_X_IDX);
intlk_trans_smaller_ltc_y_o <= trans_intlk_smaller_ltc_all(c_CHAN_Y_IDX);
intlk_trans_smaller_x_o <= trans_intlk_smaller_all(c_CHAN_X_IDX);
intlk_trans_smaller_y_o <= trans_intlk_smaller_all(c_CHAN_Y_IDX);
----------------------------------
-- Translation interlock merging
----------------------------------
----------------------------------
-- Bigger
----------------------------------
trans_intlk_bigger_or(0) <= '0';
-- ORing all trans_bigger
gen_trans_intlk_bigger : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
trans_intlk_bigger_or(i+1) <= trans_intlk_bigger_or(i) or trans_intlk_bigger_all(i);
end generate;
trans_intlk_bigger <= trans_intlk_bigger_or(c_INTLK_GEN_UPTO_CHANNEL+1);
intlk_trans_bigger_o <= trans_intlk_bigger;
intlk_trans_bigger_any_o <= trans_intlk_bigger;
trans_intlk_bigger_ltc_or(0) <= '0';
-- ORing all trans_bigger_ltc
gen_trans_intlk_bigger_ltc : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
trans_intlk_bigger_ltc_or(i+1) <= trans_intlk_bigger_ltc_or(i) or trans_intlk_bigger_ltc_all(i);
end generate;
trans_intlk_bigger_ltc <= trans_intlk_bigger_ltc_or(c_INTLK_GEN_UPTO_CHANNEL+1);
intlk_trans_bigger_ltc_o <= trans_intlk_bigger_ltc;
----------------------------------
-- Smaller
----------------------------------
trans_intlk_smaller_or(0) <= '0';
-- ORing all trans_smaller
gen_trans_intlk_smaller : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
trans_intlk_smaller_or(i+1) <= trans_intlk_smaller_or(i) or trans_intlk_smaller_all(i);
end generate;
trans_intlk_smaller <= trans_intlk_smaller_or(c_INTLK_GEN_UPTO_CHANNEL+1);
intlk_trans_smaller_o <= trans_intlk_smaller;
intlk_trans_smaller_any_o <= trans_intlk_smaller;
trans_intlk_smaller_ltc_or(0) <= '0';
-- ORing all trans_smaller_ltc
gen_trans_intlk_smaller_ltc : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
trans_intlk_smaller_ltc_or(i+1) <= trans_intlk_smaller_ltc_or(i) or trans_intlk_smaller_ltc_all(i);
end generate;
trans_intlk_smaller_ltc <= trans_intlk_smaller_ltc_or(c_INTLK_GEN_UPTO_CHANNEL+1);
intlk_trans_smaller_ltc_o <= trans_intlk_smaller_ltc;
end rtl;
|
lgpl-3.0
|
1ad34e449409cc7190f02ff52fa46a9f
| 0.544608 | 3.24637 | false | false | false | false |
elahejalalpour/CoDesign
|
Phase-2/fsl.vhd
| 1 | 11,235 |
------------------------------------------------------------------------------
-- fsl - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: fsl
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Tue Jun 23 12:23:46 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hem is
port(a,b : in std_logic_vector(3 downto 0);
r : out std_logic_vector(7 downto 0));
end hem;
architecture rtl of hem is
component mul is
port(a,b : in std_logic_vector(1 downto 0);
cout : out std_logic_vector(3 downto 0));
end component;
signal in1,in2,in3,in4 : std_logic_vector(1 downto 0);
begin
in1(0) <= a(0);
in1(1) <= b(2);
in2(0) <= a(2);
in2(1) <= b(0);
in3(0) <= a(1);
in3(1) <= b(3);
in4(0) <= a(3);
in4(1) <= b(1);
M0: mul port map (in1,in2,r(3 downto 0));
M1: mul port map (in3,in4,r(7 downto 4));
end rtl;
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mul is
port(a,b : in std_logic_vector(1 downto 0);
cout : out std_logic_vector(3 downto 0));
end mul;
architecture rtl of mul is
component ha is
port(a,b : in std_logic;
s,c : out std_logic);
end component;
signal y : std_logic;
begin
cout(0) <= a(0) and b(0);
L1: ha port map (a(0) and b(1),a(1) and b(0),cout(1),y);
L2: ha port map (y,a(1) and b(1),cout(2),cout(3));
end rtl;
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hea is
port(a,b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(7 downto 0));
end hea;
architecture rtl of hea is
component ha is
port(a,b : in std_logic;
s,c : out std_logic);
end component;
begin
L0: ha port map(b(3),a(0),s(0),s(1));
L1: ha port map(b(2),a(1),s(2),s(3));
L2: ha port map(b(1),a(2),s(4),s(5));
L3: ha port map(b(0),a(3),s(6),s(7));
end rtl;
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ha is
port(a,b : in std_logic;
s,c : out std_logic);
end ha;
architecture rtl of ha is
begin
s <= a xor b;
c <= a and b;
end rtl;
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity fsl is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
attribute SIGIS of FSL_M_Clk : signal is "Clk";
end fsl;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
-- In this section, we povide an example implementation of ENTITY fsl
-- that does the following:
--
-- 1. Read all inputs
-- 2. Add each input to the contents of register 'sum' which
-- acts as an accumulator
-- 3. After all the inputs have been read, write out the
-- content of 'sum' into the output FSL bus NUMBER_OF_OUTPUT_WORDS times
--
-- You will need to modify this example or implement a new architecture for
-- ENTITY fsl to implement your coprocessor
architecture EXAMPLE of fsl is
-- Total number of input data.
constant NUMBER_OF_INPUT_WORDS : natural := 1;
-- Total number of output data
constant NUMBER_OF_OUTPUT_WORDS : natural := 1;
type STATE_TYPE is (Idle, Read_Inputs, Write_Outputs);
signal state : STATE_TYPE;
-- Accumulator to hold sum of inputs read at any point in time
signal sum : std_logic_vector(0 to 31);
-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1;
signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1;
component hea is
port( a,b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(7 downto 0));
end component;
component hem is
port( a,b : in std_logic_vector(3 downto 0);
r : out std_logic_vector(7 downto 0));
end component;
signal temp : std_logic_vector(0 to 31);
signal tmp_out1,tmp_out2 : std_logic_vector(0 to 15);
begin
adder1 : hea port map(temp(28 to 31),temp(24 to 27),tmp_out1(8 to 15));
adder2 : hea port map(temp(20 to 23),temp(16 to 19),tmp_out1(0 to 7));
mul1 : hem port map(temp(28 to 31),temp(24 to 27),tmp_out2(8 to 15));
mul2 : hem port map(temp(20 to 23),temp(16 to 19),tmp_out2(0 to 7));
-- CAUTION:
-- The sequence in which data are read in and written out should be
-- consistent with the sequence they are written and read in the
-- driver's fsl.c file
FSL_S_Read <= FSL_S_Exists when state = Read_Inputs else '0';
FSL_M_Write <= not FSL_M_Full when state = Write_Outputs else '0';
FSL_M_Data(16 to 31) <= tmp_out1 when temp(15) = '0' else
tmp_out2;
FSL_M_Data(0 to 15) <= "0000000000000000";
The_SW_accelerator : process (FSL_Clk) is
begin -- process The_SW_accelerator
if FSL_Clk'event and FSL_Clk = '1' then -- Rising clock edge
if FSL_Rst = '1' then -- Synchronous reset (active high)
-- CAUTION: make sure your reset polarity is consistent with the
-- system reset polarity
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
sum <= (others => '0');
else
case state is
when Idle =>
if (FSL_S_Exists = '1') then
state <= Read_Inputs;
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
sum <= (others => '0');
end if;
when Read_Inputs =>
if (FSL_S_Exists = '1') then
-- Coprocessor function (Adding) happens here
-- sum <= std_logic_vector(unsigned(sum) + unsigned(FSL_S_Data));
temp <= FSL_S_Data;
if (nr_of_reads = 0) then
state <= Write_Outputs;
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
else
nr_of_reads <= nr_of_reads - 1;
end if;
end if;
when Write_Outputs =>
if (nr_of_writes = 0) then
state <= Idle;
else
if (FSL_M_Full = '0') then
nr_of_writes <= nr_of_writes - 1;
end if;
end if;
end case;
end if;
end if;
end process The_SW_accelerator;
end architecture EXAMPLE;
|
gpl-2.0
|
4b9a7614523df6dae277c15556cd51ab
| 0.495772 | 3.723898 | false | false | false | false |
nanomolina/MIPS
|
prueba/imem.vhd
| 3 | 2,427 |
-------------------------------------------------------------------------------
--
-- Title : imem
-- Design : Mips
-- Author : Eduardo Sanchez
-- Company : Famaf
--
-------------------------------------------------------------------------------
--
-- File : imem.vhd
--
-------------------------------------------------------------------------------
--
-- Description : Archivo con el diseño de la memoria ROM del procesador MIPS.
-- Para mantener un diseño corto, la memoria solo puede contener hasta 64
-- instrucciones (palabras) de 32 bits(aunque podria direccionar mas memoria)
-- Inicialmente, al salir de reset, carga en la memoria el archivo MIPS_SOFT_FILE
-- con el programa a ejecutar.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
--library WORK;
--use WORK.components.all;
entity imem is -- instruction memory
port(a: in STD_LOGIC_VECTOR(5 downto 0);
rd: out STD_LOGIC_VECTOR(31 downto 0));
end;
architecture behave of imem is
constant MAX_BOUND: Integer := 64;
constant MIPS_SOFT_FILE: string := "mips_pipeline.dat";
begin
process is
file mem_file: TEXT;
variable L: line;
variable ch: character;
variable index, result: integer;
type ramtype is array (MAX_BOUND-1 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
variable mem: ramtype;
begin
-- initialize memory from file
for i in 0 to MAX_BOUND-1 loop -- set all contents low
mem(conv_integer(i)) := CONV_STD_LOGIC_VECTOR(0, 32);
end loop;
index := 0;
FILE_OPEN(mem_file, MIPS_SOFT_FILE, READ_MODE);
while not endfile(mem_file) loop
readline(mem_file, L);
result := 0;
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := result*16 + character'pos(ch)-character'pos('0');
elsif 'a' <= ch and ch <= 'f' then
result := result*16 + character'pos(ch)-character'pos('a')+10;
else report "Format error on line " & integer'image(index)
severity error;
end if;
end loop;
mem(index) := CONV_STD_LOGIC_VECTOR(result, 32);
index := index + 1;
end loop;
-- read memory
loop
rd <= mem(CONV_INTEGER(a));
wait on a;
end loop;
end process;
end;
|
gpl-3.0
|
a84c04a44b1a7cfc6f64c43f3f072469
| 0.543057 | 3.86465 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_cmp_eq/fp_cmp_eq.vhd
| 1 | 5,884 |
-- megafunction wizard: %ALTERA_FP_FUNCTIONS v17.0%
-- GENERATION: XML
-- fp_cmp_eq.vhd
-- Generated using ACDS version 17.0 595
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fp_cmp_eq is
port (
clk : in std_logic := '0'; -- clk.clk
areset : in std_logic := '0'; -- areset.reset
a : in std_logic_vector(31 downto 0) := (others => '0'); -- a.a
b : in std_logic_vector(31 downto 0) := (others => '0'); -- b.b
q : out std_logic_vector(0 downto 0) -- q.q
);
end entity fp_cmp_eq;
architecture rtl of fp_cmp_eq is
component fp_cmp_eq_0002 is
port (
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(0 downto 0) -- q
);
end component fp_cmp_eq_0002;
begin
fp_cmp_eq_inst : component fp_cmp_eq_0002
port map (
clk => clk, -- clk.clk
areset => areset, -- areset.reset
a => a, -- a.a
b => b, -- b.b
q => q -- q.q
);
end architecture rtl; -- of fp_cmp_eq
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_fp_functions" version="17.0" >
-- Retrieval info: <generic name="FUNCTION_FAMILY" value="COMPARE" />
-- Retrieval info: <generic name="ARITH_function" value="ADD" />
-- Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
-- Retrieval info: <generic name="ALL_function" value="ADD" />
-- Retrieval info: <generic name="EXP_LOG_function" value="EXP10" />
-- Retrieval info: <generic name="TRIG_function" value="SIN" />
-- Retrieval info: <generic name="COMPARE_function" value="EQ" />
-- Retrieval info: <generic name="ROOTS_function" value="SQRT" />
-- Retrieval info: <generic name="fp_format" value="single" />
-- Retrieval info: <generic name="fp_exp" value="8" />
-- Retrieval info: <generic name="fp_man" value="23" />
-- Retrieval info: <generic name="exponent_width" value="23" />
-- Retrieval info: <generic name="frequency_target" value="25" />
-- Retrieval info: <generic name="latency_target" value="2" />
-- Retrieval info: <generic name="performance_goal" value="frequency" />
-- Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
-- Retrieval info: <generic name="faithful_rounding" value="false" />
-- Retrieval info: <generic name="gen_enable" value="false" />
-- Retrieval info: <generic name="divide_type" value="0" />
-- Retrieval info: <generic name="select_signal_enable" value="false" />
-- Retrieval info: <generic name="scale_by_pi" value="false" />
-- Retrieval info: <generic name="number_of_inputs" value="2" />
-- Retrieval info: <generic name="trig_no_range_reduction" value="false" />
-- Retrieval info: <generic name="report_resources_to_xml" value="false" />
-- Retrieval info: <generic name="fxpt_width" value="32" />
-- Retrieval info: <generic name="fxpt_fraction" value="0" />
-- Retrieval info: <generic name="fxpt_sign" value="1" />
-- Retrieval info: <generic name="fp_out_format" value="single" />
-- Retrieval info: <generic name="fp_out_exp" value="8" />
-- Retrieval info: <generic name="fp_out_man" value="23" />
-- Retrieval info: <generic name="fp_in_format" value="single" />
-- Retrieval info: <generic name="fp_in_exp" value="8" />
-- Retrieval info: <generic name="fp_in_man" value="23" />
-- Retrieval info: <generic name="enable_hard_fp" value="true" />
-- Retrieval info: <generic name="manual_dsp_planning" value="true" />
-- Retrieval info: <generic name="forceRegisters" value="1111" />
-- Retrieval info: <generic name="selected_device_family" value="MAX 10" />
-- Retrieval info: <generic name="selected_device_speedgrade" value="6" />
-- Retrieval info: </instance>
-- IPFS_FILES : fp_cmp_eq.vho
-- RELATED_FILES: fp_cmp_eq.vhd, dspba_library_package.vhd, dspba_library.vhd, fp_cmp_eq_0002.vhd
|
mit
|
3e26cfc2c7415bba971d032c3e7dc7d4
| 0.64242 | 3.465253 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/ParametrizationExample.vhd
| 1 | 2,233 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY ParametrizationExample IS
GENERIC(
PARAM_0 : INTEGER := 0;
PARAM_10 : INTEGER := 10;
PARAM_1_sll_512 : STD_LOGIC_VECTOR(512 DOWNTO 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
PARAM_1_sll_512_py_int : STRING := "13407807929942597099574024998205846127479365820592393377723561443721764030073546976801874298166903427690031858186486050853753882811946569946433649006084096"
);
PORT(
din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF ParametrizationExample IS
BEGIN
dout <= din & din;
ASSERT PARAM_0 = 0 REPORT "Generated only for this value" SEVERITY failure;
ASSERT PARAM_10 = 10 REPORT "Generated only for this value" SEVERITY failure;
ASSERT PARAM_1_sll_512 = "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" REPORT "Generated only for this value" SEVERITY failure;
ASSERT PARAM_1_sll_512_py_int = "13407807929942597099574024998205846127479365820592393377723561443721764030073546976801874298166903427690031858186486050853753882811946569946433649006084096" REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
|
mit
|
b501c3bd9010e7323ebff413b10a9cd7
| 0.859382 | 6.34375 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_mul/fp_mul.vhd
| 1 | 5,845 |
-- megafunction wizard: %ALTERA_FP_FUNCTIONS v17.0%
-- GENERATION: XML
-- fp_mul.vhd
-- Generated using ACDS version 17.0 595
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fp_mul is
port (
clk : in std_logic := '0'; -- clk.clk
areset : in std_logic := '0'; -- areset.reset
a : in std_logic_vector(31 downto 0) := (others => '0'); -- a.a
b : in std_logic_vector(31 downto 0) := (others => '0'); -- b.b
q : out std_logic_vector(31 downto 0) -- q.q
);
end entity fp_mul;
architecture rtl of fp_mul is
component fp_mul_0002 is
port (
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(31 downto 0) -- q
);
end component fp_mul_0002;
begin
fp_mul_inst : component fp_mul_0002
port map (
clk => clk, -- clk.clk
areset => areset, -- areset.reset
a => a, -- a.a
b => b, -- b.b
q => q -- q.q
);
end architecture rtl; -- of fp_mul
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_fp_functions" version="17.0" >
-- Retrieval info: <generic name="FUNCTION_FAMILY" value="ARITH" />
-- Retrieval info: <generic name="ARITH_function" value="MUL" />
-- Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
-- Retrieval info: <generic name="ALL_function" value="ADD" />
-- Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
-- Retrieval info: <generic name="TRIG_function" value="SIN" />
-- Retrieval info: <generic name="COMPARE_function" value="MIN" />
-- Retrieval info: <generic name="ROOTS_function" value="SQRT" />
-- Retrieval info: <generic name="fp_format" value="single" />
-- Retrieval info: <generic name="fp_exp" value="8" />
-- Retrieval info: <generic name="fp_man" value="23" />
-- Retrieval info: <generic name="exponent_width" value="23" />
-- Retrieval info: <generic name="frequency_target" value="25" />
-- Retrieval info: <generic name="latency_target" value="1" />
-- Retrieval info: <generic name="performance_goal" value="frequency" />
-- Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
-- Retrieval info: <generic name="faithful_rounding" value="true" />
-- Retrieval info: <generic name="gen_enable" value="false" />
-- Retrieval info: <generic name="divide_type" value="0" />
-- Retrieval info: <generic name="select_signal_enable" value="false" />
-- Retrieval info: <generic name="scale_by_pi" value="false" />
-- Retrieval info: <generic name="number_of_inputs" value="2" />
-- Retrieval info: <generic name="trig_no_range_reduction" value="false" />
-- Retrieval info: <generic name="report_resources_to_xml" value="false" />
-- Retrieval info: <generic name="fxpt_width" value="32" />
-- Retrieval info: <generic name="fxpt_fraction" value="0" />
-- Retrieval info: <generic name="fxpt_sign" value="1" />
-- Retrieval info: <generic name="fp_out_format" value="single" />
-- Retrieval info: <generic name="fp_out_exp" value="8" />
-- Retrieval info: <generic name="fp_out_man" value="23" />
-- Retrieval info: <generic name="fp_in_format" value="single" />
-- Retrieval info: <generic name="fp_in_exp" value="8" />
-- Retrieval info: <generic name="fp_in_man" value="23" />
-- Retrieval info: <generic name="enable_hard_fp" value="true" />
-- Retrieval info: <generic name="manual_dsp_planning" value="true" />
-- Retrieval info: <generic name="forceRegisters" value="1111" />
-- Retrieval info: <generic name="selected_device_family" value="MAX 10" />
-- Retrieval info: <generic name="selected_device_speedgrade" value="6" />
-- Retrieval info: </instance>
-- IPFS_FILES : fp_mul.vho
-- RELATED_FILES: fp_mul.vhd, dspba_library_package.vhd, dspba_library.vhd, fp_mul_0002.vhd
|
mit
|
c92c34893a0a48586c92ff07c9c89d0a
| 0.642429 | 3.491637 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/hpf_adcinput/mac2reg.vhd
| 1 | 3,858 |
------------------------------------------------------------------------------
-- Title : DSP48E1-based MAC and data registered data propagation (2 stages)
------------------------------------------------------------------------------
-- Author : Daniel Tavares
-- Company : CNPEM LNLS-DIG
-- Created : 2019-11-23
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Elementary mulitply-accumulate block for systolic FIR filter
-- implementation. Use 2 pipeline stages at the input data.
-- Reference: "DSP: Designing for Optimal Results"
-------------------------------------------------------------------------------
-- Copyright (c) 2019 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-11-23 1.0 daniel.tavares Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity mac2reg is
port
(
clk_i : in std_logic;
data_i : in std_logic_vector (17 downto 0);
coef_i : in std_logic_vector (24 downto 0);
casc_i : in std_logic_vector (47 downto 0);
data_o : out std_logic_vector (17 downto 0);
mac_o : out std_logic_vector (47 downto 0);
casc_o : out std_logic_vector (47 downto 0)
);
end mac2reg;
architecture rtl of mac2reg is
signal coef : std_logic_vector(29 downto 0);
begin
DSP48E1_inst : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT",
B_INPUT => "CASCADE",
USE_DPORT => FALSE,
USE_MULT => "MULTIPLY",
USE_SIMD => "ONE48",
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET",
MASK => X"3fffffffffff",
PATTERN => X"000000000000",
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_PATTERN_DETECT => "NO_PATDET",
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 1,
AREG => 1,
BCASCREG => 2,
BREG => 2,
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MREG => 1,
OPMODEREG => 0,
PREG => 1
)
port map (
CLK => clk_i,
A => coef,
B => (others => '0'),
BCOUT => data_o,
PCOUT => casc_o,
P => mac_o,
BCIN => data_i,
PCIN => casc_i,
INMODE => "00001",
OPMODE => "0010101",
ALUMODE => "0000",
-- Reset/Clock Enable Inputs
CEA1 => '1',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '1',
CEB1 => '1',
CEB2 => '1',
CEC => '0',
CECARRYIN => '0',
CECTRL => '1',
CED => '0',
CEINMODE => '0',
CEM => '1',
CEP => '1',
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
-- Unused port
ACOUT => open,
CARRYCASCOUT => open,
MULTSIGNOUT => open,
OVERFLOW => open,
PATTERNBDETECT => open,
PATTERNDETECT => open,
UNDERFLOW => open,
CARRYOUT => open,
ACIN => (others => '0'),
CARRYCASCIN => '0',
MULTSIGNIN => '0',
CARRYINSEL => "000",
C => (others => '0'),
CARRYIN => '0',
D => (others => '0')
);
-- Sign extension - DSP48E1 expects 30 bits on port A but multiplier uses only 25 bits
coef(24 downto 0) <= coef_i;
coef(29 downto 25) <= (others => coef_i(24));
end rtl;
|
lgpl-3.0
|
a31dba03f2758bdca07dc93d127bcfe8
| 0.484707 | 3.993789 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/afc_v3/wb_trigger/clk_gen.vhd
| 1 | 1,596 |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic;
sys_clk_bufg_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DIFF_SSTL15"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
sys_clk_o <= s_sys_clk;
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_bufg_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
lgpl-3.0
|
dae2dc5acaabf500bc67ed7d068b1314
| 0.513158 | 4 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_mul/fp_mul_sim/dspba_library.vhd
| 12 | 11,603 |
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
async_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
mit
|
7fabddb7794c9447cf88b4eea661820f
| 0.473843 | 4.550196 | false | false | false | false |
nanomolina/MIPS
|
prueba/EX_MEM.vhd
| 1 | 1,535 |
library ieee;
use ieee.std_logic_1164.all;
entity EX_MEM is
port (
Zero_in : in std_logic;
AluOut_in : in std_logic_vector(31 downto 0);
WriteData_in : in std_logic_vector(31 downto 0);
WriteReg_in : in std_logic_vector(4 downto 0);
PCBranch_in : in std_logic_vector(31 downto 0);
RegWrite_in: in std_logic;
MemToReg_in: in std_logic;
MemWrite_in: in std_logic;
Jump_in: in std_logic;
Branch_in: in std_logic;
clk : in std_logic;
RegWrite_out: out std_logic;
MemToReg_out: out std_logic;
MemWrite_out: out std_logic;
Jump_out: out std_logic;
Branch_out: out std_logic;
Zero_out : out std_logic;
AluOut_out : out std_logic_vector(31 downto 0);
WriteData_out : out std_logic_vector(31 downto 0);
WriteReg_out : out std_logic_vector(4 downto 0);
PCBranch_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture BH of EX_MEM is
begin
process (clk) begin
if (clk'event and clk = '1') then
RegWrite_out <= RegWrite_in;
MemToReg_out <= MemToReg_in;
MemWrite_out <= MemWrite_in;
Jump_out <= Jump_in;
Branch_out <= Branch_in;
Zero_out <= Zero_in;
AluOut_out <= AluOut_in;
WriteData_out <= WriteData_in;
WriteReg_out <= WriteReg_in;
PCBranch_out <= PCBranch_in;
end if;
end process;
end BH;
|
gpl-3.0
|
a7ff155dc5ee27b8b13f46656495c5f5
| 0.560261 | 3.646081 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/usb_system/altera_merlin_master_translator/_primary.vhd
| 1 | 4,518 |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_master_translator is
generic(
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
USE_BURSTCOUNT : integer := 1;
USE_BEGINBURSTTRANSFER: integer := 0;
USE_BEGINTRANSFER: integer := 0;
USE_CHIPSELECT : integer := 0;
USE_READ : integer := 1;
USE_READDATAVALID: integer := 1;
USE_WRITE : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_WRITERESPONSE: integer := 0;
USE_READRESPONSE: integer := 0;
AV_REGISTERINCOMINGSIGNALS: integer := 0;
AV_SYMBOLS_PER_WORD: integer := 4;
AV_ADDRESS_SYMBOLS: integer := 0;
AV_CONSTANT_BURST_BEHAVIOR: integer := 1;
AV_BURSTCOUNT_SYMBOLS: integer := 0;
AV_LINEWRAPBURSTS: integer := 0;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W: integer := 10;
UAV_CONSTANT_BURST_BEHAVIOR: integer := 0
);
port(
clk : in vl_logic;
reset : in vl_logic;
uav_write : out vl_logic;
uav_read : out vl_logic;
uav_address : out vl_logic_vector;
uav_burstcount : out vl_logic_vector;
uav_byteenable : out vl_logic_vector;
uav_writedata : out vl_logic_vector;
uav_lock : out vl_logic;
uav_debugaccess : out vl_logic;
uav_clken : out vl_logic;
uav_readdata : in vl_logic_vector;
uav_readdatavalid: in vl_logic;
uav_waitrequest : in vl_logic;
uav_response : in vl_logic_vector(1 downto 0);
uav_writeresponserequest: out vl_logic;
uav_writeresponsevalid: in vl_logic;
av_write : in vl_logic;
av_read : in vl_logic;
av_address : in vl_logic_vector;
av_byteenable : in vl_logic_vector;
av_burstcount : in vl_logic_vector;
av_writedata : in vl_logic_vector;
av_begintransfer: in vl_logic;
av_beginbursttransfer: in vl_logic;
av_lock : in vl_logic;
av_chipselect : in vl_logic;
av_debugaccess : in vl_logic;
av_clken : in vl_logic;
av_readdata : out vl_logic_vector;
av_readdatavalid: out vl_logic;
av_waitrequest : out vl_logic;
av_response : out vl_logic_vector(1 downto 0);
av_writeresponserequest: in vl_logic;
av_writeresponsevalid: out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of AV_DATA_W : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of AV_BYTEENABLE_W : constant is 1;
attribute mti_svvh_generic_type of USE_BURSTCOUNT : constant is 1;
attribute mti_svvh_generic_type of USE_BEGINBURSTTRANSFER : constant is 1;
attribute mti_svvh_generic_type of USE_BEGINTRANSFER : constant is 1;
attribute mti_svvh_generic_type of USE_CHIPSELECT : constant is 1;
attribute mti_svvh_generic_type of USE_READ : constant is 1;
attribute mti_svvh_generic_type of USE_READDATAVALID : constant is 1;
attribute mti_svvh_generic_type of USE_WRITE : constant is 1;
attribute mti_svvh_generic_type of USE_WAITREQUEST : constant is 1;
attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1;
attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1;
attribute mti_svvh_generic_type of AV_REGISTERINCOMINGSIGNALS : constant is 1;
attribute mti_svvh_generic_type of AV_SYMBOLS_PER_WORD : constant is 1;
attribute mti_svvh_generic_type of AV_ADDRESS_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of AV_CONSTANT_BURST_BEHAVIOR : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of AV_LINEWRAPBURSTS : constant is 1;
attribute mti_svvh_generic_type of UAV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of UAV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of UAV_CONSTANT_BURST_BEHAVIOR : constant is 1;
end altera_merlin_master_translator;
|
apache-2.0
|
05eb5cc09715456cc6a537ec502b0f66
| 0.615317 | 3.765 | false | false | false | false |
elahejalalpour/CoDesign
|
Phase-1/hem/hem_tb.vhd
| 1 | 2,197 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:23:35 06/27/2015
-- Design Name:
-- Module Name: C:/projectxilinx/hem/multiplier/hem_tb.vhd
-- Project Name: multiplier
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: hem
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY hem_tb IS
END hem_tb;
ARCHITECTURE behavior OF hem_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hem
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
r : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal r : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hem PORT MAP (
a => a,
b => b,
r => r
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
a<="0111";
b<="1100";
wait for 10ns;
a<="0101";
b<="1101";
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
13633bcec8db99c797105f7860449555
| 0.556213 | 3.930233 | false | true | false | false |
Jawanga/ece385final
|
simulation/modelsim/usb_system/altera_avalon_st_handshake_clock_crosser/_primary.vhd
| 2 | 2,458 |
library verilog;
use verilog.vl_types.all;
entity altera_avalon_st_handshake_clock_crosser is
generic(
DATA_WIDTH : integer := 8;
BITS_PER_SYMBOL : integer := 8;
USE_PACKETS : integer := 0;
USE_CHANNEL : integer := 0;
CHANNEL_WIDTH : integer := 1;
USE_ERROR : integer := 0;
ERROR_WIDTH : integer := 1;
VALID_SYNC_DEPTH: integer := 2;
READY_SYNC_DEPTH: integer := 2;
USE_OUTPUT_PIPELINE: integer := 1;
SYMBOLS_PER_BEAT: vl_notype;
EMPTY_WIDTH : vl_notype
);
port(
in_clk : in vl_logic;
in_reset : in vl_logic;
out_clk : in vl_logic;
out_reset : in vl_logic;
in_ready : out vl_logic;
in_valid : in vl_logic;
in_data : in vl_logic_vector;
in_channel : in vl_logic_vector;
in_error : in vl_logic_vector;
in_startofpacket: in vl_logic;
in_endofpacket : in vl_logic;
in_empty : in vl_logic_vector;
out_ready : in vl_logic;
out_valid : out vl_logic;
out_data : out vl_logic_vector;
out_channel : out vl_logic_vector;
out_error : out vl_logic_vector;
out_startofpacket: out vl_logic;
out_endofpacket : out vl_logic;
out_empty : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_SYMBOL : constant is 1;
attribute mti_svvh_generic_type of USE_PACKETS : constant is 1;
attribute mti_svvh_generic_type of USE_CHANNEL : constant is 1;
attribute mti_svvh_generic_type of CHANNEL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of USE_ERROR : constant is 1;
attribute mti_svvh_generic_type of ERROR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of VALID_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of READY_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of USE_OUTPUT_PIPELINE : constant is 1;
attribute mti_svvh_generic_type of SYMBOLS_PER_BEAT : constant is 3;
attribute mti_svvh_generic_type of EMPTY_WIDTH : constant is 3;
end altera_avalon_st_handshake_clock_crosser;
|
apache-2.0
|
0544e1bf95bde1dfea93d940c0426761
| 0.581774 | 3.690691 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/rom/rom.vhd
| 1 | 2,651 |
-- Read only memory for MARK-II
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee, lpm;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use lpm.lpm_components.all;
entity rom is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address of the ROM
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic
);
end entity rom;
architecture rom_arch of rom is
signal data_for_read: std_logic_vector(31 downto 0);
--signal thats represent chip select
signal cs: std_logic;
type ack_fsm is (idle, set);
signal ack_fsm_state: ack_fsm;
begin
-- read only memory
mem:lpm_rom
generic map(
lpm_widthad => 8,
lpm_outdata => "UNREGISTERED",
lpm_address_control => "REGISTERED",
lpm_file => "../src/rom/rom.mif",
lpm_width => 32
)
port map(
inclock=>clk,
address=>address(7 downto 0),
q=>data_for_read
);
--chip select
process(address) is begin
if((unsigned(address) >= BASE_ADDRESS) and (unsigned(address) <= (BASE_ADDRESS + 255))) then
cs <= '1';
else
cs <= '0';
end if;
end process;
--tri state outputs
data_miso <= data_for_read when (cs = '1' and RD = '1') else (others => 'Z');
process(clk) is
begin
if rising_edge(clk) then
if res = '1' then
ack_fsm_state <= idle;
else
case ack_fsm_state is
when idle =>
if (cs = '1' and RD = '1') then
ack_fsm_state <= set;
else
ack_fsm_state <= idle;
end if;
when set =>
ack_fsm_state <= idle;
end case;
end if;
end if;
end process;
process(ack_fsm_state) is
begin
case ack_fsm_state is
when idle =>
ack <= '0';
when set =>
ack <= '1';
end case;
end process;
end architecture rom_arch;
|
mit
|
dedcc27c01d35c6775cd53fb5c434455
| 0.479623 | 4.051988 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/clock_generator_pll_s16_diff.vhd
| 1 | 9,838 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: clock_generator_pll_s16_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: PLL Based clock generator. Takes in a differential clock and multiplies it
-- by the amount specified. Instantiates a BUFIO2, BUFPLL and a PLL using
-- INTERNAL feedback
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity clock_generator_pll_s16_diff is generic (
PLLD : integer := 1 ; -- Parameter to set the division factor in the PLL
PLLX : integer := 8 ; -- Parameter to set the multiplication factor in the PLL
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
CLKIN_PERIOD : real := 6.000 ; -- clock period (ns) of input clock on clkin_p
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
reset : in std_logic ; -- reset (active high)
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclk : out std_logic ; -- ioclock from BUFPLL
serdesstrobe : out std_logic ; -- serdes strobe from BUFPLL
gclk1 : out std_logic ; -- global clock output from BUFG x1
gclk2 : out std_logic ; -- global clock output from BUFG x2
bufpll_lckd : out std_logic) ; -- Locked output from BUFPLL
end clock_generator_pll_s16_diff ;
architecture arch_clock_generator_pll_s16_diff of clock_generator_pll_s16_diff is
signal clkint : std_logic ; --
signal dummy : std_logic ; --
signal pllout_xs : std_logic ; --
signal pllout_x1 : std_logic ; --
signal pllout_x2 : std_logic ; --
signal pll_lckd : std_logic ; --
signal gclk2_int : std_logic ; --
signal buf_pll_lckd :std_logic ;
begin
gclk2 <= gclk2_int ;
iob_freqgen_in : IBUFDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => clkint);
tx_pll_adv_inst : PLL_ADV generic map(
BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized"
CLKFBOUT_MULT => PLLX, -- multiplication factor for all output clocks
CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks
CLKIN1_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1
CLKIN2_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin2
CLKOUT0_DIVIDE => 1, -- division factor for clkout0 (1 to 128)
CLKOUT0_DUTY_CYCLE => 0.5, -- duty cycle for clkout0 (0.01 to 0.99)
CLKOUT0_PHASE => 0.0, -- phase shift (degrees) for clkout0 (0.0 to 360.0)
CLKOUT1_DIVIDE => 1, -- division factor for clkout1 (1 to 128)
CLKOUT1_DUTY_CYCLE => 0.5, -- duty cycle for clkout1 (0.01 to 0.99)
CLKOUT1_PHASE => 0.0, -- phase shift (degrees) for clkout1 (0.0 to 360.0)
CLKOUT2_DIVIDE => S, -- division factor for clkout2 (1 to 128)
CLKOUT2_DUTY_CYCLE => 0.5, -- duty cycle for clkout2 (0.01 to 0.99)
CLKOUT2_PHASE => 0.0, -- phase shift (degrees) for clkout2 (0.0 to 360.0)
CLKOUT3_DIVIDE => S/2, -- division factor for clkout3 (1 to 128)
CLKOUT3_DUTY_CYCLE => 0.5, -- duty cycle for clkout3 (0.01 to 0.99)
CLKOUT3_PHASE => 0.0, -- phase shift (degrees) for clkout3 (0.0 to 360.0)
CLKOUT4_DIVIDE => S, -- division factor for clkout4 (1 to 128)
CLKOUT4_DUTY_CYCLE => 0.5, -- duty cycle for clkout4 (0.01 to 0.99)
CLKOUT4_PHASE => 0.0, -- phase shift (degrees) for clkout4 (0.0 to 360.0)
CLKOUT5_DIVIDE => S, -- division factor for clkout5 (1 to 128)
CLKOUT5_DUTY_CYCLE => 0.5, -- duty cycle for clkout5 (0.01 to 0.99)
CLKOUT5_PHASE => 0.0, -- phase shift (degrees) for clkout5 (0.0 to 360.0)
COMPENSATION => "INTERNAL", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
DIVCLK_DIVIDE => PLLD, -- division factor for all clocks (1 to 52)
REF_JITTER => 0.100) -- input reference jitter (0.000 to 0.999 ui%)
port map (
CLKFBDCM => open, -- output feedback signal used when pll feeds a dcm
CLKFBOUT => dummy, -- general output feedback signal
CLKOUT0 => pllout_xs, -- x7 clock for transmitter
CLKOUT1 => open, --
CLKOUT2 => pllout_x1, -- x1 clock for BUFG
CLKOUT3 => pllout_x2, -- x2 clock for BUFG
CLKOUT4 => open, -- one of six general clock output signals
CLKOUT5 => open, -- one of six general clock output signals
CLKOUTDCM0 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM1 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM2 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM3 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM4 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM5 => open, -- one of six clock outputs to connect to the dcm
DO => open, -- dynamic reconfig data output (16-bits)
DRDY => open, -- dynamic reconfig ready output
LOCKED => pll_lckd, -- active high pll lock signal
CLKFBIN => dummy, -- clock feedback input
CLKIN1 => clkint, -- primary clock input
CLKIN2 => '0', -- secondary clock input
CLKINSEL => '1', -- selects '1' = clkin1, '0' = clkin2
DADDR => "00000", -- dynamic reconfig address input (5-bits)
DCLK => '0', -- dynamic reconfig clock input
DEN => '0', -- dynamic reconfig enable input
DI => "0000000000000000", -- dynamic reconfig data input (16-bits)
DWE => '0', -- dynamic reconfig write enable input
RST => reset, -- asynchronous pll reset
REL => '0') ; -- used to force the state of the PFD outputs (test only)
bufg_tx_x1 : BUFG port map (I => pllout_x1, O => gclk1 ) ;
bufg_tx_x2 : BUFG port map (I => pllout_x2, O => gclk2_int ) ;
tx_bufpll_inst : BUFPLL generic map(
DIVIDE => S/2) -- PLLIN0 divide-by value to produce SERDESSTROBE (1 to 8); default 1
port map (
PLLIN => pllout_xs, -- PLL Clock input
GCLK => gclk2_int, -- Global Clock input
LOCKED => pll_lckd, -- Clock0 locked input
IOCLK => ioclk, -- Output PLL Clock
LOCK => buf_pll_lckd, -- BUFPLL Clock and strobe locked
SERDESSTROBE => serdesstrobe) ; -- Output SERDES strobe
bufpll_lckd <= buf_pll_lckd and pll_lckd ;
end arch_clock_generator_pll_s16_diff ;
|
apache-2.0
|
ae3fa282eef92c3f1dc09fd60ed28b4f
| 0.581826 | 3.64911 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/BUFIO2 DDR/tb_top_nto1_ddr.vhd
| 1 | 6,999 |
------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: tb_top_nto1_ddr.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Test Bench
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------/
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and signalulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
entity tb_top_nto1_ddr is end tb_top_nto1_ddr ;
architecture rtl of tb_top_nto1_ddr is
component top_nto1_ddr_diff_rx is port (
reset : in std_logic ; -- reset (active high)
datain_p, datain_n : in std_logic_vector(7 downto 0) ; -- differential data inputs
clkin_p, clkin_n : in std_logic ; -- differential clock input
dummy_out : out std_logic_vector(63 downto 0) ) ; -- dummy outputs
end component ;
component top_nto1_ddr_diff_tx is port (
reset : in std_logic ; -- reset (active high)
refclkin_p, refclkin_n : in std_logic ; -- frequency generator clock input
dataout_p, dataout_n : out std_logic_vector(7 downto 0) ; -- differential data outputs
clkout_p, clkout_n : out std_logic ) ; -- differential clock output
end component ;
component top_nto1_ddr_se_rx is port (
reset : in std_logic ; -- reset (active high)
datain : in std_logic_vector(7 downto 0) ; -- single ended data inputs
clkin1, clkin2 : in std_logic ; -- TWO single ended clock input
dummy_out : out std_logic_vector(63 downto 0) ) ; -- dummy outputs
end component ;
component top_nto1_ddr_se_tx is port (
reset : in std_logic ; -- reset (active high)
refclkin_p, refclkin_n : in std_logic ; -- frequency generator clock input
dataout : out std_logic_vector(7 downto 0) ; -- single ended data outputs
clkout : out std_logic ) ; -- single ended clock output
end component ;
signal clk : std_logic := '0' ;
signal notclk : std_logic := '1' ;
signal clkout_p : std_logic ;
signal clkout_n : std_logic ;
signal notclkd : std_logic ;
signal reset : std_logic := '1' ;
signal reset2 : std_logic := '1' ;
signal notrxclk : std_logic := '0' ;
signal notframe : std_logic := '0' ;
signal dataout_p : std_logic_vector(7 downto 0) ;
signal dataout_n : std_logic_vector(7 downto 0) ;
signal dataout : std_logic_vector(7 downto 0) ;
signal dummy_out : std_logic_vector(63 downto 0) ;
signal dummy_outa : std_logic_vector(63 downto 0) ;
signal old : std_logic_vector(63 downto 0) ;
signal olda : std_logic_vector(63 downto 0) ;
signal match : std_logic ;
signal matcha : std_logic ;
signal clkin_p : std_logic ;
signal refclk_p : std_logic := '0' ;
signal refclk_n : std_logic ;
signal oldclk : std_logic ;
signal clkout : std_logic ;
begin
clk <= not clk after 4 nS ; -- local clock
refclk_p <= not refclk_p after 1 nS ; -- local clock
reset <= '0' after 150 nS;
reset2 <= '0' after 300 nS;
notclk <= not clk ;
refclk_n <= not refclk_p ;
process (clk) -- Check data
begin
if clk'event and clk = '1' then
old <= dummy_out ;
if dummy_out(63 downto 60) = "0011" and dummy_out(59 downto 0) = old(58 downto 0) & old(59) then
match <= '1' ;
else
match <= '0' ;
end if ;
end if ;
end process ;
diff_tx : top_nto1_ddr_diff_tx port map (
refclkin_p => refclk_p,
refclkin_n => refclk_n,
dataout_p => dataout_p,
dataout_n => dataout_n,
clkout_p => clkout_p,
clkout_n => clkout_n,
reset => reset) ;
diff_rx : top_nto1_ddr_diff_rx port map (
clkin_p => clkout_p,
clkin_n => clkout_n,
datain_p => dataout_p,
datain_n => dataout_n,
reset => reset,
dummy_out => dummy_out) ;
process (clk) -- Check data
begin
if clk'event and clk = '1' then
olda <= dummy_outa ;
if dummy_outa(63 downto 60) = "0011" and dummy_outa(59 downto 0) = olda(58 downto 0) & olda(59) then
matcha <= '1' ;
else
matcha <= '0' ;
end if ;
end if ;
end process ;
se_tx : top_nto1_ddr_se_tx port map (
refclkin_p => refclk_p,
refclkin_n => refclk_n,
dataout => dataout,
clkout => clkout,
reset => reset) ;
se_rx : top_nto1_ddr_se_rx port map (
clkin1 => clkout,
clkin2 => clkout,
datain => dataout,
reset => reset,
dummy_out => dummy_outa) ;
end rtl ;
|
apache-2.0
|
16f002160b28be718b4e2451d821f5b5
| 0.606658 | 3.214975 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/interruptControl/intController.vhd
| 1 | 22,667 |
-- Interrupt controller peripheral
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity intController is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"00000" --base address
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
int_req: in std_logic_vector(15 downto 0); --peripherals may request interrupt with this signal
int_accept: in std_logic; --from the CPU
int_completed: in std_logic; --from the CPU
int_cpu_address: out std_logic_vector(23 downto 0); --connect this to the CPU, this is address of ISR
int_cpu_rq: out std_logic
);
end entity intController;
architecture intControllerArch of intController is
--this is one rs flip flop
component intRSFF is
port(
clk: in std_logic;
res: in std_logic;
intSet: in std_logic;
intTaken: in std_logic;
intOut: out std_logic
);
end component intRSFF;
--FSM for interrupt control
component intFSM is
port(
res: in std_logic;
clk: in std_logic;
intFiltred: in std_logic_vector(15 downto 0);
int_cpu_addr_sel: out std_logic_vector(3 downto 0);
int_cpu_rq: out std_logic;
int_taken: out std_logic_vector(15 downto 0);
int_accept: in std_logic;
int_completed: in std_logic
);
end component intFSM;
component vector_reg is
port(
clk: in std_logic;
res: in std_logic;
we_a: in std_logic;
we_b: in std_logic;
data_mosi: in std_logic_vector(31 downto 0);
q: out std_logic_vector(23 downto 0)
);
end component vector_reg;
--chip select signal for mask register
signal reg_sel_int_msk: std_logic;
signal interrupt_mask_reg: std_logic_vector(15 downto 0); --interrupt mask
signal intTaken: std_logic_vector(15 downto 0); --signal from FSM to RSFF, this reset FF after interrupt is taken
signal intRaw: std_logic_vector(15 downto 0); --unmasked signals
signal intFiltred: std_logic_vector(15 downto 0); --masked int signals
signal int_cpu_addr_sel: std_logic_vector(3 downto 0);
signal reg_sel_vector: std_logic_vector(15 downto 0);
signal selected_miso_vector: std_logic_vector(23 downto 0);
signal vector_0, vector_1, vector_2, vector_3, vector_4, vector_5,
vector_6, vector_7, vector_8, vector_9, vector_10, vector_11, vector_12,
vector_13, vector_14, vector_15: std_logic_vector(23 downto 0);
signal int_cpu_address_signal: std_logic_vector(23 downto 0);
signal int_cpu_rq_signal: std_logic;
begin
--chip select
process(address) is begin
if(unsigned(address) = BASE_ADDRESS)then
reg_sel_int_msk <= '1';
else
reg_sel_int_msk <= '0';
end if;
end process;
--register for interrupt mask
process(clk, res, WR, data_mosi, reg_sel_int_msk) is begin
if rising_edge(clk) then
if(res = '1') then
interrupt_mask_reg <= (others => '0');
elsif (WR = '1' and reg_sel_int_msk = '1') then
interrupt_mask_reg <= data_mosi(15 downto 0);
end if;
end if;
end process;
--output from register
data_miso <= x"0000" & interrupt_mask_reg when (RD = '1' and reg_sel_int_msk = '1') else (others => 'Z');
ack <= '1' when
(WR = '1' and reg_sel_int_msk = '1') or
(RD = '1' and reg_sel_int_msk = '1') or
(RD = '1' and reg_sel_vector /= x"0000") or
(WR = '1' and reg_sel_vector /= x"0000")
else '0';
--this is 32 RS flip flops, for asynchronous inputs
gen_intrsff:
for I in 15 downto 0 generate
intRSFF_gen: intRSFF port map(clk, res, int_req(I), intTaken(I), intRaw(I));
end generate gen_intrsff;
--interrupt mask
intFiltred <= intRaw and interrupt_mask_reg;
--FSM which control interrupts
fsm: intFSM
port map(res, clk, intFiltred, int_cpu_addr_sel, int_cpu_rq_signal, intTaken, int_accept, int_completed);
reg_sel_vector(0) <= '1' when (unsigned(address) = (BASE_ADDRESS + 1)) else '0';
reg_sel_vector(1) <= '1' when (unsigned(address) = (BASE_ADDRESS + 2)) else '0';
reg_sel_vector(2) <= '1' when (unsigned(address) = (BASE_ADDRESS + 3)) else '0';
reg_sel_vector(3) <= '1' when (unsigned(address) = (BASE_ADDRESS + 4)) else '0';
reg_sel_vector(4) <= '1' when (unsigned(address) = (BASE_ADDRESS + 5)) else '0';
reg_sel_vector(5) <= '1' when (unsigned(address) = (BASE_ADDRESS + 6)) else '0';
reg_sel_vector(6) <= '1' when (unsigned(address) = (BASE_ADDRESS + 7)) else '0';
reg_sel_vector(7) <= '1' when (unsigned(address) = (BASE_ADDRESS + 8)) else '0';
reg_sel_vector(8) <= '1' when (unsigned(address) = (BASE_ADDRESS + 9)) else '0';
reg_sel_vector(9) <= '1' when (unsigned(address) = (BASE_ADDRESS + 10)) else '0';
reg_sel_vector(10) <= '1' when (unsigned(address) = (BASE_ADDRESS + 11)) else '0';
reg_sel_vector(11) <= '1' when (unsigned(address) = (BASE_ADDRESS + 12)) else '0';
reg_sel_vector(12) <= '1' when (unsigned(address) = (BASE_ADDRESS + 13)) else '0';
reg_sel_vector(13) <= '1' when (unsigned(address) = (BASE_ADDRESS + 14)) else '0';
reg_sel_vector(14) <= '1' when (unsigned(address) = (BASE_ADDRESS + 15)) else '0';
reg_sel_vector(15) <= '1' when (unsigned(address) = (BASE_ADDRESS + 16)) else '0';
vectorreg0: vector_reg port map(clk, res, reg_sel_vector(0), WR, data_mosi, vector_0);
vectorreg1: vector_reg port map(clk, res, reg_sel_vector(1), WR, data_mosi, vector_1);
vectorreg2: vector_reg port map(clk, res, reg_sel_vector(2), WR, data_mosi, vector_2);
vectorreg3: vector_reg port map(clk, res, reg_sel_vector(3), WR, data_mosi, vector_3);
vectorreg4: vector_reg port map(clk, res, reg_sel_vector(4), WR, data_mosi, vector_4);
vectorreg5: vector_reg port map(clk, res, reg_sel_vector(5), WR, data_mosi, vector_5);
vectorreg6: vector_reg port map(clk, res, reg_sel_vector(6), WR, data_mosi, vector_6);
vectorreg7: vector_reg port map(clk, res, reg_sel_vector(7), WR, data_mosi, vector_7);
vectorreg8: vector_reg port map(clk, res, reg_sel_vector(8), WR, data_mosi, vector_8);
vectorreg9: vector_reg port map(clk, res, reg_sel_vector(9), WR, data_mosi, vector_9);
vectorreg10: vector_reg port map(clk, res, reg_sel_vector(10), WR, data_mosi, vector_10);
vectorreg11: vector_reg port map(clk, res, reg_sel_vector(11), WR, data_mosi, vector_11);
vectorreg12: vector_reg port map(clk, res, reg_sel_vector(12), WR, data_mosi, vector_12);
vectorreg13: vector_reg port map(clk, res, reg_sel_vector(13), WR, data_mosi, vector_13);
vectorreg14: vector_reg port map(clk, res, reg_sel_vector(14), WR, data_mosi, vector_14);
vectorreg15: vector_reg port map(clk, res, reg_sel_vector(15), WR, data_mosi, vector_15);
process(reg_sel_vector, vector_0, vector_1, vector_2, vector_3, vector_4,
vector_5, vector_6, vector_7, vector_8, vector_9, vector_10, vector_11,
vector_12, vector_13, vector_14, vector_15) is begin
case reg_sel_vector is
when x"0001" => selected_miso_vector <= vector_0;
when x"0002" => selected_miso_vector <= vector_1;
when x"0004" => selected_miso_vector <= vector_2;
when x"0008" => selected_miso_vector <= vector_3;
when x"0010" => selected_miso_vector <= vector_4;
when x"0020" => selected_miso_vector <= vector_5;
when x"0040" => selected_miso_vector <= vector_6;
when x"0080" => selected_miso_vector <= vector_7;
when x"0100" => selected_miso_vector <= vector_8;
when x"0200" => selected_miso_vector <= vector_9;
when x"0400" => selected_miso_vector <= vector_10;
when x"0800" => selected_miso_vector <= vector_11;
when x"1000" => selected_miso_vector <= vector_12;
when x"2000" => selected_miso_vector <= vector_13;
when x"4000" => selected_miso_vector <= vector_14;
when others => selected_miso_vector <= vector_15;
end case;
end process;
process(RD, reg_sel_vector, selected_miso_vector) is begin
if ((RD = '1') and (reg_sel_vector /= x"0000")) then
data_miso <= x"00" & selected_miso_vector;
else
data_miso <= (others => 'Z');
end if;
end process;
process(int_cpu_addr_sel, vector_0, vector_1, vector_2, vector_3, vector_4,
vector_5, vector_6, vector_7, vector_8, vector_9, vector_10, vector_11,
vector_12, vector_13, vector_14, vector_15) is begin
case int_cpu_addr_sel is
when "0000" => int_cpu_address_signal <= vector_0;
when "0001" => int_cpu_address_signal <= vector_1;
when "0010" => int_cpu_address_signal <= vector_2;
when "0011" => int_cpu_address_signal <= vector_3;
when "0100" => int_cpu_address_signal <= vector_4;
when "0101" => int_cpu_address_signal <= vector_5;
when "0110" => int_cpu_address_signal <= vector_6;
when "0111" => int_cpu_address_signal <= vector_7;
when "1000" => int_cpu_address_signal <= vector_8;
when "1001" => int_cpu_address_signal <= vector_9;
when "1010" => int_cpu_address_signal <= vector_10;
when "1011" => int_cpu_address_signal <= vector_11;
when "1100" => int_cpu_address_signal <= vector_12;
when "1101" => int_cpu_address_signal <= vector_13;
when "1110" => int_cpu_address_signal <= vector_14;
when others => int_cpu_address_signal <= vector_15;
end case;
end process;
process(clk) is
variable vector_reg: std_logic_vector(23 downto 0);
variable rq_reg: std_logic;
begin
if rising_edge(clk) then
if res = '1' then
vector_reg := (others => '0');
rq_reg := '0';
else
vector_reg := int_cpu_address_signal;
rq_reg := int_cpu_rq_signal;
end if;
end if;
int_cpu_rq <= rq_reg;
int_cpu_address <= vector_reg;
end process;
end architecture intControllerArch;
library ieee;
use ieee.std_logic_1164.all;
entity vector_reg is
port(
clk: in std_logic;
res: in std_logic;
we_a: in std_logic;
we_b: in std_logic;
data_mosi: in std_logic_vector(31 downto 0);
q: out std_logic_vector(23 downto 0)
);
end entity vector_reg;
architecture vector_reg_arch of vector_reg is
begin
process(clk) is
variable vector: std_logic_vector(23 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
vector := (others => '0');
elsif we_a = '1' and we_b = '1' then
vector := data_mosi(23 downto 0);
end if;
end if;
q <= vector;
end process;
end architecture vector_reg_arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity intRSFF is
port(
clk: in std_logic;
res: in std_logic;
intSet: in std_logic;
intTaken: in std_logic;
intOut: out std_logic
);
end entity intRSFF;
architecture intRSFFArch of intRSFF is
begin
process(clk, res, intSet, intTaken) is
variable var: std_logic;
begin
if(rising_edge(clk))then
if(intTaken = '1' or res = '1') then
var := '0';
elsif(intSet = '1') then
var := '1';
end if;
end if;
intOut <= var;
end process;
end architecture intRSFFArch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity intFSM is
port(
res: in std_logic;
clk: in std_logic;
intFiltred: in std_logic_vector(15 downto 0);
int_cpu_addr_sel: out std_logic_vector(3 downto 0);
int_cpu_rq: out std_logic;
int_taken: out std_logic_vector(15 downto 0);
int_accept: in std_logic;
int_completed: in std_logic
);
end entity intFSM;
architecture intFSMArch of intFSM is
--states for FSM
type states is (
start, wait_for_int_come, wait_for_int_complete,
setint0, clearint0, setint1, clearint1, setint2, clearint2,
setint3, clearint3, setint4, clearint4, setint5, clearint5,
setint6, clearint6, setint7, clearint7, setint8, clearint8,
setint9, clearint9, setint10, clearint10, setint11, clearint11,
setint12, clearint12, setint13, clearint13, setint14, clearint14,
setint15, clearint15
);
--this is reg holding state
signal state: states;
begin
--logic to set up next state
process (clk, res, intFiltred, int_accept, int_completed) begin
if (rising_edge(clk)) then
if res = '1' then
state <= start;
else
case state is
when start => state <= wait_for_int_come;
when wait_for_int_come => --this is also priority decoder :)
if intFiltred(0) = '1' then state <= setint0;
elsif intFiltred(1) = '1' then state <= setint1;
elsif intFiltred(2) = '1' then state <= setint2;
elsif intFiltred(3) = '1' then state <= setint3;
elsif intFiltred(4) = '1' then state <= setint4;
elsif intFiltred(5) = '1' then state <= setint5;
elsif intFiltred(6) = '1' then state <= setint6;
elsif intFiltred(7) = '1' then state <= setint7;
elsif intFiltred(8) = '1' then state <= setint8;
elsif intFiltred(9) = '1' then state <= setint9;
elsif intFiltred(10) = '1' then state <= setint10;
elsif intFiltred(11) = '1' then state <= setint11;
elsif intFiltred(12) = '1' then state <= setint12;
elsif intFiltred(13) = '1' then state <= setint13;
elsif intFiltred(14) = '1' then state <= setint14;
elsif intFiltred(15) = '1' then state <= setint15;
else state <= start;
end if;
--ugly things, waiting for CPU take interrupt routine
when setint0 => if(int_accept = '1') then state <= clearint0; else state <= setint0; end if;
when setint1 => if(int_accept = '1') then state <= clearint1; else state <= setint1; end if;
when setint2 => if(int_accept = '1') then state <= clearint2; else state <= setint2; end if;
when setint3 => if(int_accept = '1') then state <= clearint3; else state <= setint3; end if;
when setint4 => if(int_accept = '1') then state <= clearint4; else state <= setint4; end if;
when setint5 => if(int_accept = '1') then state <= clearint5; else state <= setint5; end if;
when setint6 => if(int_accept = '1') then state <= clearint6; else state <= setint6; end if;
when setint7 => if(int_accept = '1') then state <= clearint7; else state <= setint7; end if;
when setint8 => if(int_accept = '1') then state <= clearint8; else state <= setint8; end if;
when setint9 => if(int_accept = '1') then state <= clearint9; else state <= setint9; end if;
when setint10 => if(int_accept = '1') then state <= clearint10; else state <= setint10; end if;
when setint11 => if(int_accept = '1') then state <= clearint11; else state <= setint11; end if;
when setint12 => if(int_accept = '1') then state <= clearint12; else state <= setint12; end if;
when setint13 => if(int_accept = '1') then state <= clearint13; else state <= setint13; end if;
when setint14 => if(int_accept = '1') then state <= clearint14; else state <= setint14; end if;
when setint15 => if(int_accept = '1') then state <= clearint15; else state <= setint15; end if;
--clearint will reset RS flip flop so, next interrupt can be catch
when clearint0 => state <= wait_for_int_complete;
when clearint1 => state <= wait_for_int_complete;
when clearint2 => state <= wait_for_int_complete;
when clearint3 => state <= wait_for_int_complete;
when clearint4 => state <= wait_for_int_complete;
when clearint5 => state <= wait_for_int_complete;
when clearint6 => state <= wait_for_int_complete;
when clearint7 => state <= wait_for_int_complete;
when clearint8 => state <= wait_for_int_complete;
when clearint9 => state <= wait_for_int_complete;
when clearint10 => state <= wait_for_int_complete;
when clearint11 => state <= wait_for_int_complete;
when clearint12 => state <= wait_for_int_complete;
when clearint13 => state <= wait_for_int_complete;
when clearint14 => state <= wait_for_int_complete;
when clearint15 => state <= wait_for_int_complete;
--but we also waiting for interrupt routine is completed, there isn't nested interrupts
when wait_for_int_complete =>
if(int_completed = '1') then state <= wait_for_int_come;
else state <= wait_for_int_complete;
end if;
end case;
end if;
end if;
end process;
process (state) begin
case state is
when start => int_taken <= x"0000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when wait_for_int_come => int_taken <= x"0000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when wait_for_int_complete => int_taken <= x"0000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when setint0 => int_taken <= x"0000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '1';
when setint1 => int_taken <= x"0000"; int_cpu_addr_sel <= "0001"; int_cpu_rq <= '1';
when setint2 => int_taken <= x"0000"; int_cpu_addr_sel <= "0010"; int_cpu_rq <= '1';
when setint3 => int_taken <= x"0000"; int_cpu_addr_sel <= "0011"; int_cpu_rq <= '1';
when setint4 => int_taken <= x"0000"; int_cpu_addr_sel <= "0100"; int_cpu_rq <= '1';
when setint5 => int_taken <= x"0000"; int_cpu_addr_sel <= "0101"; int_cpu_rq <= '1';
when setint6 => int_taken <= x"0000"; int_cpu_addr_sel <= "0110"; int_cpu_rq <= '1';
when setint7 => int_taken <= x"0000"; int_cpu_addr_sel <= "0111"; int_cpu_rq <= '1';
when setint8 => int_taken <= x"0000"; int_cpu_addr_sel <= "1000"; int_cpu_rq <= '1';
when setint9 => int_taken <= x"0000"; int_cpu_addr_sel <= "1001"; int_cpu_rq <= '1';
when setint10 => int_taken <= x"0000"; int_cpu_addr_sel <= "1010"; int_cpu_rq <= '1';
when setint11 => int_taken <= x"0000"; int_cpu_addr_sel <= "1011"; int_cpu_rq <= '1';
when setint12 => int_taken <= x"0000"; int_cpu_addr_sel <= "1100"; int_cpu_rq <= '1';
when setint13 => int_taken <= x"0000"; int_cpu_addr_sel <= "1101"; int_cpu_rq <= '1';
when setint14 => int_taken <= x"0000"; int_cpu_addr_sel <= "1110"; int_cpu_rq <= '1';
when setint15 => int_taken <= x"0000"; int_cpu_addr_sel <= "1111"; int_cpu_rq <= '1';
when clearint0 => int_taken <= x"0001"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint1 => int_taken <= x"0002"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint2 => int_taken <= x"0004"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint3 => int_taken <= x"0008"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint4 => int_taken <= x"0010"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint5 => int_taken <= x"0020"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint6 => int_taken <= x"0040"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint7 => int_taken <= x"0080"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint8 => int_taken <= x"0100"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint9 => int_taken <= x"0200"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint10 => int_taken <= x"0400"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint11 => int_taken <= x"0800"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint12 => int_taken <= x"1000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint13 => int_taken <= x"2000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint14 => int_taken <= x"4000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
when clearint15 => int_taken <= x"8000"; int_cpu_addr_sel <= "0000"; int_cpu_rq <= '0';
end case;
end process;
end architecture intFSMArch;
|
mit
|
549a87d7eef7411dd2f7d3ee291e0d80
| 0.548575 | 3.559918 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/uart/transmitter.vhd
| 1 | 9,972 |
-- Transmitter, part of UART.
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmitter is
port(
en: in std_logic;
clk: in std_logic;
res: in std_logic;
baud16_clk_en: in std_logic;
tx_data: in unsigned(7 downto 0);
tx: out std_logic;
tx_dcfifo_rdreq: out std_logic;
tx_dcfifo_rdusedw: in std_logic_vector(5 downto 0);
tx_sended: out std_logic
);
end entity transmitter;
architecture transmitter_arch of transmitter is
signal count: unsigned(3 downto 0);
signal baud_clk_en: std_logic;
type tx_state_type is (idle,sample_data_0, sample_data_1, set_startbit, wait_startbit, set_b0, wait_b0, set_b1, wait_b1,
set_b2, wait_b2, set_b3, wait_b3, set_b4, wait_b4, set_b5, wait_b5,
set_b6, wait_b6, set_b7, wait_b7, set_stopbit, wait_stopbit, set_flags);
signal state: tx_state_type;
signal send_reg, send_started: std_logic;
signal shift_data, load_data: std_logic;
signal sync_counter: std_logic;
begin
txcounter:
process(clk, res) is
variable counter: unsigned(3 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
counter := (others => '0');
elsif sync_counter = '1' then
counter := (others => '0');
elsif baud16_clk_en = '1' then
counter := counter + 1;
end if;
end if;
count <= counter;
end process;
process(count, baud16_clk_en) is
begin
if count = x"F" then
baud_clk_en <= baud16_clk_en;
else
baud_clk_en <= '0';
end if;
end process;
process(clk, res, baud_clk_en, tx_dcfifo_rdusedw) is begin
if rising_edge(clk) then
if res = '1' then
state <= idle;
else
case state is
when idle =>
if ((tx_dcfifo_rdusedw /= "000000") and (en = '1')) then
state <= sample_data_0;
else
state <= idle;
end if;
when sample_data_0 => state <= sample_data_1;
when sample_data_1 => state <= set_startbit;
when set_startbit => state <= wait_startbit;
when wait_startbit =>
if baud_clk_en = '1' then
state <= set_b0;
else
state <= wait_startbit;
end if;
when set_b0 => state <= wait_b0;
when wait_b0 =>
if baud_clk_en = '1' then
state <= set_b1;
else
state <= wait_b0;
end if;
when set_b1 => state <= wait_b1;
when wait_b1 =>
if baud_clk_en = '1' then
state <= set_b2;
else
state <= wait_b1;
end if;
when set_b2 => state <= wait_b2;
when wait_b2 =>
if baud_clk_en = '1' then
state <= set_b3;
else
state <= wait_b2;
end if;
when set_b3 => state <= wait_b3;
when wait_b3 =>
if baud_clk_en = '1' then
state <= set_b4;
else
state <= wait_b3;
end if;
when set_b4 => state <= wait_b4;
when wait_b4 =>
if baud_clk_en = '1' then
state <= set_b5;
else
state <= wait_b4;
end if;
when set_b5 => state <= wait_b5;
when wait_b5 =>
if baud_clk_en = '1' then
state <= set_b6;
else
state <= wait_b5;
end if;
when set_b6 => state <= wait_b6;
when wait_b6 =>
if baud_clk_en = '1' then
state <= set_b7;
else
state <= wait_b6;
end if;
when set_b7 => state <= wait_b7;
when wait_b7 =>
if baud_clk_en = '1' then
state <= set_stopbit;
else
state <= wait_b7;
end if;
when set_stopbit => state <= wait_stopbit;
when wait_stopbit =>
if baud_clk_en = '1' then
state <= set_flags;
else
state <= wait_stopbit;
end if;
when set_flags => state <= idle;
end case;
end if;
end if;
end process;
process(state) is begin
case state is
when idle =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when sample_data_0 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '1'; tx_sended <= '0';
when sample_data_1 =>
shift_data <= '0'; load_data <= '1'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_startbit =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '1'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_startbit =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b0 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b0 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b1 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b1 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b2 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b2 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b3 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b3 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b4 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b4 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b5 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b5 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b6 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b6 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_b7 =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_b7 =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_stopbit =>
shift_data <= '1'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when wait_stopbit =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '0';
when set_flags =>
shift_data <= '0'; load_data <= '0'; sync_counter <= '0'; tx_dcfifo_rdreq <= '0'; tx_sended <= '1';
end case;
end process;
process(clk, res, shift_data, load_data) is
variable data: std_logic_vector(10 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
data := (others => '1');
elsif load_data = '1' then
data := '1' & std_logic_vector(tx_data) & '0' & '1';
elsif shift_data = '1' then
data(9 downto 0) := data(10 downto 1);
data(10) := '1';
end if;
end if;
tx <= data(0);
end process;
end architecture transmitter_arch;
|
mit
|
0dad357fd2daa18a2264a52960b04c9c
| 0.407181 | 3.982029 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/alt_dspbuilder_cast_GNZ5LMFB5D.vhd
| 6 | 877 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNZ5LMFB5D is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture;
|
mit
|
cb39900bbedc824e5106c7c7280b75ca
| 0.648803 | 3.045139 | false | false | false | false |
Godoakos/conway-vhdl
|
shift_register.vhd
| 1 | 1,514 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:50:57 01/07/2015
-- Design Name:
-- Module Name: shift_register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_register is
port( CLK : in std_logic;
SI : in std_logic_vector(0 downto 0);
SO1 : out std_logic_vector(0 downto 0);
SO2 : out std_logic_vector(0 downto 0);
SO3 : out std_logic_vector(0 downto 0));
end shift_register;
architecture Behavioral of shift_register is
signal tmp: std_logic_vector(31 downto 0);
begin
process (CLK)
begin
if (CLK'event and CLK='1') then
for i in 0 to 30 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI(0);
end if;
end process;
SO1(0) <= tmp(31);
SO2(0) <= tmp(30);
SO3(0) <= tmp(29);
end Behavioral;
|
mit
|
c66377c9a38a6c27edae325b4b5cb1d6
| 0.542272 | 3.692683 | false | false | false | false |
missatisfaction/fpu
|
VHDL/table.vhd
| 1 | 31,485 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TABLE_FINV is
port ( clk : in std_logic;
addrb: in std_logic_vector(9 downto 0);
doutb: out std_logic_vector(34 downto 0));
end TABLE_FINV;
architecture tb_inv of TABLE_FINV is
type blockram is array (0 to 1023) of std_logic_vector (34 downto 0);
constant ram : blockram := ("111"&x"fffffffc", "111"&x"fc00eff4", "111"&x"f803efec", "111"&x"f408dfe4", "111"&x"f00fdfdc", "111"&x"ec18cfd4", "111"&x"e823bfcc", "111"&x"e430afc5", "111"&x"e03f7fbd", "111"&x"dc503fb5", "111"&x"d862efad", "111"&x"d477bfa6", "111"&x"d08e4f9e", "111"&x"cca6cf96", "111"&x"c8c14f8e", "111"&x"c4ddbf87", "111"&x"c0fbff7f", "111"&x"bd1c4f78", "111"&x"b93e5f70", "111"&x"b5627f69", "111"&x"b1885f61", "111"&x"adb00f59", "111"&x"a9d9cf52", "111"&x"a6054f4a", "111"&x"a232cf43", "111"&x"9e622f3c", "111"&x"9a933f34", "111"&x"96c64f2d", "111"&x"92fb0f25", "111"&x"8f31df1e", "111"&x"8b6a6f17", "111"&x"87a4af0f", "111"&x"83e0ef08", "111"&x"801f0f01", "111"&x"7c5eeefa", "111"&x"78a06ef2", "111"&x"74e3eeeb", "111"&x"71294ee4", "111"&x"6d705edd", "111"&x"69b91ed5", "111"&x"6603cece", "111"&x"62503ec7", "111"&x"5e9e6ec0", "111"&x"5aee6eb9", "111"&x"57403eb2", "111"&x"5393beab", "111"&x"4fe8fea4", "111"&x"4c400e9d", "111"&x"4898de96", "111"&x"44f34e8f", "111"&x"414f8e88", "111"&x"3dad8e81", "111"&x"3a0d3e7a", "111"&x"366eae73", "111"&x"32d1fe6d", "111"&x"2f36de66", "111"&x"2b9d6e5f", "111"&x"2805ae58", "111"&x"246f9e51", "111"&x"20db6e4b", "111"&x"1d48be44", "111"&x"19b7be3d", "111"&x"16289e37", "111"&x"129afe30", "111"&x"0f0f0e29", "111"&x"0b84be22", "111"&x"07fc4e1c", "111"&x"04754e15", "111"&x"00f01e0f", "110"&x"fd6c7e08", "110"&x"f9ea8e02", "110"&x"f66a2dfb", "110"&x"f2eb5df4", "110"&x"ef6e6dee", "110"&x"ebf2dde7", "110"&x"e8792de1", "110"&x"e500ddda", "110"&x"e18a5dd4", "110"&x"de156dce", "110"&x"daa1fdc7", "110"&x"d7304dc1", "110"&x"d3c01dbb", "110"&x"d0517db4", "110"&x"cce48dae", "110"&x"c978fda7", "110"&x"c60f3da1", "110"&x"c2a70d9b", "110"&x"bf405d95", "110"&x"bbdb1d8e", "110"&x"b8779d88", "110"&x"b5159d82", "110"&x"b1b52d7c", "110"&x"ae564d76", "110"&x"aaf8dd6f", "110"&x"a79d1d69", "110"&x"a442cd63", "110"&x"a0ea1d5d", "110"&x"9d92dd57", "110"&x"9a3d2d51", "110"&x"96e90d4b", "110"&x"93965d45", "110"&x"90453d3f", "110"&x"8cf59d39", "110"&x"89a77d33", "110"&x"865acd2d", "110"&x"830fad27", "110"&x"7fc60d21", "110"&x"7c7ded1b", "110"&x"79373d15", "110"&x"75f20d0f", "110"&x"72ae4d09", "110"&x"6f6c0d03", "110"&x"6c2b3cfd", "110"&x"68ebecf7", "110"&x"65ae2cf2", "110"&x"6271ccec", "110"&x"5f36cce6", "110"&x"5bfd4ce0", "110"&x"58c53cda", "110"&x"558ebcd5", "110"&x"52598ccf", "110"&x"4f25bcc9", "110"&x"4bf38cc4", "110"&x"48c2acbe", "110"&x"45932cb8", "110"&x"42651cb2", "110"&x"3f389cad", "110"&x"3c0d4ca7", "110"&x"38e39ca2", "110"&x"35bb3c9c", "110"&x"32942c96", "110"&x"2f6eac91", "110"&x"2c4a5c8b", "110"&x"2927ac86", "110"&x"26063c80", "110"&x"22e63c7b", "110"&x"1fc78c75", "110"&x"1caa4c70", "110"&x"198e5c6a", "110"&x"1673dc65", "110"&x"135a9c5f", "110"&x"1042dc5a", "110"&x"0d2c6c55", "110"&x"0a174c4f", "110"&x"07038c4a", "110"&x"03f11c44", "110"&x"00e01c3f", "101"&x"fdd05c3a", "101"&x"fac1fc34", "101"&x"f7b4fc2f", "101"&x"f4a93c2a", "101"&x"f19edc24", "101"&x"ee95cc1f", "101"&x"eb8e0c1a", "101"&x"e887ac15", "101"&x"e5828c0f", "101"&x"e27ebc0a", "101"&x"df7c3c05", "101"&x"dc7b0c00", "101"&x"d97b1bfa", "101"&x"d67c8bf5", "101"&x"d37f4bf0", "101"&x"d0834beb", "101"&x"cd888be6", "101"&x"ca8f1be1", "101"&x"c796fbdc", "101"&x"c4a01bd7", "101"&x"c1aa7bd1", "101"&x"beb61bcc", "101"&x"bbc31bc7", "101"&x"b8d14bc2", "101"&x"b5e0bbbd", "101"&x"b2f17bb8", "101"&x"b0037bb3", "101"&x"ad16abae", "101"&x"aa2b2ba9", "101"&x"a740dba4", "101"&x"a457db9f", "101"&x"a1700b9a", "101"&x"9e898b96", "101"&x"9ba42b90", "101"&x"98c01b8c", "101"&x"95dd3b87", "101"&x"92fb9b82", "101"&x"901b2b7d", "101"&x"8d3bfb78", "101"&x"8a5dfb73", "101"&x"87813b6f", "101"&x"84a5ab6a", "101"&x"81cb4b65", "101"&x"7ef21b60", "101"&x"7c1a2b5b", "101"&x"79435b56", "101"&x"766ddb52", "101"&x"73997b4d", "101"&x"70c64b48", "101"&x"6df44b43", "101"&x"6b237b3f", "101"&x"6853db3a", "101"&x"65855b35", "101"&x"62b81b31", "101"&x"5febfb2c", "101"&x"5d210b27", "101"&x"5a573b22", "101"&x"578e9b1e", "101"&x"54c72b19", "101"&x"5200db15", "101"&x"4f3bbb10", "101"&x"4c77ab0b", "101"&x"49b4db07", "101"&x"46f32b02", "101"&x"44329afe", "101"&x"41733af9", "101"&x"3eb4eaf5", "101"&x"3bf7caf0", "101"&x"393bbaec", "101"&x"3680dae7", "101"&x"33c70ae2", "101"&x"310e7ade", "101"&x"2e56fada", "101"&x"2ba08ad5", "101"&x"28eb4ad1", "101"&x"26371acc", "101"&x"23840ac8", "101"&x"20d20ac3", "101"&x"1e213abf", "101"&x"1b716aba", "101"&x"18c2dab6", "101"&x"16154ab2", "101"&x"1368caad", "101"&x"10bd7aa9", "101"&x"0e133aa5", "101"&x"0b6a0aa1", "101"&x"08c1ea9c", "101"&x"061aea98", "101"&x"0374ea93", "101"&x"00d01a8f", "100"&x"fe2c4a8b", "100"&x"fb899a87", "100"&x"f8e7ea82", "100"&x"f6475a7e", "100"&x"f3a7ca7a", "100"&x"f1095a76", "100"&x"ee6bea71", "100"&x"ebcf9a6d", "100"&x"e9344a69", "100"&x"e69a0a65", "100"&x"e400da61", "100"&x"e168aa5c", "100"&x"ded19a58", "100"&x"dc3b8a54", "100"&x"d9a67a50", "100"&x"d7127a4c", "100"&x"d47f8a48", "100"&x"d1ed9a44", "100"&x"cf5caa3f", "100"&x"ccccca3b", "100"&x"ca3dfa37", "100"&x"c7b02a33", "100"&x"c5235a2f", "100"&x"c2978a2b", "100"&x"c00cca27", "100"&x"bd830a23", "100"&x"bafa4a1f", "100"&x"b8728a1b", "100"&x"b5ebca17", "100"&x"b3660a13", "100"&x"b0e14a0f", "100"&x"ae5d8a0b", "100"&x"abdaca07", "100"&x"a9590a03", "100"&x"a6d849ff", "100"&x"a45889fb", "100"&x"a1d9b9f7", "100"&x"9f5bf9f4", "100"&x"9cdf19ef", "100"&x"9a6349eb", "100"&x"97e869e8", "100"&x"956e89e4", "100"&x"92f599e0", "100"&x"907da9dc", "100"&x"8e06b9d8", "100"&x"8b90b9d4", "100"&x"891ba9d0", "100"&x"86a799cd", "100"&x"843479c9", "100"&x"81c249c5", "100"&x"7f5119c1", "100"&x"7ce0c9bd", "100"&x"7a7179b9", "100"&x"780329b6", "100"&x"7595b9b2", "100"&x"732949ae", "100"&x"70bdb9aa", "100"&x"6e5329a7", "100"&x"6be989a3", "100"&x"6980c99f", "100"&x"6719099b", "100"&x"64b22998", "100"&x"624c4994", "100"&x"5fe74990", "100"&x"5d83398d", "100"&x"5b201989", "100"&x"58bdd985", "100"&x"565c8982", "100"&x"53fc297e", "100"&x"519cb97a", "100"&x"4f3e1976", "100"&x"4ce08973", "100"&x"4a83c96f", "100"&x"4827f96c", "100"&x"45cd0968", "100"&x"43730965", "100"&x"4119e961", "100"&x"3ec1a95d", "100"&x"3c6a595a", "100"&x"3a13e956", "100"&x"37be5952", "100"&x"3569b94f", "100"&x"3315e94b", "100"&x"30c31948", "100"&x"2e711944", "100"&x"2c1ff941", "100"&x"29cfc93d", "100"&x"2780693a", "100"&x"2531e936", "100"&x"22e45933", "100"&x"2097992f", "100"&x"1e4bc92c", "100"&x"1c00c928", "100"&x"19b6a925", "100"&x"176d6922", "100"&x"1525091e", "100"&x"12dd891b", "100"&x"1096d917", "100"&x"0e510914", "100"&x"0c0c1910", "100"&x"09c7f90d", "100"&x"0784b90a", "100"&x"05425906", "100"&x"0300c903", "100"&x"00c018ff", "011"&x"fe8038fc", "011"&x"fc4138f9", "011"&x"fa0308f5", "011"&x"f7c5b8f2", "011"&x"f58928ee", "011"&x"f34d88eb", "011"&x"f112b8e8", "011"&x"eed8b8e5", "011"&x"ec9f88e1", "011"&x"ea6728de", "011"&x"e82fa8db", "011"&x"e5f8f8d7", "011"&x"e3c318d4", "011"&x"e18e08d1", "011"&x"df59d8ce", "011"&x"dd2668ca", "011"&x"daf3c8c7", "011"&x"d8c208c4", "011"&x"d69108c0", "011"&x"d460e8bd", "011"&x"d23188ba", "011"&x"d002f8b7", "011"&x"cdd538b4", "011"&x"cba848b0", "011"&x"c97c28ad", "011"&x"c750d8aa", "011"&x"c52648a7", "011"&x"c2fc88a4", "011"&x"c0d398a1", "011"&x"beab689d", "011"&x"bc84189a", "011"&x"ba5d7897", "011"&x"b837b894", "011"&x"b612b891", "011"&x"b3ee788e", "011"&x"b1cb088a", "011"&x"afa86888", "011"&x"ad868884", "011"&x"ab656881", "011"&x"a945187e", "011"&x"a725887b", "011"&x"a506c878", "011"&x"a2e8c875", "011"&x"a0cb8872", "011"&x"9eaf086f", "011"&x"9c93586c", "011"&x"9a786869", "011"&x"985e3866", "011"&x"9644c862", "011"&x"942c2860", "011"&x"9214485c", "011"&x"8ffd285a", "011"&x"8de6c857", "011"&x"8bd11854", "011"&x"89bc3850", "011"&x"87a8184e", "011"&x"8594b84a", "011"&x"83821848", "011"&x"81703844", "011"&x"7f5f1842", "011"&x"7d4ea83e", "011"&x"7b3ef83c", "011"&x"79301839", "011"&x"7721e836", "011"&x"75147833", "011"&x"7307b830", "011"&x"70fbb82d", "011"&x"6ef0782a", "011"&x"6ce5f827", "011"&x"6adc2824", "011"&x"68d31821", "011"&x"66cac81e", "011"&x"64c3281c", "011"&x"62bc4819", "011"&x"60b61816", "011"&x"5eb09813", "011"&x"5cabe810", "011"&x"5aa7d80d", "011"&x"58a4880a", "011"&x"56a1f808", "011"&x"54a00804", "011"&x"529ee802", "011"&x"509e77ff", "011"&x"4e9ea7fc", "011"&x"4c9fa7f9", "011"&x"4aa147f6", "011"&x"48a3a7f4", "011"&x"46a6b7f1", "011"&x"44aa77ee", "011"&x"42aee7eb", "011"&x"40b417e9", "011"&x"3eb9e7e6", "011"&x"3cc077e3", "011"&x"3ac7b7e0", "011"&x"38cfa7de", "011"&x"36d847db", "011"&x"34e197d8", "011"&x"32eb87d5", "011"&x"30f637d2", "011"&x"2f0197d0", "011"&x"2d0da7cd", "011"&x"2b1a67ca", "011"&x"2927c7c8", "011"&x"2735e7c5", "011"&x"2544a7c2", "011"&x"235417c0", "011"&x"216437bd", "011"&x"1f74f7ba", "011"&x"1d8677b7", "011"&x"1b9897b5", "011"&x"19ab67b2", "011"&x"17bed7af", "011"&x"15d2f7ad", "011"&x"13e7c7aa", "011"&x"11fd47a7", "011"&x"101367a5", "011"&x"0e2a27a2", "011"&x"0c41a7a0", "011"&x"0a59b79d", "011"&x"0872779a", "011"&x"068be798", "011"&x"04a5f795", "011"&x"02c0b792", "011"&x"00dc1790", "010"&x"fef8278d", "010"&x"fd14c78a", "010"&x"fb322788", "010"&x"f9501786", "010"&x"f76eb783", "010"&x"f58df780", "010"&x"f3ade77e", "010"&x"f1ce777b", "010"&x"efefa779", "010"&x"ee117776", "010"&x"ec33e774", "010"&x"ea570771", "010"&x"e87ab76e", "010"&x"e69f176c", "010"&x"e4c41769", "010"&x"e2e9b767", "010"&x"e1100764", "010"&x"df36e762", "010"&x"dd5e675f", "010"&x"db86975d", "010"&x"d9af575a", "010"&x"d7d8b758", "010"&x"d602b755", "010"&x"d42d6753", "010"&x"d258a750", "010"&x"d084874e", "010"&x"ceb1074c", "010"&x"ccde1749", "010"&x"cb0bd746", "010"&x"c93a2744", "010"&x"c7692742", "010"&x"c598b73f", "010"&x"c3c8d73d", "010"&x"c1f9a73a", "010"&x"c02b0738", "010"&x"be5d0736", "010"&x"bc8fa733", "010"&x"bac2d731", "010"&x"b8f6a72e", "010"&x"b72b072c", "010"&x"b560172a", "010"&x"b395a727", "010"&x"b1cbe725", "010"&x"b002b722", "010"&x"ae3a1720", "010"&x"ac72171e", "010"&x"aaaab71b", "010"&x"a8e3e719", "010"&x"a71da716", "010"&x"a5580714", "010"&x"a392f712", "010"&x"a1ce870f", "010"&x"a00aa70d", "010"&x"9e47570b", "010"&x"9c84a708", "010"&x"9ac28706", "010"&x"99010704", "010"&x"97401701", "010"&x"957fb6ff", "010"&x"93bfe6fd", "010"&x"9200b6fa", "010"&x"904206f8", "010"&x"8e83f6f6", "010"&x"8cc686f4", "010"&x"8b0996f1", "010"&x"894d36ef", "010"&x"879176ed", "010"&x"85d646ea", "010"&x"841ba6e8", "010"&x"826196e6", "010"&x"80a816e4", "010"&x"7eef26e1", "010"&x"7d36c6df", "010"&x"7b7ef6dd", "010"&x"79c7b6da", "010"&x"781106d8", "010"&x"765ae6d6", "010"&x"74a556d4", "010"&x"72f056d2", "010"&x"713be6d0", "010"&x"6f8806cd", "010"&x"6dd4a6cb", "010"&x"6c21e6c9", "010"&x"6a6fa6c6", "010"&x"68bdf6c4", "010"&x"670cd6c2", "010"&x"655c46c0", "010"&x"63ac46be", "010"&x"61fcc6bc", "010"&x"604dd6ba", "010"&x"5e9f76b7", "010"&x"5cf196b5", "010"&x"5b4456b3", "010"&x"599786b1", "010"&x"57eb56ae", "010"&x"563fa6ac", "010"&x"549486aa", "010"&x"52e9e6a8", "010"&x"513fd6a6", "010"&x"4f9656a4", "010"&x"4ded56a2", "010"&x"4c44e6a0", "010"&x"4a9cf69e", "010"&x"48f5969b", "010"&x"474eb699", "010"&x"45a86697", "010"&x"44029695", "010"&x"425d5693", "010"&x"40b89691", "010"&x"3f14568f", "010"&x"3d70a68c", "010"&x"3bcd868a", "010"&x"3a2ad688", "010"&x"3888b686", "010"&x"36e72684", "010"&x"35460682", "010"&x"33a57680", "010"&x"3205767e", "010"&x"3065e67c", "010"&x"2ec6e67a", "010"&x"2d286678", "010"&x"2b8a7676", "010"&x"29ecf674", "010"&x"28500672", "010"&x"26b39670", "010"&x"2517a66e", "010"&x"237c366c", "010"&x"21e1566a", "010"&x"2046e668", "010"&x"1ead0666", "010"&x"1d13a664", "010"&x"1b7ab662", "010"&x"19e25660", "010"&x"184a765e", "010"&x"16b3165b", "010"&x"151c3659", "010"&x"1385d657", "010"&x"11eff656", "010"&x"105a9654", "010"&x"0ec5b652", "010"&x"0d315650", "010"&x"0b9d764e", "010"&x"0a0a164c", "010"&x"0877264a", "010"&x"06e4c648", "010"&x"0552d646", "010"&x"03c17644", "010"&x"02308642", "010"&x"00a01640", "001"&x"ff10163e", "001"&x"fd80a63c", "001"&x"fbf1a63a", "001"&x"fa633638", "001"&x"f8d52636", "001"&x"f747a634", "001"&x"f5ba9632", "001"&x"f42e1630", "001"&x"f2a1f62e", "001"&x"f116662c", "001"&x"ef8b462a", "001"&x"ee00a628", "001"&x"ec767626", "001"&x"eaecd625", "001"&x"e9639623", "001"&x"e7dae621", "001"&x"e652a61f", "001"&x"e4cad61d", "001"&x"e343861b", "001"&x"e1bcb619", "001"&x"e0365618", "001"&x"deb07616", "001"&x"dd2b0614", "001"&x"dba61612", "001"&x"da219610", "001"&x"d89d960e", "001"&x"d71a060c", "001"&x"d596e60a", "001"&x"d4144608", "001"&x"d2922607", "001"&x"d1107605", "001"&x"cf8f3603", "001"&x"ce0e6601", "001"&x"cc8e15ff", "001"&x"cb0e45fe", "001"&x"c98ed5fc", "001"&x"c80fe5fa", "001"&x"c69175f8", "001"&x"c51365f6", "001"&x"c395d5f4", "001"&x"c218b5f2", "001"&x"c09c15f1", "001"&x"bf1fd5ef", "001"&x"bda415ed", "001"&x"bc28c5eb", "001"&x"baadf5ea", "001"&x"b93385e8", "001"&x"b7b995e6", "001"&x"b64015e4", "001"&x"b4c705e2", "001"&x"b34e65e0", "001"&x"b1d635df", "001"&x"b05e75dd", "001"&x"aee735db", "001"&x"ad7065da", "001"&x"abf9f5d8", "001"&x"aa8405d6", "001"&x"a90e85d4", "001"&x"a79975d2", "001"&x"a624d5d1", "001"&x"a4b095cf", "001"&x"a33cd5cd", "001"&x"a1c985cc", "001"&x"a056a5ca", "001"&x"9ee435c8", "001"&x"9d7235c6", "001"&x"9c00a5c4", "001"&x"9a8f75c3", "001"&x"991ec5c1", "001"&x"97ae75bf", "001"&x"963ea5be", "001"&x"94cf35bc", "001"&x"936035ba", "001"&x"91f1a5b8", "001"&x"908385b7", "001"&x"8f15d5b5", "001"&x"8da885b3", "001"&x"8c3bb5b2", "001"&x"8acf45b0", "001"&x"896345ae", "001"&x"87f7a5ac", "001"&x"868c85ab", "001"&x"8521c5a9", "001"&x"83b775a8", "001"&x"824d95a6", "001"&x"80e415a4", "001"&x"7f7b05a2", "001"&x"7e1265a1", "001"&x"7caa359f", "001"&x"7b42659e", "001"&x"79db059c", "001"&x"7874059a", "001"&x"770d7598", "001"&x"75a75597", "001"&x"74419595", "001"&x"72dc4594", "001"&x"71776592", "001"&x"7012e590", "001"&x"6eaec58e", "001"&x"6d4b258d", "001"&x"6be7e58b", "001"&x"6a85058a", "001"&x"69229588", "001"&x"67c08586", "001"&x"665ee585", "001"&x"64fda583", "001"&x"639cd582", "001"&x"623c7580", "001"&x"60dc657e", "001"&x"5f7cc57d", "001"&x"5e1d957b", "001"&x"5cbec57a", "001"&x"5b606578", "001"&x"5a025576", "001"&x"58a4c575", "001"&x"57478573", "001"&x"55eab572", "001"&x"548e5570", "001"&x"5332456e", "001"&x"51d6a56d", "001"&x"507b756b", "001"&x"4f20956a", "001"&x"4dc62568", "001"&x"4c6c2566", "001"&x"4b127565", "001"&x"49b93563", "001"&x"48605562", "001"&x"4707d560", "001"&x"45afc55f", "001"&x"4458155d", "001"&x"4300c55c", "001"&x"41a9d55a", "001"&x"40534558", "001"&x"3efd2557", "001"&x"3da76556", "001"&x"3c51f554", "001"&x"3afd0552", "001"&x"39a86551", "001"&x"3854254f", "001"&x"3700554e", "001"&x"35acd54c", "001"&x"3459c54b", "001"&x"33071549", "001"&x"31b4c548", "001"&x"3062d546", "001"&x"2f114545", "001"&x"2dc01543", "001"&x"2c6f4542", "001"&x"2b1ed540", "001"&x"29cec53e", "001"&x"287f153d", "001"&x"272fc53c", "001"&x"25e0d53a", "001"&x"24925539", "001"&x"23442537", "001"&x"21f65536", "001"&x"20a8e534", "001"&x"1f5bd533", "001"&x"1e0f2531", "001"&x"1cc2c530", "001"&x"1b76d52e", "001"&x"1a2b452d", "001"&x"18e0052b", "001"&x"1795352a", "001"&x"164ab528", "001"&x"15009527", "001"&x"13b6d526", "001"&x"126d7524", "001"&x"11247522", "001"&x"0fdbc521", "001"&x"0e937520", "001"&x"0d4b851e", "001"&x"0c03f51d", "001"&x"0abcc51b", "001"&x"0975e51a", "001"&x"082f7518", "001"&x"06e95517", "001"&x"05a38516", "001"&x"045e2514", "001"&x"03191513", "001"&x"01d46511", "001"&x"00901510", "000"&x"ff4c150e", "000"&x"fe08750d", "000"&x"fcc5350c", "000"&x"fb82450a", "000"&x"fa3fb509", "000"&x"f8fd8507", "000"&x"f7bba506", "000"&x"f67a2504", "000"&x"f538f503", "000"&x"f3f83502", "000"&x"f2b7b500", "000"&x"f177a4ff", "000"&x"f037e4fe", "000"&x"eef874fc", "000"&x"edb974fb", "000"&x"ec7ab4f9", "000"&x"eb3c54f8", "000"&x"e9fe54f6", "000"&x"e8c0b4f5", "000"&x"e78354f4", "000"&x"e64664f2", "000"&x"e509c4f1", "000"&x"e3cd74f0", "000"&x"e29184ee", "000"&x"e155e4ed", "000"&x"e01aa4ec", "000"&x"dedfb4ea", "000"&x"dda524e9", "000"&x"dc6ae4e8", "000"&x"db3104e6", "000"&x"d9f774e5", "000"&x"d8be34e4", "000"&x"d78554e2", "000"&x"d64cc4e1", "000"&x"d51494df", "000"&x"d3dcb4de", "000"&x"d2a524dd", "000"&x"d16df4db", "000"&x"d03714da", "000"&x"cf0094d9", "000"&x"cdca64d7", "000"&x"cc9484d6", "000"&x"cb5ef4d5", "000"&x"ca29c4d3", "000"&x"c8f4e4d2", "000"&x"c7c054d1", "000"&x"c68c24d0", "000"&x"c55844ce", "000"&x"c424b4cd", "000"&x"c2f184cc", "000"&x"c1bea4ca", "000"&x"c08c14c9", "000"&x"bf59d4c8", "000"&x"be27e4c6", "000"&x"bcf654c5", "000"&x"bbc514c4", "000"&x"ba9424c2", "000"&x"b96384c1", "000"&x"b83344c0", "000"&x"b70344be", "000"&x"b5d3a4bd", "000"&x"b4a454bc", "000"&x"b37554ba", "000"&x"b246b4b9", "000"&x"b11854b8", "000"&x"afea54b7", "000"&x"aebc94b6", "000"&x"ad8f34b4", "000"&x"ac6224b3", "000"&x"ab3564b2", "000"&x"aa08f4b0", "000"&x"a8dcd4af", "000"&x"a7b104ae", "000"&x"a68594ac", "000"&x"a55a64ab", "000"&x"a42f84aa", "000"&x"a30504a9", "000"&x"a1dac4a8", "000"&x"a0b0e4a6", "000"&x"9f8744a5", "000"&x"9e5e04a4", "000"&x"9d3504a2", "000"&x"9c0c64a1", "000"&x"9ae414a0", "000"&x"99bc049f", "000"&x"9894449e", "000"&x"976ce49c", "000"&x"9645c49b", "000"&x"951f049a", "000"&x"93f88498", "000"&x"92d25497", "000"&x"91ac7496", "000"&x"9086e495", "000"&x"8f61a494", "000"&x"8e3cb492", "000"&x"8d181491", "000"&x"8bf3b490", "000"&x"8acfb48f", "000"&x"89abf48e", "000"&x"8888948c", "000"&x"8765748b", "000"&x"8642a48a", "000"&x"85201489", "000"&x"83fde488", "000"&x"82dbf486", "000"&x"81ba6485", "000"&x"80991484", "000"&x"7f781483", "000"&x"7e575482", "000"&x"7d36f480", "000"&x"7c16d47f", "000"&x"7af7047e", "000"&x"79d7847d", "000"&x"78b8447c", "000"&x"7799547a", "000"&x"767ab479", "000"&x"755c6478", "000"&x"743e6477", "000"&x"7320a476", "000"&x"72033474", "000"&x"70e60473", "000"&x"6fc93472", "000"&x"6eaca471", "000"&x"6d905470", "000"&x"6c74546e", "000"&x"6b58b46e", "000"&x"6a3d446c", "000"&x"6922346b", "000"&x"6807646a", "000"&x"66ecd469", "000"&x"65d2a468", "000"&x"64b8a466", "000"&x"639f0465", "000"&x"6285a464", "000"&x"616c9463", "000"&x"6053c462", "000"&x"5f3b4461", "000"&x"5e231460", "000"&x"5d0b245e", "000"&x"5bf3745d", "000"&x"5adc245c", "000"&x"59c5045b", "000"&x"58ae445a", "000"&x"5797c459", "000"&x"56818458", "000"&x"556b9456", "000"&x"5455e456", "000"&x"53408454", "000"&x"522b7453", "000"&x"5116a452", "000"&x"50021451", "000"&x"4eedd450", "000"&x"4dd9e44f", "000"&x"4cc6344e", "000"&x"4bb2c44c", "000"&x"4a9fa44b", "000"&x"498cc44a", "000"&x"487a3449", "000"&x"4767e448", "000"&x"4655e447", "000"&x"45442446", "000"&x"4432a445", "000"&x"43217444", "000"&x"42108442", "000"&x"40ffe441", "000"&x"3fef8440", "000"&x"3edf643f", "000"&x"3dcf943e", "000"&x"3cc0143d", "000"&x"3bb0c43c", "000"&x"3aa1c43b", "000"&x"3993043a", "000"&x"38849439", "000"&x"37766438", "000"&x"36687436", "000"&x"355ad436", "000"&x"344d7434", "000"&x"33405433", "000"&x"32338432", "000"&x"3126f431", "000"&x"301aa430", "000"&x"2f0e942f", "000"&x"2e02d42e", "000"&x"2cf7542d", "000"&x"2bec142c", "000"&x"2ae1242b", "000"&x"29d6742a", "000"&x"28cc0428", "000"&x"27c1d428", "000"&x"26b7f426", "000"&x"25ae4425", "000"&x"24a4e424", "000"&x"239bd423", "000"&x"2292f422", "000"&x"218a6421", "000"&x"20821420", "000"&x"1f7a041f", "000"&x"1e72341e", "000"&x"1d6aa41d", "000"&x"1c63641c", "000"&x"1b5c541b", "000"&x"1a55941a", "000"&x"194f1419", "000"&x"1848e418", "000"&x"1742e417", "000"&x"163d3416", "000"&x"1537b415", "000"&x"14328414", "000"&x"132d9413", "000"&x"1228e412", "000"&x"11247410", "000"&x"10204410", "000"&x"0f1c540e", "000"&x"0e18b40e", "000"&x"0d15440c", "000"&x"0c12240c", "000"&x"0b0f340a", "000"&x"0a0c940a", "000"&x"090a3408", "000"&x"08081408", "000"&x"07062406", "000"&x"06048406", "000"&x"05032404", "000"&x"04020404", "000"&x"03012402", "000"&x"02008402", "000"&x"01002400");
signal addr_reg : std_logic_vector(9 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
addr_reg <= addrb;
end if;
end process;
doutb <= ram(conv_integer(addr_reg));
end tb_inv;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TABLE_SQRT is
port ( clk : in std_logic;
addrb: in std_logic_vector(9 downto 0);
doutb: out std_logic_vector(35 downto 0));
end TABLE_SQRT;
architecture tb_sqr of TABLE_SQRT is
type blockram is array (0 to 767) of std_logic_vector (35 downto 0);
constant ram : blockram := (x"000003ff9", x"007fe3fe9", x"00ff83fd9", x"017ee5fc9", x"01fe05fba", x"027cebfaa", x"02fb8ff9b", x"0379f7f8b", x"03f821f7c", x"04760ff6d", x"04f3bff5e", x"057133f4f", x"05ee6bf40", x"066b67f31", x"06e829f22", x"0764aff13", x"07e0f9f05", x"085d07ef7", x"08d8dfee8", x"09547beda", x"09cfdfecb", x"0a4b09ebd", x"0ac5f9eaf", x"0b40b1ea1", x"0bbb31e93", x"0c357be85", x"0caf8be77", x"0d2965e69", x"0da305e5c", x"0e1c71e4e", x"0e95a7e40", x"0f0ea5e33", x"0f876de26", x"100001e18", x"10785fe0b", x"10f087dfe", x"11687bdf1", x"11e03bde4", x"1257c7dd6", x"12cf1ddca", x"134641dbd", x"13bd31db0", x"1433edda3", x"14aa77d96", x"1520cfd89", x"1596f3d7d", x"160ce5d71", x"1682a5d65", x"16f835d58", x"176d91d4c", x"17e2bdd40", x"1857b9d33", x"18cc83d27", x"19411dd1b", x"19b587d0f", x"1a29c1d03", x"1a9dcbcf7", x"1b11a5ceb", x"1b854fcdf", x"1bf8cbcd4", x"1c6c17cc8", x"1cdf35cbd", x"1d5225cb1", x"1dc4e7ca5", x"1e377bc9a", x"1ea9e1c8e", x"1f1c19c83", x"1f8e23c78", x"200001c6c", x"2071b1c62", x"20e335c56", x"21548dc4b", x"21c5b9c40", x"2236b7c35", x"22a789c2b", x"231831c1f", x"2388adc14", x"23f8fdc0a", x"246923bff", x"24d91dbf4", x"2548edbe9", x"25b891bdf", x"26280dbd4", x"26975dbca", x"270683bbf", x"27757fbb5", x"27e453baa", x"2852fdba0", x"28c17db96", x"292fd3b8c", x"299e03b81", x"2a0c07b78", x"2a79e5b6d", x"2ae799b63", x"2b5525b59", x"2bc28bb4f", x"2c2fc7b45", x"2c9cdbb3c", x"2d09c9b31", x"2d768fb28", x"2de32db1e", x"2e4fa5b14", x"2ebbf5b0b", x"2f2821b01", x"2f9423af8", x"300001aee", x"306bb9ae4", x"30d749adb", x"3142b5ad1", x"31adf9ac8", x"321919abe", x"328413ab5", x"32eee9aac", x"335999aa2", x"33c423a9a", x"342e89a90", x"3498cba87", x"3502e7a7e", x"356cdfa75", x"35d6b3a6c", x"364065a63", x"36a9f1a5a", x"371359a51", x"377c9da48", x"37e5bfa3f", x"384ebba37", x"38b797a2e", x"39204da25", x"3988e3a1c", x"39f153a14", x"3a59a3a0b", x"3ac1cfa02", x"3b29d99fa", x"3b91c19f1", x"3bf9859e9", x"3c61299e0", x"3cc8ab9d8", x"3d300b9d0", x"3d97499c7", x"3dfe659bf", x"3e655f9b7", x"3ecc399ae", x"3f32f39a6", x"3f998b99e", x"400001996", x"40665798d", x"40cc8d985", x"4132a197d", x"419895975", x"41fe6996d", x"42641d965", x"42c9b195d", x"432f25955", x"43947b94d", x"43f9af945", x"445ec393d", x"44c3b9936", x"45288f92e", x"458d47926", x"45f1df91e", x"465657916", x"46bab190f", x"471eeb907", x"4783098ff", x"47e7078f8", x"484ae58f0", x"48aea78e8", x"4912498e1", x"4975cf8da", x"49d9358d2", x"4a3c7d8cb", x"4a9fa98c3", x"4b02b58bc", x"4b65a58b4", x"4bc8778ad", x"4c2b2d8a6", x"4c8dc389e", x"4cf03f897", x"4d529b890", x"4db4db889", x"4e16ff882", x"4e790587a", x"4edaef873", x"4f3cbd86c", x"4f9e6d865", x"50000185e", x"506179857", x"50c2d5850", x"512415849", x"518537842", x"51e63f83b", x"52472b834", x"52a7fb82d", x"5308b1826", x"53694981f", x"53c9c7818", x"542a29812", x"548a6f80b", x"54ea9b804", x"554aab7fd", x"55aaa17f6", x"560a7b7f0", x"566a3b7e9", x"56c9e17e2", x"57296b7dc", x"5788db7d5", x"57e82f7ce", x"58476b7c8", x"58a68b7c2", x"5905917bb", x"59647d7b4", x"59c3517ae", x"5a22097a8", x"5a80a77a1", x"5adf2b79a", x"5b3d95794", x"5b9be778e", x"5bfa1f788", x"5c583d781", x"5cb64177b", x"5d142d774", x"5d71ff76e", x"5dcfb7768", x"5e2d57762", x"5e8adf75b", x"5ee84d755", x"5f45a174f", x"5fa2dd749", x"600001742", x"605d0b73c", x"60b9ff736", x"6116d9730", x"61739972a", x"61d043724", x"622cd571e", x"62894d718", x"62e5ad712", x"6341f770c", x"639e27706", x"63fa41700", x"6456416fa", x"64b22b6f4", x"650dfd6ee", x"6569b76e8", x"65c5596e3", x"6620e56dd", x"667c596d7", x"66d7b56d1", x"6732f96cc", x"678e276c6", x"67e93f6c0", x"68443f6ba", x"689f276b4", x"68f9f96af", x"6954b56a9", x"69af596a3", x"6a09e769e", x"6a645f698", x"6abebf692", x"6b190968d", x"6b733d687", x"6bcd5b682", x"6c276167c", x"6c8153676", x"6cdb2d671", x"6d34f166c", x"6d8e9f666", x"6de839660", x"6e41bb65b", x"6e9b27656", x"6ef47f650", x"6f4dbf64b", x"6fa6eb645", x"700001640", x"70590163a", x"70b1ed635", x"710ac1630", x"71638162a", x"71bc2d625", x"7214c3620", x"726d4361b", x"72c5ad616", x"731e03610", x"73764560b", x"73ce71606", x"742689600", x"747e8b5fb", x"74d6795f6", x"752e515f1", x"7586175ec", x"75ddc55e7", x"7635615e2", x"768ce75dc", x"76e45b5d7", x"773bb75d2", x"7793015cd", x"77ea375c8", x"7841575c3", x"7898655be", x"78ef5d5b9", x"7946435b4", x"799d135af", x"79f3d15aa", x"7a4a795a5", x"7aa10f5a0", x"7af78f59b", x"7b4dfd596", x"7ba457592", x"7bfa9d58c", x"7c50cf588", x"7ca6ef583", x"7cfcfb57e", x"7d52f3579", x"7da8d9574", x"7dfea9570", x"7e546956b", x"7eaa13566", x"7effab561", x"7f553155c", x"7faaa3558", x"800001553", x"80554d54e", x"80aa8554a", x"80ffab545", x"8154bf540", x"81a9bf53b", x"81fead537", x"825389532", x"82a85152d", x"82fd07529", x"8351ab524", x"83a63b520", x"83fab951b", x"844f25516", x"84a37f512", x"84f7c750d", x"854bfd509", x"85a01f504", x"85f431500", x"86482f4fb", x"869c1b4f6", x"86eff74f2", x"8743bf4ee", x"8797754e9", x"87eb1b4e5", x"883ead4e0", x"88922f4dc", x"88e59f4d7", x"8938fd4d3", x"898c494ce", x"89df834ca", x"8a32ab4c6", x"8a85c34c1", x"8ad8c94bd", x"8b2bbd4b9", x"8b7ea14b4", x"8bd1734b0", x"8c24334ac", x"8c76e34a7", x"8cc9814a3", x"8d1c0d49f", x"8d6e8949a", x"8dc0f3496", x"8e134d492", x"8e659548e", x"8eb7cd48a", x"8f09f3485", x"8f5c09481", x"8fae0d47d", x"900001479", x"9051e5474", x"90a3b7470", x"90f57946c", x"914729468", x"9198c9464", x"91ea59460", x"923bd945c", x"928d47458", x"92dea7453", x"932ff344f", x"93813144b", x"93d25f447", x"94237b443", x"94748943f", x"94c58543b", x"951671437", x"95674d433", x"95b81942f", x"9608d542b", x"965981427", x"96aa1d423", x"96faa941f", x"974b2541b", x"979b91417", x"97ebed413", x"983c3940f", x"988c7540b", x"98dca3407", x"992cbf403", x"997ccd3ff", x"99cccb3fc", x"9a1cb93f8", x"9a6c973f4", x"9abc673f0", x"9b0c273ec", x"9b5bd73e8", x"9bab773e4", x"9bfb093e0", x"9c4a8b3dc", x"9c99fd3d9", x"9ce9613d5", x"9d38b53d1", x"9d87f93cd", x"9dd72f3ca", x"9e26553c6", x"9e756d3c2", x"9ec4753be", x"9f136f3ba", x"9f62593b7", x"9fb1353b3", x"a000013af", x"a04ebf3ac", x"a09d6d3a8", x"a0ec0d3a4", x"a13a9d3a0", x"a1891f39d", x"a1d793399", x"a225f7395", x"a2744d392", x"a2c29538e", x"a310cd38a", x"a35ef9387", x"a3ad13383", x"a3fb21380", x"a4491f37c", x"a4970f378", x"a4e4f1375", x"a532c5371", x"a5808936e", x"a5ce3f36a", x"a61be7366", x"a66981363", x"a6b70d35f", x"a7048b35c", x"a751fb358", x"a79f5b355", x"a7ecaf351", x"a839f334e", x"a8872b34a", x"a8d453346", x"a9216d343", x"a96e7b340", x"a9bb7933c", x"aa086b339", x"aa554d335", x"aaa223332", x"aaeeeb32e", x"ab3ba532b", x"ab884f328", x"abd4ef324", x"ac217f320", x"ac6e0131d", x"acba7731a", x"ad06dd316", x"ad5337313", x"ad9f83310", x"adebc330c", x"ae37f3309", x"ae8417306", x"aed02d302", x"af1c372ff", x"af68332fc", x"afb4212f8", x"b000012f5", x"b04bd52f2", x"b0979b2ee", x"b0e3532eb", x"b12eff2e8", x"b17a9d2e4", x"b1c62f2e1", x"b211b32de", x"b25d292da", x"b2a8932d7", x"b2f3f12d4", x"b33f412d0", x"b38a832cd", x"b3d5b92ca", x"b420e12c7", x"b46bfd2c4", x"b4b70b2c0", x"b5020d2bd", x"b54d032ba", x"b597eb2b7", x"b5e2c72b4", x"b62d952b0", x"b678572ad", x"b6c30d2aa", x"b70db52a7", x"b758512a4", x"b7a2df2a0", x"b7ed6329d", x"b837d929a", x"b88241297", x"b8cc9f294", x"b916ef291", x"b9613328e", x"b9ab6928a", x"b9f593288", x"ba3fb3284", x"ba89c5281", x"bad3c927e", x"bb1dc327b", x"bb67af278", x"bbb18f275", x"bbfb65272", x"bc452d26f", x"bc8ee726c", x"bcd897269", x"bd223b266", x"bd6bd1262", x"bdb55d260", x"bdfedb25c", x"be484d25a", x"be91b5256", x"bedb0f254", x"bf245d250", x"bf6d9f24e", x"bfb6d724a", x"c00001248", x"c0491f244", x"c09233242", x"c0db3923e", x"c1243323c", x"c16d23239", x"c1b607236", x"c1fedd233", x"c247a9230", x"c2906922d", x"c2d91d22a", x"c321c5227", x"c36a63224", x"c3b2f3221", x"c3fb7921e", x"c443f321c", x"c48c61218", x"c4d4c3216", x"c51d1b213", x"c56567210", x"c5ada720d", x"c5f5db20a", x"c63e03207", x"c68621204", x"c6ce33202", x"c716391ff", x"c75e351fc", x"c7a6251f9", x"c7ee091f6", x"c835e31f3", x"c87db11f0", x"c8c5731ee", x"c90d2b1eb", x"c954d71e8", x"c99c771e5", x"c9e40d1e2", x"ca2b991e0", x"ca73171dd", x"caba8b1da", x"cb01f51d7", x"cb49531d4", x"cb90a51d2", x"cbd7ed1cf", x"cc1f2b1cc", x"cc665d1ca", x"ccad831c7", x"ccf49f1c4", x"cd3baf1c1", x"cd82b51be", x"cdc9b11bc", x"ce10a11b9", x"ce57851b6", x"ce9e5f1b4", x"cee52f1b1", x"cf2bf31ae", x"cf72ad1ac", x"cfb95d1a9", x"d000011a6", x"d0469b1a4", x"d08d291a1", x"d0d3ad19e", x"d11a2719c", x"d16095199", x"d1a6f9196", x"d1ed53194", x"d233a1191", x"d279e718e", x"d2c01f18c", x"d3064f189", x"d34c73186", x"d3928d184", x"d3d89d181", x"d41ea117e", x"d4649d17c", x"d4aa8d179", x"d4f073177", x"d5364d174", x"d57c1f172", x"d5c1e516f", x"d607a116c", x"d64d5316a", x"d692fb167", x"d6d897164", x"d71e2b162", x"d763b3160", x"d7a93115d", x"d7eea515a", x"d8340f158", x"d8796f155", x"d8bec5153", x"d90411150", x"d9495114e", x"d98e8914b", x"d9d3b5148", x"da18d9146", x"da5df1144", x"daa2ff141", x"dae80513e", x"db2cff13c", x"db71f113a", x"dbb6d7137", x"dbfbb3134", x"dc4087132", x"dc854f130", x"dcca0f12d", x"dd0ec312b", x"dd536f128", x"dd980f126", x"dddca7123", x"de2135121", x"de65b911e", x"deaa3111c", x"deeea311a", x"df3309117", x"df7765114", x"dfbbb7112", x"e00001110", x"e0444110d", x"e0887710b", x"e0cca3108", x"e110c5106", x"e154dd104", x"e198ed101", x"e1dcf10ff", x"e220ed0fc", x"e264e10fa", x"e2a8c90f8", x"e2eca90f5", x"e3307d0f3", x"e374490f0", x"e3b80d0ee", x"e3fbc50ec", x"e43f750ea", x"e4831b0e7", x"e4c6b90e5", x"e50a4b0e2", x"e54dd50e0", x"e591570de", x"e5d4cd0db", x"e6183b0d9", x"e65b9f0d7", x"e69efb0d4", x"e6e24d0d2", x"e725950d0", x"e768d50cd", x"e7ac0b0cb", x"e7ef370c9", x"e8325b0c6", x"e875750c4", x"e8b8850c2", x"e8fb8d0c0", x"e93e8d0bd", x"e981810bb", x"e9c46f0b9", x"ea07510b6", x"ea4a2b0b4", x"ea8cfd0b2", x"eacfc50b0", x"eb12830ad", x"eb55390ab", x"eb97e50a9", x"ebda890a6", x"ec1d230a4", x"ec5fb50a2", x"eca23d0a0", x"ece4bd09e", x"ed273309b", x"ed69a1099", x"edac07097", x"edee63094", x"ee30b5092", x"ee72ff090", x"eeb54108e", x"eef77908c", x"ef39a708a", x"ef7bcf087", x"efbded085", x"f00001083", x"f0420d081", x"f0841107e", x"f0c60b07c", x"f107fd07a", x"f149e5078", x"f18bc7076", x"f1cd9d074", x"f20f6d072", x"f2513306f", x"f292f106d", x"f2d4a506b", x"f31651069", x"f357f5066", x"f39991064", x"f3db23062", x"f41cad060", x"f45e2d05e", x"f49fa505c", x"f4e11705a", x"f5227d058", x"f563dd056", x"f5a533053", x"f5e681051", x"f627c704f", x"f6690304d", x"f6aa3704b", x"f6eb63049", x"f72c87047", x"f76da3044", x"f7aeb5042", x"f7efbf040", x"f830c103e", x"f871bb03c", x"f8b2ad03a", x"f8f395038", x"f93475036", x"f9754f034", x"f9b61f032", x"f9f6e5030", x"fa37a502e", x"fa785b02c", x"fab90b02a", x"faf9b1028", x"fb3a4f026", x"fb7ae5023", x"fbbb73021", x"fbfbf901f", x"fc3c7701d", x"fc7ceb01b", x"fcbd59019", x"fcfdbd017", x"fd3e1b015", x"fd7e6f013", x"fdbebb011", x"fdfeff00f", x"fe3f3d00d", x"fe7f7100b", x"febf9d009", x"feffc1007", x"ff3fdd005", x"ff7ff1003", x"ffbffd001");
signal addr_reg : std_logic_vector(9 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
addr_reg <= addrb;
end if;
end process;
doutb <= ram(conv_integer(addr_reg)); -- ブロックRAMにするにはここをレジスタ信号にする。
end tb_sqr;
|
apache-2.0
|
8b2e503f06ce149d5cca534b21ec1f1f
| 0.66127 | 1.80737 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/BUFIO2 DDR/top_nto1_ddr_se_tx.vhd
| 1 | 7,600 |
------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_ddr_se_tx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example single ended output transmitter for DDR clock and data using 2 x BUFIO2
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------/
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_ddr_se_tx is port (
reset : in std_logic ; -- reset (active high)
refclkin_p, refclkin_n : in std_logic ; -- frequency generator clock input
dataout : out std_logic_vector(7 downto 0) ; -- single ended data outputs
clkout : out std_logic ) ; -- single ended clock output
end top_nto1_ddr_se_tx ;
architecture arch_top_nto1_ddr_se_tx of top_nto1_ddr_se_tx is
component clock_generator_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclkap : out std_logic ; -- A P ioclock from BUFIO2
ioclkan : out std_logic ; -- A N ioclock from BUFIO2
serdesstrobea : out std_logic ; -- A serdes strobe from BUFIO2
ioclkbp : out std_logic ; -- B P ioclock from BUFIO2 - leave open if not required
ioclkbn : out std_logic ; -- B N ioclock from BUFIO2 - leave open if not required
serdesstrobeb : out std_logic ; -- B serdes strobe from BUFIO2 - leave open if not required
gclk : out std_logic) ; -- global clock output from BUFIO2
end component ;
component serdes_n_to_1_ddr_s8_se is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclkp : in std_logic ; -- IO Clock network
txioclkn : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout : out std_logic_vector(D-1 downto 0)) ; -- output
end component ;
-- Parameters for serdes factor and number of IO pins
constant S : integer := 8 ; -- Set the serdes factor
constant D : integer := 8 ; -- Set the number of inputs and outputs
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal rst : std_logic ;
signal txd : std_logic_vector(DS downto 0) ; -- Registered Data to serdeses
signal txioclkp : std_logic ;
signal txioclkn : std_logic ;
signal tx_serdesstrobe : std_logic ;
signal tx_bufg_x1 : std_logic ;
signal clkoutb : std_logic_vector(0 downto 0) ;
-- Parameters for clock generation
constant TX_CLK_GEN : std_logic_vector(S-1 downto 0) := X"AA" ; -- Transmit a constant to make a clock
begin
rst <= reset ; -- active high reset pin
-- Reference Clock Input genertaes IO clocks via 2 x BUFIO2
inst_clkgen : clock_generator_ddr_s8_diff generic map(
S => S)
port map(
clkin_p => refclkin_p,
clkin_n => refclkin_n,
ioclkap => txioclkp,
ioclkan => txioclkn,
serdesstrobea => tx_serdesstrobe,
ioclkbp => open,
ioclkbn => open,
serdesstrobeb => open,
gclk => tx_bufg_x1) ;
process (tx_bufg_x1, rst) -- Generate some data to transmit
begin
if rst = '1' then
txd <= X"3000000000000001" ;
elsif tx_bufg_x1'event and tx_bufg_x1 = '1' then
txd <= txd(63 downto 60) & txd(58 downto 0) & txd(59) ;
end if ;
end process ;
-- Transmitter Logic - Instantiate serialiser to generate forwarded clock
inst_clkout : serdes_n_to_1_ddr_s8_se generic map(
S => S,
D => 1)
port map (
dataout => clkoutb,
txioclkp => txioclkp,
txioclkn => txioclkn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => TX_CLK_GEN); -- Transmit a constant to make the clock
clkout <= clkoutb(0) ;
-- Instantiate Outputs and output serialisers for output data lines
inst_dataout : serdes_n_to_1_ddr_s8_se generic map(
S => S,
D => D)
port map (
dataout => dataout,
txioclkp => txioclkp,
txioclkn => txioclkn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => txd);
end arch_top_nto1_ddr_se_tx ;
|
apache-2.0
|
00c55c1a085b901baec385ee316357ab
| 0.6025 | 3.648584 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.