repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/PLL/top_nto1_pll_diff_rx_and_tx.vhd
| 1 | 10,131 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_pll_diff_rx_and_tx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example differential input receiver and transmitter for clock and data using PLL
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_pll_diff_rx_and_tx is port (
reset : in std_logic ; -- reset (active high)
clkin_p, clkin_n : in std_logic ; -- lvds clock input
datain_p, datain_n : in std_logic_vector(5 downto 0) ; -- lvds data inputs
clkout_p, clkout_n : out std_logic ; -- lvds clock output
dataout_p, dataout_n : out std_logic_vector(5 downto 0)) ; -- lvds data outputs
end top_nto1_pll_diff_rx_and_tx ;
architecture arch_top_nto1_pll_diff_rx_and_tx of top_nto1_pll_diff_rx_and_tx is
component serdes_1_to_n_data_s8_diff generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic ; -- Set generation of phase detector logic
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclk : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
debug_in : in std_logic_vector(1 downto 0) ; -- input debug data
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end component ;
component serdes_1_to_n_clk_pll_s8_diff generic (
PLLD : integer := 1 ; -- Parameter to set division for PLL
CLKIN_PERIOD : real := 6.700 ; -- Set PLL multiplier
PLLX : integer := 2 ; -- Set PLL multiplier
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
BS : boolean := FALSE) ; -- Parameter to enable bitslip TRUE or FALSE
port (
clkin_p : in std_logic ; -- Input from LVDS receiver pin
clkin_n : in std_logic ; -- Input from LVDS receiver pin
reset : in std_logic ; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0) ; -- Data to define pattern that bitslip should search for
pattern2 : in std_logic_vector(S-1 downto 0) ; -- Data to define alternate pattern that bitslip should search for
rxioclk : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_pll_x1 : out std_logic ; -- Global clock
rx_pll_lckd : out std_logic ; -- PLL locked - only used if a 2nd BUFPLL is required
rx_pllout_xs : out std_logic ; -- Multiplied PLL clock - only used if a 2nd BUFPLL is required
bitslip : out std_logic ; -- Bitslip control line
datain : out std_logic_vector(S-1 downto 0) ; -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end component ;
component serdes_n_to_1_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end component ;
-- Parameters for serdes factor and number of IO pins
constant S : integer := 7 ; -- Set the serdes factor to be 4
constant D : integer := 6 ; -- Set the number of inputs and outputs to be 6
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal clk_iserdes_data : std_logic_vector(6 downto 0) ;
signal rx_bufg_x1 : std_logic ;
signal rxd : std_logic_vector(DS downto 0) ;
signal capture : std_logic_vector(6 downto 0) ;
signal counter : std_logic_vector(3 downto 0) ;
signal bitslip : std_logic ;
signal rst : std_logic ;
signal rx_serdesstrobe : std_logic ;
signal rx_bufpll_clk_xn : std_logic ;
signal rx_bufpll_lckd : std_logic ;
signal not_bufpll_lckd : std_logic ;
signal temp1p : std_logic_vector(0 downto 0) ;
signal temp1n : std_logic_vector(0 downto 0) ;
signal txd : std_logic_vector(DS downto 0) ;
constant TX_CLK_GEN : std_logic_vector(S-1 downto 0) := "1100001" ; -- Transmit a constant to make a clock
begin
rst <= reset ; -- active high reset pin
-- Clock Input, Generate ioclocks via PLL
clkin : serdes_1_to_n_clk_pll_s8_diff generic map(
CLKIN_PERIOD => 6.700,
PLLD => 1,
PLLX => S,
S => S,
BS => TRUE) -- Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
port map (
clkin_p => clkin_p,
clkin_n => clkin_n,
rxioclk => rx_bufpll_clk_xn,
pattern1 => "1100001", -- default values for 7:1 video applications
pattern2 => "1100011",
rx_serdesstrobe => rx_serdesstrobe,
rx_bufg_pll_x1 => rx_bufg_x1,
bitslip => bitslip,
reset => rst,
datain => clk_iserdes_data,
rx_pll_lckd => open, -- PLL locked - only used if a 2nd BUFPLL is required
rx_pllout_xs => open, -- Multiplied PLL clock - only used if a 2nd BUFPLL is required
rx_bufpll_lckd => rx_bufpll_lckd) ;
-- Data Inputs
not_bufpll_lckd <= not rx_bufpll_lckd ;
datain : serdes_1_to_n_data_s8_diff generic map(
S => S,
D => D)
port map (
use_phase_detector => '1',
datain_p => datain_p,
datain_n => datain_n,
rxioclk => rx_bufpll_clk_xn,
rxserdesstrobe => rx_serdesstrobe,
gclk => rx_bufg_x1,
bitslip => bitslip,
reset => not_bufpll_lckd,
debug_in => "00",
data_out => rxd,
debug => open) ;
process (rx_bufg_x1)
begin
if rx_bufg_x1'event and rx_bufg_x1 = '1' then
txd <= rxd ;
end if ;
end process ;
-- Transmitter Logic - Instantiate serialiser to generate forwarded clock
clkout : serdes_n_to_1_s8_diff generic map (
S => S,
D => 1)
port map (
dataout_p => temp1p,
dataout_n => temp1n,
txioclk => rx_bufpll_clk_xn,
txserdesstrobe => rx_serdesstrobe,
gclk => rx_bufg_x1,
reset => rst,
datain => TX_CLK_GEN); -- Transmit a constant to make the clock
clkout_p <= temp1p(0) ;
clkout_n <= temp1n(0) ;
-- Instantiate Outputs and output serialisers for output data lines
dataout : serdes_n_to_1_s8_diff generic map(
S => S,
D => D)
port map (
dataout_p => dataout_p,
dataout_n => dataout_n,
txioclk => rx_bufpll_clk_xn,
txserdesstrobe => rx_serdesstrobe,
gclk => rx_bufg_x1,
reset => rst,
datain => txd);
end arch_top_nto1_pll_diff_rx_and_tx ;
|
apache-2.0
|
fbc27ac10d72983f55740676cb9898db
| 0.619485 | 3.20196 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/SimpleUnitReanamedPort5.vhd
| 1 | 1,111 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleUnitReanamedPort5 IS
PORT(
b_eth_rx : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
b_eth_rx_vld : IN STD_LOGIC;
b_eth_tx_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
b_eth_tx_last : OUT STD_LOGIC;
b_eth_tx_ready : IN STD_LOGIC;
b_eth_tx_valid : OUT STD_LOGIC;
b_rx_last : IN STD_LOGIC;
b_rx_ready : OUT STD_LOGIC;
eth_rx : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
eth_rx_vld : OUT STD_LOGIC;
eth_tx_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
eth_tx_last : IN STD_LOGIC;
eth_tx_ready : OUT STD_LOGIC;
eth_tx_valid : IN STD_LOGIC;
rx_last : OUT STD_LOGIC;
rx_ready : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleUnitReanamedPort5 IS
BEGIN
b_eth_tx_data <= eth_tx_data;
b_eth_tx_last <= eth_tx_last;
b_eth_tx_valid <= eth_tx_valid;
b_rx_ready <= rx_ready;
eth_rx <= b_eth_rx;
eth_rx_vld <= b_eth_rx_vld;
eth_tx_ready <= b_eth_tx_ready;
rx_last <= b_rx_last;
END ARCHITECTURE;
|
mit
|
4433744a0d81fa79bb452401f0d4f916
| 0.593159 | 2.91601 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_orbit_intlk/orbit_intlk_cdc_fifo.vhd
| 1 | 3,318 |
------------------------------------------------------------------------------
-- Title : CDC FIFO for Position data
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-23
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: CDC FIFO for generic data. Suitable for CDC position data
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-09-23 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Genrams
use work.genram_pkg.all;
entity orbit_intlk_cdc_fifo is
generic
(
g_data_width : natural;
g_size : natural
);
port
(
clk_wr_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
valid_i : in std_logic;
clk_rd_i : in std_logic;
rd_i : in std_logic;
data_o : out std_logic_vector(g_data_width-1 downto 0);
valid_o : out std_logic;
empty_o : out std_logic
);
end orbit_intlk_cdc_fifo;
architecture rtl of orbit_intlk_cdc_fifo is
constant c_guard_size : integer := 2;
constant c_almost_empty_thres : integer := c_guard_size;
constant c_almost_full_thres : integer := g_size - c_guard_size;
signal fifo_cdc_empty : std_logic;
signal fifo_cdc_valid : std_logic;
begin
cmp_orbit_intlk_cdc_fifo : inferred_async_fifo
generic map(
g_data_width => g_data_width,
g_size => g_size,
g_almost_empty_threshold => c_almost_empty_thres,
g_almost_full_threshold => c_almost_full_thres
)
port map(
rst_n_i => '1',
-- write port
clk_wr_i => clk_wr_i,
d_i => data_i,
we_i => valid_i, -- and valid
wr_full_o => open,
-- read port
clk_rd_i => clk_rd_i,
q_o => data_o,
rd_i => rd_i,
rd_empty_o => fifo_cdc_empty
);
empty_o <= fifo_cdc_empty;
p_gen_cdc_valid: process (clk_rd_i)
begin
if rising_edge (clk_rd_i) then
fifo_cdc_valid <= rd_i;
if fifo_cdc_empty = '1' then
fifo_cdc_valid <= '0';
end if;
end if;
end process;
valid_o <= fifo_cdc_valid;
end rtl;
|
lgpl-3.0
|
a435a94f8df986e3e8963326ec52c260
| 0.386679 | 4.483784 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_position_calc/wb_position_calc_core.vhd
| 1 | 139,645 |
------------------------------------------------------------------------------
-- Title : Wishbone Position Calculation Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-07-02
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Core Module for position calculation with de-cross and delay tuning.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-07-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- BPM cores
use work.bpm_cores_pkg.all;
-- Position Calc
use work.position_calc_core_pkg.all;
-- Counter Generator Definitions
use work.counters_gen_pkg.all;
entity wb_position_calc_core is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false;
g_rffe_version : string := "V2";
-- selection of position_calc stages
g_with_downconv : boolean := true;
-- input sizes
g_input_width : natural := 16;
g_mixed_width : natural := 16;
g_adc_ratio : natural := 1;
-- mixer
g_dds_width : natural := 16;
g_dds_points : natural := 35;
g_sin_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_sin.nif";
g_cos_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_cos.nif";
-- CIC setup
g_tbt_cic_delay : natural := 1;
g_tbt_cic_stages : natural := 2;
g_tbt_ratio : natural := 35; -- ratio between
g_tbt_decim_width : natural := 32;
g_fofb_cic_delay : natural := 1;
g_fofb_cic_stages : natural := 2;
g_fofb_ratio : natural := 980; -- ratio between adc and fofb rates
g_fofb_decim_width : natural := 32;
g_monit1_cic_delay : natural := 1;
g_monit1_cic_stages : natural := 1;
g_monit1_ratio : natural := 100; --ratio between fofb and monit 1
g_monit1_cic_ratio : positive := 8;
g_monit2_cic_delay : natural := 1;
g_monit2_cic_stages : natural := 1;
g_monit2_ratio : natural := 100; -- ratio between monit 1 and 2
g_monit2_cic_ratio : positive := 8;
g_monit_decim_width : natural := 32;
-- Cordic setup
g_tbt_cordic_stages : positive := 12;
g_tbt_cordic_iter_per_clk : positive := 3;
g_tbt_cordic_ratio : positive := 4;
g_fofb_cordic_stages : positive := 15;
g_fofb_cordic_iter_per_clk : positive := 3;
g_fofb_cordic_ratio : positive := 4;
-- width of K constants
g_k_width : natural := 25;
-- width of offset constants
g_offset_width : natural := 32;
--width for IQ output
g_IQ_width : natural := 32;
-- Swap/de-swap setup
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch2_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch3_i : in std_logic_vector(g_input_width-1 downto 0);
adc_valid_i : in std_logic;
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch1_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch2_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch3_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_tag_o : out std_logic_vector(0 downto 0);
adc_swap_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit1_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_valid_o : out std_logic;
monit_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
tbt_pos_x_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_y_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_sum_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_valid_o : out std_logic;
fofb_pos_x_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_y_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_sum_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_valid_o : out std_logic;
monit1_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_valid_o : out std_logic;
monit_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
rffe_swclk_o : out std_logic;
-----------------------------
-- Synchronization trigger for all rates. Slow clock
-----------------------------
sync_trig_slow_i : in std_logic;
-----------------------------
-- Debug signals
-----------------------------
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(g_input_width-1 downto 0)
);
end wb_position_calc_core;
architecture rtl of wb_position_calc_core is
---------------------------------------------------------
-- Functions --
---------------------------------------------------------
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end f_log2_size;
---------------------------------------------------------
-- Constants --
---------------------------------------------------------
constant c_periph_addr_size : natural := 7+2;
constant c_cdc_tbt_width : natural := 4*g_tbt_decim_width;
constant c_cdc_fofb_width : natural := 4*g_fofb_decim_width;
constant c_cdc_monit1_width : natural := 4*g_monit_decim_width;
constant c_cdc_monit_width : natural := 4*g_monit_decim_width;
constant c_cdc_mix_iq_width : natural := 8*g_IQ_width;
constant c_cdc_tbt_iq_width : natural := 8*g_tbt_decim_width;
constant c_cdc_fofb_iq_width : natural := 8*g_fofb_decim_width;
constant c_cdc_adc_width : natural := g_input_width;
constant c_cdc_ref_size : natural := 4;
constant c_tbt_decim_tag_dly_width : natural := 9;
constant c_tbt_tag_desync_cnt_width : natural := 14;
constant c_tbt_cic_mask_samples_width : natural := 10;
constant c_monit1_decim_tag_dly_width : natural := 9;
constant c_monit1_tag_desync_cnt_width : natural := 14;
constant c_monit1_cic_mask_samples_width : natural := 10;
constant c_monit2_decim_tag_dly_width : natural := 9;
constant c_monit2_tag_desync_cnt_width : natural := 14;
constant c_monit2_cic_mask_samples_width : natural := 10;
constant c_fofb_decim_desync_cnt_width : natural := 14;
constant c_fofb_cic_mask_samples_width : natural := 16;
-- full ratio is the accumulated ratio between data and clock.
constant c_adc_ratio : natural := g_adc_ratio;
constant c_tbt_ratio : natural := g_tbt_ratio;
constant c_fofb_ratio : natural := g_fofb_ratio;
constant c_monit1_ratio : natural := g_monit1_ratio;
constant c_monit2_ratio : natural := g_monit2_ratio;
constant c_adc_ratio_log2 : natural := f_log2_size(c_adc_ratio+1);
constant c_tbt_ratio_log2 : natural := f_log2_size(c_tbt_ratio+1);
constant c_fofb_ratio_log2 : natural := f_log2_size(c_fofb_ratio+1);
constant c_monit1_ratio_log2 : natural := f_log2_size(c_monit1_ratio+1);
constant c_monit2_ratio_log2 : natural := f_log2_size(c_monit2_ratio+1);
-- This must not exceed the width determined at the register file
constant c_k_width : natural := g_k_width;
constant c_offset_width : natural := g_offset_width;
constant c_cnt_width_raw : natural := g_adc_ratio;
constant c_cnt_width_mix : natural := g_IQ_width;
constant c_cnt_width_processed : natural := g_tbt_decim_width;
constant c_counters_mix_idx : natural := 0;
constant c_counters_tbt_decim_idx : natural := 1;
constant c_counters_tbt_amp_idx : natural := 2;
constant c_counters_tbt_pha_idx : natural := 3;
constant c_counters_tbt_pos_idx : natural := 4;
constant c_counters_fofb_decim_idx : natural := 5;
constant c_counters_fofb_amp_idx : natural := 6;
constant c_counters_fofb_pha_idx : natural := 7;
constant c_counters_fofb_pos_idx : natural := 8;
constant c_counters_monit1_amp_idx : natural := 9;
constant c_counters_monit1_pos_idx : natural := 10;
constant c_counters_monit_amp_idx : natural := 11;
constant c_counters_monit_pos_idx : natural := 12;
constant c_num_counters : natural := 13; -- All DSP rates
constant c_cnt_width_array : t_cnt_width_array(c_num_counters-1 downto 0) :=
(
c_counters_mix_idx => c_cnt_width_mix,
c_counters_tbt_decim_idx => c_cnt_width_processed,
c_counters_tbt_amp_idx => c_cnt_width_processed,
c_counters_tbt_pha_idx => c_cnt_width_processed,
c_counters_tbt_pos_idx => c_cnt_width_processed,
c_counters_fofb_decim_idx => c_cnt_width_processed,
c_counters_fofb_amp_idx => c_cnt_width_processed,
c_counters_fofb_pha_idx => c_cnt_width_processed,
c_counters_fofb_pos_idx => c_cnt_width_processed,
c_counters_monit1_amp_idx => c_cnt_width_processed,
c_counters_monit1_pos_idx => c_cnt_width_processed,
c_counters_monit_amp_idx => c_cnt_width_processed,
c_counters_monit_pos_idx => c_cnt_width_processed
);
-- Crossbar component constants
-- Number of slaves
constant c_slaves : natural := 2;
-- Number of masters
constant c_masters : natural := 1; -- Top master.
constant c_num_pipeline_regs : integer := 8;
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(c_xwb_pos_calc_core_regs_sdb,
x"00000000"), -- Register interface
1 => f_sdb_embed_device(c_xwb_bpm_swap_sdb, x"00000400") -- WB swap
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well.
constant c_sdb_address : t_wishbone_address := x"00000600";
-----------------------------
-- Wishbone slave adapter signals/structures
-----------------------------
signal wb_slv_adp_out : t_wishbone_master_out;
signal wb_slv_adp_in : t_wishbone_master_in;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
-- Register interface signals
signal regs_ds_tbt_thres_val_o : std_logic_vector(25 downto 0);
signal regs_ds_tbt_thres_reserved_i : std_logic_vector(5 downto 0) := (others => '0');
signal regs_ds_fofb_thres_val_o : std_logic_vector(25 downto 0);
signal regs_ds_fofb_thres_reserved_i : std_logic_vector(5 downto 0) := (others => '0');
signal regs_ds_monit_thres_val_o : std_logic_vector(25 downto 0);
signal regs_ds_monit_thres_reserved_i : std_logic_vector(5 downto 0) := (others => '0');
signal regs_kx_val_o : std_logic_vector(24 downto 0);
signal regs_kx_reserved_i : std_logic_vector(6 downto 0) := (others => '0');
signal regs_ky_val_o : std_logic_vector(24 downto 0);
signal regs_ky_reserved_i : std_logic_vector(6 downto 0) := (others => '0');
signal regs_ksum_val_o : std_logic_vector(24 downto 0);
signal regs_ksum_reserved_i : std_logic_vector(6 downto 0) := (others => '0');
signal regs_dsp_ctnr_tbt_ch01_i : std_logic_vector(15 downto 0) := (others => '0');
signal regs_dsp_ctnr_tbt_ch23_i : std_logic_vector(15 downto 0) := (others => '0');
signal regs_dsp_ctnr_fofb_ch01_i : std_logic_vector(15 downto 0) := (others => '0');
signal regs_dsp_ctnr_fofb_ch23_i : std_logic_vector(15 downto 0) := (others => '0');
signal regs_dsp_ctnr1_monit_cic_i : std_logic_vector(15 downto 0) := (others => '0');
signal regs_dsp_ctnr1_monit_cfir_i : std_logic_vector(15 downto 0) := (others => '0');
signal regs_dsp_ctnr2_monit_pfir_i : std_logic_vector(15 downto 0) := (others => '0');
signal regs_dsp_ctnr2_monit_fir_01_i : std_logic_vector(15 downto 0) := (others => '0');
signal regs_dsp_err_clr_tbt_o : std_logic;
signal regs_dsp_err_clr_fofb_o : std_logic;
signal regs_dsp_err_clr_monit_part1_o : std_logic;
signal regs_dsp_err_clr_monit_part2_o : std_logic;
signal regs_dds_cfg_valid_ch0_o : std_logic;
signal regs_dds_cfg_test_data_o : std_logic;
signal regs_dds_cfg_reserved_ch0_i : std_logic_vector(5 downto 0) := (others => '0');
signal regs_dds_cfg_valid_ch1_o : std_logic;
signal regs_dds_cfg_reserved_ch1_i : std_logic_vector(6 downto 0) := (others => '0');
signal regs_dds_cfg_valid_ch2_o : std_logic;
signal regs_dds_cfg_reserved_ch2_i : std_logic_vector(6 downto 0) := (others => '0');
signal regs_dds_cfg_valid_ch3_o : std_logic;
signal regs_dds_cfg_reserved_ch3_i : std_logic_vector(6 downto 0) := (others => '0');
signal regs_dds_pinc_ch0_val_o : std_logic_vector(29 downto 0);
signal regs_dds_pinc_ch0_reserved_i : std_logic_vector(1 downto 0) := (others => '0');
signal regs_dds_pinc_ch1_val_o : std_logic_vector(29 downto 0);
signal regs_dds_pinc_ch1_reserved_i : std_logic_vector(1 downto 0) := (others => '0');
signal regs_dds_pinc_ch2_val_o : std_logic_vector(29 downto 0);
signal regs_dds_pinc_ch2_reserved_i : std_logic_vector(1 downto 0) := (others => '0');
signal regs_dds_pinc_ch3_val_o : std_logic_vector(29 downto 0);
signal regs_dds_pinc_ch3_reserved_i : std_logic_vector(1 downto 0) := (others => '0');
signal regs_dds_poff_ch0_val_o : std_logic_vector(29 downto 0);
signal regs_dds_poff_ch0_reserved_i : std_logic_vector(1 downto 0) := (others => '0');
signal regs_dds_poff_ch1_val_o : std_logic_vector(29 downto 0);
signal regs_dds_poff_ch1_reserved_i : std_logic_vector(1 downto 0) := (others => '0');
signal regs_dds_poff_ch2_val_o : std_logic_vector(29 downto 0);
signal regs_dds_poff_ch2_reserved_i : std_logic_vector(1 downto 0) := (others => '0');
signal regs_dds_poff_ch3_val_o : std_logic_vector(29 downto 0);
signal regs_dds_poff_ch3_reserved_i : std_logic_vector(1 downto 0) := (others => '0');
signal regs_dsp_monit_amp_ch0_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit_amp_ch1_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit_amp_ch2_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit_amp_ch3_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit_pos_x_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit_pos_y_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit_pos_q_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit_pos_sum_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit_updt_o : std_logic_vector(31 downto 0);
signal regs_dsp_monit_updt_wr_o : std_logic;
signal regs_dsp_monit1_amp_ch0_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit1_amp_ch1_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit1_amp_ch2_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit1_amp_ch3_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit1_pos_x_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit1_pos_y_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit1_pos_q_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit1_pos_sum_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_dsp_monit1_updt_o : std_logic_vector(31 downto 0);
signal regs_dsp_monit1_updt_wr_o : std_logic;
signal regs_ampfifo_monit_wr_req_i : std_logic := '0';
signal regs_ampfifo_monit_wr_full_o : std_logic;
signal regs_ampfifo_monit_wr_empty_o : std_logic;
signal regs_ampfifo_monit_wr_usedw_o : std_logic_vector(3 downto 0);
signal regs_ampfifo_monit_amp_ch0_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_ampfifo_monit_amp_ch1_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_ampfifo_monit_amp_ch2_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_ampfifo_monit_amp_ch3_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_posfifo_monit_wr_req_i : std_logic := '0';
signal regs_posfifo_monit_wr_full_o : std_logic;
signal regs_posfifo_monit_wr_empty_o : std_logic;
signal regs_posfifo_monit_wr_usedw_o : std_logic_vector(3 downto 0);
signal regs_posfifo_monit_pos_x_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_posfifo_monit_pos_y_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_posfifo_monit_pos_q_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_posfifo_monit_pos_sum_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_ampfifo_monit1_wr_req_i : std_logic := '0';
signal regs_ampfifo_monit1_wr_full_o : std_logic;
signal regs_ampfifo_monit1_wr_empty_o : std_logic;
signal regs_ampfifo_monit1_wr_usedw_o : std_logic_vector(3 downto 0);
signal regs_ampfifo_monit1_amp_ch0_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_ampfifo_monit1_amp_ch1_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_ampfifo_monit1_amp_ch2_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_ampfifo_monit1_amp_ch3_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_posfifo_monit1_wr_req_i : std_logic := '0';
signal regs_posfifo_monit1_wr_full_o : std_logic;
signal regs_posfifo_monit1_wr_empty_o : std_logic;
signal regs_posfifo_monit1_wr_usedw_o : std_logic_vector(3 downto 0);
signal regs_posfifo_monit1_pos_x_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_posfifo_monit1_pos_y_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_posfifo_monit1_pos_q_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_posfifo_monit1_pos_sum_i : std_logic_vector(31 downto 0) := (others => '0');
signal regs_sw_tag_en_o : std_logic;
signal regs_sw_tag_desync_cnt_rst_o : std_logic;
signal regs_sw_tag_desync_cnt_i : std_logic_vector(13 downto 0) := (others => '0');
signal regs_sw_data_mask_en_o : std_logic;
signal regs_sw_data_mask_samples_o : std_logic_vector(15 downto 0);
signal regs_tbt_tag_en_o : std_logic;
signal regs_tbt_tag_dly_o : std_logic_vector(15 downto 0);
signal regs_tbt_tag_desync_cnt_rst_o : std_logic;
signal regs_tbt_tag_desync_cnt_i : std_logic_vector(13 downto 0) := (others => '0');
signal regs_tbt_data_mask_ctl_en_o : std_logic;
signal regs_tbt_data_mask_samples_beg_o : std_logic_vector(15 downto 0);
signal regs_tbt_data_mask_samples_end_o : std_logic_vector(15 downto 0);
signal regs_monit1_tag_en_o : std_logic;
signal regs_monit1_tag_dly_o : std_logic_vector(15 downto 0);
signal regs_monit1_tag_desync_cnt_rst_o : std_logic;
signal regs_monit1_tag_desync_cnt_i : std_logic_vector(13 downto 0) := (others => '0');
signal regs_monit1_data_mask_ctl_en_o : std_logic;
signal regs_monit1_data_mask_samples_beg_o : std_logic_vector(15 downto 0);
signal regs_monit1_data_mask_samples_end_o : std_logic_vector(15 downto 0);
signal regs_monit_tag_en_o : std_logic;
signal regs_monit_tag_dly_o : std_logic_vector(15 downto 0);
signal regs_monit_tag_desync_cnt_rst_o : std_logic;
signal regs_monit_tag_desync_cnt_i : std_logic_vector(13 downto 0) := (others => '0');
signal regs_monit_data_mask_ctl_en_o : std_logic;
signal regs_monit_data_mask_samples_beg_o : std_logic_vector(15 downto 0);
signal regs_monit_data_mask_samples_end_o : std_logic_vector(15 downto 0);
signal regs_pos_calc_offset_x_o : std_logic_vector(31 downto 0);
signal regs_pos_calc_offset_y_o : std_logic_vector(31 downto 0);
-----------------------------
-- Wishbone crossbar signals
-----------------------------
-- Crossbar master/slave arrays
signal cbar_slave_in : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_out : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_in : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- Extra Wishbone registering stage
signal cbar_slave_in_reg0 : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_out_reg0 : t_wishbone_slave_out_array(c_masters-1 downto 0);
---------------------------------------------------------
-- Clock and Reset signals --
---------------------------------------------------------
signal fs_rst2x : std_logic;
signal fs_rst : std_logic;
---------------------------------------------------------
-- Counters signals --
---------------------------------------------------------
signal cnt_ce_array : std_logic_vector(c_num_counters-1 downto 0);
signal cnt_up_array : std_logic_vector(c_num_counters-1 downto 0);
signal cnt_array : t_cnt_array(c_num_counters-1 downto 0);
signal test_data : std_logic;
---------------------------------------------------------
-- ADC, MIX and data --
---------------------------------------------------------
signal adc_ch0_sp : std_logic_vector(g_input_width-1 downto 0);
signal adc_ch1_sp : std_logic_vector(g_input_width-1 downto 0);
signal adc_ch2_sp : std_logic_vector(g_input_width-1 downto 0);
signal adc_ch3_sp : std_logic_vector(g_input_width-1 downto 0);
signal adc_tag_sp : std_logic_vector(0 downto 0);
signal adc_valid_sp : std_logic;
signal dsp_cha : std_logic_vector(g_input_width-1 downto 0);
signal dsp_chb : std_logic_vector(g_input_width-1 downto 0);
signal dsp_chc : std_logic_vector(g_input_width-1 downto 0);
signal dsp_chd : std_logic_vector(g_input_width-1 downto 0);
signal dsp_ch_tag : std_logic_vector(0 downto 0);
signal dsp_ch_tag_en : std_logic := '0';
signal dsp_ch_valid : std_logic;
-- High pass filtering
signal adc_ch0_hpf : std_logic_vector(g_input_width-1 downto 0);
signal adc_ch1_hpf : std_logic_vector(g_input_width-1 downto 0);
signal adc_ch2_hpf : std_logic_vector(g_input_width-1 downto 0);
signal adc_ch3_hpf : std_logic_vector(g_input_width-1 downto 0);
-- BPM Swap signals
signal sw_mode1 : std_logic_vector(1 downto 0);
signal sw_mode2 : std_logic_vector(1 downto 0);
signal clk_swap_en : std_logic;
signal mix_ch0_i : std_logic_vector(g_IQ_width-1 downto 0);
signal mix_ch0_q : std_logic_vector(g_IQ_width-1 downto 0);
signal mix_ch1_i : std_logic_vector(g_IQ_width-1 downto 0);
signal mix_ch1_q : std_logic_vector(g_IQ_width-1 downto 0);
signal mix_ch2_i : std_logic_vector(g_IQ_width-1 downto 0);
signal mix_ch2_q : std_logic_vector(g_IQ_width-1 downto 0);
signal mix_ch3_i : std_logic_vector(g_IQ_width-1 downto 0);
signal mix_ch3_q : std_logic_vector(g_IQ_width-1 downto 0);
signal mix_valid : std_logic;
signal mix_ce : std_logic;
---------------------------------------------------------
-- TBT data --
---------------------------------------------------------
signal tbt_decim_tag_en : std_logic := '0';
signal tbt_decim_tag_dly_c : std_logic_vector(c_tbt_decim_tag_dly_width-1 downto 0) := (others => '0');
signal tbt_decim_tag_logic : std_logic;
signal tbt_decim_tag : std_logic_vector(0 downto 0);
signal tbt_decim_mask_en : std_logic := '0';
signal tbt_decim_mask_num_samples_beg : unsigned(c_tbt_cic_mask_samples_width-1 downto 0) := (others => '0');
signal tbt_decim_mask_num_samples_end : unsigned(c_tbt_cic_mask_samples_width-1 downto 0) := (others => '0');
signal tbt_decim_ch0_i : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_decim_ch0_q : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_decim_ch1_i : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_decim_ch1_q : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_decim_ch2_i : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_decim_ch2_q : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_decim_ch3_i : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_decim_ch3_q : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_decim_valid : std_logic;
signal tbt_decim_ce : std_logic;
signal tbt_amp_ch0 : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_amp_ch1 : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_amp_ch2 : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_amp_ch3 : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_amp_valid : std_logic;
signal tbt_amp_ce : std_logic;
signal tbt_pha_ch0 : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_pha_ch1 : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_pha_ch2 : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_pha_ch3 : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_pha_valid : std_logic;
signal tbt_pha_ce : std_logic;
---------------------------------------------------------
-- FOFB data --
---------------------------------------------------------
signal fofb_decim_mask_en : std_logic := '0';
signal fofb_decim_mask_num_samples : unsigned(c_fofb_cic_mask_samples_width-1 downto 0) := (others => '0');
signal fofb_decim_ch0_i : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_decim_ch0_q : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_decim_ch1_i : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_decim_ch1_q : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_decim_ch2_i : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_decim_ch2_q : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_decim_ch3_i : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_decim_ch3_q : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_decim_valid : std_logic;
signal fofb_decim_ce : std_logic;
signal fofb_amp_ch0 : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_amp_ch1 : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_amp_ch2 : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_amp_ch3 : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_amp_valid : std_logic;
signal fofb_amp_ce : std_logic;
signal fofb_pha_ch0 : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_pha_ch1 : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_pha_ch2 : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_pha_ch3 : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_pha_valid : std_logic;
signal fofb_pha_ce : std_logic;
---------------------------------------------------------
-- Monitoring data --
---------------------------------------------------------
signal monit1_decim_tag_en : std_logic := '0';
signal monit1_decim_tag_dly_c : std_logic_vector(c_monit1_decim_tag_dly_width-1 downto 0) := (others => '0');
signal monit1_decim_tag_logic : std_logic;
signal monit1_decim_tag : std_logic_vector(0 downto 0);
signal monit1_decim_mask_en : std_logic := '0';
signal monit1_decim_mask_num_samples_beg : unsigned(c_monit1_cic_mask_samples_width-1 downto 0) := (others => '0');
signal monit1_decim_mask_num_samples_end : unsigned(c_monit1_cic_mask_samples_width-1 downto 0) := (others => '0');
signal monit1_amp_ch0 : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_ch1 : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_ch2 : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_ch3 : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_valid : std_logic;
signal monit1_amp_ce : std_logic;
signal monit1_amp_ch0_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_ch1_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_ch2_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_ch3_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_valid_wb_sync : std_logic;
signal monit_decim_tag_en : std_logic := '0';
signal monit_decim_tag_dly_c : std_logic_vector(c_monit2_decim_tag_dly_width-1 downto 0) := (others => '0');
signal monit_decim_tag_logic : std_logic;
signal monit_decim_tag : std_logic_vector(0 downto 0);
signal monit_decim_mask_en : std_logic := '0';
signal monit_decim_mask_num_samples_beg : unsigned(c_monit2_cic_mask_samples_width-1 downto 0) := (others => '0');
signal monit_decim_mask_num_samples_end : unsigned(c_monit2_cic_mask_samples_width-1 downto 0) := (others => '0');
signal monit_amp_ch0 : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_ch1 : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_ch2 : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_ch3 : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_valid : std_logic;
signal monit_amp_ce : std_logic;
signal monit_amp_ch0_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_ch1_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_ch2_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_ch3_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_valid_wb_sync : std_logic;
---------------------------------------------------------
-- Position data --
---------------------------------------------------------
signal tbt_pos_x : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_pos_y : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_pos_q : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_pos_sum : std_logic_vector(g_tbt_decim_width-1 downto 0);
signal tbt_pos_valid : std_logic;
signal tbt_pos_ce : std_logic;
signal fofb_pos_x : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_pos_y : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_pos_q : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_pos_sum : std_logic_vector(g_fofb_decim_width-1 downto 0);
signal fofb_pos_valid : std_logic;
signal fofb_pos_ce : std_logic;
signal monit1_pos_x : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_y : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_q : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_sum : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_valid : std_logic;
signal monit1_pos_ce : std_logic;
signal monit1_pos_x_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_y_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_q_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_sum_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_valid_wb_sync : std_logic;
signal dsp_monit1_updt : std_logic;
signal monit_pos_x : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_y : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_q : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_sum : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_valid : std_logic;
signal monit_pos_ce : std_logic;
signal monit_pos_x_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_y_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_q_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_sum_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_valid_wb_sync : std_logic;
signal dsp_monit_updt : std_logic;
---------------------------------------------------------
-- FIFO CDC signals
---------------------------------------------------------
signal fifo_mix_out : std_logic_vector(c_cdc_mix_iq_width-1 downto 0);
signal fifo_mix_valid_out : std_logic;
signal fifo_tbt_decim_out : std_logic_vector(c_cdc_tbt_iq_width-1 downto 0);
signal fifo_tbt_decim_valid_out : std_logic;
signal fifo_tbt_amp_out : std_logic_vector(c_cdc_tbt_width-1 downto 0);
signal fifo_tbt_amp_valid_out : std_logic;
signal fifo_tbt_pha_out : std_logic_vector(c_cdc_tbt_width-1 downto 0);
signal fifo_tbt_pha_valid_out : std_logic;
signal fifo_tbt_pos_out : std_logic_vector(c_cdc_tbt_width-1 downto 0);
signal fifo_tbt_pos_valid_out : std_logic;
signal fifo_fofb_decim_out : std_logic_vector(c_cdc_fofb_iq_width-1 downto 0);
signal fifo_fofb_decim_valid_out : std_logic;
signal fifo_fofb_amp_out : std_logic_vector(c_cdc_fofb_width-1 downto 0);
signal fifo_fofb_amp_valid_out : std_logic;
signal fifo_fofb_pha_out : std_logic_vector(c_cdc_fofb_width-1 downto 0);
signal fifo_fofb_pha_valid_out : std_logic;
signal fifo_fofb_pos_out : std_logic_vector(c_cdc_fofb_width-1 downto 0);
signal fifo_fofb_pos_valid_out : std_logic;
signal fifo_monit1_amp_out : std_logic_vector(c_cdc_monit_width-1 downto 0);
signal fifo_monit1_amp_valid_out : std_logic;
signal fifo_monit1_amp_out_wb_sync : std_logic_vector(c_cdc_monit_width-1 downto 0);
signal fifo_monit1_amp_valid_out_wb_sync : std_logic;
signal fifo_monit1_pos_out : std_logic_vector(c_cdc_monit_width-1 downto 0);
signal fifo_monit1_pos_valid_out : std_logic;
signal fifo_monit1_pos_out_wb_sync : std_logic_vector(c_cdc_monit_width-1 downto 0);
signal fifo_monit1_pos_valid_out_wb_sync : std_logic;
signal monit1_amp_ch3_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_ch2_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_ch1_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_ch0_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_amp_valid_out_wb_sync : std_logic;
signal monit1_pos_sum_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_q_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_y_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_x_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit1_pos_valid_out_wb_sync : std_logic;
signal fifo_monit_amp_out : std_logic_vector(c_cdc_monit_width-1 downto 0);
signal fifo_monit_amp_valid_out : std_logic;
signal fifo_monit_amp_out_wb_sync : std_logic_vector(c_cdc_monit_width-1 downto 0);
signal fifo_monit_amp_valid_out_wb_sync : std_logic;
signal fifo_monit_pos_out : std_logic_vector(c_cdc_monit_width-1 downto 0);
signal fifo_monit_pos_valid_out : std_logic;
signal fifo_monit_pos_out_wb_sync : std_logic_vector(c_cdc_monit_width-1 downto 0);
signal fifo_monit_pos_valid_out_wb_sync : std_logic;
signal monit_amp_ch3_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_ch2_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_ch1_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_ch0_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_amp_valid_out_wb_sync : std_logic;
signal monit_pos_sum_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_q_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_y_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_x_out_wb_sync : std_logic_vector(g_monit_decim_width-1 downto 0);
signal monit_pos_valid_out_wb_sync : std_logic;
---------------------------------------------------------
-- Components instantiation
---------------------------------------------------------
component wb_pos_calc_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk2x_i : in std_logic;
pos_calc_ds_tbt_thres_val_o : out std_logic_vector(25 downto 0);
pos_calc_ds_tbt_thres_reserved_i : in std_logic_vector(5 downto 0);
pos_calc_ds_fofb_thres_val_o : out std_logic_vector(25 downto 0);
pos_calc_ds_fofb_thres_reserved_i : in std_logic_vector(5 downto 0);
pos_calc_ds_monit_thres_val_o : out std_logic_vector(25 downto 0);
pos_calc_ds_monit_thres_reserved_i : in std_logic_vector(5 downto 0);
pos_calc_kx_val_o : out std_logic_vector(24 downto 0);
pos_calc_kx_reserved_i : in std_logic_vector(6 downto 0);
pos_calc_ky_val_o : out std_logic_vector(24 downto 0);
pos_calc_ky_reserved_i : in std_logic_vector(6 downto 0);
pos_calc_ksum_val_o : out std_logic_vector(24 downto 0);
pos_calc_ksum_reserved_i : in std_logic_vector(6 downto 0);
pos_calc_dsp_ctnr_tbt_ch01_i : in std_logic_vector(15 downto 0);
pos_calc_dsp_ctnr_tbt_ch23_i : in std_logic_vector(15 downto 0);
pos_calc_dsp_ctnr_fofb_ch01_i : in std_logic_vector(15 downto 0);
pos_calc_dsp_ctnr_fofb_ch23_i : in std_logic_vector(15 downto 0);
pos_calc_dsp_ctnr1_monit_cic_i : in std_logic_vector(15 downto 0);
pos_calc_dsp_ctnr1_monit_cfir_i : in std_logic_vector(15 downto 0);
pos_calc_dsp_ctnr2_monit_pfir_i : in std_logic_vector(15 downto 0);
pos_calc_dsp_ctnr2_monit_fir_01_i : in std_logic_vector(15 downto 0);
pos_calc_dsp_err_clr_tbt_o : out std_logic;
pos_calc_dsp_err_clr_fofb_o : out std_logic;
pos_calc_dsp_err_clr_monit_part1_o : out std_logic;
pos_calc_dsp_err_clr_monit_part2_o : out std_logic;
pos_calc_dds_cfg_valid_ch0_o : out std_logic;
pos_calc_dds_cfg_test_data_o : out std_logic;
pos_calc_dds_cfg_reserved_ch0_i : in std_logic_vector(5 downto 0);
pos_calc_dds_cfg_valid_ch1_o : out std_logic;
pos_calc_dds_cfg_reserved_ch1_i : in std_logic_vector(6 downto 0);
pos_calc_dds_cfg_valid_ch2_o : out std_logic;
pos_calc_dds_cfg_reserved_ch2_i : in std_logic_vector(6 downto 0);
pos_calc_dds_cfg_valid_ch3_o : out std_logic;
pos_calc_dds_cfg_reserved_ch3_i : in std_logic_vector(6 downto 0);
pos_calc_dds_pinc_ch0_val_o : out std_logic_vector(29 downto 0);
pos_calc_dds_pinc_ch0_reserved_i : in std_logic_vector(1 downto 0);
pos_calc_dds_pinc_ch1_val_o : out std_logic_vector(29 downto 0);
pos_calc_dds_pinc_ch1_reserved_i : in std_logic_vector(1 downto 0);
pos_calc_dds_pinc_ch2_val_o : out std_logic_vector(29 downto 0);
pos_calc_dds_pinc_ch2_reserved_i : in std_logic_vector(1 downto 0);
pos_calc_dds_pinc_ch3_val_o : out std_logic_vector(29 downto 0);
pos_calc_dds_pinc_ch3_reserved_i : in std_logic_vector(1 downto 0);
pos_calc_dds_poff_ch0_val_o : out std_logic_vector(29 downto 0);
pos_calc_dds_poff_ch0_reserved_i : in std_logic_vector(1 downto 0);
pos_calc_dds_poff_ch1_val_o : out std_logic_vector(29 downto 0);
pos_calc_dds_poff_ch1_reserved_i : in std_logic_vector(1 downto 0);
pos_calc_dds_poff_ch2_val_o : out std_logic_vector(29 downto 0);
pos_calc_dds_poff_ch2_reserved_i : in std_logic_vector(1 downto 0);
pos_calc_dds_poff_ch3_val_o : out std_logic_vector(29 downto 0);
pos_calc_dds_poff_ch3_reserved_i : in std_logic_vector(1 downto 0);
pos_calc_dsp_monit_amp_ch0_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit_amp_ch1_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit_amp_ch2_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit_amp_ch3_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit_pos_x_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit_pos_y_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit_pos_q_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit_pos_sum_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit_updt_o : out std_logic_vector(31 downto 0);
pos_calc_dsp_monit_updt_wr_o : out std_logic;
pos_calc_dsp_monit1_amp_ch0_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit1_amp_ch1_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit1_amp_ch2_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit1_amp_ch3_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit1_pos_x_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit1_pos_y_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit1_pos_q_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit1_pos_sum_i : in std_logic_vector(31 downto 0);
pos_calc_dsp_monit1_updt_o : out std_logic_vector(31 downto 0);
pos_calc_dsp_monit1_updt_wr_o : out std_logic;
pos_calc_ampfifo_monit_wr_req_i : in std_logic;
pos_calc_ampfifo_monit_wr_full_o : out std_logic;
pos_calc_ampfifo_monit_wr_empty_o : out std_logic;
pos_calc_ampfifo_monit_wr_usedw_o : out std_logic_vector(3 downto 0);
pos_calc_ampfifo_monit_amp_ch0_i : in std_logic_vector(31 downto 0);
pos_calc_ampfifo_monit_amp_ch1_i : in std_logic_vector(31 downto 0);
pos_calc_ampfifo_monit_amp_ch2_i : in std_logic_vector(31 downto 0);
pos_calc_ampfifo_monit_amp_ch3_i : in std_logic_vector(31 downto 0);
pos_calc_posfifo_monit_wr_req_i : in std_logic;
pos_calc_posfifo_monit_wr_full_o : out std_logic;
pos_calc_posfifo_monit_wr_empty_o : out std_logic;
pos_calc_posfifo_monit_wr_usedw_o : out std_logic_vector(3 downto 0);
pos_calc_posfifo_monit_pos_x_i : in std_logic_vector(31 downto 0);
pos_calc_posfifo_monit_pos_y_i : in std_logic_vector(31 downto 0);
pos_calc_posfifo_monit_pos_q_i : in std_logic_vector(31 downto 0);
pos_calc_posfifo_monit_pos_sum_i : in std_logic_vector(31 downto 0);
pos_calc_ampfifo_monit1_wr_req_i : in std_logic;
pos_calc_ampfifo_monit1_wr_full_o : out std_logic;
pos_calc_ampfifo_monit1_wr_empty_o : out std_logic;
pos_calc_ampfifo_monit1_wr_usedw_o : out std_logic_vector(3 downto 0);
pos_calc_ampfifo_monit1_amp_ch0_i : in std_logic_vector(31 downto 0);
pos_calc_ampfifo_monit1_amp_ch1_i : in std_logic_vector(31 downto 0);
pos_calc_ampfifo_monit1_amp_ch2_i : in std_logic_vector(31 downto 0);
pos_calc_ampfifo_monit1_amp_ch3_i : in std_logic_vector(31 downto 0);
pos_calc_posfifo_monit1_wr_req_i : in std_logic;
pos_calc_posfifo_monit1_wr_full_o : out std_logic;
pos_calc_posfifo_monit1_wr_empty_o : out std_logic;
pos_calc_posfifo_monit1_wr_usedw_o : out std_logic_vector(3 downto 0);
pos_calc_posfifo_monit1_pos_x_i : in std_logic_vector(31 downto 0);
pos_calc_posfifo_monit1_pos_y_i : in std_logic_vector(31 downto 0);
pos_calc_posfifo_monit1_pos_q_i : in std_logic_vector(31 downto 0);
pos_calc_posfifo_monit1_pos_sum_i : in std_logic_vector(31 downto 0);
pos_calc_sw_tag_en_o : out std_logic;
pos_calc_sw_tag_desync_cnt_rst_o : out std_logic;
pos_calc_sw_tag_desync_cnt_i : in std_logic_vector(13 downto 0);
pos_calc_sw_data_mask_en_o : out std_logic;
pos_calc_sw_data_mask_samples_o : out std_logic_vector(15 downto 0);
pos_calc_tbt_tag_en_o : out std_logic;
pos_calc_tbt_tag_dly_o : out std_logic_vector(15 downto 0);
pos_calc_tbt_tag_desync_cnt_rst_o : out std_logic;
pos_calc_tbt_tag_desync_cnt_i : in std_logic_vector(13 downto 0);
pos_calc_tbt_data_mask_ctl_en_o : out std_logic;
pos_calc_tbt_data_mask_samples_beg_o : out std_logic_vector(15 downto 0);
pos_calc_tbt_data_mask_samples_end_o : out std_logic_vector(15 downto 0);
pos_calc_monit1_tag_en_o : out std_logic;
pos_calc_monit1_tag_dly_o : out std_logic_vector(15 downto 0);
pos_calc_monit1_tag_desync_cnt_rst_o : out std_logic;
pos_calc_monit1_tag_desync_cnt_i : in std_logic_vector(13 downto 0);
pos_calc_monit1_data_mask_ctl_en_o : out std_logic;
pos_calc_monit1_data_mask_samples_beg_o : out std_logic_vector(15 downto 0);
pos_calc_monit1_data_mask_samples_end_o : out std_logic_vector(15 downto 0);
pos_calc_monit_tag_en_o : out std_logic;
pos_calc_monit_tag_dly_o : out std_logic_vector(15 downto 0);
pos_calc_monit_tag_desync_cnt_rst_o : out std_logic;
pos_calc_monit_tag_desync_cnt_i : in std_logic_vector(13 downto 0);
pos_calc_monit_data_mask_ctl_en_o : out std_logic;
pos_calc_monit_data_mask_samples_beg_o : out std_logic_vector(15 downto 0);
pos_calc_monit_data_mask_samples_end_o : out std_logic_vector(15 downto 0);
pos_calc_offset_x_o : out std_logic_vector(31 downto 0);
pos_calc_offset_y_o : out std_logic_vector(31 downto 0)
);
end component wb_pos_calc_regs;
begin
fs_rst2x <= not fs_rst2x_n_i;
fs_rst <= not fs_rst_n_i;
-----------------------------
-- Insert extra Wishbone registering stage for ease timing.
-- It effectively cuts the bandwidth in half!
-----------------------------
gen_with_extra_wb_reg : if g_with_extra_wb_reg generate
cmp_register_link : xwb_register_link -- puts a register of delay between crossbars
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
slave_i => cbar_slave_in_reg0(0),
slave_o => cbar_slave_out_reg0(0),
master_i => cbar_slave_out(0),
master_o => cbar_slave_in(0)
);
cbar_slave_in_reg0(0).adr <= wb_adr_i;
cbar_slave_in_reg0(0).dat <= wb_dat_i;
cbar_slave_in_reg0(0).sel <= wb_sel_i;
cbar_slave_in_reg0(0).we <= wb_we_i;
cbar_slave_in_reg0(0).cyc <= wb_cyc_i;
cbar_slave_in_reg0(0).stb <= wb_stb_i;
wb_dat_o <= cbar_slave_out_reg0(0).dat;
wb_ack_o <= cbar_slave_out_reg0(0).ack;
wb_stall_o <= cbar_slave_out_reg0(0).stall;
end generate;
gen_without_extra_wb_reg : if not g_with_extra_wb_reg generate
-- External master connection
cbar_slave_in(0).adr <= wb_adr_i;
cbar_slave_in(0).dat <= wb_dat_i;
cbar_slave_in(0).sel <= wb_sel_i;
cbar_slave_in(0).we <= wb_we_i;
cbar_slave_in(0).cyc <= wb_cyc_i;
cbar_slave_in(0).stb <= wb_stb_i;
wb_dat_o <= cbar_slave_out(0).dat;
wb_ack_o <= cbar_slave_out(0).ack;
wb_stall_o <= cbar_slave_out(0).stall;
end generate;
-----------------------------
-- WB Position Calc Core Address decoder
-----------------------------
-- We need 2 outputs, as in the same wishbone addressing range, 2
-- other wishbone peripherals must be driven:
--
-- 0 -> WB Position Calc Core Register Wishbone Interface
-- 1 -> WB Uncross module.
-- The Internal Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_in,
slave_o => cbar_slave_out,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_in,
master_o => cbar_master_out
);
-----------------------------
-- Slave adapter for Wishbone Register Interface
-----------------------------
cmp_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity
)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
master_i => wb_slv_adp_in,
master_o => wb_slv_adp_out,
sl_adr_i => resized_addr,
sl_dat_i => cbar_master_out(0).dat,
sl_sel_i => cbar_master_out(0).sel,
sl_cyc_i => cbar_master_out(0).cyc,
sl_stb_i => cbar_master_out(0).stb,
sl_we_i => cbar_master_out(0).we,
sl_dat_o => cbar_master_in(0).dat,
sl_ack_o => cbar_master_in(0).ack,
sl_rty_o => cbar_master_in(0).rty,
sl_err_o => cbar_master_in(0).err,
sl_stall_o => cbar_master_in(0).stall
);
resized_addr(c_periph_addr_size-1 downto 0)
<= cbar_master_out(0).adr(c_periph_addr_size-1 downto 0);
resized_addr(c_wishbone_address_width-1 downto c_periph_addr_size)
<= (others => '0');
-----------------------------
-- Position Calc Core Register Wishbone Interface. Word addressed!
-----------------------------
--Position Calc Core register interface is the slave number 0, word addressed
cmp_wb_pos_calc_regs : wb_pos_calc_regs
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_slv_adp_out.adr(6 downto 0),
wb_dat_i => wb_slv_adp_out.dat,
wb_dat_o => wb_slv_adp_in.dat,
wb_cyc_i => wb_slv_adp_out.cyc,
wb_sel_i => wb_slv_adp_out.sel,
wb_stb_i => wb_slv_adp_out.stb,
wb_we_i => wb_slv_adp_out.we,
wb_ack_o => wb_slv_adp_in.ack,
wb_stall_o => wb_slv_adp_in.stall,
fs_clk2x_i => fs_clk_i,
pos_calc_ds_tbt_thres_val_o => regs_ds_tbt_thres_val_o,
pos_calc_ds_tbt_thres_reserved_i => regs_ds_tbt_thres_reserved_i,
pos_calc_ds_fofb_thres_val_o => regs_ds_fofb_thres_val_o,
pos_calc_ds_fofb_thres_reserved_i => regs_ds_fofb_thres_reserved_i,
pos_calc_ds_monit_thres_val_o => regs_ds_monit_thres_val_o,
pos_calc_ds_monit_thres_reserved_i => regs_ds_monit_thres_reserved_i,
pos_calc_kx_val_o => regs_kx_val_o,
pos_calc_kx_reserved_i => regs_kx_reserved_i,
pos_calc_ky_val_o => regs_ky_val_o,
pos_calc_ky_reserved_i => regs_ky_reserved_i,
pos_calc_ksum_val_o => regs_ksum_val_o,
pos_calc_ksum_reserved_i => regs_ksum_reserved_i,
pos_calc_dsp_ctnr_tbt_ch01_i => regs_dsp_ctnr_tbt_ch01_i,
pos_calc_dsp_ctnr_tbt_ch23_i => regs_dsp_ctnr_tbt_ch23_i,
pos_calc_dsp_ctnr_fofb_ch01_i => regs_dsp_ctnr_fofb_ch01_i,
pos_calc_dsp_ctnr_fofb_ch23_i => regs_dsp_ctnr_fofb_ch23_i,
pos_calc_dsp_ctnr1_monit_cic_i => regs_dsp_ctnr1_monit_cic_i,
pos_calc_dsp_ctnr1_monit_cfir_i => regs_dsp_ctnr1_monit_cfir_i,
pos_calc_dsp_ctnr2_monit_pfir_i => regs_dsp_ctnr2_monit_pfir_i,
pos_calc_dsp_ctnr2_monit_fir_01_i => regs_dsp_ctnr2_monit_fir_01_i,
pos_calc_dsp_err_clr_tbt_o => regs_dsp_err_clr_tbt_o,
pos_calc_dsp_err_clr_fofb_o => regs_dsp_err_clr_fofb_o,
pos_calc_dsp_err_clr_monit_part1_o => regs_dsp_err_clr_monit_part1_o,
pos_calc_dsp_err_clr_monit_part2_o => regs_dsp_err_clr_monit_part2_o,
pos_calc_dds_cfg_valid_ch0_o => regs_dds_cfg_valid_ch0_o,
pos_calc_dds_cfg_test_data_o => regs_dds_cfg_test_data_o,
pos_calc_dds_cfg_reserved_ch0_i => regs_dds_cfg_reserved_ch0_i,
pos_calc_dds_cfg_valid_ch1_o => regs_dds_cfg_valid_ch1_o,
pos_calc_dds_cfg_reserved_ch1_i => regs_dds_cfg_reserved_ch1_i,
pos_calc_dds_cfg_valid_ch2_o => regs_dds_cfg_valid_ch2_o,
pos_calc_dds_cfg_reserved_ch2_i => regs_dds_cfg_reserved_ch2_i,
pos_calc_dds_cfg_valid_ch3_o => regs_dds_cfg_valid_ch3_o,
pos_calc_dds_cfg_reserved_ch3_i => regs_dds_cfg_reserved_ch3_i,
pos_calc_dds_pinc_ch0_val_o => regs_dds_pinc_ch0_val_o,
pos_calc_dds_pinc_ch0_reserved_i => regs_dds_pinc_ch0_reserved_i,
pos_calc_dds_pinc_ch1_val_o => regs_dds_pinc_ch1_val_o,
pos_calc_dds_pinc_ch1_reserved_i => regs_dds_pinc_ch1_reserved_i,
pos_calc_dds_pinc_ch2_val_o => regs_dds_pinc_ch2_val_o,
pos_calc_dds_pinc_ch2_reserved_i => regs_dds_pinc_ch2_reserved_i,
pos_calc_dds_pinc_ch3_val_o => regs_dds_pinc_ch3_val_o,
pos_calc_dds_pinc_ch3_reserved_i => regs_dds_pinc_ch3_reserved_i,
pos_calc_dds_poff_ch0_val_o => regs_dds_poff_ch0_val_o,
pos_calc_dds_poff_ch0_reserved_i => regs_dds_poff_ch0_reserved_i,
pos_calc_dds_poff_ch1_val_o => regs_dds_poff_ch1_val_o,
pos_calc_dds_poff_ch1_reserved_i => regs_dds_poff_ch1_reserved_i,
pos_calc_dds_poff_ch2_val_o => regs_dds_poff_ch2_val_o,
pos_calc_dds_poff_ch2_reserved_i => regs_dds_poff_ch2_reserved_i,
pos_calc_dds_poff_ch3_val_o => regs_dds_poff_ch3_val_o,
pos_calc_dds_poff_ch3_reserved_i => regs_dds_poff_ch3_reserved_i,
pos_calc_dsp_monit_amp_ch0_i => regs_dsp_monit_amp_ch0_i,
pos_calc_dsp_monit_amp_ch1_i => regs_dsp_monit_amp_ch1_i,
pos_calc_dsp_monit_amp_ch2_i => regs_dsp_monit_amp_ch2_i,
pos_calc_dsp_monit_amp_ch3_i => regs_dsp_monit_amp_ch3_i,
pos_calc_dsp_monit_pos_x_i => regs_dsp_monit_pos_x_i,
pos_calc_dsp_monit_pos_y_i => regs_dsp_monit_pos_y_i,
pos_calc_dsp_monit_pos_q_i => regs_dsp_monit_pos_q_i,
pos_calc_dsp_monit_pos_sum_i => regs_dsp_monit_pos_sum_i,
pos_calc_dsp_monit_updt_o => regs_dsp_monit_updt_o,
pos_calc_dsp_monit_updt_wr_o => regs_dsp_monit_updt_wr_o,
pos_calc_dsp_monit1_amp_ch0_i => regs_dsp_monit1_amp_ch0_i,
pos_calc_dsp_monit1_amp_ch1_i => regs_dsp_monit1_amp_ch1_i,
pos_calc_dsp_monit1_amp_ch2_i => regs_dsp_monit1_amp_ch2_i,
pos_calc_dsp_monit1_amp_ch3_i => regs_dsp_monit1_amp_ch3_i,
pos_calc_dsp_monit1_pos_x_i => regs_dsp_monit1_pos_x_i,
pos_calc_dsp_monit1_pos_y_i => regs_dsp_monit1_pos_y_i,
pos_calc_dsp_monit1_pos_q_i => regs_dsp_monit1_pos_q_i,
pos_calc_dsp_monit1_pos_sum_i => regs_dsp_monit1_pos_sum_i,
pos_calc_dsp_monit1_updt_o => regs_dsp_monit1_updt_o,
pos_calc_dsp_monit1_updt_wr_o => regs_dsp_monit1_updt_wr_o,
pos_calc_ampfifo_monit_wr_req_i => regs_ampfifo_monit_wr_req_i,
pos_calc_ampfifo_monit_wr_full_o => regs_ampfifo_monit_wr_full_o,
pos_calc_ampfifo_monit_wr_empty_o => regs_ampfifo_monit_wr_empty_o,
pos_calc_ampfifo_monit_wr_usedw_o => regs_ampfifo_monit_wr_usedw_o,
pos_calc_ampfifo_monit_amp_ch0_i => regs_ampfifo_monit_amp_ch0_i,
pos_calc_ampfifo_monit_amp_ch1_i => regs_ampfifo_monit_amp_ch1_i,
pos_calc_ampfifo_monit_amp_ch2_i => regs_ampfifo_monit_amp_ch2_i,
pos_calc_ampfifo_monit_amp_ch3_i => regs_ampfifo_monit_amp_ch3_i,
pos_calc_posfifo_monit_wr_req_i => regs_posfifo_monit_wr_req_i,
pos_calc_posfifo_monit_wr_full_o => regs_posfifo_monit_wr_full_o,
pos_calc_posfifo_monit_wr_empty_o => regs_posfifo_monit_wr_empty_o,
pos_calc_posfifo_monit_wr_usedw_o => regs_posfifo_monit_wr_usedw_o,
pos_calc_posfifo_monit_pos_x_i => regs_posfifo_monit_pos_x_i,
pos_calc_posfifo_monit_pos_y_i => regs_posfifo_monit_pos_y_i,
pos_calc_posfifo_monit_pos_q_i => regs_posfifo_monit_pos_q_i,
pos_calc_posfifo_monit_pos_sum_i => regs_posfifo_monit_pos_sum_i,
pos_calc_ampfifo_monit1_wr_req_i => regs_ampfifo_monit1_wr_req_i,
pos_calc_ampfifo_monit1_wr_full_o => regs_ampfifo_monit1_wr_full_o,
pos_calc_ampfifo_monit1_wr_empty_o => regs_ampfifo_monit1_wr_empty_o,
pos_calc_ampfifo_monit1_wr_usedw_o => regs_ampfifo_monit1_wr_usedw_o,
pos_calc_ampfifo_monit1_amp_ch0_i => regs_ampfifo_monit1_amp_ch0_i,
pos_calc_ampfifo_monit1_amp_ch1_i => regs_ampfifo_monit1_amp_ch1_i,
pos_calc_ampfifo_monit1_amp_ch2_i => regs_ampfifo_monit1_amp_ch2_i,
pos_calc_ampfifo_monit1_amp_ch3_i => regs_ampfifo_monit1_amp_ch3_i,
pos_calc_posfifo_monit1_wr_req_i => regs_posfifo_monit1_wr_req_i,
pos_calc_posfifo_monit1_wr_full_o => regs_posfifo_monit1_wr_full_o,
pos_calc_posfifo_monit1_wr_empty_o => regs_posfifo_monit1_wr_empty_o,
pos_calc_posfifo_monit1_wr_usedw_o => regs_posfifo_monit1_wr_usedw_o,
pos_calc_posfifo_monit1_pos_x_i => regs_posfifo_monit1_pos_x_i,
pos_calc_posfifo_monit1_pos_y_i => regs_posfifo_monit1_pos_y_i,
pos_calc_posfifo_monit1_pos_q_i => regs_posfifo_monit1_pos_q_i,
pos_calc_posfifo_monit1_pos_sum_i => regs_posfifo_monit1_pos_sum_i,
pos_calc_sw_tag_en_o => regs_sw_tag_en_o,
pos_calc_sw_tag_desync_cnt_rst_o => regs_sw_tag_desync_cnt_rst_o,
pos_calc_sw_tag_desync_cnt_i => regs_sw_tag_desync_cnt_i,
pos_calc_sw_data_mask_en_o => regs_sw_data_mask_en_o,
pos_calc_sw_data_mask_samples_o => regs_sw_data_mask_samples_o,
pos_calc_tbt_tag_en_o => regs_tbt_tag_en_o,
pos_calc_tbt_tag_dly_o => regs_tbt_tag_dly_o,
pos_calc_tbt_tag_desync_cnt_rst_o => regs_tbt_tag_desync_cnt_rst_o,
pos_calc_tbt_tag_desync_cnt_i => regs_tbt_tag_desync_cnt_i,
pos_calc_tbt_data_mask_ctl_en_o => regs_tbt_data_mask_ctl_en_o,
pos_calc_tbt_data_mask_samples_beg_o => regs_tbt_data_mask_samples_beg_o,
pos_calc_tbt_data_mask_samples_end_o => regs_tbt_data_mask_samples_end_o,
pos_calc_monit1_tag_en_o => regs_monit1_tag_en_o,
pos_calc_monit1_tag_dly_o => regs_monit1_tag_dly_o,
pos_calc_monit1_tag_desync_cnt_rst_o => regs_monit1_tag_desync_cnt_rst_o,
pos_calc_monit1_tag_desync_cnt_i => regs_monit1_tag_desync_cnt_i,
pos_calc_monit1_data_mask_ctl_en_o => regs_monit1_data_mask_ctl_en_o,
pos_calc_monit1_data_mask_samples_beg_o => regs_monit1_data_mask_samples_beg_o,
pos_calc_monit1_data_mask_samples_end_o => regs_monit1_data_mask_samples_end_o,
pos_calc_monit_tag_en_o => regs_monit_tag_en_o,
pos_calc_monit_tag_dly_o => regs_monit_tag_dly_o,
pos_calc_monit_tag_desync_cnt_rst_o => regs_monit_tag_desync_cnt_rst_o,
pos_calc_monit_tag_desync_cnt_i => regs_monit_tag_desync_cnt_i,
pos_calc_monit_data_mask_ctl_en_o => regs_monit_data_mask_ctl_en_o,
pos_calc_monit_data_mask_samples_beg_o => regs_monit_data_mask_samples_beg_o,
pos_calc_monit_data_mask_samples_end_o => regs_monit_data_mask_samples_end_o,
pos_calc_offset_x_o => regs_pos_calc_offset_x_o,
pos_calc_offset_y_o => regs_pos_calc_offset_y_o
);
-- Unused wishbone signals
wb_slv_adp_in.err <= '0';
wb_slv_adp_in.rty <= '0';
-- Registers fixed assignments
regs_ds_tbt_thres_reserved_i <= (others => '0');
regs_ds_fofb_thres_reserved_i <= (others => '0');
regs_ds_monit_thres_reserved_i <= (others => '0');
regs_kx_reserved_i <= (others => '0');
regs_ky_reserved_i <= (others => '0');
regs_ksum_reserved_i <= (others => '0');
regs_dds_cfg_reserved_ch0_i <= (others => '0');
regs_dds_cfg_reserved_ch1_i <= (others => '0');
regs_dds_cfg_reserved_ch2_i <= (others => '0');
regs_dds_cfg_reserved_ch3_i <= (others => '0');
regs_dds_pinc_ch0_reserved_i <= (others => '0');
regs_dds_pinc_ch1_reserved_i <= (others => '0');
regs_dds_pinc_ch2_reserved_i <= (others => '0');
regs_dds_pinc_ch3_reserved_i <= (others => '0');
regs_dds_poff_ch0_reserved_i <= (others => '0');
regs_dds_poff_ch1_reserved_i <= (others => '0');
regs_dds_poff_ch2_reserved_i <= (others => '0');
regs_dds_poff_ch3_reserved_i <= (others => '0');
--------------------------------------------------------------------------------
-- This is the old interface for acquiring data from Monit. It goes like this:
-- 1) Bus must write any value to "updt" register. This will update the output
-- register to be ready
-- 2) Read dsp_monit_* registers
--------------------------------------------------------------------------------
------------------------------------
-- Monit 1
------------------------------------
-- Sync with clk_i
regs_dsp_monit1_amp_ch0_i <=
std_logic_vector(resize(signed(monit1_amp_ch0_wb_sync), regs_dsp_monit1_amp_ch0_i'length));
regs_dsp_monit1_amp_ch1_i <=
std_logic_vector(resize(signed(monit1_amp_ch1_wb_sync), regs_dsp_monit1_amp_ch1_i'length));
regs_dsp_monit1_amp_ch2_i <=
std_logic_vector(resize(signed(monit1_amp_ch2_wb_sync), regs_dsp_monit1_amp_ch2_i'length));
regs_dsp_monit1_amp_ch3_i <=
std_logic_vector(resize(signed(monit1_amp_ch3_wb_sync), regs_dsp_monit1_amp_ch3_i'length));
-- Sync with clk_i
regs_dsp_monit1_pos_x_i <=
std_logic_vector(resize(signed(monit1_pos_x_wb_sync), regs_dsp_monit1_pos_x_i'length));
regs_dsp_monit1_pos_y_i <=
std_logic_vector(resize(signed(monit1_pos_y_wb_sync), regs_dsp_monit1_pos_y_i'length));
regs_dsp_monit1_pos_q_i <=
std_logic_vector(resize(signed(monit1_pos_q_wb_sync), regs_dsp_monit1_pos_q_i'length));
regs_dsp_monit1_pos_sum_i <=
std_logic_vector(resize(signed(monit1_pos_sum_wb_sync), regs_dsp_monit1_pos_sum_i'length));
-- Sync with clk_i
dsp_monit1_updt <= regs_dsp_monit1_updt_wr_o;
------------------------------------
-- Monit
------------------------------------
-- Sync with clk_i
regs_dsp_monit_amp_ch0_i <=
std_logic_vector(resize(signed(monit_amp_ch0_wb_sync), regs_dsp_monit_amp_ch0_i'length));
regs_dsp_monit_amp_ch1_i <=
std_logic_vector(resize(signed(monit_amp_ch1_wb_sync), regs_dsp_monit_amp_ch1_i'length));
regs_dsp_monit_amp_ch2_i <=
std_logic_vector(resize(signed(monit_amp_ch2_wb_sync), regs_dsp_monit_amp_ch2_i'length));
regs_dsp_monit_amp_ch3_i <=
std_logic_vector(resize(signed(monit_amp_ch3_wb_sync), regs_dsp_monit_amp_ch3_i'length));
-- Sync with clk_i
regs_dsp_monit_pos_x_i <=
std_logic_vector(resize(signed(monit_pos_x_wb_sync), regs_dsp_monit_pos_x_i'length));
regs_dsp_monit_pos_y_i <=
std_logic_vector(resize(signed(monit_pos_y_wb_sync), regs_dsp_monit_pos_y_i'length));
regs_dsp_monit_pos_q_i <=
std_logic_vector(resize(signed(monit_pos_q_wb_sync), regs_dsp_monit_pos_q_i'length));
regs_dsp_monit_pos_sum_i <=
std_logic_vector(resize(signed(monit_pos_sum_wb_sync), regs_dsp_monit_pos_sum_i'length));
-- Sync with clk_i
dsp_monit_updt <= regs_dsp_monit_updt_wr_o;
--------------------------------------------------------------------------------
-- This is the new interface for acquiring data from Monit. It goes like this:
-- 1) Bus checks if there is data in the output fifo.
-- 2) If positive, read from the ampfifo_* registers normally
--------------------------------------------------------------------------------
------------------------------------
-- Monit 1
------------------------------------
regs_ampfifo_monit1_wr_req_i <= monit1_amp_valid_out_wb_sync when
regs_ampfifo_monit1_wr_full_o = '0' else '0';
regs_ampfifo_monit1_amp_ch0_i <=
std_logic_vector(resize(signed(monit1_amp_ch0_out_wb_sync), regs_ampfifo_monit1_amp_ch0_i'length));
regs_ampfifo_monit1_amp_ch1_i <=
std_logic_vector(resize(signed(monit1_amp_ch1_out_wb_sync), regs_ampfifo_monit1_amp_ch1_i'length));
regs_ampfifo_monit1_amp_ch2_i <=
std_logic_vector(resize(signed(monit1_amp_ch2_out_wb_sync), regs_ampfifo_monit1_amp_ch2_i'length));
regs_ampfifo_monit1_amp_ch3_i <=
std_logic_vector(resize(signed(monit1_amp_ch3_out_wb_sync), regs_ampfifo_monit1_amp_ch3_i'length));
regs_posfifo_monit1_wr_req_i <= monit1_pos_valid_out_wb_sync when
regs_posfifo_monit1_wr_full_o = '0' else '0';
regs_posfifo_monit1_pos_x_i <=
std_logic_vector(resize(signed(monit1_pos_x_out_wb_sync), regs_posfifo_monit1_pos_x_i'length));
regs_posfifo_monit1_pos_y_i <=
std_logic_vector(resize(signed(monit1_pos_y_out_wb_sync), regs_posfifo_monit1_pos_y_i'length));
regs_posfifo_monit1_pos_q_i <=
std_logic_vector(resize(signed(monit1_pos_q_out_wb_sync), regs_posfifo_monit1_pos_q_i'length));
regs_posfifo_monit1_pos_sum_i <=
std_logic_vector(resize(signed(monit1_pos_sum_out_wb_sync), regs_posfifo_monit1_pos_sum_i'length));
------------------------------------
-- Monit
------------------------------------
regs_ampfifo_monit_wr_req_i <= monit_amp_valid_out_wb_sync when
regs_ampfifo_monit_wr_full_o = '0' else '0';
regs_ampfifo_monit_amp_ch0_i <=
std_logic_vector(resize(signed(monit_amp_ch0_out_wb_sync), regs_ampfifo_monit_amp_ch0_i'length));
regs_ampfifo_monit_amp_ch1_i <=
std_logic_vector(resize(signed(monit_amp_ch1_out_wb_sync), regs_ampfifo_monit_amp_ch1_i'length));
regs_ampfifo_monit_amp_ch2_i <=
std_logic_vector(resize(signed(monit_amp_ch2_out_wb_sync), regs_ampfifo_monit_amp_ch2_i'length));
regs_ampfifo_monit_amp_ch3_i <=
std_logic_vector(resize(signed(monit_amp_ch3_out_wb_sync), regs_ampfifo_monit_amp_ch3_i'length));
regs_posfifo_monit_wr_req_i <= monit_pos_valid_out_wb_sync when
regs_posfifo_monit_wr_full_o = '0' else '0';
regs_posfifo_monit_pos_x_i <=
std_logic_vector(resize(signed(monit_pos_x_out_wb_sync), regs_posfifo_monit_pos_x_i'length));
regs_posfifo_monit_pos_y_i <=
std_logic_vector(resize(signed(monit_pos_y_out_wb_sync), regs_posfifo_monit_pos_y_i'length));
regs_posfifo_monit_pos_q_i <=
std_logic_vector(resize(signed(monit_pos_q_out_wb_sync), regs_posfifo_monit_pos_q_i'length));
regs_posfifo_monit_pos_sum_i <=
std_logic_vector(resize(signed(monit_pos_sum_out_wb_sync), regs_posfifo_monit_pos_sum_i'length));
-- Test data
test_data <= regs_dds_cfg_test_data_o;
gen_with_downconv : if (g_with_downconv) generate
------------------------------------
-- High pass filtering on ADC input
------------------------------------
cmp_hpf0 : hpf_adcinput
port map
(
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
ce_i => '1', -- FIXME: create proper CE signal
data_i => adc_ch0_i,
data_o => adc_ch0_hpf
);
cmp_hpf1 : hpf_adcinput
port map
(
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
ce_i => '1', -- FIXME: create proper CE signal
data_i => adc_ch1_i,
data_o => adc_ch1_hpf
);
cmp_hpf2 : hpf_adcinput
port map
(
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
ce_i => '1', -- FIXME: create proper CE signal
data_i => adc_ch2_i,
data_o => adc_ch2_hpf
);
cmp_hpf3 : hpf_adcinput
port map
(
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
ce_i => '1', -- FIXME: create proper CE signal
data_i => adc_ch3_i,
data_o => adc_ch3_hpf
);
end generate;
gen_without_downconv : if (not g_with_downconv) generate
adc_ch0_hpf <= adc_ch0_i;
adc_ch1_hpf <= adc_ch1_i;
adc_ch2_hpf <= adc_ch2_i;
adc_ch3_hpf <= adc_ch3_i;
end generate;
-----------------------------
-- BPM Swap Module.
-----------------------------
-- BPM Swap Module interface is the slave number 1
cmp_wb_bpm_swap : wb_bpm_swap
generic map
(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_delay_vec_width => g_delay_vec_width,
g_swap_div_freq_vec_width => g_swap_div_freq_vec_width,
g_ch_width => g_input_width
)
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
fs_clk_i => fs_clk_i,
fs_rst_n_i => fs_rst_n_i,
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i => cbar_master_out(1).adr,
wb_dat_i => cbar_master_out(1).dat,
wb_dat_o => cbar_master_in(1).dat,
wb_sel_i => cbar_master_out(1).sel,
wb_we_i => cbar_master_out(1).we,
wb_cyc_i => cbar_master_out(1).cyc,
wb_stb_i => cbar_master_out(1).stb,
wb_ack_o => cbar_master_in(1).ack,
wb_stall_o => cbar_master_in(1).stall,
-----------------------------
-- External ports
-----------------------------
-- Input from ADC FMC board
cha_i => adc_ch0_hpf,
chb_i => adc_ch1_hpf,
chc_i => adc_ch2_hpf,
chd_i => adc_ch3_hpf,
ch_valid_i => adc_valid_i,
cha_o => adc_ch0_sp,
chb_o => adc_ch1_sp,
chc_o => adc_ch2_sp,
chd_o => adc_ch3_sp,
ch_tag_o => adc_tag_sp,
ch_valid_o => adc_valid_sp,
rffe_swclk_o => rffe_swclk_o,
sync_trig_i => sync_trig_slow_i
);
adc_ch0_swap_o <= adc_ch0_sp;
adc_ch1_swap_o <= adc_ch1_sp;
adc_ch2_swap_o <= adc_ch2_sp;
adc_ch3_swap_o <= adc_ch3_sp;
adc_tag_o <= adc_tag_sp;
adc_swap_valid_o <= adc_valid_sp;
-- For compatibility only
dbg_cur_address_o <= (others => '0');
dbg_adc_ch0_cond_o <= (others => '0');
dbg_adc_ch1_cond_o <= (others => '0');
dbg_adc_ch2_cond_o <= (others => '0');
dbg_adc_ch3_cond_o <= (others => '0');
-- IMPORTANT. Up until this point we were treating the DSP signals
-- as ch0, ch1, ch2 and ch3, so as to reflect the signal that were
-- input to the ADC. So, ch0 is the signal coming from ADC ch0, and
-- so on.
-- However, in the position calculation application, we have the
-- switching scheme between ADC channels ch0 <-> ch1 and ch2 <-> ch3
-- that are in fact connected to the analog signals in the following way:
--
-- ch0 <-> A
-- ch1 <-> C
-- ch2 <-> B
-- ch3 <-> D
--
-- Next, we use the position calculation formula considering the
-- analog signal convention (A, B, C, D) as this is how the information
-- is coded. This have the implication that we must input the A, B, C, D
-- in the correct order for the position_calc module, but this still
-- uses ch0, ch1, ch2, ch3 convention.
--
-- So, to fix this, we must change the order of the input signal to match
-- the analog <-> digital signal domains using: ch0 as channel A,
-- ch1 as channel C, and so on according to the scheme above.
dsp_cha <= adc_ch0_sp;
dsp_chb <= adc_ch2_sp;
dsp_chc <= adc_ch1_sp;
dsp_chd <= adc_ch3_sp;
dsp_ch_tag <= adc_tag_sp;
dsp_ch_tag_en <= regs_sw_tag_en_o;
dsp_ch_valid <= adc_valid_sp;
tbt_decim_tag_en <= regs_tbt_tag_en_o;
tbt_decim_tag_dly_c <= regs_tbt_tag_dly_o(c_tbt_decim_tag_dly_width-1 downto 0);
tbt_decim_mask_en <= regs_tbt_data_mask_ctl_en_o;
tbt_decim_mask_num_samples_beg <= unsigned(regs_tbt_data_mask_samples_beg_o(c_tbt_cic_mask_samples_width-1 downto 0));
tbt_decim_mask_num_samples_end <= unsigned(regs_tbt_data_mask_samples_end_o(c_tbt_cic_mask_samples_width-1 downto 0));
fofb_decim_mask_en <= regs_sw_data_mask_en_o;
fofb_decim_mask_num_samples <= unsigned(regs_sw_data_mask_samples_o);
monit1_decim_tag_en <= regs_monit1_tag_en_o;
monit1_decim_tag_dly_c <= regs_monit1_tag_dly_o(c_monit1_decim_tag_dly_width-1 downto 0);
monit1_decim_mask_en <= regs_monit1_data_mask_ctl_en_o;
monit1_decim_mask_num_samples_beg <= unsigned(regs_monit1_data_mask_samples_beg_o(c_monit1_cic_mask_samples_width-1 downto 0));
monit1_decim_mask_num_samples_end <= unsigned(regs_monit1_data_mask_samples_end_o(c_monit1_cic_mask_samples_width-1 downto 0));
monit_decim_tag_en <= regs_monit_tag_en_o;
monit_decim_tag_dly_c <= regs_monit_tag_dly_o(c_monit2_decim_tag_dly_width-1 downto 0);
monit_decim_mask_en <= regs_monit_data_mask_ctl_en_o;
monit_decim_mask_num_samples_beg <= unsigned(regs_monit_data_mask_samples_beg_o(c_monit2_cic_mask_samples_width-1 downto 0));
monit_decim_mask_num_samples_end <= unsigned(regs_monit_data_mask_samples_end_o(c_monit2_cic_mask_samples_width-1 downto 0));
----------------------------------------------
-- Generate Triggers for all data rates
----------------------------------------------
-- Generate proper tag for TBT
cmp_tbt_tag : swap_freqgen
generic map (
g_delay_vec_width => c_tbt_decim_tag_dly_width,
g_swap_div_freq_vec_width => c_tbt_ratio_log2
)
port map (
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
sync_trig_i => sync_trig_slow_i,
-- Swap and de-swap signals
swap_o => open,
deswap_o => tbt_decim_tag_logic,
swap_mode_i => c_swmode_swap_deswap,
swap_div_f_i => std_logic_vector(to_unsigned(c_tbt_ratio,
c_tbt_ratio_log2)),
deswap_delay_i => tbt_decim_tag_dly_c
);
tbt_decim_tag(0) <= tbt_decim_tag_logic;
-- Generate proper tag for MONIT1
cmp_monit1_tag : swap_freqgen
generic map (
g_delay_vec_width => c_monit1_decim_tag_dly_width,
g_swap_div_freq_vec_width => c_monit1_ratio_log2
)
port map (
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
en_i => fofb_amp_ce,
sync_trig_i => sync_trig_slow_i,
-- Swap and de-swap signals
swap_o => open,
deswap_o => monit1_decim_tag_logic,
swap_mode_i => c_swmode_swap_deswap,
swap_div_f_i => std_logic_vector(to_unsigned(c_monit1_ratio,
c_monit1_ratio_log2)),
swap_div_f_cnt_en_i => fofb_amp_valid,
deswap_delay_i => monit1_decim_tag_dly_c
);
monit1_decim_tag(0) <= monit1_decim_tag_logic;
-- Generate proper tag for MONIT
cmp_monit_tag : swap_freqgen
generic map (
g_delay_vec_width => c_monit2_decim_tag_dly_width,
g_swap_div_freq_vec_width => c_monit2_ratio_log2
)
port map (
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
en_i => monit1_amp_ce,
sync_trig_i => sync_trig_slow_i,
-- Swap and de-swap signals
swap_o => open,
deswap_o => monit_decim_tag_logic,
swap_mode_i => c_swmode_swap_deswap,
swap_div_f_i => std_logic_vector(to_unsigned(c_monit2_ratio,
c_monit2_ratio_log2)),
swap_div_f_cnt_en_i => monit1_amp_valid,
deswap_delay_i => monit_decim_tag_dly_c
);
monit_decim_tag(0) <= monit_decim_tag_logic;
----------------------------------------------
-- Position calculation
----------------------------------------------
cmp_position_calc : position_calc
generic map
(
-- selection of position_calc stages
g_with_downconv => g_with_downconv,
-- input sizes
g_input_width => g_input_width,
g_mixed_width => g_mixed_width,
g_adc_ratio => g_adc_ratio,
-- mixer
g_dds_width => g_dds_width,
g_dds_points => g_dds_points,
g_sin_file => g_sin_file,
g_cos_file => g_cos_file,
g_tbt_tag_desync_cnt_width => c_tbt_tag_desync_cnt_width,
g_tbt_cic_mask_samples_width => c_tbt_cic_mask_samples_width,
-- CIC setup
g_tbt_cic_delay => g_tbt_cic_delay,
g_tbt_cic_stages => g_tbt_cic_stages,
g_tbt_ratio => g_tbt_ratio,
g_tbt_decim_width => g_tbt_decim_width,
g_fofb_cic_delay => g_fofb_cic_delay,
g_fofb_cic_stages => g_fofb_cic_stages,
g_fofb_ratio => g_fofb_ratio,
g_fofb_decim_width => g_fofb_decim_width,
g_fofb_decim_desync_cnt_width => c_fofb_decim_desync_cnt_width,
g_fofb_cic_mask_samples_width => c_fofb_cic_mask_samples_width,
g_monit1_cic_delay => g_monit1_cic_delay,
g_monit1_cic_stages => g_monit1_cic_stages,
g_monit1_ratio => g_monit1_ratio,
g_monit1_cic_ratio => g_monit1_cic_ratio,
g_monit1_tag_desync_cnt_width => c_monit1_tag_desync_cnt_width,
g_monit1_cic_mask_samples_width => c_monit1_cic_mask_samples_width,
g_monit2_cic_delay => g_monit2_cic_delay,
g_monit2_cic_stages => g_monit2_cic_stages,
g_monit2_ratio => g_monit2_ratio,
g_monit2_cic_ratio => g_monit2_cic_ratio,
g_monit2_tag_desync_cnt_width => c_monit2_tag_desync_cnt_width,
g_monit2_cic_mask_samples_width => c_monit2_cic_mask_samples_width,
g_monit_decim_width => g_monit_decim_width,
-- Cordic setup
g_tbt_cordic_stages => g_tbt_cordic_stages,
g_tbt_cordic_iter_per_clk => g_tbt_cordic_iter_per_clk,
g_tbt_cordic_ratio => g_tbt_cordic_ratio,
g_fofb_cordic_stages => g_fofb_cordic_stages,
g_fofb_cordic_iter_per_clk => g_fofb_cordic_iter_per_clk,
g_fofb_cordic_ratio => g_fofb_cordic_ratio,
-- width of K constants
g_k_width => c_k_width,
-- width of offset constants
g_offset_width => c_offset_width,
--width for IQ output
g_IQ_width => g_IQ_width
)
port map
(
adc_ch0_i => dsp_cha,
adc_ch1_i => dsp_chb,
adc_ch2_i => dsp_chc,
adc_ch3_i => dsp_chd,
adc_tag_i => dsp_ch_tag,
adc_tag_en_i => dsp_ch_tag_en,
adc_valid_i => dsp_ch_valid,
clk_i => fs_clk_i,
rst_i => fs_rst,
ksum_i => regs_ksum_val_o(c_k_width-1 downto 0),
kx_i => regs_kx_val_o(c_k_width-1 downto 0),
ky_i => regs_ky_val_o(c_k_width-1 downto 0),
offset_x_i => regs_pos_calc_offset_x_o(c_offset_width-1 downto 0),
offset_y_i => regs_pos_calc_offset_y_o(c_offset_width-1 downto 0),
mix_ch0_i_o => mix_ch0_i,
mix_ch0_q_o => mix_ch0_q,
mix_ch1_i_o => mix_ch1_i,
mix_ch1_q_o => mix_ch1_q,
mix_ch2_i_o => mix_ch2_i,
mix_ch2_q_o => mix_ch2_q,
mix_ch3_i_o => mix_ch3_i,
mix_ch3_q_o => mix_ch3_q,
mix_valid_o => mix_valid,
mix_ce_o => mix_ce,
-- Synchronization trigger for TBT filter chain
tbt_tag_i => tbt_decim_tag,
tbt_tag_en_i => tbt_decim_tag_en,
tbt_tag_desync_cnt_rst_i => regs_tbt_tag_desync_cnt_rst_o,
tbt_tag_desync_cnt_o => regs_tbt_tag_desync_cnt_i,
tbt_decim_mask_en_i => tbt_decim_mask_en,
tbt_decim_mask_num_samples_beg_i => tbt_decim_mask_num_samples_beg,
tbt_decim_mask_num_samples_end_i => tbt_decim_mask_num_samples_end,
tbt_decim_ch0_i_o => tbt_decim_ch0_i,
tbt_decim_ch0_q_o => tbt_decim_ch0_q,
tbt_decim_ch1_i_o => tbt_decim_ch1_i,
tbt_decim_ch1_q_o => tbt_decim_ch1_q,
tbt_decim_ch2_i_o => tbt_decim_ch2_i,
tbt_decim_ch2_q_o => tbt_decim_ch2_q,
tbt_decim_ch3_i_o => tbt_decim_ch3_i,
tbt_decim_ch3_q_o => tbt_decim_ch3_q,
tbt_decim_valid_o => tbt_decim_valid,
tbt_decim_ce_o => tbt_decim_ce,
tbt_amp_ch0_o => tbt_amp_ch0,
tbt_amp_ch1_o => tbt_amp_ch1,
tbt_amp_ch2_o => tbt_amp_ch2,
tbt_amp_ch3_o => tbt_amp_ch3,
tbt_amp_valid_o => tbt_amp_valid,
tbt_amp_ce_o => tbt_amp_ce,
tbt_pha_ch0_o => tbt_pha_ch0,
tbt_pha_ch1_o => tbt_pha_ch1,
tbt_pha_ch2_o => tbt_pha_ch2,
tbt_pha_ch3_o => tbt_pha_ch3,
tbt_pha_valid_o => tbt_pha_valid,
tbt_pha_ce_o => tbt_pha_ce,
fofb_decim_desync_cnt_rst_i => regs_sw_tag_desync_cnt_rst_o,
fofb_decim_desync_cnt_o => regs_sw_tag_desync_cnt_i,
fofb_decim_mask_en_i => fofb_decim_mask_en,
fofb_decim_mask_num_samples_i => fofb_decim_mask_num_samples,
fofb_decim_ch0_i_o => fofb_decim_ch0_i,
fofb_decim_ch0_q_o => fofb_decim_ch0_q,
fofb_decim_ch1_i_o => fofb_decim_ch1_i,
fofb_decim_ch1_q_o => fofb_decim_ch1_q,
fofb_decim_ch2_i_o => fofb_decim_ch2_i,
fofb_decim_ch2_q_o => fofb_decim_ch2_q,
fofb_decim_ch3_i_o => fofb_decim_ch3_i,
fofb_decim_ch3_q_o => fofb_decim_ch3_q,
fofb_decim_valid_o => fofb_decim_valid,
fofb_decim_ce_o => fofb_decim_ce,
fofb_amp_ch0_o => fofb_amp_ch0,
fofb_amp_ch1_o => fofb_amp_ch1,
fofb_amp_ch2_o => fofb_amp_ch2,
fofb_amp_ch3_o => fofb_amp_ch3,
fofb_amp_valid_o => fofb_amp_valid,
fofb_amp_ce_o => fofb_amp_ce,
fofb_pha_ch0_o => fofb_pha_ch0,
fofb_pha_ch1_o => fofb_pha_ch1,
fofb_pha_ch2_o => fofb_pha_ch2,
fofb_pha_ch3_o => fofb_pha_ch3,
fofb_pha_valid_o => fofb_pha_valid,
fofb_pha_ce_o => fofb_pha_ce,
-- Synchronization trigger for TBT filter chain
monit1_tag_i => monit1_decim_tag,
monit1_tag_en_i => monit1_decim_tag_en,
monit1_tag_desync_cnt_rst_i => regs_monit1_tag_desync_cnt_rst_o,
monit1_tag_desync_cnt_o => regs_monit1_tag_desync_cnt_i,
monit1_decim_mask_en_i => monit1_decim_mask_en,
monit1_decim_mask_num_samples_beg_i => monit1_decim_mask_num_samples_beg,
monit1_decim_mask_num_samples_end_i => monit1_decim_mask_num_samples_end,
monit1_amp_ch0_o => monit1_amp_ch0,
monit1_amp_ch1_o => monit1_amp_ch1,
monit1_amp_ch2_o => monit1_amp_ch2,
monit1_amp_ch3_o => monit1_amp_ch3,
monit1_amp_valid_o => monit1_amp_valid,
monit1_amp_ce_o => monit1_amp_ce,
-- Synchronization trigger for TBT filter chain
monit_tag_i => monit_decim_tag,
monit_tag_en_i => monit_decim_tag_en,
monit_tag_desync_cnt_rst_i => regs_monit_tag_desync_cnt_rst_o,
monit_tag_desync_cnt_o => regs_monit_tag_desync_cnt_i,
monit_decim_mask_en_i => monit_decim_mask_en,
monit_decim_mask_num_samples_beg_i => monit_decim_mask_num_samples_beg,
monit_decim_mask_num_samples_end_i => monit_decim_mask_num_samples_end,
monit_amp_ch0_o => monit_amp_ch0,
monit_amp_ch1_o => monit_amp_ch1,
monit_amp_ch2_o => monit_amp_ch2,
monit_amp_ch3_o => monit_amp_ch3,
monit_amp_valid_o => monit_amp_valid,
monit_amp_ce_o => monit_amp_ce,
tbt_pos_x_o => tbt_pos_x,
tbt_pos_y_o => tbt_pos_y,
tbt_pos_q_o => tbt_pos_q,
tbt_pos_sum_o => tbt_pos_sum,
tbt_pos_valid_o => tbt_pos_valid,
tbt_pos_ce_o => tbt_pos_ce,
fofb_pos_x_o => fofb_pos_x,
fofb_pos_y_o => fofb_pos_y,
fofb_pos_q_o => fofb_pos_q,
fofb_pos_sum_o => fofb_pos_sum,
fofb_pos_valid_o => fofb_pos_valid,
fofb_pos_ce_o => fofb_pos_ce,
monit1_pos_x_o => monit1_pos_x,
monit1_pos_y_o => monit1_pos_y,
monit1_pos_q_o => monit1_pos_q,
monit1_pos_sum_o => monit1_pos_sum,
monit1_pos_valid_o => monit1_pos_valid,
monit1_pos_ce_o => monit1_pos_ce,
monit_pos_x_o => monit_pos_x,
monit_pos_y_o => monit_pos_y,
monit_pos_q_o => monit_pos_q,
monit_pos_sum_o => monit_pos_sum,
monit_pos_valid_o => monit_pos_valid,
monit_pos_ce_o => monit_pos_ce
);
--------------------------------------------------------------------------
-- Counters Generation --
--------------------------------------------------------------------------
cmp_counters_gen : counters_gen
generic map
(
g_cnt_width => c_cnt_width_array
)
port map
(
rst_n_i => fs_rst_n_i,
clk_i => fs_clk_i,
---------------------------------
-- Counter generation interface
---------------------------------
cnt_ce_array_i => cnt_ce_array,
cnt_up_array_i => cnt_up_array,
cnt_array_o => cnt_array
);
cnt_ce_array <= (
c_counters_mix_idx => mix_ce,
c_counters_tbt_decim_idx => tbt_decim_ce,
c_counters_tbt_amp_idx => tbt_amp_ce,
c_counters_tbt_pha_idx => tbt_pha_ce,
c_counters_tbt_pos_idx => tbt_pos_ce,
c_counters_fofb_decim_idx => fofb_decim_ce,
c_counters_fofb_amp_idx => fofb_amp_ce,
c_counters_fofb_pha_idx => fofb_pha_ce,
c_counters_fofb_pos_idx => fofb_pos_ce,
c_counters_monit1_amp_idx => monit1_amp_ce,
c_counters_monit1_pos_idx => monit1_pos_ce,
c_counters_monit_amp_idx => monit_amp_ce,
c_counters_monit_pos_idx => monit_pos_ce);
-- Don't wait on the actual valid from the DSP rates.
-- Just assume every test word is valid, which it is.
cnt_up_array <= (
c_counters_mix_idx => '1',
c_counters_tbt_decim_idx => '1',
c_counters_tbt_amp_idx => '1',
c_counters_tbt_pha_idx => '1',
c_counters_tbt_pos_idx => '1',
c_counters_fofb_decim_idx => '1',
c_counters_fofb_amp_idx => '1',
c_counters_fofb_pha_idx => '1',
c_counters_fofb_pos_idx => '1',
c_counters_monit1_amp_idx => '1',
c_counters_monit1_pos_idx => '1',
c_counters_monit_amp_idx => '1',
c_counters_monit_pos_idx => '1');
--------------------------------------------------------------------------
-- CDC position data (Amplitudes and Position) to fs_clk domain --
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- MIX data --
--------------------------------------------------------------------------
-- MIX data
p_reg_cdc_fifo_mix_inputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if mix_ce = '1' then
if test_data = '1' then
fifo_mix_out <= f_dup_counter_array(cnt_array(c_counters_mix_idx)(c_cnt_width_array(c_counters_mix_idx)-1 downto 0),
8);
fifo_mix_valid_out <= cnt_up_array(c_counters_mix_idx);
else
fifo_mix_out <= mix_ch3_q &
mix_ch3_i &
mix_ch2_q &
mix_ch2_i &
mix_ch1_q &
mix_ch1_i &
mix_ch0_q &
mix_ch0_i;
fifo_mix_valid_out <= mix_valid;
end if;
else
fifo_mix_valid_out <= '0';
end if;
end if;
end process;
mix_ch3_q_o <= fifo_mix_out(8*g_IQ_width-1 downto 7*g_IQ_width);
mix_ch3_i_o <= fifo_mix_out(7*g_IQ_width-1 downto 6*g_IQ_width);
mix_ch2_q_o <= fifo_mix_out(6*g_IQ_width-1 downto 5*g_IQ_width);
mix_ch2_i_o <= fifo_mix_out(5*g_IQ_width-1 downto 4*g_IQ_width);
mix_ch1_q_o <= fifo_mix_out(4*g_IQ_width-1 downto 3*g_IQ_width);
mix_ch1_i_o <= fifo_mix_out(3*g_IQ_width-1 downto 2*g_IQ_width);
mix_ch0_q_o <= fifo_mix_out(2*g_IQ_width-1 downto g_IQ_width);
mix_ch0_i_o <= fifo_mix_out(g_IQ_width-1 downto 0);
mix_valid_o <= fifo_mix_valid_out;
--------------------------------------------------------------------------
-- TBT data --
--------------------------------------------------------------------------
-- TBT Decim data
p_reg_cdc_fifo_tbt_decim_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if tbt_decim_ce = '1' then
if test_data = '1' then
fifo_tbt_decim_out <= f_dup_counter_array(cnt_array(c_counters_tbt_decim_idx)(c_cnt_width_array(c_counters_tbt_decim_idx)-1 downto 0),
8);
fifo_tbt_decim_valid_out <= cnt_up_array(c_counters_tbt_decim_idx);
else
fifo_tbt_decim_out <= tbt_decim_ch3_q &
tbt_decim_ch3_i &
tbt_decim_ch2_q &
tbt_decim_ch2_i &
tbt_decim_ch1_q &
tbt_decim_ch1_i &
tbt_decim_ch0_q &
tbt_decim_ch0_i;
fifo_tbt_decim_valid_out <= tbt_decim_valid;
end if;
else
fifo_tbt_decim_valid_out <= '0';
end if;
end if;
end process;
tbt_decim_ch3_q_o <= fifo_tbt_decim_out(8*g_tbt_decim_width-1 downto 7*g_tbt_decim_width);
tbt_decim_ch3_i_o <= fifo_tbt_decim_out(7*g_tbt_decim_width-1 downto 6*g_tbt_decim_width);
tbt_decim_ch2_q_o <= fifo_tbt_decim_out(6*g_tbt_decim_width-1 downto 5*g_tbt_decim_width);
tbt_decim_ch2_i_o <= fifo_tbt_decim_out(5*g_tbt_decim_width-1 downto 4*g_tbt_decim_width);
tbt_decim_ch1_q_o <= fifo_tbt_decim_out(4*g_tbt_decim_width-1 downto 3*g_tbt_decim_width);
tbt_decim_ch1_i_o <= fifo_tbt_decim_out(3*g_tbt_decim_width-1 downto 2*g_tbt_decim_width);
tbt_decim_ch0_q_o <= fifo_tbt_decim_out(2*g_tbt_decim_width-1 downto g_tbt_decim_width);
tbt_decim_ch0_i_o <= fifo_tbt_decim_out(g_tbt_decim_width-1 downto 0);
tbt_decim_valid_o <= fifo_tbt_decim_valid_out;
--TBT amplitudes data
p_reg_cdc_fifo_tbt_amp_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if tbt_amp_ce = '1' then
if test_data = '1' then
fifo_tbt_amp_out <= f_dup_counter_array(cnt_array(c_counters_tbt_amp_idx)(c_cnt_width_array(c_counters_tbt_amp_idx)-1 downto 0),
4);
fifo_tbt_amp_valid_out <= cnt_up_array(c_counters_tbt_amp_idx);
else
fifo_tbt_amp_out <= tbt_amp_ch3 &
tbt_amp_ch2 &
tbt_amp_ch1 &
tbt_amp_ch0;
fifo_tbt_amp_valid_out <= tbt_amp_valid;
end if;
else
fifo_tbt_amp_valid_out <= '0';
end if;
end if;
end process;
tbt_amp_ch3_o <= fifo_tbt_amp_out(4*g_tbt_decim_width-1 downto 3*g_tbt_decim_width);
tbt_amp_ch2_o <= fifo_tbt_amp_out(3*g_tbt_decim_width-1 downto 2*g_tbt_decim_width);
tbt_amp_ch1_o <= fifo_tbt_amp_out(2*g_tbt_decim_width-1 downto g_tbt_decim_width);
tbt_amp_ch0_o <= fifo_tbt_amp_out(g_tbt_decim_width-1 downto 0);
tbt_amp_valid_o <= fifo_tbt_amp_valid_out;
--TBT phase data
p_reg_cdc_fifo_tbt_pha_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if tbt_pha_ce = '1' then
if test_data = '1' then
fifo_tbt_pha_out <= f_dup_counter_array(cnt_array(c_counters_tbt_pha_idx)(c_cnt_width_array(c_counters_tbt_pha_idx)-1 downto 0),
4);
fifo_tbt_pha_valid_out <= cnt_up_array(c_counters_tbt_pha_idx);
else
fifo_tbt_pha_out <= tbt_pha_ch3 &
tbt_pha_ch2 &
tbt_pha_ch1 &
tbt_pha_ch0;
fifo_tbt_pha_valid_out <= tbt_pha_valid;
end if;
else
fifo_tbt_pha_valid_out <= '0';
end if;
end if;
end process;
tbt_pha_ch3_o <= fifo_tbt_pha_out(4*g_tbt_decim_width-1 downto 3*g_tbt_decim_width);
tbt_pha_ch2_o <= fifo_tbt_pha_out(3*g_tbt_decim_width-1 downto 2*g_tbt_decim_width);
tbt_pha_ch1_o <= fifo_tbt_pha_out(2*g_tbt_decim_width-1 downto g_tbt_decim_width);
tbt_pha_ch0_o <= fifo_tbt_pha_out(g_tbt_decim_width-1 downto 0);
tbt_pha_valid_o <= fifo_tbt_pha_valid_out;
-- TBT position data
p_reg_cdc_fifo_tbt_pos_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if tbt_pos_ce = '1' then
if test_data = '1' then
fifo_tbt_pos_out <= f_dup_counter_array(cnt_array(c_counters_tbt_pos_idx)(c_cnt_width_array(c_counters_tbt_pos_idx)-1 downto 0),
4);
fifo_tbt_pos_valid_out <= cnt_up_array(c_counters_tbt_pos_idx);
else
fifo_tbt_pos_out <= tbt_pos_sum &
tbt_pos_q &
tbt_pos_y &
tbt_pos_x;
fifo_tbt_pos_valid_out <= tbt_pos_valid;
end if;
else
fifo_tbt_pos_valid_out <= '0';
end if;
end if;
end process;
tbt_pos_sum_o <= fifo_tbt_pos_out(4*g_tbt_decim_width-1 downto 3*g_tbt_decim_width);
tbt_pos_q_o <= fifo_tbt_pos_out(3*g_tbt_decim_width-1 downto 2*g_tbt_decim_width);
tbt_pos_y_o <= fifo_tbt_pos_out(2*g_tbt_decim_width-1 downto g_tbt_decim_width);
tbt_pos_x_o <= fifo_tbt_pos_out(g_tbt_decim_width-1 downto 0);
tbt_pos_valid_o <= fifo_tbt_pos_valid_out;
--------------------------------------------------------------------------
-- FOFB data --
--------------------------------------------------------------------------
-- FOFB Decim data
p_reg_cdc_fifo_fofb_decim_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fofb_decim_ce = '1' then
if test_data = '1' then
fifo_fofb_decim_out <= f_dup_counter_array(cnt_array(c_counters_fofb_decim_idx)(c_cnt_width_array(c_counters_fofb_decim_idx)-1 downto 0),
8);
fifo_fofb_decim_valid_out <= cnt_up_array(c_counters_fofb_decim_idx);
else
fifo_fofb_decim_out <= fofb_decim_ch3_q &
fofb_decim_ch3_i &
fofb_decim_ch2_q &
fofb_decim_ch2_i &
fofb_decim_ch1_q &
fofb_decim_ch1_i &
fofb_decim_ch0_q &
fofb_decim_ch0_i;
fifo_fofb_decim_valid_out <= fofb_decim_valid;
end if;
else
fifo_fofb_decim_valid_out <= '0';
end if;
end if;
end process;
fofb_decim_ch3_q_o <= fifo_fofb_decim_out(8*g_fofb_decim_width-1 downto 7*g_fofb_decim_width);
fofb_decim_ch3_i_o <= fifo_fofb_decim_out(7*g_fofb_decim_width-1 downto 6*g_fofb_decim_width);
fofb_decim_ch2_q_o <= fifo_fofb_decim_out(6*g_fofb_decim_width-1 downto 5*g_fofb_decim_width);
fofb_decim_ch2_i_o <= fifo_fofb_decim_out(5*g_fofb_decim_width-1 downto 4*g_fofb_decim_width);
fofb_decim_ch1_q_o <= fifo_fofb_decim_out(4*g_fofb_decim_width-1 downto 3*g_fofb_decim_width);
fofb_decim_ch1_i_o <= fifo_fofb_decim_out(3*g_fofb_decim_width-1 downto 2*g_fofb_decim_width);
fofb_decim_ch0_q_o <= fifo_fofb_decim_out(2*g_fofb_decim_width-1 downto g_fofb_decim_width);
fofb_decim_ch0_i_o <= fifo_fofb_decim_out(g_fofb_decim_width-1 downto 0);
fofb_decim_valid_o <= fifo_fofb_decim_valid_out;
--FOFB amplitudes data
p_reg_cdc_fifo_fofb_amp_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fofb_amp_ce = '1' then
if test_data = '1' then
fifo_fofb_amp_out <= f_dup_counter_array(cnt_array(c_counters_fofb_amp_idx)(c_cnt_width_array(c_counters_fofb_amp_idx)-1 downto 0),
4);
fifo_fofb_amp_valid_out <= cnt_up_array(c_counters_fofb_amp_idx);
else
fifo_fofb_amp_out <= fofb_amp_ch3 &
fofb_amp_ch2 &
fofb_amp_ch1 &
fofb_amp_ch0;
fifo_fofb_amp_valid_out <= fofb_amp_valid;
end if;
else
fifo_fofb_amp_valid_out <= '0';
end if;
end if;
end process;
fofb_amp_ch3_o <= fifo_fofb_amp_out(4*g_fofb_decim_width-1 downto 3*g_fofb_decim_width);
fofb_amp_ch2_o <= fifo_fofb_amp_out(3*g_fofb_decim_width-1 downto 2*g_fofb_decim_width);
fofb_amp_ch1_o <= fifo_fofb_amp_out(2*g_fofb_decim_width-1 downto g_fofb_decim_width);
fofb_amp_ch0_o <= fifo_fofb_amp_out(g_fofb_decim_width-1 downto 0);
fofb_amp_valid_o <= fifo_fofb_amp_valid_out;
-- FOFB phase data
p_reg_cdc_fifo_fofb_pha_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fofb_pha_ce = '1' then
if test_data = '1' then
fifo_fofb_pha_out <= f_dup_counter_array(cnt_array(c_counters_fofb_pha_idx)(c_cnt_width_array(c_counters_fofb_pha_idx)-1 downto 0),
4);
fifo_fofb_pha_valid_out <= cnt_up_array(c_counters_fofb_pha_idx);
else
fifo_fofb_pha_out <= fofb_pha_ch3 &
fofb_pha_ch2 &
fofb_pha_ch1 &
fofb_pha_ch0;
fifo_fofb_pha_valid_out <= fofb_pha_valid;
end if;
else
fifo_fofb_pha_valid_out <= '0';
end if;
end if;
end process;
fofb_pha_ch3_o <= fifo_fofb_pha_out(4*g_fofb_decim_width-1 downto 3*g_fofb_decim_width);
fofb_pha_ch2_o <= fifo_fofb_pha_out(3*g_fofb_decim_width-1 downto 2*g_fofb_decim_width);
fofb_pha_ch1_o <= fifo_fofb_pha_out(2*g_fofb_decim_width-1 downto g_fofb_decim_width);
fofb_pha_ch0_o <= fifo_fofb_pha_out(g_fofb_decim_width-1 downto 0);
fofb_pha_valid_o <= fifo_fofb_pha_valid_out;
-- FOFB position data
p_reg_cdc_fifo_fofb_pos_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fofb_pos_ce = '1' then
if test_data = '1' then
fifo_fofb_pos_out <= f_dup_counter_array(cnt_array(c_counters_fofb_pos_idx)(c_cnt_width_array(c_counters_fofb_pos_idx)-1 downto 0),
4);
fifo_fofb_pos_valid_out <= cnt_up_array(c_counters_fofb_pos_idx);
else
fifo_fofb_pos_out <= fofb_pos_sum &
fofb_pos_q &
fofb_pos_y &
fofb_pos_x;
fifo_fofb_pos_valid_out <= fofb_pos_valid;
end if;
else
fifo_fofb_pos_valid_out <= '0';
end if;
end if;
end process;
fofb_pos_sum_o <= fifo_fofb_pos_out(4*g_fofb_decim_width-1 downto 3*g_fofb_decim_width);
fofb_pos_q_o <= fifo_fofb_pos_out(3*g_fofb_decim_width-1 downto 2*g_fofb_decim_width);
fofb_pos_y_o <= fifo_fofb_pos_out(2*g_fofb_decim_width-1 downto g_fofb_decim_width);
fofb_pos_x_o <= fifo_fofb_pos_out(g_fofb_decim_width-1 downto 0);
fofb_pos_valid_o <= fifo_fofb_pos_valid_out;
--------------------------------------------------------------------------
-- Monitoring 1 data --
--------------------------------------------------------------------------
-- Monitoring 1 amplitudes data
cmp_position_calc_cdc_fifo_monit1_amp_wb : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_monit_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk_i,
data_i => fifo_monit1_amp_out,
valid_i => fifo_monit1_amp_valid_out,
clk_rd_i => clk_i,
data_o => fifo_monit1_amp_out_wb_sync,
valid_o => fifo_monit1_amp_valid_out_wb_sync
);
monit1_amp_ch3_out_wb_sync <= fifo_monit1_amp_out_wb_sync(4*g_monit_decim_width-1 downto 3*g_monit_decim_width);
monit1_amp_ch2_out_wb_sync <= fifo_monit1_amp_out_wb_sync(3*g_monit_decim_width-1 downto 2*g_monit_decim_width);
monit1_amp_ch1_out_wb_sync <= fifo_monit1_amp_out_wb_sync(2*g_monit_decim_width-1 downto g_monit_decim_width);
monit1_amp_ch0_out_wb_sync <= fifo_monit1_amp_out_wb_sync(g_monit_decim_width-1 downto 0);
monit1_amp_valid_out_wb_sync <= fifo_monit1_amp_valid_out_wb_sync;
p_reg_cdc_fifo_monit1_amp_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if monit1_amp_ce = '1' then
if test_data = '1' then
fifo_monit1_amp_out <= f_dup_counter_array(cnt_array(c_counters_monit1_amp_idx)(c_cnt_width_array(c_counters_monit1_amp_idx)-1 downto 0),
4);
fifo_monit1_amp_valid_out <= cnt_up_array(c_counters_monit1_amp_idx);
else
fifo_monit1_amp_out <= monit1_amp_ch3 &
monit1_amp_ch2 &
monit1_amp_ch1 &
monit1_amp_ch0;
fifo_monit1_amp_valid_out <= monit1_amp_valid;
end if;
else
fifo_monit1_amp_valid_out <= '0';
end if;
end if;
end process;
monit1_amp_ch3_o <= fifo_monit1_amp_out(4*g_monit_decim_width-1 downto 3*g_monit_decim_width);
monit1_amp_ch2_o <= fifo_monit1_amp_out(3*g_monit_decim_width-1 downto 2*g_monit_decim_width);
monit1_amp_ch1_o <= fifo_monit1_amp_out(2*g_monit_decim_width-1 downto g_monit_decim_width);
monit1_amp_ch0_o <= fifo_monit1_amp_out(g_monit_decim_width-1 downto 0);
monit1_amp_valid_o <= fifo_monit1_amp_valid_out;
p_reg_monit1_amp_sync_wb : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
monit1_amp_valid_wb_sync <= '0';
monit1_amp_ch3_wb_sync <= (others => '0');
monit1_amp_ch2_wb_sync <= (others => '0');
monit1_amp_ch1_wb_sync <= (others => '0');
monit1_amp_ch0_wb_sync <= (others => '0');
else
monit1_amp_valid_wb_sync <= monit1_amp_valid_out_wb_sync;
-- FIXME: We don't care to wait for the FIFO valid bit. The data remains
-- after it. Also, the synchronism between "true" valid data and the DSP
-- MONIT 1 registers (read from the WB bus) must be fixed in another
-- way, anyway, rendering the capture of only the "true" valid data by
-- another register wasteful.
if dsp_monit1_updt = '1' then
monit1_amp_ch3_wb_sync <= monit1_amp_ch3_out_wb_sync;
monit1_amp_ch2_wb_sync <= monit1_amp_ch2_out_wb_sync;
monit1_amp_ch1_wb_sync <= monit1_amp_ch1_out_wb_sync;
monit1_amp_ch0_wb_sync <= monit1_amp_ch0_out_wb_sync;
end if;
end if;
end if;
end process;
-- Monitoring position data
cmp_position_calc_cdc_fifo_monit1_pos_wb : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_monit_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk_i,
data_i => fifo_monit1_pos_out,
valid_i => fifo_monit1_pos_valid_out,
clk_rd_i => clk_i,
data_o => fifo_monit1_pos_out_wb_sync,
valid_o => fifo_monit1_pos_valid_out_wb_sync
);
monit1_pos_sum_out_wb_sync <= fifo_monit1_pos_out_wb_sync(4*g_monit_decim_width-1 downto 3*g_monit_decim_width);
monit1_pos_q_out_wb_sync <= fifo_monit1_pos_out_wb_sync(3*g_monit_decim_width-1 downto 2*g_monit_decim_width);
monit1_pos_y_out_wb_sync <= fifo_monit1_pos_out_wb_sync(2*g_monit_decim_width-1 downto g_monit_decim_width);
monit1_pos_x_out_wb_sync <= fifo_monit1_pos_out_wb_sync(g_monit_decim_width-1 downto 0);
monit1_pos_valid_out_wb_sync <= fifo_monit1_pos_valid_out_wb_sync;
p_reg_cdc_fifo_monit1_pos_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if monit1_pos_ce = '1' then
if test_data = '1' then
fifo_monit1_pos_out <= f_dup_counter_array(cnt_array(c_counters_monit1_pos_idx)(c_cnt_width_array(c_counters_monit1_pos_idx)-1 downto 0),
4);
else
fifo_monit1_pos_out <= monit1_pos_sum &
monit1_pos_q &
monit1_pos_y &
monit1_pos_x;
end if;
fifo_monit1_pos_valid_out <= monit1_pos_valid;
else
fifo_monit1_pos_valid_out <= '0';
end if;
end if;
end process;
monit1_pos_sum_o <= fifo_monit1_pos_out(4*g_monit_decim_width-1 downto 3*g_monit_decim_width);
monit1_pos_q_o <= fifo_monit1_pos_out(3*g_monit_decim_width-1 downto 2*g_monit_decim_width);
monit1_pos_y_o <= fifo_monit1_pos_out(2*g_monit_decim_width-1 downto g_monit_decim_width);
monit1_pos_x_o <= fifo_monit1_pos_out(g_monit_decim_width-1 downto 0);
monit1_pos_valid_o <= fifo_monit1_pos_valid_out;
p_reg_monit1_pos_sync_wb : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
monit1_pos_valid_wb_sync <= '0';
monit1_pos_sum_wb_sync <= (others => '0');
monit1_pos_q_wb_sync <= (others => '0');
monit1_pos_y_wb_sync <= (others => '0');
monit1_pos_x_wb_sync <= (others => '0');
else
monit1_pos_valid_wb_sync <= monit1_pos_valid_out_wb_sync;
-- FIXME: We don't care to wait for the FIFO valid bit. The data remains
-- after it. Also, the synchronism between "true" valid data and the DSP
-- MONIT registers (read from the WB bus) must be fixed in another
-- way, anyway, rendering the capture of only the "true" valid data by
-- another register wasteful.
if dsp_monit1_updt = '1' then
monit1_pos_sum_wb_sync <= monit1_pos_sum_out_wb_sync;
monit1_pos_q_wb_sync <= monit1_pos_q_out_wb_sync;
monit1_pos_y_wb_sync <= monit1_pos_y_out_wb_sync;
monit1_pos_x_wb_sync <= monit1_pos_x_out_wb_sync;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- Monitoring data --
--------------------------------------------------------------------------
-- Monitoring amplitudes data
cmp_position_calc_cdc_fifo_monit_amp_wb : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_monit_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk_i,
data_i => fifo_monit_amp_out,
valid_i => fifo_monit_amp_valid_out,
clk_rd_i => clk_i,
data_o => fifo_monit_amp_out_wb_sync,
valid_o => fifo_monit_amp_valid_out_wb_sync
);
monit_amp_ch3_out_wb_sync <= fifo_monit_amp_out_wb_sync(4*g_monit_decim_width-1 downto 3*g_monit_decim_width);
monit_amp_ch2_out_wb_sync <= fifo_monit_amp_out_wb_sync(3*g_monit_decim_width-1 downto 2*g_monit_decim_width);
monit_amp_ch1_out_wb_sync <= fifo_monit_amp_out_wb_sync(2*g_monit_decim_width-1 downto g_monit_decim_width);
monit_amp_ch0_out_wb_sync <= fifo_monit_amp_out_wb_sync(g_monit_decim_width-1 downto 0);
monit_amp_valid_out_wb_sync <= fifo_monit_amp_valid_out_wb_sync;
p_reg_cdc_fifo_monit_amp_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if monit_amp_ce = '1' then
if test_data = '1' then
fifo_monit_amp_out <= f_dup_counter_array(cnt_array(c_counters_monit_amp_idx)(c_cnt_width_array(c_counters_monit_amp_idx)-1 downto 0),
4);
fifo_monit_amp_valid_out <= cnt_up_array(c_counters_monit_amp_idx);
else
fifo_monit_amp_out <= monit_amp_ch3 &
monit_amp_ch2 &
monit_amp_ch1 &
monit_amp_ch0;
fifo_monit_amp_valid_out <= monit_amp_valid;
end if;
else
fifo_monit_amp_valid_out <= '0';
end if;
end if;
end process;
monit_amp_ch3_o <= fifo_monit_amp_out(4*g_monit_decim_width-1 downto 3*g_monit_decim_width);
monit_amp_ch2_o <= fifo_monit_amp_out(3*g_monit_decim_width-1 downto 2*g_monit_decim_width);
monit_amp_ch1_o <= fifo_monit_amp_out(2*g_monit_decim_width-1 downto g_monit_decim_width);
monit_amp_ch0_o <= fifo_monit_amp_out(g_monit_decim_width-1 downto 0);
monit_amp_valid_o <= fifo_monit_amp_valid_out;
p_reg_monit_amp_sync_wb : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
monit_amp_valid_wb_sync <= '0';
monit_amp_ch3_wb_sync <= (others => '0');
monit_amp_ch2_wb_sync <= (others => '0');
monit_amp_ch1_wb_sync <= (others => '0');
monit_amp_ch0_wb_sync <= (others => '0');
else
monit_amp_valid_wb_sync <= monit_amp_valid_out_wb_sync;
-- FIXME: We don't care to wait for the FIFO valid bit. The data remains
-- after it. Also, the synchronism between "true" valid data and the DSP
-- MONIT registers (read from the WB bus) must be fixed in another
-- way, anyway, rendering the capture of only the "true" valid data by
-- another register wasteful.
if dsp_monit_updt = '1' then
monit_amp_ch3_wb_sync <= monit_amp_ch3_out_wb_sync;
monit_amp_ch2_wb_sync <= monit_amp_ch2_out_wb_sync;
monit_amp_ch1_wb_sync <= monit_amp_ch1_out_wb_sync;
monit_amp_ch0_wb_sync <= monit_amp_ch0_out_wb_sync;
end if;
end if;
end if;
end process;
-- Monitoring position data
cmp_position_calc_cdc_fifo_monit_pos_wb : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_monit_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk_i,
data_i => fifo_monit_pos_out,
valid_i => fifo_monit_pos_valid_out,
clk_rd_i => clk_i,
data_o => fifo_monit_pos_out_wb_sync,
valid_o => fifo_monit_pos_valid_out_wb_sync
);
monit_pos_sum_out_wb_sync <= fifo_monit_pos_out_wb_sync(4*g_monit_decim_width-1 downto 3*g_monit_decim_width);
monit_pos_q_out_wb_sync <= fifo_monit_pos_out_wb_sync(3*g_monit_decim_width-1 downto 2*g_monit_decim_width);
monit_pos_y_out_wb_sync <= fifo_monit_pos_out_wb_sync(2*g_monit_decim_width-1 downto g_monit_decim_width);
monit_pos_x_out_wb_sync <= fifo_monit_pos_out_wb_sync(g_monit_decim_width-1 downto 0);
monit_pos_valid_out_wb_sync <= fifo_monit_pos_valid_out_wb_sync;
p_reg_cdc_fifo_monit_pos_outputs : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if monit_pos_ce = '1' then
if test_data = '1' then
fifo_monit_pos_out <= f_dup_counter_array(cnt_array(c_counters_monit_pos_idx)(c_cnt_width_array(c_counters_monit_pos_idx)-1 downto 0),
4);
else
fifo_monit_pos_out <= monit_pos_sum &
monit_pos_q &
monit_pos_y &
monit_pos_x;
end if;
fifo_monit_pos_valid_out <= monit_pos_valid;
else
fifo_monit_pos_valid_out <= '0';
end if;
end if;
end process;
monit_pos_sum_o <= fifo_monit_pos_out(4*g_monit_decim_width-1 downto 3*g_monit_decim_width);
monit_pos_q_o <= fifo_monit_pos_out(3*g_monit_decim_width-1 downto 2*g_monit_decim_width);
monit_pos_y_o <= fifo_monit_pos_out(2*g_monit_decim_width-1 downto g_monit_decim_width);
monit_pos_x_o <= fifo_monit_pos_out(g_monit_decim_width-1 downto 0);
monit_pos_valid_o <= fifo_monit_pos_valid_out;
p_reg_monit_pos_sync_wb : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
monit_pos_valid_wb_sync <= '0';
monit_pos_sum_wb_sync <= (others => '0');
monit_pos_q_wb_sync <= (others => '0');
monit_pos_y_wb_sync <= (others => '0');
monit_pos_x_wb_sync <= (others => '0');
else
monit_pos_valid_wb_sync <= monit_pos_valid_out_wb_sync;
-- FIXME: We don't care to wait for the FIFO valid bit. The data remains
-- after it. Also, the synchronism between "true" valid data and the DSP
-- MONIT registers (read from the WB bus) must be fixed in another
-- way, anyway, rendering the capture of only the "true" valid data by
-- another register wasteful.
if dsp_monit_updt = '1' then
monit_pos_sum_wb_sync <= monit_pos_sum_out_wb_sync;
monit_pos_q_wb_sync <= monit_pos_q_out_wb_sync;
monit_pos_y_wb_sync <= monit_pos_y_out_wb_sync;
monit_pos_x_wb_sync <= monit_pos_x_out_wb_sync;
end if;
end if;
end if;
end process;
end rtl;
|
lgpl-3.0
|
dcdb0d6d097009f7679c6c86c3cfa2c9
| 0.50589 | 3.310221 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/machine/sirius_sr_130M/machine_pkg.vhd
| 1 | 3,753 |
-------------------------------------------------------------------------------
-- Title : Machine package for Sirius with 130MSps ADC
-- Project :
-------------------------------------------------------------------------------
-- File : machine_pkg.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-04-14
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Machine package with parameters for Sirius ADC
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-14 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package machine_pkg is
constant c_pos_calc_with_downconv : boolean := true;
constant c_pos_calc_adc_freq : real := 122.804e6;
constant c_pos_calc_input_width : natural := 16;
constant c_pos_calc_mixed_width : natural := 16;
constant c_pos_calc_adc_ratio : natural := 1;
constant c_pos_calc_dds_width : natural := 16;
constant c_pos_calc_dds_points : natural := 203;
constant c_pos_calc_sin_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_sin.nif";
constant c_pos_calc_cos_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_cos.nif";
constant c_pos_calc_tbt_cic_delay : natural := 1;
constant c_pos_calc_tbt_cic_stages : natural := 1;
constant c_pos_calc_tbt_ratio : natural := 203;
constant c_pos_calc_tbt_decim_width : natural := 32;
constant c_pos_calc_fofb_cic_delay : natural := 1;
constant c_pos_calc_fofb_cic_stages : natural := 1;
constant c_pos_calc_fofb_ratio : natural := 490;
constant c_pos_calc_fofb_decim_width : natural := 32;
constant c_pos_calc_monit1_cic_delay : natural := 1;
constant c_pos_calc_monit1_cic_stages : natural := 1;
constant c_pos_calc_monit1_ratio : natural := 200; --ratio between fofb and monit 1
constant c_pos_calc_monit1_cic_ratio : natural := 8;
constant c_pos_calc_monit2_cic_delay : natural := 1;
constant c_pos_calc_monit2_cic_stages : natural := 1;
constant c_pos_calc_monit2_ratio : natural := 100; -- ratio between monit 1 and 2
constant c_pos_calc_monit2_cic_ratio : natural := 8;
constant c_pos_calc_monit_decim_width : natural := 32;
constant c_pos_calc_tbt_cordic_stages : positive := 12;
constant c_pos_calc_tbt_cordic_iter_per_clk : positive := 3;
constant c_pos_calc_tbt_cordic_ratio : positive := 4;
constant c_pos_calc_fofb_cordic_stages : positive := 15;
constant c_pos_calc_fofb_cordic_iter_per_clk : positive := 3;
constant c_pos_calc_fofb_cordic_ratio : positive := 4;
constant c_pos_calc_k_width : natural := 25;
constant c_pos_calc_offset_width : natural := 32;
constant c_pos_calc_IQ_width : natural := c_pos_calc_mixed_width;
constant c_pos_calc_k_sum : natural := 85e5;
constant c_pos_calc_k_x : natural := 85e5;
constant c_pos_calc_k_y : natural := 85e5;
end machine_pkg;
|
lgpl-3.0
|
09665c683ce5c55ab9ca5feea15aada3
| 0.505995 | 3.901247 | false | false | false | false |
tec499-20142/t01-warmup
|
sim/tb/interface_control-tb.vhd
| 1 | 3,320 |
----------------------------------------------------------------------------------
-- Data de criação: 18 de setembro de 2014;
-- Module Name: Teste de interface de recepção de dados;
-- Used TAB of 4 Spaces
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity interface_tb is
end interface_tb;
architecture Behavioral of interface_tb is
----------------------------------------------
-- Constants
----------------------------------------------
constant MAIN_CLK_PER : time := 20 ns; -- 50 MHz
constant MAIN_CLK : integer := 50;
constant BAUD_RATE : integer := 9600; -- Bits per Second
constant RST_LVL : std_logic := '1'; -- Active Level of Reset
----------------------------------------------
-- Signal Declaration
----------------------------------------------
-- Clock and reset Signals
signal clk_50m : std_logic := '0';
signal rst : std_logic;
signal rx_ready_in : std_logic;
signal rx_data_in : std_logic_vector(7 downto 0);
-- componente descrito como manda o documento de arquitetura,
-- segundo fontes, caso o mapeamento das portas seja esse, funciona
-- independentemente da linguagem.
component interfaceControl is
port (
clk: in std_logic;
reset: in std_logic;
rx_data_ready: in std_logic;
rx_data: in std_logic_vector(7 downto 0);
data_a: out std_logic_vector(7 downto 0);
data_b: out std_logic_vector(7 downto 0);
operation: out std_logic_vector(7 downto 0)
);
end component;
begin
----------------------------------------------
-- Components Instantiation
----------------------------------------------
uut: component interfaceControl port map(
-- Controle
clk => clk_50m, -- seta clock para o gerado por este rtl
reset => rst, -- seta o reset para o gerado por este rtl
-- interface de entrada
rx_data_ready => rx_ready_in, -- seta o pino que anuncia a transmissão
rx_data => rx_data_in, -- seta o pino que tem os dados da transmissão
-- Saídas
data_a => open,
data_b => open,
operation => open
);
----------------------------------------------
-- Main Signals Generation
----------------------------------------------
-- gera clocl que é enviado para o modulo de interface_control
main_clock_generation : process
begin
wait for MAIN_CLK_PER / 2;
clk_50m <= not clk_50m;
end process;
envia_dados : process
variable temp : integer := 1;
begin
--verifica qual o valor de temp, pois temp define qual dado será enviado
if temp = 1 then
rx_data_in <= "00000001";
temp:= temp +1;
elsif temp = 2 then
rx_data_in <= "01000010";
temp:= temp+1;
else
rx_data_in <= "11111111";
end if;
-- atraso
wait for 100ns;
-- rx_ready_in fica com valor '1' durante tempo de um pulso de clock
rx_ready_in <= '1';
wait for MAIN_CLK_PER / 2;
rx_ready_in <= '0';
-- reinicia a variavel temp e envia um reset caso 3 dados já forem enviados
if temp = 3 then
temp := 1;
wait for 200ns;
rst <= '1';
wait for MAIN_CLK_PER /2;
rst <= '0';
end if;
end process envia_dados;
end Behavioral;
|
gpl-2.0
|
e98a99f4dba9111bf2184c5bc0db0972
| 0.535347 | 3.641364 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/usb_system/altera_merlin_slave_agent/_primary.vhd
| 1 | 6,926 |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_slave_agent is
generic(
PKT_BEGIN_BURST : integer := 81;
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_LOCK : integer := 87;
PKT_TRANS_COMPRESSED_READ: integer := 67;
PKT_TRANS_POSTED: integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H: integer := 86;
PKT_PROTECTION_L: integer := 86;
PKT_RESPONSE_STATUS_H: integer := 89;
PKT_RESPONSE_STATUS_L: integer := 88;
PKT_BURST_SIZE_H: integer := 92;
PKT_BURST_SIZE_L: integer := 90;
PKT_ORI_BURST_SIZE_L: integer := 93;
PKT_ORI_BURST_SIZE_H: integer := 95;
ST_DATA_W : integer := 96;
ST_CHANNEL_W : integer := 32;
ADDR_W : vl_notype;
AVS_DATA_W : vl_notype;
AVS_BURSTCOUNT_W: integer := 4;
PKT_SYMBOLS : vl_notype;
PREVENT_FIFO_OVERFLOW: integer := 0;
SUPPRESS_0_BYTEEN_CMD: integer := 1;
USE_READRESPONSE: integer := 0;
USE_WRITERESPONSE: integer := 0;
AVS_BE_W : vl_notype;
BURST_SIZE_W : integer := 3;
FIFO_DATA_W : vl_notype
);
port(
clk : in vl_logic;
reset : in vl_logic;
m0_address : out vl_logic_vector;
m0_burstcount : out vl_logic_vector;
m0_byteenable : out vl_logic_vector;
m0_read : out vl_logic;
m0_readdata : in vl_logic_vector;
m0_waitrequest : in vl_logic;
m0_write : out vl_logic;
m0_writedata : out vl_logic_vector;
m0_readdatavalid: in vl_logic;
m0_debugaccess : out vl_logic;
m0_lock : out vl_logic;
m0_response : in vl_logic_vector(1 downto 0);
m0_writeresponserequest: out vl_logic;
m0_writeresponsevalid: in vl_logic;
rf_source_data : out vl_logic_vector;
rf_source_valid : out vl_logic;
rf_source_startofpacket: out vl_logic;
rf_source_endofpacket: out vl_logic;
rf_source_ready : in vl_logic;
rf_sink_data : in vl_logic_vector;
rf_sink_valid : in vl_logic;
rf_sink_startofpacket: in vl_logic;
rf_sink_endofpacket: in vl_logic;
rf_sink_ready : out vl_logic;
rdata_fifo_src_data: out vl_logic_vector;
rdata_fifo_src_valid: out vl_logic;
rdata_fifo_src_ready: in vl_logic;
rdata_fifo_sink_data: in vl_logic_vector;
rdata_fifo_sink_valid: in vl_logic;
rdata_fifo_sink_ready: out vl_logic;
cp_ready : out vl_logic;
cp_valid : in vl_logic;
cp_data : in vl_logic_vector;
cp_channel : in vl_logic_vector;
cp_startofpacket: in vl_logic;
cp_endofpacket : in vl_logic;
rp_ready : in vl_logic;
rp_valid : out vl_logic;
rp_data : out vl_logic_vector;
rp_startofpacket: out vl_logic;
rp_endofpacket : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of PKT_BEGIN_BURST : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_H : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_L : constant is 1;
attribute mti_svvh_generic_type of PKT_SYMBOL_W : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTEEN_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTEEN_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_H : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_L : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_LOCK : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_COMPRESSED_READ : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_POSTED : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_WRITE : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_READ : constant is 1;
attribute mti_svvh_generic_type of PKT_SRC_ID_H : constant is 1;
attribute mti_svvh_generic_type of PKT_SRC_ID_L : constant is 1;
attribute mti_svvh_generic_type of PKT_DEST_ID_H : constant is 1;
attribute mti_svvh_generic_type of PKT_DEST_ID_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BURSTWRAP_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BURSTWRAP_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTE_CNT_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTE_CNT_L : constant is 1;
attribute mti_svvh_generic_type of PKT_PROTECTION_H : constant is 1;
attribute mti_svvh_generic_type of PKT_PROTECTION_L : constant is 1;
attribute mti_svvh_generic_type of PKT_RESPONSE_STATUS_H : constant is 1;
attribute mti_svvh_generic_type of PKT_RESPONSE_STATUS_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_SIZE_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_SIZE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ORI_BURST_SIZE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ORI_BURST_SIZE_H : constant is 1;
attribute mti_svvh_generic_type of ST_DATA_W : constant is 1;
attribute mti_svvh_generic_type of ST_CHANNEL_W : constant is 1;
attribute mti_svvh_generic_type of ADDR_W : constant is 3;
attribute mti_svvh_generic_type of AVS_DATA_W : constant is 3;
attribute mti_svvh_generic_type of AVS_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of PKT_SYMBOLS : constant is 3;
attribute mti_svvh_generic_type of PREVENT_FIFO_OVERFLOW : constant is 1;
attribute mti_svvh_generic_type of SUPPRESS_0_BYTEEN_CMD : constant is 1;
attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1;
attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1;
attribute mti_svvh_generic_type of AVS_BE_W : constant is 3;
attribute mti_svvh_generic_type of BURST_SIZE_W : constant is 1;
attribute mti_svvh_generic_type of FIFO_DATA_W : constant is 3;
end altera_merlin_slave_agent;
|
apache-2.0
|
c91d732288667ae7ad34a982691b9176
| 0.607566 | 3.435516 | false | false | false | false |
nanomolina/MIPS
|
PIPELINE/datapath_tb.vhd
| 2 | 1,600 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity datapath_tb is
end entity;
architecture TB of datapath_tb is
component datapath
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
AluSrc : in std_logic;
RegDst : in std_logic;
RegWrite : in std_logic;
Jump : in std_logic;
AluControl : in std_logic_vector(2 downto 0);
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic
);
end component;
signal MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump,
dump, reset, clk : std_logic;
signal AluControl : std_logic_vector(2 downto 0);
signal pc, instr: std_logic_vector(31 downto 0);
begin
dut : datapath port map (
MemToReg => MemToReg,
MemWrite => MemWrite,
Branch => Branch,
AluSrc => AluSrc,
RegDst => RegDst,
RegWrite => RegWrite,
Jump => Jump,
AluControl => AluControl,
dump => dump,
pc => pc,
instr => instr,
reset => reset,
clk => clk
);
process begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;
process begin
--ADD--
reset <= '1';
wait for 2 ns;
reset <= '0';
MemToReg <= '0';
MemWrite <= '0';
Branch <= '0'; --??
AluSrc <= '1';
RegDst <= '0'; --??
RegWrite <= '1';
Jump <= '1';
AluControl <= "010";
dump <= '1';
wait for 20 ns;
dump <= '0';
end process;
end TB;
|
gpl-3.0
|
5259f32f5c986018331660f78e80766c
| 0.593125 | 3.001876 | false | false | false | false |
nanomolina/MIPS
|
prueba/pipeline.vhd
| 2 | 2,231 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pipeline is
port (
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
dump : in std_logic;
reset : in std_logic;
clk : in std_logic
);
end entity;
architecture BH of pipeline is
--DECLARACION DE COMPONENTES--
component datapath
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
AluSrc : in std_logic;
RegDst : in std_logic;
RegWrite : in std_logic;
Jump : in std_logic;
AluControl : in std_logic_vector(2 downto 0);
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic
);
end component;
component controller
port (
Op: in std_logic_vector(5 downto 0);
Funct: in std_logic_vector(5 downto 0);
MemToReg: out std_logic;
MemWrite: out std_logic;
Branch: out std_logic;
AluSrc: out std_logic;
RegDst: out std_logic;
RegWrite: out std_logic;
Jump: out std_logic;
alucontrol: out std_logic_vector (2 downto 0)
);
end component;
--DECLARACION DE SEniALES--
signal MemToReg_s, MemWrite_s, Branch_s, AluSrc_s, RegDst_s, RegWrite_s, Jump_s : std_logic;
signal AluControl_s : std_logic_vector(2 downto 0);
signal Instr_s : std_logic_vector(31 downto 0);
begin
CONTROLLER1: controller port map(
Op => Instr_s(31 downto 26),
Funct => Instr_s(5 downto 0),
MemToReg => MemToReg_s,
MemWrite => MemWrite_s,
Branch => Branch_s,
AluSrc => AluSrc_s,
RegDst => RegDst_s,
RegWrite => RegWrite_s,
Jump => Jump_s,
alucontrol => AluControl_s
);
DATAPATH1: datapath port map(
MemToReg => MemToReg_s,
MemWrite => MemWrite_s,
Branch => Branch_s,
AluSrc => AluSrc_s,
RegDst => RegDst_s,
RegWrite => RegWrite_s,
Jump => Jump_s,
AluControl => AluControl_s,
dump => dump,
pc => pc,
instr => Instr_s,
reset => reset,
clk => clk
);
instr <= Instr_s; -- IMPORTANTE !!!
end BH;
|
gpl-3.0
|
2778c165f02ce37081319e54fd6a9c2c
| 0.616316 | 3.043656 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_fmc516/sys_pll.vhd
| 11 | 6,148 |
-- MMCM_BASE : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the body of the design code. The instance name
-- declaration : (MMCM_BASE_inst) and/or the port declarations after the
-- code : "=>" declaration maybe changed to properly reference and
-- : connect this function to the design. All inputs and outputs
-- : must be connected.
-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.
-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity sys_pll is
generic(
-- 200 MHz input clock
g_clkin_period : real := 5.000;
g_clkbout_mult_f : real := 5.000;
-- 100 MHz output clock
g_clk0_divide_f : real := 10.000;
-- 200 MHz output clock
g_clk1_divide : integer := 5
);
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end sys_pll;
architecture syn of sys_pll is
signal s_mmcm_fbin : std_logic;
signal s_mmcm_fbout : std_logic;
signal s_clk0 : std_logic;
signal s_clk1 : std_logic;
begin
-- MMCM_BASE: Base Mixed Mode Clock Manager
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
-- Clock PLL
cmp_mmcm : MMCM_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => g_clkbout_mult_f,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => g_clk0_divide_f,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => g_clk1_divide,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => g_clkin_period,
REF_JITTER1 => 0.010,
-- Not used. Just to bypass Xilinx errors
-- Just input g_clkin_period input clock period
CLKIN2_PERIOD => g_clkin_period,
REF_JITTER2 => 0.010
)
port map(
-- Output clocks
CLKFBOUT => s_mmcm_fbout,
CLKFBOUTB => open,
CLKOUT0 => s_clk0,
CLKOUT0B => open,
CLKOUT1 => s_clk1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => s_mmcm_fbin,
CLKIN1 => clk_i,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_o,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst_i
);
-- Global clock buffers for "cmp_mmcm" instance
cmp_clkf_bufg : BUFG
port map(
O => s_mmcm_fbin,
I => s_mmcm_fbout
);
cmp_clkout0_buf : BUFG
port map(
O => clk0_o,
I => s_clk0
);
cmp_clkout1_buf : BUFG
port map(
O => clk1_o,
I => s_clk1
);
end syn;
|
lgpl-3.0
|
a5390bcf70ad0e3ddfb61822c34a8d02
| 0.379961 | 5.183811 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module.vhd
| 2 | 41,321 |
-- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is
port (
data_out : out std_logic_vector(23 downto 0); -- data_out.wire
write : in std_logic := '0'; -- write.wire
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire
sop : in std_logic := '0'; -- sop.wire
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- addr.wire
eop : in std_logic := '0'; -- eop.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0' -- .reset
);
end entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module;
architecture rtl of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNLF52SJQ3 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLF52SJQ3;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_multiplexer_GNCALBUTDR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNCALBUTDR;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module is
port (
data_out : out std_logic_vector(23 downto 0); -- wire
data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
thr : in std_logic_vector(7 downto 0) := (others => 'X') -- wire
);
end component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_port_GN6TDLHAW6 is
port (
input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_port_GN6TDLHAW6;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
component alt_dspbuilder_if_statement_GN7VA7SRUP is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GN7VA7SRUP;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
data_out : out std_logic_vector(23 downto 0) -- wire
);
end component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module;
component alt_dspbuilder_decoder_GNEQGKKPXW is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNEQGKKPXW;
component alt_dspbuilder_cast_GNZ5LMFB5D is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNZ5LMFB5D;
component alt_dspbuilder_cast_GNSB3OXIQS is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_cast_GNSB3OXIQS;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal decoder2sclrgnd_output_wire : std_logic; -- Decoder2sclrGND:output -> Decoder2:sclr
signal decoder2enavcc_output_wire : std_logic; -- Decoder2enaVCC:output -> Decoder2:ena
signal decoder3sclrgnd_output_wire : std_logic; -- Decoder3sclrGND:output -> Decoder3:sclr
signal decoder3enavcc_output_wire : std_logic; -- Decoder3enaVCC:output -> Decoder3:ena
signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr
signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena
signal delay6sclrgnd_output_wire : std_logic; -- Delay6sclrGND:output -> Delay6:sclr
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr
signal delay4enavcc_output_wire : std_logic; -- Delay4enaVCC:output -> Delay4:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr
signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr
signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena
signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> [Bus_Conversion1:input, Bus_Conversion6:input]
signal addr_0_output_wire : std_logic_vector(1 downto 0); -- addr_0:output -> [Decoder2:data, Decoder:data]
signal bus_conversion1_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion1:output -> Delay2:input
signal delay2_output_wire : std_logic_vector(7 downto 0); -- Delay2:output -> Delay3:input
signal delay3_output_wire : std_logic_vector(7 downto 0); -- Delay3:output -> Gray_Binarization_Gray_Binarization_Module_Binarization_Module_0:thr
signal delay4_output_wire : std_logic_vector(0 downto 0); -- Delay4:output -> [Delay:input, cast2:input]
signal bus_conversion6_output_wire : std_logic_vector(0 downto 0); -- Bus_Conversion6:output -> Delay5:input
signal delay5_output_wire : std_logic_vector(0 downto 0); -- Delay5:output -> Delay6:input
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Decoder1:data, Decoder3:data, Gray_Binarization_Gray_Binarization_Module_Gray_Module_0:data_in, If_Statement1:a, Multiplexer:in0]
signal gray_binarization_gray_binarization_module_gray_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Gray_Binarization_Gray_Binarization_Module_Gray_Module_0:data_out -> [Gray_Binarization_Gray_Binarization_Module_Binarization_Module_0:data_in, Multiplexer2:in0]
signal constant3_output_wire : std_logic_vector(23 downto 0); -- Constant3:output -> If_Statement1:b
signal constant4_output_wire : std_logic_vector(23 downto 0); -- Constant4:output -> If_Statement1:c
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Logical_Bit_Operator:data0
signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator3:data0, Logical_Bit_Operator5:data0, Logical_Bit_Operator:data1]
signal eop_0_output_wire : std_logic; -- eop_0:output -> Logical_Bit_Operator1:data0
signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator2:data0
signal write_0_output_wire : std_logic; -- write_0:output -> [Logical_Bit_Operator2:data1, Logical_Bit_Operator4:data1]
signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> Delay2:ena
signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay3:ena
signal decoder2_dec_wire : std_logic; -- Decoder2:dec -> Logical_Bit_Operator4:data0
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Delay5:ena
signal decoder3_dec_wire : std_logic; -- Decoder3:dec -> Logical_Bit_Operator5:data1
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> Delay6:ena
signal delay_output_wire : std_logic_vector(0 downto 0); -- Delay:output -> [Multiplexer:sel, cast4:input]
signal delay6_output_wire : std_logic_vector(0 downto 0); -- Delay6:output -> Multiplexer2:sel
signal gray_binarization_gray_binarization_module_binarization_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Gray_Binarization_Gray_Binarization_Module_Binarization_Module_0:data_out -> Multiplexer2:in1
signal multiplexer2_result_wire : std_logic_vector(23 downto 0); -- Multiplexer2:result -> Multiplexer:in1
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> data_out_0:input
signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> cast1:input
signal cast1_output_wire : std_logic; -- cast1:output -> Delay:sclr
signal cast2_output_wire : std_logic; -- cast2:output -> Delay:ena
signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> cast3:input
signal cast3_output_wire : std_logic_vector(0 downto 0); -- cast3:output -> Delay4:input
signal cast4_output_wire : std_logic; -- cast4:output -> Logical_Bit_Operator1:data1
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> cast5:input
signal cast5_output_wire : std_logic_vector(0 downto 0); -- cast5:output -> Delay1:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Decoder1:aclr, Decoder2:aclr, Decoder3:aclr, Decoder:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay4:aclr, Delay5:aclr, Delay6:aclr, Delay:aclr, Gray_Binarization_Gray_Binarization_Module_Binarization_Module_0:aclr, Gray_Binarization_Gray_Binarization_Module_Gray_Module_0:aclr, Multiplexer2:aclr, Multiplexer:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Decoder1:clock, Decoder2:clock, Decoder3:clock, Decoder:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay4:clock, Delay5:clock, Delay6:clock, Delay:clock, Gray_Binarization_Gray_Binarization_Module_Binarization_Module_0:Clock, Gray_Binarization_Gray_Binarization_Module_Gray_Module_0:Clock, Multiplexer2:clock, Multiplexer:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GNLF52SJQ3
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => writedata, -- input.wire
output => writedata_0_output_wire -- output.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => delay_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => data_in_0_output_wire, -- in0.wire
in1 => multiplexer2_result_wire -- in1.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
gray_binarization_gray_binarization_module_binarization_module_0 : component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module
port map (
data_out => gray_binarization_gray_binarization_module_binarization_module_0_data_out_wire, -- data_out.wire
data_in => gray_binarization_gray_binarization_module_gray_module_0_data_out_wire, -- data_in.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
thr => delay3_output_wire -- thr.wire
);
constant4 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant4_output_wire -- output.wire
);
addr_0 : component alt_dspbuilder_port_GN6TDLHAW6
port map (
input => addr, -- input.wire
output => addr_0_output_wire -- output.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder3_dec_wire -- data1.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => decoder2_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
constant3 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant3_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => delay4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => cast1_output_wire, -- sclr.wire
ena => cast2_output_wire -- ena.wire
);
write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => write, -- input.wire
output => write_0_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder1_dec_wire -- data1.wire
);
logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator2_result_wire, -- result.wire
data0 => decoder_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => eop, -- input.wire
output => eop_0_output_wire -- output.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => eop_0_output_wire, -- data0.wire
data1 => cast4_output_wire -- data1.wire
);
decoder2 : component alt_dspbuilder_decoder_GNM4LOIHXZ
generic map (
decode => "01",
pipeline => 1,
width => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder2_dec_wire, -- dec.wire
sclr => decoder2sclrgnd_output_wire, -- sclr.wire
ena => decoder2enavcc_output_wire -- ena.wire
);
decoder2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder2sclrgnd_output_wire -- output.wire
);
decoder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder2enavcc_output_wire -- output.wire
);
decoder3 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_in_0_output_wire, -- data.wire
dec => decoder3_dec_wire, -- dec.wire
sclr => decoder3sclrgnd_output_wire, -- sclr.wire
ena => decoder3enavcc_output_wire -- ena.wire
);
decoder3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder3sclrgnd_output_wire -- output.wire
);
decoder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder3enavcc_output_wire -- output.wire
);
decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_in_0_output_wire, -- data.wire
dec => decoder1_dec_wire, -- dec.wire
sclr => decoder1sclrgnd_output_wire, -- sclr.wire
ena => decoder1enavcc_output_wire -- ena.wire
);
decoder1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder1sclrgnd_output_wire -- output.wire
);
decoder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder1enavcc_output_wire -- output.wire
);
logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator_result_wire, -- result.wire
data0 => if_statement1_true_wire, -- data0.wire
data1 => sop_0_output_wire -- data1.wire
);
delay6 : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => delay5_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay6_output_wire, -- output.wire
sclr => delay6sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator5_result_wire -- ena.wire
);
delay6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay6sclrgnd_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => bus_conversion6_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator4_result_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay4 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay4_output_wire, -- output.wire
sclr => delay4sclrgnd_output_wire, -- sclr.wire
ena => delay4enavcc_output_wire -- ena.wire
);
delay4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay4sclrgnd_output_wire -- output.wire
);
delay4enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay4enavcc_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNVTJPHWYT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "01111111",
width => 8
)
port map (
input => delay2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator3_result_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GN7VA7SRUP
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) and (a /= c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => data_in_0_output_wire, -- a.wire
b => constant3_output_wire, -- b.wire
c => constant4_output_wire -- c.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNHYCSAEGT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "0",
width => 1
)
port map (
input => cast5_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
multiplexer2 : component alt_dspbuilder_multiplexer_GNCALBUTDR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => delay6_output_wire, -- sel.wire
result => multiplexer2_result_wire, -- result.wire
ena => multiplexer2enavcc_output_wire, -- ena.wire
user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire
in0 => gray_binarization_gray_binarization_module_gray_module_0_data_out_wire, -- in0.wire
in1 => gray_binarization_gray_binarization_module_binarization_module_0_data_out_wire -- in1.wire
);
multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer2user_aclrgnd_output_wire -- output.wire
);
multiplexer2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer2enavcc_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNVTJPHWYT
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "01111111",
width => 8
)
port map (
input => bus_conversion1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator2_result_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => multiplexer_result_wire, -- input.wire
output => data_out -- output.wire
);
gray_binarization_gray_binarization_module_gray_module_0 : component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module
port map (
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
data_in => data_in_0_output_wire, -- data_in.wire
data_out => gray_binarization_gray_binarization_module_gray_module_0_data_out_wire -- data_out.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
decoder : component alt_dspbuilder_decoder_GNEQGKKPXW
generic map (
decode => "10",
pipeline => 1,
width => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder_dec_wire, -- dec.wire
sclr => decodersclrgnd_output_wire, -- sclr.wire
ena => decoderenavcc_output_wire -- ena.wire
);
decodersclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decodersclrgnd_output_wire -- output.wire
);
decoderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoderenavcc_output_wire -- output.wire
);
bus_conversion6 : component alt_dspbuilder_cast_GNZ5LMFB5D
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion6_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay4_output_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator_result_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
cast4 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay_output_wire, -- input.wire
output => cast4_output_wire -- output.wire
);
cast5 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator1_result_wire, -- input.wire
output => cast5_output_wire -- output.wire
);
end architecture rtl; -- of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module
|
mit
|
f08dfa10ee1a972d074b1f0b42646595
| 0.530215 | 3.669064 | false | false | false | false |
nanomolina/MIPS
|
prueba/sign.vhd
| 3 | 526 |
library ieee;
use ieee.std_logic_1164.all;
entity sign is
port(a: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of sign is
begin
process (a)
variable v : std_logic_vector(15 downto 0);
begin
if (a(0)='1') then
v := (others => '1');
y <= (a & v);
elsif (a(0)='0') then
v := (others => '0');
y <= (a & v);
end if;
end process;
end architecture;
|
gpl-3.0
|
49fbd2de93239d18e255a06c8ff91d47
| 0.498099 | 3.483444 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/db/alt_dspbuilder_delay.vhd
| 2 | 3,978 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic := '0'
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(8-1 downto 0) := (others=>'0');
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
begin
alt_dspbuilder_delay_GNUECIBFDH_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNUECIBFDH_0: alt_dspbuilder_delay_GNUECIBFDH
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNHYCSAEGT_1: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNHYCSAEGT_1: alt_dspbuilder_delay_GNHYCSAEGT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNVTJPHWYT_2: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_2: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
0a0d25807056d53339c045e111dc5eab
| 0.643539 | 3.124902 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/pcie/top_afcv3.vhd
| 2 | 8,547 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
use work.ipcores_pkg.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
generic (
SIMULATION : string := "FALSE"
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(C_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(C_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(C_DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(C_DDR_CKE_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(C_DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(C_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(c_pcielanes-1 downto 0);
pci_exp_rxn : in std_logic_vector(c_pcielanes-1 downto 0);
pci_exp_txp : out std_logic_vector(c_pcielanes-1 downto 0);
pci_exp_txn : out std_logic_vector(c_pcielanes-1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic;
ddr_sys_clk_n : in std_logic;
pci_sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
pci_sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic
);
end entity top;
architecture arch of top is
signal ddr_sys_clk_i : std_logic;
signal ddr_sys_rst_i : std_logic;
signal ddr_axi_aclk_o : std_logic;
signal sys_rst_n_c : std_logic;
signal pll_clkin : std_logic;
signal pll_clkfbout : std_logic;
signal pll_clkout0 : std_logic;
signal pll_locked : std_logic;
signal wbone_clk : std_logic;
signal wbone_addr : std_logic_vector(31 downto 0);
signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_we : std_logic;
signal wbone_sel : std_logic_vector(0 downto 0);
signal wbone_stb : std_logic;
signal wbone_ack : std_logic;
signal wbone_cyc : std_logic;
signal wbone_rst : std_logic;
begin
bpm_pcie_i: entity work.bpm_pcie
generic map(
SIMULATION => SIMULATION
)
port map(
--DDR3 memory pins
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
-- PCIe transceivers
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- Necessity signals
ddr_sys_clk => ddr_sys_clk_i,
ddr_sys_rst => ddr_sys_rst_i,
pci_sys_clk_p => pci_sys_clk_p,
pci_sys_clk_n => pci_sys_clk_n,
pci_sys_rst_n => sys_rst_n_c,
-- DDR memory controller AXI4 interface --
-- Slave interface clock
ddr_axi_aclk_o => ddr_axi_aclk_o,
ddr_axi_aresetn_o => open,
-- Slave Interface Write Address Ports
ddr_axi_awid => (others => '0'),
ddr_axi_awaddr => (others => '0'),
ddr_axi_awlen => (others => '0'),
ddr_axi_awsize => (others => '0'),
ddr_axi_awburst => (others => '0'),
ddr_axi_awlock => '0',
ddr_axi_awcache => (others => '0'),
ddr_axi_awprot => (others => '0'),
ddr_axi_awqos => (others => '0'),
ddr_axi_awvalid => '0',
ddr_axi_awready => open,
-- Slave Interface Write Data Ports
ddr_axi_wdata => (others => '0'),
ddr_axi_wstrb => (others => '0'),
ddr_axi_wlast => '0',
ddr_axi_wvalid => '0',
ddr_axi_wready => open,
-- Slave Interface Write Response Ports
ddr_axi_bid => open,
ddr_axi_bresp => open,
ddr_axi_bvalid => open,
ddr_axi_bready => '1',
-- Slave Interface Read Address Ports
ddr_axi_arid => (others => '0'),
ddr_axi_araddr => (others => '0'),
ddr_axi_arlen => (others => '0'),
ddr_axi_arsize => (others => '0'),
ddr_axi_arburst => (others => '0'),
ddr_axi_arlock => '0',
ddr_axi_arcache => (others => '0'),
ddr_axi_arprot => (others => '0'),
ddr_axi_arqos => (others => '0'),
ddr_axi_arvalid => '0',
ddr_axi_arready => open,
-- Slave Interface Read Data Ports
ddr_axi_rid => open,
ddr_axi_rdata => open,
ddr_axi_rresp => open,
ddr_axi_rlast => open,
ddr_axi_rvalid => open,
ddr_axi_rready => '1',
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I => wbone_clk,
RST_I => wbone_rst,
ACK_I => wbone_ack,
DAT_I => wbone_mdin,
ADDR_O => wbone_addr(28 downto 0),
DAT_O => wbone_mdout,
WE_O => wbone_we,
STB_O => wbone_stb,
SEL_O => wbone_sel(0),
CYC_O => wbone_cyc,
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o => wbone_rst
);
Wishbone_mem_large: if (SIMULATION = "TRUE") generate
wb_mem_sim :
entity work.wb_mem
generic map(
AWIDTH => 16,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
Wishbone_mem_sample: if (SIMULATION = "FALSE") generate
wb_mem_syn :
entity work.wb_mem
generic map(
AWIDTH => 7,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
--temporary clock assignment
wbone_clk <= pll_clkin;
sys_reset_n_ibuf : IBUF
port map (
O => sys_rst_n_c,
I => sys_rst_n
);
ddr_inclk_buf : IBUFGDS
generic map(
IBUF_LOW_PWR => false
)
port map
(o => pll_clkin,
i => ddr_sys_clk_p,
ib => ddr_sys_clk_n
);
plle2_adv_inst : PLLE2_ADV
generic map
(bandwidth => "high",
compensation => "zhold",
divclk_divide => 5,
clkfbout_mult => 64,
clkfbout_phase => 0.000,
clkout0_divide => 8,
clkout0_phase => 0.000,
clkout0_duty_cycle => 0.500,
clkin1_period => 8.000,
ref_jitter1 => 0.010)
port map
-- output clocks
(clkfbout => pll_clkfbout,
clkout0 => pll_clkout0,
clkout1 => open,
clkout2 => open,
clkout3 => open,
clkout4 => open,
clkout5 => open,
-- input clock control
clkfbin => pll_clkfbout,
clkin1 => pll_clkin,
clkin2 => '0',
-- tied to always select the primary input clock
clkinsel => '1',
-- ports for dynamic reconfiguration
daddr => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Other control and status signals
LOCKED => pll_locked,
PWRDWN => '0',
RST => '0');
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => ddr_sys_clk_i,
I => pll_clkout0
);
ddr_sys_rst_i <= not(pll_locked);
end architecture;
|
lgpl-3.0
|
167e27199c361775cd9a8a3af38fadf1
| 0.551305 | 3.095618 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/rtl_work/ball/_primary.vhd
| 1 | 2,298 |
library verilog;
use verilog.vl_types.all;
entity ball is
generic(
Ball_X_Center : vl_logic_vector(9 downto 0) := (Hi0, Hi1, Hi0, Hi1, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
Ball_X_Right : vl_logic_vector(9 downto 0) := (Hi0, Hi1, Hi1, Hi0, Hi0, Hi1, Hi0, Hi0, Hi0, Hi0);
Ball_X_Left : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi1, Hi1, Hi1, Hi1, Hi0, Hi0, Hi0, Hi0);
Ball_Y_Center : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi1, Hi1, Hi1, Hi1, Hi0, Hi0, Hi0, Hi0);
Ball_X_Min : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
Ball_X_Max : vl_logic_vector(9 downto 0) := (Hi1, Hi0, Hi0, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1);
Ball_Y_Min : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
Ball_Y_Max : vl_logic_vector(9 downto 0) := (Hi0, Hi1, Hi1, Hi1, Hi0, Hi1, Hi1, Hi1, Hi1, Hi1);
Ball_X_Step : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1);
Ball_Y_Step : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1)
);
port(
Reset : in vl_logic;
frame_clk : in vl_logic;
keycode : in vl_logic_vector(7 downto 0);
color : in vl_logic;
BallX : out vl_logic_vector(9 downto 0);
BallY : out vl_logic_vector(9 downto 0);
BallS : out vl_logic_vector(9 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of Ball_X_Center : constant is 2;
attribute mti_svvh_generic_type of Ball_X_Right : constant is 2;
attribute mti_svvh_generic_type of Ball_X_Left : constant is 2;
attribute mti_svvh_generic_type of Ball_Y_Center : constant is 2;
attribute mti_svvh_generic_type of Ball_X_Min : constant is 2;
attribute mti_svvh_generic_type of Ball_X_Max : constant is 2;
attribute mti_svvh_generic_type of Ball_Y_Min : constant is 2;
attribute mti_svvh_generic_type of Ball_Y_Max : constant is 2;
attribute mti_svvh_generic_type of Ball_X_Step : constant is 2;
attribute mti_svvh_generic_type of Ball_Y_Step : constant is 2;
end ball;
|
apache-2.0
|
629522937b634be588e2cc692b71a576
| 0.588338 | 2.735714 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/testbench/downconversion/downconv_bench.vhd
| 1 | 6,318 |
-------------------------------------------------------------------------------
-- Title : Downconverter testbench
-- Project :
-------------------------------------------------------------------------------
-- File : downconv_bench.vhd
-- Author : Gustavo BM Bruno
-- Company : LNLS
-- Created : 2014-04-16
-- Last update: 2014-06-05
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Tests the downconversion integration.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-04-16 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity downconv_bench is
end downconv_bench;
architecture test of downconv_bench is
constant c_input_freq : real := 120.0e6;
constant clock_period : time := 1.0 sec / (2.0 * c_input_freq);
-- Bus widths
constant c_input_width : natural := 24;
constant c_mixed_width : natural := 24;
constant c_output_width : natural := 32;
constant c_phase_width : natural := 8;
-- Mixer parameters
constant c_sin_file : string := "./dds_sin.nif";
constant c_cos_file : string := "./dds_cos.nif";
constant c_number_of_points : natural := 6;
-- CIC parameters
constant c_diff_delay : natural := 2;
constant c_stages : natural := 3;
constant c_decimation_rate : natural := 1000;
constant c_bus_width : natural := natural(ceil(log2(real(c_decimation_rate))));
-- Signals
signal clock : std_logic := '0';
signal adc_data : std_logic_vector(c_input_width-1 downto 0) := (others => '0');
signal endoffile : bit := '0';
signal reset : std_logic := '1';
signal ce : std_logic;
signal I_out : std_logic_vector(c_output_width-1 downto 0);
signal Q_out : std_logic_vector(c_output_width-1 downto 0);
signal cic_valid : std_logic;
component downconv is
generic (
g_input_width : natural;
g_mixed_width : natural;
g_output_width : natural;
g_phase_width : natural;
g_sin_file : string;
g_cos_file : string;
g_number_of_points : natural;
g_diff_delay : natural;
g_stages : natural;
g_decimation_rate : natural);
port (
signal_i : in std_logic_vector(g_input_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
phase_i : in std_logic_vector(g_phase_width-1 downto 0);
I_o : out std_logic_vector(g_output_width-1 downto 0);
Q_o : out std_logic_vector(g_output_width-1 downto 0);
valid_o : out std_logic);
end component downconv;
component strobe_gen is
generic (
g_maxrate : natural;
g_bus_width : natural);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
ratio_i : in std_logic_vector(g_bus_width-1 downto 0);
strobe_o : out std_logic);
end component strobe_gen;
begin
clk_gen : process
begin
clock <= '0';
wait for clock_period;
clock <= '1';
wait for clock_period;
end process;
strobe_gen_1 : strobe_gen
generic map (
g_maxrate => 2,
g_bus_width => 2)
port map (
clk_i => clock,
rst_i => '0',
ce_i => '1',
ratio_i => std_logic_vector(to_unsigned(2, 2)),
strobe_o => ce);
rst_gen : process(clock)
variable clock_count : natural := 10;
begin
if rising_edge(clock) then
if clock_count /= 0 then
clock_count := clock_count - 1;
else
reset <= '0';
end if;
end if;
end process;
adc_read : process(clock)
file adc_file : text open read_mode is "downconv.samples";
variable cur_line : line;
variable datain : real;
begin
if rising_edge(clock) and reset = '0' then
if ce = '1' then
if not endfile(adc_file) then
readline(adc_file, cur_line);
read(cur_line, datain);
adc_data <= std_logic_vector(to_signed(integer(datain*real(2**(c_input_width-1))), c_input_width));
else
endoffile <= '1';
end if;
end if;
end if;
end process adc_read;
uut : downconv
generic map (
g_input_width => c_input_width,
g_mixed_width => c_mixed_width,
g_output_width => c_output_width,
g_phase_width => c_phase_width,
g_sin_file => c_sin_file,
g_cos_file => c_cos_file,
g_number_of_points => c_number_of_points,
g_diff_delay => c_diff_delay,
g_stages => c_stages,
g_decimation_rate => c_decimation_rate)
port map (
signal_i => adc_data,
clk_i => clock,
ce_i => ce,
rst_i => reset,
phase_i => std_logic_vector(to_unsigned(0, c_phase_width)),
I_o => I_out,
Q_o => Q_out,
valid_o => cic_valid);
signal_write : process(reset, clock)
file downconv_file : text open write_mode is "downconv_out.samples";
variable cur_line : line;
variable I, Q, mag, phase : integer;
begin
--put a header when simulation starts
if falling_edge(reset) then
write(cur_line, string'("I"));
write(cur_line, ht);
write(cur_line, string'("Q"));
write(cur_line, ht);
end if;
if rising_edge(clock) then
if(endoffile = '0') then
if(cic_valid = '1') then
I := to_integer(signed(I_out));
write(cur_line, I);
Q := to_integer(signed(Q_out));
write(cur_line, ht);
write(cur_line, Q);
writeline(downconv_file, cur_line);
end if;
else
assert (false) report "Input file finished." severity failure;
end if;
end if;
end process;
end test;
|
lgpl-3.0
|
24385e7c5283056650cb1fe3f1a2a4e6
| 0.52026 | 3.567476 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd
| 1 | 29,322 |
-- Simple DBE simple design
-- Created by Lucas Russo <[email protected]>
-- Date: 11/10/2012
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_simple_top is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- FMC150 pins
-----------------------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_simple_top;
architecture rtl of dbe_bpm_simple_top is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 7; -- LED, Button, Dual-port memory, UART, DMA control port, FMC150
-- Number of masters
constant c_masters : natural := 4; -- LM32 master. Data + Instruction, DMA read+write master
--constant c_dpram_size : natural := 16384; -- in 32-bit words (64KB)
constant c_dpram_size : natural := 22528; -- in 32-bit words (64KB)
-- Number of source/sink Wishbone stream components
constant c_sinks : natural := 1;
constant c_sources : natural := c_sinks;
-- GPIO num pins
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 64KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(c_xwb_dma_sdb, x"20000400"), -- DMA control port
3 => f_sdb_embed_device(c_xwb_fmc150_sdb, x"20000500"), -- FMC control port
4 => f_sdb_embed_device(c_xwb_uart_sdb, x"20000600"), -- UART control port
5 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000700"), -- GPIO LED
6 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000800") -- GPIO Button
--7 => f_sdb_embed_device(c_xwb_irqmngr_sdb, x"20000900") -- IRQ_MNGR
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well.
constant c_sdb_address : t_wishbone_address := x"20000000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- Wishbone Stream source/sinks arrays
signal wbs_src_i : t_wbs_source_in_array(c_sources-1 downto 0);
signal wbs_src_o : t_wbs_source_out_array(c_sources-1 downto 0);
-- Check the use of this kind of alias
alias wbs_sink_i is wbs_src_o;
alias wbs_sink_o is wbs_src_i;
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_adc_rstn : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_adc_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_adc : std_logic;
signal rst_button_sys_n : std_logic;
signal rst_button_adc_n : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(1 downto 0);
signal reset_rstn : std_logic_vector(1 downto 0);
-- 200 Mhz clocck for iodelatctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal s_leds : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- IRQ manager signals
--signal gpio_slave_irqmngr_o : t_wishbone_slave_out;
--signal gpio_slave_irqmngr_i : t_wishbone_slave_in;
-- LEDS, button and irq manager signals
--signal r_leds : std_logic_vector(7 downto 0);
--signal r_reset : std_logic;
-- Counter signal
signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
constant s_counter_full : integer := 100000000;
-- FMC150 signals
signal clk_adc : std_logic;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
component chipscope_icon_2_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
-- Is this a safe approach to ADC reset domain?
cmp_reset : gc_reset
generic map(
g_clocks => 2 -- CLK_SYS + CLK_ADC
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Detect button positive edge of clk_adc
cmp_button_adc_ffs : gc_sync_ffs
port map (
clk_i => clk_adc,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_adc_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_adc_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_adc,
rst_n_i => '1',
pulse_i => rst_button_adc_pp,
extended_o => rst_button_adc
);
rst_button_sys_n <= not rst_button_sys;
rst_button_adc_n <= not rst_button_adc;
reset_clks(0) <= clk_sys;
reset_clks(1) <= clk_adc;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_adc_rstn <= reset_rstn(1) and rst_button_adc_n;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => false, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
cmp_lm32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug"
) -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(0), -- Data bus
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1), -- Instruction bus
iwb_i => cbar_slave_o(1)
);
-- Interrupts 31 downto 1 disabled for now.
-- Interrupt '0' is DMA completion.
lm32_interrupt(31 downto 1) <= (others => '0');
-- A DMA controller is master 2+3, slave 2, and interrupt 0
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(2),
slave_o => cbar_master_i(2),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => lm32_interrupt(0)
);
-- Slave 0+1 is the RAM. Load a input file containing a simple led blink program!
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
g_init_file => "../../../embedded-sw/dbe.ram",--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
--slave2_i => cc_dummy_slave_in, -- CYC always low
--slave2_o => open
);
-- Slave 3 is the FMC150 interface
cmp_xwb_fmc150 : xwb_fmc150
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE
--g_packet_size => 32,
--g_sim => 0
)
port map(
rst_n_i => clk_sys_rstn,
clk_sys_i => clk_sys,
--clk_100Mhz_i : in std_logic;
clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => cbar_master_o(3),
wb_slv_o => cbar_master_i(3),
-----------------------------
-- Simulation Only ports!
-----------------------------
sim_adc_clk_i => '0',
sim_adc_clk2x_i => '0',
sim_adc_cha_data_i => f_zeros(14),
sim_adc_chb_data_i => f_zeros(14),
sim_adc_data_valid => '0',
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i => adc_clk_ab_p_i,
adc_clk_ab_n_i => adc_clk_ab_n_i,
adc_cha_p_i => adc_cha_p_i,
adc_cha_n_i => adc_cha_n_i,
adc_chb_p_i => adc_chb_p_i,
adc_chb_n_i => adc_chb_n_i,
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o => dac_dclk_p_o,
dac_dclk_n_o => dac_dclk_n_o,
dac_data_p_o => dac_data_p_o,
dac_data_n_o => dac_data_n_o,
dac_frame_p_o => dac_frame_p_o,
dac_frame_n_o => dac_frame_n_o,
txenable_o => txenable_o,
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o => spi_sclk_o, -- Shared SPI clock line
spi_sdata_o => spi_sdata_o,-- Shared SPI data line
-- ADC specific signals
adc_n_en_o => adc_n_en_o, -- SPI chip select
adc_sdo_i => adc_sdo_i, -- SPI data out
adc_reset_o => adc_reset_o,-- SPI reset
-- CDCE specific signals
cdce_n_en_o => cdce_n_en_o, -- SPI chip select
cdce_sdo_i => cdce_sdo_i, -- SPI data out
cdce_n_reset_o => cdce_n_reset_o,
cdce_n_pd_o => cdce_n_pd_o,
cdce_ref_en_o => cdce_ref_en_o,
cdce_pll_status_i => cdce_pll_status_i,
-- DAC specific signals
dac_n_en_o => dac_n_en_o, -- SPI chip select
dac_sdo_i => dac_sdo_i, -- SPI data out
-- Monitoring specific signals
mon_n_en_o => mon_n_en_o, -- SPI chip select
mon_sdo_i => mon_sdo_i, -- SPI data out
mon_n_reset_o => mon_n_reset_o,
mon_n_int_i => mon_n_int_i,
--FMC Present status
prsnt_m2c_l_i => prsnt_m2c_l_i,
-- ADC output signals
-- ADC data is interfaced through the wishbone stream interface (wbs_src_o)
adc_dout_o => open,
clk_adc_o => clk_adc,
-- Wishbone Streaming Interface Source
wbs_source_i => wbs_src_i(0),
wbs_source_o => wbs_src_o(0)
);
-- Slave 4 is the UART
cmp_uart : xwb_simple_uart
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map (
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(4),
slave_o => cbar_master_i(4),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o
);
-- Slave 5 is the example LED driver
cmp_leds : xwb_gpio_port
generic map(
--g_interface_mode => CLASSIC;
g_address_granularity => BYTE,
g_num_pins => c_leds_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(5),
slave_o => cbar_master_i(5),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => s_leds,
--gpio_out_o => open,
gpio_in_i => s_leds,
gpio_oen_o => open
);
leds_o <= s_leds;
--p_test_leds : process (clk_adc)
--begin
-- if rising_edge(clk_adc) then
-- if clk_adc_rstn = '0' then
-- s_counter <= (others => '0');
-- s_leds <= x"55";
-- else
-- if (s_counter = s_counter_full-1) then
-- s_counter <= (others => '0');
-- s_leds <= s_leds(c_leds_num_pins-2 downto 0) & s_leds(c_leds_num_pins-1);
-- else
-- s_counter <= s_counter + 1;
-- end if;
-- end if;
-- end if;
--end process;
-- Slave 1 is the example LED driver
--gpio_slave_led_i <= cbar_master_o(1);
--cbar_master_i(1) <= gpio_slave_led_o;
--leds_o <= not r_leds;
-- There is a tool called 'wbgen2' which can autogenerate a Wishbone
-- interface and C header file, but this is a simple example.
--gpio : process(clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- It is vitally important that for each occurance of
-- (cyc and stb and not stall) there is (ack or rty or err)
-- sometime later on the bus.
--
-- This is an easy solution for a device that never stalls:
-- gpio_slave_led_o.ack <= gpio_slave_led_i.cyc and gpio_slave_led_i.stb;
-- Detect a write to the register byte
-- if gpio_slave_led_i.cyc = '1' and gpio_slave_led_i.stb = '1' and
-- gpio_slave_led_i.we = '1' and gpio_slave_led_i.sel(0) = '1' then
-- Register 0x0 = LEDs, 0x4 = CPU reset
-- if gpio_slave_led_i.adr(2) = '0' then
-- r_leds <= gpio_slave_led_i.dat(7 downto 0);
-- else
-- r_reset <= gpio_slave_led_i.dat(0);
-- end if;
-- end if;
-- Read to the register byte
-- if gpio_slave_led_i.adr(2) = '0' then
-- gpio_slave_led_o.dat(31 downto 8) <= (others => '0');
-- gpio_slave_led_o.dat(7 downto 0) <= r_leds;
-- else
-- gpio_slave_led_o.dat(31 downto 2) <= (others => '0');
-- gpio_slave_led_o.dat(0) <= r_reset;
-- end if;
--end if;
--end process;
--gpio_slave_led_o.int <= '0';
--gpio_slave_led_o.err <= '0';
--gpio_slave_led_o.rty <= '0';
--gpio_slave_led_o.stall <= '0'; -- This simple example is always ready
-- Slave 6 is the example Button driver
cmp_buttons : xwb_gpio_port
generic map(
--g_interface_mode => CLASSIC;
g_address_granularity => BYTE,
g_num_pins => c_buttons_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(6),
slave_o => cbar_master_i(6),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => open,
gpio_in_i => buttons_i,
gpio_oen_o => open
);
-- Xilinx Chipscope
cmp_chipscope_icon_0 : chipscope_icon_2_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1
);
cmp_chipscope_ila_0 : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_sys,
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- FMC150 master output (slave input) control data
TRIG_ILA0_0 <= cbar_master_o(3).dat;
-- FMC150 master input (slave output) control data
TRIG_ILA0_1 <= cbar_master_i(3).dat;
-- FMC150 master control output (slave input) control signals
-- Partial decoding. Thus, only the LSB part of address matters to
-- a specific slave core
TRIG_ILA0_2(16 downto 0) <= cbar_master_o(3).cyc &
cbar_master_o(3).stb &
cbar_master_o(3).adr(9 downto 0) &
cbar_master_o(3).sel &
cbar_master_o(3).we;
--TRIG_ILA0_2(31 downto 11) <= (others => '0');
TRIG_ILA0_2(31 downto 17) <= (others => '0');
-- FMC150 master control input (slave output) control signals
TRIG_ILA0_3(4 downto 0) <= cbar_master_i(3).ack &
cbar_master_i(3).err &
cbar_master_i(3).rty &
cbar_master_i(3).stall &
cbar_master_i(3).int;
TRIG_ILA0_3(31 downto 5) <= (others => '0');
cmp_chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL1,
CLK => clk_adc,
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3
);
-- FMC150 source output (sink input) stream data
TRIG_ILA1_0 <= wbs_src_o(0).dat;
-- FMC150 source input (sink output) stream data
--TRIG_ILA1_1 <= wbs_src_i(0).dat;
-- FMC150 source control output (sink input) stream signals
-- Partial decoding. Thus, only the LSB part of address matters to
-- a specific slave core
TRIG_ILA1_1(10 downto 0) <= wbs_src_o(0).cyc &
wbs_src_o(0).stb &
wbs_src_o(0).adr(3 downto 0) &
wbs_src_o(0).sel &
wbs_src_o(0).we;
TRIG_ILA1_1(31 downto 11) <= (others => '0');
-- FMC150 master control input (slave output) stream signals
TRIG_ILA1_2(3 downto 0) <= wbs_src_i(0).ack &
wbs_src_i(0).err &
wbs_src_i(0).rty &
wbs_src_i(0).stall;
TRIG_ILA1_2(31 downto 4) <= (others => '0');
TRIG_ILA1_3(31 downto 0) <= (others => '0');
end rtl;
|
lgpl-3.0
|
e6b45ba4c53b3a933a2901ad0604ed9d
| 0.462383 | 3.601769 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/statements/SimpleIfStatementMergable2.vhd
| 1 | 659 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY SimpleIfStatementMergable2 IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
d : OUT STD_LOGIC;
e : OUT STD_LOGIC;
f : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleIfStatementMergable2 IS
BEGIN
assig_process_d: PROCESS(a, b, c)
BEGIN
IF a = '1' THEN
d <= b;
IF b = '1' THEN
e <= c;
f <= '0';
END IF;
ELSE
d <= '0';
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
3185f65cd506c41a5c9809a4c6a56372
| 0.485584 | 3.486772 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/sw_windowing/counter.vhd
| 1 | 3,853 |
-------------------------------------------------------------------------------
-- Title : Window position index counter
-- Project :
-------------------------------------------------------------------------------
-- File : counter.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-01-31
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Up/Down for symmetrical window LUT
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-31 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity counter is
generic (
g_mem_size : natural := 601;
g_bus_size : natural := 15
--g_switch_delay : natural := 2
);
port (
clk_i : in std_logic; -- input clock
ce_i : in std_logic; -- clock enable
rst_n_i : in std_logic; -- reset
switch_delay_i : in std_logic_vector(15 downto 0);
switch_en_i : in std_logic;
switch_o : out std_logic;
index_o : out std_logic_vector(g_bus_size-1 downto 0)); -- Memory address to current
-- window data
end entity counter;
architecture behavioural of counter is
-- This is the address of the last sample in a vector with half
-- the size of the window
constant last_address : natural := g_mem_size-1;
signal switch_state : std_logic := '0';
signal switch_delay_slice : std_logic_vector(g_bus_size-1 downto 0);
begin -- architecture behavioural
counting : process(clk_i)
variable going_up : boolean := true;
--variable count : natural := 0; -- internal counter
variable count : unsigned(g_bus_size-1 downto 0) :=
to_unsigned(0, g_bus_size); -- internal counter
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count := (others => '0');
going_up := true;
switch_state <= '0';
else
if ce_i = '1' then
if switch_en_i = '0' then
count := (others => '0');
going_up := true;
switch_state <= '0';
else
if going_up then
count := count + 1;
if count = last_address then
going_up := false;
end if; --count = last_address
-- toggle switch clock. FIXME: switch_delay_slice
-- cannot be greater than last_address, otherwise
-- we will not switch properly
if count = last_address - unsigned(switch_delay_slice) then
switch_state <= not switch_state;
end if;
else
--counting down
count := count - 1;
if count = to_unsigned(0, g_bus_size) then
going_up := true;
end if; -- count = 0
--switch N samples before reaches zero
--if count = g_switch_delay then
if count = unsigned(switch_delay_slice) then
switch_state <= not switch_state;
end if; -- count = switch_state
end if; -- going up
index_o <= std_logic_vector(count);
switch_o <= switch_state;
end if; -- switch_en_i
end if; -- ce
end if; -- reset
end if; -- rising edge
end process counting;
switch_delay_slice <= switch_delay_i(g_bus_size-1 downto 0);
end architecture behavioural;
|
lgpl-3.0
|
3e444754ade61296d7a1f04c45125731
| 0.474436 | 4.257459 | false | false | false | false |
nanomolina/MIPS
|
prueba/maindec.vhd
| 6 | 1,077 |
library ieee;
use ieee.std_logic_1164.all;
entity maindec is
port (Op: in std_logic_vector(5 downto 0);
MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump: out std_logic;
AluOp: out std_logic_vector(1 downto 0));
end entity;
architecture arq_maindec of maindec is
signal parcial_result: std_logic_vector(8 downto 0);
begin
parcial_result <= ("110000010") when (Op = "000000") else
("101001000") when (Op = "100011") else
("001010000") when (Op = "101011") else
("000100001") when (Op = "000100") else
("101000000") when (Op = "001000") else
("000000100") when (Op = "000010") else
("---------");
RegWrite <= parcial_result(8);
RegDst <= parcial_result(7);
AluSrc <= parcial_result(6);
Branch <= parcial_result(5);
MemWrite <= parcial_result(4);
MemToReg <= parcial_result(3);
Jump <= parcial_result(2);
AluOp <= parcial_result(1 downto 0);
end architecture;
|
gpl-3.0
|
23a41e3c877d18ae25a1decf2e518e8d
| 0.558032 | 4.095057 | false | false | false | false |
nanomolina/MIPS
|
prueba/aludec.vhd
| 6 | 766 |
library ieee;
use ieee.std_logic_1164.all;
entity aludec is
port (funct: in std_logic_vector(5 downto 0);
aluop: in std_logic_vector(1 downto 0);
alucontrol: out std_logic_vector(2 downto 0));
end entity;
architecture arq_aludec of aludec is
begin
alucontrol <= "010" when aluop = "00" else
"110" when aluop = "01" else
"010" when aluop(0) = '1' and funct = "100000" else
"110" when aluop(0) = '1' and funct = "100010" else
"000" when aluop(0) = '1' and funct = "100100" else
"001" when aluop(0) = '1' and funct = "100101" else
"111" when aluop(0) = '1' and funct = "101010" else
unaffected;
end architecture;
|
gpl-3.0
|
1df5e0cba9806af4f18d73dfecd544f8
| 0.548303 | 3.579439 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/ps2/ps2.vhd
| 1 | 1,630 |
-- PS2 wrapper, peripheral for MARK-II
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ps2 is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_miso: out std_logic_vector(31 downto 0);
RD: in std_logic;
ack: out std_logic;
--device
ps2clk: in std_logic;
ps2dat: in std_logic;
intrq: out std_logic
);
end entity ps2;
architecture ps2_arch of ps2 is
component ps2core is
port(
clk: in std_logic;
res: in std_logic;
byte_out: out unsigned(7 downto 0);
byte_recieved: out std_logic;
ps2clk: in std_logic;
ps2dat: in std_logic
);
end component ps2core;
signal byte: unsigned(7 downto 0);
signal cs: std_logic;
begin
ps2core0: ps2core
port map(clk, res, byte, intrq, ps2clk, ps2dat);
process(address) is
begin
if unsigned(address) = BASE_ADDRESS then
cs <= '1';
else
cs <= '0';
end if;
end process;
data_miso <= std_logic_vector( x"000000" & byte ) when (RD = '1' and cs = '1') else (others => 'Z');
ack <= '1' when (RD = '1' and cs = '1') else '0';
end architecture ps2_arch;
|
mit
|
24b3ae32653679d9e5e7e4ff2ea9076a
| 0.543278 | 3.495708 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.vhd
| 1 | 75,575 |
------------------------------------------------------------------------------
-- Title : Top DSP design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-02-25
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-25 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Custom common cores
use work.ifc_common_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- DSP definitions
use work.dsp_cores_pkg.all;
-- BPM definitions
use work.bpm_cores_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_dsp is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------
-- FMC516 ports
-----------------------------
-- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM,
-- AD7417 temperature diodes and AD7417 supply rails
sys_i2c_scl_b : inout std_logic;
sys_i2c_sda_b : inout std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i : in std_logic;
adc_clk0_n_i : in std_logic;
adc_clk1_p_i : in std_logic;
adc_clk1_n_i : in std_logic;
adc_clk2_p_i : in std_logic;
adc_clk2_n_i : in std_logic;
adc_clk3_p_i : in std_logic;
adc_clk3_n_i : in std_logic;
-- DDR ADC data channels.
adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o : out std_logic;
adc_clk_div_rst_n_o : out std_logic;
-- FMC Front leds. Typical uses: Over Range or Full Scale
-- condition.
fmc_leds_o : out std_logic_vector(1 downto 0);
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o : out std_logic;
sys_spi_data_b : inout std_logic;
sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- External Trigger To/From FMC
m2c_trig_p_i : in std_logic;
m2c_trig_n_i : in std_logic;
c2m_trig_p_o : out std_logic;
c2m_trig_n_o : out std_logic;
-- LMK (National Semiconductor) is the clock and distribution IC,
-- programmable via Microwire Interface
lmk_lock_i : in std_logic;
lmk_sync_o : out std_logic;
lmk_uwire_latch_en_o : out std_logic;
lmk_uwire_data_o : out std_logic;
lmk_uwire_clock_o : out std_logic;
-- Programable VCXO via I2C
vcxo_i2c_sda_b : inout std_logic;
vcxo_i2c_scl_o : out std_logic;
vcxo_pd_l_o : out std_logic;
-- One-wire To/From DS2431 (VMETRO Data)
fmc_id_dq_b : inout std_logic;
-- One-wire To/From DS2432 SHA-1 (SP-Devices key)
fmc_key_dq_b : inout std_logic;
-- General board pins
fmc_pwr_good_i : in std_logic;
-- Internal/External clock distribution selection
fmc_clk_sel_o : out std_logic;
-- Reset ADCs
fmc_reset_adcs_n_o : out std_logic;
--FMC Present status
fmc_prsnt_m2c_l_i : in std_logic;
-- General board status
fmc_mmcm_lock_o : out std_logic;
fmc_lmk_lock_o : out std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_dsp;
architecture rtl of dbe_bpm_dsp is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 10;
-- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC,
--Etherbone, FMC516, Peripherals
-- Number of masters
constant c_masters : natural := 8; -- LM32 master, Data + Instruction,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
--constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
constant c_dpram_size : natural := 90112/4; -- in 32-bit words (90KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
--constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
constant c_dpram_ethbuf_size : natural := 16384/4; -- in 32-bit words (16KB)
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- TICs counter period. 100MHz clock -> msec granularity
constant c_tics_cntr_period : natural := 100000;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_adc_ref_clk : natural := 1;
-- DSP constants
constant c_dsp_ref_num_bits : natural := 24;
constant c_dsp_pos_num_bits : natural := 26;
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- FMC516 layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter
constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400");
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"20000000"), -- 64KB RAM
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port
7 => f_sdb_embed_device(c_xwb_position_calc_core_sdb,
x"30008000"), -- Position Calc Core control port
8 => f_sdb_embed_bridge(c_fmc516_bridge_sdb, x"30010000"), -- FMC516 control port
9 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000") -- General peripherals control port
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"30000000";
-- FMC516 ADC data constants
constant c_adc_data_ch0_lsb : natural := 0;
constant c_adc_data_ch0_msb : natural := c_num_adc_bits-1 + c_adc_data_ch0_lsb;
constant c_adc_data_ch1_lsb : natural := c_adc_data_ch0_msb + 1;
constant c_adc_data_ch1_msb : natural := c_num_adc_bits-1 + c_adc_data_ch1_lsb;
constant c_adc_data_ch2_lsb : natural := c_adc_data_ch1_msb + 1;
constant c_adc_data_ch2_msb : natural := c_num_adc_bits-1 + c_adc_data_ch2_lsb;
constant c_adc_data_ch3_lsb : natural := c_adc_data_ch2_msb + 1;
constant c_adc_data_ch3_msb : natural := c_num_adc_bits-1 + c_adc_data_ch3_lsb;
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- FMC516 Signals
signal wbs_fmc516_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc516_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc516_mmcm_lock_int : std_logic;
signal fmc516_lmk_lock_int : std_logic;
signal fmc516_fs_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_fs_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_adc_data : std_logic_vector(c_num_adc_channels*16-1 downto 0);
signal fmc516_adc_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
--signal fmc_debug : std_logic;
--signal reset_adc_counter : unsigned(6 downto 0) := (others => '0');
signal fs_rst_sync_n : std_logic;
signal fs_rst_n : std_logic;
-- FMC516 Debug
signal fmc516_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
signal sys_spi_clk_int : std_logic;
--signal sys_spi_data_int : std_logic;
signal sys_spi_dout_int : std_logic;
signal sys_spi_din_int : std_logic;
signal sys_spi_miosio_oe_n_int : std_logic;
signal sys_spi_cs_adc0_n_int : std_logic;
signal sys_spi_cs_adc1_n_int : std_logic;
signal sys_spi_cs_adc2_n_int : std_logic;
signal sys_spi_cs_adc3_n_int : std_logic;
signal lmk_lock_int : std_logic;
signal lmk_sync_int : std_logic;
signal lmk_uwire_latch_en_int : std_logic;
signal lmk_uwire_data_int : std_logic;
signal lmk_uwire_clock_int : std_logic;
signal fmc_reset_adcs_n_int : std_logic;
signal fmc_reset_adcs_n_out : std_logic;
-- DSP signals
signal dsp_sysce : std_logic;
signal dsp_sysce_clr : std_logic;
signal dsp_sysclk : std_logic;
signal dsp_sysclk2x : std_logic;
signal dsp_rst_n : std_logic;
signal dsp_kx : std_logic_vector(24 downto 0);
signal dsp_ky : std_logic_vector(24 downto 0);
signal dsp_ksum : std_logic_vector(24 downto 0);
signal dsp_del_sig_div_thres : std_logic_vector(25 downto 0);
signal dsp_adc_ch0_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_bpf_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_bpf_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_poly35_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_poly35_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_x_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_x_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_x_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_tbt_decim_q_ch01_incorrect : std_logic;
signal dsp_tbt_decim_q_ch23_incorrect : std_logic;
signal dsp_fofb_decim_q_01_missing : std_logic;
signal dsp_fofb_decim_q_23_missing : std_logic;
signal dsp_monit_cic_unexpected : std_logic;
signal dsp_monit_cfir_incorrect : std_logic;
signal dsp_monit_pfir_incorrect : std_logic;
signal dsp_clk_ce_1 : std_logic;
signal dsp_clk_ce_2 : std_logic;
signal dsp_clk_ce_35 : std_logic;
signal dsp_clk_ce_70 : std_logic;
signal dsp_clk_ce_1390000 : std_logic;
signal dsp_clk_ce_1112 : std_logic;
signal dsp_clk_ce_2224 : std_logic;
signal dsp_clk_ce_11120000 : std_logic;
signal dsp_clk_ce_22240000 : std_logic;
signal dsp_clk_ce_5000 : std_logic;
signal dsp_clk_ce_556 : std_logic;
signal dsp_clk_ce_2780000 : std_logic;
signal dsp_clk_ce_5560000 : std_logic;
signal clk_rffe_swap : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- Counter signal
--signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
--constant s_counter_full : integer := 100000000;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal CONTROL2 : std_logic_vector(35 downto 0);
signal CONTROL3 : std_logic_vector(35 downto 0);
signal CONTROL4 : std_logic_vector(35 downto 0);
signal CONTROL5 : std_logic_vector(35 downto 0);
signal CONTROL6 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 2 signals
signal TRIG_ILA2_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 3 signals
signal TRIG_ILA3_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 4 signals
signal TRIG_ILA4_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA4_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 5 signals
signal TRIG_ILA5_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA5_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 6 signals
signal TRIG_ILA6_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA6_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_4 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
--component chipscope_icon_2_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0)
--);
--end component;
--component chipscope_icon_4_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0);
-- CONTROL2 : inout std_logic_vector(35 downto 0);
-- CONTROL3 : inout std_logic_vector(35 downto 0)
--);
--end component;
--component chipscope_icon_8_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0);
-- CONTROL2 : inout std_logic_vector(35 downto 0);
-- CONTROL3 : inout std_logic_vector(35 downto 0);
-- CONTROL4 : inout std_logic_vector(35 downto 0);
-- CONTROL5 : inout std_logic_vector(35 downto 0);
-- CONTROL6 : inout std_logic_vector(35 downto 0);
-- CONTROL7 : inout std_logic_vector(35 downto 0)
--);
--end component;
component chipscope_icon_7_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0);
CONTROL4 : inout std_logic_vector(35 downto 0);
CONTROL5 : inout std_logic_vector(35 downto 0);
CONTROL6 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
component chipscope_ila_8192
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(7 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0);
TRIG4 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => 1 -- CLK_SYS
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
cmp_lm32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug"
) -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(0), -- Data bus
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1), -- Instruction bus
iwb_i => cbar_slave_o(1)
);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
4 => irq_tx_done, others => '0');
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(4),
wb_master_out => cbar_slave_i(4),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
---- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
--The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(5),
tx_ram_i => cbar_slave_o(5),
rx_ram_o => cbar_slave_i(6),
rx_ram_i => cbar_slave_o(6),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(7) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(7);
-- The FMC516 is slave 8
cmp_xwb_fmc516 : xwb_fmc516
generic map(
g_fpga_device => "VIRTEX6",
g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
g_address_granularity => BYTE,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (0.0, 0.0, 8.882, 8.882), --476.066*35/148 aprox 112.583 MHz
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from FMC516 (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from FMC516.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "0011",
g_use_data_chains => "1111",
g_map_clk_data_chains => (1,0,0,1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_adc_ref_clk,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(8),
wb_slv_o => cbar_master_i(8),
-----------------------------
-- External ports
-----------------------------
-- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM,
-- AD7417 temperature diodes and AD7417 supply rails
sys_i2c_scl_b => sys_i2c_scl_b,
sys_i2c_sda_b => sys_i2c_sda_b,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i => adc_clk0_p_i,
adc_clk0_n_i => adc_clk0_n_i,
adc_clk1_p_i => adc_clk1_p_i,
adc_clk1_n_i => adc_clk1_n_i,
adc_clk2_p_i => adc_clk2_p_i,
adc_clk2_n_i => adc_clk2_n_i,
adc_clk3_p_i => adc_clk3_p_i,
adc_clk3_n_i => adc_clk3_n_i,
-- DDR ADC data channels.
adc_data_ch0_p_i => adc_data_ch0_p_i,
adc_data_ch0_n_i => adc_data_ch0_n_i,
adc_data_ch1_p_i => adc_data_ch1_p_i,
adc_data_ch1_n_i => adc_data_ch1_n_i,
adc_data_ch2_p_i => adc_data_ch2_p_i,
adc_data_ch2_n_i => adc_data_ch2_n_i,
adc_data_ch3_p_i => adc_data_ch3_p_i,
adc_data_ch3_n_i => adc_data_ch3_n_i,
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o => adc_clk_div_rst_p_o,
adc_clk_div_rst_n_o => adc_clk_div_rst_n_o,
-- FMC Front leds. Typical uses: Over Range or Full Scale
-- condition.
fmc_leds_o => fmc_leds_o,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o => sys_spi_clk_int,--sys_spi_clk_o,
sys_spi_data_b => sys_spi_data_b,
--sys_spi_dout_o => sys_spi_dout_int,
--sys_spi_din_i => sys_spi_din_int,
sys_spi_cs_adc0_n_o => sys_spi_cs_adc0_n_int, -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o => sys_spi_cs_adc1_n_int, -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o => sys_spi_cs_adc2_n_int, -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o => sys_spi_cs_adc3_n_int, -- SPI ADC CS channel 3
--sys_spi_miosio_oe_n_o => sys_spi_miosio_oe_n_int,
-- External Trigger To/From FMC
m2c_trig_p_i => m2c_trig_p_i,
m2c_trig_n_i => m2c_trig_n_i,
c2m_trig_p_o => c2m_trig_p_o,
c2m_trig_n_o => c2m_trig_n_o,
-- LMK (National Semiconductor) is the clock and distribution IC.
-- uWire interface
lmk_lock_i => lmk_lock_int,--lmk_lock_i,
lmk_sync_o => lmk_sync_int,--lmk_sync_o,
lmk_uwire_latch_en_o => lmk_uwire_latch_en_int,--lmk_uwire_latch_en_o,
lmk_uwire_data_o => lmk_uwire_data_int,--lmk_uwire_data_o,
lmk_uwire_clock_o => lmk_uwire_clock_int,--lmk_uwire_clock_o,
-- Programable VCXO via I2C
vcxo_i2c_sda_b => vcxo_i2c_sda_b,
vcxo_i2c_scl_o => vcxo_i2c_scl_o,
vcxo_pd_l_o => vcxo_pd_l_o,
-- One-wire To/From DS2431 (VMETRO Data)
fmc_id_dq_b => fmc_id_dq_b,
-- One-wire To/From DS2432 SHA-1 (SP-Devices key)
fmc_key_dq_b => fmc_key_dq_b,
-- General board pins
fmc_pwr_good_i => fmc_pwr_good_i,
-- Internal/External clock distribution selection
fmc_clk_sel_o => fmc_clk_sel_o,
-- Reset ADCs
fmc_reset_adcs_n_o => fmc_reset_adcs_n_o,--fmc_reset_adcs_n_int,
--FMC Present status
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_l_i,
-----------------------------
-- ADC output signals. Continuous flow.
-----------------------------
adc_clk_o => fmc516_fs_clk,
adc_clk2x_o => fmc516_fs_clk2x,
adc_rst_n_o => open,
adc_data_o => fmc516_adc_data,
adc_data_valid_o => fmc516_adc_valid,
-----------------------------
-- General ADC output signals
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => clk_rffe_swap, -- from Position Calculation Core
-- General board status
fmc_mmcm_lock_o => fmc516_mmcm_lock_int,
fmc_lmk_lock_o => fmc516_lmk_lock_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc516_in_array,
wbs_source_o => wbs_fmc516_out_array,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc516_debug_valid_int,
fifo_debug_full_o => fmc516_debug_full_int,
fifo_debug_empty_o => fmc516_debug_empty_int
);
gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc516_in_array(i) <= cc_dummy_src_com_in;
end generate;
fmc_mmcm_lock_o <= fmc516_mmcm_lock_int;
fmc_lmk_lock_o <= fmc516_lmk_lock_int;
sys_spi_clk_o <= sys_spi_clk_int;
sys_spi_cs_adc0_n_o <= sys_spi_cs_adc0_n_int;
sys_spi_cs_adc1_n_o <= sys_spi_cs_adc1_n_int;
sys_spi_cs_adc2_n_o <= sys_spi_cs_adc2_n_int;
sys_spi_cs_adc3_n_o <= sys_spi_cs_adc3_n_int;
lmk_lock_int <= lmk_lock_i;
lmk_sync_o <= lmk_sync_int;
lmk_uwire_latch_en_o <= lmk_uwire_latch_en_int;
lmk_uwire_data_o <= lmk_uwire_data_int;
lmk_uwire_clock_o <= lmk_uwire_clock_int;
-- Position calc core is slave 7
cmp_xwb_position_calc_core : xwb_position_calc_core
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => WORD
)
port map (
rst_n_i => clk_sys_rstn,
clk_i => clk_sys, -- wishbone clock
fs_clk_i => dsp_sysclk2x, -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => cbar_master_o(7),
wb_slv_o => cbar_master_i(7),
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i => fmc516_adc_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb),
adc_ch1_i => fmc516_adc_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb),
adc_ch2_i => fmc516_adc_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb),
adc_ch3_i => fmc516_adc_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb),
-----------------------------
-- DSP config parameter signals
-----------------------------
kx => dsp_kx,
ky => dsp_ky,
ksum => dsp_ksum,
del_sig_div_fofb_thres_i => dsp_del_sig_div_thres,
del_sig_div_tbt_thres_i => dsp_del_sig_div_thres,
del_sig_div_monit_thres_i => dsp_del_sig_div_thres,
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o => dsp_adc_ch0_data,
adc_ch1_dbg_data_o => dsp_adc_ch1_data,
adc_ch2_dbg_data_o => dsp_adc_ch2_data,
adc_ch3_dbg_data_o => dsp_adc_ch3_data,
bpf_ch0_o => dsp_bpf_ch0,
--bpf_ch1_o => out std_logic_vector(23 downto 0);
bpf_ch2_o => dsp_bpf_ch2,
--bpf_ch3_o => out std_logic_vector(23 downto 0);
mix_ch0_i_o => dsp_mix_ch0,
--mix_ch0_q_o => out std_logic_vector(23 downto 0);
--mix_ch1_i_o => out std_logic_vector(23 downto 0);
--mix_ch1_q_o => out std_logic_vector(23 downto 0);
mix_ch2_i_o => dsp_mix_ch2,
--mix_ch2_q_o => out std_logic_vector(23 downto 0);
--mix_ch3_i_o => out std_logic_vector(23 downto 0);
--mix_ch3_q_o => out std_logic_vector(23 downto 0);
tbt_decim_ch0_i_o => dsp_poly35_ch0,
--tbt_decim_ch0_i_o => open,
--poly35_ch0_q_o => out std_logic_vector(23 downto 0);
--poly35_ch1_i_o => out std_logic_vector(23 downto 0);
--poly35_ch1_q_o => out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o => dsp_poly35_ch2,
--tbt_decim_ch2_i_o => open,
--poly35_ch2_q_o => out std_logic_vector(23 downto 0);
--poly35_ch3_i_o => out std_logic_vector(23 downto 0);
--poly35_ch3_q_o => out std_logic_vector(23 downto 0);
tbt_decim_q_ch01_incorrect_o => dsp_tbt_decim_q_ch01_incorrect,
tbt_decim_q_ch23_incorrect_o => dsp_tbt_decim_q_ch23_incorrect,
tbt_amp_ch0_o => dsp_tbt_amp_ch0,
tbt_amp_ch1_o => dsp_tbt_amp_ch1,
tbt_amp_ch2_o => dsp_tbt_amp_ch2,
tbt_amp_ch3_o => dsp_tbt_amp_ch3,
fofb_decim_ch0_i_o => dsp_cic_fofb_ch0, --out std_logic_vector(23 downto 0);
--cic_fofb_ch0_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_q_o => out std_logic_vector(24 downto 0);
fofb_decim_ch2_i_o => dsp_cic_fofb_ch2, --out std_logic_vector(23 downto 0);
--cic_fofb_ch2_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_q_o => out std_logic_vector(24 downto 0);
fofb_decim_q_01_missing_o => dsp_fofb_decim_q_01_missing,
fofb_decim_q_23_missing_o => dsp_fofb_decim_q_23_missing,
fofb_amp_ch0_o => dsp_fofb_amp_ch0,
fofb_amp_ch1_o => dsp_fofb_amp_ch1,
fofb_amp_ch2_o => dsp_fofb_amp_ch2,
fofb_amp_ch3_o => dsp_fofb_amp_ch3,
monit_amp_ch0_o => dsp_monit_amp_ch0,
monit_amp_ch1_o => dsp_monit_amp_ch1,
monit_amp_ch2_o => dsp_monit_amp_ch2,
monit_amp_ch3_o => dsp_monit_amp_ch3,
x_tbt_o => dsp_x_tbt,
y_tbt_o => dsp_y_tbt,
q_tbt_o => dsp_q_tbt,
sum_tbt_o => dsp_sum_tbt,
x_fofb_o => dsp_x_fofb,
y_fofb_o => dsp_y_fofb,
q_fofb_o => dsp_q_fofb,
sum_fofb_o => dsp_sum_fofb,
x_monit_o => dsp_x_monit,
y_monit_o => dsp_y_monit,
q_monit_o => dsp_q_monit,
sum_monit_o => dsp_sum_monit,
monit_cic_unexpected_o => dsp_monit_cic_unexpected,
monit_cfir_incorrect_o => dsp_monit_cfir_incorrect,
monit_pfir_incorrect_o => dsp_monit_pfir_incorrect,
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o => clk_rffe_swap,
ctrl1_o => open,
ctrl2_o => open,
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o => dsp_clk_ce_1,
clk_ce_1112_o => dsp_clk_ce_1112,
clk_ce_11120000_o => dsp_clk_ce_11120000,
clk_ce_1390000_o => dsp_clk_ce_1390000,
clk_ce_2_o => dsp_clk_ce_2,
clk_ce_2224_o => dsp_clk_ce_2224,
clk_ce_22240000_o => dsp_clk_ce_22240000,
clk_ce_2780000_o => dsp_clk_ce_2780000,
clk_ce_35_o => dsp_clk_ce_35,
clk_ce_5000_o => dsp_clk_ce_5000,
clk_ce_556_o => dsp_clk_ce_556,
clk_ce_5560000_o => dsp_clk_ce_5560000,
clk_ce_70_o => dsp_clk_ce_70
);
--dsp_poly35_ch0 <= (others => '0');
--dsp_poly35_ch2 <= (others => '0');
--
--dsp_monit_amp_ch0 <= (others => '0');
--dsp_monit_amp_ch1 <= (others => '0');
--dsp_monit_amp_ch2 <= (others => '0');
--dsp_monit_amp_ch3 <= (others => '0');
-- Signals for the DSP chain
dsp_sysce <= '1';
dsp_sysce_clr <= '0';
--dsp_sysclk <= fmc516_fs_clk(c_adc_ref_clk);
dsp_sysclk2x <= fmc516_fs_clk2x(c_adc_ref_clk); -- oversampled DSP chain
dsp_sysclk <= fmc516_fs_clk(c_adc_ref_clk); -- oversampled DSP chain
--dsp_rst_n <= fmc516_fs_rst_n(c_adc_ref_clk);
dsp_del_sig_div_thres <= "00000000000000001000000000"; -- aprox 1.22e-4 FIX26_22
--dsp_kx <= "100110001001011010000000"; -- 10000000 UFIX24_0
dsp_kx <= "0100000000000000000000000"; -- ??? UFIX25_0
--dsp_kx <= "00100110001001011010000000"; -- 10000000 UFIX26_0
--dsp_ky <= "100110001001011010000000"; -- 10000000 UFIX24_0
dsp_ky <= "0100000000000000000000000"; -- ??? UFIX25_0
--dsp_ky <= "00100110001001011010000000"; -- 10000000 UFIX26_0
dsp_ksum <= "0111111111111111111111111"; -- 1.0 FIX25_24
--dsp_ksum <= "10000000000000000000000000"; -- 1.0 FIX26_25
--dsp_ksum <= "100000000000000000000000"; -- 1.0 FIX24_23
--dsp_ksum <= "10000000000000000000000000"; -- 1.0 FIX26_25
-- The board peripherals components is slave 9
cmp_xwb_dbe_periph : xwb_dbe_periph
generic map(
-- NOT used!
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period => c_tics_cntr_period,
g_num_leds => c_leds_num_pins,
g_num_buttons => c_buttons_num_pins
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- UART
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- LEDs
led_out_o => gpio_leds_int,
led_in_i => gpio_leds_int,
led_oen_o => open,
-- Buttons
button_out_o => open,
button_in_i => buttons_i,
button_oen_o => open,
-- Wishbone
slave_i => cbar_master_o(9),
slave_o => cbar_master_i(9)
);
leds_o <= gpio_leds_int;
---- Xilinx Chipscope
--cmp_chipscope_icon_0 : chipscope_icon_4_port
--port map (
-- CONTROL0 => CONTROL0,
-- CONTROL1 => CONTROL1,
-- CONTROL2 => CONTROL2,
-- CONTROL3 => CONTROL3
--);
cmp_chipscope_icon_7_port : chipscope_icon_7_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1,
CONTROL2 => CONTROL2,
CONTROL3 => CONTROL3,
CONTROL4 => CONTROL4,
CONTROL5 => CONTROL5,
CONTROL6 => CONTROL6
);
cmp_chipscope_ila_0_fmc516_adc : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => fmc516_fs_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- FMC516 WBS master output data
--TRIG_ILA0_0 <= fmc516_adc_data(31 downto 16) &
-- fmc516_adc_data(47 downto 32);
TRIG_ILA0_0 <= dsp_adc_ch1_data &
dsp_adc_ch0_data;
TRIG_ILA0_1 <= dsp_adc_ch3_data &
dsp_adc_ch2_data;
TRIG_ILA0_2 <= (others => '0');
TRIG_ILA0_3 <= (others => '0');
-- FMC516 WBS master output data
--TRIG_ILA0_1(11 downto 0) <= adc_dly_reg_debug_int(1).clk_load &
-- adc_dly_reg_debug_int(1).data_load &
-- adc_dly_reg_debug_int(1).clk_dly_reg &
-- adc_dly_reg_debug_int(1).data_dly_reg;
--TRIG_ILA0_1(31 downto 12) <= (others => '0');
---- FMC516 WBS master output control signals
--TRIG_ILA0_2(17 downto 0) <= wbs_fmc516_out_array(1).cyc &
-- wbs_fmc516_out_array(1).stb &
-- wbs_fmc516_out_array(1).adr &
-- wbs_fmc516_out_array(1).sel &
-- wbs_fmc516_out_array(1).we &
-- wbs_fmc516_out_array(2).cyc &
-- wbs_fmc516_out_array(2).stb &
-- wbs_fmc516_out_array(2).adr &
-- wbs_fmc516_out_array(2).sel &
-- wbs_fmc516_out_array(2).we;
--TRIG_ILA0_2(18) <= fmc_reset_adcs_n_out;
--TRIG_ILA0_2(22 downto 19) <= fmc516_adc_valid;
--TRIG_ILA0_2(23) <= fmc516_mmcm_lock_int;
--TRIG_ILA0_2(24) <= fmc516_lmk_lock_int;
--TRIG_ILA0_2(25) <= fmc516_debug_valid_int(1);
--TRIG_ILA0_2(26) <= fmc516_debug_full_int(1);
--TRIG_ILA0_2(27) <= fmc516_debug_empty_int(1);
--TRIG_ILA0_2(31 downto 28) <= (others => '0');
--
--TRIG_ILA0_3 <= dsp_adc_ch3_data &
-- dsp_adc_ch2_data;
-- Mix and BPF data
cmp_chipscope_ila_8192_bpf_mix : chipscope_ila_8192
port map (
CONTROL => CONTROL1,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3,
TRIG4 => TRIG_ILA1_4
);
TRIG_ILA1_0(0) <= dsp_clk_ce_1;
TRIG_ILA1_0(1) <= dsp_clk_ce_35;
TRIG_ILA1_0(2) <= dsp_clk_ce_1112;
TRIG_ILA1_0(3) <= dsp_clk_ce_1390000; -- not used
TRIG_ILA1_0(4) <= dsp_clk_ce_2780000;
TRIG_ILA1_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA1_0(7 downto 6) <= (others => '0');
--TRIG_ILA1_1(dsp_bpf_ch0'range) <= dsp_bpf_ch0;
--TRIG_ILA1_2(dsp_bpf_ch2'range) <= dsp_bpf_ch2;
--TRIG_ILA1_1(dsp_poly35_ch0'range) <= dsp_poly35_ch0;
--TRIG_ILA1_2(dsp_poly35_ch2'range) <= dsp_poly35_ch2;
--TRIG_ILA1_3(dsp_cic_fofb_ch0'range) <= dsp_cic_fofb_ch0;
--TRIG_ILA1_4(dsp_cic_fofb_ch2'range) <= dsp_cic_fofb_ch2;
TRIG_ILA1_1(dsp_monit_amp_ch0'range) <= dsp_monit_amp_ch0;
TRIG_ILA1_2(dsp_monit_amp_ch1'range) <= dsp_monit_amp_ch1;
TRIG_ILA1_3(dsp_monit_amp_ch2'range) <= dsp_monit_amp_ch2;
TRIG_ILA1_4(dsp_monit_amp_ch3'range) <= dsp_monit_amp_ch3;
TRIG_ILA1_4(dsp_monit_amp_ch3'left+3 downto
dsp_monit_amp_ch3'left+1) <= dsp_monit_cic_unexpected &
dsp_monit_cfir_incorrect &
dsp_monit_pfir_incorrect;
-- TBT amplitudes data
cmp_chipscope_ila_8192_tbt_amp : chipscope_ila_8192
port map (
CONTROL => CONTROL2,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA2_0,
TRIG1 => TRIG_ILA2_1,
TRIG2 => TRIG_ILA2_2,
TRIG3 => TRIG_ILA2_3,
TRIG4 => TRIG_ILA2_4
);
TRIG_ILA2_0(0) <= dsp_clk_ce_1;
TRIG_ILA2_0(1) <= dsp_clk_ce_35;
TRIG_ILA2_0(2) <= dsp_clk_ce_1112;
TRIG_ILA2_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA2_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA2_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA2_0(7 downto 6) <= (others => '0');
TRIG_ILA2_1(dsp_tbt_amp_ch0'range) <= dsp_tbt_amp_ch0;
TRIG_ILA2_2(dsp_tbt_amp_ch1'range) <= dsp_tbt_amp_ch1;
TRIG_ILA2_3(dsp_tbt_amp_ch2'range) <= dsp_tbt_amp_ch2;
TRIG_ILA2_4(dsp_tbt_amp_ch3'range) <= dsp_tbt_amp_ch3;
TRIG_ILA2_4(dsp_tbt_amp_ch3'left+2 downto
dsp_tbt_amp_ch3'left+1) <= dsp_tbt_decim_q_ch01_incorrect &
dsp_tbt_decim_q_ch23_incorrect;
-- TBT position data
cmp_chipscope_ila_8192_tbt_pos : chipscope_ila_8192
port map (
CONTROL => CONTROL3,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA3_0,
TRIG1 => TRIG_ILA3_1,
TRIG2 => TRIG_ILA3_2,
TRIG3 => TRIG_ILA3_3,
TRIG4 => TRIG_ILA3_4
);
TRIG_ILA3_0(0) <= dsp_clk_ce_1;
TRIG_ILA3_0(1) <= dsp_clk_ce_35;
TRIG_ILA3_0(2) <= dsp_clk_ce_1112;
TRIG_ILA3_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA3_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA3_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA3_0(7 downto 6) <= (others => '0');
TRIG_ILA3_1(dsp_x_tbt'range) <= dsp_x_tbt;
TRIG_ILA3_2(dsp_y_tbt'range) <= dsp_y_tbt;
TRIG_ILA3_3(dsp_q_tbt'range) <= dsp_q_tbt;
TRIG_ILA3_4(dsp_sum_tbt'range) <= dsp_sum_tbt;
-- FOFB amplitudes data
cmp_chipscope_ila_8192_fofb_amp : chipscope_ila_8192
port map (
CONTROL => CONTROL4,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA4_0,
TRIG1 => TRIG_ILA4_1,
TRIG2 => TRIG_ILA4_2,
TRIG3 => TRIG_ILA4_3,
TRIG4 => TRIG_ILA4_4
);
TRIG_ILA4_0(0) <= dsp_clk_ce_1;
TRIG_ILA4_0(1) <= dsp_clk_ce_35;
TRIG_ILA4_0(2) <= dsp_clk_ce_1112;
TRIG_ILA4_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA4_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA4_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA4_0(7 downto 6) <= (others => '0');
TRIG_ILA4_1(dsp_fofb_amp_ch0'range) <= dsp_fofb_amp_ch0;
TRIG_ILA4_2(dsp_fofb_amp_ch1'range) <= dsp_fofb_amp_ch1;
TRIG_ILA4_3(dsp_fofb_amp_ch2'range) <= dsp_fofb_amp_ch2;
TRIG_ILA4_4(dsp_fofb_amp_ch3'range) <= dsp_fofb_amp_ch3;
TRIG_ILA4_4(dsp_fofb_amp_ch3'left+2 downto
dsp_fofb_amp_ch3'left+1) <= dsp_fofb_decim_q_01_missing &
dsp_fofb_decim_q_23_missing;
-- FOFB position data
cmp_chipscope_ila_8192_fofb_pos : chipscope_ila_8192
port map (
CONTROL => CONTROL5,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA5_0,
TRIG1 => TRIG_ILA5_1,
TRIG2 => TRIG_ILA5_2,
TRIG3 => TRIG_ILA5_3,
TRIG4 => TRIG_ILA5_4
);
TRIG_ILA5_0(0) <= dsp_clk_ce_1;
TRIG_ILA5_0(1) <= dsp_clk_ce_35;
TRIG_ILA5_0(2) <= dsp_clk_ce_1112;
TRIG_ILA5_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA5_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA5_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA5_0(7 downto 6) <= (others => '0');
TRIG_ILA5_1(dsp_x_fofb'range) <= dsp_x_fofb;
TRIG_ILA5_2(dsp_y_fofb'range) <= dsp_y_fofb;
TRIG_ILA5_3(dsp_q_fofb'range) <= dsp_q_fofb;
TRIG_ILA5_4(dsp_sum_fofb'range) <= dsp_sum_fofb;
-- Monitoring position data
cmp_chipscope_ila_8192_monit_pos : chipscope_ila_8192
port map (
CONTROL => CONTROL6,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA6_0,
TRIG1 => TRIG_ILA6_1,
TRIG2 => TRIG_ILA6_2,
TRIG3 => TRIG_ILA6_3,
TRIG4 => TRIG_ILA6_4
);
TRIG_ILA6_0(0) <= dsp_clk_ce_1;
TRIG_ILA6_0(1) <= dsp_clk_ce_35;
TRIG_ILA6_0(2) <= dsp_clk_ce_1112;
TRIG_ILA6_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA6_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA6_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA6_0(7 downto 6) <= (others => '0');
TRIG_ILA6_1(dsp_x_monit'range) <= dsp_x_monit;
TRIG_ILA6_2(dsp_y_monit'range) <= dsp_y_monit;
TRIG_ILA6_3(dsp_q_monit'range) <= dsp_q_monit;
TRIG_ILA6_4(dsp_sum_monit'range) <= dsp_sum_monit;
end rtl;
|
lgpl-3.0
|
0edc692363bc48f00b7804489c58f397
| 0.432828 | 3.841559 | false | false | false | false |
Godoakos/conway-vhdl
|
ConwayFinal.vhd
| 1 | 7,495 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:48:40 01/16/2015
-- Design Name:
-- Module Name: ConwayFinal - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ConwayFinal is
Port ( clkin : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
hsync : out STD_LOGIC:='1';
vsync : out STD_LOGIC:='1');
end ConwayFinal;
architecture Behavioral of ConwayFinal is
COMPONENT clkgen
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
component DualPortBRAM is
port (CLK : in std_logic;
WE : in std_logic;
EN : in std_logic;
ADDRW : in std_logic_vector(7 downto 0);
ADDRR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(0 downto 0);
DO : out std_logic_vector(0 downto 0));
end component;
component shift_register is
port( CLK : in std_logic;
SI : in std_logic_vector(0 downto 0);
SO1 : out std_logic_vector(0 downto 0);
SO2 : out std_logic_vector(0 downto 0);
SO3 : out std_logic_vector(0 downto 0));
end component;
type STATE_TYPE is (INIT, FILL_SHIFTREG, NEXT_STATE, DRAW);
signal state : STATE_TYPE := INIT;
signal clkout : std_logic;
signal clksig : std_logic_vector(2 downto 0);
-------------------------------------------
signal hcount : unsigned(10 downto 0) := (others => '0');
signal vcount : unsigned(10 downto 0) := (others => '0');
-------------------------------------------
signal di : std_logic_vector(0 downto 0);
signal we_fb : std_logic := '1';
signal addrw_fb : std_logic_vector(7 downto 0) := (others => '0'); --elso 3 bit: melyik sor
signal addrr_fb : std_logic_vector(7 downto 0) := (others => '0'); --utolsó 5 bit: sorban hol
signal do_fb : std_logic_vector(0 downto 0);
signal we_sb : std_logic := '1';
signal addrw_sb : std_logic_vector(7 downto 0) := (others => '0');
signal addrr_sb : std_logic_vector(7 downto 0) := (others => '0');
signal do_sb : std_logic_vector(0 downto 0);
-------------------------------------------
signal so11 : std_logic_vector(0 downto 0);
signal so12 : std_logic_vector(0 downto 0);
signal so13 : std_logic_vector(0 downto 0);
signal so21 : std_logic_vector(0 downto 0);
signal so22 : std_logic_vector(0 downto 0);
signal so23 : std_logic_vector(0 downto 0);
signal so31 : std_logic_vector(0 downto 0);
signal so32 : std_logic_vector(0 downto 0);
signal so33 : std_logic_vector(0 downto 0);
-------------------------------------------
signal neigh : unsigned(3 downto 0) := "0000";
signal change : unsigned(4 downto 0) := (others => '0');
-------------------------------------------
begin
Inst_clkgen: clkgen PORT MAP(
CLKIN_IN => clkin,
RST_IN => '0',
CLKFX_OUT => clkout,
CLKIN_IBUFG_OUT => clksig(0),
CLK0_OUT => clksig(1),
LOCKED_OUT => clksig(2)
);
framebuff : DualPortBRAM port map (CLK => clkout, WE => we_fb, EN => '1', ADDRW => addrw_fb, ADDRR => addrr_fb, DI=> di, DO=> do_fb);
statebuff : DualPortBRAM port map (CLK => clkout, WE => we_sb, EN => '1', ADDRW => addrw_sb, ADDRR => addrr_sb, DI=> di, DO=> do_sb);
shiftreg1 : shift_register port map (CLK => clkout, SI => do_sb, SO1 => so11, SO2=>so12, SO3=>so13);
shiftreg2 : shift_register port map (CLK => clkout, SI => so13, SO1 => so21, SO2=>so22, SO3=>so23);
shiftreg3 : shift_register port map (CLK => clkout, SI => so23, SO1 => so31, SO2=>so32, SO3=>so33);
robotkurva_logika_es_kirajzolo : process(clkout)
begin
if clkout'event and clkout = '1' then
---------KIRAJZOLÓ--------------------
if hcount < 799 then
hcount <= hcount + 1;
else
hcount <= (others => '0');
end if;
if hcount = 799 then
if vcount < 524 then
vcount <= vcount + 1;
else
vcount <= (others => '0');
end if;
end if;
if hcount < 752 and hcount > 656 then
hsync <= '0';
else
hsync <= '1';
end if;
if vcount < 493 and vcount > 490 then
vsync <= '0';
else
vsync <= '1';
end if;
if hcount = 257 and vcount = 256 then --számolás elölrol
if change = "11111" then
state <= FILL_SHIFTREG;
addrr_fb <= (others => '0');
addrr_sb <= (others => '0');
addrw_fb <= (others => '0');
addrw_sb <= (others => '0');
end if;
change <= change+1;
end if;
if vcount < 257 and hcount < 257 then
if state = DRAW then
if do_fb(0) = '1' then
dout <= (others => '1');
else
dout <= (others => '0');
end if;
else
dout <= (others => '0');
end if;
else
dout <= (others => '0');
end if;
------------------ÁLLAPOTOK-----------
if state = INIT then
if addrw_fb = "11111111" or addrw_sb = "11111111" then
state <= FILL_SHIFTREG;
we_fb <= '0';
we_sb <= '0';
end if;
di(0) <= (clksig(2) xor clksig(1)) or addrw_fb(0); --random enough IMHO
if addrw_sb(7 downto 5) = "000" or addrw_sb(7 downto 5) = "111" then
di(0) <= '0';
end if;
if addrw_sb(4 downto 0) = "00000" or addrw_sb(4 downto 0) = "11111" then
di(0) <= '0';
end if;
addrw_fb <= std_logic_vector(unsigned(addrw_fb)+"00000001");
addrw_sb <= std_logic_vector(unsigned(addrw_sb)+"00000001");
---------------------------------------
elsif state = FILL_SHIFTREG then
if addrr_sb = "01100000" then --96
state <= NEXT_STATE;
we_fb <= '1';
we_sb <= '1';
else
addrr_sb <= std_logic_vector(unsigned(addrr_sb)+"00000001");
end if;
-------------------------------------------
elsif state = NEXT_STATE then
neigh <= (("000"&so11(0)) + ("000"&so12(0)) + ("000"&so13(0)) + ("000"&so21(0)) + ("000"&so23(0)) + ("000"&so31(0)) + ("000"&so32(0)) + ("000"&so33(0))); --kettes redva mód active
if (neigh<"0010" or neigh>"0011") then
di(0) <= '0';
elsif (neigh = "0011") then
di(0) <= '1';
else
di(0)<= so22(0);
end if;
if addrw_sb(7 downto 5) = "000" or addrw_sb(7 downto 5) = "111" then
di(0) <= '0';
end if;
if addrw_sb(4 downto 0) = "00000" or addrw_sb(4 downto 0) = "11111" then
di(0) <= '0';
end if;
if addrw_sb = "11111111" then
state <= DRAW;
we_fb <= '0';
we_sb <= '0';
else
addrr_sb <= std_logic_vector(unsigned(addrr_sb)+"00000001");
addrw_fb <= std_logic_vector(unsigned(addrw_fb)+"00000001");
addrw_sb <= std_logic_vector(unsigned(addrw_sb)+"00000001");
end if;
---------------------------------------------
elsif state = DRAW then
addrr_fb <= std_logic_vector(vcount(6 downto 3) & hcount(6 downto 3));
end if; --állapotok
end if; --órajel
end process;
end Behavioral;
|
mit
|
b75b031fe859605112ade25fc90785d8
| 0.544363 | 3.151808 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/cpu.vhd
| 1 | 29,820 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cpu is
port(
--system interface
clk: in std_logic;
res: in std_logic;
--bus interface
address: out std_logic_vector(23 downto 0);
data_mosi: out std_logic_vector(31 downto 0);
data_miso: in std_logic_vector(31 downto 0);
we: out std_logic;
oe: out std_logic;
ack: in std_logic;
swirq: out std_logic;
--interrupts
int: in std_logic;
int_address: in std_logic_vector(23 downto 0);
int_accept: out std_logic;
int_completed: out std_logic
);
end entity cpu;
architecture cpu_arch of cpu is
component id is
port(
clk: in std_logic;
res: in std_logic;
instr_opcode: in std_logic_vector(7 downto 0);
flag: in std_logic;
ack: in std_logic;
int: in std_logic;
swirq: out std_logic;
we: out std_logic;
oe: out std_logic;
int_accept: out std_logic;
int_completed: out std_logic;
data_c_sel: out std_logic_vector(2 downto 0);
data_a_sel: out std_logic_vector(3 downto 0);
data_b_sel: out std_logic_vector(2 downto 0);
force_we_reg_14: out std_logic;
inc_r14: out std_logic;
inc_r15: out std_logic;
dec_r15: out std_logic;
instruction_we: out std_logic;
regfile_c_we: out std_logic
);
end component id;
component regfile_reg is port(
clk: in std_logic;
res: in std_logic;
we: in std_logic;
inc: in std_logic;
dec: in std_logic;
datain: in std_logic_vector(31 downto 0);
dataout: buffer std_logic_vector(31 downto 0) );
end component regfile_reg;
component comparator is port(
opcode: in std_logic_vector(3 downto 0);
data_a: in std_logic_vector(31 downto 0);
data_b: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0) );
end component comparator;
component fp_mul is port(
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(31 downto 0) ); -- q
end component fp_mul;
component fp_div is port(
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(31 downto 0) ); -- q
end component fp_div;
component fp_addsub is port(
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(31 downto 0); -- q
s : out std_logic_vector(31 downto 0) ); -- s
end component fp_addsub;
component lpm_clshift
generic (
lpm_shifttype : string;
lpm_width : natural;
lpm_widthdist : natural
);
port(
data : in std_logic_vector (31 downto 0);
direction : in std_logic ;
distance : in std_logic_vector (4 downto 0);
result : out std_logic_vector (31 downto 0)
);
end component;
component lpm_mult
generic (
lpm_hint : string;
lpm_representation : string;
lpm_widtha : natural;
lpm_widthb : natural;
lpm_widthp : natural
);
port (
datab : in std_logic_vector (31 downto 0);
dataa : in std_logic_vector (31 downto 0);
result : out std_logic_vector (63 downto 0)
);
end component;
component lpm_divide
generic (
lpm_drepresentation : string;
lpm_hint : string;
lpm_nrepresentation : string;
lpm_pipeline : natural;
lpm_widthd : natural;
lpm_widthn : natural
);
port (
aclr : in std_logic ;
clock : in std_logic ;
remain : out std_logic_vector (31 downto 0);
denom : in std_logic_vector (31 downto 0);
numer : in std_logic_vector (31 downto 0);
quotient : out std_logic_vector (31 downto 0)
);
end component;
-- main bus signals
signal data_a, data_b, data_c: std_logic_vector(31 downto 0) := x"00000000" ;
-- partial results
signal
result_fpsub, result_fpmul, result_fpdiv, result_fpadd, result_log,
result_rot, result_ari, divu_res, divs_res,
divu_remain, divs_remain, add_res, sub_res, inc_res, dec_res, and_res,
or_res, xor_res, mvil_res, mvih_res, not_res
: std_logic_vector(31 downto 0) := x"00000000" ;
signal
mulu_res, muls_res
: std_logic_vector(63 downto 0) := x"0000000000000000" ;
-- register values
signal
reg00_q, reg01_q, reg02_q, reg03_q, reg04_q, reg05_q, reg06_q, reg07_q,
reg08_q, reg09_q, reg10_q, reg11_q, reg12_q, reg13_q, reg14_q, reg15_q
: std_logic_vector(31 downto 0) := x"00000000" ;
-- register we
signal
reg00_we, reg01_we, reg02_we, reg03_we, reg04_we, reg05_we, reg06_we, reg07_we,
reg08_we, reg09_we, reg10_we, reg11_we, reg12_we, reg13_we, reg14_we, reg15_we
: std_logic := '0';
-- results from main parts
signal
fpu_result, comp_result, alu_result, barrel_result
: std_logic_vector(31 downto 0) := x"00000000" ;
signal
regfile_a, regfile_b
: std_logic_vector(31 downto 0) := x"00000000" ;
signal
zero_flag
: std_logic_vector(15 downto 0) := x"0000" ;
signal instruction_word: std_logic_vector(31 downto 0) := x"00000000" ;
signal res_sync: std_logic := '0';
--control signals from ID
signal instr_opcode: std_logic_vector(7 downto 0) := x"00";
signal data_c_sel: std_logic_vector(2 downto 0) := "000";
signal data_a_sel: std_logic_vector(3 downto 0) := x"0";
signal data_b_sel: std_logic_vector(2 downto 0) := "000";
signal force_we_reg_14: std_logic := '0';
signal inc_r14, inc_r15, dec_r15: std_logic := '0';
signal instruction_we: std_logic := '0';
signal regfile_c_we: std_logic := '0';
signal flag: std_logic := '0';
begin
-- instruction register
instr_reg0: process(clk) is
variable instruction_var: std_logic_vector(31 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
instruction_var := (others => '0');
elsif instruction_we = '1' then
instruction_var := data_miso;
end if;
end if;
instruction_word <= instruction_var;
end process;
-- Synchronize reset for some MF
process(clk) is
variable res_v1: std_logic;
variable res_v2: std_logic;
begin
if rising_edge(clk) then
res_v2 := res_v1;
res_v1 := res;
end if;
res_sync <= res_v2;
end process;
-- Initialize FP cores
-- 00 - subtraction - 1 cycles
-- 01 - multiplication - 2 cycles
-- 10 - division - 8 cycles
-- 11 - addition - 1 cycles
fpmul0: fp_mul
port map(clk, res_sync, data_a, data_b, result_fpmul);
fpdiv0: fp_div
port map(clk, res_sync, data_a, data_b, result_fpdiv);
fpadd0: fp_addsub
port map(clk, res_sync, data_a, data_b, result_fpadd, result_fpsub);
fpu_result <=
result_fpsub when (instruction_word(21 downto 20) = "00") else
result_fpmul when (instruction_word(21 downto 20) = "01") else
result_fpdiv when (instruction_word(21 downto 20) = "10") else
result_fpadd;
-- barrel cores
shift_log_0: lpm_clshift
generic map ("logical", 32, 5)
port map (data_a, instruction_word(20), data_b(4 downto 0), result_log);
shift_rot_0: lpm_clshift
generic map ("rotate", 32, 5)
port map (data_a, instruction_word(20), data_b(4 downto 0), result_rot);
shift_ari_0: lpm_clshift
generic map ("arithmetic", 32, 5)
port map (data_a, instruction_word(20), data_b(4 downto 0), result_ari);
barrel_result <=
result_log when (instruction_word(22 downto 21) = "00") else
result_rot when (instruction_word(22 downto 21) = "01") else
result_ari;
-- ALU
mul_unsigned_0 : lpm_mult
generic map ("maximize_speed=9", "unsigned", 32, 32, 64)
port map (data_b, data_a, mulu_res);
mul_signed_0 : lpm_mult
generic map ("maximize_speed=9", "signed", 32, 32, 64)
port map (data_b, data_a, muls_res);
div_unsigned_0: lpm_divide
generic map ("unsigned", "maximize_speed=9,lpm_remainderpositive=true", "unsigned", 16, 32, 32)
port map (res_sync, clk,divu_remain, data_b, data_a, divu_res);
div_signed_0: lpm_divide
generic map ("signed", "maximize_speed=9,lpm_remainderpositive=true", "signed", 16, 32, 32)
port map (res_sync, clk,divs_remain, data_b, data_a, divs_res);
--add
add_res <= std_logic_vector(unsigned(data_a) + unsigned(data_b));
--sub
sub_res <= std_logic_vector(unsigned(data_a) - unsigned(data_b));
--inc
inc_res <= std_logic_vector(unsigned(data_a) + 1);
--dec
dec_res <= std_logic_vector(unsigned(data_a) - 1);
--and
and_res <= data_a and data_b;
--or
or_res <= data_a or data_b;
--xor
xor_res <= data_a xor data_b;
--not
not_res <= not(data_a);
-- alu select result
alu_result <=
mulu_res(31 downto 0) when (instruction_word(23 downto 20) = x"0") else
muls_res(31 downto 0) when (instruction_word(23 downto 20) = x"1") else
divu_res when (instruction_word(23 downto 20) = x"2") else
divs_res when (instruction_word(23 downto 20) = x"3") else
divu_remain when (instruction_word(23 downto 20) = x"4") else
divs_remain when (instruction_word(23 downto 20) = x"5") else
add_res when (instruction_word(23 downto 20) = x"6") else
sub_res when (instruction_word(23 downto 20) = x"7") else
inc_res when (instruction_word(23 downto 20) = x"8") else
dec_res when (instruction_word(23 downto 20) = x"9") else
and_res when (instruction_word(23 downto 20) = x"a") else
or_res when (instruction_word(23 downto 20) = x"b") else
xor_res when (instruction_word(23 downto 20) = x"c") else
not_res when (instruction_word(23 downto 20) = x"d") else
mulu_res(63 downto 32) when (instruction_word(23 downto 20) = x"e") else
muls_res(63 downto 32);
-- FP and INT comparator
comp0: comparator
port map(instruction_word(23 downto 20), data_a, data_b, comp_result);
-- register file
reg00_q <= (others => '0');
reg01: regfile_reg
port map(clk, res, reg01_we, '0', '0', data_c, reg01_q);
reg02: regfile_reg
port map(clk, res, reg02_we, '0', '0', data_c, reg02_q);
reg03: regfile_reg
port map(clk, res, reg03_we, '0', '0', data_c, reg03_q);
reg04: regfile_reg
port map(clk, res, reg04_we, '0', '0', data_c, reg04_q);
reg05: regfile_reg
port map(clk, res, reg05_we, '0', '0', data_c, reg05_q);
reg06: regfile_reg
port map(clk, res, reg06_we, '0', '0', data_c, reg06_q);
reg07: regfile_reg
port map(clk, res, reg07_we, '0', '0', data_c, reg07_q);
reg08: regfile_reg
port map(clk, res, reg08_we, '0', '0', data_c, reg08_q);
reg09: regfile_reg
port map(clk, res, reg09_we, '0', '0', data_c, reg09_q);
reg10: regfile_reg
port map(clk, res, reg10_we, '0', '0', data_c, reg10_q);
reg11: regfile_reg
port map(clk, res, reg11_we, '0', '0', data_c, reg11_q);
reg12: regfile_reg
port map(clk, res, reg12_we, '0', '0', data_c, reg12_q);
reg13: regfile_reg
port map(clk, res, reg13_we, '0', '0', data_c, reg13_q);
reg14: regfile_reg
port map(clk, res, reg14_we, inc_r14, '0', data_c, reg14_q);
reg15: regfile_reg
port map(clk, res, reg15_we, inc_r15, dec_r15, data_c, reg15_q);
reg01_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"1")) else '0';
reg02_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"2")) else '0';
reg03_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"3")) else '0';
reg04_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"4")) else '0';
reg05_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"5")) else '0';
reg06_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"6")) else '0';
reg07_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"7")) else '0';
reg08_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"8")) else '0';
reg09_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"9")) else '0';
reg10_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"a")) else '0';
reg11_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"b")) else '0';
reg12_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"c")) else '0';
reg13_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"d")) else '0';
reg14_we <= '1' when (((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"e")) or (force_we_reg_14 = '1')) else '0';
reg15_we <= '1' when ((regfile_c_we = '1') and (instruction_word(3 downto 0) = x"f")) else '0';
process(clk) is
begin
if rising_edge(clk) then
if res = '1' then
regfile_a <= (others => '0');
else
case instruction_word(11 downto 8) is
when x"0" => regfile_a <= reg00_q;
when x"1" => regfile_a <= reg01_q;
when x"2" => regfile_a <= reg02_q;
when x"3" => regfile_a <= reg03_q;
when x"4" => regfile_a <= reg04_q;
when x"5" => regfile_a <= reg05_q;
when x"6" => regfile_a <= reg06_q;
when x"7" => regfile_a <= reg07_q;
when x"8" => regfile_a <= reg08_q;
when x"9" => regfile_a <= reg09_q;
when x"a" => regfile_a <= reg10_q;
when x"b" => regfile_a <= reg11_q;
when x"c" => regfile_a <= reg12_q;
when x"d" => regfile_a <= reg13_q;
when x"e" => regfile_a <= reg14_q;
when others => regfile_a <= reg15_q;
end case;
end if;
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
if res = '1' then
regfile_b <= (others => '0');
else
case instruction_word(7 downto 4) is
when x"0" => regfile_b <= reg00_q;
when x"1" => regfile_b <= reg01_q;
when x"2" => regfile_b <= reg02_q;
when x"3" => regfile_b <= reg03_q;
when x"4" => regfile_b <= reg04_q;
when x"5" => regfile_b <= reg05_q;
when x"6" => regfile_b <= reg06_q;
when x"7" => regfile_b <= reg07_q;
when x"8" => regfile_b <= reg08_q;
when x"9" => regfile_b <= reg09_q;
when x"a" => regfile_b <= reg10_q;
when x"b" => regfile_b <= reg11_q;
when x"c" => regfile_b <= reg12_q;
when x"d" => regfile_b <= reg13_q;
when x"e" => regfile_b <= reg14_q;
when others => regfile_b <= reg15_q;
end case;
end if;
end if;
end process;
zero_flag(0) <= '1' when (reg00_q = x"00000000") else '0';
zero_flag(1) <= '1' when (reg01_q = x"00000000") else '0';
zero_flag(2) <= '1' when (reg02_q = x"00000000") else '0';
zero_flag(3) <= '1' when (reg03_q = x"00000000") else '0';
zero_flag(4) <= '1' when (reg04_q = x"00000000") else '0';
zero_flag(5) <= '1' when (reg05_q = x"00000000") else '0';
zero_flag(6) <= '1' when (reg06_q = x"00000000") else '0';
zero_flag(7) <= '1' when (reg07_q = x"00000000") else '0';
zero_flag(8) <= '1' when (reg08_q = x"00000000") else '0';
zero_flag(9) <= '1' when (reg09_q = x"00000000") else '0';
zero_flag(10) <= '1' when (reg10_q = x"00000000") else '0';
zero_flag(11) <= '1' when (reg11_q = x"00000000") else '0';
zero_flag(12) <= '1' when (reg12_q = x"00000000") else '0';
zero_flag(13) <= '1' when (reg13_q = x"00000000") else '0';
zero_flag(14) <= '1' when (reg14_q = x"00000000") else '0';
zero_flag(15) <= '1' when (reg15_q = x"00000000") else '0';
flag <=
zero_flag(0) when instruction_word(23 downto 20) = x"0" else
zero_flag(1) when instruction_word(23 downto 20) = x"1" else
zero_flag(2) when instruction_word(23 downto 20) = x"2" else
zero_flag(3) when instruction_word(23 downto 20) = x"3" else
zero_flag(4) when instruction_word(23 downto 20) = x"4" else
zero_flag(5) when instruction_word(23 downto 20) = x"5" else
zero_flag(6) when instruction_word(23 downto 20) = x"6" else
zero_flag(7) when instruction_word(23 downto 20) = x"7" else
zero_flag(8) when instruction_word(23 downto 20) = x"8" else
zero_flag(9) when instruction_word(23 downto 20) = x"9" else
zero_flag(10) when instruction_word(23 downto 20) = x"a" else
zero_flag(11) when instruction_word(23 downto 20) = x"b" else
zero_flag(12) when instruction_word(23 downto 20) = x"c" else
zero_flag(13) when instruction_word(23 downto 20) = x"d" else
zero_flag(14) when instruction_word(23 downto 20) = x"e" else
zero_flag(15);
data_b <=
regfile_b when data_b_sel = "000" else --register file
regfile_a when data_b_sel = "001" else --show register A on busB (speed up CALLI)
reg14_q when data_b_sel = "010" else --PC
x"00" & instruction_word(27 downto 4) when data_b_sel = "011" else --call argument format
reg00_q; --reg 0
data_a <=
x"00" & instruction_word(27 downto 4) when data_a_sel = "0000" else --mvia, call and ld format
x"00" & instruction_word(27 downto 24) & instruction_word(19 downto 0) when data_a_sel = "0001" else --branch format
x"00" & instruction_word(27 downto 8) & instruction_word(3 downto 0) when data_a_sel = "0010" else --st format
x"0000" & instruction_word(23 downto 8) when data_a_sel = "0011" else --mvih mvil
x"00" & int_address when data_a_sel = "0100" else --interrupt addr
reg14_q when data_a_sel = "0101" else --PC
reg15_q when data_a_sel = "0110" else --SP
x"00" & std_logic_vector(unsigned(reg15_q(23 downto 0)) + 1) when data_a_sel = "0111" else --SP+1
x"00" & std_logic_vector(unsigned(reg15_q(23 downto 0)) - 1) when data_a_sel = "1000" else --SP-1
regfile_a; --register file
data_c <=
fpu_result when data_c_sel = "000" else --fpu
comp_result when data_c_sel = "001" else --comparator
alu_result when data_c_sel = "010" else --alu
barrel_result when data_c_sel = "011" else --barrel
data_miso when data_c_sel = "100" else --miso bus
data_b(31 downto 16) & data_a(15 downto 0) when data_c_sel = "101" else --alu mvil
data_a(15 downto 0) & data_b(15 downto 0) when data_c_sel = "110" else --alu mvih
data_a or data_b; --alu A or B
address <= data_a(23 downto 0);
data_mosi <= data_b;
id0: id
port map(
clk, res, instruction_word(31 downto 24), flag, ack, int, swirq, we, oe,
int_accept, int_completed, data_c_sel, data_a_sel, data_b_sel,
force_we_reg_14, inc_r14, inc_r15, dec_r15, instruction_we,
regfile_c_we
);
end architecture cpu_arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity regfile_reg is
port(
clk: in std_logic;
res: in std_logic;
we: in std_logic;
inc: in std_logic;
dec: in std_logic;
datain: in std_logic_vector(31 downto 0);
dataout: out std_logic_vector(31 downto 0)
);
end entity regfile_reg;
architecture regfile_reg_arch of regfile_reg is begin
process(clk) is
variable reg_var: std_logic_vector(31 downto 0);
begin
if rising_edge(clk) then
if (res = '1') then
reg_var := (others => '0');
elsif (inc = '1') then
reg_var := std_logic_vector(unsigned(reg_var) + 1);
elsif (dec = '1') then
reg_var := std_logic_vector(unsigned(reg_var) - 1);
elsif (we = '1') then
reg_var := datain;
end if;
end if;
dataout <= reg_var;
end process;
end architecture regfile_reg_arch;
library ieee;
use ieee.std_logic_1164.all;
-- function opcode cycles
-- fp_aeb 0 1
-- fp_agb 1 1
-- fp_ageb 2 1
-- fp_alb 3 1
-- fp_aleb 4 1
-- fp_aneb 5 1
-- int_aeb 6 0
-- int_aneb 7 0
-- int_agb 8 0
-- int_ageb 9 0
-- int_alb A 0
-- int_aleb B 0
-- int_agb_u C 0
-- int_ageb_u D 0
-- int_alb_u E 0
-- int_aleb_u F 0
entity comparator is
port(
opcode: in std_logic_vector(3 downto 0);
data_a: in std_logic_vector(31 downto 0);
data_b: in std_logic_vector(31 downto 0);
output: out std_logic_vector(31 downto 0)
);
end entity comparator;
architecture comp_arch of comparator is
component fpcmp is port(
dataa: in std_logic_vector(31 downto 0);
datab: in std_logic_vector(31 downto 0);
aeb: buffer std_logic;
aneb: out std_logic;
agb: buffer std_logic;
ageb: out std_logic;
alb: buffer std_logic;
aleb: out std_logic );
end component fpcmp;
component intcmp is port(
dataa: in std_logic_vector(31 downto 0);
datab: in std_logic_vector(31 downto 0);
aeb: buffer std_logic;
aneb: out std_logic;
agb: buffer std_logic;
ageb: out std_logic;
alb: buffer std_logic;
aleb: out std_logic;
agb_u: buffer std_logic;
ageb_u: out std_logic;
alb_u: buffer std_logic;
aleb_u: out std_logic );
end component intcmp;
--results
signal fp_aeb, fp_agb, fp_ageb, fp_alb, fp_aleb, fp_aneb: std_logic;
signal int_aeb, int_aneb, int_agb, int_ageb, int_alb, int_aleb, int_agb_u, int_ageb_u, int_alb_u, int_aleb_u : std_logic;
signal result: std_logic;
begin
--initialize comparators
fpcmp0: fpcmp
port map(
data_a, data_b, fp_aeb, fp_aneb, fp_agb, fp_ageb, fp_alb, fp_aleb
);
intcmp0: intcmp
port map(
data_a, data_b, int_aeb, int_aneb, int_agb, int_ageb, int_alb,
int_aleb, int_agb_u, int_ageb_u, int_alb_u, int_aleb_u
);
-- result selector
result <=
fp_aeb when (opcode = x"0") else
fp_agb when (opcode = x"1") else
fp_ageb when (opcode = x"2") else
fp_alb when (opcode = x"3") else
fp_aleb when (opcode = x"4") else
fp_aneb when (opcode = x"5") else
int_aeb when (opcode = x"6") else
int_aneb when (opcode = x"7") else
int_agb when (opcode = x"8") else
int_ageb when (opcode = x"9") else
int_alb when (opcode = x"A") else
int_aleb when (opcode = x"B") else
int_agb_u when (opcode = x"C") else
int_ageb_u when (opcode = x"D") else
int_alb_u when (opcode = x"E") else
int_aleb_u;
-- output generator
output <= (x"0000000" & "000" & result);
end architecture comp_arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity intcmp is
port(
dataa: in std_logic_vector(31 downto 0);
datab: in std_logic_vector(31 downto 0);
aeb: buffer std_logic;
aneb: out std_logic;
agb: buffer std_logic;
ageb: out std_logic;
alb: buffer std_logic;
aleb: out std_logic;
agb_u: buffer std_logic;
ageb_u: out std_logic;
alb_u: buffer std_logic;
aleb_u: out std_logic
);
end entity intcmp;
architecture intcmp_arch of intcmp is begin
-- comparator for A == B
process(dataa, datab) is begin
if unsigned(dataa) = unsigned(datab) then
aeb <= '1';
else
aeb <= '0';
end if;
end process;
-- comparator for signed A > B
process(dataa, datab) is begin
if signed(dataa) > signed(datab) then
agb <= '1';
else
agb <= '0';
end if;
end process;
-- comparator for signed A < B
process(dataa, datab) is begin
if signed(dataa) < signed(datab) then
alb <= '1';
else
alb <= '0';
end if;
end process;
-- comparator for unsigned A > B
process(dataa, datab) is begin
if unsigned(dataa) > unsigned(datab) then
agb_u <= '1';
else
agb_u <= '0';
end if;
end process;
-- comparator for unsigned A < B
process(dataa, datab) is begin
if unsigned(dataa) < unsigned(datab) then
alb_u <= '1';
else
alb_u <= '0';
end if;
end process;
-- compute all others flags
aneb <= not(aeb);
ageb <= agb or aeb;
aleb <= alb or aeb;
ageb_u <= agb_u or aeb;
aleb_u <= alb_u or aeb;
end architecture intcmp_arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fpcmp is
port(
dataa: in std_logic_vector(31 downto 0);
datab: in std_logic_vector(31 downto 0);
aeb: buffer std_logic;
aneb: out std_logic;
agb: buffer std_logic;
ageb: out std_logic;
alb: buffer std_logic;
aleb: out std_logic
);
end entity fpcmp;
architecture fpcmp_arch of fpcmp is
component fp_cmp_eq is port(
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(0 downto 0) ); -- q
end component fp_cmp_eq;
component fp_cmp_gt is port(
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(0 downto 0) ); -- q
end component fp_cmp_gt;
component fp_cmp_lt is port(
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(0 downto 0) ); -- q
end component fp_cmp_lt;
signal alb_v, agb_v, aeb_v: std_logic_vector(0 downto 0);
begin
fpcmplt0: fp_cmp_lt
port map('0', '0', dataa, datab, alb_v);
fpcmpgt0: fp_cmp_gt
port map('0', '0', dataa, datab, agb_v);
fpcmpeq0: fp_cmp_eq
port map('0', '0', dataa, datab, aeb_v);
alb <= alb_v(0);
agb <= agb_v(0);
aeb <= aeb_v(0);
ageb <= agb or aeb;
aleb <= alb or aeb;
aneb <= not(aeb);
end architecture fpcmp_arch;
|
mit
|
7a08ffb6370726f6b993de597e589b02
| 0.519416 | 3.290664 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/clock_generator_pll_s8_diff.vhd
| 1 | 10,329 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: clock_generator_pll_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: PLL Based clock generator. Takes in a differential clock and multiplies it
-- by the amount specified. Instantiates a BUFIO2, BUFPLL and a PLL using
-- INTERNAL feedback
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity clock_generator_pll_s8_diff is generic (
PLLD : integer := 1 ; -- Parameter to set the division factor in the PLL
PLLX : integer := 8 ; -- Parameter to set the multiplication factor in the PLL
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
CLKIN_PERIOD : real := 6.000 ; -- clock period (ns) of input clock on clkin_p
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
reset : in std_logic ; -- reset (active high)
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclk : out std_logic ; -- ioclock from BUFPLL
serdesstrobe : out std_logic ; -- serdes strobe from BUFPLL
gclk : out std_logic ; -- global clock output from BUFG x1
bufpll_lckd : out std_logic) ; -- Locked output from BUFPLL
end clock_generator_pll_s8_diff ;
architecture arch_clock_generator_pll_s8_diff of clock_generator_pll_s8_diff is
signal clkint : std_logic ; --
signal clkintb : std_logic ; --
signal dummy : std_logic ; --
signal pllout_xs : std_logic ; --
signal pllout_x1 : std_logic ; --
signal pll_lckd : std_logic ; --
signal gclk_int : std_logic ; --
signal buf_pll_lckd :std_logic ;
begin
gclk <= gclk_int ;
iob_freqgen_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => clkint);
bufio2_inst : BUFIO2 generic map(
DIVIDE => 1, -- The DIVCLK divider divide-by value; default 1
I_INVERT => FALSE,
DIVIDE_BYPASS => TRUE,
USE_DOUBLER => FALSE)
port map (
I => clkint, -- Input source clock 0 degrees
IOCLK => open, -- Output Clock for IO
DIVCLK => clkintb, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
tx_pll_adv_inst : PLL_ADV generic map(
BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized"
CLKFBOUT_MULT => PLLX, -- multiplication factor for all output clocks
CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks
CLKIN1_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1
CLKIN2_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin2
CLKOUT0_DIVIDE => 1, -- division factor for clkout0 (1 to 128)
CLKOUT0_DUTY_CYCLE => 0.5, -- duty cycle for clkout0 (0.01 to 0.99)
CLKOUT0_PHASE => 0.0, -- phase shift (degrees) for clkout0 (0.0 to 360.0)
CLKOUT1_DIVIDE => 1, -- division factor for clkout1 (1 to 128)
CLKOUT1_DUTY_CYCLE => 0.5, -- duty cycle for clkout1 (0.01 to 0.99)
CLKOUT1_PHASE => 0.0, -- phase shift (degrees) for clkout1 (0.0 to 360.0)
CLKOUT2_DIVIDE => S, -- division factor for clkout2 (1 to 128)
CLKOUT2_DUTY_CYCLE => 0.5, -- duty cycle for clkout2 (0.01 to 0.99)
CLKOUT2_PHASE => 0.0, -- phase shift (degrees) for clkout2 (0.0 to 360.0)
CLKOUT3_DIVIDE => S, -- division factor for clkout3 (1 to 128)
CLKOUT3_DUTY_CYCLE => 0.5, -- duty cycle for clkout3 (0.01 to 0.99)
CLKOUT3_PHASE => 0.0, -- phase shift (degrees) for clkout3 (0.0 to 360.0)
CLKOUT4_DIVIDE => S, -- division factor for clkout4 (1 to 128)
CLKOUT4_DUTY_CYCLE => 0.5, -- duty cycle for clkout4 (0.01 to 0.99)
CLKOUT4_PHASE => 0.0, -- phase shift (degrees) for clkout4 (0.0 to 360.0)
CLKOUT5_DIVIDE => S, -- division factor for clkout5 (1 to 128)
CLKOUT5_DUTY_CYCLE => 0.5, -- duty cycle for clkout5 (0.01 to 0.99)
CLKOUT5_PHASE => 0.0, -- phase shift (degrees) for clkout5 (0.0 to 360.0)
COMPENSATION => "INTERNAL", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
DIVCLK_DIVIDE => PLLD, -- division factor for all clocks (1 to 52)
REF_JITTER => 0.100) -- input reference jitter (0.000 to 0.999 ui%)
port map (
CLKFBDCM => open, -- output feedback signal used when pll feeds a dcm
CLKFBOUT => dummy, -- general output feedback signal
CLKOUT0 => pllout_xs, -- x7 clock for transmitter
CLKOUT1 => open, --
CLKOUT2 => pllout_x1, -- x1 clock for BUFG
CLKOUT3 => open, -- x2 clock for BUFG
CLKOUT4 => open, -- one of six general clock output signals
CLKOUT5 => open, -- one of six general clock output signals
CLKOUTDCM0 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM1 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM2 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM3 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM4 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM5 => open, -- one of six clock outputs to connect to the dcm
DO => open, -- dynamic reconfig data output (16-bits)
DRDY => open, -- dynamic reconfig ready output
LOCKED => pll_lckd, -- active high pll lock signal
CLKFBIN => dummy, -- clock feedback input
CLKIN1 => clkintb, -- primary clock input
CLKIN2 => '0', -- secondary clock input
CLKINSEL => '1', -- selects '1' = clkin1, '0' = clkin2
DADDR => "00000", -- dynamic reconfig address input (5-bits)
DCLK => '0', -- dynamic reconfig clock input
DEN => '0', -- dynamic reconfig enable input
DI => "0000000000000000", -- dynamic reconfig data input (16-bits)
DWE => '0', -- dynamic reconfig write enable input
RST => reset, -- asynchronous pll reset
REL => '0') ; -- used to force the state of the PFD outputs (test only)
bufg_tx_x1 : BUFG port map (I => pllout_x1, O => gclk_int ) ;
tx_bufpll_inst : BUFPLL generic map(
DIVIDE => S) -- PLLIN0 divide-by value to produce SERDESSTROBE (1 to 8); default 1
port map (
PLLIN => pllout_xs, -- PLL Clock input
GCLK => gclk_int, -- Global Clock input
LOCKED => pll_lckd, -- Clock0 locked input
IOCLK => ioclk, -- Output PLL Clock
LOCK => buf_pll_lckd, -- BUFPLL Clock and strobe locked
SERDESSTROBE => serdesstrobe) ; -- Output SERDES strobe
bufpll_lckd <= buf_pll_lckd and pll_lckd ;
end arch_clock_generator_pll_s8_diff ;
|
apache-2.0
|
d661143d79b4cf80c647808985646bea
| 0.569465 | 3.643386 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/clkgen/pll.vhd
| 1 | 16,975 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
locked <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "833",
compensate_clock => "CLK0",
inclk0_input_frequency => 40000,
intended_device_family => "MAX 10",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "30.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_sdram.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "833"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
mit
|
8a09d9a436f67045b1140e57f5ab9145
| 0.698616 | 3.316725 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/rtlLvl/AxiReaderCore.vhd
| 1 | 802 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY AxiReaderCore IS
PORT(
arRd : IN STD_LOGIC;
arVld : IN STD_LOGIC;
rRd : IN STD_LOGIC;
rVld : IN STD_LOGIC;
r_idle : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AxiReaderCore IS
TYPE rSt_t IS (rdIdle, rdData);
SIGNAL rSt : rst_t;
BEGIN
assig_process_rSt: PROCESS(arRd, arVld, rRd, rVld)
BEGIN
IF arRd = '1' THEN
IF arVld = '1' THEN
rSt <= rddata;
ELSE
rSt <= rdidle;
END IF;
ELSIF (rRd AND rVld) = '1' THEN
rSt <= rdidle;
ELSE
rSt <= rddata;
END IF;
END PROCESS;
r_idle <= '1' WHEN (rSt = rdidle) ELSE '0';
END ARCHITECTURE;
|
mit
|
b76fc42ae4a9ad04c5f8a27c6860e8a5
| 0.523691 | 3.412766 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs_pkg.vhd
| 1 | 12,122 |
package pos_calc_Consts is
constant POS_CALC_SIZE : Natural := 276;
constant ADDR_POS_CALC_DS_TBT_THRES : Natural := 16#0#;
constant POS_CALC_DS_TBT_THRES_VAL_OFFSET : Natural := 0;
constant POS_CALC_DS_TBT_THRES_RESERVED_OFFSET : Natural := 26;
constant ADDR_POS_CALC_DS_FOFB_THRES : Natural := 16#4#;
constant POS_CALC_DS_FOFB_THRES_VAL_OFFSET : Natural := 0;
constant POS_CALC_DS_FOFB_THRES_RESERVED_OFFSET : Natural := 26;
constant ADDR_POS_CALC_DS_MONIT_THRES : Natural := 16#8#;
constant POS_CALC_DS_MONIT_THRES_VAL_OFFSET : Natural := 0;
constant POS_CALC_DS_MONIT_THRES_RESERVED_OFFSET : Natural := 26;
constant ADDR_POS_CALC_KX : Natural := 16#c#;
constant POS_CALC_KX_VAL_OFFSET : Natural := 0;
constant POS_CALC_KX_RESERVED_OFFSET : Natural := 25;
constant ADDR_POS_CALC_KY : Natural := 16#10#;
constant POS_CALC_KY_VAL_OFFSET : Natural := 0;
constant POS_CALC_KY_RESERVED_OFFSET : Natural := 25;
constant ADDR_POS_CALC_KSUM : Natural := 16#14#;
constant POS_CALC_KSUM_VAL_OFFSET : Natural := 0;
constant POS_CALC_KSUM_RESERVED_OFFSET : Natural := 25;
constant ADDR_POS_CALC_DSP_CTNR_TBT : Natural := 16#18#;
constant POS_CALC_DSP_CTNR_TBT_CH01_OFFSET : Natural := 0;
constant POS_CALC_DSP_CTNR_TBT_CH23_OFFSET : Natural := 16;
constant ADDR_POS_CALC_DSP_CTNR_FOFB : Natural := 16#1c#;
constant POS_CALC_DSP_CTNR_FOFB_CH01_OFFSET : Natural := 0;
constant POS_CALC_DSP_CTNR_FOFB_CH23_OFFSET : Natural := 16;
constant ADDR_POS_CALC_DSP_CTNR1_MONIT : Natural := 16#20#;
constant POS_CALC_DSP_CTNR1_MONIT_CIC_OFFSET : Natural := 0;
constant POS_CALC_DSP_CTNR1_MONIT_CFIR_OFFSET : Natural := 16;
constant ADDR_POS_CALC_DSP_CTNR2_MONIT : Natural := 16#24#;
constant POS_CALC_DSP_CTNR2_MONIT_PFIR_OFFSET : Natural := 0;
constant POS_CALC_DSP_CTNR2_MONIT_FIR_01_OFFSET : Natural := 16;
constant ADDR_POS_CALC_DSP_ERR_CLR : Natural := 16#28#;
constant POS_CALC_DSP_ERR_CLR_TBT_OFFSET : Natural := 0;
constant POS_CALC_DSP_ERR_CLR_FOFB_OFFSET : Natural := 1;
constant POS_CALC_DSP_ERR_CLR_MONIT_PART1_OFFSET : Natural := 2;
constant POS_CALC_DSP_ERR_CLR_MONIT_PART2_OFFSET : Natural := 3;
constant ADDR_POS_CALC_DDS_CFG : Natural := 16#2c#;
constant POS_CALC_DDS_CFG_VALID_CH0_OFFSET : Natural := 0;
constant POS_CALC_DDS_CFG_TEST_DATA_OFFSET : Natural := 1;
constant POS_CALC_DDS_CFG_RESERVED_CH0_OFFSET : Natural := 2;
constant POS_CALC_DDS_CFG_VALID_CH1_OFFSET : Natural := 8;
constant POS_CALC_DDS_CFG_RESERVED_CH1_OFFSET : Natural := 9;
constant POS_CALC_DDS_CFG_VALID_CH2_OFFSET : Natural := 16;
constant POS_CALC_DDS_CFG_RESERVED_CH2_OFFSET : Natural := 17;
constant POS_CALC_DDS_CFG_VALID_CH3_OFFSET : Natural := 24;
constant POS_CALC_DDS_CFG_RESERVED_CH3_OFFSET : Natural := 25;
constant ADDR_POS_CALC_DDS_PINC_CH0 : Natural := 16#30#;
constant POS_CALC_DDS_PINC_CH0_VAL_OFFSET : Natural := 0;
constant POS_CALC_DDS_PINC_CH0_RESERVED_OFFSET : Natural := 30;
constant ADDR_POS_CALC_DDS_PINC_CH1 : Natural := 16#34#;
constant POS_CALC_DDS_PINC_CH1_VAL_OFFSET : Natural := 0;
constant POS_CALC_DDS_PINC_CH1_RESERVED_OFFSET : Natural := 30;
constant ADDR_POS_CALC_DDS_PINC_CH2 : Natural := 16#38#;
constant POS_CALC_DDS_PINC_CH2_VAL_OFFSET : Natural := 0;
constant POS_CALC_DDS_PINC_CH2_RESERVED_OFFSET : Natural := 30;
constant ADDR_POS_CALC_DDS_PINC_CH3 : Natural := 16#3c#;
constant POS_CALC_DDS_PINC_CH3_VAL_OFFSET : Natural := 0;
constant POS_CALC_DDS_PINC_CH3_RESERVED_OFFSET : Natural := 30;
constant ADDR_POS_CALC_DDS_POFF_CH0 : Natural := 16#40#;
constant POS_CALC_DDS_POFF_CH0_VAL_OFFSET : Natural := 0;
constant POS_CALC_DDS_POFF_CH0_RESERVED_OFFSET : Natural := 30;
constant ADDR_POS_CALC_DDS_POFF_CH1 : Natural := 16#44#;
constant POS_CALC_DDS_POFF_CH1_VAL_OFFSET : Natural := 0;
constant POS_CALC_DDS_POFF_CH1_RESERVED_OFFSET : Natural := 30;
constant ADDR_POS_CALC_DDS_POFF_CH2 : Natural := 16#48#;
constant POS_CALC_DDS_POFF_CH2_VAL_OFFSET : Natural := 0;
constant POS_CALC_DDS_POFF_CH2_RESERVED_OFFSET : Natural := 30;
constant ADDR_POS_CALC_DDS_POFF_CH3 : Natural := 16#4c#;
constant POS_CALC_DDS_POFF_CH3_VAL_OFFSET : Natural := 0;
constant POS_CALC_DDS_POFF_CH3_RESERVED_OFFSET : Natural := 30;
constant ADDR_POS_CALC_DSP_MONIT_AMP_CH0 : Natural := 16#50#;
constant ADDR_POS_CALC_DSP_MONIT_AMP_CH1 : Natural := 16#54#;
constant ADDR_POS_CALC_DSP_MONIT_AMP_CH2 : Natural := 16#58#;
constant ADDR_POS_CALC_DSP_MONIT_AMP_CH3 : Natural := 16#5c#;
constant ADDR_POS_CALC_DSP_MONIT_POS_X : Natural := 16#60#;
constant ADDR_POS_CALC_DSP_MONIT_POS_Y : Natural := 16#64#;
constant ADDR_POS_CALC_DSP_MONIT_POS_Q : Natural := 16#68#;
constant ADDR_POS_CALC_DSP_MONIT_POS_SUM : Natural := 16#6c#;
constant ADDR_POS_CALC_DSP_MONIT_UPDT : Natural := 16#70#;
constant ADDR_POS_CALC_DSP_MONIT1_AMP_CH0 : Natural := 16#74#;
constant ADDR_POS_CALC_DSP_MONIT1_AMP_CH1 : Natural := 16#78#;
constant ADDR_POS_CALC_DSP_MONIT1_AMP_CH2 : Natural := 16#7c#;
constant ADDR_POS_CALC_DSP_MONIT1_AMP_CH3 : Natural := 16#80#;
constant ADDR_POS_CALC_DSP_MONIT1_POS_X : Natural := 16#84#;
constant ADDR_POS_CALC_DSP_MONIT1_POS_Y : Natural := 16#88#;
constant ADDR_POS_CALC_DSP_MONIT1_POS_Q : Natural := 16#8c#;
constant ADDR_POS_CALC_DSP_MONIT1_POS_SUM : Natural := 16#90#;
constant ADDR_POS_CALC_DSP_MONIT1_UPDT : Natural := 16#94#;
constant ADDR_POS_CALC_AMPFIFO_MONIT : Natural := 16#98#;
constant POS_CALC_AMPFIFO_MONIT_SIZE : Natural := 20;
constant ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0 : Natural := 16#98#;
constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R0_AMP_CH0_OFFSET : Natural := 0;
constant ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1 : Natural := 16#9c#;
constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R1_AMP_CH1_OFFSET : Natural := 0;
constant ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2 : Natural := 16#a0#;
constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R2_AMP_CH2_OFFSET : Natural := 0;
constant ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3 : Natural := 16#a4#;
constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_R3_AMP_CH3_OFFSET : Natural := 0;
constant ADDR_POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR : Natural := 16#a8#;
constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_FULL_OFFSET : Natural := 16;
constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_EMPTY_OFFSET : Natural := 17;
constant POS_CALC_AMPFIFO_MONIT_AMPFIFO_MONIT_CSR_COUNT_OFFSET : Natural := 0;
constant ADDR_POS_CALC_POSFIFO_MONIT : Natural := 16#ac#;
constant POS_CALC_POSFIFO_MONIT_SIZE : Natural := 20;
constant ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0 : Natural := 16#ac#;
constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R0_POS_X_OFFSET : Natural := 0;
constant ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1 : Natural := 16#b0#;
constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R1_POS_Y_OFFSET : Natural := 0;
constant ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2 : Natural := 16#b4#;
constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R2_POS_Q_OFFSET : Natural := 0;
constant ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3 : Natural := 16#b8#;
constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_R3_POS_SUM_OFFSET : Natural := 0;
constant ADDR_POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR : Natural := 16#bc#;
constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_FULL_OFFSET : Natural := 16;
constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_EMPTY_OFFSET : Natural := 17;
constant POS_CALC_POSFIFO_MONIT_POSFIFO_MONIT_CSR_COUNT_OFFSET : Natural := 0;
constant ADDR_POS_CALC_AMPFIFO_MONIT1 : Natural := 16#c0#;
constant POS_CALC_AMPFIFO_MONIT1_SIZE : Natural := 20;
constant ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0 : Natural := 16#c0#;
constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R0_AMP_CH0_OFFSET : Natural := 0;
constant ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1 : Natural := 16#c4#;
constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R1_AMP_CH1_OFFSET : Natural := 0;
constant ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2 : Natural := 16#c8#;
constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R2_AMP_CH2_OFFSET : Natural := 0;
constant ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3 : Natural := 16#cc#;
constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_R3_AMP_CH3_OFFSET : Natural := 0;
constant ADDR_POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR : Natural := 16#d0#;
constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_FULL_OFFSET : Natural := 16;
constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_EMPTY_OFFSET : Natural := 17;
constant POS_CALC_AMPFIFO_MONIT1_AMPFIFO_MONIT1_CSR_COUNT_OFFSET : Natural := 0;
constant ADDR_POS_CALC_POSFIFO_MONIT1 : Natural := 16#d4#;
constant POS_CALC_POSFIFO_MONIT1_SIZE : Natural := 20;
constant ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0 : Natural := 16#d4#;
constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R0_POS_X_OFFSET : Natural := 0;
constant ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1 : Natural := 16#d8#;
constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R1_POS_Y_OFFSET : Natural := 0;
constant ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2 : Natural := 16#dc#;
constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R2_POS_Q_OFFSET : Natural := 0;
constant ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3 : Natural := 16#e0#;
constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_R3_POS_SUM_OFFSET : Natural := 0;
constant ADDR_POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR : Natural := 16#e4#;
constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_FULL_OFFSET : Natural := 16;
constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_EMPTY_OFFSET : Natural := 17;
constant POS_CALC_POSFIFO_MONIT1_POSFIFO_MONIT1_CSR_COUNT_OFFSET : Natural := 0;
constant ADDR_POS_CALC_SW_TAG : Natural := 16#e8#;
constant POS_CALC_SW_TAG_EN_OFFSET : Natural := 0;
constant POS_CALC_SW_TAG_DESYNC_CNT_RST_OFFSET : Natural := 8;
constant POS_CALC_SW_TAG_DESYNC_CNT_OFFSET : Natural := 9;
constant ADDR_POS_CALC_SW_DATA_MASK : Natural := 16#ec#;
constant POS_CALC_SW_DATA_MASK_EN_OFFSET : Natural := 0;
constant POS_CALC_SW_DATA_MASK_SAMPLES_OFFSET : Natural := 1;
constant ADDR_POS_CALC_TBT_TAG : Natural := 16#f0#;
constant POS_CALC_TBT_TAG_EN_OFFSET : Natural := 0;
constant POS_CALC_TBT_TAG_DLY_OFFSET : Natural := 1;
constant POS_CALC_TBT_TAG_DESYNC_CNT_RST_OFFSET : Natural := 17;
constant POS_CALC_TBT_TAG_DESYNC_CNT_OFFSET : Natural := 18;
constant ADDR_POS_CALC_TBT_DATA_MASK_CTL : Natural := 16#f4#;
constant POS_CALC_TBT_DATA_MASK_CTL_EN_OFFSET : Natural := 0;
constant ADDR_POS_CALC_TBT_DATA_MASK_SAMPLES : Natural := 16#f8#;
constant POS_CALC_TBT_DATA_MASK_SAMPLES_BEG_OFFSET : Natural := 0;
constant POS_CALC_TBT_DATA_MASK_SAMPLES_END_OFFSET : Natural := 16;
constant ADDR_POS_CALC_MONIT1_TAG : Natural := 16#fc#;
constant POS_CALC_MONIT1_TAG_EN_OFFSET : Natural := 0;
constant POS_CALC_MONIT1_TAG_DLY_OFFSET : Natural := 1;
constant POS_CALC_MONIT1_TAG_DESYNC_CNT_RST_OFFSET : Natural := 17;
constant POS_CALC_MONIT1_TAG_DESYNC_CNT_OFFSET : Natural := 18;
constant ADDR_POS_CALC_MONIT1_DATA_MASK_CTL : Natural := 16#100#;
constant POS_CALC_MONIT1_DATA_MASK_CTL_EN_OFFSET : Natural := 0;
constant ADDR_POS_CALC_MONIT1_DATA_MASK_SAMPLES : Natural := 16#104#;
constant POS_CALC_MONIT1_DATA_MASK_SAMPLES_BEG_OFFSET : Natural := 0;
constant POS_CALC_MONIT1_DATA_MASK_SAMPLES_END_OFFSET : Natural := 16;
constant ADDR_POS_CALC_MONIT_TAG : Natural := 16#108#;
constant POS_CALC_MONIT_TAG_EN_OFFSET : Natural := 0;
constant POS_CALC_MONIT_TAG_DLY_OFFSET : Natural := 1;
constant POS_CALC_MONIT_TAG_DESYNC_CNT_RST_OFFSET : Natural := 17;
constant POS_CALC_MONIT_TAG_DESYNC_CNT_OFFSET : Natural := 18;
constant ADDR_POS_CALC_MONIT_DATA_MASK_CTL : Natural := 16#10c#;
constant POS_CALC_MONIT_DATA_MASK_CTL_EN_OFFSET : Natural := 0;
constant ADDR_POS_CALC_MONIT_DATA_MASK_SAMPLES : Natural := 16#110#;
constant POS_CALC_MONIT_DATA_MASK_SAMPLES_BEG_OFFSET : Natural := 0;
constant POS_CALC_MONIT_DATA_MASK_SAMPLES_END_OFFSET : Natural := 16;
end package pos_calc_Consts;
|
lgpl-3.0
|
26138916a1b2f550407e2f17a3273060
| 0.715723 | 2.999753 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/afc_v3/dbe_bpm_gen/dbe_bpm_gen.vhd
| 1 | 283,907 |
------------------------------------------------------------------------------
-- Title : Top generic BPM design with FMC130M and FMC250 options
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-11-11
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top generic BPM design with FMC130 or FMC250 ADC boards
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-11 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Custom common cores
use work.ifc_common_pkg.all;
-- Generic cores
use work.ifc_generic_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- FMC ADC definitions
use work.fmc_adc_pkg.all;
-- DSP definitions
use work.dsp_cores_pkg.all;
-- BPM definitions
use work.bpm_cores_pkg.all;
-- Positicon Calc constants
use work.machine_pkg.all;
-- Genrams
use work.genram_pkg.all;
-- Data Acquisition core
use work.acq_core_pkg.all;
-- IP cores constants
use work.ipcores_pkg.all;
-- Meta Package
use work.synthesis_descriptor_pkg.all;
-- AXI cores
use work.pcie_cntr_axi_pkg.all;
-- Trigger Modules
use work.trigger_pkg.all;
-- Trigger Common Modules
use work.trigger_common_pkg.all;
-- AFC definitions
use work.afc_base_pkg.all;
-- AFC Acq definitions
use work.afc_base_acq_pkg.all;
-- Orbit interlock
use work.orbit_intlk_pkg.all;
-- DCC
use work.fofb_cc_pkg.all;
-- DCC wrappers
use work.fofb_ctrl_pkg.all;
entity dbe_bpm_gen is
generic(
g_fmc_adc_type : string := "FMC250M";
-- Enable RTM SFP module or not
g_WITH_RTM_SFP : boolean := false;
-- Number of RTM SFP GTs
g_NUM_SFPS : integer := 0;
-- Start index of the RTM SFP GTs
g_SFP_START_ID : integer := 4;
-- enables RTM 8SFP FOFB DCC. Is this is "true", g_WITH_P2P_FOFB_DCC is
-- automatically true, as well
g_WITH_RTM_SFP_FOFB_DCC : boolean := false;
-- Number of P2P GTs
g_NUM_P2P_GTS : integer range 1 to 8 := 4;
-- Start index of the P2P GTs
g_P2P_GT_START_ID : integer := 0;
-- Enable P2P FOFB DCC or not
g_WITH_P2P_FOFB_DCC : boolean := false
);
port(
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;
afc_fp2_clk1_p_i : in std_logic;
afc_fp2_clk1_n_i : in std_logic;
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0);
trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0);
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i : in std_logic := '0';
diag_spi_si_i : in std_logic := '0';
diag_spi_so_o : out std_logic;
diag_spi_clk_i : in std_logic := '0';
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o : out std_logic;
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b : inout std_logic;
afc_si57x_sda_b : inout std_logic;
-- Si57x oscillator output enable
afc_si57x_oe_o : out std_logic;
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b : inout std_logic;
board_i2c_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o : out std_logic;
-- spi_cs_n_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic := '0';
---------------------------------------------------------------------------
-- P2P GT pins
---------------------------------------------------------------------------
-- P2P
p2p_gt_rx_p_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '0');
p2p_gt_rx_n_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '1');
p2p_gt_tx_p_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
p2p_gt_tx_n_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
-----------------------------
-- FMC1_130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc130_1_adc_pga_o : out std_logic;
fmc130_1_adc_shdn_o : out std_logic;
fmc130_1_adc_dith_o : out std_logic;
fmc130_1_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc130_1_adc0_clk_i : in std_logic := '0';
fmc130_1_adc0_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc0_of_i : in std_logic := '0'; -- Unused
-- ADC1 LTC2208
fmc130_1_adc1_clk_i : in std_logic := '0';
fmc130_1_adc1_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc1_of_i : in std_logic := '0'; -- Unused
-- ADC2 LTC2208
fmc130_1_adc2_clk_i : in std_logic := '0';
fmc130_1_adc2_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc2_of_i : in std_logic := '0'; -- Unused
-- ADC3 LTC2208
fmc130_1_adc3_clk_i : in std_logic := '0';
fmc130_1_adc3_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc3_of_i : in std_logic := '0'; -- Unused
---- FMC General Status
--fmc130_1_prsnt_i : in std_logic := '0';
--fmc130_1_pg_m2c_i : in std_logic := '0';
--fmc130_1_clk_dir_i : in std_logic := '0';
-- Trigger
fmc130_1_trig_dir_o : out std_logic;
fmc130_1_trig_term_o : out std_logic;
fmc130_1_trig_val_p_b : inout std_logic;
fmc130_1_trig_val_n_b : inout std_logic;
-- Si571 clock gen
fmc130_1_si571_scl_pad_b : inout std_logic;
fmc130_1_si571_sda_pad_b : inout std_logic;
fmc130_1_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc130_1_spi_ad9510_cs_o : out std_logic;
fmc130_1_spi_ad9510_sclk_o : out std_logic;
fmc130_1_spi_ad9510_mosi_o : out std_logic;
fmc130_1_spi_ad9510_miso_i : in std_logic := '0';
fmc130_1_pll_function_o : out std_logic;
fmc130_1_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc130_1_fpga_clk_p_i : in std_logic := '0';
fmc130_1_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc130_1_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
fmc130_1_eeprom_scl_pad_b : inout std_logic;
fmc130_1_eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor (LM75AIMM)
fmc130_1_lm75_scl_pad_b : inout std_logic;
fmc130_1_lm75_sda_pad_b : inout std_logic;
fmc130_1_lm75_temp_alarm_i : in std_logic := '0';
-- FMC LEDs
fmc130_1_led1_o : out std_logic;
fmc130_1_led2_o : out std_logic;
fmc130_1_led3_o : out std_logic;
-----------------------------
-- FMC2_130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc130_2_adc_pga_o : out std_logic;
fmc130_2_adc_shdn_o : out std_logic;
fmc130_2_adc_dith_o : out std_logic;
fmc130_2_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc130_2_adc0_clk_i : in std_logic := '0';
fmc130_2_adc0_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc0_of_i : in std_logic := '0'; -- Unused
-- ADC1 LTC2208
fmc130_2_adc1_clk_i : in std_logic := '0';
fmc130_2_adc1_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc1_of_i : in std_logic := '0'; -- Unused
-- ADC2 LTC2208
fmc130_2_adc2_clk_i : in std_logic := '0';
fmc130_2_adc2_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc2_of_i : in std_logic := '0'; -- Unused
-- ADC3 LTC2208
fmc130_2_adc3_clk_i : in std_logic := '0';
fmc130_2_adc3_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc3_of_i : in std_logic := '0'; -- Unused
---- FMC General Status
--fmc130_2_prsnt_i : in std_logic := '0';
--fmc130_2_pg_m2c_i : in std_logic := '0';
--fmc130_2_clk_dir_i : in std_logic := '0';
-- Trigger
fmc130_2_trig_dir_o : out std_logic;
fmc130_2_trig_term_o : out std_logic;
fmc130_2_trig_val_p_b : inout std_logic;
fmc130_2_trig_val_n_b : inout std_logic;
-- Si571 clock gen
fmc130_2_si571_scl_pad_b : inout std_logic;
fmc130_2_si571_sda_pad_b : inout std_logic;
fmc130_2_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc130_2_spi_ad9510_cs_o : out std_logic;
fmc130_2_spi_ad9510_sclk_o : out std_logic;
fmc130_2_spi_ad9510_mosi_o : out std_logic;
fmc130_2_spi_ad9510_miso_i : in std_logic := '0';
fmc130_2_pll_function_o : out std_logic;
fmc130_2_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc130_2_fpga_clk_p_i : in std_logic := '0';
fmc130_2_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc130_2_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor (LM75AIMM)
fmc130_2_lm75_scl_pad_b : inout std_logic;
fmc130_2_lm75_sda_pad_b : inout std_logic;
fmc130_2_lm75_temp_alarm_i : in std_logic := '0';
-- FMC LEDs
fmc130_2_led1_o : out std_logic;
fmc130_2_led2_o : out std_logic;
fmc130_2_led3_o : out std_logic;
-----------------------------
-- FMC1_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_1_adc_clk_div_rst_p_o : out std_logic;
fmc250_1_adc_clk_div_rst_n_o : out std_logic;
fmc250_1_adc_ext_rst_n_o : out std_logic;
fmc250_1_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_1_adc_clk0_p_i : in std_logic := '0';
fmc250_1_adc_clk0_n_i : in std_logic := '0';
fmc250_1_adc_clk1_p_i : in std_logic := '0';
fmc250_1_adc_clk1_n_i : in std_logic := '0';
fmc250_1_adc_clk2_p_i : in std_logic := '0';
fmc250_1_adc_clk2_n_i : in std_logic := '0';
fmc250_1_adc_clk3_p_i : in std_logic := '0';
fmc250_1_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc250_1_adc_data_ch0_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch0_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch1_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch1_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch2_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch2_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch3_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch3_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc250_1_prsnt_i : in std_logic := '0';
--fmc250_1_pg_m2c_i : in std_logic := '0';
--fmc250_1_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_1_trig_dir_o : out std_logic;
fmc250_1_trig_term_o : out std_logic;
fmc250_1_trig_val_p_b : inout std_logic;
fmc250_1_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_1_adc_spi_clk_o : out std_logic;
fmc250_1_adc_spi_mosi_o : out std_logic;
fmc250_1_adc_spi_miso_i : in std_logic := '0';
fmc250_1_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc250_1_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc250_1_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc250_1_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc250_1_si571_scl_pad_b : inout std_logic;
fmc250_1_si571_sda_pad_b : inout std_logic;
fmc250_1_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc250_1_spi_ad9510_cs_o : out std_logic;
fmc250_1_spi_ad9510_sclk_o : out std_logic;
fmc250_1_spi_ad9510_mosi_o : out std_logic;
fmc250_1_spi_ad9510_miso_i : in std_logic := '0';
fmc250_1_pll_function_o : out std_logic;
fmc250_1_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc250_1_fpga_clk_p_i : in std_logic := '0';
fmc250_1_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc250_1_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
fmc250_1_eeprom_scl_pad_b : inout std_logic;
fmc250_1_eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_1_amc7823_spi_cs_o : out std_logic;
fmc250_1_amc7823_spi_sclk_o : out std_logic;
fmc250_1_amc7823_spi_mosi_o : out std_logic;
fmc250_1_amc7823_spi_miso_i : in std_logic := '0';
fmc250_1_amc7823_davn_i : in std_logic := '0';
-- FMC LEDs
fmc250_1_led1_o : out std_logic;
fmc250_1_led2_o : out std_logic;
fmc250_1_led3_o : out std_logic;
-----------------------------
-- FMC2_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_2_adc_clk_div_rst_p_o : out std_logic;
fmc250_2_adc_clk_div_rst_n_o : out std_logic;
fmc250_2_adc_ext_rst_n_o : out std_logic;
fmc250_2_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_2_adc_clk0_p_i : in std_logic := '0';
fmc250_2_adc_clk0_n_i : in std_logic := '0';
fmc250_2_adc_clk1_p_i : in std_logic := '0';
fmc250_2_adc_clk1_n_i : in std_logic := '0';
fmc250_2_adc_clk2_p_i : in std_logic := '0';
fmc250_2_adc_clk2_n_i : in std_logic := '0';
fmc250_2_adc_clk3_p_i : in std_logic := '0';
fmc250_2_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc250_2_adc_data_ch0_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch0_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch1_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch1_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch2_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch2_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch3_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch3_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc250_2_prsnt_i : in std_logic := '0';
--fmc250_2_pg_m2c_i : in std_logic := '0';
--fmc250_2_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_2_trig_dir_o : out std_logic;
fmc250_2_trig_term_o : out std_logic;
fmc250_2_trig_val_p_b : inout std_logic;
fmc250_2_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_2_adc_spi_clk_o : out std_logic;
fmc250_2_adc_spi_mosi_o : out std_logic;
fmc250_2_adc_spi_miso_i : in std_logic := '0';
fmc250_2_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc250_2_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc250_2_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc250_2_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc250_2_si571_scl_pad_b : inout std_logic;
fmc250_2_si571_sda_pad_b : inout std_logic;
fmc250_2_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc250_2_spi_ad9510_cs_o : out std_logic;
fmc250_2_spi_ad9510_sclk_o : out std_logic;
fmc250_2_spi_ad9510_mosi_o : out std_logic;
fmc250_2_spi_ad9510_miso_i : in std_logic := '0';
fmc250_2_pll_function_o : out std_logic;
fmc250_2_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc250_2_fpga_clk_p_i : in std_logic := '0';
fmc250_2_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc250_2_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_2_amc7823_spi_cs_o : out std_logic;
fmc250_2_amc7823_spi_sclk_o : out std_logic;
fmc250_2_amc7823_spi_mosi_o : out std_logic;
fmc250_2_amc7823_spi_miso_i : in std_logic := '0';
fmc250_2_amc7823_davn_i : in std_logic := '0';
-- FMC LEDs
fmc250_2_led1_o : out std_logic;
fmc250_2_led2_o : out std_logic;
fmc250_2_led3_o : out std_logic;
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_1_adc_cnv_o : out std_logic;
fmcpico_1_adc_sck_o : out std_logic;
fmcpico_1_adc_sck_rtrn_i : in std_logic := '0';
fmcpico_1_adc_sdo1_i : in std_logic := '0';
fmcpico_1_adc_sdo2_i : in std_logic := '0';
fmcpico_1_adc_sdo3_i : in std_logic := '0';
fmcpico_1_adc_sdo4_i : in std_logic := '0';
fmcpico_1_adc_busy_cmn_i : in std_logic := '0';
fmcpico_1_rng_r1_o : out std_logic;
fmcpico_1_rng_r2_o : out std_logic;
fmcpico_1_rng_r3_o : out std_logic;
fmcpico_1_rng_r4_o : out std_logic;
fmcpico_1_led1_o : out std_logic;
fmcpico_1_led2_o : out std_logic;
fmcpico_1_sm_scl_o : out std_logic;
fmcpico_1_sm_sda_b : inout std_logic;
fmcpico_1_a_scl_o : out std_logic;
fmcpico_1_a_sda_b : inout std_logic;
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_2_adc_cnv_o : out std_logic;
fmcpico_2_adc_sck_o : out std_logic;
fmcpico_2_adc_sck_rtrn_i : in std_logic := '0';
fmcpico_2_adc_sdo1_i : in std_logic := '0';
fmcpico_2_adc_sdo2_i : in std_logic := '0';
fmcpico_2_adc_sdo3_i : in std_logic := '0';
fmcpico_2_adc_sdo4_i : in std_logic := '0';
fmcpico_2_adc_busy_cmn_i : in std_logic := '0';
fmcpico_2_rng_r1_o : out std_logic;
fmcpico_2_rng_r2_o : out std_logic;
fmcpico_2_rng_r3_o : out std_logic;
fmcpico_2_rng_r4_o : out std_logic;
fmcpico_2_led1_o : out std_logic;
fmcpico_2_led2_o : out std_logic;
---- Connected through FPGA MUX
--fmcpico_2_sm_scl_o : out std_logic;
--fmcpico_2_sm_sda_b : inout std_logic;
fmcpico_2_a_scl_o : out std_logic;
fmcpico_2_a_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- RTM board pins
---------------------------------------------------------------------------
-- SFP
rtm_sfp_rx_p_i : in std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID) := (others => '0');
rtm_sfp_rx_n_i : in std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID) := (others => '1');
rtm_sfp_tx_p_o : out std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID);
rtm_sfp_tx_n_o : out std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID);
-- RTM I2C.
-- SFP configuration pins, behind a I2C MAX7356. I2C addr = 1110_100 & '0' = 0xE8
-- Si570 oscillator. Input 0 of CDCLVD1212. I2C addr = 1010101 & '0' = 0x55
rtm_scl_b : inout std_logic;
rtm_sda_b : inout std_logic;
-- Si570 oscillator output enable
rtm_si570_oe_o : out std_logic;
---- Clock to RTM connector. Input 1 of CDCLVD1212. Not connected directly to
-- AFC
--rtm_rtm_sync_clk_p_o : out std_logic;
--rtm_rtm_sync_clk_n_o : out std_logic;
-- Select between input 0 or 1 or CDCLVD1212. 0 is Si570, 1 is RTM sync clock
rtm_clk_in_sel_o : out std_logic;
-- FPGA clocks from CDCLVD1212
rtm_fpga_clk1_p_i : in std_logic := '0';
rtm_fpga_clk1_n_i : in std_logic := '0';
rtm_fpga_clk2_p_i : in std_logic := '0';
rtm_fpga_clk2_n_i : in std_logic := '0';
-- SFP status bits. Behind 4 74HC165, 8-parallel-in/serial-out. 4 x 8 bits.
-- The PISO chips are organized like this:
--
-- Parallel load
rtm_sfp_status_reg_pl_o : out std_logic;
-- Clock N
rtm_sfp_status_reg_clk_n_o : out std_logic;
-- Serial output
rtm_sfp_status_reg_out_i : in std_logic := '0';
-- SFP control bits. Behind 4 74HC4094D, serial-in/8-parallel-out. 5 x 8 bits.
-- The SIPO chips are organized like this:
--
-- Strobe
rtm_sfp_ctl_str_n_o : out std_logic;
-- Data input
rtm_sfp_ctl_din_n_o : out std_logic;
-- Parallel output enable
rtm_sfp_ctl_oe_n_o : out std_logic;
-- External clock from RTM to FPGA
rtm_ext_clk_p_i : in std_logic := '0';
rtm_ext_clk_n_i : in std_logic := '0'
);
end dbe_bpm_gen;
architecture rtl of dbe_bpm_gen is
function f_num_bits_adc(adc_type : string)
return natural is
begin
if (adc_type = "FMC130M") then
return 16;
elsif (adc_type = "FMC250M") then
return 16;
elsif (adc_type = "FMCPICO_1M") then
return 20;
else
return 16;
end if;
end f_num_bits_adc;
function f_num_bits_se_adc(adc_type : string)
return natural is
begin
if (adc_type = "FMC130M") then
return 16;
elsif (adc_type = "FMC250M") then
return 16;
elsif (adc_type = "FMCPICO_1M") then
-- next power of 2
return 32;
else
return 16;
end if;
end f_num_bits_se_adc;
function f_acq_channel_adc_param(adc_type : string)
return t_facq_chan_param is
variable v_facq_chan : t_facq_chan_param;
begin
if (adc_type = "FMC130M") then
v_facq_chan := (width => to_unsigned(64, c_acq_chan_cmplt_width_log2),
num_atoms => to_unsigned(4, c_acq_num_atoms_width_log2),
atom_width => to_unsigned(16, c_acq_atom_width_log2) -- 2^4 = 16-bit
);
elsif (adc_type = "FMC250M") then
v_facq_chan := (width => to_unsigned(64, c_acq_chan_cmplt_width_log2),
num_atoms => to_unsigned(4, c_acq_num_atoms_width_log2),
atom_width => to_unsigned(16, c_acq_atom_width_log2) -- 2^4 = 16-bit
);
elsif (adc_type = "FMCPICO_1M") then
v_facq_chan := (width => to_unsigned(128, c_acq_chan_cmplt_width_log2),
num_atoms => to_unsigned(4, c_acq_num_atoms_width_log2),
atom_width => to_unsigned(32, c_acq_atom_width_log2) -- 2^5 = 32-bit
);
else
v_facq_chan := (width => to_unsigned(64, c_acq_chan_cmplt_width_log2),
num_atoms => to_unsigned(4, c_acq_num_atoms_width_log2),
atom_width => to_unsigned(16, c_acq_atom_width_log2) -- 2^4 = 16-bit
);
end if;
return v_facq_chan;
end f_acq_channel_adc_param;
-- FIXME: get these values from machine_pkg.vhd for each machine
function f_acq_channel_mix_param(adc_type : string)
return t_facq_chan_param is
variable v_facq_chan : t_facq_chan_param;
begin
if (adc_type = "FMC130M") then
v_facq_chan := (width => to_unsigned(128, c_acq_chan_cmplt_width_log2),
num_atoms => to_unsigned(8, c_acq_num_atoms_width_log2),
atom_width => to_unsigned(16, c_acq_atom_width_log2) -- 2^4 = 16-bit
);
elsif (adc_type = "FMC250M") then
v_facq_chan := (width => to_unsigned(128, c_acq_chan_cmplt_width_log2),
num_atoms => to_unsigned(8, c_acq_num_atoms_width_log2),
atom_width => to_unsigned(16, c_acq_atom_width_log2) -- 2^4 = 16-bit
);
elsif (adc_type = "FMCPICO_1M") then
v_facq_chan := (width => to_unsigned(256, c_acq_chan_cmplt_width_log2),
num_atoms => to_unsigned(8, c_acq_num_atoms_width_log2),
atom_width => to_unsigned(32, c_acq_atom_width_log2) -- 2^5 = 32-bit
);
else
v_facq_chan := (width => to_unsigned(128, c_acq_chan_cmplt_width_log2),
num_atoms => to_unsigned(8, c_acq_num_atoms_width_log2),
atom_width => to_unsigned(16, c_acq_atom_width_log2) -- 2^4 = 16-bit
);
end if;
return v_facq_chan;
end f_acq_channel_mix_param;
type t_gt_cfg is record
with_fp_p2p : boolean;
num_p2p_gts : integer;
max_p2p_gts : integer;
num_fp_p2p_gts : integer;
max_fp_p2p_gts : integer;
end record;
function f_extract_gt_cfg(num_p2p : integer) return t_gt_cfg is
variable rv : t_gt_cfg;
begin
rv.max_p2p_gts := 4; -- maximum
rv.max_fp_p2p_gts := 4; -- maximum
if num_p2p > 4 then
rv.with_fp_p2p := true;
rv.num_p2p_gts := 4; -- maximum
rv.max_p2p_gts := 4; -- maximum
rv.num_fp_p2p_gts := num_p2p - 4; -- remaining, up to 4
rv.max_fp_p2p_gts := 4; -- maximum
else
rv.with_fp_p2p := false;
rv.num_p2p_gts := num_p2p; -- up to 4
rv.num_fp_p2p_gts := 0; -- no FP GT
end if;
return rv;
end function;
-----------------------------------------------------------------------------
-- General constants
-----------------------------------------------------------------------------
constant c_SYS_CLOCK_FREQ : natural := 100000000;
constant c_REF_CLOCK_FREQ : natural := 69306000; -- RF*5/36
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_ADC_REF_CLK : natural := 2;
constant c_NUM_USER_IRQ : natural := 1;
-- Swap/de-swap settings
constant c_POS_CALC_DELAY_VEC_WIDTH : natural := 8;
constant c_POS_CALC_SWAP_DIV_FREQ_VEC_WIDTH : natural := 16;
constant c_AFC_SI57x_I2C_FREQ : natural := 400000;
constant c_AFC_SI57x_INIT_OSC : boolean := true;
constant c_AFC_SI57x_INIT_RFREQ_VALUE : std_logic_vector(37 downto 0) := "00" & x"2bc0af3b8";
constant c_AFC_SI57x_INIT_N1_VALUE : std_logic_vector(6 downto 0) := "0000111";
constant c_AFC_SI57x_INIT_HS_VALUE : std_logic_vector(2 downto 0) := "000";
-----------------------------------------------------------------------------
-- AFC Si57x signals
-----------------------------------------------------------------------------
signal afc_si57x_sta_reconfig_done : std_logic;
signal afc_si57x_sta_reconfig_done_pp : std_logic;
signal afc_si57x_reconfig_rst : std_logic;
signal afc_si57x_reconfig_rst_n : std_logic;
signal afc_si57x_ext_wr : std_logic;
signal afc_si57x_ext_rfreq_value : std_logic_vector(37 downto 0);
signal afc_si57x_ext_n1_value : std_logic_vector(6 downto 0);
signal afc_si57x_ext_hs_value : std_logic_vector(2 downto 0);
-----------------------------------------------------------------------------
-- RTM SFP signals
-----------------------------------------------------------------------------
-- RTM 8SFP IDs
constant c_NUM_SFPS_FOFB : integer := g_NUM_SFPS;
constant c_RTM_8SFP_NUM_CORES : natural := 1;
constant c_RTM_8SFP_0_ID : natural := 0;
constant c_SLV_RTM_8SFP_CORE_IDS : t_num_array(c_RTM_8SFP_NUM_CORES-1 downto 0) :=
f_gen_ramp(0, c_RTM_8SFP_NUM_CORES);
constant c_RTM_SI57x_I2C_FREQ : integer := 400000;
constant c_RTM_SI57x_INIT_OSC : boolean := true;
constant c_RTM_SI57x_INIT_RFREQ_VALUE : std_logic_vector(37 downto 0) := "00" & x"2bc0af3b8";
constant c_RTM_SI57x_INIT_N1_VALUE : std_logic_vector(6 downto 0) := "0000111";
constant c_RTM_SI57x_INIT_HS_VALUE : std_logic_vector(2 downto 0) := "000";
-- Wishbone bus from user afc_base_acq to RTM
signal wb_rtm_master_out : t_wishbone_master_out_array(c_RTM_8SFP_NUM_CORES-1 downto 0);
signal wb_rtm_master_in : t_wishbone_master_in_array(c_RTM_8SFP_NUM_CORES-1 downto 0);
-- Fix SFP inversion from 1 to 8 to 8 to 1
signal rtm_sfp_fix_rx_p : std_logic_vector(c_NUM_SFPS_FOFB-1 downto 0);
signal rtm_sfp_fix_rx_n : std_logic_vector(c_NUM_SFPS_FOFB-1 downto 0);
signal rtm_sfp_fix_tx_p : std_logic_vector(c_NUM_SFPS_FOFB-1 downto 0);
signal rtm_sfp_fix_tx_n : std_logic_vector(c_NUM_SFPS_FOFB-1 downto 0);
-- SFPs to FOFB controller
signal rtm_sfp_rx_p : std_logic_vector(c_NUM_SFPS_FOFB-1 downto 0);
signal rtm_sfp_rx_n : std_logic_vector(c_NUM_SFPS_FOFB-1 downto 0);
signal rtm_sfp_tx_p : std_logic_vector(c_NUM_SFPS_FOFB-1 downto 0);
signal rtm_sfp_tx_n : std_logic_vector(c_NUM_SFPS_FOFB-1 downto 0);
signal rtm_clk1_p : std_logic;
signal rtm_clk1_n : std_logic;
signal rtm_clk2_p : std_logic;
signal rtm_clk2_n : std_logic;
signal rtm_ext_clk_p : std_logic;
signal rtm_ext_clk_n : std_logic;
signal rtm_sta_reconfig_done : std_logic;
signal rtm_sta_reconfig_done_pp : std_logic;
signal rtm_reconfig_rst : std_logic;
signal rtm_reconfig_rst_n : std_logic;
signal rtm_ext_wr : std_logic;
signal rtm_ext_rfreq_value : std_logic_vector(37 downto 0);
signal rtm_ext_n1_value : std_logic_vector(6 downto 0);
signal rtm_ext_hs_value : std_logic_vector(2 downto 0);
signal sfp_txdisable : std_logic_vector(7 downto 0) := (others => '0');
signal sfp_rs0 : std_logic_vector(7 downto 0) := (others => '0');
signal sfp_rs1 : std_logic_vector(7 downto 0) := (others => '0');
signal sfp_led1 : std_logic_vector(7 downto 0);
signal sfp_los : std_logic_vector(7 downto 0);
signal sfp_txfault : std_logic_vector(7 downto 0);
signal sfp_detect_n : std_logic_vector(7 downto 0);
signal sfp_fix_txdisable : std_logic_vector(7 downto 0) := (others => '0');
signal sfp_fix_rs0 : std_logic_vector(7 downto 0) := (others => '0');
signal sfp_fix_rs1 : std_logic_vector(7 downto 0) := (others => '0');
signal sfp_fix_led1 : std_logic_vector(7 downto 0);
signal sfp_fix_los : std_logic_vector(7 downto 0);
signal sfp_fix_txfault : std_logic_vector(7 downto 0);
signal sfp_fix_detect_n : std_logic_vector(7 downto 0);
-----------------------------------------------------------------------------
-- FOFB DCC signals
-----------------------------------------------------------------------------
-- FOFB CC
constant c_NUM_FOFB_CC_CORES : natural := 2; -- Max of RTM SFP + P2P
-- P2P GT IDs
constant c_GT_CFG : t_gt_cfg := f_extract_gt_cfg(g_NUM_P2P_GTS);
constant c_NUM_P2P_GTS : integer := c_GT_CFG.num_p2p_gts + c_GT_CFG.num_fp_p2p_gts;
constant c_FOFB_CC_P2P_ID : natural := 0;
constant c_FOFB_CC_RTM_ID : natural := 1;
constant c_BPMS : integer := 2;
constant c_FAI_DW : integer := 16;
constant c_DMUX : integer := 2;
constant c_MAX_LANE_COUNT : integer := 8;
constant c_USE_CHIPSCOPE : boolean := false;
constant c_FOFB_DCC_DATA_WIDTH : natural := 32*PacketSize;
type t_fofb_cc_logic_array is array (natural range <>) of std_logic;
type t_fofb_cc_data_fai_array is array (natural range <>) of std_logic_vector(c_FAI_DW-1 downto 0);
type t_fofb_cc_buf_addr_array is array (natural range <>) of std_logic_vector(NodeW downto 0);
type t_fofb_cc_buf_data_array is array (natural range <>) of std_logic_vector(63 downto 0);
type t_fofb_cc_node_mask_array is array (natural range <>) of std_logic_vector(NodeNum-1 downto 0);
type t_fofb_cc_std32_array is array (natural range <>) of std_logic_vector(31 downto 0);
type t_fofb_cc_std4_array is array (natural range <>) of std_logic_vector(3 downto 0);
type t_fofb_cc_fod_data_array is array (natural range <>) of std_logic_vector(c_FOFB_DCC_DATA_WIDTH-1 downto 0);
type t_fofb_cc_fod_val_array is array (natural range <>) of std_logic_vector(c_MAX_LANE_COUNT-1 downto 0);
type t_fofb_cc_rio_array is array (natural range <>) of std_logic_vector(c_MAX_LANE_COUNT-1 downto 0);
type t_fai_fa_pl_state is (IDLE, WAIT_TRIGGER, SEND_BPM_DATA);
signal fai_fa_block_start : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal fai_fa_data_valid : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal fai_fa_d : t_fofb_cc_data_fai_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => (others => '0'));
signal fai_fa_pl_data_valid_r : std_logic := '0';
signal fai_fa_pl_d_x_r : std_logic_2d_32(c_BPMS-1 downto 0) := (others => (others => '0'));
signal fai_fa_pl_d_y_r : std_logic_2d_32(c_BPMS-1 downto 0) := (others => (others => '0'));
signal fai_fa_pl_state : t_fai_fa_pl_state;
signal fai_sim_data_sel : t_fofb_cc_std4_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => (others => '0'));
signal fai_sim_enable : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '1');
signal fai_sim_trigger : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal fai_sim_trigger_internal : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal fai_sim_armed : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fai_cfg_clk : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal fai_cfg_val : t_fofb_cc_std32_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => (others => '0'));
signal fofb_userclk : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal fofb_userrst : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal fofb_userrst_n : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal timeframe_start : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal timeframe_end : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal fofb_dma_ok : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal fofb_node_mask : t_fofb_cc_node_mask_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => (others => '0'));
signal fofb_timestamp_val : t_fofb_cc_std32_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => (others => '0'));
signal fofb_link_status : t_fofb_cc_std32_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => (others => '0'));
signal fofb_cc_enable : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
(others => '0');
signal fofb_fod_dat : t_fofb_cc_fod_data_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fofb_fod_dat_val : t_fofb_cc_fod_val_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fofb_fod_dat_fs_sync : t_fofb_cc_fod_data_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fofb_fod_dat_val_fs_sync : t_fofb_cc_fod_val_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fofb_rio_rx_p : t_fofb_cc_rio_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fofb_rio_rx_n : t_fofb_cc_rio_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fofb_rio_tx_p : t_fofb_cc_rio_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fofb_rio_tx_n : t_fofb_cc_rio_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fofb_rio_tx_disable : t_fofb_cc_rio_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fofb_ref_clk_p : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fofb_ref_clk_n : t_fofb_cc_logic_array(c_NUM_FOFB_CC_CORES-1 downto 0);
signal fofb_sysreset_n : std_logic_vector(c_NUM_FOFB_CC_CORES-1 downto 0);
-----------------------------------------------------------------------------
-- Acquisition signals
-----------------------------------------------------------------------------
constant c_ACQ_FIFO_SIZE : natural := 256;
-- Type of DDR3 core interface
constant c_DDR_INTERFACE_TYPE : string := "AXIS";
constant c_ACQ_ADC_ID : natural := 0;
constant c_ACQ_ADC_SWAP_ID : natural := 1;
constant c_ACQ_MIXIQ_ID : natural := 2;
constant c_DUMMY0_ID : natural := 3;
constant c_ACQ_TBTDECIMIQ_ID : natural := 4;
constant c_DUMMY1_ID : natural := 5;
constant c_ACQ_TBT_AMP_ID : natural := 6;
constant c_ACQ_TBT_PHASE_ID : natural := 7;
constant c_ACQ_TBT_POS_ID : natural := 8;
constant c_ACQ_FOFBDECIMIQ_ID : natural := 9;
constant c_DUMMY2_ID : natural := 10;
constant c_ACQ_FOFB_AMP_ID : natural := 11;
constant c_ACQ_FOFB_PHASE_ID : natural := 12;
constant c_ACQ_FOFB_POS_ID : natural := 13;
constant c_ACQ_MONIT1_AMP_ID : natural := 14;
constant c_ACQ_MONIT1_POS_ID : natural := 15;
constant c_ACQ_MONIT_AMP_ID : natural := 16;
constant c_ACQ_MONIT_POS_ID : natural := 17;
constant c_TRIGGER_SW_CLK_ID : natural := 18;
constant c_PHASE_SYNC_TRIGGER_SLOW_ID : natural := 19;
constant c_ACQ_DCC_ID : natural := 20;
-- Number of channels per acquisition core
constant c_ACQ_NUM_CHANNELS : natural := 21; -- ADC + ADC SWAP + MIXER + TBT AMP + TBT POS +
-- FOFB AMP + FOFB POS + MONIT AMP + MONIT POS + MONIT1 AMP +
-- MONIT1 POS for each FMC + trigger ID + DCC
constant c_ACQ_POS_DDR3_WIDTH : natural := 32;
-- Acquisition core IDs
constant c_ACQ_CORE_0_ID : natural := 0;
constant c_ACQ_CORE_1_ID : natural := 1;
constant c_ACQ_CORE_2_ID : natural := 2;
constant c_ACQ_CORE_3_ID : natural := 3;
-- Number of acquisition cores. Same as the number of RTM_LAMP
-- Number of acquisition cores (FMC1, FMC2, Post Mortem 1, Post Mortem 2)
constant c_ACQ_NUM_CORES : natural := 4;
constant c_ACQ_ADDR_WIDTH : natural := c_DDR_ADDR_WIDTH;
-- Post-Mortem Acq Cores dont need Multishot. So, set them to 0
constant c_ACQ_MULTISHOT_RAM_SIZE : t_property_value_array(c_ACQ_NUM_CORES-1 downto 0) := (0, 0, 2048, 2048);
constant c_ACQ_DDR_ADDR_RES_WIDTH : natural := 32;
constant c_ACQ_DDR_ADDR_DIFF : natural := c_ACQ_DDR_ADDR_RES_WIDTH-c_DDR_ADDR_WIDTH;
constant c_ACQ_WIDTH_U64 : unsigned(c_ACQ_CHAN_CMPLT_WIDTH_LOG2-1 downto 0) :=
to_unsigned(64, c_ACQ_CHAN_CMPLT_WIDTH_LOG2);
constant c_ACQ_WIDTH_U128 : unsigned(c_ACQ_CHAN_CMPLT_WIDTH_LOG2-1 downto 0) :=
to_unsigned(128, c_ACQ_CHAN_CMPLT_WIDTH_LOG2);
constant c_ACQ_WIDTH_U256 : unsigned(c_ACQ_CHAN_CMPLT_WIDTH_LOG2-1 downto 0) :=
to_unsigned(256, c_ACQ_CHAN_CMPLT_WIDTH_LOG2);
constant c_ACQ_NUM_ATOMS_U4 : unsigned(c_ACQ_NUM_ATOMS_WIDTH_LOG2-1 downto 0) :=
to_unsigned(4, c_ACQ_NUM_ATOMS_WIDTH_LOG2);
constant c_ACQ_NUM_ATOMS_U8 : unsigned(c_ACQ_NUM_ATOMS_WIDTH_LOG2-1 downto 0) :=
to_unsigned(8, c_ACQ_NUM_ATOMS_WIDTH_LOG2);
constant c_ACQ_ATOM_WIDTH_U16 : unsigned(c_ACQ_ATOM_WIDTH_LOG2-1 downto 0) :=
to_unsigned(16, c_ACQ_ATOM_WIDTH_LOG2);
constant c_ACQ_ATOM_WIDTH_U32 : unsigned(c_ACQ_ATOM_WIDTH_LOG2-1 downto 0) :=
to_unsigned(32, c_ACQ_ATOM_WIDTH_LOG2);
constant c_FACQ_PARAMS_ADC : t_facq_chan_param := f_acq_channel_adc_param(g_FMC_ADC_TYPE);
constant c_FACQ_PARAMS_MIX : t_facq_chan_param := f_acq_channel_mix_param(g_FMC_ADC_TYPE);
constant c_FACQ_PARAMS_DCC : t_facq_chan_param := (
width => to_unsigned(128, c_ACQ_CHAN_CMPLT_WIDTH_LOG2),
num_atoms => to_unsigned(4, c_ACQ_NUM_ATOMS_WIDTH_LOG2),
atom_width => to_unsigned(32, c_ACQ_ATOM_WIDTH_LOG2)
);
constant c_FACQ_CHANNELS : t_facq_chan_param_array(c_ACQ_NUM_CHANNELS-1 downto 0) :=
(
c_ACQ_ADC_ID => c_FACQ_PARAMS_ADC,
c_ACQ_ADC_SWAP_ID => c_FACQ_PARAMS_ADC,
c_ACQ_MIXIQ_ID => c_FACQ_PARAMS_MIX,
c_DUMMY0_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_TBTDECIMIQ_ID => (width => c_ACQ_WIDTH_U256, num_atoms => c_ACQ_NUM_ATOMS_U8, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_DUMMY1_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_TBT_AMP_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_TBT_PHASE_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_TBT_POS_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_FOFBDECIMIQ_ID => (width => c_ACQ_WIDTH_U256, num_atoms => c_ACQ_NUM_ATOMS_U8, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_DUMMY2_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_FOFB_AMP_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_FOFB_PHASE_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_FOFB_POS_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_MONIT1_AMP_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_MONIT1_POS_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_MONIT_AMP_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_MONIT_POS_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
-- Unused channel, for compatibility
c_TRIGGER_SW_CLK_ID => (width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
-- Unused channel, for compatibility
c_PHASE_SYNC_TRIGGER_SLOW_ID =>
(width => c_ACQ_WIDTH_U128, num_atoms => c_ACQ_NUM_ATOMS_U4, atom_width => c_ACQ_ATOM_WIDTH_U32),
c_ACQ_DCC_ID => c_FACQ_PARAMS_DCC
);
signal acq_chan_array : t_facq_chan_array2d(c_ACQ_NUM_CORES-1 downto 0, c_ACQ_NUM_CHANNELS-1 downto 0);
-- Acquisition clocks
-- ADC clock
signal fs1_clk : std_logic;
signal fs1_clk2x : std_logic;
signal fs_ref_clk : std_logic;
signal fs_ref_clk2x : std_logic;
signal fs2_clk : std_logic;
signal fs2_clk2x : std_logic;
signal fs1_rstn : std_logic;
signal fs1_rst2xn : std_logic;
signal fs_ref_rstn : std_logic;
signal fs_ref_rst : std_logic;
signal fs_ref_rst2xn : std_logic;
signal fs2_rstn : std_logic;
signal fs2_rst2xn : std_logic;
signal fs_rstn_dbg : std_logic;
signal fs_rst2xn_dbg : std_logic;
signal fs_clk_dbg : std_logic;
signal fs_clk2x_dbg : std_logic;
signal fs_clk_array : std_logic_vector(c_ACQ_NUM_CORES-1 downto 0);
signal fs_rst_n_array : std_logic_vector(c_ACQ_NUM_CORES-1 downto 0);
signal fs_rst_array : std_logic_vector(c_ACQ_NUM_CORES-1 downto 0);
signal fs_ce_array : std_logic_vector(c_ACQ_NUM_CORES-1 downto 0);
-----------------------------------------------------------------------------
-- Trigger signals
-----------------------------------------------------------------------------
-- Trigger core IDs
constant c_TRIG_MUX_SYNC_EDGE : string := "positive";
constant c_TRIG_MUX_NUM_CHANNELS : natural := 3;
constant c_TRIG_MUX_INTERN_NUM : positive := c_TRIG_MUX_NUM_CHANNELS + c_ACQ_NUM_CHANNELS;
constant c_TRIG_MUX_OUT_RESOLVER : string := "fanout";
constant c_TRIG_MUX_IN_RESOLVER : string := "or";
constant c_TRIG_MUX_WITH_INPUT_SYNC : boolean := true;
constant c_TRIG_MUX_WITH_OUTPUT_SYNC : boolean := true;
-- Trigger RCV intern IDs
constant c_TRIG_RCV_INTERN_CHAN_1_ID : natural := 0; -- Internal Channel 1
constant c_TRIG_RCV_INTERN_CHAN_2_ID : natural := 1; -- Internal Channel 2
constant c_TRIG_RCV_INTERN_CHAN_INTLK_ID : natural := 2; -- Internal Channel 3, Interlock
constant c_TRIG_MUX_RCV_INTERN_NUM : positive := 3; -- 2 FMCs + 1 Interlock
-- Trigger core IDs
constant c_TRIG_MUX_0_ID : natural := 0;
constant c_TRIG_MUX_1_ID : natural := 1;
constant c_TRIG_MUX_2_ID : natural := 2;
constant c_TRIG_MUX_3_ID : natural := 3;
constant c_TRIG_MUX_NUM_CORES : natural := c_ACQ_NUM_CORES;
signal trig_rcv_intern : t_trig_channel_array2d(c_TRIG_MUX_NUM_CORES-1 downto 0, c_TRIG_MUX_RCV_INTERN_NUM-1 downto 0);
signal trig_pulse_transm : t_trig_channel_array2d(c_TRIG_MUX_NUM_CORES-1 downto 0, c_TRIG_MUX_INTERN_NUM-1 downto 0);
signal trig_pulse_rcv : t_trig_channel_array2d(c_TRIG_MUX_NUM_CORES-1 downto 0, c_TRIG_MUX_INTERN_NUM-1 downto 0);
signal trig_fmc1_channel_1 : t_trig_channel;
signal trig_fmc1_channel_2 : t_trig_channel;
signal trig_fmc2_channel_1 : t_trig_channel;
signal trig_fmc2_channel_2 : t_trig_channel;
signal trig_1_channel_intlk : t_trig_channel;
signal trig_2_channel_intlk : t_trig_channel;
-- Post-Mortem triggers
signal trig_fmc1_pm_channel_1 : t_trig_channel;
signal trig_fmc1_pm_channel_2 : t_trig_channel;
signal trig_fmc2_pm_channel_1 : t_trig_channel;
signal trig_fmc2_pm_channel_2 : t_trig_channel;
signal trig_1_pm_channel_intlk : t_trig_channel;
signal trig_2_pm_channel_intlk : t_trig_channel;
-----------------------------------------------------------------------------
-- User Signals
-----------------------------------------------------------------------------
constant c_WITH_RTM_SFP_FOFB_DCC : boolean := g_WITH_RTM_SFP_FOFB_DCC;
constant c_WITH_P2P_FOFB_DCC : boolean := g_WITH_P2P_FOFB_DCC or
c_WITH_RTM_SFP_FOFB_DCC;
-- FMC_ADC_1, FMC_ADC_2,
-- Position_calc_1, Posiotion_calc_2,
-- Orbit Interlock
constant c_SLV_POS_CALC_1_ID : natural := 0;
constant c_SLV_FMC_ADC_1_ID : natural := 1;
constant c_SLV_POS_CALC_2_ID : natural := 2;
constant c_SLV_FMC_ADC_2_ID : natural := 3;
constant c_SLV_ORBIT_INTLK_ID : natural := 4;
constant c_SLV_FOFB_START : natural := 5;
constant c_SLV_FOFB_CC_CORE_IDS : t_num_array(c_NUM_FOFB_CC_CORES-1 downto 0) :=
f_gen_ramp(c_SLV_FOFB_START, c_SLV_FOFB_START+c_NUM_FOFB_CC_CORES);
-- Because VHDL doesn't like non-globally static things...
--constant c_SLV_FOFB_CC_P2P_ID : natural := c_SLV_FOFB_CC_CORE_IDS(c_FOFB_CC_P2P_ID);
--constant c_SLV_FOFB_CC_RTM_ID : natural := c_SLV_FOFB_CC_CORE_IDS(c_FOFB_CC_RTM_ID);
constant c_SLV_FOFB_CC_P2P_ID : natural := 5;
constant c_SLV_FOFB_CC_RTM_ID : natural := 6;
constant c_USER_NUM_CORES : natural := 7;
-- FMC_ADC layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
constant c_FMC_ADC_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00006000");
-- Position CAlC. layout. Regs, SWAP
constant c_POS_CALC_CORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000600");
constant c_USER_SDB_RECORD_ARRAY : t_sdb_record_array(c_USER_NUM_CORES-1 downto 0) :=
(
c_SLV_POS_CALC_1_ID => f_sdb_auto_bridge(c_POS_CALC_CORE_BRIDGE_SDB, true),
c_SLV_FMC_ADC_1_ID => f_sdb_auto_bridge(c_FMC_ADC_BRIDGE_SDB, true),
c_SLV_POS_CALC_2_ID => f_sdb_auto_bridge(c_POS_CALC_CORE_BRIDGE_SDB, true),
c_SLV_FMC_ADC_2_ID => f_sdb_auto_bridge(c_FMC_ADC_BRIDGE_SDB, true),
c_SLV_ORBIT_INTLK_ID => f_sdb_auto_device(c_XWB_ORBIT_INTLK_SDB, true),
c_SLV_FOFB_CC_P2P_ID => f_sdb_auto_device(c_XWB_FOFB_CC_REGS_SDB, c_WITH_P2P_FOFB_DCC),
c_SLV_FOFB_CC_RTM_ID => f_sdb_auto_device(c_XWB_FOFB_CC_REGS_SDB, c_WITH_RTM_SFP_FOFB_DCC)
);
signal clk_sys : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal clk_aux : std_logic;
signal clk_aux_rstn : std_logic;
signal clk_aux_rst : std_logic;
signal clk_aux_raw : std_logic;
signal clk_aux_raw_rstn : std_logic;
signal clk_aux_raw_rst : std_logic;
signal clk_fp2_clk1_p : std_logic;
signal clk_fp2_clk1_n : std_logic;
signal clk_200mhz : std_logic;
signal clk_200mhz_rstn : std_logic;
signal clk_300mhz : std_logic;
signal clk_300mhz_rstn : std_logic;
signal clk_master : std_logic;
signal clk_master_rstn : std_logic;
signal clk_pcie : std_logic;
signal clk_pcie_rstn : std_logic;
signal clk_trig_ref : std_logic;
signal clk_trig_ref_rstn : std_logic;
signal pcb_rev_id : std_logic_vector(3 downto 0);
signal irq_user : std_logic_vector(c_NUM_USER_IRQ + 5 downto 6) := (others => '0');
signal trig_out : t_trig_channel_array(c_NUM_TRIG-1 downto 0);
signal trig_in : t_trig_channel_array(c_NUM_TRIG-1 downto 0) := (others => c_TRIG_CHANNEL_DUMMY);
signal trig_dbg : std_logic_vector(c_NUM_TRIG-1 downto 0);
signal trig_dbg_data_sync : std_logic_vector(c_NUM_TRIG-1 downto 0);
signal trig_dbg_data_degliteched : std_logic_vector(c_NUM_TRIG-1 downto 0);
signal user_wb_out : t_wishbone_master_out_array(c_USER_NUM_CORES-1 downto 0);
signal user_wb_in : t_wishbone_master_in_array(c_USER_NUM_CORES-1 downto 0) := (others => c_DUMMY_WB_MASTER_IN);
-----------------------------------------------------------------------------
-- DSP Signals
-----------------------------------------------------------------------------
constant c_num_unprocessed_bits : natural := f_num_bits_adc(g_fmc_adc_type);
constant c_num_unprocessed_se_bits : natural := f_num_bits_se_adc(g_fmc_adc_type);
-- FMC ADC data constants
constant c_adc_data_ch0_lsb : natural := 0;
constant c_adc_data_ch0_msb : natural := c_num_unprocessed_bits-1 + c_adc_data_ch0_lsb;
constant c_adc_data_ch1_lsb : natural := c_adc_data_ch0_msb + 1;
constant c_adc_data_ch1_msb : natural := c_num_unprocessed_bits-1 + c_adc_data_ch1_lsb;
constant c_adc_data_ch2_lsb : natural := c_adc_data_ch1_msb + 1;
constant c_adc_data_ch2_msb : natural := c_num_unprocessed_bits-1 + c_adc_data_ch2_lsb;
constant c_adc_data_ch3_lsb : natural := c_adc_data_ch2_msb + 1;
constant c_adc_data_ch3_msb : natural := c_num_unprocessed_bits-1 + c_adc_data_ch3_lsb;
-- FMC_ADC 2 Signals
signal wbs_fmc1_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc1_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc1_mmcm_lock_int : std_logic;
signal fmc1_pll_status_int : std_logic;
signal fmc1_led1_int : std_logic;
signal fmc1_led2_int : std_logic;
signal fmc1_led3_int : std_logic;
signal fmc1_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc1_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc1_data : std_logic_vector(c_num_adc_channels*c_num_unprocessed_bits-1 downto 0);
signal fmc1_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc1_adc_fast_spi_clk : std_logic;
signal fmc1_adc_fast_spi_rstn : std_logic;
signal fmc1_adc_busy : std_logic;
signal fmc1_adc_data_ch0 : std_logic_vector(c_num_unprocessed_bits-1 downto 0) := (others => '0');
signal fmc1_adc_data_ch1 : std_logic_vector(c_num_unprocessed_bits-1 downto 0) := (others => '0');
signal fmc1_adc_data_ch2 : std_logic_vector(c_num_unprocessed_bits-1 downto 0) := (others => '0');
signal fmc1_adc_data_ch3 : std_logic_vector(c_num_unprocessed_bits-1 downto 0) := (others => '0');
signal fmc1_adc_data_se_ch0 : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0) := (others => '0');
signal fmc1_adc_data_se_ch1 : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0) := (others => '0');
signal fmc1_adc_data_se_ch2 : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0) := (others => '0');
signal fmc1_adc_data_se_ch3 : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0) := (others => '0');
signal fmc1_adc_valid : std_logic := '0';
signal fmc1_debug : std_logic;
signal fmc1_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc1_rst2x_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc1_trig_hw : std_logic;
signal fmc1_trig_hw_in : std_logic;
-- FMC_ADC 1 Debug
signal fmc1_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc1_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc1_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc1_adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
-- FMC_ADC 2 Signals
signal wbs_fmc2_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc2_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc2_mmcm_lock_int : std_logic;
signal fmc2_pll_status_int : std_logic;
signal fmc2_led1_int : std_logic;
signal fmc2_led2_int : std_logic;
signal fmc2_led3_int : std_logic;
signal fmc2_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc2_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc2_data : std_logic_vector(c_num_adc_channels*c_num_unprocessed_bits-1 downto 0);
signal fmc2_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc2_adc_fast_spi_clk : std_logic;
signal fmc2_adc_fast_spi_rstn : std_logic;
signal fmc2_adc_busy : std_logic;
signal fmc2_adc_data_ch0 : std_logic_vector(c_num_unprocessed_bits-1 downto 0) := (others => '0');
signal fmc2_adc_data_ch1 : std_logic_vector(c_num_unprocessed_bits-1 downto 0) := (others => '0');
signal fmc2_adc_data_ch2 : std_logic_vector(c_num_unprocessed_bits-1 downto 0) := (others => '0');
signal fmc2_adc_data_ch3 : std_logic_vector(c_num_unprocessed_bits-1 downto 0) := (others => '0');
signal fmc2_adc_data_se_ch0 : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0) := (others => '0');
signal fmc2_adc_data_se_ch1 : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0) := (others => '0');
signal fmc2_adc_data_se_ch2 : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0) := (others => '0');
signal fmc2_adc_data_se_ch3 : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0) := (others => '0');
signal fmc2_adc_valid : std_logic := '0';
signal fmc2_debug : std_logic;
signal fmc2_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc2_rst2x_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc2_trig_hw : std_logic;
signal fmc2_trig_hw_in : std_logic;
-- FMC_ADC 2 Debug
signal fmc2_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc2_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc2_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc2_adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
-- Uncross 1 signals
signal dsp1_clk_rffe_swap : std_logic;
signal dsp1_flag1_int : std_logic;
signal dsp1_flag2_int : std_logic;
-- DSP 1 signals
signal dsp1_adc_ch0_data : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp1_adc_ch1_data : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp1_adc_ch2_data : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp1_adc_ch3_data : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp1_adc_tag : std_logic_vector(0 downto 0);
signal dsp1_adc_valid : std_logic;
signal dsp1_adc_se_ch0_data : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0);
signal dsp1_adc_se_ch1_data : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0);
signal dsp1_adc_se_ch2_data : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0);
signal dsp1_adc_se_ch3_data : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0);
signal dsp1_mixi_ch0 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp1_mixi_ch1 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp1_mixi_ch2 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp1_mixi_ch3 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp1_mix_valid : std_logic;
signal dsp1_mixq_ch0 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp1_mixq_ch1 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp1_mixq_ch2 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp1_mixq_ch3 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp1_tbtdecimi_ch0 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbtdecimi_ch1 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbtdecimi_ch2 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbtdecimi_ch3 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbtdecim_valid : std_logic;
signal dsp1_tbtdecimq_ch0 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbtdecimq_ch1 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbtdecimq_ch2 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbtdecimq_ch3 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_amp_ch0 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_amp_ch1 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_amp_ch2 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_amp_ch3 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_amp_valid : std_logic;
signal dsp1_tbt_pha_ch0 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_pha_ch1 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_pha_ch2 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_pha_ch3 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_pha_valid : std_logic;
signal dsp1_fofbdecimi_ch0 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofbdecimi_ch1 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofbdecimi_ch2 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofbdecimi_ch3 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofbdecim_valid : std_logic;
signal dsp1_fofbdecimq_ch0 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofbdecimq_ch1 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofbdecimq_ch2 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofbdecimq_ch3 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_amp_ch0 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_amp_ch1 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_amp_ch2 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_amp_ch3 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_amp_valid : std_logic;
signal dsp1_fofb_pha_ch0 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_pha_ch1 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_pha_ch2 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_pha_ch3 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_pha_valid : std_logic;
signal dsp1_monit1_amp_ch0 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit1_amp_ch1 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit1_amp_ch2 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit1_amp_ch3 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit1_amp_valid : std_logic;
signal dsp1_monit_amp_ch0 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit_amp_ch1 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit_amp_ch2 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit_amp_ch3 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit_amp_valid : std_logic;
signal dsp1_tbt_pos_x : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_pos_y : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_pos_q : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_pos_sum : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp1_tbt_pos_valid : std_logic;
signal dsp1_fofb_pos_x : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_pos_y : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_pos_q : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_pos_sum : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp1_fofb_pos_valid : std_logic;
signal dsp1_monit1_pos_x : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit1_pos_y : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit1_pos_q : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit1_pos_sum : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit1_pos_valid : std_logic;
signal dsp1_monit_pos_x : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit_pos_y : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit_pos_q : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit_pos_sum : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp1_monit_pos_valid : std_logic;
signal dsp1_dbg_cur_address : std_logic_vector(31 downto 0);
signal dsp1_dbg_adc_ch0_cond : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp1_dbg_adc_ch1_cond : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp1_dbg_adc_ch2_cond : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp1_dbg_adc_ch3_cond : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
-- Uncross 2 signals
signal dsp2_clk_rffe_swap : std_logic;
signal dsp2_flag1_int : std_logic;
signal dsp2_flag2_int : std_logic;
-- DSP 2 signals
signal dsp2_adc_ch0_data : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp2_adc_ch1_data : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp2_adc_ch2_data : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp2_adc_ch3_data : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp2_adc_tag : std_logic_vector(0 downto 0);
signal dsp2_adc_valid : std_logic;
signal dsp2_adc_se_ch0_data : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0);
signal dsp2_adc_se_ch1_data : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0);
signal dsp2_adc_se_ch2_data : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0);
signal dsp2_adc_se_ch3_data : std_logic_vector(c_num_unprocessed_se_bits-1 downto 0);
signal dsp2_mixi_ch0 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp2_mixi_ch1 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp2_mixi_ch2 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp2_mixi_ch3 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp2_mix_valid : std_logic;
signal dsp2_mixq_ch0 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp2_mixq_ch1 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp2_mixq_ch2 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp2_mixq_ch3 : std_logic_vector(c_pos_calc_IQ_width-1 downto 0);
signal dsp2_tbtdecimi_ch0 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbtdecimi_ch1 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbtdecimi_ch2 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbtdecimi_ch3 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbtdecim_valid : std_logic;
signal dsp2_tbtdecimq_ch0 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbtdecimq_ch1 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbtdecimq_ch2 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbtdecimq_ch3 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_amp_ch0 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_amp_ch1 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_amp_ch2 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_amp_ch3 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_amp_valid : std_logic;
signal dsp2_tbt_pha_ch0 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_pha_ch1 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_pha_ch2 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_pha_ch3 : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_pha_valid : std_logic;
signal dsp2_fofbdecimi_ch0 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofbdecimi_ch1 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofbdecimi_ch2 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofbdecimi_ch3 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofbdecim_valid : std_logic;
signal dsp2_fofbdecimq_ch0 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofbdecimq_ch1 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofbdecimq_ch2 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofbdecimq_ch3 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_amp_ch0 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_amp_ch1 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_amp_ch2 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_amp_ch3 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_amp_valid : std_logic;
signal dsp2_fofb_pha_ch0 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_pha_ch1 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_pha_ch2 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_pha_ch3 : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_pha_valid : std_logic;
signal dsp2_monit1_amp_ch0 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit1_amp_ch1 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit1_amp_ch2 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit1_amp_ch3 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit1_amp_valid : std_logic;
signal dsp2_monit_amp_ch0 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit_amp_ch1 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit_amp_ch2 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit_amp_ch3 : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit_amp_valid : std_logic;
signal dsp2_tbt_pos_x : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_pos_y : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_pos_q : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_pos_sum : std_logic_vector(c_pos_calc_tbt_decim_width-1 downto 0);
signal dsp2_tbt_pos_valid : std_logic;
signal dsp2_fofb_pos_x : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_pos_y : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_pos_q : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_pos_sum : std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
signal dsp2_fofb_pos_valid : std_logic;
signal dsp2_monit1_pos_x : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit1_pos_y : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit1_pos_q : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit1_pos_sum : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit1_pos_valid : std_logic;
signal dsp2_monit_pos_x : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit_pos_y : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit_pos_q : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit_pos_sum : std_logic_vector(c_pos_calc_monit_decim_width-1 downto 0);
signal dsp2_monit_pos_valid : std_logic;
signal dsp2_dbg_cur_address : std_logic_vector(31 downto 0);
signal dsp2_dbg_adc_ch0_cond : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp2_dbg_adc_ch1_cond : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp2_dbg_adc_ch2_cond : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
signal dsp2_dbg_adc_ch3_cond : std_logic_vector(c_num_unprocessed_bits-1 downto 0);
-- DSP DCC signal
subtype t_pos_calc_fofb_data is std_logic_vector(c_pos_calc_fofb_decim_width-1 downto 0);
type t_pos_calc_fofb_data_array is array(natural range <>) of t_pos_calc_fofb_data;
signal dsp1_fofb_pos_xy_in_fifo : t_pos_calc_fofb_data_array(c_BPMS-1 downto 0);
signal dsp1_fofb_pos_valid_in_fifo : std_logic;
signal dsp1_fofb_pos_xy_out_fifo_slv : std_logic_vector(c_BPMS*t_pos_calc_fofb_data'length-1 downto 0);
signal dsp1_fofb_pos_xy_out_fifo : t_pos_calc_fofb_data_array(c_BPMS-1 downto 0);
signal dsp1_fofb_pos_x_out_fifo : t_pos_calc_fofb_data;
signal dsp1_fofb_pos_y_out_fifo : t_pos_calc_fofb_data;
signal dsp1_fofb_pos_valid_out_fifo : std_logic;
signal dsp2_fofb_pos_xy_in_fifo : t_pos_calc_fofb_data_array(c_BPMS-1 downto 0);
signal dsp2_fofb_pos_valid_in_fifo : std_logic;
signal dsp2_fofb_pos_xy_out_fifo_slv : std_logic_vector(c_BPMS*t_pos_calc_fofb_data'length-1 downto 0);
signal dsp2_fofb_pos_xy_out_fifo : t_pos_calc_fofb_data_array(c_BPMS-1 downto 0);
signal dsp2_fofb_pos_x_out_fifo : t_pos_calc_fofb_data;
signal dsp2_fofb_pos_y_out_fifo : t_pos_calc_fofb_data;
signal dsp2_fofb_pos_valid_out_fifo : std_logic;
signal dsp_fofb_pos_fifo_rden : std_logic;
signal dsp_fofb_pos_rstn : std_logic;
signal dsp_fofb_pos_enable_bpm_data : std_logic;
-- Interlock signals
signal intlk_ltc : std_logic;
signal intlk : std_logic;
function f_to_slv(fofb_array : t_pos_calc_fofb_data_array) return std_logic_vector is
constant c_FOFB_ARRAY_ELEM_LENGTH : natural := fofb_array(0)'length;
variable ret : std_logic_vector((fofb_array'length * c_FOFB_ARRAY_ELEM_LENGTH) - 1 downto 0);
begin
for i in fofb_array'range loop
ret((i+1)*c_FOFB_ARRAY_ELEM_LENGTH-1 downto (i*c_FOFB_ARRAY_ELEM_LENGTH)) :=
fofb_array(i);
end loop;
return ret;
end function;
function f_to_fofb_array(fofb_slv : std_logic_vector) return t_pos_calc_fofb_data_array is
constant c_FOFB_SLV_LENGTH : natural := fofb_slv'length;
constant c_FOFB_ARRAY_LENGTH : natural := (c_FOFB_SLV_LENGTH + t_pos_calc_fofb_data'length -1)/t_pos_calc_fofb_data'length;
variable ret : t_pos_calc_fofb_data_array(c_FOFB_ARRAY_LENGTH-1 downto 0);
begin
for i in ret'range loop
ret(i) := fofb_slv((i+1)*t_pos_calc_fofb_data'length-1 downto (i*t_pos_calc_fofb_data'length));
end loop;
return ret;
end function;
begin
cmp_afc_base_acq : afc_base_acq
generic map (
g_DIVCLK_DIVIDE => 1,
g_CLKBOUT_MULT_F => 8,
g_CLK0_DIVIDE_F => 8, -- 100 MHz
g_CLK1_DIVIDE => 5, -- Must be 200 MHz
g_SYS_CLOCK_FREQ => c_SYS_CLOCK_FREQ,
-- AFC Si57x parameters
g_AFC_SI57x_I2C_FREQ => c_AFC_SI57x_I2C_FREQ,
-- Whether or not to initialize oscilator with the specified values
g_AFC_SI57x_INIT_OSC => c_AFC_SI57x_INIT_OSC,
-- Init Oscillator values
g_AFC_SI57x_INIT_RFREQ_VALUE => c_AFC_SI57x_INIT_RFREQ_VALUE,
g_AFC_SI57x_INIT_N1_VALUE => c_AFC_SI57x_INIT_N1_VALUE,
g_AFC_SI57x_INIT_HS_VALUE => c_AFC_SI57x_INIT_HS_VALUE,
-- If true, instantiate a VIC/UART/DIAG/SPI.
g_WITH_VIC => true,
g_WITH_UART_MASTER => true,
g_WITH_DIAG => true,
g_WITH_TRIGGER => true,
g_WITH_SPI => false,
g_WITH_AFC_SI57x => true,
g_WITH_BOARD_I2C => true,
g_ACQ_NUM_CORES => c_ACQ_NUM_CORES,
g_TRIG_MUX_NUM_CORES => c_TRIG_MUX_NUM_CORES,
g_USER_NUM_CORES => c_USER_NUM_CORES,
-- Acquisition module generics
g_ACQ_NUM_CHANNELS => c_ACQ_NUM_CHANNELS,
g_ACQ_MULTISHOT_RAM_SIZE => c_ACQ_MULTISHOT_RAM_SIZE,
g_ACQ_FIFO_FC_SIZE => c_ACQ_FIFO_SIZE,
g_FACQ_CHANNELS => c_FACQ_CHANNELS,
-- Trigger Mux generic
g_TRIG_MUX_SYNC_EDGE => c_TRIG_MUX_SYNC_EDGE,
g_TRIG_MUX_INTERN_NUM => c_TRIG_MUX_INTERN_NUM,
g_TRIG_MUX_RCV_INTERN_NUM => c_TRIG_MUX_RCV_INTERN_NUM,
g_TRIG_MUX_OUT_RESOLVER => c_TRIG_MUX_OUT_RESOLVER,
g_TRIG_MUX_IN_RESOLVER => c_TRIG_MUX_IN_RESOLVER,
g_TRIG_MUX_WITH_INPUT_SYNC => c_TRIG_MUX_WITH_INPUT_SYNC,
g_TRIG_MUX_WITH_OUTPUT_SYNC => c_TRIG_MUX_WITH_OUTPUT_SYNC,
-- User generic. Must be g_USER_NUM_CORES length
g_USER_SDB_RECORD_ARRAY => c_USER_SDB_RECORD_ARRAY,
-- Auxiliary clock used to sync incoming triggers in the trigger module.
-- If false, trigger will be synch'ed with clk_sys
g_WITH_AUX_CLK => true,
-- Number of user interrupts
g_NUM_USER_IRQ => c_NUM_USER_IRQ
)
port map (
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
aux_clk_p_i => aux_clk_p_i,
aux_clk_n_i => aux_clk_n_i,
afc_fp2_clk1_p_i => afc_fp2_clk1_p_i,
afc_fp2_clk1_n_i => afc_fp2_clk1_n_i,
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i => sys_rst_button_n_i,
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o => trig_dir_o,
trig_b => trig_b,
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i => diag_spi_cs_i,
diag_spi_si_i => diag_spi_si_i,
diag_spi_so_o => diag_spi_so_o,
diag_spi_clk_i => diag_spi_clk_i,
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o => adn4604_vadj2_clk_updt_n_o,
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b => afc_si57x_scl_b,
afc_si57x_sda_b => afc_si57x_sda_b,
-- Si57x oscillator output enable
afc_si57x_oe_o => afc_si57x_oe_o,
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- PCI clock and reset signals
pcie_clk_p_i => pcie_clk_p_i,
pcie_clk_n_i => pcie_clk_n_i,
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o => leds_o,
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b => board_i2c_scl_b,
board_i2c_sda_b => board_i2c_sda_b,
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o => spi_sclk_o,
-- spi_cs_n_o => spi_cs_n_o,
-- spi_mosi_o => spi_mosi_o,
-- spi_miso_i => spi_miso_i,
--
---------------------------------------------------------------------------
-- Miscellanous AFC pins
---------------------------------------------------------------------------
-- PCB version
pcb_rev_id_i => pcb_rev_id,
---------------------------------------------------------------------------
-- User part
---------------------------------------------------------------------------
-- Clocks and reset.
clk_sys_o => clk_sys,
rst_sys_n_o => clk_sys_rstn,
clk_aux_o => clk_aux,
rst_aux_n_o => clk_aux_rstn,
clk_aux_raw_o => clk_aux_raw,
rst_aux_raw_n_o => clk_aux_raw_rstn,
clk_200mhz_o => clk_200mhz,
rst_200mhz_n_o => clk_200mhz_rstn,
clk_pcie_o => clk_pcie,
rst_pcie_n_o => clk_pcie_rstn,
clk_300mhz_o => clk_300mhz,
rst_300mhz_n_o => clk_300mhz_rstn,
clk_trig_ref_o => clk_trig_ref,
rst_trig_ref_n_o => clk_trig_ref_rstn,
clk_fp2_clk1_p_o => clk_fp2_clk1_p,
clk_fp2_clk1_n_o => clk_fp2_clk1_n,
-- Interrupts
irq_user_i => irq_user,
-- Acquisition
fs_clk_array_i => fs_clk_array,
fs_ce_array_i => fs_ce_array,
fs_rst_n_array_i => fs_rst_n_array,
acq_chan_array_i => acq_chan_array,
-- Triggers -- Triggers
trig_rcv_intern_i => trig_rcv_intern,
trig_pulse_transm_i => trig_pulse_transm,
trig_pulse_rcv_o => trig_pulse_rcv,
trig_dbg_o => trig_dbg,
trig_dbg_data_sync_o => trig_dbg_data_sync,
trig_dbg_data_degliteched_o => trig_dbg_data_degliteched,
-- AFC Si57x
afc_si57x_ext_wr_i => afc_si57x_ext_wr,
afc_si57x_ext_rfreq_value_i => afc_si57x_ext_rfreq_value,
afc_si57x_ext_n1_value_i => afc_si57x_ext_n1_value,
afc_si57x_ext_hs_value_i => afc_si57x_ext_hs_value,
afc_si57x_sta_reconfig_done_o => afc_si57x_sta_reconfig_done,
afc_si57x_oe_i => '1',
afc_si57x_addr_i => "10101010",
-- The wishbone bus from the pcie/host to the application
-- LSB addresses are not available (used by the carrier).
-- For the exact used addresses see SDB Description.
-- This is a pipelined wishbone with byte granularity.
user_wb_o => user_wb_out,
user_wb_i => user_wb_in
);
pcb_rev_id <= (others => '0');
clk_aux_rst <= not clk_aux_rstn;
clk_aux_raw_rst <= not clk_aux_raw_rstn;
----------------------------------------------------------------------
-- AFC Si57x --
----------------------------------------------------------------------
-- Generate large pulse for reset
cmp_afc_si57x_gc_posedge : gc_posedge
port map (
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
data_i => afc_si57x_sta_reconfig_done,
pulse_o => afc_si57x_sta_reconfig_done_pp
);
cmp_afc_si57x_gc_extend_pulse : gc_extend_pulse
generic map (
g_width => 50000
)
port map (
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
pulse_i => afc_si57x_sta_reconfig_done_pp,
extended_o => afc_si57x_reconfig_rst
);
afc_si57x_reconfig_rst_n <= not afc_si57x_reconfig_rst;
----------------------------------------------------------------------
-- FMC ADCs --
----------------------------------------------------------------------
-- Insert more FMC ADC boards here
assert (g_fmc_adc_type = "FMC130M" or g_fmc_adc_type = "FMC250M" or g_fmc_adc_type = "FMCPICO_1M")
report "[dbe_bpm_gen] FMC ADC board must be either \'FMC130M\' or \'FMC250M\' or \'FMCPICO_1M\'"
severity Failure;
gen_fmc130 : if (g_fmc_adc_type = "FMC130M") generate
----------------------------------------------------------------------
-- FMC 130M_4CH 1 Core --
----------------------------------------------------------------------
cmp1_xwb_fmc130m_4ch : xwb_fmc130m_4ch
generic map(
g_fpga_device => "7SERIES",
g_delay_type => "VAR_LOAD",
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_with_extra_wb_reg => true,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88),
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from fmc130m_4ch.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "1111",
g_with_bufio_clk_chains => "0000",
g_with_bufr_clk_chains => "1111",
g_with_idelayctrl => false,
--g_with_idelayctrl => true,
g_use_data_chains => "1111",
--g_map_clk_data_chains => (-1,-1,-1,-1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_ADC_REF_CLK,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => user_wb_out(c_SLV_FMC_ADC_1_ID),
wb_slv_o => user_wb_in(c_SLV_FMC_ADC_1_ID),
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o => fmc130_1_adc_pga_o,
fmc_adc_shdn_o => fmc130_1_adc_shdn_o,
fmc_adc_dith_o => fmc130_1_adc_dith_o,
fmc_adc_rand_o => fmc130_1_adc_rand_o,
-- ADC0 LTC2208
fmc_adc0_clk_i => fmc130_1_adc0_clk_i,
fmc_adc0_data_i => fmc130_1_adc0_data_i,
fmc_adc0_of_i => fmc130_1_adc0_of_i,
-- ADC1 LTC2208
fmc_adc1_clk_i => fmc130_1_adc1_clk_i,
fmc_adc1_data_i => fmc130_1_adc1_data_i,
fmc_adc1_of_i => fmc130_1_adc1_of_i,
-- ADC2 LTC2208
fmc_adc2_clk_i => fmc130_1_adc2_clk_i,
fmc_adc2_data_i => fmc130_1_adc2_data_i,
fmc_adc2_of_i => fmc130_1_adc2_of_i,
-- ADC3 LTC2208
fmc_adc3_clk_i => fmc130_1_adc3_clk_i,
fmc_adc3_data_i => fmc130_1_adc3_data_i,
fmc_adc3_of_i => fmc130_1_adc3_of_i,
-- FMC General Status
--fmc_prsnt_i => fmc130_1_prsnt_i,
--fmc_pg_m2c_i => fmc130_1_pg_m2c_i,
fmc_prsnt_i => '0', -- Connected to the CPU
fmc_pg_m2c_i => '0', -- Connected to the CPU
-- Trigger
fmc_trig_dir_o => fmc130_1_trig_dir_o,
fmc_trig_term_o => fmc130_1_trig_term_o,
fmc_trig_val_p_b => fmc130_1_trig_val_p_b,
fmc_trig_val_n_b => fmc130_1_trig_val_n_b,
-- Si571 clock gen
si571_scl_pad_b => fmc130_1_si571_scl_pad_b,
si571_sda_pad_b => fmc130_1_si571_sda_pad_b,
fmc_si571_oe_o => fmc130_1_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => fmc130_1_spi_ad9510_cs_o,
spi_ad9510_sclk_o => fmc130_1_spi_ad9510_sclk_o,
spi_ad9510_mosi_o => fmc130_1_spi_ad9510_mosi_o,
spi_ad9510_miso_i => fmc130_1_spi_ad9510_miso_i,
fmc_pll_function_o => fmc130_1_pll_function_o,
fmc_pll_status_i => fmc130_1_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc130_1_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc130_1_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc130_1_clk_sel_o,
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b => eeprom_scl_pad_b,
--eeprom_sda_pad_b => eeprom_sda_pad_b,
eeprom_scl_pad_b => fmc130_1_eeprom_scl_pad_b,
eeprom_sda_pad_b => fmc130_1_eeprom_sda_pad_b,
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b => fmc130_1_lm75_scl_pad_b,
lm75_sda_pad_b => fmc130_1_lm75_sda_pad_b,
fmc_lm75_temp_alarm_i => fmc130_1_lm75_temp_alarm_i,
-- FMC LEDs
fmc_led1_o => fmc1_led1_int,
fmc_led2_o => fmc1_led2_int,
fmc_led3_o => fmc1_led3_int,
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i => '0',
fmc_ext_ref_clk2x_i => '0',
fmc_ext_ref_mmcm_locked_i => '0',
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => fmc1_clk,
adc_clk2x_o => fmc1_clk2x,
adc_rst_n_o => fmc1_rst_n,
adc_rst2x_n_o => fmc1_rst2x_n,
adc_data_o => fmc1_data,
adc_data_valid_o => fmc1_data_valid,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => fmc1_trig_hw,
trig_hw_i => fmc1_trig_hw_in,
-- General board status
fmc_mmcm_lock_o => fmc1_mmcm_lock_int,
fmc_pll_status_o => fmc1_pll_status_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc1_in_array,
wbs_source_o => wbs_fmc1_out_array,
adc_dly_debug_o => fmc1_adc_dly_debug_int,
fifo_debug_valid_o => fmc1_debug_valid_int,
fifo_debug_full_o => fmc1_debug_full_int,
fifo_debug_empty_o => fmc1_debug_empty_int
);
gen_wbs1_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc1_in_array(i) <= cc_dummy_src_com_in;
end generate;
--fmc130_1_mmcm_lock_led_o <= fmc1_mmcm_lock_int;
--fmc130_1_pll_status_led_o <= fmc1_pll_status_int;
fmc130_1_led1_o <= fmc1_led1_int;
fmc130_1_led2_o <= fmc1_led2_int;
fmc130_1_led3_o <= fmc1_led3_int;
fmc1_adc_data_ch0 <= fmc1_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb);
fmc1_adc_data_ch1 <= fmc1_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb);
fmc1_adc_data_ch2 <= fmc1_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb);
fmc1_adc_data_ch3 <= fmc1_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb);
fmc1_adc_data_se_ch0 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb)),
fmc1_adc_data_se_ch0'length));
fmc1_adc_data_se_ch1 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb)),
fmc1_adc_data_se_ch1'length));
fmc1_adc_data_se_ch2 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb)),
fmc1_adc_data_se_ch2'length));
fmc1_adc_data_se_ch3 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb)),
fmc1_adc_data_se_ch3'length));
fmc1_adc_valid <= '1';
fs1_clk <= fmc1_clk(c_ADC_REF_CLK);
fs1_rstn <= fmc1_rst_n(c_ADC_REF_CLK);
fs1_clk2x <= fmc1_clk2x(c_ADC_REF_CLK);
fs1_rst2xn <= fmc1_rst2x_n(c_ADC_REF_CLK);
-- Use ADC trigger for testing
fmc1_trig_hw_in <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_TRIGGER_SW_CLK_ID).pulse;
-- Debug clock for chipscope
fs_clk_dbg <= fs1_clk;
fs_rstn_dbg <= fs1_rstn;
fs_clk2x_dbg <= fs1_clk2x;
fs_rst2xn_dbg <= fs1_rst2xn;
----------------------------------------------------------------------
-- FMC 130M_4CH 2 Core --
----------------------------------------------------------------------
cmp2_xwb_fmc130m_4ch : xwb_fmc130m_4ch
generic map(
g_fpga_device => "7SERIES",
g_delay_type => "VAR_LOAD",
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_with_extra_wb_reg => true,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88),
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from fmc130m_4ch.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "1111",
g_with_bufio_clk_chains => "0000",
g_with_bufr_clk_chains => "1111",
g_with_idelayctrl => false,
--g_with_idelayctrl => true,
g_use_data_chains => "1111",
--g_map_clk_data_chains => (-1,-1,-1,-1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_ADC_REF_CLK,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => user_wb_out(c_SLV_FMC_ADC_2_ID),
wb_slv_o => user_wb_in(c_SLV_FMC_ADC_2_ID),
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o => fmc130_2_adc_pga_o,
fmc_adc_shdn_o => fmc130_2_adc_shdn_o,
fmc_adc_dith_o => fmc130_2_adc_dith_o,
fmc_adc_rand_o => fmc130_2_adc_rand_o,
-- ADC0 LTC2208
fmc_adc0_clk_i => fmc130_2_adc0_clk_i,
fmc_adc0_data_i => fmc130_2_adc0_data_i,
fmc_adc0_of_i => fmc130_2_adc0_of_i,
-- ADC1 LTC2208
fmc_adc1_clk_i => fmc130_2_adc1_clk_i,
fmc_adc1_data_i => fmc130_2_adc1_data_i,
fmc_adc1_of_i => fmc130_2_adc1_of_i,
-- ADC2 LTC2208
fmc_adc2_clk_i => fmc130_2_adc2_clk_i,
fmc_adc2_data_i => fmc130_2_adc2_data_i,
fmc_adc2_of_i => fmc130_2_adc2_of_i,
-- ADC3 LTC2208
fmc_adc3_clk_i => fmc130_2_adc3_clk_i,
fmc_adc3_data_i => fmc130_2_adc3_data_i,
fmc_adc3_of_i => fmc130_2_adc3_of_i,
-- FMC General Status
--fmc_prsnt_i => fmc130_2_prsnt_i,
--fmc_pg_m2c_i => fmc130_2_pg_m2c_i,
fmc_prsnt_i => '0', -- Connected to the CPU
fmc_pg_m2c_i => '0', -- Connected to the CPU
-- Trigger
fmc_trig_dir_o => fmc130_2_trig_dir_o,
fmc_trig_term_o => fmc130_2_trig_term_o,
fmc_trig_val_p_b => fmc130_2_trig_val_p_b,
fmc_trig_val_n_b => fmc130_2_trig_val_n_b,
-- Si571 clock gen
si571_scl_pad_b => fmc130_2_si571_scl_pad_b,
si571_sda_pad_b => fmc130_2_si571_sda_pad_b,
fmc_si571_oe_o => fmc130_2_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => fmc130_2_spi_ad9510_cs_o,
spi_ad9510_sclk_o => fmc130_2_spi_ad9510_sclk_o,
spi_ad9510_mosi_o => fmc130_2_spi_ad9510_mosi_o,
spi_ad9510_miso_i => fmc130_2_spi_ad9510_miso_i,
fmc_pll_function_o => fmc130_2_pll_function_o,
fmc_pll_status_i => fmc130_2_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc130_2_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc130_2_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc130_2_clk_sel_o,
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b => eeprom_scl_pad_b,
--eeprom_sda_pad_b => eeprom_sda_pad_b,
eeprom_scl_pad_b => open,
eeprom_sda_pad_b => open,
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b => fmc130_2_lm75_scl_pad_b,
lm75_sda_pad_b => fmc130_2_lm75_sda_pad_b,
fmc_lm75_temp_alarm_i => fmc130_2_lm75_temp_alarm_i,
-- FMC LEDs
fmc_led1_o => fmc2_led1_int,
fmc_led2_o => fmc2_led2_int,
fmc_led3_o => fmc2_led3_int,
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i => '0',
fmc_ext_ref_clk2x_i => '0',
fmc_ext_ref_mmcm_locked_i => '0',
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => fmc2_clk,
adc_clk2x_o => fmc2_clk2x,
adc_rst_n_o => fmc2_rst_n,
adc_rst2x_n_o => fmc2_rst2x_n,
adc_data_o => fmc2_data,
adc_data_valid_o => fmc2_data_valid,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => fmc2_trig_hw,
trig_hw_i => fmc2_trig_hw_in,
-- General board status
fmc_mmcm_lock_o => fmc2_mmcm_lock_int,
fmc_pll_status_o => fmc2_pll_status_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc2_in_array,
wbs_source_o => wbs_fmc2_out_array,
adc_dly_debug_o => fmc2_adc_dly_debug_int,
fifo_debug_valid_o => fmc2_debug_valid_int,
fifo_debug_full_o => fmc2_debug_full_int,
fifo_debug_empty_o => fmc2_debug_empty_int
);
gen_wbs2_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc2_in_array(i) <= cc_dummy_src_com_in;
end generate;
-- Only FMC 1 is connected for now
--fmc130_2_mmcm_lock_led_o <= fmc2_mmcm_lock_int;
--fmc130_2_pll_status_led_o <= fmc2_pll_status_int;
fmc130_2_led1_o <= fmc2_led1_int;
fmc130_2_led2_o <= fmc2_led2_int;
fmc130_2_led3_o <= fmc2_led3_int;
fmc2_adc_data_ch0 <= fmc2_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb);
fmc2_adc_data_ch1 <= fmc2_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb);
fmc2_adc_data_ch2 <= fmc2_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb);
fmc2_adc_data_ch3 <= fmc2_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb);
fmc2_adc_data_se_ch0 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb)),
fmc2_adc_data_se_ch0'length));
fmc2_adc_data_se_ch1 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb)),
fmc2_adc_data_se_ch1'length));
fmc2_adc_data_se_ch2 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb)),
fmc2_adc_data_se_ch2'length));
fmc2_adc_data_se_ch3 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb)),
fmc2_adc_data_se_ch3'length));
fmc2_adc_valid <= '1';
fs2_clk <= fmc2_clk(c_ADC_REF_CLK);
fs2_rstn <= fmc2_rst_n(c_ADC_REF_CLK);
fs2_clk2x <= fmc2_clk2x(c_ADC_REF_CLK);
fs2_rst2xn <= fmc2_rst2x_n(c_ADC_REF_CLK);
-- Use ADC trigger for testing
fmc2_trig_hw_in <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_TRIGGER_SW_CLK_ID).pulse;
end generate;
gen_fmc250 : if (g_fmc_adc_type = "FMC250M") generate
----------------------------------------------------------------------
-- FMC 250M_4CH 1 Core --
----------------------------------------------------------------------
cmp1_xwb_fmc250m_4ch : xwb_fmc250m_4ch
generic map(
g_fpga_device => "7SERIES",
g_delay_type => "VAR_LOAD",
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_with_extra_wb_reg => true,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (4.00, 4.00, 4.00, 4.00),
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from fmc250m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from fmc250m_4ch.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "1111",
g_with_bufio_clk_chains => "0000",
g_with_bufr_clk_chains => "1111",
g_with_idelayctrl => false,
--g_with_idelayctrl => true,
g_use_data_chains => "1111",
--g_map_clk_data_chains => (-1,-1,-1,-1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_ADC_REF_CLK,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => user_wb_out(c_SLV_FMC_ADC_1_ID),
wb_slv_o => user_wb_in(c_SLV_FMC_ADC_1_ID),
-----------------------------
-- External ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o => fmc250_1_adc_clk_div_rst_p_o,
adc_clk_div_rst_n_o => fmc250_1_adc_clk_div_rst_n_o,
adc_ext_rst_n_o => fmc250_1_adc_ext_rst_n_o,
adc_sleep_o => fmc250_1_adc_sleep_o,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i => fmc250_1_adc_clk0_p_i,
adc_clk0_n_i => fmc250_1_adc_clk0_n_i,
adc_clk1_p_i => fmc250_1_adc_clk1_p_i,
adc_clk1_n_i => fmc250_1_adc_clk1_n_i,
adc_clk2_p_i => fmc250_1_adc_clk2_p_i,
adc_clk2_n_i => fmc250_1_adc_clk2_n_i,
adc_clk3_p_i => fmc250_1_adc_clk3_p_i,
adc_clk3_n_i => fmc250_1_adc_clk3_n_i,
-- DDR ADC data channels.
adc_data_ch0_p_i => fmc250_1_adc_data_ch0_p_i,
adc_data_ch0_n_i => fmc250_1_adc_data_ch0_n_i,
adc_data_ch1_p_i => fmc250_1_adc_data_ch1_p_i,
adc_data_ch1_n_i => fmc250_1_adc_data_ch1_n_i,
adc_data_ch2_p_i => fmc250_1_adc_data_ch2_p_i,
adc_data_ch2_n_i => fmc250_1_adc_data_ch2_n_i,
adc_data_ch3_p_i => fmc250_1_adc_data_ch3_p_i,
adc_data_ch3_n_i => fmc250_1_adc_data_ch3_n_i,
-- FMC General Status
--fmc_prsnt_i => fmc250_1_prsnt_i,
--fmc_pg_m2c_i => fmc250_1_pg_m2c_i,
fmc_prsnt_i => '0', -- Connected to the CPU
fmc_pg_m2c_i => '0', -- Connected to the CPU
-- Trigger
fmc_trig_dir_o => fmc250_1_trig_dir_o,
fmc_trig_term_o => fmc250_1_trig_term_o,
fmc_trig_val_p_b => fmc250_1_trig_val_p_b,
fmc_trig_val_n_b => fmc250_1_trig_val_n_b,
-- ADC SPI control interface.
adc_spi_clk_o => fmc250_1_adc_spi_clk_o,
adc_spi_mosi_o => fmc250_1_adc_spi_mosi_o,
adc_spi_miso_i => fmc250_1_adc_spi_miso_i,
adc_spi_cs_adc0_n_o => fmc250_1_adc_spi_cs_adc0_n_o,
adc_spi_cs_adc1_n_o => fmc250_1_adc_spi_cs_adc1_n_o,
adc_spi_cs_adc2_n_o => fmc250_1_adc_spi_cs_adc2_n_o,
adc_spi_cs_adc3_n_o => fmc250_1_adc_spi_cs_adc3_n_o,
-- Si571 clock gen
si571_scl_pad_b => fmc250_1_si571_scl_pad_b,
si571_sda_pad_b => fmc250_1_si571_sda_pad_b,
fmc_si571_oe_o => fmc250_1_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => fmc250_1_spi_ad9510_cs_o,
spi_ad9510_sclk_o => fmc250_1_spi_ad9510_sclk_o,
spi_ad9510_mosi_o => fmc250_1_spi_ad9510_mosi_o,
spi_ad9510_miso_i => fmc250_1_spi_ad9510_miso_i,
fmc_pll_function_o => fmc250_1_pll_function_o,
fmc_pll_status_i => fmc250_1_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc250_1_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc250_1_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc250_1_clk_sel_o,
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b => eeprom_scl_pad_b,
--eeprom_sda_pad_b => eeprom_sda_pad_b,
eeprom_scl_pad_b => fmc250_1_eeprom_scl_pad_b,
eeprom_sda_pad_b => fmc250_1_eeprom_sda_pad_b,
-- AMC7823 temperature monitor
amc7823_spi_cs_o => fmc250_1_amc7823_spi_cs_o,
amc7823_spi_sclk_o => fmc250_1_amc7823_spi_sclk_o,
amc7823_spi_mosi_o => fmc250_1_amc7823_spi_mosi_o,
amc7823_spi_miso_i => fmc250_1_amc7823_spi_miso_i,
amc7823_davn_i => fmc250_1_amc7823_davn_i,
-- FMC LEDs
fmc_led1_o => fmc1_led1_int,
fmc_led2_o => fmc1_led2_int,
fmc_led3_o => fmc1_led3_int,
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i => '0',
fmc_ext_ref_clk2x_i => '0',
fmc_ext_ref_mmcm_locked_i => '0',
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => fmc1_clk,
adc_clk2x_o => fmc1_clk2x,
adc_rst_n_o => fmc1_rst_n,
adc_rst2x_n_o => fmc1_rst2x_n,
adc_data_o => fmc1_data,
adc_data_valid_o => fmc1_data_valid,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => fmc1_trig_hw,
trig_hw_i => fmc1_trig_hw_in,
-- General board status
fmc_mmcm_lock_o => fmc1_mmcm_lock_int,
fmc_pll_status_o => fmc1_pll_status_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc1_in_array,
wbs_source_o => wbs_fmc1_out_array,
adc_dly_debug_o => fmc1_adc_dly_debug_int,
fifo_debug_valid_o => fmc1_debug_valid_int,
fifo_debug_full_o => fmc1_debug_full_int,
fifo_debug_empty_o => fmc1_debug_empty_int
);
gen_wbs1_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc1_in_array(i) <= cc_dummy_src_com_in;
end generate;
--fmc250_1_mmcm_lock_led_o <= fmc1_mmcm_lock_int;
--fmc250_1_pll_status_led_o <= fmc1_pll_status_int;
fmc250_1_led1_o <= fmc1_led1_int;
fmc250_1_led2_o <= fmc1_led2_int;
fmc250_1_led3_o <= fmc1_led3_int;
fmc1_adc_data_ch0 <= fmc1_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb);
fmc1_adc_data_ch1 <= fmc1_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb);
fmc1_adc_data_ch2 <= fmc1_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb);
fmc1_adc_data_ch3 <= fmc1_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb);
fmc1_adc_data_se_ch0 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb)),
fmc1_adc_data_se_ch0'length));
fmc1_adc_data_se_ch1 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb)),
fmc1_adc_data_se_ch1'length));
fmc1_adc_data_se_ch2 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb)),
fmc1_adc_data_se_ch2'length));
fmc1_adc_data_se_ch3 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb)),
fmc1_adc_data_se_ch3'length));
fmc1_adc_valid <= '1';
fs1_clk <= fmc1_clk(c_ADC_REF_CLK);
fs1_rstn <= fmc1_rst_n(c_ADC_REF_CLK);
fs1_clk2x <= fmc1_clk2x(c_ADC_REF_CLK);
fs1_rst2xn <= fmc1_rst2x_n(c_ADC_REF_CLK);
-- Use ADC trigger for testing
fmc1_trig_hw_in <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_TRIGGER_SW_CLK_ID).pulse;
-- Debug clock for chipscope
fs_clk_dbg <= fs1_clk;
fs_rstn_dbg <= fs1_rstn;
fs_clk2x_dbg <= fs1_clk2x;
fs_rst2xn_dbg <= fs1_rst2xn;
----------------------------------------------------------------------
-- FMC 250M_4CH 2 Core --
----------------------------------------------------------------------
cmp2_xwb_fmc250m_4ch : xwb_fmc250m_4ch
generic map(
g_fpga_device => "7SERIES",
g_delay_type => "VAR_LOAD",
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_with_extra_wb_reg => true,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (4.00, 4.00, 4.00, 4.00),
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from fmc250m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from fmc250m_4ch.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "1111",
g_with_bufio_clk_chains => "0000",
g_with_bufr_clk_chains => "1111",
g_with_idelayctrl => false,
--g_with_idelayctrl => true,
g_use_data_chains => "1111",
--g_map_clk_data_chains => (-1,-1,-1,-1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_ADC_REF_CLK,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => user_wb_out(c_SLV_FMC_ADC_2_ID),
wb_slv_o => user_wb_in(c_SLV_FMC_ADC_2_ID),
-----------------------------
-- External ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o => fmc250_2_adc_clk_div_rst_p_o,
adc_clk_div_rst_n_o => fmc250_2_adc_clk_div_rst_n_o,
adc_ext_rst_n_o => fmc250_2_adc_ext_rst_n_o,
adc_sleep_o => fmc250_2_adc_sleep_o,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i => fmc250_2_adc_clk0_p_i,
adc_clk0_n_i => fmc250_2_adc_clk0_n_i,
adc_clk1_p_i => fmc250_2_adc_clk1_p_i,
adc_clk1_n_i => fmc250_2_adc_clk1_n_i,
adc_clk2_p_i => fmc250_2_adc_clk2_p_i,
adc_clk2_n_i => fmc250_2_adc_clk2_n_i,
adc_clk3_p_i => fmc250_2_adc_clk3_p_i,
adc_clk3_n_i => fmc250_2_adc_clk3_n_i,
-- DDR ADC data channels.
adc_data_ch0_p_i => fmc250_2_adc_data_ch0_p_i,
adc_data_ch0_n_i => fmc250_2_adc_data_ch0_n_i,
adc_data_ch1_p_i => fmc250_2_adc_data_ch1_p_i,
adc_data_ch1_n_i => fmc250_2_adc_data_ch1_n_i,
adc_data_ch2_p_i => fmc250_2_adc_data_ch2_p_i,
adc_data_ch2_n_i => fmc250_2_adc_data_ch2_n_i,
adc_data_ch3_p_i => fmc250_2_adc_data_ch3_p_i,
adc_data_ch3_n_i => fmc250_2_adc_data_ch3_n_i,
-- FMC General Status
--fmc_prsnt_i => fmc250_2_prsnt_i,
--fmc_pg_m2c_i => fmc250_2_pg_m2c_i,
fmc_prsnt_i => '0', -- Connected to the CPU
fmc_pg_m2c_i => '0', -- Connected to the CPU
-- Trigger
fmc_trig_dir_o => fmc250_2_trig_dir_o,
fmc_trig_term_o => fmc250_2_trig_term_o,
fmc_trig_val_p_b => fmc250_2_trig_val_p_b,
fmc_trig_val_n_b => fmc250_2_trig_val_n_b,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
adc_spi_clk_o => fmc250_2_adc_spi_clk_o,
adc_spi_mosi_o => fmc250_2_adc_spi_mosi_o,
adc_spi_miso_i => fmc250_2_adc_spi_miso_i,
adc_spi_cs_adc0_n_o => fmc250_2_adc_spi_cs_adc0_n_o,
adc_spi_cs_adc1_n_o => fmc250_2_adc_spi_cs_adc1_n_o,
adc_spi_cs_adc2_n_o => fmc250_2_adc_spi_cs_adc2_n_o,
adc_spi_cs_adc3_n_o => fmc250_2_adc_spi_cs_adc3_n_o,
-- Si571 clock gen
si571_scl_pad_b => fmc250_2_si571_scl_pad_b,
si571_sda_pad_b => fmc250_2_si571_sda_pad_b,
fmc_si571_oe_o => fmc250_2_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => fmc250_2_spi_ad9510_cs_o,
spi_ad9510_sclk_o => fmc250_2_spi_ad9510_sclk_o,
spi_ad9510_mosi_o => fmc250_2_spi_ad9510_mosi_o,
spi_ad9510_miso_i => fmc250_2_spi_ad9510_miso_i,
fmc_pll_function_o => fmc250_2_pll_function_o,
fmc_pll_status_i => fmc250_2_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc250_2_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc250_2_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc250_2_clk_sel_o,
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b => eeprom_scl_pad_b,
--eeprom_sda_pad_b => eeprom_sda_pad_b,
eeprom_scl_pad_b => open,
eeprom_sda_pad_b => open,
-- AMC7823 temperature monitor
amc7823_spi_cs_o => fmc250_2_amc7823_spi_cs_o,
amc7823_spi_sclk_o => fmc250_2_amc7823_spi_sclk_o,
amc7823_spi_mosi_o => fmc250_2_amc7823_spi_mosi_o,
amc7823_spi_miso_i => fmc250_2_amc7823_spi_miso_i,
amc7823_davn_i => fmc250_2_amc7823_davn_i,
-- FMC LEDs
fmc_led1_o => fmc2_led1_int,
fmc_led2_o => fmc2_led2_int,
fmc_led3_o => fmc2_led3_int,
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i => '0',
fmc_ext_ref_clk2x_i => '0',
fmc_ext_ref_mmcm_locked_i => '0',
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => fmc2_clk,
adc_clk2x_o => fmc2_clk2x,
adc_rst_n_o => fmc2_rst_n,
adc_rst2x_n_o => fmc2_rst2x_n,
adc_data_o => fmc2_data,
adc_data_valid_o => fmc2_data_valid,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => fmc2_trig_hw,
trig_hw_i => fmc2_trig_hw_in,
-- General board status
fmc_mmcm_lock_o => fmc2_mmcm_lock_int,
fmc_pll_status_o => fmc2_pll_status_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc2_in_array,
wbs_source_o => wbs_fmc2_out_array,
adc_dly_debug_o => fmc2_adc_dly_debug_int,
fifo_debug_valid_o => fmc2_debug_valid_int,
fifo_debug_full_o => fmc2_debug_full_int,
fifo_debug_empty_o => fmc2_debug_empty_int
);
gen_wbs2_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc2_in_array(i) <= cc_dummy_src_com_in;
end generate;
-- Only FMC 1 is connected for now
--fmc250_2_mmcm_lock_led_o <= fmc2_mmcm_lock_int;
--fmc250_2_pll_status_led_o <= fmc2_pll_status_int;
fmc250_2_led1_o <= fmc2_led1_int;
fmc250_2_led2_o <= fmc2_led2_int;
fmc250_2_led3_o <= fmc2_led3_int;
fmc2_adc_data_ch0 <= fmc2_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb);
fmc2_adc_data_ch1 <= fmc2_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb);
fmc2_adc_data_ch2 <= fmc2_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb);
fmc2_adc_data_ch3 <= fmc2_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb);
fmc2_adc_data_se_ch0 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb)),
fmc2_adc_data_se_ch0'length));
fmc2_adc_data_se_ch1 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb)),
fmc2_adc_data_se_ch1'length));
fmc2_adc_data_se_ch2 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb)),
fmc2_adc_data_se_ch2'length));
fmc2_adc_data_se_ch3 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb)),
fmc2_adc_data_se_ch3'length));
fmc2_adc_valid <= '1';
fs2_clk <= fmc2_clk(c_ADC_REF_CLK);
fs2_rstn <= fmc2_rst_n(c_ADC_REF_CLK);
fs2_clk2x <= fmc2_clk2x(c_ADC_REF_CLK);
fs2_rst2xn <= fmc2_rst2x_n(c_ADC_REF_CLK);
-- Use ADC trigger for testing
fmc2_trig_hw_in <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_TRIGGER_SW_CLK_ID).pulse;
end generate;
gen_fmcpico_1m : if (g_fmc_adc_type = "FMCPICO_1M") generate
----------------------------------------------------------------------
-- FMC PICO 1M_4CH 1 Core --
----------------------------------------------------------------------
cmp1_xwb_fmcpico1m_4ch : xwb_fmcpico1m_4ch
generic map
(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
-- g_num_adc_bits natural := 20;
-- g_num_adc_channels natural := 4;
-- g_clk_freq natural := 300000000; -- Hz
-- g_sclk_freq natural := 75000000 --Hz
)
port map
(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => user_wb_out(c_SLV_FMC_ADC_1_ID),
wb_slv_o => user_wb_in(c_SLV_FMC_ADC_1_ID),
-----------------------------
-- External ports
-----------------------------
adc_fast_spi_clk_i => clk_300mhz,
adc_fast_spi_rstn_i => clk_300mhz_rstn,
-- Control signals
adc_start_i => '1',
-- SPI bus
adc_sdo1_i => fmcpico_1_adc_sdo1_i,
adc_sdo2_i => fmcpico_1_adc_sdo2_i,
adc_sdo3_i => fmcpico_1_adc_sdo3_i,
adc_sdo4_i => fmcpico_1_adc_sdo4_i,
adc_sck_o => fmcpico_1_adc_sck_o,
adc_sck_rtrn_i => fmcpico_1_adc_sck_rtrn_i,
adc_busy_cmn_i => fmcpico_1_adc_busy_cmn_i,
adc_cnv_out_o => fmcpico_1_adc_cnv_o,
-- Range selection
adc_rng_r1_o => fmcpico_1_rng_r1_o,
adc_rng_r2_o => fmcpico_1_rng_r2_o,
adc_rng_r3_o => fmcpico_1_rng_r3_o,
adc_rng_r4_o => fmcpico_1_rng_r4_o,
-- Board LEDs
fmc_led1_o => fmcpico_1_led1_o,
fmc_led2_o => fmcpico_1_led2_o,
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
-- clock to CDC. This must be g_sclk_freq/g_num_adc_bits. A regular 100MHz should
-- suffice in all cases
adc_clk_i => fs1_clk,
adc_data_o => fmc1_data,
adc_data_valid_o => fmc1_data_valid,
adc_out_busy_o => fmc1_adc_busy
);
fmc1_adc_data_ch0 <= fmc1_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb);
fmc1_adc_data_ch1 <= fmc1_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb);
fmc1_adc_data_ch2 <= fmc1_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb);
fmc1_adc_data_ch3 <= fmc1_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb);
fmc1_adc_data_se_ch0 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb)),
fmc1_adc_data_se_ch0'length));
fmc1_adc_data_se_ch1 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb)),
fmc1_adc_data_se_ch1'length));
fmc1_adc_data_se_ch2 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb)),
fmc1_adc_data_se_ch2'length));
fmc1_adc_data_se_ch3 <= std_logic_vector(resize(signed(
fmc1_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb)),
fmc1_adc_data_se_ch3'length));
fmc1_adc_valid <= fmc1_data_valid(0);
fmc1_clk <= (others => clk_sys);
fmc1_clk2x <= (others => clk_sys);
fmc1_rst_n <= (others => clk_sys_rstn);
fmc1_rst2x_n <= (others => clk_sys_rstn);
fs1_clk <= fmc1_clk(c_ADC_REF_CLK);
fs1_clk2x <= fmc1_clk2x(c_ADC_REF_CLK);
fs1_rstn <= fmc1_rst_n(c_ADC_REF_CLK);
fs1_rst2xn <= fmc1_rst2x_n(c_ADC_REF_CLK);
-- Temporary assignemnts
fmcpico_1_sm_scl_o <= '0';
fmcpico_1_a_scl_o <= '0';
----------------------------------------------------------------------
-- FMC PICO 1M_4CH 2 Core --
----------------------------------------------------------------------
cmp2_xwb_fmcpico1m_4ch : xwb_fmcpico1m_4ch
generic map
(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
-- g_num_adc_bits natural := 20;
-- g_num_adc_channels natural := 4;
-- g_clk_freq natural := 300000000; -- Hz
-- g_sclk_freq natural := 75000000 --Hz
)
port map
(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => user_wb_out(c_SLV_FMC_ADC_2_ID),
wb_slv_o => user_wb_in(c_SLV_FMC_ADC_2_ID),
-----------------------------
-- External ports
-----------------------------
adc_fast_spi_clk_i => clk_300mhz,
adc_fast_spi_rstn_i => clk_300mhz_rstn,
-- Control signals
adc_start_i => '1',
-- SPI bus
adc_sdo1_i => fmcpico_2_adc_sdo1_i,
adc_sdo2_i => fmcpico_2_adc_sdo2_i,
adc_sdo3_i => fmcpico_2_adc_sdo3_i,
adc_sdo4_i => fmcpico_2_adc_sdo4_i,
adc_sck_o => fmcpico_2_adc_sck_o,
adc_sck_rtrn_i => fmcpico_2_adc_sck_rtrn_i,
adc_busy_cmn_i => fmcpico_2_adc_busy_cmn_i,
adc_cnv_out_o => fmcpico_2_adc_cnv_o,
-- Range selection
adc_rng_r1_o => fmcpico_2_rng_r1_o,
adc_rng_r2_o => fmcpico_2_rng_r2_o,
adc_rng_r3_o => fmcpico_2_rng_r3_o,
adc_rng_r4_o => fmcpico_2_rng_r4_o,
-- Board LEDs
fmc_led1_o => fmcpico_2_led1_o,
fmc_led2_o => fmcpico_2_led2_o,
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
-- clock to CDC. This must be g_sclk_freq/g_num_adc_bits. A regular 100MHz should
-- suffice in all cases
adc_clk_i => fs2_clk,
adc_data_o => fmc2_data,
adc_data_valid_o => fmc2_data_valid,
adc_out_busy_o => fmc2_adc_busy
);
fmc2_adc_data_ch0 <= fmc2_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb);
fmc2_adc_data_ch1 <= fmc2_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb);
fmc2_adc_data_ch2 <= fmc2_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb);
fmc2_adc_data_ch3 <= fmc2_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb);
fmc2_adc_data_se_ch0 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb)),
fmc2_adc_data_se_ch0'length));
fmc2_adc_data_se_ch1 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb)),
fmc2_adc_data_se_ch1'length));
fmc2_adc_data_se_ch2 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb)),
fmc2_adc_data_se_ch2'length));
fmc2_adc_data_se_ch3 <= std_logic_vector(resize(signed(
fmc2_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb)),
fmc2_adc_data_se_ch3'length));
fmc2_adc_valid <= fmc2_data_valid(0);
fmc2_clk <= (others => clk_sys);
fmc2_clk2x <= (others => clk_sys);
fmc2_rst_n <= (others => clk_sys_rstn);
fmc2_rst2x_n <= (others => clk_sys_rstn);
fs2_clk <= fmc2_clk(c_ADC_REF_CLK);
fs2_clk2x <= fmc2_clk2x(c_ADC_REF_CLK);
fs2_rstn <= fmc2_rst_n(c_ADC_REF_CLK);
fs2_rst2xn <= fmc2_rst2x_n(c_ADC_REF_CLK);
---- Connected through FPGA MUX
---- Temporary assignemnts
--fmcpico_2_sm_scl_o <= '0';
--fmcpico_2_a_scl_o <= '0';
end generate;
-- Reference FMC ADC clock
fs_ref_clk <= fs1_clk;
fs_ref_clk2x <= fs1_clk2x;
fs_ref_rstn <= fs1_rstn;
fs_ref_rst2xn <= fs1_rst2xn;
fs_ref_rst <= not fs_ref_rstn;
----------------------------------------------------------------------
-- DSP Chain 1 Core --
----------------------------------------------------------------------
cmp1_xwb_position_calc_core : xwb_position_calc_core
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_with_extra_wb_reg => true,
-- selection of position_calc stages
g_with_downconv => c_pos_calc_with_downconv,
-- input sizes
g_input_width => c_num_unprocessed_bits,
g_mixed_width => c_pos_calc_mixed_width,
g_adc_ratio => c_pos_calc_adc_ratio,
-- mixer
g_dds_width => c_pos_calc_dds_width,
g_dds_points => c_pos_calc_dds_points,
g_sin_file => c_pos_calc_sin_file,
g_cos_file => c_pos_calc_cos_file,
-- CIC setup
g_tbt_cic_delay => c_pos_calc_tbt_cic_delay,
g_tbt_cic_stages => c_pos_calc_tbt_cic_stages,
g_tbt_ratio => c_pos_calc_tbt_ratio,
g_tbt_decim_width => c_pos_calc_tbt_decim_width,
g_fofb_cic_delay => c_pos_calc_fofb_cic_delay,
g_fofb_cic_stages => c_pos_calc_fofb_cic_stages,
g_fofb_ratio => c_pos_calc_fofb_ratio,
g_fofb_decim_width => c_pos_calc_fofb_decim_width,
g_monit1_cic_delay => c_pos_calc_monit1_cic_delay,
g_monit1_cic_stages => c_pos_calc_monit1_cic_stages,
g_monit1_ratio => c_pos_calc_monit1_ratio,
g_monit1_cic_ratio => c_pos_calc_monit1_cic_ratio,
g_monit2_cic_delay => c_pos_calc_monit2_cic_delay,
g_monit2_cic_stages => c_pos_calc_monit2_cic_stages,
g_monit2_ratio => c_pos_calc_monit2_ratio,
g_monit2_cic_ratio => c_pos_calc_monit2_cic_ratio,
-- Cordic setup
g_tbt_cordic_stages => c_pos_calc_tbt_cordic_stages,
g_tbt_cordic_iter_per_clk => c_pos_calc_tbt_cordic_iter_per_clk,
g_tbt_cordic_ratio => c_pos_calc_tbt_cordic_ratio,
g_fofb_cordic_stages => c_pos_calc_fofb_cordic_stages,
g_fofb_cordic_iter_per_clk => c_pos_calc_fofb_cordic_iter_per_clk,
g_fofb_cordic_ratio => c_pos_calc_fofb_cordic_ratio,
g_monit_decim_width => c_pos_calc_monit_decim_width,
-- width of K constants
g_k_width => c_pos_calc_k_width,
-- width of offset constants
g_offset_width => c_pos_calc_offset_width,
--width for IQ output
g_IQ_width => c_pos_calc_IQ_width,
-- Swap/de-swap setup
g_delay_vec_width => c_POS_CALC_DELAY_VEC_WIDTH,
g_swap_div_freq_vec_width => c_POS_CALC_SWAP_DIV_FREQ_VEC_WIDTH
)
port map (
rst_n_i => clk_sys_rstn,
clk_i => clk_sys, -- Wishbone clock
fs_rst_n_i => fs1_rstn,
fs_rst2x_n_i => fs1_rst2xn,
fs_clk_i => fs1_clk,
fs_clk2x_i => fs1_clk2x,
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => user_wb_out(c_SLV_POS_CALC_1_ID),
wb_slv_o => user_wb_in(c_SLV_POS_CALC_1_ID),
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i => fmc1_adc_data_ch0,
adc_ch1_i => fmc1_adc_data_ch1,
adc_ch2_i => fmc1_adc_data_ch2,
adc_ch3_i => fmc1_adc_data_ch3,
adc_valid_i => fmc1_adc_valid,
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_swap_o => dsp1_adc_ch0_data,
adc_ch1_swap_o => dsp1_adc_ch1_data,
adc_ch2_swap_o => dsp1_adc_ch2_data,
adc_ch3_swap_o => dsp1_adc_ch3_data,
adc_tag_o => dsp1_adc_tag,
adc_swap_valid_o => dsp1_adc_valid,
mix_ch0_i_o => dsp1_mixi_ch0,
mix_ch0_q_o => dsp1_mixq_ch0,
mix_ch1_i_o => dsp1_mixi_ch1,
mix_ch1_q_o => dsp1_mixq_ch1,
mix_ch2_i_o => dsp1_mixi_ch2,
mix_ch2_q_o => dsp1_mixq_ch2,
mix_ch3_i_o => dsp1_mixi_ch3,
mix_ch3_q_o => dsp1_mixq_ch3,
mix_valid_o => dsp1_mix_valid,
tbt_decim_ch0_i_o => dsp1_tbtdecimi_ch0,
tbt_decim_ch0_q_o => dsp1_tbtdecimq_ch0,
tbt_decim_ch1_i_o => dsp1_tbtdecimi_ch1,
tbt_decim_ch1_q_o => dsp1_tbtdecimq_ch1,
tbt_decim_ch2_i_o => dsp1_tbtdecimi_ch2,
tbt_decim_ch2_q_o => dsp1_tbtdecimq_ch2,
tbt_decim_ch3_i_o => dsp1_tbtdecimi_ch3,
tbt_decim_ch3_q_o => dsp1_tbtdecimq_ch3,
tbt_decim_valid_o => dsp1_tbtdecim_valid,
tbt_amp_ch0_o => dsp1_tbt_amp_ch0,
tbt_amp_ch1_o => dsp1_tbt_amp_ch1,
tbt_amp_ch2_o => dsp1_tbt_amp_ch2,
tbt_amp_ch3_o => dsp1_tbt_amp_ch3,
tbt_amp_valid_o => dsp1_tbt_amp_valid,
tbt_pha_ch0_o => dsp1_tbt_pha_ch0,
tbt_pha_ch1_o => dsp1_tbt_pha_ch1,
tbt_pha_ch2_o => dsp1_tbt_pha_ch2,
tbt_pha_ch3_o => dsp1_tbt_pha_ch3,
tbt_pha_valid_o => dsp1_tbt_pha_valid,
fofb_decim_ch0_i_o => dsp1_fofbdecimi_ch0,
fofb_decim_ch0_q_o => dsp1_fofbdecimq_ch0,
fofb_decim_ch1_i_o => dsp1_fofbdecimi_ch1,
fofb_decim_ch1_q_o => dsp1_fofbdecimq_ch1,
fofb_decim_ch2_i_o => dsp1_fofbdecimi_ch2,
fofb_decim_ch2_q_o => dsp1_fofbdecimq_ch2,
fofb_decim_ch3_i_o => dsp1_fofbdecimi_ch3,
fofb_decim_ch3_q_o => dsp1_fofbdecimq_ch3,
fofb_decim_valid_o => dsp1_fofbdecim_valid,
fofb_amp_ch0_o => dsp1_fofb_amp_ch0,
fofb_amp_ch1_o => dsp1_fofb_amp_ch1,
fofb_amp_ch2_o => dsp1_fofb_amp_ch2,
fofb_amp_ch3_o => dsp1_fofb_amp_ch3,
fofb_amp_valid_o => dsp1_fofb_amp_valid,
fofb_pha_ch0_o => dsp1_fofb_pha_ch0,
fofb_pha_ch1_o => dsp1_fofb_pha_ch1,
fofb_pha_ch2_o => dsp1_fofb_pha_ch2,
fofb_pha_ch3_o => dsp1_fofb_pha_ch3,
fofb_pha_valid_o => dsp1_fofb_pha_valid,
monit1_amp_ch0_o => dsp1_monit1_amp_ch0,
monit1_amp_ch1_o => dsp1_monit1_amp_ch1,
monit1_amp_ch2_o => dsp1_monit1_amp_ch2,
monit1_amp_ch3_o => dsp1_monit1_amp_ch3,
monit1_amp_valid_o => dsp1_monit1_amp_valid,
monit_amp_ch0_o => dsp1_monit_amp_ch0,
monit_amp_ch1_o => dsp1_monit_amp_ch1,
monit_amp_ch2_o => dsp1_monit_amp_ch2,
monit_amp_ch3_o => dsp1_monit_amp_ch3,
monit_amp_valid_o => dsp1_monit_amp_valid,
tbt_pos_x_o => dsp1_tbt_pos_x,
tbt_pos_y_o => dsp1_tbt_pos_y,
tbt_pos_q_o => dsp1_tbt_pos_q,
tbt_pos_sum_o => dsp1_tbt_pos_sum,
tbt_pos_valid_o => dsp1_tbt_pos_valid,
fofb_pos_x_o => dsp1_fofb_pos_x,
fofb_pos_y_o => dsp1_fofb_pos_y,
fofb_pos_q_o => dsp1_fofb_pos_q,
fofb_pos_sum_o => dsp1_fofb_pos_sum,
fofb_pos_valid_o => dsp1_fofb_pos_valid,
monit1_pos_x_o => dsp1_monit1_pos_x,
monit1_pos_y_o => dsp1_monit1_pos_y,
monit1_pos_q_o => dsp1_monit1_pos_q,
monit1_pos_sum_o => dsp1_monit1_pos_sum,
monit1_pos_valid_o => dsp1_monit1_pos_valid,
monit_pos_x_o => dsp1_monit_pos_x,
monit_pos_y_o => dsp1_monit_pos_y,
monit_pos_q_o => dsp1_monit_pos_q,
monit_pos_sum_o => dsp1_monit_pos_sum,
monit_pos_valid_o => dsp1_monit_pos_valid,
-----------------------------
-- Output to RFFE board
-----------------------------
rffe_swclk_o => dsp1_clk_rffe_swap,
-----------------------------
-- Synchronization trigger for all rates. Slow clock
-----------------------------
sync_trig_slow_i => trig_pulse_rcv(c_TRIG_MUX_0_ID, c_PHASE_SYNC_TRIGGER_SLOW_ID).pulse,
-----------------------------
-- Debug signals
-----------------------------
dbg_cur_address_o => dsp1_dbg_cur_address,
dbg_adc_ch0_cond_o => dsp1_dbg_adc_ch0_cond,
dbg_adc_ch1_cond_o => dsp1_dbg_adc_ch1_cond,
dbg_adc_ch2_cond_o => dsp1_dbg_adc_ch2_cond,
dbg_adc_ch3_cond_o => dsp1_dbg_adc_ch3_cond
);
-- Sign-extension to acquisition core
dsp1_adc_se_ch0_data <= std_logic_vector(resize(signed(
dsp1_adc_ch0_data),
dsp1_adc_se_ch0_data'length));
dsp1_adc_se_ch1_data <= std_logic_vector(resize(signed(
dsp1_adc_ch1_data),
dsp1_adc_se_ch1_data'length));
dsp1_adc_se_ch2_data <= std_logic_vector(resize(signed(
dsp1_adc_ch2_data),
dsp1_adc_se_ch2_data'length));
dsp1_adc_se_ch3_data <= std_logic_vector(resize(signed(
dsp1_adc_ch3_data),
dsp1_adc_se_ch3_data'length));
----------------------------------------------------------------------
-- DSP Chain 2 Core --
----------------------------------------------------------------------
cmp2_xwb_position_calc_core : xwb_position_calc_core
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_with_extra_wb_reg => true,
-- selection of position_calc stages
g_with_downconv => c_pos_calc_with_downconv,
-- input sizes
g_input_width => c_num_unprocessed_bits,
g_mixed_width => c_pos_calc_mixed_width,
g_adc_ratio => c_pos_calc_adc_ratio,
-- mixer
g_dds_width => c_pos_calc_dds_width,
g_dds_points => c_pos_calc_dds_points,
g_sin_file => c_pos_calc_sin_file,
g_cos_file => c_pos_calc_cos_file,
-- CIC setup
g_tbt_cic_delay => c_pos_calc_tbt_cic_delay,
g_tbt_cic_stages => c_pos_calc_tbt_cic_stages,
g_tbt_ratio => c_pos_calc_tbt_ratio,
g_tbt_decim_width => c_pos_calc_tbt_decim_width,
g_fofb_cic_delay => c_pos_calc_fofb_cic_delay,
g_fofb_cic_stages => c_pos_calc_fofb_cic_stages,
g_fofb_ratio => c_pos_calc_fofb_ratio,
g_fofb_decim_width => c_pos_calc_fofb_decim_width,
g_monit1_cic_delay => c_pos_calc_monit1_cic_delay,
g_monit1_cic_stages => c_pos_calc_monit1_cic_stages,
g_monit1_ratio => c_pos_calc_monit1_ratio,
g_monit1_cic_ratio => c_pos_calc_monit1_cic_ratio,
g_monit2_cic_delay => c_pos_calc_monit2_cic_delay,
g_monit2_cic_stages => c_pos_calc_monit2_cic_stages,
g_monit2_ratio => c_pos_calc_monit2_ratio,
g_monit2_cic_ratio => c_pos_calc_monit2_cic_ratio,
g_monit_decim_width => c_pos_calc_monit_decim_width,
-- Cordic setup
g_tbt_cordic_stages => c_pos_calc_tbt_cordic_stages,
g_tbt_cordic_iter_per_clk => c_pos_calc_tbt_cordic_iter_per_clk,
g_tbt_cordic_ratio => c_pos_calc_tbt_cordic_ratio,
g_fofb_cordic_stages => c_pos_calc_fofb_cordic_stages,
g_fofb_cordic_iter_per_clk => c_pos_calc_fofb_cordic_iter_per_clk,
g_fofb_cordic_ratio => c_pos_calc_fofb_cordic_ratio,
-- width of K constants
g_k_width => c_pos_calc_k_width,
-- width of offset constants
g_offset_width => c_pos_calc_offset_width,
--width for IQ output
g_IQ_width => c_pos_calc_IQ_width,
-- Swap/de-swap setup
g_delay_vec_width => c_POS_CALC_DELAY_VEC_WIDTH,
g_swap_div_freq_vec_width => c_POS_CALC_SWAP_DIV_FREQ_VEC_WIDTH
)
port map (
rst_n_i => clk_sys_rstn,
clk_i => clk_sys, -- Wishbone clock
fs_rst_n_i => fs2_rstn,
fs_rst2x_n_i => fs2_rst2xn,
fs_clk_i => fs2_clk,
fs_clk2x_i => fs2_clk2x,
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => user_wb_out(c_SLV_POS_CALC_2_ID),
wb_slv_o => user_wb_in(c_SLV_POS_CALC_2_ID),
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i => fmc2_adc_data_ch0,
adc_ch1_i => fmc2_adc_data_ch1,
adc_ch2_i => fmc2_adc_data_ch2,
adc_ch3_i => fmc2_adc_data_ch3,
adc_valid_i => fmc2_adc_valid,
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_swap_o => dsp2_adc_ch0_data,
adc_ch1_swap_o => dsp2_adc_ch1_data,
adc_ch2_swap_o => dsp2_adc_ch2_data,
adc_ch3_swap_o => dsp2_adc_ch3_data,
adc_tag_o => dsp2_adc_tag,
adc_swap_valid_o => dsp2_adc_valid,
mix_ch0_i_o => dsp2_mixi_ch0,
mix_ch0_q_o => dsp2_mixq_ch0,
mix_ch1_i_o => dsp2_mixi_ch1,
mix_ch1_q_o => dsp2_mixq_ch1,
mix_ch2_i_o => dsp2_mixi_ch2,
mix_ch2_q_o => dsp2_mixq_ch2,
mix_ch3_i_o => dsp2_mixi_ch3,
mix_ch3_q_o => dsp2_mixq_ch3,
mix_valid_o => dsp2_mix_valid,
tbt_decim_ch0_i_o => dsp2_tbtdecimi_ch0,
tbt_decim_ch0_q_o => dsp2_tbtdecimq_ch0,
tbt_decim_ch1_i_o => dsp2_tbtdecimi_ch1,
tbt_decim_ch1_q_o => dsp2_tbtdecimq_ch1,
tbt_decim_ch2_i_o => dsp2_tbtdecimi_ch2,
tbt_decim_ch2_q_o => dsp2_tbtdecimq_ch2,
tbt_decim_ch3_i_o => dsp2_tbtdecimi_ch3,
tbt_decim_ch3_q_o => dsp2_tbtdecimq_ch3,
tbt_decim_valid_o => dsp2_tbtdecim_valid,
tbt_amp_ch0_o => dsp2_tbt_amp_ch0,
tbt_amp_ch1_o => dsp2_tbt_amp_ch1,
tbt_amp_ch2_o => dsp2_tbt_amp_ch2,
tbt_amp_ch3_o => dsp2_tbt_amp_ch3,
tbt_amp_valid_o => dsp2_tbt_amp_valid,
tbt_pha_ch0_o => dsp2_tbt_pha_ch0,
tbt_pha_ch1_o => dsp2_tbt_pha_ch1,
tbt_pha_ch2_o => dsp2_tbt_pha_ch2,
tbt_pha_ch3_o => dsp2_tbt_pha_ch3,
tbt_pha_valid_o => dsp2_tbt_pha_valid,
fofb_decim_ch0_i_o => dsp2_fofbdecimi_ch0,
fofb_decim_ch0_q_o => dsp2_fofbdecimq_ch0,
fofb_decim_ch1_i_o => dsp2_fofbdecimi_ch1,
fofb_decim_ch1_q_o => dsp2_fofbdecimq_ch1,
fofb_decim_ch2_i_o => dsp2_fofbdecimi_ch2,
fofb_decim_ch2_q_o => dsp2_fofbdecimq_ch2,
fofb_decim_ch3_i_o => dsp2_fofbdecimi_ch3,
fofb_decim_ch3_q_o => dsp2_fofbdecimq_ch3,
fofb_decim_valid_o => dsp2_fofbdecim_valid,
fofb_amp_ch0_o => dsp2_fofb_amp_ch0,
fofb_amp_ch1_o => dsp2_fofb_amp_ch1,
fofb_amp_ch2_o => dsp2_fofb_amp_ch2,
fofb_amp_ch3_o => dsp2_fofb_amp_ch3,
fofb_amp_valid_o => dsp2_fofb_amp_valid,
fofb_pha_ch0_o => dsp2_fofb_pha_ch0,
fofb_pha_ch1_o => dsp2_fofb_pha_ch1,
fofb_pha_ch2_o => dsp2_fofb_pha_ch2,
fofb_pha_ch3_o => dsp2_fofb_pha_ch3,
fofb_pha_valid_o => dsp2_fofb_pha_valid,
monit1_amp_ch0_o => dsp2_monit1_amp_ch0,
monit1_amp_ch1_o => dsp2_monit1_amp_ch1,
monit1_amp_ch2_o => dsp2_monit1_amp_ch2,
monit1_amp_ch3_o => dsp2_monit1_amp_ch3,
monit1_amp_valid_o => dsp2_monit1_amp_valid,
monit_amp_ch0_o => dsp2_monit_amp_ch0,
monit_amp_ch1_o => dsp2_monit_amp_ch1,
monit_amp_ch2_o => dsp2_monit_amp_ch2,
monit_amp_ch3_o => dsp2_monit_amp_ch3,
monit_amp_valid_o => dsp2_monit_amp_valid,
tbt_pos_x_o => dsp2_tbt_pos_x,
tbt_pos_y_o => dsp2_tbt_pos_y,
tbt_pos_q_o => dsp2_tbt_pos_q,
tbt_pos_sum_o => dsp2_tbt_pos_sum,
tbt_pos_valid_o => dsp2_tbt_pos_valid,
fofb_pos_x_o => dsp2_fofb_pos_x,
fofb_pos_y_o => dsp2_fofb_pos_y,
fofb_pos_q_o => dsp2_fofb_pos_q,
fofb_pos_sum_o => dsp2_fofb_pos_sum,
fofb_pos_valid_o => dsp2_fofb_pos_valid,
monit1_pos_x_o => dsp2_monit1_pos_x,
monit1_pos_y_o => dsp2_monit1_pos_y,
monit1_pos_q_o => dsp2_monit1_pos_q,
monit1_pos_sum_o => dsp2_monit1_pos_sum,
monit1_pos_valid_o => dsp2_monit1_pos_valid,
monit_pos_x_o => dsp2_monit_pos_x,
monit_pos_y_o => dsp2_monit_pos_y,
monit_pos_q_o => dsp2_monit_pos_q,
monit_pos_sum_o => dsp2_monit_pos_sum,
monit_pos_valid_o => dsp2_monit_pos_valid,
-----------------------------
-- Output to RFFE board
-----------------------------
rffe_swclk_o => dsp2_clk_rffe_swap,
-----------------------------
-- Synchronization trigger for all rates. Slow clock
-----------------------------
sync_trig_slow_i => trig_pulse_rcv(c_TRIG_MUX_1_ID, c_PHASE_SYNC_TRIGGER_SLOW_ID).pulse,
-----------------------------
-- Debug signals
-----------------------------
dbg_cur_address_o => dsp2_dbg_cur_address,
dbg_adc_ch0_cond_o => dsp2_dbg_adc_ch0_cond,
dbg_adc_ch1_cond_o => dsp2_dbg_adc_ch1_cond,
dbg_adc_ch2_cond_o => dsp2_dbg_adc_ch2_cond,
dbg_adc_ch3_cond_o => dsp2_dbg_adc_ch3_cond
);
-- Sign-extension to acquisition core
dsp2_adc_se_ch0_data <= std_logic_vector(resize(signed(
dsp2_adc_ch0_data),
dsp2_adc_se_ch0_data'length));
dsp2_adc_se_ch1_data <= std_logic_vector(resize(signed(
dsp2_adc_ch1_data),
dsp2_adc_se_ch1_data'length));
dsp2_adc_se_ch2_data <= std_logic_vector(resize(signed(
dsp2_adc_ch2_data),
dsp2_adc_se_ch2_data'length));
dsp2_adc_se_ch3_data <= std_logic_vector(resize(signed(
dsp2_adc_ch3_data),
dsp2_adc_se_ch3_data'length));
----------------------------------------------------------------------
-- RTM 8SFP OHWR --
----------------------------------------------------------------------
gen_fix_inv_sfps: for i in 0 to c_NUM_SFPS_FOFB-1 generate
rtm_sfp_fix_rx_p(c_NUM_SFPS_FOFB-1-i) <= rtm_sfp_rx_p_i(g_SFP_START_ID+i);
rtm_sfp_fix_rx_n(c_NUM_SFPS_FOFB-1-i) <= rtm_sfp_rx_n_i(g_SFP_START_ID+i);
rtm_sfp_tx_p_o(g_SFP_START_ID+i) <= rtm_sfp_fix_tx_p(c_NUM_SFPS_FOFB-1-i);
rtm_sfp_tx_n_o(g_SFP_START_ID+i) <= rtm_sfp_fix_tx_n(c_NUM_SFPS_FOFB-1-i);
end generate;
gen_with_rtm_8sfp : if g_WITH_RTM_SFP generate
cmp_rtm8sfp_ohwr : rtm8sfp_ohwr
generic map (
g_NUM_SFPS => c_NUM_SFPS_FOFB,
g_SYS_CLOCK_FREQ => c_SYS_CLOCK_FREQ,
g_SI57x_I2C_FREQ => c_RTM_SI57x_I2C_FREQ,
-- Whether or not to initialize oscilator with the specified values
g_SI57x_INIT_OSC => c_RTM_SI57x_INIT_OSC,
-- Init Oscillator values
g_SI57x_INIT_RFREQ_VALUE => c_RTM_SI57x_INIT_RFREQ_VALUE,
g_SI57x_INIT_N1_VALUE => c_RTM_SI57x_INIT_N1_VALUE,
g_SI57x_INIT_HS_VALUE => c_RTM_SI57x_INIT_HS_VALUE
)
port map (
---------------------------------------------------------------------------
-- clock and reset interface
---------------------------------------------------------------------------
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
---------------------------------------------------------------------------
-- RTM board pins
---------------------------------------------------------------------------
-- SFP
sfp_rx_p_i => rtm_sfp_fix_rx_p,
sfp_rx_n_i => rtm_sfp_fix_rx_n,
sfp_tx_p_o => rtm_sfp_fix_tx_p,
sfp_tx_n_o => rtm_sfp_fix_tx_n,
-- RTM I2C.
-- SFP configuration pins, behind a I2C MAX7356. I2C addr = 1110_100 & '0' = 0xE8
-- Si570 oscillator. Input 0 of CDCLVD1212. I2C addr = 1010101 & '0' = 0x55
rtm_scl_b => rtm_scl_b,
rtm_sda_b => rtm_sda_b,
-- Si570 oscillator output enable
si570_oe_o => rtm_si570_oe_o,
---- Clock to RTM connector. Input 1 of CDCLVD1212. Not connected to FPGA
-- rtm_sync_clk_p_o => rtm_sync_clk_p_o,
-- rtm_sync_clk_n_o => rtm_sync_clk_n_o,
-- Select between input 0 or 1 or CDCLVD1212. 0 is Si570, 1 is RTM sync clock
clk_in_sel_o => rtm_clk_in_sel_o,
-- FPGA clocks from CDCLVD1212
fpga_clk1_p_i => rtm_fpga_clk1_p_i,
fpga_clk1_n_i => rtm_fpga_clk1_n_i,
fpga_clk2_p_i => rtm_fpga_clk2_p_i,
fpga_clk2_n_i => rtm_fpga_clk2_n_i,
-- SFP status bits. Behind 4 74HC165, 8-parallel-in/serial-out. 4 x 8 bits.
--
-- Parallel load
sfp_status_reg_pl_o => rtm_sfp_status_reg_pl_o,
-- Clock N
sfp_status_reg_clk_n_o => rtm_sfp_status_reg_clk_n_o,
-- Serial output
sfp_status_reg_out_i => rtm_sfp_status_reg_out_i,
-- SFP control bits. Behind 4 74HC4094D, serial-in/8-parallel-out. 5 x 8 bits.
--
-- Strobe
sfp_ctl_reg_str_n_o => rtm_sfp_ctl_str_n_o,
-- Data input
sfp_ctl_reg_din_n_o => rtm_sfp_ctl_din_n_o,
-- Parallel output enable
sfp_ctl_reg_oe_n_o => rtm_sfp_ctl_oe_n_o,
-- External clock from RTM to FPGA
ext_clk_p_i => rtm_ext_clk_p_i,
ext_clk_n_i => rtm_ext_clk_n_i,
---------------------------------------------------------------------------
-- Optional external RFFREQ interface
---------------------------------------------------------------------------
ext_wr_i => rtm_ext_wr,
ext_rfreq_value_i => rtm_ext_rfreq_value,
ext_n1_value_i => rtm_ext_n1_value,
ext_hs_value_i => rtm_ext_hs_value,
---------------------------------------------------------------------------
-- Status pins
---------------------------------------------------------------------------
sta_reconfig_done_o => rtm_sta_reconfig_done,
---------------------------------------------------------------------------
-- FPGA side
---------------------------------------------------------------------------
sfp_txdisable_i => sfp_txdisable,
sfp_rs0_i => sfp_rs0,
sfp_rs1_i => sfp_rs1,
sfp_led1_o => sfp_led1,
sfp_los_o => sfp_los,
sfp_txfault_o => sfp_txfault,
sfp_detect_n_o => sfp_detect_n,
fpga_sfp_rx_p_o => rtm_sfp_rx_p,
fpga_sfp_rx_n_o => rtm_sfp_rx_n,
fpga_sfp_tx_p_i => rtm_sfp_tx_p,
fpga_sfp_tx_n_i => rtm_sfp_tx_n,
fpga_si570_oe_i => '1',
fpga_si57x_addr_i => "10101010",
fpga_clk_in_sel_i => '0',
fpga_clk1_p_o => rtm_clk1_p,
fpga_clk1_n_o => rtm_clk1_n,
fpga_clk2_p_o => rtm_clk2_p,
fpga_clk2_n_o => rtm_clk2_n,
fpga_ext_clk_p_o => rtm_ext_clk_p,
fpga_ext_clk_n_o => rtm_ext_clk_n
);
end generate;
gen_without_rtm_8sfp : if (not g_WITH_RTM_SFP) generate
-- default assignmentes for unused pins
rtm_si570_oe_o <= '0';
rtm_clk_in_sel_o <= '0';
rtm_sfp_status_reg_pl_o <= '0';
rtm_sfp_status_reg_clk_n_o <= '1';
rtm_sfp_ctl_str_n_o <= '1';
rtm_sfp_ctl_din_n_o <= '1';
rtm_sfp_ctl_oe_n_o <= '1';
end generate;
gen_fix_sfp_ctl_status: for i in 0 to 7 generate
sfp_txdisable(i) <= sfp_fix_txdisable(7-i);
sfp_rs0(i) <= sfp_fix_rs0(7-i);
sfp_rs1(i) <= sfp_fix_rs1(7-i);
sfp_fix_led1(7-i) <= sfp_led1(i);
sfp_fix_los(7-i) <= sfp_los(i);
sfp_fix_txfault(7-i) <= sfp_txfault(i);
sfp_fix_detect_n(7-i) <= sfp_detect_n(i);
end generate;
-- Generate large pulse for reset
cmp_gc_posedge : gc_posedge
port map (
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
data_i => rtm_sta_reconfig_done,
pulse_o => rtm_sta_reconfig_done_pp
);
cmp_gc_extend_pulse : gc_extend_pulse
generic map (
g_width => 50000
)
port map (
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
pulse_i => rtm_sta_reconfig_done_pp,
extended_o => rtm_reconfig_rst
);
rtm_reconfig_rst_n <= not rtm_reconfig_rst;
----------------------------------------------------------------------
-- FOFB DCC RTM --
----------------------------------------------------------------------
gen_fofb_sfps: for i in 0 to c_NUM_SFPS_FOFB-1 generate
-- assign SFPs if WITH_RTM_SFP is false will likely generate
-- placer errors
assert (g_WITH_RTM_SFP)
report "[dbe_bpm_gen] g_WITH_RTM_SFP must be true to use rtm_sfp_rx/tx ports."
severity Failure;
-- RX lines
fofb_rio_rx_p(c_FOFB_CC_RTM_ID)(i) <= rtm_sfp_rx_p(i);
fofb_rio_rx_n(c_FOFB_CC_RTM_ID)(i) <= rtm_sfp_rx_n(i);
-- TX lines
rtm_sfp_tx_p(i) <= fofb_rio_tx_p(c_FOFB_CC_RTM_ID)(i);
rtm_sfp_tx_n(i) <= fofb_rio_tx_n(c_FOFB_CC_RTM_ID)(i);
end generate;
-- Clocks. Use rtm_clk1_p as this goes to the same bank as SFP 0, 1, 2, 3
-- transceivers
fofb_ref_clk_p(c_FOFB_CC_RTM_ID) <= rtm_clk1_p;
fofb_ref_clk_n(c_FOFB_CC_RTM_ID) <= rtm_clk1_n;
-- if RTM_SFP_FOFB_DCC is selected, then WITH_RTM_SFP also needs to be selected
assert ((c_WITH_RTM_SFP_FOFB_DCC and g_WITH_RTM_SFP) or
(not c_WITH_RTM_SFP_FOFB_DCC and not g_WITH_RTM_SFP))
report "[dbe_bpm_gen] if g_WITH_RTM_SFP_FOFB_DCC is selected then g_WITH_RTM_SFP must also be seletected"
severity Failure;
gen_with_rtm_sfp_fofb_dcc : if c_WITH_RTM_SFP_FOFB_DCC generate
cmp_fofb_ctrl_wrapper_0 : xwb_fofb_ctrl_wrapper
generic map
(
g_INTERFACE_MODE => PIPELINED,
g_ADDRESS_GRANULARITY => BYTE,
g_ID => 0,
g_DEVICE => DISTRIBUTOR,
g_PHYSICAL_INTERFACE => "SFP",
g_REFCLK_INPUT => "REFCLK0",
g_LANE_COUNT => c_NUM_SFPS_FOFB,
g_USE_CHIPSCOPE => c_USE_CHIPSCOPE,
-- Data from another DCC
g_USE_EXT_CC_IF => true,
-- BPM synthetic data
g_SIM_BPM_DATA => false
)
port map
(
---------------------------------------------------------------------------
-- differential MGT/GTP clock inputs
---------------------------------------------------------------------------
refclk_p_i => fofb_ref_clk_p(c_FOFB_CC_RTM_ID),
refclk_n_i => fofb_ref_clk_n(c_FOFB_CC_RTM_ID),
---------------------------------------------------------------------------
-- clock and reset interface
---------------------------------------------------------------------------
adcclk_i => fs_clk_array(c_FOFB_CC_RTM_ID),
adcreset_i => fs_rst_array(c_FOFB_CC_RTM_ID),
sysclk_i => clk_sys,
sysreset_n_i => fofb_sysreset_n(c_FOFB_CC_RTM_ID),
---------------------------------------------------------------------------
-- Wishbone Control Interface signals
---------------------------------------------------------------------------
wb_slv_i => user_wb_out(c_SLV_FOFB_CC_RTM_ID),
wb_slv_o => user_wb_in(c_SLV_FOFB_CC_RTM_ID),
---------------------------------------------------------------------------
-- external CC interface for data from another DCC. Used
-- when the other DCC is typically in a DISTRIBUTOR mode and
-- the other one (using this inteface) is part of another DCC
-- network that receives data from both externl GT links and
-- DCC. Used when USE_EXT_CC_IF = true. Overrides USE_PARALLEL_FA_IF
---------------------------------------------------------------------------
ext_cc_clk_i => fofb_userclk(c_FOFB_CC_P2P_ID),
ext_cc_rst_n_i => fofb_userrst_n(c_FOFB_CC_P2P_ID),
ext_cc_dat_i => fofb_fod_dat(c_FOFB_CC_P2P_ID),
ext_cc_dat_val_i => fofb_fod_dat_val(c_FOFB_CC_P2P_ID)(0),
---------------------------------------------------------------------------
-- serial I/Os for eight RocketIOs on the Libera
---------------------------------------------------------------------------
fai_rio_rdp_i => fofb_rio_rx_p(c_FOFB_CC_RTM_ID)(c_NUM_SFPS_FOFB-1 downto 0),
fai_rio_rdn_i => fofb_rio_rx_n(c_FOFB_CC_RTM_ID)(c_NUM_SFPS_FOFB-1 downto 0),
fai_rio_tdp_o => fofb_rio_tx_p(c_FOFB_CC_RTM_ID)(c_NUM_SFPS_FOFB-1 downto 0),
fai_rio_tdn_o => fofb_rio_tx_n(c_FOFB_CC_RTM_ID)(c_NUM_SFPS_FOFB-1 downto 0),
fai_rio_tdis_o => fofb_rio_tx_disable(c_FOFB_CC_RTM_ID)(c_NUM_SFPS_FOFB-1 downto 0),
---------------------------------------------------------------------------
-- Higher-level integration interface (PMC, SNIFFER_V5)
---------------------------------------------------------------------------
fofb_userclk_o => fofb_userclk(c_FOFB_CC_RTM_ID),
fofb_userrst_o => fofb_userrst(c_FOFB_CC_RTM_ID),
timeframe_start_o => timeframe_start(c_FOFB_CC_RTM_ID),
timeframe_end_o => timeframe_end(c_FOFB_CC_RTM_ID),
fofb_dma_ok_i => fofb_dma_ok(c_FOFB_CC_RTM_ID),
fofb_node_mask_o => fofb_node_mask(c_FOFB_CC_RTM_ID),
fofb_timestamp_val_o => fofb_timestamp_val(c_FOFB_CC_RTM_ID),
fofb_link_status_o => fofb_link_status(c_FOFB_CC_RTM_ID),
fofb_cc_enable_o => fofb_cc_enable(c_FOFB_CC_RTM_ID),
fofb_fod_dat_o => fofb_fod_dat(c_FOFB_CC_RTM_ID),
fofb_fod_dat_val_o => fofb_fod_dat_val(c_FOFB_CC_RTM_ID)(c_NUM_SFPS_FOFB-1 downto 0)
);
fofb_sysreset_n(c_FOFB_CC_RTM_ID) <= clk_sys_rstn and rtm_reconfig_rst_n;
fofb_userrst_n(c_FOFB_CC_RTM_ID) <= not fofb_userrst(c_FOFB_CC_RTM_ID);
-- CDC between FOFB clock and ACQ clock
cmp_inferred_async_fwft_fifo : inferred_async_fwft_fifo
generic map
(
g_data_width => c_FOFB_DCC_DATA_WIDTH,
g_size => 8,
g_almost_empty_threshold => 1,
g_almost_full_threshold => 7,
g_async => true
)
port map
(
-- Write clock
wr_clk_i => fofb_userclk(c_FOFB_CC_RTM_ID),
wr_rst_n_i => fofb_userrst_n(c_FOFB_CC_RTM_ID),
wr_data_i => fofb_fod_dat(c_FOFB_CC_RTM_ID),
wr_en_i => fofb_fod_dat_val(c_FOFB_CC_RTM_ID)(0),
-- Read clock
rd_clk_i => fs1_clk,
rd_rst_n_i => fs1_rstn,
rd_data_o => fofb_fod_dat_fs_sync(c_FOFB_CC_RTM_ID),
rd_valid_o => fofb_fod_dat_val_fs_sync(c_FOFB_CC_RTM_ID)(0),
rd_en_i => '1'
);
end generate;
----------------------------------------------------------------------
-- FOFB DCC P2P --
----------------------------------------------------------------------
gen_fofb_p2p_gts: for i in 0 to c_GT_CFG.num_p2p_gts-1 generate
-- RX lines
fofb_rio_rx_p(c_FOFB_CC_P2P_ID)(i) <= p2p_gt_rx_p_i(g_P2P_GT_START_ID+i);
fofb_rio_rx_n(c_FOFB_CC_P2P_ID)(i) <= p2p_gt_rx_n_i(g_P2P_GT_START_ID+i);
-- TX lines
p2p_gt_tx_p_o(g_P2P_GT_START_ID+i) <= fofb_rio_tx_p(c_FOFB_CC_P2P_ID)(i);
p2p_gt_tx_n_o(g_P2P_GT_START_ID+i) <= fofb_rio_tx_n(c_FOFB_CC_P2P_ID)(i);
end generate;
gen_unused_fofb_p2p_gts: for i in c_GT_CFG.num_p2p_gts to c_GT_CFG.max_p2p_gts-1 generate
-- TX lines
p2p_gt_tx_p_o(g_P2P_GT_START_ID+i) <= '0';
p2p_gt_tx_n_o(g_P2P_GT_START_ID+i) <= '1';
end generate;
gen_with_fofb_fp : if c_GT_CFG.with_fp_p2p generate
gen_fofb_fp_p2p_gts: for i in 0 to c_GT_CFG.num_fp_p2p_gts-1 generate
-- RX lines. Starts after all possible P2P GTs
fofb_rio_rx_p(c_FOFB_CC_P2P_ID)(g_P2P_GT_START_ID+c_GT_CFG.max_p2p_gts+i) <=
p2p_gt_rx_p_i(g_P2P_GT_START_ID+c_GT_CFG.max_p2p_gts+i);
fofb_rio_rx_n(c_FOFB_CC_P2P_ID)(g_P2P_GT_START_ID+c_GT_CFG.max_p2p_gts+i) <=
p2p_gt_rx_n_i(g_P2P_GT_START_ID+c_GT_CFG.max_p2p_gts+i);
-- TX lines. Starts after all possible P2P GTs
p2p_gt_tx_p_o(g_P2P_GT_START_ID+c_GT_CFG.max_p2p_gts+i) <=
fofb_rio_tx_p(c_FOFB_CC_P2P_ID)(g_P2P_GT_START_ID+c_GT_CFG.max_p2p_gts+i);
p2p_gt_tx_n_o(g_P2P_GT_START_ID+c_GT_CFG.max_p2p_gts+i) <=
fofb_rio_tx_n(c_FOFB_CC_P2P_ID)(g_P2P_GT_START_ID+c_GT_CFG.max_p2p_gts+i);
end generate;
gen_unused_fofb_fp_p2p_gts: for i in c_GT_CFG.num_fp_p2p_gts to c_GT_CFG.max_fp_p2p_gts-1 generate
-- TX lines
p2p_gt_tx_p_o(g_P2P_GT_START_ID+c_GT_CFG.max_p2p_gts+i) <= '0';
p2p_gt_tx_n_o(g_P2P_GT_START_ID+c_GT_CFG.max_p2p_gts+i) <= '1';
end generate;
end generate;
-- Only used if FP P2P is not used.
fofb_ref_clk_p(c_FOFB_CC_P2P_ID) <= clk_fp2_clk1_p;
fofb_ref_clk_n(c_FOFB_CC_P2P_ID) <= clk_fp2_clk1_n;
gen_with_p2p_fofb_dcc : if c_WITH_P2P_FOFB_DCC generate
-----------------------------------------
-- CDC DSP 1 between ACQ clock and FOFB clock
-----------------------------------------
dsp1_fofb_pos_xy_in_fifo <= (dsp1_fofb_pos_x, dsp1_fofb_pos_y);
dsp1_fofb_pos_valid_in_fifo <= dsp1_fofb_pos_valid;
cmp_dsp_1_fofb_fifo : inferred_async_fwft_fifo
generic map
(
g_data_width => dsp1_fofb_pos_xy_out_fifo_slv'length,
g_size => 8,
g_almost_empty_threshold => 1,
g_almost_full_threshold => 7,
g_async => true
)
port map
(
-- Write clock
wr_clk_i => fs1_clk,
wr_rst_n_i => dsp_fofb_pos_rstn,
wr_data_i => f_to_slv(dsp1_fofb_pos_xy_in_fifo),
wr_en_i => dsp1_fofb_pos_valid_in_fifo,
-- Read clock
rd_clk_i => fs_ref_clk,
rd_rst_n_i => fs_ref_rstn,
rd_data_o => dsp1_fofb_pos_xy_out_fifo_slv,
rd_valid_o => dsp1_fofb_pos_valid_out_fifo,
rd_en_i => dsp_fofb_pos_fifo_rden
);
dsp1_fofb_pos_xy_out_fifo <= f_to_fofb_array(dsp1_fofb_pos_xy_out_fifo_slv);
(dsp1_fofb_pos_x_out_fifo, dsp1_fofb_pos_y_out_fifo) <= dsp1_fofb_pos_xy_out_fifo;
-----------------------------------------
-- CDC DSP 1 between ACQ clock and FOFB clock
-----------------------------------------
dsp2_fofb_pos_xy_in_fifo <= (dsp2_fofb_pos_x, dsp2_fofb_pos_y);
dsp2_fofb_pos_valid_in_fifo <= dsp2_fofb_pos_valid;
cmp_dsp_2_fofb_fifo : inferred_async_fwft_fifo
generic map
(
g_data_width => dsp2_fofb_pos_xy_out_fifo_slv'length,
g_size => 8,
g_almost_empty_threshold => 1,
g_almost_full_threshold => 7,
g_async => true
)
port map
(
-- Write clock
wr_clk_i => fs2_clk,
wr_rst_n_i => dsp_fofb_pos_rstn,
wr_data_i => f_to_slv(dsp2_fofb_pos_xy_in_fifo),
wr_en_i => dsp2_fofb_pos_valid_in_fifo,
-- Read clock
rd_clk_i => fs_ref_clk,
rd_rst_n_i => fs_ref_rstn,
rd_data_o => dsp2_fofb_pos_xy_out_fifo_slv,
rd_valid_o => dsp2_fofb_pos_valid_out_fifo,
rd_en_i => dsp_fofb_pos_fifo_rden
);
dsp2_fofb_pos_xy_out_fifo <= f_to_fofb_array(dsp2_fofb_pos_xy_out_fifo_slv);
(dsp2_fofb_pos_x_out_fifo, dsp2_fofb_pos_y_out_fifo) <= dsp2_fofb_pos_xy_out_fifo;
-----------------------------------------
-- FIFO read logic
-----------------------------------------
dsp_fofb_pos_rstn <= fs_ref_rstn and dsp_fofb_pos_enable_bpm_data;
dsp_fofb_pos_fifo_rden <= '1' when dsp1_fofb_pos_valid_out_fifo = '1' and
dsp2_fofb_pos_valid_out_fifo = '1' else '0';
-----------------------------------------
-- Send data to DCC
-----------------------------------------
-- Trigger signal for DCC timeframe_start.
-- Trigger pulses are synch'ed with the respective fs_clk
p_sync_start_fofb_dcc : process(fs_ref_clk)
begin
if rising_edge(fs_ref_clk) then
if fs_ref_rstn = '0' then
fai_fa_pl_state <= IDLE;
fai_fa_pl_data_valid_r <= '0';
dsp_fofb_pos_enable_bpm_data <= '0';
else
case fai_fa_pl_state is
when IDLE =>
fai_fa_pl_data_valid_r <= '0';
-- we cross domains here, but fofb_cc_enable is pretty much
-- static, controlled by software.
if fofb_cc_enable(c_FOFB_CC_P2P_ID) = '1' then
fai_fa_pl_state <= WAIT_TRIGGER;
end if;
when WAIT_TRIGGER =>
if fofb_cc_enable(c_FOFB_CC_P2P_ID) = '0' then
fai_fa_pl_state <= IDLE;
-- use FOFB CC ID as the TRIGGER_MUX ID
elsif trig_pulse_rcv(c_FOFB_CC_P2P_ID, c_ACQ_DCC_ID).pulse = '1' then
dsp_fofb_pos_enable_bpm_data <= '1';
fai_fa_pl_state <= SEND_BPM_DATA;
end if;
when SEND_BPM_DATA =>
fai_fa_pl_data_valid_r <= dsp_fofb_pos_fifo_rden;
fai_fa_pl_d_x_r <= dsp2_fofb_pos_x_out_fifo & dsp1_fofb_pos_x_out_fifo;
fai_fa_pl_d_y_r <= dsp2_fofb_pos_y_out_fifo & dsp1_fofb_pos_y_out_fifo;
if fofb_cc_enable(c_FOFB_CC_P2P_ID) = '0' then
fai_fa_pl_data_valid_r <= '0';
dsp_fofb_pos_enable_bpm_data <= '0';
fai_fa_pl_state <= IDLE;
end if;
when others =>
fai_fa_pl_data_valid_r <= '0';
dsp_fofb_pos_enable_bpm_data <= '0';
fai_fa_pl_state <= IDLE;
end case;
end if;
end if;
end process;
cmp_fofb_ctrl_wrapper_1 : xwb_fofb_ctrl_wrapper
generic map
(
g_INTERFACE_MODE => PIPELINED,
g_ADDRESS_GRANULARITY => BYTE,
g_ID => 0,
g_DEVICE => BPM,
g_PHYSICAL_INTERFACE => "BACKPLANE",
-- clock from right-side GTP
g_REFCLK_INPUT => "REFCLK1",
-- if FP P2P is used we take ref. clock from it, if not we instantiate
-- the clock buffers ourselves
g_CLK_BUFFERS => true,
g_USE_PARALLEL_FA_IF => true,
g_LANE_COUNT => c_NUM_P2P_GTS,
g_BPMS => c_BPMS,
g_USE_CHIPSCOPE => c_USE_CHIPSCOPE,
-- BPM synthetic data
g_SIM_BPM_DATA => false
)
port map
(
-- Only used when CLK_BUFFERS := false
---------------------------------------------------------------------------
-- differential MGT/GTP clock inputs
---------------------------------------------------------------------------
refclk_p_i => fofb_ref_clk_p(c_FOFB_CC_P2P_ID),
refclk_n_i => fofb_ref_clk_n(c_FOFB_CC_P2P_ID),
---------------------------------------------------------------------------
-- clock and reset interface
---------------------------------------------------------------------------
adcclk_i => fs_ref_clk,
adcreset_i => fs_ref_rst,
sysclk_i => clk_sys,
sysreset_n_i => fofb_sysreset_n(c_FOFB_CC_P2P_ID),
fai_fa_pl_data_valid_i => fai_fa_pl_data_valid_r,
fai_fa_pl_d_x_i => fai_fa_pl_d_x_r,
fai_fa_pl_d_y_i => fai_fa_pl_d_y_r,
---------------------------------------------------------------------------
-- Wishbone Control Interface signals
---------------------------------------------------------------------------
wb_slv_i => user_wb_out(c_SLV_FOFB_CC_P2P_ID),
wb_slv_o => user_wb_in(c_SLV_FOFB_CC_P2P_ID),
---------------------------------------------------------------------------
-- serial I/Os for eight RocketIOs on the Libera
---------------------------------------------------------------------------
fai_rio_rdp_i => fofb_rio_rx_p(c_FOFB_CC_P2P_ID)(c_NUM_P2P_GTS-1 downto 0),
fai_rio_rdn_i => fofb_rio_rx_n(c_FOFB_CC_P2P_ID)(c_NUM_P2P_GTS-1 downto 0),
fai_rio_tdp_o => fofb_rio_tx_p(c_FOFB_CC_P2P_ID)(c_NUM_P2P_GTS-1 downto 0),
fai_rio_tdn_o => fofb_rio_tx_n(c_FOFB_CC_P2P_ID)(c_NUM_P2P_GTS-1 downto 0),
fai_rio_tdis_o => fofb_rio_tx_disable(c_FOFB_CC_P2P_ID)(c_NUM_P2P_GTS-1 downto 0),
---------------------------------------------------------------------------
-- Higher-level integration interface (PMC, SNIFFER_V5)
---------------------------------------------------------------------------
fofb_userclk_o => fofb_userclk(c_FOFB_CC_P2P_ID),
fofb_userrst_o => fofb_userrst(c_FOFB_CC_P2P_ID),
timeframe_start_o => timeframe_start(c_FOFB_CC_P2P_ID),
timeframe_end_o => timeframe_end(c_FOFB_CC_P2P_ID),
fofb_dma_ok_i => fofb_dma_ok(c_FOFB_CC_P2P_ID),
fofb_node_mask_o => fofb_node_mask(c_FOFB_CC_P2P_ID),
fofb_timestamp_val_o => fofb_timestamp_val(c_FOFB_CC_P2P_ID),
fofb_link_status_o => fofb_link_status(c_FOFB_CC_P2P_ID),
fofb_cc_enable_o => fofb_cc_enable(c_FOFB_CC_P2P_ID),
fofb_fod_dat_o => fofb_fod_dat(c_FOFB_CC_P2P_ID),
fofb_fod_dat_val_o => fofb_fod_dat_val(c_FOFB_CC_P2P_ID)(c_NUM_P2P_GTS-1 downto 0)
);
fofb_sysreset_n(c_FOFB_CC_P2P_ID) <= clk_sys_rstn and afc_si57x_reconfig_rst_n;
fofb_userrst_n(c_FOFB_CC_P2P_ID) <= not fofb_userrst(c_FOFB_CC_P2P_ID);
-- CDC between FOFB clock and ACQ clock
cmp_inferred_async_fwft_fifo : inferred_async_fwft_fifo
generic map
(
g_data_width => c_FOFB_DCC_DATA_WIDTH,
g_size => 8,
g_almost_empty_threshold => 1,
g_almost_full_threshold => 7,
g_async => true
)
port map
(
-- Write clock
wr_clk_i => fofb_userclk(c_FOFB_CC_P2P_ID),
wr_rst_n_i => fofb_userrst_n(c_FOFB_CC_P2P_ID),
wr_data_i => fofb_fod_dat(c_FOFB_CC_P2P_ID),
wr_en_i => fofb_fod_dat_val(c_FOFB_CC_P2P_ID)(0),
-- Read clock
rd_clk_i => fs1_clk,
rd_rst_n_i => fs1_rstn,
rd_data_o => fofb_fod_dat_fs_sync(c_FOFB_CC_P2P_ID),
rd_valid_o => fofb_fod_dat_val_fs_sync(c_FOFB_CC_P2P_ID)(0),
rd_en_i => '1'
);
end generate;
gen_without_p2p_fofb_dcc: if (not c_WITH_P2P_FOFB_DCC) generate
fofb_fod_dat_fs_sync(c_FOFB_CC_P2P_ID) <= (others => '0');
fofb_fod_dat_val_fs_sync(c_FOFB_CC_P2P_ID) <= (others => '0');
end generate;
-- If only P2P FOFB is available use its acquisition channel so it's easier
-- for software, if not, P2P data will be forwarded to the RTM DCC. So, that
-- will be eventually stored as well.
gen_only_p2p_fofb_dcc : if (not c_WITH_RTM_SFP_FOFB_DCC) generate
gen_p2p_fofb_dcc : if c_WITH_P2P_FOFB_DCC generate
fofb_fod_dat_fs_sync(c_FOFB_CC_RTM_ID) <= fofb_fod_dat_fs_sync(c_FOFB_CC_P2P_ID);
fofb_fod_dat_val_fs_sync(c_FOFB_CC_RTM_ID) <= fofb_fod_dat_val_fs_sync(c_FOFB_CC_P2P_ID);
end generate;
gen_no_fofb_dcc : if (not c_WITH_P2P_FOFB_DCC) generate
fofb_fod_dat_fs_sync(c_FOFB_CC_RTM_ID) <= (others => '0');
fofb_fod_dat_val_fs_sync(c_FOFB_CC_RTM_ID) <= (others => '0');
end generate;
end generate;
----------------------------------------------------------------------
-- Acquisition Core --
----------------------------------------------------------------------
fs_clk_array <= fs2_clk & fs1_clk & fs2_clk & fs1_clk;
fs_ce_array <= "1111";
fs_rst_n_array <= fs2_rstn & fs1_rstn & fs2_rstn & fs1_rstn;
--------------------
-- ADC 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_adc_id).val(to_integer(c_facq_channels(c_acq_adc_id).width)-1 downto 0) <=
fmc1_adc_data_se_ch3 &
fmc1_adc_data_se_ch2 &
fmc1_adc_data_se_ch1 &
fmc1_adc_data_se_ch0;
acq_chan_array(c_acq_core_0_id, c_acq_adc_id).dvalid <= fmc1_adc_valid;
acq_chan_array(c_acq_core_0_id, c_acq_adc_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_adc_id).pulse;
--------------------
-- ADC SWAP 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_adc_swap_id).val(to_integer(c_facq_channels(c_acq_adc_swap_id).width)-1 downto 0) <=
dsp1_adc_se_ch3_data &
dsp1_adc_se_ch2_data &
dsp1_adc_se_ch1_data &
dsp1_adc_se_ch0_data;
acq_chan_array(c_acq_core_0_id, c_acq_adc_swap_id).dvalid <= dsp1_adc_valid;
acq_chan_array(c_acq_core_0_id, c_acq_adc_swap_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_adc_swap_id).pulse;
--------------------
-- MIXER I/Q 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_mixiq_id).val(to_integer(c_facq_channels(c_acq_mixiq_id).width)-1 downto 0) <=
dsp1_mixq_ch3 &
dsp1_mixi_ch3 &
dsp1_mixq_ch2 &
dsp1_mixi_ch2 &
dsp1_mixq_ch1 &
dsp1_mixi_ch1 &
dsp1_mixq_ch0 &
dsp1_mixi_ch0;
acq_chan_array(c_acq_core_0_id, c_acq_mixiq_id).dvalid <= dsp1_mix_valid;
acq_chan_array(c_acq_core_0_id, c_acq_mixiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_mixiq_id).pulse;
--------------------
-- DUMMY 0 (for compatibility)
--------------------
acq_chan_array(c_acq_core_0_id, c_dummy0_id).val(to_integer(c_facq_channels(c_dummy0_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_0_id, c_dummy0_id).dvalid <= '0';
acq_chan_array(c_acq_core_0_id, c_dummy0_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_dummy0_id).pulse;
--------------------
-- TBT I/Q 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_tbtdecimiq_id).val(to_integer(c_facq_channels(c_acq_tbtdecimiq_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_tbtdecimq_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimi_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimq_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimi_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimq_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimi_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimq_ch0), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimi_ch0), 32));
acq_chan_array(c_acq_core_0_id, c_acq_tbtdecimiq_id).dvalid <= dsp1_tbtdecim_valid;
acq_chan_array(c_acq_core_0_id, c_acq_tbtdecimiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_tbtdecimiq_id).pulse;
--------------------
-- DUMMY 1 (for compatibility)
--------------------
acq_chan_array(c_acq_core_0_id, c_dummy1_id).val(to_integer(c_facq_channels(c_dummy1_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_0_id, c_dummy1_id).dvalid <= '0';
acq_chan_array(c_acq_core_0_id, c_dummy1_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_dummy1_id).pulse;
--------------------
-- TBT AMP 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_tbt_amp_id).val(to_integer(c_facq_channels(c_acq_tbt_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_tbt_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_amp_ch0), 32));
acq_chan_array(c_acq_core_0_id, c_acq_tbt_amp_id).dvalid <= dsp1_tbt_amp_valid;
acq_chan_array(c_acq_core_0_id, c_acq_tbt_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_tbt_amp_id).pulse;
--------------------
-- TBT PHASE 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_tbt_phase_id).val(to_integer(c_facq_channels(c_acq_tbt_phase_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_tbt_pha_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pha_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pha_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pha_ch0), 32));
acq_chan_array(c_acq_core_0_id, c_acq_tbt_phase_id).dvalid <= dsp1_tbt_pha_valid;
acq_chan_array(c_acq_core_0_id, c_acq_tbt_phase_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_tbt_phase_id).pulse;
--------------------
-- TBT POS 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_tbt_pos_id).val(to_integer(c_facq_channels(c_acq_tbt_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_tbt_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pos_q), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pos_y), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pos_x), 32));
acq_chan_array(c_acq_core_0_id, c_acq_tbt_pos_id).dvalid <= dsp1_tbt_pos_valid;
acq_chan_array(c_acq_core_0_id, c_acq_tbt_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_tbt_pos_id).pulse;
--------------------
-- FOFB I/Q 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_fofbdecimiq_id).val(to_integer(c_facq_channels(c_acq_fofbdecimiq_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_fofbdecimq_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimi_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimq_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimi_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimq_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimi_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimq_ch0), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimi_ch0), 32));
acq_chan_array(c_acq_core_0_id, c_acq_fofbdecimiq_id).dvalid <= dsp1_fofbdecim_valid;
acq_chan_array(c_acq_core_0_id, c_acq_fofbdecimiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_fofbdecimiq_id).pulse;
--------------------
-- DUMMY 2 (for compatibility)
--------------------
acq_chan_array(c_acq_core_0_id, c_dummy2_id).val(to_integer(c_facq_channels(c_dummy2_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_0_id, c_dummy2_id).dvalid <= '0';
acq_chan_array(c_acq_core_0_id, c_dummy2_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_dummy1_id).pulse;
--------------------
-- FOFB AMP 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_fofb_amp_id).val(to_integer(c_facq_channels(c_acq_fofb_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_fofb_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_amp_ch0), 32));
acq_chan_array(c_acq_core_0_id, c_acq_fofb_amp_id).dvalid <= dsp1_fofb_amp_valid;
acq_chan_array(c_acq_core_0_id, c_acq_fofb_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_fofb_amp_id).pulse;
--------------------
-- FOFB PHASE 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_fofb_phase_id).val(to_integer(c_facq_channels(c_acq_fofb_phase_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_fofb_pha_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pha_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pha_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pha_ch0), 32));
acq_chan_array(c_acq_core_0_id, c_acq_fofb_phase_id).dvalid <= dsp1_fofb_pha_valid;
acq_chan_array(c_acq_core_0_id, c_acq_fofb_phase_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_fofb_phase_id).pulse;
--------------------
-- FOFB POS 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_fofb_pos_id).val(to_integer(c_facq_channels(c_acq_fofb_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_fofb_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pos_q), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pos_y), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pos_x), 32));
acq_chan_array(c_acq_core_0_id, c_acq_fofb_pos_id).dvalid <= dsp1_fofb_pos_valid;
acq_chan_array(c_acq_core_0_id, c_acq_fofb_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_fofb_pos_id).pulse;
--------------------
-- MONIT1 AMP 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_monit1_amp_id).val(to_integer(c_facq_channels(c_acq_monit1_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_monit1_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_amp_ch0), 32));
acq_chan_array(c_acq_core_0_id, c_acq_monit1_amp_id).dvalid <= dsp1_monit1_amp_valid;
acq_chan_array(c_acq_core_0_id, c_acq_monit1_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_monit1_amp_id).pulse;
--------------------
-- MONIT1 POS 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_monit1_pos_id).val(to_integer(c_facq_channels(c_acq_monit1_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_monit1_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_pos_q), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_pos_y), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_pos_x), 32));
acq_chan_array(c_acq_core_0_id, c_acq_monit1_pos_id).dvalid <= dsp1_monit1_pos_valid;
acq_chan_array(c_acq_core_0_id, c_acq_monit1_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_monit1_pos_id).pulse;
--------------------
-- MONIT AMP 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_monit_amp_id).val(to_integer(c_facq_channels(c_acq_monit_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_monit_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_monit_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_monit_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_monit_amp_ch0), 32));
acq_chan_array(c_acq_core_0_id, c_acq_monit_amp_id).dvalid <= dsp1_monit_amp_valid;
acq_chan_array(c_acq_core_0_id, c_acq_monit_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_monit_amp_id).pulse;
--------------------
-- MONIT POS 1 data
--------------------
acq_chan_array(c_acq_core_0_id, c_acq_monit_pos_id).val(to_integer(c_facq_channels(c_acq_monit_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_monit_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp1_monit_pos_q), 32)) &
std_logic_vector(resize(signed(dsp1_monit_pos_y), 32)) &
std_logic_vector(resize(signed(dsp1_monit_pos_x), 32));
acq_chan_array(c_acq_core_0_id, c_acq_monit_pos_id).dvalid <= dsp1_monit_pos_valid;
acq_chan_array(c_acq_core_0_id, c_acq_monit_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_acq_monit_pos_id).pulse;
--------------------
-- FOFB DCC data
--------------------
acq_chan_array(c_acq_core_0_id, c_ACQ_DCC_ID).val(to_integer(c_facq_channels(c_ACQ_DCC_ID).width)-1 downto 0) <=
fofb_fod_dat_fs_sync(c_FOFB_CC_RTM_ID);
acq_chan_array(c_acq_core_0_id, c_ACQ_DCC_ID).dvalid <= fofb_fod_dat_val_fs_sync(c_FOFB_CC_RTM_ID)(0);
acq_chan_array(c_acq_core_0_id, c_ACQ_DCC_ID).trig <= trig_pulse_rcv(c_TRIG_MUX_0_ID, c_ACQ_DCC_ID).pulse;
--------------------
-- ADC 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_adc_id).val(to_integer(c_facq_channels(c_acq_adc_id).width)-1 downto 0) <=
fmc2_adc_data_se_ch3 &
fmc2_adc_data_se_ch2 &
fmc2_adc_data_se_ch1 &
fmc2_adc_data_se_ch0;
acq_chan_array(c_acq_core_1_id, c_acq_adc_id).dvalid <= fmc2_adc_valid;
acq_chan_array(c_acq_core_1_id, c_acq_adc_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_adc_id).pulse;
--------------------
-- ADC SWAP 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_adc_swap_id).val(to_integer(c_facq_channels(c_acq_adc_swap_id).width)-1 downto 0) <=
dsp2_adc_se_ch3_data &
dsp2_adc_se_ch2_data &
dsp2_adc_se_ch1_data &
dsp2_adc_se_ch0_data;
acq_chan_array(c_acq_core_1_id, c_acq_adc_swap_id).dvalid <= dsp2_adc_valid;
acq_chan_array(c_acq_core_1_id, c_acq_adc_swap_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_adc_swap_id).pulse;
--------------------
-- MIXER I/Q 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_mixiq_id).val(to_integer(c_facq_channels(c_acq_mixiq_id).width)-1 downto 0) <=
dsp2_mixq_ch3 &
dsp2_mixi_ch3 &
dsp2_mixq_ch2 &
dsp2_mixi_ch2 &
dsp2_mixq_ch1 &
dsp2_mixi_ch1 &
dsp2_mixq_ch0 &
dsp2_mixi_ch0;
acq_chan_array(c_acq_core_1_id, c_acq_mixiq_id).dvalid <= dsp2_mix_valid;
acq_chan_array(c_acq_core_1_id, c_acq_mixiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_mixiq_id).pulse;
--------------------
-- DUMMY 0 (for compatibility)
--------------------
acq_chan_array(c_acq_core_1_id, c_dummy0_id).val(to_integer(c_facq_channels(c_dummy0_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_1_id, c_dummy0_id).dvalid <= '0';
acq_chan_array(c_acq_core_1_id, c_dummy0_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_dummy0_id).pulse;
--------------------
-- TBT I/Q 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_tbtdecimiq_id).val(to_integer(c_facq_channels(c_acq_tbtdecimiq_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_tbtdecimq_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimi_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimq_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimi_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimq_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimi_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimq_ch0), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimi_ch0), 32));
acq_chan_array(c_acq_core_1_id, c_acq_tbtdecimiq_id).dvalid <= dsp2_tbtdecim_valid;
acq_chan_array(c_acq_core_1_id, c_acq_tbtdecimiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_tbtdecimiq_id).pulse;
--------------------
-- DUMMY 1 (for compatibility)
--------------------
acq_chan_array(c_acq_core_1_id, c_dummy1_id).val(to_integer(c_facq_channels(c_dummy1_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_1_id, c_dummy1_id).dvalid <= '0';
acq_chan_array(c_acq_core_1_id, c_dummy1_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_dummy1_id).pulse;
--------------------
-- TBT AMP 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_tbt_amp_id).val(to_integer(c_facq_channels(c_acq_tbt_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_tbt_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_amp_ch0), 32));
acq_chan_array(c_acq_core_1_id, c_acq_tbt_amp_id).dvalid <= dsp2_tbt_amp_valid;
acq_chan_array(c_acq_core_1_id, c_acq_tbt_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_tbt_amp_id).pulse;
--------------------
-- TBT PHASE 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_tbt_phase_id).val(to_integer(c_facq_channels(c_acq_tbt_phase_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_tbt_pha_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pha_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pha_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pha_ch0), 32));
acq_chan_array(c_acq_core_1_id, c_acq_tbt_phase_id).dvalid <= dsp2_tbt_pha_valid;
acq_chan_array(c_acq_core_1_id, c_acq_tbt_phase_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_tbt_phase_id).pulse;
--------------------
-- TBT POS 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_tbt_pos_id).val(to_integer(c_facq_channels(c_acq_tbt_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_tbt_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pos_q), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pos_y), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pos_x), 32));
acq_chan_array(c_acq_core_1_id, c_acq_tbt_pos_id).dvalid <= dsp2_tbt_pos_valid;
acq_chan_array(c_acq_core_1_id, c_acq_tbt_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_tbt_pos_id).pulse;
--------------------
-- FOFB I/Q 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_fofbdecimiq_id).val(to_integer(c_facq_channels(c_acq_fofbdecimiq_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_fofbdecimq_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimi_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimq_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimi_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimq_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimi_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimq_ch0), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimi_ch0), 32));
acq_chan_array(c_acq_core_1_id, c_acq_fofbdecimiq_id).dvalid <= dsp2_fofbdecim_valid;
acq_chan_array(c_acq_core_1_id, c_acq_fofbdecimiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_fofbdecimiq_id).pulse;
--------------------
-- DUMMY 2 (for compatibility)
--------------------
acq_chan_array(c_acq_core_1_id, c_dummy2_id).val(to_integer(c_facq_channels(c_dummy2_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_1_id, c_dummy2_id).dvalid <= '0';
acq_chan_array(c_acq_core_1_id, c_dummy2_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_dummy1_id).pulse;
--------------------
-- FOFB AMP 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_fofb_amp_id).val(to_integer(c_facq_channels(c_acq_fofb_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_fofb_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_amp_ch0), 32));
acq_chan_array(c_acq_core_1_id, c_acq_fofb_amp_id).dvalid <= dsp2_fofb_amp_valid;
acq_chan_array(c_acq_core_1_id, c_acq_fofb_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_fofb_amp_id).pulse;
--------------------
-- FOFB PHASE 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_fofb_phase_id).val(to_integer(c_facq_channels(c_acq_fofb_phase_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_fofb_pha_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pha_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pha_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pha_ch0), 32));
acq_chan_array(c_acq_core_1_id, c_acq_fofb_phase_id).dvalid <= dsp2_fofb_pha_valid;
acq_chan_array(c_acq_core_1_id, c_acq_fofb_phase_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_fofb_phase_id).pulse;
--------------------
-- FOFB POS 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_fofb_pos_id).val(to_integer(c_facq_channels(c_acq_fofb_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_fofb_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pos_q), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pos_y), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pos_x), 32));
acq_chan_array(c_acq_core_1_id, c_acq_fofb_pos_id).dvalid <= dsp2_fofb_pos_valid;
acq_chan_array(c_acq_core_1_id, c_acq_fofb_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_fofb_pos_id).pulse;
--------------------
-- MONIT1 AMP 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_monit1_amp_id).val(to_integer(c_facq_channels(c_acq_monit1_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_monit1_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_amp_ch0), 32));
acq_chan_array(c_acq_core_1_id, c_acq_monit1_amp_id).dvalid <= dsp2_monit1_amp_valid;
acq_chan_array(c_acq_core_1_id, c_acq_monit1_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_monit1_amp_id).pulse;
--------------------
-- MONIT1 POS 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_monit1_pos_id).val(to_integer(c_facq_channels(c_acq_monit1_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_monit1_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_pos_q), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_pos_y), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_pos_x), 32));
acq_chan_array(c_acq_core_1_id, c_acq_monit1_pos_id).dvalid <= dsp2_monit1_pos_valid;
acq_chan_array(c_acq_core_1_id, c_acq_monit1_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_monit1_pos_id).pulse;
--------------------
-- MONIT AMP 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_monit_amp_id).val(to_integer(c_facq_channels(c_acq_monit_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_monit_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_monit_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_monit_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_monit_amp_ch0), 32));
acq_chan_array(c_acq_core_1_id, c_acq_monit_amp_id).dvalid <= dsp2_monit_amp_valid;
acq_chan_array(c_acq_core_1_id, c_acq_monit_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_monit_amp_id).pulse;
--------------------
-- MONIT POS 2 data
--------------------
acq_chan_array(c_acq_core_1_id, c_acq_monit_pos_id).val(to_integer(c_facq_channels(c_acq_monit_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_monit_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp2_monit_pos_q), 32)) &
std_logic_vector(resize(signed(dsp2_monit_pos_y), 32)) &
std_logic_vector(resize(signed(dsp2_monit_pos_x), 32));
acq_chan_array(c_acq_core_1_id, c_acq_monit_pos_id).dvalid <= dsp2_monit_pos_valid;
acq_chan_array(c_acq_core_1_id, c_acq_monit_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_1_ID, c_acq_monit_pos_id).pulse;
--------------------
-- ADC 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_adc_id).val(to_integer(c_facq_channels(c_acq_adc_id).width)-1 downto 0) <=
fmc1_adc_data_se_ch3 &
fmc1_adc_data_se_ch2 &
fmc1_adc_data_se_ch1 &
fmc1_adc_data_se_ch0;
acq_chan_array(c_acq_core_2_id, c_acq_adc_id).dvalid <= fmc1_adc_valid;
acq_chan_array(c_acq_core_2_id, c_acq_adc_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_adc_id).pulse;
--------------------
-- ADC SWAP 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_adc_swap_id).val(to_integer(c_facq_channels(c_acq_adc_swap_id).width)-1 downto 0) <=
dsp1_adc_se_ch3_data &
dsp1_adc_se_ch2_data &
dsp1_adc_se_ch1_data &
dsp1_adc_se_ch0_data;
acq_chan_array(c_acq_core_2_id, c_acq_adc_swap_id).dvalid <= dsp1_adc_valid;
acq_chan_array(c_acq_core_2_id, c_acq_adc_swap_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_adc_swap_id).pulse;
--------------------
-- MIXER I/Q 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_mixiq_id).val(to_integer(c_facq_channels(c_acq_mixiq_id).width)-1 downto 0) <=
dsp1_mixq_ch3 &
dsp1_mixi_ch3 &
dsp1_mixq_ch2 &
dsp1_mixi_ch2 &
dsp1_mixq_ch1 &
dsp1_mixi_ch1 &
dsp1_mixq_ch0 &
dsp1_mixi_ch0;
acq_chan_array(c_acq_core_2_id, c_acq_mixiq_id).dvalid <= dsp1_mix_valid;
acq_chan_array(c_acq_core_2_id, c_acq_mixiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_mixiq_id).pulse;
--------------------
-- DUMMY 0 (for compatibility)
--------------------
acq_chan_array(c_acq_core_2_id, c_dummy0_id).val(to_integer(c_facq_channels(c_dummy0_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_2_id, c_dummy0_id).dvalid <= '0';
acq_chan_array(c_acq_core_2_id, c_dummy0_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_dummy0_id).pulse;
--------------------
-- TBT I/Q 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_tbtdecimiq_id).val(to_integer(c_facq_channels(c_acq_tbtdecimiq_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_tbtdecimq_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimi_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimq_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimi_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimq_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimi_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimq_ch0), 32)) &
std_logic_vector(resize(signed(dsp1_tbtdecimi_ch0), 32));
acq_chan_array(c_acq_core_2_id, c_acq_tbtdecimiq_id).dvalid <= dsp1_tbtdecim_valid;
acq_chan_array(c_acq_core_2_id, c_acq_tbtdecimiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_tbtdecimiq_id).pulse;
--------------------
-- DUMMY 1 (for compatibility)
--------------------
acq_chan_array(c_acq_core_2_id, c_dummy1_id).val(to_integer(c_facq_channels(c_dummy1_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_2_id, c_dummy1_id).dvalid <= '0';
acq_chan_array(c_acq_core_2_id, c_dummy1_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_dummy1_id).pulse;
--------------------
-- TBT AMP 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_tbt_amp_id).val(to_integer(c_facq_channels(c_acq_tbt_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_tbt_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_amp_ch0), 32));
acq_chan_array(c_acq_core_2_id, c_acq_tbt_amp_id).dvalid <= dsp1_tbt_amp_valid;
acq_chan_array(c_acq_core_2_id, c_acq_tbt_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_tbt_amp_id).pulse;
--------------------
-- TBT PHASE 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_tbt_phase_id).val(to_integer(c_facq_channels(c_acq_tbt_phase_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_tbt_pha_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pha_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pha_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pha_ch0), 32));
acq_chan_array(c_acq_core_2_id, c_acq_tbt_phase_id).dvalid <= dsp1_tbt_pha_valid;
acq_chan_array(c_acq_core_2_id, c_acq_tbt_phase_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_tbt_phase_id).pulse;
--------------------
-- TBT POS 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_tbt_pos_id).val(to_integer(c_facq_channels(c_acq_tbt_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_tbt_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pos_q), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pos_y), 32)) &
std_logic_vector(resize(signed(dsp1_tbt_pos_x), 32));
acq_chan_array(c_acq_core_2_id, c_acq_tbt_pos_id).dvalid <= dsp1_tbt_pos_valid;
acq_chan_array(c_acq_core_2_id, c_acq_tbt_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_tbt_pos_id).pulse;
--------------------
-- FOFB I/Q 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_fofbdecimiq_id).val(to_integer(c_facq_channels(c_acq_fofbdecimiq_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_fofbdecimq_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimi_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimq_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimi_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimq_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimi_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimq_ch0), 32)) &
std_logic_vector(resize(signed(dsp1_fofbdecimi_ch0), 32));
acq_chan_array(c_acq_core_2_id, c_acq_fofbdecimiq_id).dvalid <= dsp1_fofbdecim_valid;
acq_chan_array(c_acq_core_2_id, c_acq_fofbdecimiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_fofbdecimiq_id).pulse;
--------------------
-- DUMMY 2 (for compatibility)
--------------------
acq_chan_array(c_acq_core_2_id, c_dummy2_id).val(to_integer(c_facq_channels(c_dummy2_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_2_id, c_dummy2_id).dvalid <= '0';
acq_chan_array(c_acq_core_2_id, c_dummy2_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_dummy1_id).pulse;
--------------------
-- FOFB AMP 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_fofb_amp_id).val(to_integer(c_facq_channels(c_acq_fofb_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_fofb_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_amp_ch0), 32));
acq_chan_array(c_acq_core_2_id, c_acq_fofb_amp_id).dvalid <= dsp1_fofb_amp_valid;
acq_chan_array(c_acq_core_2_id, c_acq_fofb_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_fofb_amp_id).pulse;
--------------------
-- FOFB PHASE 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_fofb_phase_id).val(to_integer(c_facq_channels(c_acq_fofb_phase_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_fofb_pha_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pha_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pha_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pha_ch0), 32));
acq_chan_array(c_acq_core_2_id, c_acq_fofb_phase_id).dvalid <= dsp1_fofb_pha_valid;
acq_chan_array(c_acq_core_2_id, c_acq_fofb_phase_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_fofb_phase_id).pulse;
--------------------
-- FOFB POS 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_fofb_pos_id).val(to_integer(c_facq_channels(c_acq_fofb_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_fofb_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pos_q), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pos_y), 32)) &
std_logic_vector(resize(signed(dsp1_fofb_pos_x), 32));
acq_chan_array(c_acq_core_2_id, c_acq_fofb_pos_id).dvalid <= dsp1_fofb_pos_valid;
acq_chan_array(c_acq_core_2_id, c_acq_fofb_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_fofb_pos_id).pulse;
--------------------
-- MONIT1 AMP 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_monit1_amp_id).val(to_integer(c_facq_channels(c_acq_monit1_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_monit1_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_amp_ch0), 32));
acq_chan_array(c_acq_core_2_id, c_acq_monit1_amp_id).dvalid <= dsp1_monit1_amp_valid;
acq_chan_array(c_acq_core_2_id, c_acq_monit1_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_monit1_amp_id).pulse;
--------------------
-- MONIT1 POS 3 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_monit1_pos_id).val(to_integer(c_facq_channels(c_acq_monit1_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_monit1_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_pos_q), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_pos_y), 32)) &
std_logic_vector(resize(signed(dsp1_monit1_pos_x), 32));
acq_chan_array(c_acq_core_2_id, c_acq_monit1_pos_id).dvalid <= dsp1_monit1_pos_valid;
acq_chan_array(c_acq_core_2_id, c_acq_monit1_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_monit1_pos_id).pulse;
--------------------
-- MONIT AMP 1 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_monit_amp_id).val(to_integer(c_facq_channels(c_acq_monit_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_monit_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp1_monit_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp1_monit_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp1_monit_amp_ch0), 32));
acq_chan_array(c_acq_core_2_id, c_acq_monit_amp_id).dvalid <= dsp1_monit_amp_valid;
acq_chan_array(c_acq_core_2_id, c_acq_monit_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_monit_amp_id).pulse;
--------------------
-- MONIT POS 1 data
--------------------
acq_chan_array(c_acq_core_2_id, c_acq_monit_pos_id).val(to_integer(c_facq_channels(c_acq_monit_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp1_monit_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp1_monit_pos_q), 32)) &
std_logic_vector(resize(signed(dsp1_monit_pos_y), 32)) &
std_logic_vector(resize(signed(dsp1_monit_pos_x), 32));
acq_chan_array(c_acq_core_2_id, c_acq_monit_pos_id).dvalid <= dsp1_monit_pos_valid;
acq_chan_array(c_acq_core_2_id, c_acq_monit_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_2_ID, c_acq_monit_pos_id).pulse;
--------------------
-- ADC 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_adc_id).val(to_integer(c_facq_channels(c_acq_adc_id).width)-1 downto 0) <=
fmc2_adc_data_se_ch3 &
fmc2_adc_data_se_ch2 &
fmc2_adc_data_se_ch1 &
fmc2_adc_data_se_ch0;
acq_chan_array(c_acq_core_3_id, c_acq_adc_id).dvalid <= fmc2_adc_valid;
acq_chan_array(c_acq_core_3_id, c_acq_adc_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_adc_id).pulse;
--------------------
-- ADC SWAP 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_adc_swap_id).val(to_integer(c_facq_channels(c_acq_adc_swap_id).width)-1 downto 0) <=
dsp2_adc_se_ch3_data &
dsp2_adc_se_ch2_data &
dsp2_adc_se_ch1_data &
dsp2_adc_se_ch0_data;
acq_chan_array(c_acq_core_3_id, c_acq_adc_swap_id).dvalid <= dsp2_adc_valid;
acq_chan_array(c_acq_core_3_id, c_acq_adc_swap_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_adc_swap_id).pulse;
--------------------
-- MIXER I/Q 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_mixiq_id).val(to_integer(c_facq_channels(c_acq_mixiq_id).width)-1 downto 0) <=
dsp2_mixq_ch3 &
dsp2_mixi_ch3 &
dsp2_mixq_ch2 &
dsp2_mixi_ch2 &
dsp2_mixq_ch1 &
dsp2_mixi_ch1 &
dsp2_mixq_ch0 &
dsp2_mixi_ch0;
acq_chan_array(c_acq_core_3_id, c_acq_mixiq_id).dvalid <= dsp2_mix_valid;
acq_chan_array(c_acq_core_3_id, c_acq_mixiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_mixiq_id).pulse;
--------------------
-- DUMMY 0 (for compatibility)
--------------------
acq_chan_array(c_acq_core_3_id, c_dummy0_id).val(to_integer(c_facq_channels(c_dummy0_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_3_id, c_dummy0_id).dvalid <= '0';
acq_chan_array(c_acq_core_3_id, c_dummy0_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_dummy0_id).pulse;
--------------------
-- TBT I/Q 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_tbtdecimiq_id).val(to_integer(c_facq_channels(c_acq_tbtdecimiq_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_tbtdecimq_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimi_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimq_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimi_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimq_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimi_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimq_ch0), 32)) &
std_logic_vector(resize(signed(dsp2_tbtdecimi_ch0), 32));
acq_chan_array(c_acq_core_3_id, c_acq_tbtdecimiq_id).dvalid <= dsp2_tbtdecim_valid;
acq_chan_array(c_acq_core_3_id, c_acq_tbtdecimiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_tbtdecimiq_id).pulse;
--------------------
-- DUMMY 1 (for compatibility)
--------------------
acq_chan_array(c_acq_core_3_id, c_dummy1_id).val(to_integer(c_facq_channels(c_dummy1_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_3_id, c_dummy1_id).dvalid <= '0';
acq_chan_array(c_acq_core_3_id, c_dummy1_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_dummy1_id).pulse;
--------------------
-- TBT AMP 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_tbt_amp_id).val(to_integer(c_facq_channels(c_acq_tbt_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_tbt_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_amp_ch0), 32));
acq_chan_array(c_acq_core_3_id, c_acq_tbt_amp_id).dvalid <= dsp2_tbt_amp_valid;
acq_chan_array(c_acq_core_3_id, c_acq_tbt_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_tbt_amp_id).pulse;
--------------------
-- TBT PHASE 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_tbt_phase_id).val(to_integer(c_facq_channels(c_acq_tbt_phase_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_tbt_pha_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pha_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pha_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pha_ch0), 32));
acq_chan_array(c_acq_core_3_id, c_acq_tbt_phase_id).dvalid <= dsp2_tbt_pha_valid;
acq_chan_array(c_acq_core_3_id, c_acq_tbt_phase_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_tbt_phase_id).pulse;
--------------------
-- TBT POS 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_tbt_pos_id).val(to_integer(c_facq_channels(c_acq_tbt_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_tbt_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pos_q), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pos_y), 32)) &
std_logic_vector(resize(signed(dsp2_tbt_pos_x), 32));
acq_chan_array(c_acq_core_3_id, c_acq_tbt_pos_id).dvalid <= dsp2_tbt_pos_valid;
acq_chan_array(c_acq_core_3_id, c_acq_tbt_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_tbt_pos_id).pulse;
--------------------
-- FOFB I/Q 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_fofbdecimiq_id).val(to_integer(c_facq_channels(c_acq_fofbdecimiq_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_fofbdecimq_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimi_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimq_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimi_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimq_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimi_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimq_ch0), 32)) &
std_logic_vector(resize(signed(dsp2_fofbdecimi_ch0), 32));
acq_chan_array(c_acq_core_3_id, c_acq_fofbdecimiq_id).dvalid <= dsp2_fofbdecim_valid;
acq_chan_array(c_acq_core_3_id, c_acq_fofbdecimiq_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_fofbdecimiq_id).pulse;
--------------------
-- DUMMY 2 (for compatibility)
--------------------
acq_chan_array(c_acq_core_3_id, c_dummy2_id).val(to_integer(c_facq_channels(c_dummy2_id).width)-1 downto 0) <=
(others => '0');
acq_chan_array(c_acq_core_3_id, c_dummy2_id).dvalid <= '0';
acq_chan_array(c_acq_core_3_id, c_dummy2_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_dummy2_id).pulse;
--------------------
-- FOFB AMP 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_fofb_amp_id).val(to_integer(c_facq_channels(c_acq_fofb_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_fofb_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_amp_ch0), 32));
acq_chan_array(c_acq_core_3_id, c_acq_fofb_amp_id).dvalid <= dsp2_fofb_amp_valid;
acq_chan_array(c_acq_core_3_id, c_acq_fofb_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_fofb_amp_id).pulse;
--------------------
-- FOFB PHASE 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_fofb_phase_id).val(to_integer(c_facq_channels(c_acq_fofb_phase_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_fofb_pha_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pha_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pha_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pha_ch0), 32));
acq_chan_array(c_acq_core_3_id, c_acq_fofb_phase_id).dvalid <= dsp2_fofb_pha_valid;
acq_chan_array(c_acq_core_3_id, c_acq_fofb_phase_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_fofb_phase_id).pulse;
--------------------
-- FOFB POS 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_fofb_pos_id).val(to_integer(c_facq_channels(c_acq_fofb_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_fofb_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pos_q), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pos_y), 32)) &
std_logic_vector(resize(signed(dsp2_fofb_pos_x), 32));
acq_chan_array(c_acq_core_3_id, c_acq_fofb_pos_id).dvalid <= dsp2_fofb_pos_valid;
acq_chan_array(c_acq_core_3_id, c_acq_fofb_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_fofb_pos_id).pulse;
--------------------
-- MONIT1 AMP 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_monit1_amp_id).val(to_integer(c_facq_channels(c_acq_monit1_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_monit1_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_amp_ch0), 32));
acq_chan_array(c_acq_core_3_id, c_acq_monit1_amp_id).dvalid <= dsp2_monit1_amp_valid;
acq_chan_array(c_acq_core_3_id, c_acq_monit1_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_monit1_amp_id).pulse;
--------------------
-- MONIT1 POS 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_monit1_pos_id).val(to_integer(c_facq_channels(c_acq_monit1_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_monit1_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_pos_q), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_pos_y), 32)) &
std_logic_vector(resize(signed(dsp2_monit1_pos_x), 32));
acq_chan_array(c_acq_core_3_id, c_acq_monit1_pos_id).dvalid <= dsp2_monit1_pos_valid;
acq_chan_array(c_acq_core_3_id, c_acq_monit1_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_monit1_pos_id).pulse;
--------------------
-- MONIT AMP 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_monit_amp_id).val(to_integer(c_facq_channels(c_acq_monit_amp_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_monit_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp2_monit_amp_ch2), 32)) &
std_logic_vector(resize(signed(dsp2_monit_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp2_monit_amp_ch0), 32));
acq_chan_array(c_acq_core_3_id, c_acq_monit_amp_id).dvalid <= dsp2_monit_amp_valid;
acq_chan_array(c_acq_core_3_id, c_acq_monit_amp_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_monit_amp_id).pulse;
--------------------
-- MONIT POS 4 data
--------------------
acq_chan_array(c_acq_core_3_id, c_acq_monit_pos_id).val(to_integer(c_facq_channels(c_acq_monit_pos_id).width)-1 downto 0) <=
std_logic_vector(resize(signed(dsp2_monit_pos_sum), 32)) &
std_logic_vector(resize(signed(dsp2_monit_pos_q), 32)) &
std_logic_vector(resize(signed(dsp2_monit_pos_y), 32)) &
std_logic_vector(resize(signed(dsp2_monit_pos_x), 32));
acq_chan_array(c_acq_core_3_id, c_acq_monit_pos_id).dvalid <= dsp2_monit_pos_valid;
acq_chan_array(c_acq_core_3_id, c_acq_monit_pos_id).trig <= trig_pulse_rcv(c_TRIG_MUX_3_ID, c_acq_monit_pos_id).pulse;
----------------------------------------------------------------------
-- Orbit Interlock --
----------------------------------------------------------------------
cmp_xwb_orbit_intlk : xwb_orbit_intlk
generic map
(
-- Wishbone
g_ADDRESS_GRANULARITY => BYTE,
g_INTERFACE_MODE => PIPELINED,
-- Position
g_ADC_WIDTH => c_num_unprocessed_se_bits,
g_DECIM_WIDTH => c_pos_calc_fofb_decim_width
)
port map
(
-----------------------------
-- Clocks and resets
-----------------------------
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
ref_clk_i => fs1_clk,
ref_rst_n_i => fs1_rstn,
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => user_wb_out(c_SLV_ORBIT_INTLK_ID),
wb_slv_o => user_wb_in(c_SLV_ORBIT_INTLK_ID),
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i => fs1_clk,
adc_ds_ch0_swap_i => dsp1_adc_se_ch0_data,
adc_ds_ch1_swap_i => dsp1_adc_se_ch1_data,
adc_ds_ch2_swap_i => dsp1_adc_se_ch2_data,
adc_ds_ch3_swap_i => dsp1_adc_se_ch3_data,
adc_ds_tag_i => dsp1_adc_tag,
adc_ds_swap_valid_i => dsp1_adc_valid,
decim_ds_pos_x_i => dsp1_monit1_pos_x,
decim_ds_pos_y_i => dsp1_monit1_pos_y,
decim_ds_pos_q_i => dsp1_monit1_pos_q,
decim_ds_pos_sum_i => dsp1_monit1_pos_sum,
decim_ds_pos_valid_i => dsp1_monit1_pos_valid,
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i => fs2_clk,
adc_us_ch0_swap_i => dsp2_adc_se_ch0_data,
adc_us_ch1_swap_i => dsp2_adc_se_ch1_data,
adc_us_ch2_swap_i => dsp2_adc_se_ch2_data,
adc_us_ch3_swap_i => dsp2_adc_se_ch3_data,
adc_us_tag_i => dsp2_adc_tag,
adc_us_swap_valid_i => dsp2_adc_valid,
decim_us_pos_x_i => dsp2_monit1_pos_x,
decim_us_pos_y_i => dsp2_monit1_pos_y,
decim_us_pos_q_i => dsp2_monit1_pos_q,
decim_us_pos_sum_i => dsp2_monit1_pos_sum,
decim_us_pos_valid_i => dsp2_monit1_pos_valid,
-----------------------------
-- Interlock outputs
-----------------------------
-- only cleared when intlk_clr_i is asserted
intlk_ltc_o => intlk_ltc,
-- conditional to intlk_en_i
intlk_o => intlk
);
----------------------------------------------------------------------
-- Trigger --
----------------------------------------------------------------------
-- Assign FMCs trigger pulses to trigger channel interfaces
trig_fmc1_channel_1.pulse <= fmc1_trig_hw;
trig_fmc1_channel_2.pulse <= dsp1_clk_rffe_swap;
trig_fmc2_channel_1.pulse <= fmc2_trig_hw;
trig_fmc2_channel_2.pulse <= dsp2_clk_rffe_swap;
-- Post-Mortem triggers (mainly for testing. The real trigger would come from the
-- Backplane MLVDS triggers)
trig_fmc1_pm_channel_1.pulse <= '0';
trig_fmc1_pm_channel_2.pulse <= fmc1_trig_hw;
trig_fmc2_pm_channel_1.pulse <= '0';
trig_fmc2_pm_channel_2.pulse <= fmc2_trig_hw;
-- Interlock
trig_1_channel_intlk.pulse <= intlk;
trig_2_channel_intlk.pulse <= intlk;
trig_1_pm_channel_intlk.pulse <= '0';
trig_2_pm_channel_intlk.pulse <= '0';
-- Assign intern triggers to trigger module
trig_rcv_intern(c_TRIG_MUX_0_ID, c_TRIG_RCV_INTERN_CHAN_1_ID) <= trig_fmc1_channel_1;
trig_rcv_intern(c_TRIG_MUX_0_ID, c_TRIG_RCV_INTERN_CHAN_2_ID) <= trig_fmc1_channel_2;
trig_rcv_intern(c_TRIG_MUX_0_ID, c_TRIG_RCV_INTERN_CHAN_INTLK_ID) <= trig_1_channel_intlk;
trig_rcv_intern(c_TRIG_MUX_1_ID, c_TRIG_RCV_INTERN_CHAN_1_ID) <= trig_fmc2_channel_1;
trig_rcv_intern(c_TRIG_MUX_1_ID, c_TRIG_RCV_INTERN_CHAN_2_ID) <= trig_fmc2_channel_2;
trig_rcv_intern(c_TRIG_MUX_1_ID, c_TRIG_RCV_INTERN_CHAN_INTLK_ID) <= trig_2_channel_intlk;
-- Post-Mortem triggers
trig_rcv_intern(c_TRIG_MUX_2_ID, c_TRIG_RCV_INTERN_CHAN_1_ID) <= trig_fmc1_pm_channel_1;
trig_rcv_intern(c_TRIG_MUX_2_ID, c_TRIG_RCV_INTERN_CHAN_2_ID) <= trig_fmc1_pm_channel_2;
trig_rcv_intern(c_TRIG_MUX_2_ID, c_TRIG_RCV_INTERN_CHAN_INTLK_ID) <= trig_1_pm_channel_intlk;
trig_rcv_intern(c_TRIG_MUX_3_ID, c_TRIG_RCV_INTERN_CHAN_1_ID) <= trig_fmc2_pm_channel_1;
trig_rcv_intern(c_TRIG_MUX_3_ID, c_TRIG_RCV_INTERN_CHAN_2_ID) <= trig_fmc2_pm_channel_2;
trig_rcv_intern(c_TRIG_MUX_3_ID, c_TRIG_RCV_INTERN_CHAN_INTLK_ID) <= trig_2_pm_channel_intlk;
end rtl;
|
lgpl-3.0
|
03dc135479b4f15c808c83670f495398
| 0.435178 | 3.570888 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_cmp_gt/fp_cmp_gt/fp_cmp_gt_0002.vhd
| 1 | 13,698 |
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_cmp_gt_0002
-- VHDL created on Thu Feb 15 17:02:54 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cmp_gt_0002 is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(0 downto 0); -- ufix1
clk : in std_logic;
areset : in std_logic
);
end fp_cmp_gt_0002;
architecture normal of fp_cmp_gt_0002 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid6_fpCompareTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid7_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid8_fpCompareTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal exp_x_uid9_fpCompareTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_x_uid10_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_x_uid11_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid12_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid13_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid14_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid16_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal exp_y_uid23_fpCompareTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_y_uid24_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_y_uid25_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid26_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid27_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid28_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid30_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneIsNaN_uid34_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal xNotZero_uid39_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal yNotZero_uid40_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXPS_uid41_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracXPS_uid41_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracYPS_uid42_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracYPS_uid42_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expFracX_uid43_fpCompareTest_q : STD_LOGIC_VECTOR (30 downto 0);
signal expFracY_uid45_fpCompareTest_q : STD_LOGIC_VECTOR (30 downto 0);
signal efxGTefy_uid47_fpCompareTest_a : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_b : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_o : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal efxLTefy_uid48_fpCompareTest_a : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_b : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_o : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal signX_uid52_fpCompareTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signY_uid53_fpCompareTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal two_uid54_fpCompareTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal concSYSX_uid55_fpCompareTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal sxGTsy_uid56_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal xorSigns_uid57_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sxEQsy_uid58_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expFracCompMux_uid59_fpCompareTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal expFracCompMux_uid59_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneNonZero_uid62_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rc2_uid63_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sxEQsyExpFracCompMux_uid64_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal r_uid65_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rPostExc_uid66_fpCompareTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal rPostExc_uid66_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
begin
-- GND(CONSTANT,0)
GND_q <= "0";
-- cstAllZWE_uid8_fpCompareTest(CONSTANT,7)
cstAllZWE_uid8_fpCompareTest_q <= "00000000";
-- exp_y_uid23_fpCompareTest(BITSELECT,22)@0
exp_y_uid23_fpCompareTest_b <= b(30 downto 23);
-- excZ_y_uid25_fpCompareTest(LOGICAL,24)@0
excZ_y_uid25_fpCompareTest_q <= "1" WHEN exp_y_uid23_fpCompareTest_b = cstAllZWE_uid8_fpCompareTest_q ELSE "0";
-- yNotZero_uid40_fpCompareTest(LOGICAL,39)@0
yNotZero_uid40_fpCompareTest_q <= not (excZ_y_uid25_fpCompareTest_q);
-- exp_x_uid9_fpCompareTest(BITSELECT,8)@0
exp_x_uid9_fpCompareTest_b <= a(30 downto 23);
-- excZ_x_uid11_fpCompareTest(LOGICAL,10)@0
excZ_x_uid11_fpCompareTest_q <= "1" WHEN exp_x_uid9_fpCompareTest_b = cstAllZWE_uid8_fpCompareTest_q ELSE "0";
-- xNotZero_uid39_fpCompareTest(LOGICAL,38)@0
xNotZero_uid39_fpCompareTest_q <= not (excZ_x_uid11_fpCompareTest_q);
-- oneNonZero_uid62_fpCompareTest(LOGICAL,61)@0
oneNonZero_uid62_fpCompareTest_q <= xNotZero_uid39_fpCompareTest_q or yNotZero_uid40_fpCompareTest_q;
-- two_uid54_fpCompareTest(CONSTANT,53)
two_uid54_fpCompareTest_q <= "10";
-- signY_uid53_fpCompareTest(BITSELECT,52)@0
signY_uid53_fpCompareTest_b <= STD_LOGIC_VECTOR(b(31 downto 31));
-- signX_uid52_fpCompareTest(BITSELECT,51)@0
signX_uid52_fpCompareTest_b <= STD_LOGIC_VECTOR(a(31 downto 31));
-- concSYSX_uid55_fpCompareTest(BITJOIN,54)@0
concSYSX_uid55_fpCompareTest_q <= signY_uid53_fpCompareTest_b & signX_uid52_fpCompareTest_b;
-- sxGTsy_uid56_fpCompareTest(LOGICAL,55)@0
sxGTsy_uid56_fpCompareTest_q <= "1" WHEN concSYSX_uid55_fpCompareTest_q = two_uid54_fpCompareTest_q ELSE "0";
-- rc2_uid63_fpCompareTest(LOGICAL,62)@0
rc2_uid63_fpCompareTest_q <= sxGTsy_uid56_fpCompareTest_q and oneNonZero_uid62_fpCompareTest_q;
-- frac_y_uid24_fpCompareTest(BITSELECT,23)@0
frac_y_uid24_fpCompareTest_b <= b(22 downto 0);
-- fracYPS_uid42_fpCompareTest(LOGICAL,41)@0
fracYPS_uid42_fpCompareTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((22 downto 1 => yNotZero_uid40_fpCompareTest_q(0)) & yNotZero_uid40_fpCompareTest_q));
fracYPS_uid42_fpCompareTest_q <= frac_y_uid24_fpCompareTest_b and fracYPS_uid42_fpCompareTest_b;
-- expFracY_uid45_fpCompareTest(BITJOIN,44)@0
expFracY_uid45_fpCompareTest_q <= exp_y_uid23_fpCompareTest_b & fracYPS_uid42_fpCompareTest_q;
-- frac_x_uid10_fpCompareTest(BITSELECT,9)@0
frac_x_uid10_fpCompareTest_b <= a(22 downto 0);
-- fracXPS_uid41_fpCompareTest(LOGICAL,40)@0
fracXPS_uid41_fpCompareTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((22 downto 1 => xNotZero_uid39_fpCompareTest_q(0)) & xNotZero_uid39_fpCompareTest_q));
fracXPS_uid41_fpCompareTest_q <= frac_x_uid10_fpCompareTest_b and fracXPS_uid41_fpCompareTest_b;
-- expFracX_uid43_fpCompareTest(BITJOIN,42)@0
expFracX_uid43_fpCompareTest_q <= exp_x_uid9_fpCompareTest_b & fracXPS_uid41_fpCompareTest_q;
-- efxLTefy_uid48_fpCompareTest(COMPARE,47)@0
efxLTefy_uid48_fpCompareTest_a <= STD_LOGIC_VECTOR("00" & expFracX_uid43_fpCompareTest_q);
efxLTefy_uid48_fpCompareTest_b <= STD_LOGIC_VECTOR("00" & expFracY_uid45_fpCompareTest_q);
efxLTefy_uid48_fpCompareTest_o <= STD_LOGIC_VECTOR(UNSIGNED(efxLTefy_uid48_fpCompareTest_a) - UNSIGNED(efxLTefy_uid48_fpCompareTest_b));
efxLTefy_uid48_fpCompareTest_c(0) <= efxLTefy_uid48_fpCompareTest_o(32);
-- efxGTefy_uid47_fpCompareTest(COMPARE,46)@0
efxGTefy_uid47_fpCompareTest_a <= STD_LOGIC_VECTOR("00" & expFracY_uid45_fpCompareTest_q);
efxGTefy_uid47_fpCompareTest_b <= STD_LOGIC_VECTOR("00" & expFracX_uid43_fpCompareTest_q);
efxGTefy_uid47_fpCompareTest_o <= STD_LOGIC_VECTOR(UNSIGNED(efxGTefy_uid47_fpCompareTest_a) - UNSIGNED(efxGTefy_uid47_fpCompareTest_b));
efxGTefy_uid47_fpCompareTest_c(0) <= efxGTefy_uid47_fpCompareTest_o(32);
-- expFracCompMux_uid59_fpCompareTest(MUX,58)@0
expFracCompMux_uid59_fpCompareTest_s <= signX_uid52_fpCompareTest_b;
expFracCompMux_uid59_fpCompareTest_combproc: PROCESS (expFracCompMux_uid59_fpCompareTest_s, efxGTefy_uid47_fpCompareTest_c, efxLTefy_uid48_fpCompareTest_c)
BEGIN
CASE (expFracCompMux_uid59_fpCompareTest_s) IS
WHEN "0" => expFracCompMux_uid59_fpCompareTest_q <= efxGTefy_uid47_fpCompareTest_c;
WHEN "1" => expFracCompMux_uid59_fpCompareTest_q <= efxLTefy_uid48_fpCompareTest_c;
WHEN OTHERS => expFracCompMux_uid59_fpCompareTest_q <= (others => '0');
END CASE;
END PROCESS;
-- xorSigns_uid57_fpCompareTest(LOGICAL,56)@0
xorSigns_uid57_fpCompareTest_q <= signX_uid52_fpCompareTest_b xor signY_uid53_fpCompareTest_b;
-- sxEQsy_uid58_fpCompareTest(LOGICAL,57)@0
sxEQsy_uid58_fpCompareTest_q <= not (xorSigns_uid57_fpCompareTest_q);
-- sxEQsyExpFracCompMux_uid64_fpCompareTest(LOGICAL,63)@0
sxEQsyExpFracCompMux_uid64_fpCompareTest_q <= sxEQsy_uid58_fpCompareTest_q and expFracCompMux_uid59_fpCompareTest_q;
-- r_uid65_fpCompareTest(LOGICAL,64)@0
r_uid65_fpCompareTest_q <= sxEQsyExpFracCompMux_uid64_fpCompareTest_q or rc2_uid63_fpCompareTest_q;
-- cstZeroWF_uid7_fpCompareTest(CONSTANT,6)
cstZeroWF_uid7_fpCompareTest_q <= "00000000000000000000000";
-- fracXIsZero_uid27_fpCompareTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCompareTest_q <= "1" WHEN cstZeroWF_uid7_fpCompareTest_q = frac_y_uid24_fpCompareTest_b ELSE "0";
-- fracXIsNotZero_uid28_fpCompareTest(LOGICAL,27)@0
fracXIsNotZero_uid28_fpCompareTest_q <= not (fracXIsZero_uid27_fpCompareTest_q);
-- cstAllOWE_uid6_fpCompareTest(CONSTANT,5)
cstAllOWE_uid6_fpCompareTest_q <= "11111111";
-- expXIsMax_uid26_fpCompareTest(LOGICAL,25)@0
expXIsMax_uid26_fpCompareTest_q <= "1" WHEN exp_y_uid23_fpCompareTest_b = cstAllOWE_uid6_fpCompareTest_q ELSE "0";
-- excN_y_uid30_fpCompareTest(LOGICAL,29)@0
excN_y_uid30_fpCompareTest_q <= expXIsMax_uid26_fpCompareTest_q and fracXIsNotZero_uid28_fpCompareTest_q;
-- fracXIsZero_uid13_fpCompareTest(LOGICAL,12)@0
fracXIsZero_uid13_fpCompareTest_q <= "1" WHEN cstZeroWF_uid7_fpCompareTest_q = frac_x_uid10_fpCompareTest_b ELSE "0";
-- fracXIsNotZero_uid14_fpCompareTest(LOGICAL,13)@0
fracXIsNotZero_uid14_fpCompareTest_q <= not (fracXIsZero_uid13_fpCompareTest_q);
-- expXIsMax_uid12_fpCompareTest(LOGICAL,11)@0
expXIsMax_uid12_fpCompareTest_q <= "1" WHEN exp_x_uid9_fpCompareTest_b = cstAllOWE_uid6_fpCompareTest_q ELSE "0";
-- excN_x_uid16_fpCompareTest(LOGICAL,15)@0
excN_x_uid16_fpCompareTest_q <= expXIsMax_uid12_fpCompareTest_q and fracXIsNotZero_uid14_fpCompareTest_q;
-- oneIsNaN_uid34_fpCompareTest(LOGICAL,33)@0
oneIsNaN_uid34_fpCompareTest_q <= excN_x_uid16_fpCompareTest_q or excN_y_uid30_fpCompareTest_q;
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- rPostExc_uid66_fpCompareTest(MUX,65)@0
rPostExc_uid66_fpCompareTest_s <= oneIsNaN_uid34_fpCompareTest_q;
rPostExc_uid66_fpCompareTest_combproc: PROCESS (rPostExc_uid66_fpCompareTest_s, r_uid65_fpCompareTest_q, GND_q)
BEGIN
CASE (rPostExc_uid66_fpCompareTest_s) IS
WHEN "0" => rPostExc_uid66_fpCompareTest_q <= r_uid65_fpCompareTest_q;
WHEN "1" => rPostExc_uid66_fpCompareTest_q <= GND_q;
WHEN OTHERS => rPostExc_uid66_fpCompareTest_q <= (others => '0');
END CASE;
END PROCESS;
-- xOut(GPOUT,4)@0
q <= rPostExc_uid66_fpCompareTest_q;
END normal;
|
mit
|
63fe05f947124cda680ebc7b1e3cde5d
| 0.720105 | 3.568117 | false | true | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/ExampleA.vhd
| 1 | 2,956 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY OnceUnit IS
PORT(
a : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF OnceUnit IS
BEGIN
a <= '1';
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ParamsUniqUnit IS
GENERIC(
A : INTEGER := 0;
B : INTEGER := 1
);
PORT(
a_0 : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF ParamsUniqUnit IS
BEGIN
a_0 <= '1';
ASSERT A = 0 REPORT "Generated only for this value" SEVERITY failure;
ASSERT B = 1 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ParamsUniqUnit_0 IS
GENERIC(
A : INTEGER := 0;
B : INTEGER := 12
);
PORT(
a_0 : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF ParamsUniqUnit_0 IS
BEGIN
a_0 <= '1';
ASSERT A = 0 REPORT "Generated only for this value" SEVERITY failure;
ASSERT B = 12 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ExampleA IS
PORT(
a : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF ExampleA IS
COMPONENT ExcludedUnit IS
PORT(
a : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT OnceUnit IS
PORT(
a : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT ParamsUniqUnit IS
GENERIC(
A : INTEGER := 0;
B : INTEGER := 1
);
PORT(
a_0 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT ParamsUniqUnit_0 IS
GENERIC(
A : INTEGER := 0;
B : INTEGER := 12
);
PORT(
a_0 : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL sig_u0_a : STD_LOGIC;
SIGNAL sig_u1_a : STD_LOGIC;
SIGNAL sig_u2_a : STD_LOGIC;
SIGNAL sig_u3_a : STD_LOGIC;
SIGNAL sig_u4_a : STD_LOGIC;
SIGNAL sig_u5_a : STD_LOGIC;
SIGNAL sig_u6_a : STD_LOGIC;
SIGNAL sig_u7_a : STD_LOGIC;
BEGIN
u0_inst: ExcludedUnit PORT MAP(
a => sig_u0_a
);
u1_inst: ExcludedUnit PORT MAP(
a => sig_u1_a
);
u2_inst: OnceUnit PORT MAP(
a => sig_u2_a
);
u3_inst: OnceUnit PORT MAP(
a => sig_u3_a
);
u4_inst: OnceUnit PORT MAP(
a => sig_u4_a
);
u5_inst: ParamsUniqUnit GENERIC MAP(
A => 0,
B => 1
) PORT MAP(
a_0 => sig_u5_a
);
u6_inst: ParamsUniqUnit GENERIC MAP(
A => 0,
B => 1
) PORT MAP(
a_0 => sig_u6_a
);
u7_inst: ParamsUniqUnit_0 GENERIC MAP(
A => 0,
B => 12
) PORT MAP(
a_0 => sig_u7_a
);
a <= sig_u0_a & sig_u1_a & sig_u2_a & sig_u3_a & sig_u4_a & sig_u5_a & sig_u6_a;
END ARCHITECTURE;
|
mit
|
7ea259ce8acfd90dddb92e03c5a0b676
| 0.554804 | 3.359091 | false | false | false | false |
elahejalalpour/CoDesign
|
Phase-1/hem/hem.vhd
| 1 | 882 |
--------------------------------------------------------------------------------
-- Author: Elahe Jalalpour ([email protected])
--
-- Create Date: 28-08-2015
-- Module Name: hem.vhd
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity hem is
port(a, b : in std_logic_vector(3 downto 0);
r : out std_logic_vector(7 downto 0));
end hem;
architecture rtl of hem is
component mul
port(a, b : in std_logic_vector(1 downto 0);
cout : out std_logic_vector(3 downto 0));
end component;
signal in1, in2, in3, in4 : std_logic_vector(1 downto 0);
begin
in1(0) <= a(0);
in1(1) <= b(2);
in2(0) <= a(2);
in2(1) <= b(0);
in3(0) <= a(1);
in3(1) <= b(3);
in4(0) <= a(3);
in4(1) <= b(1);
M0: mul port map (in1, in2, r(3 downto 0));
M1: mul port map (in3, in4, r(7 downto 4));
end rtl;
|
gpl-2.0
|
37b4715f0d99b7b43d457d530744e42b
| 0.495465 | 2.76489 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_bpm_swap/wb_bpm_swap.vhd
| 1 | 9,418 |
------------------------------------------------------------------------------
-- Title : Wishbone BPM SWAP flat interface
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone interface with BPM Swap core. In flat style.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-04-12 1.0 jose.berkenbrock Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- BPM cores
use work.bpm_cores_pkg.all;
-- Register Bank
use work.bpm_swap_wbgen2_pkg.all;
entity wb_bpm_swap is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16;
g_ch_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
-- Input data from ADCs
cha_i : in std_logic_vector(g_ch_width-1 downto 0);
chb_i : in std_logic_vector(g_ch_width-1 downto 0);
chc_i : in std_logic_vector(g_ch_width-1 downto 0);
chd_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
-- Output data to BPM DSP chain
cha_o : out std_logic_vector(g_ch_width-1 downto 0);
chb_o : out std_logic_vector(g_ch_width-1 downto 0);
chc_o : out std_logic_vector(g_ch_width-1 downto 0);
chd_o : out std_logic_vector(g_ch_width-1 downto 0);
ch_tag_o : out std_logic_vector(0 downto 0);
ch_valid_o : out std_logic;
-- RFFE swap clock (or switchwing clock)
rffe_swclk_o : out std_logic;
-- RFFE swap clock synchronization trigger
sync_trig_i : in std_logic
);
end wb_bpm_swap;
architecture rtl of wb_bpm_swap is
constant c_periph_addr_size : natural := 1+2;
signal fs_rst_n : std_logic;
-----------------------------
-- Wishbone Register Interface signals
-----------------------------
-- wb_bpm_swap reg structure
signal regs_in : t_bpm_swap_in_registers;
signal regs_out : t_bpm_swap_out_registers;
-----------------------------
-- Wishbone slave adapter signals/structures
-----------------------------
signal wb_slv_adp_out : t_wishbone_master_out;
signal wb_slv_adp_in : t_wishbone_master_in;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
signal deswap_delay : std_logic_vector(g_delay_vec_width-1 downto 0);
component wb_bpm_swap_regs
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
regs_i : in t_bpm_swap_in_registers;
regs_o : out t_bpm_swap_out_registers
);
end component;
begin
-----------------------------
-- Slave adapter for Wishbone Register Interface
-----------------------------
cmp_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity
)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_slv_adp_in,
master_o => wb_slv_adp_out,
sl_adr_i => resized_addr,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_rty_o => open,
sl_err_o => open,
sl_stall_o => wb_stall_o
);
-- See wb_bpm_swap_port.vhd for register bank addresses.
resized_addr(c_periph_addr_size-1 downto 0) <= wb_adr_i(c_periph_addr_size-1 downto 0); --cbar_master_out(0).adr(c_periph_addr_size-1 downto 0);
resized_addr(c_wishbone_address_width-1 downto c_periph_addr_size) <= (others => '0');
-- Register Bank / Wishbone Interface
cmp_wb_bpm_swap_regs : wb_bpm_swap_regs
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_slv_adp_out.adr(0 downto 0),
wb_dat_i => wb_slv_adp_out.dat,
wb_dat_o => wb_slv_adp_in.dat,
wb_cyc_i => wb_slv_adp_out.cyc,
wb_sel_i => wb_slv_adp_out.sel,
wb_stb_i => wb_slv_adp_out.stb,
wb_we_i => wb_slv_adp_out.we,
wb_ack_o => wb_slv_adp_in.ack,
wb_stall_o => wb_slv_adp_in.stall,
fs_clk_i => fs_clk_i,
regs_i => regs_in,
regs_o => regs_out
);
-- Registers assignment
regs_in.ctrl_reserved_i <= (others => '0');
regs_in.dly_reserved_i <= (others => '0');
-- Unused wishbone signals
wb_slv_adp_in.err <= '0';
wb_slv_adp_in.rty <= '0';
cmp_bpm_swap : bpm_swap
generic map (
g_delay_vec_width => g_delay_vec_width,
g_swap_div_freq_vec_width => g_swap_div_freq_vec_width,
g_ch_width => g_ch_width
)
port map (
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
cha_i => cha_i,
chb_i => chb_i,
chc_i => chc_i,
chd_i => chd_i,
ch_valid_i => ch_valid_i,
cha_o => cha_o,
chb_o => chb_o,
chc_o => chc_o,
chd_o => chd_o,
ch_tag_o => ch_tag_o,
ch_valid_o => ch_valid_o,
rffe_swclk_o => rffe_swclk_o,
sync_trig_i => sync_trig_i,
swap_mode_i => regs_out.ctrl_mode_o,
swap_div_f_i => regs_out.ctrl_swap_div_f_o,
deswap_delay_i => deswap_delay
);
deswap_delay <= regs_out.dly_deswap_o(g_delay_vec_width-1 downto 0);
end rtl;
|
lgpl-3.0
|
e6094e04017c2f91c066222f9da67c1a
| 0.404544 | 3.880511 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd
| 1 | 117,352 |
------------------------------------------------------------------------------
-- Title : Top DSP design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-01
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC130M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-09-01 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Custom common cores
use work.ifc_common_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- DSP definitions
use work.dsp_cores_pkg.all;
-- BPM definitions
use work.bpm_cores_pkg.all;
-- Genrams
use work.genram_pkg.all;
-- Data Acquisition core
use work.acq_core_pkg.all;
-- PCIe Core
use work.bpm_pcie_ml605_pkg.all;
-- PCIe Core Constants
use work.bpm_pcie_ml605_const_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_dsp is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
rs232_txd_o : out std_logic;
rs232_rxd_i : in std_logic;
--uart_txd_o : out std_logic;
--uart_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------
-- FMC130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o : out std_logic;
fmc_adc_shdn_o : out std_logic;
fmc_adc_dith_o : out std_logic;
fmc_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc_adc0_clk_i : in std_logic;
fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc0_of_i : in std_logic; -- Unused
-- ADC1 LTC2208
fmc_adc1_clk_i : in std_logic;
fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc1_of_i : in std_logic; -- Unused
-- ADC2 LTC2208
fmc_adc2_clk_i : in std_logic;
fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc2_of_i : in std_logic; -- Unused
-- ADC3 LTC2208
fmc_adc3_clk_i : in std_logic;
fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc3_of_i : in std_logic; -- Unused
-- FMC General Status
fmc_prsnt_i : in std_logic;
fmc_pg_m2c_i : in std_logic;
--fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o : out std_logic;
fmc_trig_term_o : out std_logic;
fmc_trig_val_p_b : inout std_logic;
fmc_trig_val_n_b : inout std_logic;
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic;
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic;
fmc_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-- EEPROM
eeprom_scl_pad_b : inout std_logic;
eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor (LM75AIMM)
lm75_scl_pad_b : inout std_logic;
lm75_sda_pad_b : inout std_logic;
fmc_lm75_temp_alarm_i : in std_logic;
-- FMC LEDs
fmc_led1_o : out std_logic;
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------------------
-- Position Calc signals
-----------------------------------------
-- Uncross signals
clk_swap_o : out std_logic;
clk_swap2x_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
-----------------------------------------
-- General board status
-----------------------------------------
fmc_mmcm_lock_led_o : out std_logic;
fmc_pll_status_led_o : out std_logic;
-----------------------------------------
-- PCIe pins
-----------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_ddr_dq_width-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_ddr_row_width-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_ddr_bank_width-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_ddr_ck_width-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_ddr_ck_width-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_ddr_cke_width-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_ddr_dm_width-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_ddr_odt_width-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_pcie_lanes - 1 downto 0);
-- PCI clock and reset signals
pcie_rst_n_i : in std_logic;
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
--buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_dsp;
architecture rtl of dbe_bpm_dsp is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 11;
-- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC,
--Etherbone, FMC516, Peripherals
-- Number of masters
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, RS232-Syscon
constant c_masters : natural := 8; -- RS232-Syscon, PCIe
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
--constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
constant c_dpram_size : natural := 90112/4; -- in 32-bit words (90KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
--constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
constant c_dpram_ethbuf_size : natural := 16384/4; -- in 32-bit words (16KB)
constant c_acq_fifo_size : natural := 256;
constant c_acq_addr_width : natural := c_ddr_addr_width;
constant c_acq_ddr_addr_res_width : natural := 32;
constant c_acq_ddr_addr_diff : natural := c_acq_ddr_addr_res_width-c_ddr_addr_width;
constant c_acq_adc_id : natural := 0;
constant c_acq_tbt_amp_id : natural := 1;
constant c_acq_tbt_pos_id : natural := 2;
constant c_acq_fofb_amp_id : natural := 3;
constant c_acq_fofb_pos_id : natural := 4;
constant c_acq_monit_amp_id : natural := 5;
constant c_acq_monit_pos_id : natural := 6;
constant c_acq_monit_1_pos_id : natural := 7;
constant c_acq_pos_ddr3_width : natural := 32;
constant c_acq_num_channels : natural := 8; -- ADC + TBT AMP + TBT POS +
-- FOFB AMP + FOFB POS + MONIT AMP + MONIT POS + MONIT_1 POS
constant c_acq_channels : t_acq_chan_param_array(c_acq_num_channels-1 downto 0) :=
( c_acq_adc_id => (width => to_unsigned(64, c_acq_chan_max_w_log2)),
c_acq_tbt_amp_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_tbt_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_fofb_amp_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_fofb_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_monit_amp_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_monit_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_monit_1_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2))
);
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- TICs counter period. 100MHz clock -> msec granularity
constant c_tics_cntr_period : natural := 100000;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_adc_ref_clk : natural := 1;
-- Number of top level clocks
constant c_num_tlvl_clks : natural := 2; -- CLK_SYS and CLK_200 MHz
constant c_clk_sys_id : natural := 0; -- CLK_SYS and CLK_200 MHz
constant c_clk_200mhz_id : natural := 1; -- CLK_SYS and CLK_200 MHz
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- FMC130m_4ch layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
--constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- FMC130m_4ch
constant c_fmc130m_4ch_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- Position CAlC. layout. Regs, SWAP
constant c_pos_calc_core_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000600");
-- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter
constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400");
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 90KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00100000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"00200000"), -- 64KB RAM
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"00304000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"00305000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"00306000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"00307000"), -- Etherbone control port
7 => f_sdb_embed_bridge(c_pos_calc_core_bridge_sdb,
x"00308000"), -- Position Calc Core control port
8 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"00310000"), -- FMC130m_4ch control port
9 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"00320000"), -- General peripherals control port
10 => f_sdb_embed_device(c_xwb_acq_core_sdb, x"00330000") -- Data Acquisition control port
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"00300000";
-- FMC ADC data constants
constant c_adc_data_ch0_lsb : natural := 0;
constant c_adc_data_ch0_msb : natural := c_num_adc_bits-1 + c_adc_data_ch0_lsb;
constant c_adc_data_ch1_lsb : natural := c_adc_data_ch0_msb + 1;
constant c_adc_data_ch1_msb : natural := c_num_adc_bits-1 + c_adc_data_ch1_lsb;
constant c_adc_data_ch2_lsb : natural := c_adc_data_ch1_msb + 1;
constant c_adc_data_ch2_msb : natural := c_num_adc_bits-1 + c_adc_data_ch2_lsb;
constant c_adc_data_ch3_lsb : natural := c_adc_data_ch2_msb + 1;
constant c_adc_data_ch3_msb : natural := c_num_adc_bits-1 + c_adc_data_ch3_lsb;
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- PCIe signals
signal wb_ma_pcie_ack_in : std_logic;
signal wb_ma_pcie_dat_in : std_logic_vector(63 downto 0);
signal wb_ma_pcie_addr_out : std_logic_vector(28 downto 0);
signal wb_ma_pcie_dat_out : std_logic_vector(63 downto 0);
signal wb_ma_pcie_we_out : std_logic;
signal wb_ma_pcie_stb_out : std_logic;
signal wb_ma_pcie_sel_out : std_logic;
signal wb_ma_pcie_cyc_out : std_logic;
signal wb_ma_pcie_rst : std_logic;
signal wb_ma_pcie_rstn : std_logic;
signal wb_ma_sladp_pcie_ack_in : std_logic;
signal wb_ma_sladp_pcie_dat_in : std_logic_vector(31 downto 0);
signal wb_ma_sladp_pcie_addr_out : std_logic_vector(31 downto 0);
signal wb_ma_sladp_pcie_dat_out : std_logic_vector(31 downto 0);
signal wb_ma_sladp_pcie_we_out : std_logic;
signal wb_ma_sladp_pcie_stb_out : std_logic;
signal wb_ma_sladp_pcie_sel_out : std_logic_vector(3 downto 0);
signal wb_ma_sladp_pcie_cyc_out : std_logic;
-- PCIe Debug signals
signal dbg_app_addr : std_logic_vector(31 downto 0);
signal dbg_app_cmd : std_logic_vector(2 downto 0);
signal dbg_app_en : std_logic;
signal dbg_app_wdf_data : std_logic_vector(c_ddr_payload_width-1 downto 0);
signal dbg_app_wdf_end : std_logic;
signal dbg_app_wdf_wren : std_logic;
signal dbg_app_wdf_mask : std_logic_vector(c_ddr_payload_width/8-1 downto 0);
signal dbg_app_rd_data : std_logic_vector(c_ddr_payload_width-1 downto 0);
signal dbg_app_rd_data_end : std_logic;
signal dbg_app_rd_data_valid : std_logic;
signal dbg_app_rdy : std_logic;
signal dbg_app_wdf_rdy : std_logic;
signal dbg_ddr_ui_clk : std_logic;
signal dbg_ddr_ui_reset : std_logic;
signal dbg_arb_req : std_logic_vector(1 downto 0);
signal dbg_arb_gnt : std_logic_vector(1 downto 0);
-- To/From Acquisition Core
signal acq_chan_array : t_acq_chan_array(c_acq_num_channels-1 downto 0);
signal bpm_acq_dpram_dout : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0);
signal bpm_acq_dpram_valid : std_logic;
signal bpm_acq_ext_dout : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0);
signal bpm_acq_ext_valid : std_logic;
signal bpm_acq_ext_addr : std_logic_vector(c_acq_addr_width-1 downto 0);
signal bpm_acq_ext_sof : std_logic;
signal bpm_acq_ext_eof : std_logic;
signal bpm_acq_ext_dreq : std_logic;
signal bpm_acq_ext_stall : std_logic;
signal memc_ui_clk : std_logic;
signal memc_ui_rst : std_logic;
signal memc_ui_rstn : std_logic;
signal memc_cmd_rdy : std_logic;
signal memc_cmd_en : std_logic;
signal memc_cmd_instr : std_logic_vector(2 downto 0);
signal memc_cmd_addr_resized : std_logic_vector(c_acq_ddr_addr_res_width-1 downto 0);
signal memc_cmd_addr : std_logic_vector(c_ddr_addr_width-1 downto 0);
signal memc_wr_en : std_logic;
signal memc_wr_end : std_logic;
signal memc_wr_mask : std_logic_vector(c_ddr_payload_width/8-1 downto 0);
signal memc_wr_data : std_logic_vector(c_ddr_payload_width-1 downto 0);
signal memc_wr_rdy : std_logic;
signal memc_rd_data : std_logic_vector(c_ddr_payload_width-1 downto 0);
signal memc_rd_valid : std_logic;
signal dbg_ddr_rb_data : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0);
signal dbg_ddr_rb_addr : std_logic_vector(c_acq_addr_width-1 downto 0);
signal dbg_ddr_rb_valid : std_logic;
-- memory arbiter interface
signal memarb_acc_req : std_logic;
signal memarb_acc_gnt : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal clk_200mhz_rst : std_logic;
signal clk_200mhz_rstn : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
-- "c_num_tlvl_clks" clocks
signal reset_clks : std_logic_vector(c_num_tlvl_clks-1 downto 0);
signal reset_rstn : std_logic_vector(c_num_tlvl_clks-1 downto 0);
signal rs232_rstn : std_logic;
signal fs_rstn : std_logic;
signal fs_rst2xn : std_logic;
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- ADC clock
signal fs_clk : std_logic;
signal fs_clk2x : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
signal sys_clk_gen_bufg : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- FMC130m_4ch Signals
signal wbs_fmc130m_4ch_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc130m_4ch_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc_mmcm_lock_int : std_logic;
signal fmc_pll_status_int : std_logic;
signal fmc_led1_int : std_logic;
signal fmc_led2_int : std_logic;
signal fmc_led3_int : std_logic;
signal fmc_130m_4ch_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_data : std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
signal fmc_130m_4ch_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_data_ch0 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ch1 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ch2 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ch3 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal fmc_debug : std_logic;
signal reset_adc_counter : unsigned(6 downto 0) := (others => '0');
signal fmc_130m_4ch_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_rst2x_n : std_logic_vector(c_num_adc_channels-1 downto 0);
-- fmc130m_4ch Debug
signal fmc130m_4ch_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
-- Uncross signals
signal flag1_int : std_logic;
signal flag2_int : std_logic;
-- DSP signals
signal dsp_kx : std_logic_vector(24 downto 0);
signal dsp_ky : std_logic_vector(24 downto 0);
signal dsp_ksum : std_logic_vector(24 downto 0);
signal dsp_kx_in : std_logic_vector(24 downto 0);
signal dsp_ky_in : std_logic_vector(24 downto 0);
signal dsp_ksum_in : std_logic_vector(24 downto 0);
signal dsp_del_sig_div_thres_sel : std_logic_vector(1 downto 0);
signal dsp_kx_sel : std_logic_vector(1 downto 0);
signal dsp_ky_sel : std_logic_vector(1 downto 0);
signal dsp_ksum_sel : std_logic_vector(1 downto 0);
signal dsp_del_sig_div_thres : std_logic_vector(25 downto 0);
signal dsp_del_sig_div_thres_in : std_logic_vector(25 downto 0);
signal dsp_dds_config_valid_ch0 : std_logic;
signal dsp_dds_config_valid_ch1 : std_logic;
signal dsp_dds_config_valid_ch2 : std_logic;
signal dsp_dds_config_valid_ch3 : std_logic;
signal dsp_dds_pinc_ch0 : std_logic_vector(29 downto 0);
signal dsp_dds_pinc_ch1 : std_logic_vector(29 downto 0);
signal dsp_dds_pinc_ch2 : std_logic_vector(29 downto 0);
signal dsp_dds_pinc_ch3 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch0 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch1 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch2 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch3 : std_logic_vector(29 downto 0);
signal dsp_adc_ch0_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_bpf_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_bpf_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_bpf_valid : std_logic;
signal dsp_mix_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_valid : std_logic;
signal dsp_poly35_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_poly35_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_poly35_valid : std_logic;
signal dsp_cic_fofb_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_valid : std_logic;
signal dsp_tbt_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_valid : std_logic;
signal dsp_tbt_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_valid : std_logic;
signal dsp_fofb_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_valid : std_logic;
signal dsp_fofb_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_valid : std_logic;
signal dsp_monit_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_valid : std_logic;
signal dsp_pos_x_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_y_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_q_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_sum_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_tbt_valid : std_logic;
signal dsp_pos_x_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_y_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_q_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_sum_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_fofb_valid : std_logic;
signal dsp_pos_x_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_y_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_q_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_sum_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_monit_valid : std_logic;
signal dsp_pos_x_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_y_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_q_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_sum_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_pos_monit_1_valid : std_logic;
signal dsp_clk_ce_1 : std_logic;
signal dsp_clk_ce_2 : std_logic;
signal dsp_clk_ce_35 : std_logic;
signal dsp_clk_ce_70 : std_logic;
signal dsp_clk_ce_1390000 : std_logic;
signal dsp_clk_ce_1112 : std_logic;
signal dsp_clk_ce_2224 : std_logic;
signal dsp_clk_ce_11120000 : std_logic;
signal dsp_clk_ce_111200000 : std_logic;
signal dsp_clk_ce_22240000 : std_logic;
signal dsp_clk_ce_222400000 : std_logic;
signal dsp_clk_ce_5000 : std_logic;
signal dsp_clk_ce_556 : std_logic;
signal dsp_clk_ce_2780000 : std_logic;
signal dsp_clk_ce_5560000 : std_logic;
signal dbg_cur_address : std_logic_vector(31 downto 0);
signal dbg_adc_ch0_cond : std_logic_vector(15 downto 0);
signal dbg_adc_ch1_cond : std_logic_vector(15 downto 0);
signal dbg_adc_ch2_cond : std_logic_vector(15 downto 0);
signal dbg_adc_ch3_cond : std_logic_vector(15 downto 0);
-- DDS test
signal dds_data : std_logic_vector(2*c_num_adc_bits-1 downto 0); -- cosine + sine
signal dds_sine : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dds_cosine : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc0 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc1 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc2 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc3 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc0_full : std_logic_vector(25 downto 0);
signal synth_adc1_full : std_logic_vector(25 downto 0);
signal synth_adc2_full : std_logic_vector(25 downto 0);
signal synth_adc3_full : std_logic_vector(25 downto 0);
signal dds_sine_gain_ch0 : std_logic_vector(9 downto 0);
signal dds_sine_gain_ch1 : std_logic_vector(9 downto 0);
signal dds_sine_gain_ch2 : std_logic_vector(9 downto 0);
signal dds_sine_gain_ch3 : std_logic_vector(9 downto 0);
signal adc_synth_data_en : std_logic;
signal clk_rffe_swap : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
signal buttons_dummy : std_logic_vector(7 downto 0) := (others => '0');
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
---- Chipscope control signals
--signal CONTROL0 : std_logic_vector(35 downto 0);
--signal CONTROL1 : std_logic_vector(35 downto 0);
--signal CONTROL2 : std_logic_vector(35 downto 0);
--signal CONTROL3 : std_logic_vector(35 downto 0);
--signal CONTROL4 : std_logic_vector(35 downto 0);
--signal CONTROL5 : std_logic_vector(35 downto 0);
--signal CONTROL6 : std_logic_vector(35 downto 0);
--signal CONTROL7 : std_logic_vector(35 downto 0);
--signal CONTROL8 : std_logic_vector(35 downto 0);
--signal CONTROL9 : std_logic_vector(35 downto 0);
--signal CONTROL10 : std_logic_vector(35 downto 0);
--signal CONTROL11 : std_logic_vector(35 downto 0);
--signal CONTROL12 : std_logic_vector(35 downto 0);
---- Chipscope ILA 0 signals
--signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
--signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA0_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 1 signals
--signal TRIG_ILA1_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA1_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 2 signals
--signal TRIG_ILA2_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA2_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 3 signals
--signal TRIG_ILA3_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA3_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 4 signals
--signal TRIG_ILA4_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA4_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA4_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA4_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA4_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 5 signals
--signal TRIG_ILA5_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA5_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA5_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA5_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA5_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 6 signals
--signal TRIG_ILA6_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA6_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA6_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA6_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA6_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 7 signals
--signal TRIG_ILA7_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA7_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA7_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA7_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA7_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 8 signals
--signal TRIG_ILA8_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA8_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA8_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA8_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA8_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 9 signals
--signal TRIG_ILA9_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA9_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA9_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA9_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA9_4 : std_logic_vector(31 downto 0);
---- Chipscope ILA 10 signals
--signal TRIG_ILA10_0 : std_logic_vector(7 downto 0);
--signal TRIG_ILA10_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA10_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA10_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA10_4 : std_logic_vector(31 downto 0);
---- Chipscope VIO signals
--signal vio_out : std_logic_vector(255 downto 0);
--signal vio_out_dsp_config : std_logic_vector(255 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic;
sys_clk_bufg_o : out std_logic
);
end component;
-- Xilinx PLL
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
component multiplier_16x10_DSP
port (
clk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(9 downto 0);
p : out std_logic_vector(25 downto 0)
);
end component;
component dds_adc_input
port (
aclk : in std_logic;
m_axis_data_tvalid : out std_logic;
m_axis_data_tdata : out std_logic_vector(31 downto 0)
);
end component;
component chipscope_icon_13_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0);
CONTROL4 : inout std_logic_vector(35 downto 0);
CONTROL5 : inout std_logic_vector(35 downto 0);
CONTROL6 : inout std_logic_vector(35 downto 0);
CONTROL7 : inout std_logic_vector(35 downto 0);
CONTROL8 : inout std_logic_vector(35 downto 0);
CONTROL9 : inout std_logic_vector(35 downto 0);
CONTROL10 : inout std_logic_vector(35 downto 0);
CONTROL11 : inout std_logic_vector(35 downto 0);
CONTROL12 : inout std_logic_vector(35 downto 0)
);
end component;
component chipscope_ila
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(31 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila_1024_5_port
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(31 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_8192_5_port
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(31 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_1024
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(7 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_4096
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(7 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_65536
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(7 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_131072
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(7 downto 0);
trig1 : in std_logic_vector(15 downto 0);
trig2 : in std_logic_vector(15 downto 0);
trig3 : in std_logic_vector(15 downto 0);
trig4 : in std_logic_vector(15 downto 0));
end component;
component chipscope_vio_256 is
port (
control : inout std_logic_vector(35 downto 0);
async_out : out std_logic_vector(255 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen,
sys_clk_bufg_o => sys_clk_gen_bufg
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen_bufg,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => c_num_tlvl_clks -- CLK_SYS & CLK_200
)
port map(
--free_clk_i => sys_clk_gen,
free_clk_i => sys_clk_gen_bufg,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(c_clk_sys_id) <= clk_sys;
reset_clks(c_clk_200mhz_id) <= clk_200mhz;
--clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_sys_rstn <= reset_rstn(c_clk_sys_id) and rst_button_sys_n and
rs232_rstn;-- and wb_ma_pcie_rstn;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
clk_200mhz_rstn <= reset_rstn(c_clk_200mhz_id);
clk_200mhz_rst <= not(reset_rstn(c_clk_200mhz_id));
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
--cmp_lm32 : xwb_lm32
--generic map(
-- g_profile => "medium_icache_debug"
--) -- Including JTAG and I-cache (no divide)
--port map(
-- clk_sys_i => clk_sys,
-- rst_n_i => lm32_rstn,
-- irq_i => lm32_interrupt,
-- dwb_o => cbar_slave_i(0), -- Data bus
-- dwb_i => cbar_slave_o(0),
-- iwb_o => cbar_slave_i(1), -- Instruction bus
-- iwb_i => cbar_slave_o(1)
--);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
--lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
-- 4 => irq_tx_done, others => '0');
----------------------------------
-- PCIe Core --
----------------------------------
cmp_xwb_bpm_pcie_ml605 : xwb_bpm_pcie_ml605
generic map (
g_ma_interface_mode => PIPELINED,
g_ma_address_granularity => BYTE,
g_sim_bypass_init_cal => "OFF"
)
port map (
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- Necessity signals
ddr_clk_p_i => clk_200mhz, --200 MHz DDR core clock (connect through BUFG or PLL)
ddr_clk_n_i => '0', --200 MHz DDR core clock (connect through BUFG or PLL)
pcie_clk_p_i => pcie_clk_p_i, --100 MHz PCIe Clock (connect directly to input pin)
pcie_clk_n_i => pcie_clk_n_i, --100 MHz PCIe Clock
pcie_rst_n_i => pcie_rst_n_i, -- PCIe core reset
-- DDR memory controller interface --
ddr_core_rst_i => clk_sys_rst,
memc_ui_clk_o => memc_ui_clk,
memc_ui_rst_o => memc_ui_rst,
memc_cmd_rdy_o => memc_cmd_rdy,
memc_cmd_en_i => memc_cmd_en,
memc_cmd_instr_i => memc_cmd_instr,
memc_cmd_addr_i => memc_cmd_addr_resized,
memc_wr_en_i => memc_wr_en,
memc_wr_end_i => memc_wr_end,
memc_wr_mask_i => memc_wr_mask,
memc_wr_data_i => memc_wr_data,
memc_wr_rdy_o => memc_wr_rdy,
memc_rd_data_o => memc_rd_data,
memc_rd_valid_o => memc_rd_valid,
---- memory arbiter interface
memarb_acc_req_i => memarb_acc_req,
memarb_acc_gnt_o => memarb_acc_gnt,
-- Wishbone interface --
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
wb_ma_i => cbar_slave_o(0),
wb_ma_o => cbar_slave_i(0),
-- Additional exported signals for instantiation
wb_ma_pcie_rst_o => wb_ma_pcie_rst,
-- Debug signals
dbg_app_addr_o => dbg_app_addr,
dbg_app_cmd_o => dbg_app_cmd,
dbg_app_en_o => dbg_app_en,
dbg_app_wdf_data_o => dbg_app_wdf_data,
dbg_app_wdf_end_o => dbg_app_wdf_end,
dbg_app_wdf_wren_o => dbg_app_wdf_wren,
dbg_app_wdf_mask_o => dbg_app_wdf_mask,
dbg_app_rd_data_o => dbg_app_rd_data,
dbg_app_rd_data_end_o => dbg_app_rd_data_end,
dbg_app_rd_data_valid_o => dbg_app_rd_data_valid,
dbg_app_rdy_o => dbg_app_rdy,
dbg_app_wdf_rdy_o => dbg_app_wdf_rdy,
dbg_ddr_ui_clk_o => dbg_ddr_ui_clk,
dbg_ddr_ui_reset_o => dbg_ddr_ui_reset,
dbg_arb_req_o => dbg_arb_req,
dbg_arb_gnt_o => dbg_arb_gnt
);
wb_ma_pcie_rstn <= not wb_ma_pcie_rst;
----------------------------------
-- RS232 Core --
----------------------------------
cmp_xwb_rs232_syscon : xwb_rs232_syscon
generic map (
g_ma_interface_mode => PIPELINED,
g_ma_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rstn_i => '1', -- No need for resetting the controller
-- External ports
rs232_rxd_i => rs232_rxd_i,
rs232_txd_o => rs232_txd_o,
-- Reset to FPGA logic
rstn_o => rs232_rstn,
-- WISHBONE master
wb_master_i => cbar_slave_o(1),
wb_master_o => cbar_slave_i(1)
);
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
--g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
--g_must_have_init_file => true,
g_must_have_init_file => false,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(4),
wb_master_out => cbar_slave_i(4),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
---- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
--The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(5),
tx_ram_i => cbar_slave_o(5),
rx_ram_o => cbar_slave_i(6),
rx_ram_i => cbar_slave_o(6),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(7) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(7);
-- The FMC130M_4CH is slave 8
cmp_xwb_fmc130m_4ch : xwb_fmc130m_4ch
generic map(
g_fpga_device => "VIRTEX6",
g_delay_type => "VAR_LOADABLE",
g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
g_address_granularity => BYTE,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88),
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from fmc130m_4ch.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "1111",
g_with_bufio_clk_chains => "0000",
g_with_bufr_clk_chains => "1111",
g_use_data_chains => "1111",
--g_map_clk_data_chains => (-1,-1,-1,-1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_adc_ref_clk,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(8),
wb_slv_o => cbar_master_i(8),
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o => fmc_adc_pga_o,
fmc_adc_shdn_o => fmc_adc_shdn_o,
fmc_adc_dith_o => fmc_adc_dith_o,
fmc_adc_rand_o => fmc_adc_rand_o,
-- ADC0 LTC2208
fmc_adc0_clk_i => fmc_adc0_clk_i,
fmc_adc0_data_i => fmc_adc0_data_i,
fmc_adc0_of_i => fmc_adc0_of_i,
-- ADC1 LTC2208
fmc_adc1_clk_i => fmc_adc1_clk_i,
fmc_adc1_data_i => fmc_adc1_data_i,
fmc_adc1_of_i => fmc_adc1_of_i,
-- ADC2 LTC2208
fmc_adc2_clk_i => fmc_adc2_clk_i,
fmc_adc2_data_i => fmc_adc2_data_i,
fmc_adc2_of_i => fmc_adc2_of_i,
-- ADC3 LTC2208
fmc_adc3_clk_i => fmc_adc3_clk_i,
fmc_adc3_data_i => fmc_adc3_data_i,
fmc_adc3_of_i => fmc_adc3_of_i,
-- FMC General Status
fmc_prsnt_i => fmc_prsnt_i,
fmc_pg_m2c_i => fmc_pg_m2c_i,
-- Trigger
fmc_trig_dir_o => fmc_trig_dir_o,
fmc_trig_term_o => fmc_trig_term_o,
fmc_trig_val_p_b => fmc_trig_val_p_b,
fmc_trig_val_n_b => fmc_trig_val_n_b,
-- Si571 clock gen
si571_scl_pad_b => si571_scl_pad_b,
si571_sda_pad_b => si571_sda_pad_b,
fmc_si571_oe_o => fmc_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => spi_ad9510_cs_o,
spi_ad9510_sclk_o => spi_ad9510_sclk_o,
spi_ad9510_mosi_o => spi_ad9510_mosi_o,
spi_ad9510_miso_i => spi_ad9510_miso_i,
fmc_pll_function_o => fmc_pll_function_o,
fmc_pll_status_i => fmc_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc_clk_sel_o,
-- EEPROM
eeprom_scl_pad_b => eeprom_scl_pad_b,
eeprom_sda_pad_b => eeprom_sda_pad_b,
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b => lm75_scl_pad_b,
lm75_sda_pad_b => lm75_sda_pad_b,
fmc_lm75_temp_alarm_i => fmc_lm75_temp_alarm_i,
-- FMC LEDs
fmc_led1_o => fmc_led1_int,
fmc_led2_o => fmc_led2_int,
fmc_led3_o => fmc_led3_int,
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i => '0', -- Unused
fmc_ext_ref_clk2x_i => '0', -- Unused
fmc_ext_ref_mmcm_locked_i => '0', -- Unused
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => fmc_130m_4ch_clk,
adc_clk2x_o => fmc_130m_4ch_clk2x,
adc_rst_n_o => fmc_130m_4ch_rst_n,
adc_rst2x_n_o => fmc_130m_4ch_rst2x_n,
adc_data_o => fmc_130m_4ch_data,
adc_data_valid_o => fmc_130m_4ch_data_valid,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => '0',
-- General board status
fmc_mmcm_lock_o => fmc_mmcm_lock_int,
fmc_pll_status_o => fmc_pll_status_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc130m_4ch_in_array,
wbs_source_o => wbs_fmc130m_4ch_out_array,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc130m_4ch_debug_valid_int,
fifo_debug_full_o => fmc130m_4ch_debug_full_int,
fifo_debug_empty_o => fmc130m_4ch_debug_empty_int
);
gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc130m_4ch_in_array(i) <= cc_dummy_src_com_in;
end generate;
fmc_mmcm_lock_led_o <= fmc_mmcm_lock_int;
fmc_pll_status_led_o <= fmc_pll_status_int;
fmc_led1_o <= fmc_led1_int;
fmc_led2_o <= fmc_led2_int;
fmc_led3_o <= fmc_led3_int;
adc_data_ch0 <= fmc_130m_4ch_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb);
adc_data_ch1 <= fmc_130m_4ch_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb);
adc_data_ch2 <= fmc_130m_4ch_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb);
adc_data_ch3 <= fmc_130m_4ch_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb);
fs_clk <= fmc_130m_4ch_clk(c_adc_ref_clk);
fs_rstn <= fmc_130m_4ch_rst_n(c_adc_ref_clk);
fs_clk2x <= fmc_130m_4ch_clk2x(c_adc_ref_clk);
fs_rst2xn <= fmc_130m_4ch_rst2x_n(c_adc_ref_clk);
--led_south_o <= fmc_led1_int;
--led_east_o <= fmc_led2_int;
--led_north_o <= fmc_led3_int;
----------------------------------------------------------------------
-- DSP Chain Core --
----------------------------------------------------------------------
-- Testing with internal DDS
cmp_dds_adc_input : dds_adc_input
port map (
aclk => fs_clk,
m_axis_data_tvalid => open,
m_axis_data_tdata => dds_data
);
dds_sine <= dds_data(31 downto 16);
dds_cosine <= dds_data(15 downto 0);
cmp_multiplier_16x10_DSP_ch0 : multiplier_16x10_DSP
port map (
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch0,
p => synth_adc0_full
);
synth_adc0 <= synth_adc0_full(25 downto 10);
cmp_multiplier_16x10_DSP_ch1 : multiplier_16x10_DSP
port map(
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch1,
p => synth_adc1_full
);
synth_adc1 <= synth_adc1_full(25 downto 10);
cmp_multiplier_16x10_DSP_ch2 : multiplier_16x10_DSP
port map(
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch2,
p => synth_adc2_full
);
synth_adc2 <= synth_adc2_full(25 downto 10);
cmp_multiplier_16x10_DSP_ch3 : multiplier_16x10_DSP
port map (
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch3,
p => synth_adc3_full
);
synth_adc3 <= synth_adc3_full(25 downto 10);
-- MUX between sinthetic data and real ADC data
adc_ch0_data <= synth_adc0 when adc_synth_data_en = '1' else adc_data_ch0;
adc_ch1_data <= synth_adc1 when adc_synth_data_en = '1' else adc_data_ch1;
adc_ch2_data <= synth_adc2 when adc_synth_data_en = '1' else adc_data_ch2;
adc_ch3_data <= synth_adc3 when adc_synth_data_en = '1' else adc_data_ch3;
-- Position calc core is slave 7
cmp_xwb_position_calc_core : xwb_position_calc_core
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_with_switching => 0
)
port map (
rst_n_i => clk_sys_rstn,
clk_i => clk_sys, -- Wishbone clock
fs_rst_n_i => fs_rstn,
fs_rst2x_n_i => fs_rst2xn,
fs_clk_i => fs_clk, -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i => fs_clk2x, -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => cbar_master_o(7),
wb_slv_o => cbar_master_i(7),
-----------------------------
-- Raw ADC signals
-----------------------------
--adc_ch0_i => adc_ch0_data_uncross,
--adc_ch1_i => adc_ch1_data_uncross,
--adc_ch2_i => adc_ch2_data_uncross,
--adc_ch3_i => adc_ch3_data_uncross,
adc_ch0_i => adc_ch0_data,
adc_ch1_i => adc_ch1_data,
adc_ch2_i => adc_ch2_data,
adc_ch3_i => adc_ch3_data,
-------------------------------
---- DSP config parameter signals
-------------------------------
--kx_i => dsp_kx,
--ky_i => dsp_ky,
--ksum_i => dsp_ksum,
--
--del_sig_div_fofb_thres_i => dsp_del_sig_div_thres,
--del_sig_div_tbt_thres_i => dsp_del_sig_div_thres,
--del_sig_div_monit_thres_i => dsp_del_sig_div_thres,
--
--dds_config_valid_ch0_i => dsp_dds_config_valid_ch0,
--dds_config_valid_ch1_i => dsp_dds_config_valid_ch1,
--dds_config_valid_ch2_i => dsp_dds_config_valid_ch2,
--dds_config_valid_ch3_i => dsp_dds_config_valid_ch3,
--dds_pinc_ch0_i => dsp_dds_pinc_ch0,
--dds_pinc_ch1_i => dsp_dds_pinc_ch1,
--dds_pinc_ch2_i => dsp_dds_pinc_ch2,
--dds_pinc_ch3_i => dsp_dds_pinc_ch3,
--dds_poff_ch0_i => dsp_dds_poff_ch0,
--dds_poff_ch1_i => dsp_dds_poff_ch1,
--dds_poff_ch2_i => dsp_dds_poff_ch2,
--dds_poff_ch3_i => dsp_dds_poff_ch3,
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o => dsp_adc_ch0_data,
adc_ch1_dbg_data_o => dsp_adc_ch1_data,
adc_ch2_dbg_data_o => dsp_adc_ch2_data,
adc_ch3_dbg_data_o => dsp_adc_ch3_data,
bpf_ch0_o => dsp_bpf_ch0,
--bpf_ch1_o => out std_logic_vector(23 downto 0);
bpf_ch2_o => dsp_bpf_ch2,
--bpf_ch3_o => out std_logic_vector(23 downto 0);
bpf_valid_o => dsp_bpf_valid,
mix_ch0_i_o => dsp_mix_ch0,
--mix_ch0_q_o => out std_logic_vector(23 downto 0);
--mix_ch1_i_o => out std_logic_vector(23 downto 0);
--mix_ch1_q_o => out std_logic_vector(23 downto 0);
mix_ch2_i_o => dsp_mix_ch2,
--mix_ch2_q_o => out std_logic_vector(23 downto 0);
--mix_ch3_i_o => out std_logic_vector(23 downto 0);
--mix_ch3_q_o => out std_logic_vector(23 downto 0);
mix_valid_o => dsp_mix_valid,
tbt_decim_ch0_i_o => dsp_poly35_ch0,
--tbt_decim_ch0_i_o => open,
--poly35_ch0_q_o => out std_logic_vector(23 downto 0);
--poly35_ch1_i_o => out std_logic_vector(23 downto 0);
--poly35_ch1_q_o => out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o => dsp_poly35_ch2,
--tbt_decim_ch2_i_o => open,
--poly35_ch2_q_o => out std_logic_vector(23 downto 0);
--poly35_ch3_i_o => out std_logic_vector(23 downto 0);
--poly35_ch3_q_o => out std_logic_vector(23 downto 0);
tbt_decim_valid_o => dsp_poly35_valid,
--tbt_decim_q_ch01_incorrect_o => dsp_tbt_decim_q_ch01_incorrect,
--tbt_decim_q_ch23_incorrect_o => dsp_tbt_decim_q_ch23_incorrect,
tbt_amp_ch0_o => dsp_tbt_amp_ch0,
tbt_amp_ch1_o => dsp_tbt_amp_ch1,
tbt_amp_ch2_o => dsp_tbt_amp_ch2,
tbt_amp_ch3_o => dsp_tbt_amp_ch3,
tbt_amp_valid_o => dsp_tbt_amp_valid,
tbt_pha_ch0_o => dsp_tbt_pha_ch0,
tbt_pha_ch1_o => dsp_tbt_pha_ch1,
tbt_pha_ch2_o => dsp_tbt_pha_ch2,
tbt_pha_ch3_o => dsp_tbt_pha_ch3,
tbt_pha_valid_o => dsp_tbt_pha_valid,
fofb_decim_ch0_i_o => dsp_cic_fofb_ch0, --out std_logic_vector(23 downto 0);
--cic_fofb_ch0_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_q_o => out std_logic_vector(24 downto 0);
fofb_decim_ch2_i_o => dsp_cic_fofb_ch2, --out std_logic_vector(23 downto 0);
--cic_fofb_ch2_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_q_o => out std_logic_vector(24 downto 0);
fofb_decim_valid_o => dsp_cic_fofb_valid,
fofb_amp_ch0_o => dsp_fofb_amp_ch0,
fofb_amp_ch1_o => dsp_fofb_amp_ch1,
fofb_amp_ch2_o => dsp_fofb_amp_ch2,
fofb_amp_ch3_o => dsp_fofb_amp_ch3,
fofb_amp_valid_o => dsp_fofb_amp_valid,
fofb_pha_ch0_o => dsp_fofb_pha_ch0,
fofb_pha_ch1_o => dsp_fofb_pha_ch1,
fofb_pha_ch2_o => dsp_fofb_pha_ch2,
fofb_pha_ch3_o => dsp_fofb_pha_ch3,
fofb_pha_valid_o => dsp_fofb_pha_valid,
monit_amp_ch0_o => dsp_monit_amp_ch0,
monit_amp_ch1_o => dsp_monit_amp_ch1,
monit_amp_ch2_o => dsp_monit_amp_ch2,
monit_amp_ch3_o => dsp_monit_amp_ch3,
monit_amp_valid_o => dsp_monit_amp_valid,
pos_x_tbt_o => dsp_pos_x_tbt,
pos_y_tbt_o => dsp_pos_y_tbt,
pos_q_tbt_o => dsp_pos_q_tbt,
pos_sum_tbt_o => dsp_pos_sum_tbt,
pos_tbt_valid_o => dsp_pos_tbt_valid,
pos_x_fofb_o => dsp_pos_x_fofb,
pos_y_fofb_o => dsp_pos_y_fofb,
pos_q_fofb_o => dsp_pos_q_fofb,
pos_sum_fofb_o => dsp_pos_sum_fofb,
pos_fofb_valid_o => dsp_pos_fofb_valid,
pos_x_monit_o => dsp_pos_x_monit,
pos_y_monit_o => dsp_pos_y_monit,
pos_q_monit_o => dsp_pos_q_monit,
pos_sum_monit_o => dsp_pos_sum_monit,
pos_monit_valid_o => dsp_pos_monit_valid,
pos_x_monit_1_o => dsp_pos_x_monit_1,
pos_y_monit_1_o => dsp_pos_y_monit_1,
pos_q_monit_1_o => dsp_pos_q_monit_1,
pos_sum_monit_1_o => dsp_pos_sum_monit_1,
pos_monit_1_valid_o => dsp_pos_monit_1_valid,
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o => clk_rffe_swap,
flag1_o => flag1_int,
flag2_o => flag2_int,
ctrl1_o => open,
ctrl2_o => open,
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o => dsp_clk_ce_1,
clk_ce_1112_o => dsp_clk_ce_1112,
clk_ce_11120000_o => dsp_clk_ce_11120000,
clk_ce_1390000_o => dsp_clk_ce_1390000,
clk_ce_2_o => dsp_clk_ce_2,
clk_ce_2224_o => dsp_clk_ce_2224,
clk_ce_22240000_o => dsp_clk_ce_22240000,
clk_ce_2780000_o => dsp_clk_ce_2780000,
clk_ce_35_o => dsp_clk_ce_35,
clk_ce_5000_o => dsp_clk_ce_5000,
clk_ce_556_o => dsp_clk_ce_556,
clk_ce_5560000_o => dsp_clk_ce_5560000,
clk_ce_70_o => dsp_clk_ce_70,
dbg_cur_address_o => dbg_cur_address,
dbg_adc_ch0_cond_o => dbg_adc_ch0_cond,
dbg_adc_ch1_cond_o => dbg_adc_ch1_cond,
dbg_adc_ch2_cond_o => dbg_adc_ch2_cond,
dbg_adc_ch3_cond_o => dbg_adc_ch3_cond
);
flag1_o <= flag1_int;
flag2_o <= flag2_int;
-- There is no clk_swap2x_o, so we just output the same as clk_swap_o
clk_swap_o <= clk_rffe_swap;
clk_swap2x_o <= clk_rffe_swap;
-- The board peripherals components is slave 9
cmp_xwb_dbe_periph : xwb_dbe_periph
generic map(
-- NOT used!
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period => c_tics_cntr_period,
g_num_leds => c_leds_num_pins,
g_num_buttons => c_buttons_num_pins
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- UART
--uart_rxd_i => uart_rxd_i,
--uart_txd_o => uart_txd_o,
uart_rxd_i => '1',
uart_txd_o => open,
-- LEDs
led_out_o => gpio_leds_int,
led_in_i => gpio_leds_int,
led_oen_o => open,
-- Buttons
button_out_o => open,
--button_in_i => buttons_i,
button_in_i => buttons_dummy,
button_oen_o => open,
-- Wishbone
slave_i => cbar_master_o(9),
slave_o => cbar_master_i(9)
);
leds_o <= gpio_leds_int;
--------------------
-- ADC data
--------------------
acq_chan_array(c_acq_adc_id).val_low <= dsp_adc_ch3_data &
dsp_adc_ch2_data &
dsp_adc_ch1_data &
dsp_adc_ch0_data;
acq_chan_array(c_acq_adc_id).val_high <= (others => '0');
acq_chan_array(c_acq_adc_id).dvalid <= '1';
acq_chan_array(c_acq_adc_id).trig <= '0';
--------------------
-- TBT AMP data
--------------------
acq_chan_array(c_acq_tbt_amp_id).val_low <= std_logic_vector(resize(signed(dsp_tbt_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp_tbt_amp_ch0), 32));
acq_chan_array(c_acq_tbt_amp_id).val_high <= std_logic_vector(resize(signed(dsp_tbt_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp_tbt_amp_ch2), 32));
acq_chan_array(c_acq_tbt_amp_id).dvalid <= dsp_tbt_amp_valid;
acq_chan_array(c_acq_tbt_amp_id).trig <= '0';
--------------------
-- TBT POS data
--------------------
acq_chan_array(c_acq_tbt_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_tbt), 32)) &
std_logic_vector(resize(signed(dsp_pos_x_tbt), 32));
acq_chan_array(c_acq_tbt_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_tbt), 32)) &
std_logic_vector(resize(signed(dsp_pos_q_tbt), 32));
acq_chan_array(c_acq_tbt_pos_id).dvalid <= dsp_pos_tbt_valid;
acq_chan_array(c_acq_tbt_pos_id).trig <= '0';
--------------------
-- FOFB AMP data
--------------------
acq_chan_array(c_acq_fofb_amp_id).val_low <= std_logic_vector(resize(signed(dsp_fofb_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp_fofb_amp_ch0), 32));
acq_chan_array(c_acq_fofb_amp_id).val_high <= std_logic_vector(resize(signed(dsp_fofb_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp_fofb_amp_ch2), 32));
acq_chan_array(c_acq_fofb_amp_id).dvalid <= dsp_fofb_amp_valid;
acq_chan_array(c_acq_fofb_amp_id).trig <= '0';
--------------------
-- FOFB POS data
--------------------
acq_chan_array(c_acq_fofb_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_fofb), 32)) &
std_logic_vector(resize(signed(dsp_pos_x_fofb), 32));
acq_chan_array(c_acq_fofb_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_fofb), 32)) &
std_logic_vector(resize(signed(dsp_pos_q_fofb), 32));
acq_chan_array(c_acq_fofb_pos_id).dvalid <= dsp_pos_fofb_valid;
acq_chan_array(c_acq_fofb_pos_id).trig <= '0';
--------------------
-- MONIT AMP data
--------------------
acq_chan_array(c_acq_monit_amp_id).val_low <= std_logic_vector(resize(signed(dsp_monit_amp_ch1), 32)) &
std_logic_vector(resize(signed(dsp_monit_amp_ch0), 32));
acq_chan_array(c_acq_monit_amp_id).val_high <= std_logic_vector(resize(signed(dsp_monit_amp_ch3), 32)) &
std_logic_vector(resize(signed(dsp_monit_amp_ch2), 32));
acq_chan_array(c_acq_monit_amp_id).dvalid <= dsp_monit_amp_valid;
acq_chan_array(c_acq_monit_amp_id).trig <= '0';
--------------------
-- MONIT POS data
--------------------
acq_chan_array(c_acq_monit_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_monit), 32)) &
std_logic_vector(resize(signed(dsp_pos_x_monit), 32));
acq_chan_array(c_acq_monit_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_monit), 32)) &
std_logic_vector(resize(signed(dsp_pos_q_monit), 32));
acq_chan_array(c_acq_monit_pos_id).dvalid <= dsp_pos_monit_valid;
acq_chan_array(c_acq_monit_pos_id).trig <= '0';
--------------------
-- MONIT1 POS data
--------------------
acq_chan_array(c_acq_monit_1_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_monit_1), 32)) &
std_logic_vector(resize(signed(dsp_pos_x_monit_1), 32));
acq_chan_array(c_acq_monit_1_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_monit_1), 32)) &
std_logic_vector(resize(signed(dsp_pos_q_monit_1), 32));
acq_chan_array(c_acq_monit_1_pos_id).dvalid <= dsp_pos_monit_1_valid;
acq_chan_array(c_acq_monit_1_pos_id).trig <= '0';
-- The xwb_acq_core is slave 9
cmp_xwb_acq_core : xwb_acq_core
generic map
(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_acq_addr_width => c_acq_addr_width,
g_acq_num_channels => c_acq_num_channels,
g_acq_channels => c_acq_channels,
g_ddr_payload_width => c_ddr_payload_width,
g_ddr_dq_width => c_ddr_dq_width,
g_ddr_addr_width => c_ddr_addr_width,
--g_multishot_ram_size => 2048,
g_fifo_fc_size => c_acq_fifo_size -- avoid fifo overflow
--g_sim_readback => false
)
port map
(
fs_clk_i => fmc_130m_4ch_clk(c_adc_ref_clk),
fs_ce_i => '1',
fs_rst_n_i => fmc_130m_4ch_rst_n(c_adc_ref_clk),
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
-- From DDR3 Controller
ext_clk_i => memc_ui_clk,
ext_rst_n_i => memc_ui_rstn,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(10),
wb_slv_o => cbar_master_i(10),
-----------------------------
-- External Interface
-----------------------------
acq_chan_array_i => acq_chan_array,
-----------------------------
-- DRRAM Interface
-----------------------------
dpram_dout_o => bpm_acq_dpram_dout , -- to chipscope
dpram_valid_o => bpm_acq_dpram_valid, -- to chipscope
-----------------------------
-- External Interface (w/ FLow Control)
-----------------------------
ext_dout_o => bpm_acq_ext_dout, -- to chipscope
ext_valid_o => bpm_acq_ext_valid, -- to chipscope
ext_addr_o => bpm_acq_ext_addr, -- to chipscope
ext_sof_o => bpm_acq_ext_sof, -- to chipscope
ext_eof_o => bpm_acq_ext_eof, -- to chipscope
ext_dreq_o => bpm_acq_ext_dreq, -- to chipscope
ext_stall_o => bpm_acq_ext_stall, -- to chipscope
-----------------------------
-- DDR3 SDRAM Interface
-----------------------------
ui_app_addr_o => memc_cmd_addr,
ui_app_cmd_o => memc_cmd_instr,
ui_app_en_o => memc_cmd_en,
ui_app_rdy_i => memc_cmd_rdy,
ui_app_wdf_data_o => memc_wr_data,
ui_app_wdf_end_o => memc_wr_end,
ui_app_wdf_mask_o => memc_wr_mask,
ui_app_wdf_wren_o => memc_wr_en,
ui_app_wdf_rdy_i => memc_wr_rdy,
ui_app_rd_data_i => memc_rd_data, -- not used!
ui_app_rd_data_end_i => '0', -- not used!
ui_app_rd_data_valid_i => memc_rd_valid, -- not used!
-- DDR3 arbitrer for multiple accesses
ui_app_req_o => memarb_acc_req,
ui_app_gnt_i => memarb_acc_gnt,
-----------------------------
-- Debug Interface
-----------------------------
dbg_ddr_rb_data_o => dbg_ddr_rb_data,
dbg_ddr_rb_addr_o => dbg_ddr_rb_addr,
dbg_ddr_rb_valid_o => dbg_ddr_rb_valid
);
memc_ui_rstn <= not(memc_ui_rst);
memc_cmd_addr_resized <= f_gen_std_logic_vector(c_acq_ddr_addr_diff, '0') &
memc_cmd_addr;
---- Chipscope Analysis
--cmp_chipscope_icon_13 : chipscope_icon_13_port
--port map (
-- CONTROL0 => CONTROL0,
-- CONTROL1 => CONTROL1,
-- CONTROL2 => CONTROL2,
-- CONTROL3 => CONTROL3,
-- CONTROL4 => CONTROL4,
-- CONTROL5 => CONTROL5,
-- CONTROL6 => CONTROL6,
-- CONTROL7 => CONTROL7,
-- CONTROL8 => CONTROL8,
-- CONTROL9 => CONTROL9,
-- CONTROL10 => CONTROL10,
-- CONTROL11 => CONTROL11,
-- CONTROL12 => CONTROL12
--);
----cmp_chipscope_ila_0_adc : chipscope_ila
--cmp_chipscope_ila_adc : chipscope_ila_8192_5_port
--port map (
-- CONTROL => CONTROL0,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA0_0,
-- TRIG1 => TRIG_ILA0_1,
-- TRIG2 => TRIG_ILA0_2,
-- TRIG3 => TRIG_ILA0_3,
-- TRIG4 => TRIG_ILA0_4
--);
---- ADC Data
--TRIG_ILA0_0 <= dsp_adc_ch1_data & dsp_adc_ch0_data;
--TRIG_ILA0_1 <= dsp_adc_ch3_data & dsp_adc_ch2_data;
--TRIG_ILA0_2 <= dbg_adc_ch1_cond & dbg_adc_ch0_cond;
--TRIG_ILA0_3 <= dbg_adc_ch3_cond & dbg_adc_ch2_cond;
--TRIG_ILA0_4(dbg_cur_address'left downto 0)
-- <= dbg_cur_address;
---- Mix and BPF data
--cmp_chipscope_ila_1024_bpf_mix : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL1,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA1_0,
-- TRIG1 => TRIG_ILA1_1,
-- TRIG2 => TRIG_ILA1_2,
-- TRIG3 => TRIG_ILA1_3,
-- TRIG4 => TRIG_ILA1_4
--);
--TRIG_ILA1_0(0) <= dsp_bpf_valid;
--TRIG_ILA1_0(1) <= '0';
--TRIG_ILA1_0(2) <= '0';
--TRIG_ILA1_0(3) <= '0';
--TRIG_ILA1_0(4) <= '0';
--TRIG_ILA1_0(5) <= '0';
--TRIG_ILA1_0(6) <= '0';
--TRIG_ILA1_1(dsp_bpf_ch0'left downto 0) <= dsp_bpf_ch0;
--TRIG_ILA1_2(dsp_bpf_ch2'left downto 0) <= dsp_bpf_ch2;
--TRIG_ILA1_3(dsp_mix_ch0'left downto 0) <= dsp_mix_ch0;
--TRIG_ILA1_4(dsp_mix_ch2'left downto 0) <= dsp_mix_ch2;
----TBT amplitudes data
--cmp_chipscope_ila_1024_tbt_amp : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL2,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA2_0,
-- TRIG1 => TRIG_ILA2_1,
-- TRIG2 => TRIG_ILA2_2,
-- TRIG3 => TRIG_ILA2_3,
-- TRIG4 => TRIG_ILA2_4
--);
--TRIG_ILA2_0(0) <= dsp_tbt_amp_valid;
--TRIG_ILA2_0(1) <= '0';
--TRIG_ILA2_0(2) <= '0';
--TRIG_ILA2_0(3) <= '0';
--TRIG_ILA2_0(4) <= '0';
--TRIG_ILA2_0(5) <= '0';
--TRIG_ILA2_0(6) <= '0';
--TRIG_ILA2_1(dsp_tbt_amp_ch0'left downto 0) <= dsp_tbt_amp_ch0;
--TRIG_ILA2_2(dsp_tbt_amp_ch1'left downto 0) <= dsp_tbt_amp_ch1;
--TRIG_ILA2_3(dsp_tbt_amp_ch2'left downto 0) <= dsp_tbt_amp_ch2;
--TRIG_ILA2_4(dsp_tbt_amp_ch3'left downto 0) <= dsp_tbt_amp_ch3;
---- TBT position data
--cmp_chipscope_ila_1024_tbt_pos : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL3,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA3_0,
-- TRIG1 => TRIG_ILA3_1,
-- TRIG2 => TRIG_ILA3_2,
-- TRIG3 => TRIG_ILA3_3,
-- TRIG4 => TRIG_ILA3_4
--);
--TRIG_ILA3_0(0) <= dsp_pos_tbt_valid;
--TRIG_ILA3_0(1) <= '0';
--TRIG_ILA3_0(2) <= '0';
--TRIG_ILA3_0(3) <= '0';
--TRIG_ILA3_0(4) <= '0';
--TRIG_ILA3_0(5) <= '0';
--TRIG_ILA3_0(6) <= '0';
--TRIG_ILA3_1(dsp_pos_x_tbt'left downto 0) <= dsp_pos_x_tbt;
--TRIG_ILA3_2(dsp_pos_y_tbt'left downto 0) <= dsp_pos_y_tbt;
--TRIG_ILA3_3(dsp_pos_q_tbt'left downto 0) <= dsp_pos_q_tbt;
--TRIG_ILA3_4(dsp_pos_sum_tbt'left downto 0) <= dsp_pos_sum_tbt;
---- FOFB amplitudes data
--cmp_chipscope_ila_1024_fofb_amp : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL4,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA4_0,
-- TRIG1 => TRIG_ILA4_1,
-- TRIG2 => TRIG_ILA4_2,
-- TRIG3 => TRIG_ILA4_3,
-- TRIG4 => TRIG_ILA4_4
--);
--TRIG_ILA4_0(0) <= dsp_fofb_amp_valid;
--TRIG_ILA4_0(1) <= '0';
--TRIG_ILA4_0(2) <= '0';
--TRIG_ILA4_0(3) <= '0';
--TRIG_ILA4_0(4) <= '0';
--TRIG_ILA4_0(5) <= '0';
--TRIG_ILA4_0(6) <= '0';
--TRIG_ILA4_1(dsp_fofb_amp_ch0'left downto 0) <= dsp_fofb_amp_ch0;
--TRIG_ILA4_2(dsp_fofb_amp_ch1'left downto 0) <= dsp_fofb_amp_ch1;
--TRIG_ILA4_3(dsp_fofb_amp_ch2'left downto 0) <= dsp_fofb_amp_ch2;
--TRIG_ILA4_4(dsp_fofb_amp_ch3'left downto 0) <= dsp_fofb_amp_ch3;
---- FOFB position data
--cmp_chipscope_ila_1024_fofb_pos : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL5,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA5_0,
-- TRIG1 => TRIG_ILA5_1,
-- TRIG2 => TRIG_ILA5_2,
-- TRIG3 => TRIG_ILA5_3,
-- TRIG4 => TRIG_ILA5_4
--);
--TRIG_ILA5_0(0) <= dsp_pos_fofb_valid;
--TRIG_ILA5_0(1) <= '0';
--TRIG_ILA5_0(2) <= '0';
--TRIG_ILA5_0(3) <= '0';
--TRIG_ILA5_0(4) <= '0';
--TRIG_ILA5_0(5) <= '0';
--TRIG_ILA5_0(6) <= '0';
--TRIG_ILA5_1(dsp_pos_x_fofb'left downto 0) <= dsp_pos_x_fofb;
--TRIG_ILA5_2(dsp_pos_y_fofb'left downto 0) <= dsp_pos_y_fofb;
--TRIG_ILA5_3(dsp_pos_q_fofb'left downto 0) <= dsp_pos_q_fofb;
--TRIG_ILA5_4(dsp_pos_sum_fofb'left downto 0) <= dsp_pos_sum_fofb;
---- Monitoring position amplitude
--cmp_chipscope_ila_1024_monit_amp : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL6,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA6_0,
-- TRIG1 => TRIG_ILA6_1,
-- TRIG2 => TRIG_ILA6_2,
-- TRIG3 => TRIG_ILA6_3,
-- TRIG4 => TRIG_ILA6_4
--);
--TRIG_ILA6_0(0) <= dsp_monit_amp_valid;
--TRIG_ILA6_0(1) <= '0';
--TRIG_ILA6_0(2) <= '0';
--TRIG_ILA6_0(3) <= '0';
--TRIG_ILA6_0(4) <= '0';
--TRIG_ILA6_0(5) <= '0';
--TRIG_ILA6_0(6) <= '0';
--TRIG_ILA6_1(dsp_monit_amp_ch0'left downto 0) <= dsp_monit_amp_ch0;
--TRIG_ILA6_2(dsp_monit_amp_ch1'left downto 0) <= dsp_monit_amp_ch1;
--TRIG_ILA6_3(dsp_monit_amp_ch2'left downto 0) <= dsp_monit_amp_ch2;
--TRIG_ILA6_4(dsp_monit_amp_ch3'left downto 0) <= dsp_monit_amp_ch3;
---- Monitoring position data
---- cmp_chipscope_ila_4096_monit_pos : chipscope_ila_4096
--cmp_chipscope_ila_1024_monit_pos : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL7,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA7_0,
-- TRIG1 => TRIG_ILA7_1,
-- TRIG2 => TRIG_ILA7_2,
-- TRIG3 => TRIG_ILA7_3,
-- TRIG4 => TRIG_ILA7_4
--);
--TRIG_ILA7_0(0) <= dsp_pos_monit_valid;
--TRIG_ILA7_0(1) <= '0';
--TRIG_ILA7_0(2) <= '0';
--TRIG_ILA7_0(3) <= '0';
--TRIG_ILA7_0(4) <= '0';
--TRIG_ILA7_0(5) <= '0';
--TRIG_ILA7_0(6) <= '0';
--TRIG_ILA7_1(dsp_pos_x_monit'left downto 0) <= dsp_pos_x_monit;
--TRIG_ILA7_2(dsp_pos_y_monit'left downto 0) <= dsp_pos_y_monit;
--TRIG_ILA7_3(dsp_pos_q_monit'left downto 0) <= dsp_pos_q_monit;
--TRIG_ILA7_4(dsp_pos_sum_monit'left downto 0) <= dsp_pos_sum_monit;
---- Monitoring 1 position data
--cmp_chipscope_ila_1024_monit_pos_1 : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL8,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA8_0,
-- TRIG1 => TRIG_ILA8_1,
-- TRIG2 => TRIG_ILA8_2,
-- TRIG3 => TRIG_ILA8_3,
-- TRIG4 => TRIG_ILA8_4
--);
--TRIG_ILA8_0(0) <= dsp_pos_monit_1_valid;
--TRIG_ILA8_0(1) <= '0';
--TRIG_ILA8_0(2) <= '0';
--TRIG_ILA8_0(3) <= '0';
--TRIG_ILA8_0(4) <= '0';
--TRIG_ILA8_0(5) <= '0';
--TRIG_ILA8_0(6) <= '0';
--TRIG_ILA8_1(dsp_pos_x_monit_1'left downto 0) <= dsp_pos_x_monit_1;
--TRIG_ILA8_2(dsp_pos_y_monit_1'left downto 0) <= dsp_pos_y_monit_1;
--TRIG_ILA8_3(dsp_pos_q_monit_1'left downto 0) <= dsp_pos_q_monit_1;
--TRIG_ILA8_4(dsp_pos_sum_monit_1'left downto 0) <= dsp_pos_sum_monit_1;
---- TBT Phase data
--cmp_chipscope_ila_1024_tbt_pha : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL9,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA9_0,
-- TRIG1 => TRIG_ILA9_1,
-- TRIG2 => TRIG_ILA9_2,
-- TRIG3 => TRIG_ILA9_3,
-- TRIG4 => TRIG_ILA9_4
--);
--TRIG_ILA9_0(0) <= dsp_tbt_pha_valid;
--TRIG_ILA9_0(1) <= '0';
--TRIG_ILA9_0(2) <= '0';
--TRIG_ILA9_0(3) <= '0';
--TRIG_ILA9_0(4) <= '0';
--TRIG_ILA9_0(5) <= '0';
--TRIG_ILA9_0(6) <= '0';
--TRIG_ILA9_1(dsp_tbt_pha_ch0'left downto 0) <= dsp_tbt_pha_ch0;
--TRIG_ILA9_2(dsp_tbt_pha_ch1'left downto 0) <= dsp_tbt_pha_ch1;
--TRIG_ILA9_3(dsp_tbt_pha_ch2'left downto 0) <= dsp_tbt_pha_ch2;
--TRIG_ILA9_4(dsp_tbt_pha_ch3'left downto 0) <= dsp_tbt_pha_ch3;
---- FOFB Phase data
--cmp_chipscope_ila_1024_fofb_pha : chipscope_ila_1024
--port map (
-- CONTROL => CONTROL10,
-- CLK => fs_clk,
-- TRIG0 => TRIG_ILA10_0,
-- TRIG1 => TRIG_ILA10_1,
-- TRIG2 => TRIG_ILA10_2,
-- TRIG3 => TRIG_ILA10_3,
-- TRIG4 => TRIG_ILA10_4
--);
--TRIG_ILA10_0(0) <= dsp_fofb_pha_valid;
--TRIG_ILA10_0(1) <= '0';
--TRIG_ILA10_0(2) <= '0';
--TRIG_ILA10_0(3) <= '0';
--TRIG_ILA10_0(4) <= '0';
--TRIG_ILA10_0(5) <= '0';
--TRIG_ILA10_0(6) <= '0';
--TRIG_ILA10_1(dsp_fofb_pha_ch0'left downto 0) <= dsp_fofb_pha_ch0;
--TRIG_ILA10_2(dsp_fofb_pha_ch1'left downto 0) <= dsp_fofb_pha_ch1;
--TRIG_ILA10_3(dsp_fofb_pha_ch2'left downto 0) <= dsp_fofb_pha_ch2;
--TRIG_ILA10_4(dsp_fofb_pha_ch3'left downto 0) <= dsp_fofb_pha_ch3;
---- Controllable gain for test data
--cmp_chipscope_vio_256 : chipscope_vio_256
--port map (
-- CONTROL => CONTROL11,
-- ASYNC_OUT => vio_out
--);
--dds_sine_gain_ch0 <= vio_out(10-1 downto 0);
--dds_sine_gain_ch1 <= vio_out(20-1 downto 10);
--dds_sine_gain_ch2 <= vio_out(30-1 downto 20);
--dds_sine_gain_ch3 <= vio_out(40-1 downto 30);
--adc_synth_data_en <= vio_out(40);
---- Controllable DDS frequency and phase
--cmp_chipscope_vio_256_dsp_config : chipscope_vio_256
--port map (
-- CONTROL => CONTROL12,
-- ASYNC_OUT => vio_out_dsp_config
--);
end ;
|
lgpl-3.0
|
ec4de576bf44e07649260bea73bb1fd0
| 0.42704 | 3.770345 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/TmpVarExample1.vhd
| 1 | 661 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TmpVarExample1 IS
PORT(
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF TmpVarExample1 IS
BEGIN
assig_process_b: PROCESS(a)
VARIABLE tmpTypeConv_0 : BOOLEAN;
VARIABLE tmpTypeConv_1 : BOOLEAN;
BEGIN
tmpTypeConv_0 := a(15 DOWNTO 0) = X"0001";
tmpTypeConv_1 := a(31 DOWNTO 16) = X"0001";
IF tmpTypeConv_0 AND tmpTypeConv_1 THEN
b <= X"00000000";
ELSE
b <= X"00000001";
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
8b1517ddd9aa289cae02bbb15e68fee2
| 0.606657 | 3.692737 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/PLL/tb_top_nto1_pll.vhd
| 1 | 6,758 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: tb_top_nto1_pll.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Test Bench
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
entity tb_top_nto1_pll is end tb_top_nto1_pll ;
architecture rtl of tb_top_nto1_pll is
component top_nto1_pll_diff_tx is port (
refclkin_p, refclkin_n : in std_logic ; -- reference clock input
reset : in std_logic ; -- reset (active high)
clkout_p, clkout_n : out std_logic ; -- lvds clock output
dataout_p, dataout_n : out std_logic_vector(5 downto 0)) ; -- lvds data outputs
end component;
component top_nto1_pll_diff_rx is port (
reset : in std_logic ; -- reset (active high)
clkin_p, clkin_n : in std_logic ; -- lvds clock input
datain_p, datain_n : in std_logic_vector(5 downto 0) ; -- lvds data inputs
dummy_out : out std_logic_vector(41 downto 0)) ; -- dummy outputs
end component ;
component top_nto1_pll_diff_rx_and_tx is port (
reset : in std_logic ; -- reset (active high)
clkin_p, clkin_n : in std_logic ; -- lvds clock input
datain_p, datain_n : in std_logic_vector(5 downto 0) ; -- lvds data inputs
clkout_p, clkout_n : out std_logic ; -- lvds clock output
dataout_p, dataout_n : out std_logic_vector(5 downto 0)) ; -- lvds data outputs
end component ;
signal clkout_p : std_logic ;
signal clkout_n : std_logic ;
signal dummy_out : std_logic_vector(41 downto 0) ;
signal dummy_out2 : std_logic_vector(41 downto 0) ;
signal old : std_logic_vector(41 downto 0) ;
signal clkin_p : std_logic ;
signal old2 : std_logic_vector(41 downto 0) ;
signal pixelclock_p : std_logic := '0' ;
signal pixelclock_n : std_logic ;
signal match : std_logic ;
signal reset : std_logic := '1' ;
signal reset2 : std_logic := '1' ;
signal dataout_p : std_logic_vector(5 downto 0) ;
signal dataout_n : std_logic_vector(5 downto 0) ;
signal match2 : std_logic ;
signal dataout2_p : std_logic_vector(5 downto 0) ;
signal dataout2_n : std_logic_vector(5 downto 0) ;
signal clkout2_p : std_logic ;
signal clkout2_n : std_logic ;
begin
pixelclock_p <= not pixelclock_p after 3 nS ; -- local clock
reset <= '0' after 150 nS;
reset2 <= '0' after 300 nS;
pixelclock_n <= not pixelclock_p ;
process (pixelclock_p)
begin
if pixelclock_p'event and pixelclock_p = '1' then
old <= dummy_out ;
if dummy_out = old(40 downto 0) & old(41) then
match <= '1' ;
else
match <= '0' ;
end if ;
end if ;
end process ;
process (pixelclock_p)
begin
if pixelclock_p'event and pixelclock_p = '1' then
old2 <= dummy_out2 ;
if dummy_out2 = old2(40 downto 0) & old2(41) then
match2 <= '1' ;
else
match2 <= '0' ;
end if ;
end if ;
end process ;
diff_tx : top_nto1_pll_diff_tx port map (
refclkin_p => pixelclock_p,
refclkin_n => pixelclock_n,
reset => reset,
clkout_p => clkout_p,
clkout_n => clkout_n,
dataout_p => dataout_p,
dataout_n => dataout_n) ;
diff_rx : top_nto1_pll_diff_rx port map (
reset => reset,
clkin_p => clkout_p,
clkin_n => clkout_n,
datain_p => dataout_p,
datain_n => dataout_n,
dummy_out => dummy_out) ;
diff_rx_and_tx : top_nto1_pll_diff_rx_and_tx port map (
reset => reset,
clkin_p => clkout_p,
clkin_n => clkout_n,
datain_p => dataout_p,
datain_n => dataout_n,
clkout_p => clkout2_p,
clkout_n => clkout2_n,
dataout_p => dataout2_p,
dataout_n => dataout2_n) ;
diff_rx2 : top_nto1_pll_diff_rx port map (
reset => reset,
clkin_p => clkout2_p,
clkin_n => clkout2_n,
datain_p => dataout2_p,
datain_n => dataout2_n,
dummy_out => dummy_out2) ;
end rtl ;
|
apache-2.0
|
e189d3637581fd05dea7b749866b1464
| 0.59559 | 3.231946 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/mixer/mixer.vhd
| 1 | 3,912 |
-------------------------------------------------------------------------------
-- Title : BPM Mixer
-- Project :
-------------------------------------------------------------------------------
-- File : mixer.vhd
-- Author : Gustavo BM Bruno
-- Company : LNLS - CNPEM
-- Created : 2014-01-21
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Mixer at input stage for BPM
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-21 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.dsp_cores_pkg.all;
use work.bpm_cores_pkg.all;
entity mixer is
generic(
g_sin_file : string := "./dds_sin.nif";
g_cos_file : string := "./dds_cos.nif";
g_number_of_points : natural := 6;
g_input_width : natural := 16;
g_dds_width : natural := 16;
g_output_width : natural := 32;
g_tag_width : natural := 1; -- Input data tag width
g_mult_levels : natural := 7
);
port(
rst_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
signal_i : in std_logic_vector(g_input_width-1 downto 0);
valid_i : in std_logic;
tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
I_out : out std_logic_vector(g_output_width-1 downto 0);
I_tag_out : out std_logic_vector(g_tag_width-1 downto 0);
Q_out : out std_logic_vector(g_output_width-1 downto 0);
Q_tag_out : out std_logic_vector(g_tag_width-1 downto 0);
valid_o : out std_logic);
end entity mixer;
architecture rtl of mixer is
signal sine : std_logic_vector(g_dds_width-1 downto 0);
signal cosine : std_logic_vector(g_dds_width-1 downto 0);
signal dds_valid : std_logic;
signal I_valid_out : std_logic;
signal Q_valid_out : std_logic;
begin
cmp_dds : fixed_dds
generic map (
g_number_of_points => g_number_of_points,
g_output_width => g_dds_width,
g_sin_file => g_sin_file,
g_cos_file => g_cos_file)
port map (
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i,
valid_i => valid_i,
sin_o => sine,
cos_o => cosine,
valid_o => dds_valid);
cmp_mult_I : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_dds_width,
g_tag_width => g_tag_width,
g_signed => true,
g_p_width => g_output_width,
g_round_convergent => 1)
port map (
a_i => signal_i,
b_i => cosine,
tag_i => tag_i,
valid_i => dds_valid,
p_o => I_out,
valid_o => I_valid_out,
tag_o => I_tag_out,
ce_i => ce_i,
clk_i => clk_i,
rst_i => rst_i);
cmp_mult_Q : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_dds_width,
g_tag_width => g_tag_width,
g_signed => true,
g_p_width => g_output_width,
g_round_convergent => 1)
port map (
a_i => signal_i,
b_i => sine,
tag_i => tag_i,
valid_i => dds_valid,
p_o => Q_out,
valid_o => Q_valid_out,
tag_o => Q_tag_out,
clk_i => clk_i,
ce_i => ce_i,
rst_i => rst_i);
-- Any valid, either from I or Q is fine.
valid_o <= I_valid_out;
end rtl;
|
lgpl-3.0
|
eed495710e8336079845edb4fc6a91c4
| 0.453988 | 3.323704 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/afc_v3/dbe_pbpm/dbe_pbpm.vhd
| 1 | 43,271 |
------------------------------------------------------------------------------
-- Title : Top FMC250M design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC250M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-19 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- IP cores constants
use work.ipcores_pkg.all;
-- AFC definitions
use work.afc_base_pkg.all;
entity dbe_pbpm is
port(
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;
afc_fp2_clk1_p_i : in std_logic;
afc_fp2_clk1_n_i : in std_logic;
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0);
trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0);
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i : in std_logic := '0';
diag_spi_si_i : in std_logic := '0';
diag_spi_so_o : out std_logic;
diag_spi_clk_i : in std_logic := '0';
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o : out std_logic;
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b : inout std_logic;
afc_si57x_sda_b : inout std_logic;
-- Si57x oscillator output enable
afc_si57x_oe_o : out std_logic;
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b : inout std_logic;
board_i2c_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o : out std_logic;
-- spi_cs_n_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic := '0';
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmc1_adc_cnv_o : out std_logic;
fmc1_adc_sck_o : out std_logic;
fmc1_adc_sck_rtrn_i : in std_logic;
fmc1_adc_sdo1_i : in std_logic;
fmc1_adc_sdo2_i : in std_logic;
fmc1_adc_sdo3_i : in std_logic;
fmc1_adc_sdo4_i : in std_logic;
fmc1_adc_busy_cmn_i : in std_logic;
fmc1_rng_r1_o : out std_logic;
fmc1_rng_r2_o : out std_logic;
fmc1_rng_r3_o : out std_logic;
fmc1_rng_r4_o : out std_logic;
fmc1_led1_o : out std_logic;
fmc1_led2_o : out std_logic;
-- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
-- fmc1_sm_scl_o : out std_logic;
-- fmc1_sm_sda_b : inout std_logic;
fmc1_a_scl_o : out std_logic;
fmc1_a_sda_b : inout std_logic;
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmc2_adc_cnv_o : out std_logic;
fmc2_adc_sck_o : out std_logic;
fmc2_adc_sck_rtrn_i : in std_logic;
fmc2_adc_sdo1_i : in std_logic;
fmc2_adc_sdo2_i : in std_logic;
fmc2_adc_sdo3_i : in std_logic;
fmc2_adc_sdo4_i : in std_logic;
fmc2_adc_busy_cmn_i : in std_logic;
fmc2_rng_r1_o : out std_logic;
fmc2_rng_r2_o : out std_logic;
fmc2_rng_r3_o : out std_logic;
fmc2_rng_r4_o : out std_logic;
fmc2_led1_o : out std_logic;
fmc2_led2_o : out std_logic;
-- Connected through FPGA MUX. Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
--fmc2_sm_scl_o : out std_logic;
--fmc2_sm_sda_b : inout std_logic;
fmc2_a_scl_o : out std_logic;
fmc2_a_sda_b : inout std_logic
);
end dbe_pbpm;
architecture rtl of dbe_pbpm is
---------------------------
-- Components --
---------------------------
component dbe_bpm_gen
generic(
g_fmc_adc_type : string := "FMC250M"
);
port(
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;
afc_fp2_clk1_p_i : in std_logic;
afc_fp2_clk1_n_i : in std_logic;
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0);
trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0);
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i : in std_logic := '0';
diag_spi_si_i : in std_logic := '0';
diag_spi_so_o : out std_logic;
diag_spi_clk_i : in std_logic := '0';
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o : out std_logic;
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b : inout std_logic;
afc_si57x_sda_b : inout std_logic;
-- Si57x oscillator output enable
afc_si57x_oe_o : out std_logic;
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b : inout std_logic;
board_i2c_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o : out std_logic;
-- spi_cs_n_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic := '0';
-----------------------------
-- FMC1_130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc130_1_adc_pga_o : out std_logic;
fmc130_1_adc_shdn_o : out std_logic;
fmc130_1_adc_dith_o : out std_logic;
fmc130_1_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc130_1_adc0_clk_i : in std_logic := '0';
fmc130_1_adc0_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc0_of_i : in std_logic := '0'; -- Unused
-- ADC1 LTC2208
fmc130_1_adc1_clk_i : in std_logic := '0';
fmc130_1_adc1_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc1_of_i : in std_logic := '0'; -- Unused
-- ADC2 LTC2208
fmc130_1_adc2_clk_i : in std_logic := '0';
fmc130_1_adc2_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc2_of_i : in std_logic := '0'; -- Unused
-- ADC3 LTC2208
fmc130_1_adc3_clk_i : in std_logic := '0';
fmc130_1_adc3_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc3_of_i : in std_logic := '0'; -- Unused
---- FMC General Status
--fmc130_1_prsnt_i : in std_logic := '0';
--fmc130_1_pg_m2c_i : in std_logic := '0';
--fmc130_1_clk_dir_i : in std_logic := '0';
-- Trigger
fmc130_1_trig_dir_o : out std_logic;
fmc130_1_trig_term_o : out std_logic;
fmc130_1_trig_val_p_b : inout std_logic;
fmc130_1_trig_val_n_b : inout std_logic;
-- Si571 clock gen
fmc130_1_si571_scl_pad_b : inout std_logic;
fmc130_1_si571_sda_pad_b : inout std_logic;
fmc130_1_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc130_1_spi_ad9510_cs_o : out std_logic;
fmc130_1_spi_ad9510_sclk_o : out std_logic;
fmc130_1_spi_ad9510_mosi_o : out std_logic;
fmc130_1_spi_ad9510_miso_i : in std_logic := '0';
fmc130_1_pll_function_o : out std_logic;
fmc130_1_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc130_1_fpga_clk_p_i : in std_logic := '0';
fmc130_1_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc130_1_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
fmc130_1_eeprom_scl_pad_b : inout std_logic;
fmc130_1_eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor (LM75AIMM)
fmc130_1_lm75_scl_pad_b : inout std_logic;
fmc130_1_lm75_sda_pad_b : inout std_logic;
fmc130_1_lm75_temp_alarm_i : in std_logic := '0';
-- FMC LEDs
fmc130_1_led1_o : out std_logic;
fmc130_1_led2_o : out std_logic;
fmc130_1_led3_o : out std_logic;
-----------------------------
-- FMC2_130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc130_2_adc_pga_o : out std_logic;
fmc130_2_adc_shdn_o : out std_logic;
fmc130_2_adc_dith_o : out std_logic;
fmc130_2_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc130_2_adc0_clk_i : in std_logic := '0';
fmc130_2_adc0_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc0_of_i : in std_logic := '0'; -- Unused
-- ADC1 LTC2208
fmc130_2_adc1_clk_i : in std_logic := '0';
fmc130_2_adc1_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc1_of_i : in std_logic := '0'; -- Unused
-- ADC2 LTC2208
fmc130_2_adc2_clk_i : in std_logic := '0';
fmc130_2_adc2_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc2_of_i : in std_logic := '0'; -- Unused
-- ADC3 LTC2208
fmc130_2_adc3_clk_i : in std_logic := '0';
fmc130_2_adc3_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc3_of_i : in std_logic := '0'; -- Unused
---- FMC General Status
--fmc130_2_prsnt_i : in std_logic := '0';
--fmc130_2_pg_m2c_i : in std_logic := '0';
--fmc130_2_clk_dir_i : in std_logic := '0';
-- Trigger
fmc130_2_trig_dir_o : out std_logic;
fmc130_2_trig_term_o : out std_logic;
fmc130_2_trig_val_p_b : inout std_logic;
fmc130_2_trig_val_n_b : inout std_logic;
-- Si571 clock gen
fmc130_2_si571_scl_pad_b : inout std_logic;
fmc130_2_si571_sda_pad_b : inout std_logic;
fmc130_2_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc130_2_spi_ad9510_cs_o : out std_logic;
fmc130_2_spi_ad9510_sclk_o : out std_logic;
fmc130_2_spi_ad9510_mosi_o : out std_logic;
fmc130_2_spi_ad9510_miso_i : in std_logic := '0';
fmc130_2_pll_function_o : out std_logic;
fmc130_2_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc130_2_fpga_clk_p_i : in std_logic := '0';
fmc130_2_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc130_2_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor (LM75AIMM)
fmc130_2_lm75_scl_pad_b : inout std_logic;
fmc130_2_lm75_sda_pad_b : inout std_logic;
fmc130_2_lm75_temp_alarm_i : in std_logic := '0';
-- FMC LEDs
fmc130_2_led1_o : out std_logic;
fmc130_2_led2_o : out std_logic;
fmc130_2_led3_o : out std_logic;
-----------------------------
-- FMC1_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_1_adc_clk_div_rst_p_o : out std_logic;
fmc250_1_adc_clk_div_rst_n_o : out std_logic;
fmc250_1_adc_ext_rst_n_o : out std_logic;
fmc250_1_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_1_adc_clk0_p_i : in std_logic := '0';
fmc250_1_adc_clk0_n_i : in std_logic := '0';
fmc250_1_adc_clk1_p_i : in std_logic := '0';
fmc250_1_adc_clk1_n_i : in std_logic := '0';
fmc250_1_adc_clk2_p_i : in std_logic := '0';
fmc250_1_adc_clk2_n_i : in std_logic := '0';
fmc250_1_adc_clk3_p_i : in std_logic := '0';
fmc250_1_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc250_1_adc_data_ch0_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch0_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch1_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch1_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch2_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch2_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch3_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch3_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc250_1_prsnt_i : in std_logic := '0';
--fmc250_1_pg_m2c_i : in std_logic := '0';
--fmc250_1_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_1_trig_dir_o : out std_logic;
fmc250_1_trig_term_o : out std_logic;
fmc250_1_trig_val_p_b : inout std_logic;
fmc250_1_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_1_adc_spi_clk_o : out std_logic;
fmc250_1_adc_spi_mosi_o : out std_logic;
fmc250_1_adc_spi_miso_i : in std_logic := '0';
fmc250_1_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc250_1_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc250_1_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc250_1_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc250_1_si571_scl_pad_b : inout std_logic;
fmc250_1_si571_sda_pad_b : inout std_logic;
fmc250_1_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc250_1_spi_ad9510_cs_o : out std_logic;
fmc250_1_spi_ad9510_sclk_o : out std_logic;
fmc250_1_spi_ad9510_mosi_o : out std_logic;
fmc250_1_spi_ad9510_miso_i : in std_logic := '0';
fmc250_1_pll_function_o : out std_logic;
fmc250_1_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc250_1_fpga_clk_p_i : in std_logic := '0';
fmc250_1_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc250_1_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
fmc250_1_eeprom_scl_pad_b : inout std_logic;
fmc250_1_eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_1_amc7823_spi_cs_o : out std_logic;
fmc250_1_amc7823_spi_sclk_o : out std_logic;
fmc250_1_amc7823_spi_mosi_o : out std_logic;
fmc250_1_amc7823_spi_miso_i : in std_logic := '0';
fmc250_1_amc7823_davn_i : in std_logic := '0';
-- FMC LEDs
fmc250_1_led1_o : out std_logic;
fmc250_1_led2_o : out std_logic;
fmc250_1_led3_o : out std_logic;
-----------------------------
-- FMC2_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_2_adc_clk_div_rst_p_o : out std_logic;
fmc250_2_adc_clk_div_rst_n_o : out std_logic;
fmc250_2_adc_ext_rst_n_o : out std_logic;
fmc250_2_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_2_adc_clk0_p_i : in std_logic := '0';
fmc250_2_adc_clk0_n_i : in std_logic := '0';
fmc250_2_adc_clk1_p_i : in std_logic := '0';
fmc250_2_adc_clk1_n_i : in std_logic := '0';
fmc250_2_adc_clk2_p_i : in std_logic := '0';
fmc250_2_adc_clk2_n_i : in std_logic := '0';
fmc250_2_adc_clk3_p_i : in std_logic := '0';
fmc250_2_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc250_2_adc_data_ch0_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch0_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch1_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch1_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch2_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch2_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch3_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch3_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc250_2_prsnt_i : in std_logic := '0';
--fmc250_2_pg_m2c_i : in std_logic := '0';
--fmc250_2_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_2_trig_dir_o : out std_logic;
fmc250_2_trig_term_o : out std_logic;
fmc250_2_trig_val_p_b : inout std_logic;
fmc250_2_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_2_adc_spi_clk_o : out std_logic;
fmc250_2_adc_spi_mosi_o : out std_logic;
fmc250_2_adc_spi_miso_i : in std_logic := '0';
fmc250_2_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc250_2_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc250_2_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc250_2_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc250_2_si571_scl_pad_b : inout std_logic;
fmc250_2_si571_sda_pad_b : inout std_logic;
fmc250_2_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc250_2_spi_ad9510_cs_o : out std_logic;
fmc250_2_spi_ad9510_sclk_o : out std_logic;
fmc250_2_spi_ad9510_mosi_o : out std_logic;
fmc250_2_spi_ad9510_miso_i : in std_logic := '0';
fmc250_2_pll_function_o : out std_logic;
fmc250_2_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc250_2_fpga_clk_p_i : in std_logic := '0';
fmc250_2_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc250_2_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_2_amc7823_spi_cs_o : out std_logic;
fmc250_2_amc7823_spi_sclk_o : out std_logic;
fmc250_2_amc7823_spi_mosi_o : out std_logic;
fmc250_2_amc7823_spi_miso_i : in std_logic := '0';
fmc250_2_amc7823_davn_i : in std_logic := '0';
-- FMC LEDs
fmc250_2_led1_o : out std_logic;
fmc250_2_led2_o : out std_logic;
fmc250_2_led3_o : out std_logic;
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_1_adc_cnv_o : out std_logic;
fmcpico_1_adc_sck_o : out std_logic;
fmcpico_1_adc_sck_rtrn_i : in std_logic := '0';
fmcpico_1_adc_sdo1_i : in std_logic := '0';
fmcpico_1_adc_sdo2_i : in std_logic := '0';
fmcpico_1_adc_sdo3_i : in std_logic := '0';
fmcpico_1_adc_sdo4_i : in std_logic := '0';
fmcpico_1_adc_busy_cmn_i : in std_logic := '0';
fmcpico_1_rng_r1_o : out std_logic;
fmcpico_1_rng_r2_o : out std_logic;
fmcpico_1_rng_r3_o : out std_logic;
fmcpico_1_rng_r4_o : out std_logic;
fmcpico_1_led1_o : out std_logic;
fmcpico_1_led2_o : out std_logic;
fmcpico_1_sm_scl_o : out std_logic;
fmcpico_1_sm_sda_b : inout std_logic;
fmcpico_1_a_scl_o : out std_logic;
fmcpico_1_a_sda_b : inout std_logic;
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_2_adc_cnv_o : out std_logic;
fmcpico_2_adc_sck_o : out std_logic;
fmcpico_2_adc_sck_rtrn_i : in std_logic := '0';
fmcpico_2_adc_sdo1_i : in std_logic := '0';
fmcpico_2_adc_sdo2_i : in std_logic := '0';
fmcpico_2_adc_sdo3_i : in std_logic := '0';
fmcpico_2_adc_sdo4_i : in std_logic := '0';
fmcpico_2_adc_busy_cmn_i : in std_logic := '0';
fmcpico_2_rng_r1_o : out std_logic;
fmcpico_2_rng_r2_o : out std_logic;
fmcpico_2_rng_r3_o : out std_logic;
fmcpico_2_rng_r4_o : out std_logic;
fmcpico_2_led1_o : out std_logic;
fmcpico_2_led2_o : out std_logic;
---- Connected through FPGA MUX.
--fmcpico_2_sm_scl_o : out std_logic;
--fmcpico_2_sm_sda_b : inout std_logic;
fmcpico_2_a_scl_o : out std_logic;
fmcpico_2_a_sda_b : inout std_logic
);
end component;
begin
cmp_dbe_bpm_gen : dbe_bpm_gen
generic map (
g_fmc_adc_type => "FMCPICO_1M"
)
port map (
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
aux_clk_p_i => aux_clk_p_i,
aux_clk_n_i => aux_clk_n_i,
afc_fp2_clk1_p_i => afc_fp2_clk1_p_i,
afc_fp2_clk1_n_i => afc_fp2_clk1_n_i,
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i => sys_rst_button_n_i,
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o => trig_dir_o,
trig_b => trig_b,
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i => diag_spi_cs_i,
diag_spi_si_i => diag_spi_si_i,
diag_spi_so_o => diag_spi_so_o,
diag_spi_clk_i => diag_spi_clk_i,
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o => adn4604_vadj2_clk_updt_n_o,
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b => afc_si57x_scl_b,
afc_si57x_sda_b => afc_si57x_sda_b,
-- Si57x oscillator output enable
afc_si57x_oe_o => afc_si57x_oe_o,
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- PCI clock and reset signals
pcie_clk_p_i => pcie_clk_p_i,
pcie_clk_n_i => pcie_clk_n_i,
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o => leds_o,
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b => board_i2c_scl_b,
board_i2c_sda_b => board_i2c_sda_b,
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o => spi_sclk_o,
-- spi_cs_n_o => spi_cs_n_o,
-- spi_mosi_o => spi_mosi_o,
-- spi_miso_i => spi_miso_i,
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_1_adc_cnv_o => fmc1_adc_cnv_o,
fmcpico_1_adc_sck_o => fmc1_adc_sck_o,
fmcpico_1_adc_sck_rtrn_i => fmc1_adc_sck_rtrn_i,
fmcpico_1_adc_sdo1_i => fmc1_adc_sdo1_i,
fmcpico_1_adc_sdo2_i => fmc1_adc_sdo2_i,
fmcpico_1_adc_sdo3_i => fmc1_adc_sdo3_i,
fmcpico_1_adc_sdo4_i => fmc1_adc_sdo4_i,
fmcpico_1_adc_busy_cmn_i => fmc1_adc_busy_cmn_i,
fmcpico_1_rng_r1_o => fmc1_rng_r1_o,
fmcpico_1_rng_r2_o => fmc1_rng_r2_o,
fmcpico_1_rng_r3_o => fmc1_rng_r3_o,
fmcpico_1_rng_r4_o => fmc1_rng_r4_o,
fmcpico_1_led1_o => fmc1_led1_o,
fmcpico_1_led2_o => fmc1_led2_o,
---- Connected through FPGA MUX. Use board I2C, if needed
--fmcpico_1_sm_scl_o => fmc1_sm_scl_o,
--fmcpico_1_sm_sda_b => fmc1_sm_sda_b,
fmcpico_1_a_scl_o => fmc1_a_scl_o,
fmcpico_1_a_sda_b => fmc1_a_sda_b,
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_2_adc_cnv_o => fmc2_adc_cnv_o,
fmcpico_2_adc_sck_o => fmc2_adc_sck_o,
fmcpico_2_adc_sck_rtrn_i => fmc2_adc_sck_rtrn_i,
fmcpico_2_adc_sdo1_i => fmc2_adc_sdo1_i,
fmcpico_2_adc_sdo2_i => fmc2_adc_sdo2_i,
fmcpico_2_adc_sdo3_i => fmc2_adc_sdo3_i,
fmcpico_2_adc_sdo4_i => fmc2_adc_sdo4_i,
fmcpico_2_adc_busy_cmn_i => fmc2_adc_busy_cmn_i,
fmcpico_2_rng_r1_o => fmc2_rng_r1_o,
fmcpico_2_rng_r2_o => fmc2_rng_r2_o,
fmcpico_2_rng_r3_o => fmc2_rng_r3_o,
fmcpico_2_rng_r4_o => fmc2_rng_r4_o,
fmcpico_2_led1_o => fmc2_led1_o,
fmcpico_2_led2_o => fmc2_led2_o,
-- Connected through FPGA MUX. Use board I2C, if needed
--fmcpico_2_sm_scl_o => fmc2_sm_scl_o,
--fmcpico_2_sm_sda_b => fmc2_sm_sda_b,
fmcpico_2_a_scl_o => fmc2_a_scl_o,
fmcpico_2_a_sda_b => fmc2_a_sda_b
);
end rtl;
|
lgpl-3.0
|
931d26e0d7049d23c28eaced434b8608
| 0.362691 | 3.940175 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_clk_pll_s8_diff.vhd
| 1 | 19,965 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_pll_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n clock receiver modulefor serdes factors
-- from 2 to 8
-- Instantiates necessary clock buffers and PLL
-- Contains state machine to calibrate clock input delay line,
-- and perform bitslip if required.
-- Takes in 1 bit of differential data and deserialises this to
-- n bits for where this data is required
-- data is received LSB first
-- 0, 1, 2 ......
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_clk_pll_s8_diff is generic (
PLLD : integer := 1 ; -- Parameter to set division for PLL
PLLX : integer := 2 ; -- Parameter to set multiplier for PLL (7 for video links, 2 for DDR etc)
CLKIN_PERIOD : real := 6.000 ; -- clock period (ns) of input clock on clkin_p
S : integer := 7 ; -- Parameter to set the serdes factor 1..8
BS : boolean := FALSE ; -- Parameter to enable bitslip TRUE or FALSE
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic ; -- Input from LVDS receiver pin
clkin_n : in std_logic ; -- Input from LVDS receiver pin
reset : in std_logic ; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0) ; -- Data to define pattern that bitslip should search for
pattern2 : in std_logic_vector(S-1 downto 0) ; -- Data to define alternate pattern that bitslip should search for
rxioclk : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_pll_x1 : out std_logic ; -- Global clock
rx_pll_lckd : out std_logic ; -- PLL locked - only used if a 2nd BUFPLL is required
rx_pllout_xs : out std_logic ; -- Multiplied PLL clock - only used if a 2nd BUFPLL is required
bitslip : out std_logic ; -- Bitslip control line
datain : out std_logic_vector(S-1 downto 0) ; -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end serdes_1_to_n_clk_pll_s8_diff ;
architecture arch_serdes_1_to_n_clk_pll_s8_diff of serdes_1_to_n_clk_pll_s8_diff is
signal P_clk : std_logic; -- P clock out to BUFIO2
signal buf_pll_fb_clk : std_logic; -- PLL feedback clock into BUFIOFB
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal mdataout : std_logic_vector(7 downto 0) ; --
signal cascade : std_logic ; --
signal pd_edge : std_logic ; --
signal busys : std_logic ; --
signal busym : std_logic ; --
signal rx_clk_in : std_logic ; --
signal feedback : std_logic ; --
signal buf_P_clk : std_logic ; --
signal iob_data_in : std_logic ; --
signal rx_bufg_pll_x1_int : std_logic ;
signal rxioclk_int : std_logic ;
signal rx_serdesstrobe_int : std_logic ;
signal rx_pllout_xs_int : std_logic ;
signal rx_pllout_x1 : std_logic ;
signal rx_pll_lckd_int : std_logic ;
signal state : integer range 0 to 9 ;
signal bslip : std_logic ;
signal count : std_logic_vector(2 downto 0) ;
signal busyd : std_logic ;
signal counter : std_logic_vector(11 downto 0) ;
signal clk_iserdes_data : std_logic_vector(S-1 downto 0) ;
signal cal_clk : std_logic ;
signal rst_clk : std_logic ;
signal rx_bufplllckd : std_logic ;
signal not_rx_bufpll_lckd : std_logic ;
signal busy_clk : std_logic ;
signal enable : std_logic ;
constant RX_SWAP_CLK : std_logic := '0' ; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
rx_bufg_pll_x1 <= rx_bufg_pll_x1_int ;
rxioclk <= rxioclk_int ;
rx_serdesstrobe <= rx_serdesstrobe_int ;
rx_pllout_xs <= rx_pllout_xs_int ;
rx_pll_lckd <= rx_pll_lckd_int ;
bitslip <= bslip ;
iob_clk_in : IBUFDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => rx_clk_in);
iob_data_in <= rx_clk_in xor RX_SWAP_CLK ; -- Invert clock as required
busy_clk <= busym ;
datain <= clk_iserdes_data ;
-- Bitslip and CAL state machine
process (rx_bufg_pll_x1_int, not_rx_bufpll_lckd)
begin
if not_rx_bufpll_lckd = '1' then
state <= 0 ;
enable <= '0' ;
cal_clk <= '0' ;
rst_clk <= '0' ;
bslip <= '0' ;
busyd <= '1' ;
counter <= "000000000000" ;
elsif rx_bufg_pll_x1_int'event and rx_bufg_pll_x1_int = '1' then
busyd <= busy_clk ;
if counter(5) = '1' then
enable <= '1' ;
end if ;
if counter(11) = '1' then
state <= 0 ;
cal_clk <= '0' ;
rst_clk <= '0' ;
bslip <= '0' ;
busyd <= '1' ;
counter <= "000000000000" ;
else
counter <= counter + 1 ;
if state = 0 and enable = '1' and busyd = '0' then
state <= 1 ;
elsif state = 1 then -- cal high
cal_clk <= '1' ; state <= 2 ;
elsif state = 2 and busyd = '1' then -- wait for busy high
cal_clk <= '0' ; state <= 3 ; -- cal low
elsif state = 3 and busyd = '0' then -- wait for busy low
rst_clk <= '1' ; state <= 4 ; -- rst high
elsif state = 4 then -- rst low
rst_clk <= '0' ; state <= 5 ;
elsif state = 5 and busyd = '0' then -- wait for busy low
state <= 6 ;
count <= "000" ;
elsif state = 6 then -- hang around
count <= count + 1 ;
if count = "111" then
state <= 7 ;
end if ;
elsif state = 7 then
if BS = TRUE and clk_iserdes_data /= pattern1 and clk_iserdes_data /= pattern2 then
bslip <= '1' ; -- bitslip needed
state <= 8 ;
count <= "000" ;
else
state <= 9 ;
end if ;
elsif state = 8 then
bslip <= '0' ; -- bitslip low
count <= count + 1 ;
if count = "111" then
state <= 7 ;
end if ;
elsif state = 9 then -- repeat after a delay
state <= 9 ;
end if ;
end if ;
end if ;
end process ;
loop0 : for i in 0 to (S - 1) generate -- Limit the output data bus to the most significant 'S' number of bits
clk_iserdes_data(i) <= mdataout(8+i-S) ;
end generate ;
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN" ) -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk_int, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => rx_bufg_pll_x1_int, -- Fabric clock (GCLK) for control signals
CAL => cal_clk, -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => rst_clk, -- Reset delay line to 1/2 max in this case
BUSY => busym) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- <DEFAULT>, FIXED, VARIABLE
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from slave IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate control signal, never needed as the slave supplies the clock input to the PLL
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
P_clk_bufio2_inst : BUFIO2 generic map(
DIVIDE => 1, -- The DIVCLK divider divide-by value; default 1
DIVIDE_BYPASS => TRUE) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => P_clk, -- P_clk input from IDELAY
IOCLK => open, -- Output Clock
DIVCLK => buf_P_clk, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
P_clk_bufio2fb_inst : BUFIO2FB generic map(
DIVIDE_BYPASS => TRUE) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => feedback, -- PLL generated Clock
O => buf_pll_fb_clk) ; -- PLL Output Feedback Clock
iserdes_m : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting in BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => pd_edge,
BITSLIP => bslip,
FABRICOUT => open,
DFB => open,
CFB0 => open,
CFB1 => open,
Q4 => mdataout(7),
Q3 => mdataout(6),
Q2 => mdataout(5),
Q1 => mdataout(4),
VALID => open,
INCDEC => open,
SHIFTOUT => cascade);
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => cascade,
BITSLIP => bslip,
FABRICOUT => open,
DFB => P_clk,
CFB0 => feedback,
CFB1 => open,
Q4 => mdataout(3),
Q3 => mdataout(2),
Q2 => mdataout(1),
Q1 => mdataout(0),
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge);
rx_pll_adv_inst : PLL_ADV generic map(
BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized"
CLKFBOUT_MULT => PLLX, -- multiplication factor for all output clocks
CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks
CLKIN1_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1
CLKIN2_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin2
CLKOUT0_DIVIDE => 1, -- division factor for clkout0 (1 to 128)
CLKOUT0_DUTY_CYCLE => 0.5, -- duty cycle for clkout0 (0.01 to 0.99)
CLKOUT0_PHASE => 0.0, -- phase shift (degrees) for clkout0 (0.0 to 360.0)
CLKOUT1_DIVIDE => 1, -- division factor for clkout1 (1 to 128)
CLKOUT1_DUTY_CYCLE => 0.5, -- duty cycle for clkout1 (0.01 to 0.99)
CLKOUT1_PHASE => 0.0, -- phase shift (degrees) for clkout1 (0.0 to 360.0)
CLKOUT2_DIVIDE => S, -- division factor for clkout2 (1 to 128)
CLKOUT2_DUTY_CYCLE => 0.5, -- duty cycle for clkout2 (0.01 to 0.99)
CLKOUT2_PHASE => 0.0, -- phase shift (degrees) for clkout2 (0.0 to 360.0)
CLKOUT3_DIVIDE => 7, -- division factor for clkout3 (1 to 128)
CLKOUT3_DUTY_CYCLE => 0.5, -- duty cycle for clkout3 (0.01 to 0.99)
CLKOUT3_PHASE => 0.0, -- phase shift (degrees) for clkout3 (0.0 to 360.0)
CLKOUT4_DIVIDE => 7, -- division factor for clkout4 (1 to 128)
CLKOUT4_DUTY_CYCLE => 0.5, -- duty cycle for clkout4 (0.01 to 0.99)
CLKOUT4_PHASE => 0.0, -- phase shift (degrees) for clkout4 (0.0 to 360.0)
CLKOUT5_DIVIDE => 7, -- division factor for clkout5 (1 to 128)
CLKOUT5_DUTY_CYCLE => 0.5, -- duty cycle for clkout5 (0.01 to 0.99)
CLKOUT5_PHASE => 0.0, -- phase shift (degrees) for clkout5 (0.0 to 360.0)
-- COMPENSATION => "SOURCE_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
DIVCLK_DIVIDE => PLLD, -- division factor for all clocks (1 to 52)
CLK_FEEDBACK => "CLKOUT0",
REF_JITTER => 0.100) -- input reference jitter (0.000 to 0.999 ui%)
port map (
CLKFBDCM => open, -- output feedback signal used when pll feeds a dcm
CLKFBOUT => open, -- general output feedback signal
CLKOUT0 => rx_pllout_xs_int, -- x7 clock for transmitter
CLKOUT1 => open,
CLKOUT2 => rx_pllout_x1, -- x1 clock for BUFG
CLKOUT3 => open, -- one of six general clock output signals
CLKOUT4 => open, -- one of six general clock output signals
CLKOUT5 => open, -- one of six general clock output signals
CLKOUTDCM0 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM1 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM2 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM3 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM4 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM5 => open, -- one of six clock outputs to connect to the dcm
DO => open, -- dynamic reconfig data output (16-bits)
DRDY => open, -- dynamic reconfig ready output
LOCKED => rx_pll_lckd_int, -- active high pll lock signal
CLKFBIN => buf_pll_fb_clk, -- clock feedback input
CLKIN1 => buf_P_clk, -- primary clock input
CLKIN2 => '0', -- secondary clock input
CLKINSEL => '1', -- selects '1' = clkin1, '0' = clkin2
DADDR => "00000", -- dynamic reconfig address input (5-bits)
DCLK => '0', -- dynamic reconfig clock input
DEN => '0', -- dynamic reconfig enable input
DI => "0000000000000000", -- dynamic reconfig data input (16-bits)
DWE => '0', -- dynamic reconfig write enable input
RST => reset, -- asynchronous pll reset
REL => '0') ; -- used to force the state of the PFD outputs (test only)
bufg_135 : BUFG port map (I => rx_pllout_x1, O => rx_bufg_pll_x1_int) ;
rx_bufpll_inst : BUFPLL generic map(
DIVIDE => S) -- PLLIN0 divide-by value to produce rx_serdesstrobe (1 to 8); default 1
port map (
PLLIN => rx_pllout_xs_int, -- PLL Clock input
GCLK => rx_bufg_pll_x1_int, -- Global Clock input
LOCKED => rx_pll_lckd_int, -- Clock0 locked input
IOCLK => rxioclk_int, -- Output PLL Clock
LOCK => rx_bufplllckd, -- BUFPLL Clock and strobe locked
serdesstrobe => rx_serdesstrobe_int) ; -- Output SERDES strobe
rx_bufpll_lckd <= rx_pll_lckd_int and rx_bufplllckd ;
not_rx_bufpll_lckd <= not (rx_pll_lckd_int and rx_bufplllckd) ;
end arch_serdes_1_to_n_clk_pll_s8_diff ;
|
apache-2.0
|
320c3b9e6c2c39a412f1c5fb4a73c86d
| 0.576659 | 3.192357 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_fmc516/clk_gen.vhd
| 9 | 1,499 |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
lgpl-3.0
|
49ef7c849ffe3d544033571fae54aed4
| 0.517678 | 4.095628 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/usb_system/altera_avalon_sc_fifo/_primary.vhd
| 2 | 2,919 |
library verilog;
use verilog.vl_types.all;
entity altera_avalon_sc_fifo is
generic(
SYMBOLS_PER_BEAT: integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
USE_STORE_FORWARD: integer := 0;
USE_ALMOST_FULL_IF: integer := 0;
USE_ALMOST_EMPTY_IF: integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS: integer := 1;
DATA_WIDTH : vl_notype;
EMPTY_WIDTH : vl_notype
);
port(
clk : in vl_logic;
reset : in vl_logic;
in_data : in vl_logic_vector;
in_valid : in vl_logic;
in_startofpacket: in vl_logic;
in_endofpacket : in vl_logic;
in_empty : in vl_logic_vector;
in_error : in vl_logic_vector;
in_channel : in vl_logic_vector;
in_ready : out vl_logic;
out_data : out vl_logic_vector;
out_valid : out vl_logic;
out_startofpacket: out vl_logic;
out_endofpacket : out vl_logic;
out_empty : out vl_logic_vector;
out_error : out vl_logic_vector;
out_channel : out vl_logic_vector;
out_ready : in vl_logic;
csr_address : in vl_logic_vector;
csr_write : in vl_logic;
csr_read : in vl_logic;
csr_writedata : in vl_logic_vector(31 downto 0);
csr_readdata : out vl_logic_vector(31 downto 0);
almost_full_data: out vl_logic;
almost_empty_data: out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of SYMBOLS_PER_BEAT : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_SYMBOL : constant is 1;
attribute mti_svvh_generic_type of FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of CHANNEL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of ERROR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of USE_PACKETS : constant is 1;
attribute mti_svvh_generic_type of USE_FILL_LEVEL : constant is 1;
attribute mti_svvh_generic_type of USE_STORE_FORWARD : constant is 1;
attribute mti_svvh_generic_type of USE_ALMOST_FULL_IF : constant is 1;
attribute mti_svvh_generic_type of USE_ALMOST_EMPTY_IF : constant is 1;
attribute mti_svvh_generic_type of EMPTY_LATENCY : constant is 1;
attribute mti_svvh_generic_type of USE_MEMORY_BLOCKS : constant is 1;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 3;
attribute mti_svvh_generic_type of EMPTY_WIDTH : constant is 3;
end altera_avalon_sc_fifo;
|
apache-2.0
|
b348d56b3e6443d209ef4934e1ee0857
| 0.581706 | 3.644195 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/uart/uart_core.vhd
| 1 | 10,634 |
-- Core for UART
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_core is
port(
clk_sys: in std_logic; --system clock
clk_uart: in std_logic; --uart clock (14,4?)
res: in std_logic; --reset
tx: out std_logic; --tx TLE pin
rx: in std_logic; --rx TLE pin
rx_data_output: out unsigned(7 downto 0); --rx data read from fifo
rx_data_count: out unsigned(5 downto 0); --byte count in fifo
rx_data_rdreq: in std_logic; --request read from rx fifo
tx_data_input: in unsigned(7 downto 0); --tx data write into fifo
tx_data_count: out unsigned(5 downto 0); --byte count in tx fifo
tx_data_wrreq: in std_logic; --request write into tx fifo
n: in unsigned(15 downto 0); --control signals
txen: in std_logic;
rxen: in std_logic;
tx_done: out std_logic; --byte sended
rx_done: out std_logic --byte recieved
);
end entity uart_core;
architecture uart_core_arch of uart_core is
component baudgen is
port(
clk: in std_logic;
res: in std_logic;
n: in unsigned(15 downto 0);
baud16_clk_en: out std_logic
);
end component baudgen;
component transmitter is
port(
en: in std_logic;
clk: in std_logic;
res: in std_logic;
baud16_clk_en: in std_logic;
tx_data: in unsigned(7 downto 0);
tx: out std_logic;
tx_dcfifo_rdreq: out std_logic;
tx_dcfifo_rdusedw: in std_logic_vector(5 downto 0);
tx_sended: out std_logic
);
end component transmitter;
component reciever is
port(
en: in std_logic;
clk: in std_logic;
res: in std_logic;
rx: in std_logic;
baud16_clk_en: in std_logic;
rx_data: out unsigned(7 downto 0);
rx_done: out std_logic
);
end component reciever;
component dcfifo is
generic(
intended_device_family: string;
lpm_numwords: natural;
lpm_showahead: string;
lpm_type: string;
lpm_width: natural;
lpm_widthu: natural;
overflow_checking: string;
rdsync_delaypipe: natural;
read_aclr_synch: string;
underflow_checking: string;
use_eab: string;
write_aclr_synch: string;
wrsync_delaypipe: natural;
add_usedw_msb_bit: string
);
port(
rdclk : in std_logic ;
q : out std_logic_vector (7 downto 0);
wrclk : in std_logic ;
wrreq : in std_logic ;
wrusedw : out std_logic_vector (5 downto 0);
aclr : in std_logic ;
data : in std_logic_vector (7 downto 0);
rdreq : in std_logic ;
rdusedw : out std_logic_vector (5 downto 0)
);
end component;
signal baud16_clk_en: std_logic;
signal rx_data: unsigned(7 downto 0);
signal rx_dcfifo_q: std_logic_vector(7 downto 0);
signal rx_dcfifo_rdusedw: std_logic_vector(5 downto 0);
signal tx_dcfifo_data: std_logic_vector(7 downto 0);
signal tx_dcfifo_wrusedw: std_logic_vector(5 downto 0);
signal tx_data: unsigned(7 downto 0);
signal tx_dcfifo_rdreq: std_logic;
signal tx_dcfifo_rdusedw: std_logic_vector(5 downto 0);
signal n_uart: unsigned(15 downto 0);
signal rx_dcfifo_data: std_logic_vector(7 downto 0);
signal tx_dcfifo_q: std_logic_vector(7 downto 0);
signal tx_en_sync, rx_en_sync: std_logic;
signal rx_done_uart, tx_done_uart: std_logic;
signal rx_done_raw, tx_done_raw: std_logic;
type statetype is (idle, come, waittocompleted);
signal tx_done_state: statetype;
signal rx_done_state: statetype;
begin
--clk_uart domain
baudgen0: baudgen
port map(clk_uart, res, n_uart, baud16_clk_en);
transmitter0: transmitter
port map(tx_en_sync, clk_uart, res, baud16_clk_en, tx_data, tx, tx_dcfifo_rdreq, tx_dcfifo_rdusedw, tx_done_uart);
reciever0: reciever
port map(rx_en_sync, clk_uart, res, rx, baud16_clk_en, rx_data, rx_done_uart);
rx_dcfifo_data <= std_logic_vector(rx_data);
tx_data <= unsigned(tx_dcfifo_q);
--crossing clk domains
rx_dcfifo : dcfifo
generic map (
intended_device_family => "cyclone iv e",
lpm_numwords => 32,
lpm_showahead => "off",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 6,
overflow_checking => "on",
rdsync_delaypipe => 4,
read_aclr_synch => "on",
underflow_checking => "on",
use_eab => "on",
write_aclr_synch => "on",
wrsync_delaypipe => 4,
add_usedw_msb_bit => "ON"
)
port map (
rdclk => clk_sys,
wrclk => clk_uart,
wrreq => rx_done_uart,
aclr => res,
data => rx_dcfifo_data,
rdreq => rx_data_rdreq,
q => rx_dcfifo_q,
wrusedw => open,
rdusedw => rx_dcfifo_rdusedw
);
tx_dcfifo : dcfifo
generic map (
intended_device_family => "cyclone iv e",
lpm_numwords => 32,
lpm_showahead => "off",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 6,
overflow_checking => "on",
rdsync_delaypipe => 4,
read_aclr_synch => "on",
underflow_checking => "on",
use_eab => "on",
write_aclr_synch => "on",
wrsync_delaypipe => 4,
add_usedw_msb_bit => "ON"
)
port map (
rdclk => clk_uart,
wrclk => clk_sys,
wrreq => tx_data_wrreq,
aclr => res,
data => tx_dcfifo_data,
rdreq => tx_dcfifo_rdreq,
q => tx_dcfifo_q,
wrusedw => tx_dcfifo_wrusedw,
rdusedw => tx_dcfifo_rdusedw
);
--from sys to uart
process(clk_uart) is
variable n_d1: unsigned(15 downto 0);
variable n_d2: unsigned(15 downto 0);
variable txen_1: std_logic;
variable txen_2: std_logic;
variable rxen_1: std_logic;
variable rxen_2: std_logic;
begin
if rising_edge(clk_uart) then
if res = '1' then
n_d1 := (others => '0');
n_d2 := (others => '0');
txen_1 := '0';
txen_2 := '0';
rxen_1 := '0';
rxen_2 := '0';
else
n_d2 := n_d1;
n_d1 := n;
txen_2 := txen_1;
txen_1 := txen;
rxen_2 := rxen_1;
rxen_1 := rxen;
end if;
end if;
n_uart <= n_d2;
rx_en_sync <= rxen_2;
tx_en_sync <= txen_2;
end process;
--from uart to sys
process(clk_sys) is
variable rx_done_1: std_logic;
variable rx_done_2: std_logic;
variable tx_done_1: std_logic;
variable tx_done_2: std_logic;
begin
if rising_edge(clk_sys) then
if res = '1' then
rx_done_2 := '0';
rx_done_1 := '0';
tx_done_2 := '0';
tx_done_1 := '0';
else
rx_done_2 := rx_done_1;
rx_done_1 := rx_done_uart;
tx_done_2 := tx_done_1;
tx_done_1 := tx_done_uart;
end if;
end if;
tx_done_raw <= tx_done_2;
rx_done_raw <= rx_done_2;
end process;
--sysclk domain
rx_data_output <= unsigned(rx_dcfifo_q);
rx_data_count <= unsigned(rx_dcfifo_rdusedw);
tx_dcfifo_data <= std_logic_vector(tx_data_input);
tx_data_count <= unsigned(tx_dcfifo_wrusedw);
process(clk_sys) is
begin
if(rising_edge(clk_sys)) then
if(res = '1') then
tx_done_state <= idle;
else
case tx_done_state is
when idle =>
if (tx_done_raw = '1') then
tx_done_state <= come;
else
tx_done_state <= idle;
end if;
when come => tx_done_state <= waittocompleted;
when waittocompleted =>
if(tx_done_raw = '1') then
tx_done_state <= waittocompleted;
else
tx_done_state <= idle;
end if;
end case;
end if;
end if;
end process;
process(tx_done_state) is
begin
case tx_done_state is
when idle => tx_done <= '0';
when come => tx_done <= '1';
when waittocompleted => tx_done <= '0';
end case;
end process;
process(clk_sys) is
begin
if(rising_edge(clk_sys)) then
if(res = '1') then
rx_done_state <= idle;
else
case rx_done_state is
when idle =>
if (rx_done_raw = '1') then
rx_done_state <= come;
else
rx_done_state <= idle;
end if;
when come => rx_done_state <= waittocompleted;
when waittocompleted =>
if(rx_done_raw = '1') then
rx_done_state <= waittocompleted;
else
rx_done_state <= idle;
end if;
end case;
end if;
end if;
end process;
process(rx_done_state) is
begin
case rx_done_state is
when idle => rx_done <= '0';
when come => rx_done <= '1';
when waittocompleted => rx_done <= '0';
end case;
end process;
end architecture uart_core_arch;
|
mit
|
5a0838c94a28828bdd621a6b4e2cc17c
| 0.477006 | 3.982397 | false | false | false | false |
Godoakos/conway-vhdl
|
ConwayFinal_tb.vhd
| 1 | 3,376 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:29:16 01/17/2015
-- Design Name:
-- Module Name: D:/Docs/Xilinx/ConwayFinal/ConwayFinal_tb.vhd
-- Project Name: ConwayFinal
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ConwayFinal
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ConwayFinal_tb IS
END ConwayFinal_tb;
ARCHITECTURE behavior OF ConwayFinal_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ConwayFinal
PORT(
clkin : IN std_logic;
dout : OUT std_logic_vector(7 downto 0);
hsync : OUT std_logic;
vsync : OUT std_logic
);
END COMPONENT;
--Inputs
signal clkin : std_logic := '0';
--Outputs
signal dout : std_logic_vector(7 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
-- Clock period definitions
constant clkin_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ConwayFinal PORT MAP (
clkin => clkin,
dout => dout,
hsync => hsync,
vsync => vsync
);
-- Clock process definitions
clkin_process :process
begin
clkin <= '0';
wait for clkin_period/2;
clkin <= '1';
wait for clkin_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clkin_period*10;
-- insert stimulus here
wait;
end process;
process (clkin)
file file_pointer: text is out "write.txt";
variable line_el: line;
begin
if rising_edge(clkin) then
-- Write the time
write(line_el, now); -- write the line.
write(line_el, ":"); -- write the line.
-- Write the hsync
write(line_el, " ");
write(line_el, hsync); -- write the line.
-- Write the vsync
write(line_el, " ");
write(line_el, vsync); -- write the line.
-- Write the red
write(line_el, " ");
write(line_el, dout(7 downto 5)); -- write the line.
-- Write the green
write(line_el, " ");
write(line_el, dout(5 downto 2)); -- write the line.
-- Write the blue
write(line_el, " ");
write(line_el, dout(2 downto 0)); -- write the line.
writeline(file_pointer, line_el); -- write the contents into the file.
end if;
end process;
END;
|
mit
|
c67c4d7ba7c6bde56537aecfdfb58686
| 0.565462 | 4 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd
| 1 | 25,998 |
------------------------------------------------------------------------------
-- Title : Wishbone Orbit Interlock Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2022-06-12
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone wrapper for orbit interlock
-------------------------------------------------------------------------------
-- Copyright (c) 2020 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2020-06-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Orbit interlock cores
use work.orbit_intlk_pkg.all;
-- Regs
use work.orbit_intlk_wbgen2_pkg.all;
entity wb_orbit_intlk is
generic
(
-- Wishbone
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_WITH_EXTRA_WB_REG : boolean := false;
-- Position
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_WISHBONE_ADDRESS_WIDTH-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_WISHBONE_DATA_WIDTH-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_WISHBONE_DATA_WIDTH-1 downto 0);
wb_sel_i : in std_logic_vector(c_WISHBONE_DATA_WIDTH/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic;
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_o : out std_logic
);
end wb_orbit_intlk;
architecture rtl of wb_orbit_intlk is
---------------------------------------------------------
-- Constants --
---------------------------------------------------------
constant c_PERIPH_ADDR_SIZE : natural := 4+2;
constant c_INTLK_LMT_WIDTH : natural := 32;
-----------------------------
-- Wishbone Register Interface signals
-----------------------------
-- wb_orbit_intlk reg structure
signal regs_in : t_orbit_intlk_in_registers;
signal regs_out : t_orbit_intlk_out_registers;
-----------------------------
-- Wishbone slave adapter signals/structures
-----------------------------
signal wb_slv_adp_out : t_wishbone_master_out;
signal wb_slv_adp_in : t_wishbone_master_in;
signal resized_addr : std_logic_vector(c_WISHBONE_ADDRESS_WIDTH-1 downto 0);
-----------------------------
-- Orbit Interlock signals
-----------------------------
signal intlk_en_reg : std_logic;
signal intlk_clr_reg : std_logic;
signal intlk_min_sum_en_reg : std_logic;
signal intlk_min_sum_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_trans_en_reg : std_logic;
signal intlk_trans_clr_reg : std_logic;
signal intlk_trans_max_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_trans_max_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_trans_min_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_trans_min_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_ang_en_reg : std_logic;
signal intlk_ang_clr_reg : std_logic;
signal intlk_ang_max_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_ang_max_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_ang_min_x_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_ang_min_y_reg : std_logic_vector(c_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_trans_bigger_x : std_logic;
signal intlk_trans_bigger_y : std_logic;
signal intlk_trans_bigger_ltc_x : std_logic;
signal intlk_trans_bigger_ltc_y : std_logic;
signal intlk_trans_bigger_any : std_logic;
signal intlk_trans_bigger_ltc : std_logic;
signal intlk_trans_bigger : std_logic;
signal intlk_trans_smaller_x : std_logic;
signal intlk_trans_smaller_y : std_logic;
signal intlk_trans_smaller_ltc_x : std_logic;
signal intlk_trans_smaller_ltc_y : std_logic;
signal intlk_trans_smaller_any : std_logic;
signal intlk_trans_smaller_ltc : std_logic;
signal intlk_trans_smaller : std_logic;
signal intlk_ang_bigger_x : std_logic;
signal intlk_ang_bigger_y : std_logic;
signal intlk_ang_bigger_ltc_x : std_logic;
signal intlk_ang_bigger_ltc_y : std_logic;
signal intlk_ang_bigger_any : std_logic;
signal intlk_ang_bigger_ltc : std_logic;
signal intlk_ang_bigger : std_logic;
signal intlk_ang_smaller_x : std_logic;
signal intlk_ang_smaller_y : std_logic;
signal intlk_ang_smaller_ltc_x : std_logic;
signal intlk_ang_smaller_ltc_y : std_logic;
signal intlk_ang_smaller_any : std_logic;
signal intlk_ang_smaller_ltc : std_logic;
signal intlk_ang_smaller : std_logic;
signal intlk : std_logic;
signal intlk_ltc : std_logic;
component wb_orbit_intlk_regs
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
regs_i : in t_orbit_intlk_in_registers;
regs_o : out t_orbit_intlk_out_registers
);
end component;
begin
-----------------------------
-- Slave adapter for Wishbone Register Interface
-----------------------------
cmp_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_INTERFACE_MODE,
g_slave_granularity => g_ADDRESS_GRANULARITY
)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
master_i => wb_slv_adp_in,
master_o => wb_slv_adp_out,
sl_adr_i => resized_addr,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_rty_o => open,
sl_err_o => open,
sl_stall_o => wb_stall_o
);
-- See wb_orbit_intlk_port.vhd for register bank addresses.
resized_addr(c_periph_addr_size-1 downto 0) <= wb_adr_i(c_periph_addr_size-1 downto 0);
resized_addr(c_wishbone_address_width-1 downto c_PERIPH_ADDR_SIZE) <= (others => '0');
-- Register Bank / Wishbone Interface
cmp_wb_orbit_intlk_regs : wb_orbit_intlk_regs
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_slv_adp_out.adr(3 downto 0),
wb_dat_i => wb_slv_adp_out.dat,
wb_dat_o => wb_slv_adp_in.dat,
wb_cyc_i => wb_slv_adp_out.cyc,
wb_sel_i => wb_slv_adp_out.sel,
wb_stb_i => wb_slv_adp_out.stb,
wb_we_i => wb_slv_adp_out.we,
wb_ack_o => wb_slv_adp_in.ack,
wb_stall_o => wb_slv_adp_in.stall,
fs_clk_i => ref_clk_i,
regs_i => regs_in,
regs_o => regs_out
);
-- Registers assignment
intlk_en_reg <= regs_out.ctrl_en_o;
intlk_clr_reg <= regs_out.ctrl_clr_o;
intlk_min_sum_en_reg <= regs_out.ctrl_min_sum_en_o;
intlk_min_sum_reg <= regs_out.min_sum_o;
intlk_trans_en_reg <= regs_out.ctrl_trans_en_o;
intlk_trans_clr_reg <= regs_out.ctrl_trans_clr_o;
intlk_trans_max_x_reg <= regs_out.trans_max_x_o;
intlk_trans_max_y_reg <= regs_out.trans_max_y_o;
intlk_trans_min_x_reg <= regs_out.trans_min_x_o;
intlk_trans_min_y_reg <= regs_out.trans_min_y_o;
intlk_ang_en_reg <= regs_out.ctrl_ang_en_o;
intlk_ang_clr_reg <= regs_out.ctrl_ang_clr_o;
intlk_ang_max_x_reg <= regs_out.ang_max_x_o;
intlk_ang_max_y_reg <= regs_out.ang_max_y_o;
intlk_ang_min_x_reg <= regs_out.ang_min_x_o;
intlk_ang_min_y_reg <= regs_out.ang_min_y_o;
regs_in.sts_trans_bigger_x_i <= intlk_trans_bigger_x;
regs_in.sts_trans_bigger_y_i <= intlk_trans_bigger_y;
regs_in.sts_trans_bigger_ltc_x_i <= intlk_trans_bigger_ltc_x;
regs_in.sts_trans_bigger_ltc_y_i <= intlk_trans_bigger_ltc_y;
regs_in.sts_trans_bigger_any_i <= intlk_trans_bigger_any;
regs_in.sts_trans_bigger_ltc_i <= intlk_trans_bigger_ltc;
regs_in.sts_trans_bigger_i <= intlk_trans_bigger;
regs_in.sts_trans_smaller_x_i <= intlk_trans_smaller_x;
regs_in.sts_trans_smaller_y_i <= intlk_trans_smaller_y;
regs_in.sts_trans_smaller_ltc_x_i <= intlk_trans_smaller_ltc_x;
regs_in.sts_trans_smaller_ltc_y_i <= intlk_trans_smaller_ltc_y;
regs_in.sts_trans_smaller_any_i <= intlk_trans_smaller_any;
regs_in.sts_trans_smaller_ltc_i <= intlk_trans_smaller_ltc;
regs_in.sts_trans_smaller_i <= intlk_trans_smaller;
regs_in.sts_ang_bigger_x_i <= intlk_ang_bigger_x;
regs_in.sts_ang_bigger_y_i <= intlk_ang_bigger_y;
regs_in.sts_ang_bigger_ltc_x_i <= intlk_ang_bigger_ltc_x;
regs_in.sts_ang_bigger_ltc_y_i <= intlk_ang_bigger_ltc_y;
regs_in.sts_ang_bigger_any_i <= intlk_ang_bigger_any;
regs_in.sts_ang_bigger_ltc_i <= intlk_ang_bigger_ltc;
regs_in.sts_ang_bigger_i <= intlk_ang_bigger;
regs_in.sts_ang_smaller_x_i <= intlk_ang_smaller_x;
regs_in.sts_ang_smaller_y_i <= intlk_ang_smaller_y;
regs_in.sts_ang_smaller_ltc_x_i <= intlk_ang_smaller_ltc_x;
regs_in.sts_ang_smaller_ltc_y_i <= intlk_ang_smaller_ltc_y;
regs_in.sts_ang_smaller_any_i <= intlk_ang_smaller_any;
regs_in.sts_ang_smaller_ltc_i <= intlk_ang_smaller_ltc;
regs_in.sts_ang_smaller_i <= intlk_ang_smaller;
regs_in.sts_intlk_i <= intlk;
regs_in.sts_intlk_ltc_i <= intlk_ltc;
-- Unused wishbone signals
wb_slv_adp_in.err <= '0';
wb_slv_adp_in.rty <= '0';
cmp_orbit_intlk : orbit_intlk
generic map
(
g_ADC_WIDTH => g_ADC_WIDTH,
g_DECIM_WIDTH => g_DECIM_WIDTH,
g_INTLK_LMT_WIDTH => c_INTLK_LMT_WIDTH
)
port map
(
-----------------------------
-- Clocks and resets
-----------------------------
ref_rst_n_i => ref_rst_n_i,
ref_clk_i => ref_clk_i,
-----------------------------
-- Interlock enable and limits signals
-----------------------------
intlk_en_i => intlk_en_reg,
intlk_clr_i => intlk_clr_reg,
-- Minimum threshold interlock on/off
intlk_min_sum_en_i => intlk_min_sum_en_reg,
-- Minimum threshold to interlock
intlk_min_sum_i => intlk_min_sum_reg,
-- Translation interlock on/off
intlk_trans_en_i => intlk_trans_en_reg,
-- Translation interlock clear
intlk_trans_clr_i => intlk_trans_clr_reg,
intlk_trans_max_x_i => intlk_trans_max_x_reg,
intlk_trans_max_y_i => intlk_trans_max_y_reg,
intlk_trans_min_x_i => intlk_trans_min_x_reg,
intlk_trans_min_y_i => intlk_trans_min_y_reg,
-- Angular interlock on/off
intlk_ang_en_i => intlk_ang_en_reg,
-- Angular interlock clear
intlk_ang_clr_i => intlk_ang_clr_reg,
intlk_ang_max_x_i => intlk_ang_max_x_reg,
intlk_ang_max_y_i => intlk_ang_max_y_reg,
intlk_ang_min_x_i => intlk_ang_min_x_reg,
intlk_ang_min_y_i => intlk_ang_min_y_reg,
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i => fs_clk_ds_i,
adc_ds_ch0_swap_i => adc_ds_ch0_swap_i,
adc_ds_ch1_swap_i => adc_ds_ch1_swap_i,
adc_ds_ch2_swap_i => adc_ds_ch2_swap_i,
adc_ds_ch3_swap_i => adc_ds_ch3_swap_i,
adc_ds_tag_i => adc_ds_tag_i,
adc_ds_swap_valid_i => adc_ds_swap_valid_i,
decim_ds_pos_x_i => decim_ds_pos_x_i,
decim_ds_pos_y_i => decim_ds_pos_y_i,
decim_ds_pos_q_i => decim_ds_pos_q_i,
decim_ds_pos_sum_i => decim_ds_pos_sum_i,
decim_ds_pos_valid_i => decim_ds_pos_valid_i,
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i => fs_clk_us_i,
adc_us_ch0_swap_i => adc_us_ch0_swap_i,
adc_us_ch1_swap_i => adc_us_ch1_swap_i,
adc_us_ch2_swap_i => adc_us_ch2_swap_i,
adc_us_ch3_swap_i => adc_us_ch3_swap_i,
adc_us_tag_i => adc_us_tag_i,
adc_us_swap_valid_i => adc_us_swap_valid_i,
decim_us_pos_x_i => decim_us_pos_x_i,
decim_us_pos_y_i => decim_us_pos_y_i,
decim_us_pos_q_i => decim_us_pos_q_i,
decim_us_pos_sum_i => decim_us_pos_sum_i,
decim_us_pos_valid_i => decim_us_pos_valid_i,
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o => intlk_trans_bigger_x,
intlk_trans_bigger_y_o => intlk_trans_bigger_y,
intlk_trans_bigger_ltc_x_o => intlk_trans_bigger_ltc_x,
intlk_trans_bigger_ltc_y_o => intlk_trans_bigger_ltc_y,
intlk_trans_bigger_any_o => intlk_trans_bigger_any,
intlk_trans_bigger_ltc_o => intlk_trans_bigger_ltc,
intlk_trans_bigger_o => intlk_trans_bigger,
intlk_trans_smaller_x_o => intlk_trans_smaller_x,
intlk_trans_smaller_y_o => intlk_trans_smaller_y,
intlk_trans_smaller_ltc_x_o => intlk_trans_smaller_ltc_x,
intlk_trans_smaller_ltc_y_o => intlk_trans_smaller_ltc_y,
intlk_trans_smaller_any_o => intlk_trans_smaller_any,
intlk_trans_smaller_ltc_o => intlk_trans_smaller_ltc,
intlk_trans_smaller_o => intlk_trans_smaller,
intlk_ang_bigger_x_o => intlk_ang_bigger_x,
intlk_ang_bigger_y_o => intlk_ang_bigger_y,
intlk_ang_bigger_ltc_x_o => intlk_ang_bigger_ltc_x,
intlk_ang_bigger_ltc_y_o => intlk_ang_bigger_ltc_y,
intlk_ang_bigger_any_o => intlk_ang_bigger_any,
intlk_ang_bigger_ltc_o => intlk_ang_bigger_ltc,
intlk_ang_bigger_o => intlk_ang_bigger,
intlk_ang_smaller_x_o => intlk_ang_smaller_x,
intlk_ang_smaller_y_o => intlk_ang_smaller_y,
intlk_ang_smaller_ltc_x_o => intlk_ang_smaller_ltc_x,
intlk_ang_smaller_ltc_y_o => intlk_ang_smaller_ltc_y,
intlk_ang_smaller_any_o => intlk_ang_smaller_any,
intlk_ang_smaller_ltc_o => intlk_ang_smaller_ltc,
intlk_ang_smaller_o => intlk_ang_smaller,
intlk_ltc_o => intlk_ltc,
intlk_o => intlk
);
-- Output assignments
intlk_trans_bigger_x_o <= intlk_trans_bigger_x;
intlk_trans_bigger_y_o <= intlk_trans_bigger_y;
intlk_trans_bigger_ltc_x_o <= intlk_trans_bigger_ltc_x;
intlk_trans_bigger_ltc_y_o <= intlk_trans_bigger_ltc_y;
intlk_trans_bigger_any_o <= intlk_trans_bigger_any;
intlk_trans_bigger_ltc_o <= intlk_trans_bigger_ltc;
intlk_trans_bigger_o <= intlk_trans_bigger;
intlk_trans_smaller_x_o <= intlk_trans_smaller_x;
intlk_trans_smaller_y_o <= intlk_trans_smaller_y;
intlk_trans_smaller_ltc_x_o <= intlk_trans_smaller_ltc_x;
intlk_trans_smaller_ltc_y_o <= intlk_trans_smaller_ltc_y;
intlk_trans_smaller_any_o <= intlk_trans_smaller_any;
intlk_trans_smaller_ltc_o <= intlk_trans_smaller_ltc;
intlk_trans_smaller_o <= intlk_trans_smaller;
intlk_ang_bigger_x_o <= intlk_ang_bigger_x;
intlk_ang_bigger_y_o <= intlk_ang_bigger_y;
intlk_ang_bigger_ltc_x_o <= intlk_ang_bigger_ltc_x;
intlk_ang_bigger_ltc_y_o <= intlk_ang_bigger_ltc_y;
intlk_ang_bigger_any_o <= intlk_ang_bigger_any;
intlk_ang_bigger_ltc_o <= intlk_ang_bigger_ltc;
intlk_ang_bigger_o <= intlk_ang_bigger;
intlk_ang_smaller_x_o <= intlk_ang_smaller_x;
intlk_ang_smaller_y_o <= intlk_ang_smaller_y;
intlk_ang_smaller_ltc_x_o <= intlk_ang_smaller_ltc_x;
intlk_ang_smaller_ltc_y_o <= intlk_ang_smaller_ltc_y;
intlk_ang_smaller_any_o <= intlk_ang_smaller_any;
intlk_ang_smaller_ltc_o <= intlk_ang_smaller_ltc;
intlk_ang_smaller_o <= intlk_ang_smaller;
intlk_ltc_o <= intlk_ltc;
intlk_o <= intlk;
end rtl;
|
lgpl-3.0
|
09bd6e7d088c470a36ddaec7c9330a77
| 0.465613 | 3.595851 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/statements/IfStatementPartiallyEnclosed.vhd
| 1 | 1,068 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY IfStatementPartiallyEnclosed IS
PORT(
a : OUT STD_LOGIC;
b : OUT STD_LOGIC;
c : IN STD_LOGIC;
clk : IN STD_LOGIC;
d : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF IfStatementPartiallyEnclosed IS
SIGNAL a_reg : STD_LOGIC;
SIGNAL a_reg_next : STD_LOGIC;
SIGNAL b_reg : STD_LOGIC;
SIGNAL b_reg_next : STD_LOGIC;
BEGIN
a <= a_reg;
assig_process_a_reg_next: PROCESS(b_reg, c, d)
BEGIN
IF c = '1' THEN
a_reg_next <= '1';
b_reg_next <= '1';
ELSIF d = '1' THEN
a_reg_next <= '0';
b_reg_next <= b_reg;
ELSE
a_reg_next <= '1';
b_reg_next <= '1';
END IF;
END PROCESS;
b <= b_reg;
assig_process_b_reg: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
b_reg <= b_reg_next;
a_reg <= a_reg_next;
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
f98df15347a0ad53d8e7c7f44ce54ac5
| 0.514981 | 3.178571 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_data_s16_diff.vhd
| 1 | 16,663 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_data_s16_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic 1:n data receiver module with differential inputs
-- Takes in 1 bit of differential data and deserialises this to n bits
-- data is received LSB first
-- Serial input words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Parallel output word
-- DS, DS-1 ..... 1, 0
--
-- Includes state machine to control CAL and the phase detector
-- Data inversion can be accomplished via the RX_RX_SWAP_MASK parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_data_s16_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16 ; -- Set the number of inputs and outputs
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
use_phase_detector : in std_logic ; -- Set generation of phase detector logic
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclk : in std_logic ; -- IO Clock network
rx_serdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
rx_toggle : in std_logic ; -- control line
rx_bufg_pll_x1 : in std_logic ; -- Global clock
rx_bufg_pll_x2 : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
data_out : out std_logic_vector((D*S)-1 downto 0)) ; -- Output data
end serdes_1_to_n_data_s16_diff ;
architecture arch_serdes_1_to_n_data_s16_diff of serdes_1_to_n_data_s16_diff is
signal ddly_m : std_logic_vector(D-1 downto 0) ; -- Master output from IODELAY1
signal ddly_s : std_logic_vector(D-1 downto 0) ; -- Slave output from IODELAY1
signal cascade : std_logic_vector(D-1 downto 0) ;
signal busys : std_logic_vector(D-1 downto 0) ;
signal busym : std_logic_vector(D-1 downto 0) ;
signal rx_data_in : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_fix : std_logic_vector(D-1 downto 0) ;
signal state : integer range 0 to 8 ;
signal lows : std_logic_vector(D-1 downto 0) ;
signal highs : std_logic_vector(D-1 downto 0) ;
signal busyd : std_logic_vector(D-1 downto 0) ;
signal cal_data_sint : std_logic ;
signal busy_data : std_logic_vector(D-1 downto 0) ;
signal busy_data_d : std_logic ;
signal counter : std_logic_vector(8 downto 0) ;
signal enable : std_logic ;
signal pd_edge : std_logic_vector(D-1 downto 0) ;
signal cal_data_slave : std_logic ;
signal cal_data_master : std_logic ;
signal valid_data : std_logic_vector(D-1 downto 0) ;
signal valid_data_d : std_logic ;
signal rst_data : std_logic ;
signal mdataout : std_logic_vector((8*D)-1 downto 0) ;
signal pdcounter : std_logic_vector(4 downto 0) ;
signal inc_data : std_logic ;
signal ce_data : std_logic_vector(D-1 downto 0) ;
signal ce_data_inta : std_logic ;
signal inc_data_int : std_logic ;
signal incdec_data : std_logic_vector(D-1 downto 0) ;
signal incdec_data_d : std_logic ;
signal datah : std_logic_vector((D*S/2)-1 downto 0) ;
signal rxd : std_logic_vector((D*S/2)-1 downto 0) ;
signal datain : std_logic_vector((D*S)-1 downto 0) ;
signal flag : std_logic ;
signal mux : std_logic_vector(D-1 downto 0) ;
signal incdec_data_or : std_logic_vector(D downto 0) ;
signal valid_data_or : std_logic_vector(D downto 0) ;
signal busy_data_or : std_logic_vector(D downto 0) ;
signal incdec_data_im : std_logic_vector(D-1 downto 0) ;
signal valid_data_im : std_logic_vector(D-1 downto 0) ;
constant RX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
busy_data <= busys ;
data_out <= datain ;
cal_data_slave <= cal_data_sint ;
process (rx_bufg_pll_x1)
begin
if rx_bufg_pll_x1'event and rx_bufg_pll_x1 = '1' then
datain <= rxd & datah ;
end if ;
end process ;
process (rx_bufg_pll_x2)
begin
if rx_bufg_pll_x2'event and rx_bufg_pll_x2 = '1' then
if rx_toggle = '1' then
datah <= rxd ;
end if ;
end if ;
end process ;
process (rx_bufg_pll_x2, reset)
begin
if reset = '1' then
state <= 0 ;
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
counter <= (others => '0') ;
enable <= '0' ;
counter <= (others => '0') ;
mux <= (0 => '1', others => '0') ;
elsif rx_bufg_pll_x2'event and rx_bufg_pll_x2 = '1' then
counter <= counter + 1 ;
if counter(8) = '1' then
counter <= "000000000" ;
end if ;
if counter(5) = '1' then
enable <= '1' ;
end if ;
if state = 0 and enable = '1' then -- Wait for all IODELAYs to be available
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 1 ;
end if ;
elsif state = 1 then -- Issue calibrate command to both master and slave
cal_data_master <= '1' ;
cal_data_sint <= '1' ;
if busy_data_d = '1' then -- and wait for command to be accepted
state <= 2 ;
end if ;
elsif state = 2 then -- Now RST all master and slave IODELAYs
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
if busy_data_d = '0' then
rst_data <= '1' ;
state <= 3 ;
end if ;
elsif state = 3 then -- Wait for all IODELAYs to be available
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
elsif state = 4 then -- Hang around
if counter(8) = '1' then
state <= 5 ;
end if ;
elsif state = 5 then -- Calibrate slave only
if busy_data_d = '0' then
cal_data_sint <= '1' ;
state <= 6 ;
if D /= 1 then
mux <= mux(D-2 downto 0) & mux(D-1) ;
end if ;
end if ;
elsif state = 6 then -- Wait for command to be accepted
if busy_data_d = '1' then
cal_data_sint <= '0' ;
state <= 7 ;
end if ;
elsif state = 7 then -- Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
end if ;
end if ;
end process ;
process (rx_bufg_pll_x2, reset)
begin
if reset = '1' then
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
flag <= '0' ;
elsif rx_bufg_pll_x2'event and rx_bufg_pll_x2 = '1' then
busy_data_d <= busy_data_or(D) ;
if use_phase_detector = '1' then -- decide whether pd is used
incdec_data_d <= incdec_data_or(D) ;
valid_data_d <= valid_data_or(D) ;
if ce_data_inta = '1' then
ce_data <= mux ;
else
ce_data <= (others => '0') ;
end if ;
if state = 7 then
flag <= '0' ;
elsif state /= 4 or busy_data_d = '1' then -- Reset filter if state machine issues a cal command or unit is busy
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
elsif pdcounter = "11111" and flag = '0' then -- Filter has reached positive max - increment the tap count
ce_data_inta <= '1' ;
inc_data_int <= '1' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif pdcounter = "00000" and flag = '0' then -- Filter has reached negative max - decrement the tap count
ce_data_inta <= '1' ;
inc_data_int <= '0' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif valid_data_d = '1' then -- increment filter
ce_data_inta <= '0' ;
if incdec_data_d = '1' and pdcounter /= "11111" then
pdcounter <= pdcounter + 1 ;
elsif incdec_data_d = '0' and pdcounter /= "00000" then -- decrement filter
pdcounter <= pdcounter - 1 ;
end if ;
else
ce_data_inta <= '0' ;
end if ;
else
ce_data <= (others => '1') ;
inc_data_int <= '0' ;
end if ;
end if ;
end process ;
inc_data <= inc_data_int ;
incdec_data_or(0) <= '0' ; -- Input Mux - Initialise generate loop OR gates
valid_data_or(0) <= '0' ;
busy_data_or(0) <= '0' ;
loop0 : for i in 0 to (D - 1) generate
incdec_data_im(i) <= incdec_data(i) and mux(i) ; -- Input muxes
incdec_data_or(i+1) <= incdec_data_im(i) or incdec_data_or(i) ; -- AND gates to allow just one signal through at a tome
valid_data_im(i) <= valid_data(i) and mux(i) ; -- followed by an OR
valid_data_or(i+1) <= valid_data_im(i) or valid_data_or(i) ; -- for the three inputs from each PD
busy_data_or(i+1) <= busy_data(i) or busy_data_or(i) ; -- The busy signals just need an OR gate
rx_data_in_fix(i) <= rx_data_in(i) xor RX_SWAP_MASK(i) ; -- Invert signals as required
iob_clk_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => datain_p(i),
IB => datain_n(i),
O => rx_data_in(i));
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => rx_bufg_pll_x2, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busym(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND" , -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN" , -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => rx_bufg_pll_x2, -- Fabric clock (GCLK) for control signals
CAL => cal_data_slave, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i) , -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busys(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rx_serdesstrobe,
RST => reset,
CLKDIV => rx_bufg_pll_x2,
SHIFTIN => pd_edge(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => valid_data(i),
INCDEC => incdec_data(i),
SHIFTOUT => cascade(i));
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rx_serdesstrobe,
RST => reset,
CLKDIV => rx_bufg_pll_x2,
SHIFTIN => cascade(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+3),
Q3 => mdataout((8*i)+2),
Q2 => mdataout((8*i)+1),
Q1 => mdataout((8*i)+0),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge(i));
loop1 : for j in 7 downto (8-(S/2)) generate
rxd(((D*(j+(S/2)-8))+i)) <= mdataout((8*i)+j) ;
end generate ;
end generate ;
end arch_serdes_1_to_n_data_s16_diff ;
|
apache-2.0
|
74c5cedeb29f6ef764195fd9da7f1394
| 0.59113 | 2.938282 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/clk_gen.vhd
| 1 | 1,592 |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic;
sys_clk_bufg_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
sys_clk_o <= s_sys_clk;
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_bufg_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
lgpl-3.0
|
8bfee587f11f6e102d968717c8b41575
| 0.512563 | 4.020202 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/alt_dspbuilder_decoder_GNA3ETEQ66.vhd
| 3 | 901 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNA3ETEQ66 is
generic ( decode : string := "00";
pipeline : natural := 1;
width : natural := 2);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNA3ETEQ66 is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 2,
decode => "00",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture;
|
mit
|
25b430fe784485b761a6a6a3777c1a41
| 0.653718 | 2.906452 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/machine/sirius_sr_250M/dds_cos_lut.vhd
| 1 | 2,363 |
-------------------------------------------------------------------------------
-- Title : Vivado DDS cos lut for SIRIUS 250M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_cos_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-04-15
-- Last update: 2016-04-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Temporary cosine lut for SIRIUS machine with 250M ADC generated
-- through Vivado.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-04 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
entity dds_cos_lut is
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end entity dds_cos_lut;
architecture str of dds_cos_lut is
component generic_rom
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
begin
cmp_cos_lut_sirius_50_191_1 : generic_rom
generic map (
g_data_width => 16,
g_size => 191,
g_init_file => "cos_lut_sirius_50_191.mif",
g_fail_if_file_not_found => true
)
port map (
rst_n_i => '1',
clk_i => clka,
a_i => addra,
q_o => douta
);
end architecture str;
|
lgpl-3.0
|
cdb50eddecff7debea6a0cdf8967b553
| 0.404994 | 4.319927 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_orbit_intlk/xwb_orbit_intlk.vhd
| 1 | 12,771 |
------------------------------------------------------------------------------
-- Title : Wishbone Orbit Interlock Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2022-06-12
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone wrapper for orbit interlock
-------------------------------------------------------------------------------
-- Copyright (c) 2020 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2020-06-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Orbit interlock cores
use work.orbit_intlk_pkg.all;
-- BPM cores
use work.bpm_cores_pkg.all;
entity xwb_orbit_intlk is
generic
(
-- Wishbone
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_WITH_EXTRA_WB_REG : boolean := false;
-- Position
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic;
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_o : out std_logic
);
end xwb_orbit_intlk;
architecture rtl of xwb_orbit_intlk is
begin
cmp_wb_orbit_intlk : wb_orbit_intlk
generic map
(
-- Wishbone
g_INTERFACE_MODE => g_INTERFACE_MODE,
g_ADDRESS_GRANULARITY => g_ADDRESS_GRANULARITY,
g_WITH_EXTRA_WB_REG => g_WITH_EXTRA_WB_REG,
-- Position
g_ADC_WIDTH => g_ADC_WIDTH,
g_DECIM_WIDTH => g_DECIM_WIDTH
)
port map
(
-----------------------------
-- Clocks and resets
-----------------------------
rst_n_i => rst_n_i,
clk_i => clk_i,
ref_rst_n_i => ref_rst_n_i,
ref_clk_i => ref_clk_i,
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i => fs_clk_ds_i,
adc_ds_ch0_swap_i => adc_ds_ch0_swap_i,
adc_ds_ch1_swap_i => adc_ds_ch1_swap_i,
adc_ds_ch2_swap_i => adc_ds_ch2_swap_i,
adc_ds_ch3_swap_i => adc_ds_ch3_swap_i,
adc_ds_tag_i => adc_ds_tag_i,
adc_ds_swap_valid_i => adc_ds_swap_valid_i,
decim_ds_pos_x_i => decim_ds_pos_x_i,
decim_ds_pos_y_i => decim_ds_pos_y_i,
decim_ds_pos_q_i => decim_ds_pos_q_i,
decim_ds_pos_sum_i => decim_ds_pos_sum_i,
decim_ds_pos_valid_i => decim_ds_pos_valid_i,
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i => fs_clk_us_i,
adc_us_ch0_swap_i => adc_us_ch0_swap_i,
adc_us_ch1_swap_i => adc_us_ch1_swap_i,
adc_us_ch2_swap_i => adc_us_ch2_swap_i,
adc_us_ch3_swap_i => adc_us_ch3_swap_i,
adc_us_tag_i => adc_us_tag_i,
adc_us_swap_valid_i => adc_us_swap_valid_i,
decim_us_pos_x_i => decim_us_pos_x_i,
decim_us_pos_y_i => decim_us_pos_y_i,
decim_us_pos_q_i => decim_us_pos_q_i,
decim_us_pos_sum_i => decim_us_pos_sum_i,
decim_us_pos_valid_i => decim_us_pos_valid_i,
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o => intlk_trans_bigger_x_o,
intlk_trans_bigger_y_o => intlk_trans_bigger_y_o,
intlk_trans_bigger_ltc_x_o => intlk_trans_bigger_ltc_x_o,
intlk_trans_bigger_ltc_y_o => intlk_trans_bigger_ltc_y_o,
intlk_trans_bigger_any_o => intlk_trans_bigger_any_o,
intlk_trans_bigger_ltc_o => intlk_trans_bigger_ltc_o,
intlk_trans_bigger_o => intlk_trans_bigger_o,
intlk_trans_smaller_x_o => intlk_trans_smaller_x_o,
intlk_trans_smaller_y_o => intlk_trans_smaller_y_o,
intlk_trans_smaller_ltc_x_o => intlk_trans_smaller_ltc_x_o,
intlk_trans_smaller_ltc_y_o => intlk_trans_smaller_ltc_y_o,
intlk_trans_smaller_any_o => intlk_trans_smaller_any_o,
intlk_trans_smaller_ltc_o => intlk_trans_smaller_ltc_o,
intlk_trans_smaller_o => intlk_trans_smaller_o,
intlk_ang_bigger_x_o => intlk_ang_bigger_x_o,
intlk_ang_bigger_y_o => intlk_ang_bigger_y_o,
intlk_ang_bigger_ltc_x_o => intlk_ang_bigger_ltc_x_o,
intlk_ang_bigger_ltc_y_o => intlk_ang_bigger_ltc_y_o,
intlk_ang_bigger_any_o => intlk_ang_bigger_any_o,
intlk_ang_bigger_ltc_o => intlk_ang_bigger_ltc_o,
intlk_ang_bigger_o => intlk_ang_bigger_o,
intlk_ang_smaller_x_o => intlk_ang_smaller_x_o,
intlk_ang_smaller_y_o => intlk_ang_smaller_y_o,
intlk_ang_smaller_ltc_x_o => intlk_ang_smaller_ltc_x_o,
intlk_ang_smaller_ltc_y_o => intlk_ang_smaller_ltc_y_o,
intlk_ang_smaller_any_o => intlk_ang_smaller_any_o,
intlk_ang_smaller_ltc_o => intlk_ang_smaller_ltc_o,
intlk_ang_smaller_o => intlk_ang_smaller_o,
intlk_ltc_o => intlk_ltc_o,
intlk_o => intlk_o
);
end rtl;
|
lgpl-3.0
|
4ed16dc6b82768ed73978605b4d0a08d
| 0.423459 | 3.811101 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_bpm_swap/bpm_swap/swap_freqgen.vhd
| 1 | 5,421 |
------------------------------------------------------------------------------
-- Title : BPM RF channels swapping and de-swapping frequency generator
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Generate swap and de-swap signals for given swapping frequency
-- and de-swapping delay settings.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bpm_cores_pkg.all;
entity swap_freqgen is
generic(
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
sync_trig_i : in std_logic;
-- Swap and de-swap signals
swap_o : out std_logic;
deswap_o : out std_logic;
-- Swap mode setting
swap_mode_i : in t_swap_mode;
-- Swap frequency settings
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
swap_div_f_cnt_en_i : in std_logic := '1';
-- De-swap delay setting
deswap_delay_i : in std_logic_vector(g_delay_vec_width-1 downto 0)
);
end swap_freqgen;
architecture rtl of swap_freqgen is
component swmode_sel
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
clk_swap_i : in std_logic;
swap_mode_i : in t_swap_mode;
swap_o : out std_logic;
deswap_o : out std_logic
);
end component;
component gc_shiftreg
generic (
g_size : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic;
a_i : in std_logic_vector
);
end component;
signal count : natural range 0 to 2**g_swap_div_freq_vec_width-1;
signal cnst_swap_div_f_old : natural range 0 to 2**g_swap_div_freq_vec_width-1;
signal cnst_swap_div_f : natural range 0 to 2**g_swap_div_freq_vec_width-1;
signal clk_swap : std_logic;
signal deswap : std_logic;
signal synch_pending : std_logic;
begin
----------------------------------------------------------------
-- components instantiation
----------------------------------------------------------------
cmp_swmode_sel: swmode_sel
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
en_i => '1',
clk_swap_i => clk_swap,
swap_mode_i => swap_mode_i,
swap_o => swap_o,
deswap_o => deswap
);
cmp_gc_shiftreg: gc_shiftreg
generic map (
g_size => 2**g_delay_vec_width
)
port map (
clk_i => clk_i,
en_i => '1',
d_i => deswap,
q_o => deswap_o,
a_i => deswap_delay_i
);
----------------------------------------------------------------
-- RTL logic
----------------------------------------------------------------
p_reg_swap_div : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cnst_swap_div_f_old <= 0;
cnst_swap_div_f <= 0;
else
if en_i = '1' then
cnst_swap_div_f_old <= (to_integer(unsigned(swap_div_f_i))-1);
cnst_swap_div_f <= cnst_swap_div_f_old;
end if;
end if;
end if;
end process p_reg_swap_div;
p_freq_swap : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= 0;
clk_swap <= '1';
synch_pending <= '0';
else
if en_i = '1' then
-- Clear SW counter if we received a new SW divider period
-- This is important to ensure that we don't swap signals
-- between crossed antennas
if cnst_swap_div_f /= cnst_swap_div_f_old then
count <= 0;
clk_swap <= '1';
elsif swap_div_f_cnt_en_i = '1' then
if synch_pending = '1' then
count <= 0;
clk_swap <= '1';
synch_pending <= '0';
elsif count = cnst_swap_div_f then
count <= 0;
clk_swap <= not clk_swap;
else
count <= count + 1;
end if;
end if;
end if;
-- Clear SW counter on sync_trig regardless of en_i
if(sync_trig_i = '1' and -- sync trig arrived,
(count /= cnst_swap_div_f -- but no sync necessary
or clk_swap = '0')) then -- unless it's synchronized with a different phase, then reset it
synch_pending <= '1';
end if;
end if;
end if;
end process p_freq_swap;
end;
|
lgpl-3.0
|
a35e48518c8203d9dd04b72c675c1b8b
| 0.439771 | 3.82299 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_div/fp_div_sim/fp_div.vhd
| 1 | 86,872 |
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_div
-- VHDL created on Thu Feb 15 13:09:41 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_div is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(31 downto 0); -- float32_m23
clk : in std_logic;
areset : in std_logic
);
end fp_div;
architecture normal of fp_div is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstBiasM1_uid6_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal expX_uid9_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal fracX_uid10_fpDivTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal signX_uid11_fpDivTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal expY_uid12_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal fracY_uid13_fpDivTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal signY_uid14_fpDivTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal paddingY_uid15_fpDivTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal updatedY_uid16_fpDivTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal fracYZero_uid15_fpDivTest_a : STD_LOGIC_VECTOR (23 downto 0);
signal fracYZero_uid15_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracYZero_uid15_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid18_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstAllZWE_uid20_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_x_uid23_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_x_uid23_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid24_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid24_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid25_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid25_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid26_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_x_uid27_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid28_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid29_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid30_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_x_uid31_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid37_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid37_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid38_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid38_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid39_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid39_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid40_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_y_uid41_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid42_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid43_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid44_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_y_uid45_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid46_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid46_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXmY_uid47_fpDivTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expXmY_uid47_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expXmY_uid47_fpDivTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expXmY_uid47_fpDivTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal expR_uid48_fpDivTest_a : STD_LOGIC_VECTOR (10 downto 0);
signal expR_uid48_fpDivTest_b : STD_LOGIC_VECTOR (10 downto 0);
signal expR_uid48_fpDivTest_o : STD_LOGIC_VECTOR (10 downto 0);
signal expR_uid48_fpDivTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal yAddr_uid51_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal yPE_uid52_fpDivTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal fracYPostZ_uid56_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracYPostZ_uid56_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal lOAdded_uid58_fpDivTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal oFracXSE_bottomExtension_uid61_fpDivTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal oFracXSE_mergedSignalTM_uid63_fpDivTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal divValPreNormS_uid65_fpDivTest_b : STD_LOGIC_VECTOR (25 downto 0);
signal divValPreNormTrunc_uid66_fpDivTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal divValPreNormTrunc_uid66_fpDivTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal norm_uid67_fpDivTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal divValPreNormHigh_uid68_fpDivTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal divValPreNormHigh_uid68_fpDivTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal divValPreNormLow_uid69_fpDivTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal divValPreNormLow_uid69_fpDivTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal normFracRnd_uid70_fpDivTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal normFracRnd_uid70_fpDivTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal expFracRnd_uid71_fpDivTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal rndOp_uid75_fpDivTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal expFracPostRnd_uid76_fpDivTest_a : STD_LOGIC_VECTOR (35 downto 0);
signal expFracPostRnd_uid76_fpDivTest_b : STD_LOGIC_VECTOR (35 downto 0);
signal expFracPostRnd_uid76_fpDivTest_o : STD_LOGIC_VECTOR (35 downto 0);
signal expFracPostRnd_uid76_fpDivTest_q : STD_LOGIC_VECTOR (34 downto 0);
signal fracRPreExc_uid78_fpDivTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExc_uid78_fpDivTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excRPreExc_uid79_fpDivTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal excRPreExc_uid79_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expRExt_uid80_fpDivTest_b : STD_LOGIC_VECTOR (10 downto 0);
signal expUdf_uid81_fpDivTest_a : STD_LOGIC_VECTOR (12 downto 0);
signal expUdf_uid81_fpDivTest_b : STD_LOGIC_VECTOR (12 downto 0);
signal expUdf_uid81_fpDivTest_o : STD_LOGIC_VECTOR (12 downto 0);
signal expUdf_uid81_fpDivTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal expOvf_uid84_fpDivTest_a : STD_LOGIC_VECTOR (12 downto 0);
signal expOvf_uid84_fpDivTest_b : STD_LOGIC_VECTOR (12 downto 0);
signal expOvf_uid84_fpDivTest_o : STD_LOGIC_VECTOR (12 downto 0);
signal expOvf_uid84_fpDivTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal zeroOverReg_uid85_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal regOverRegWithUf_uid86_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal xRegOrZero_uid87_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal regOrZeroOverInf_uid88_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid89_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXRYZ_uid90_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXRYROvf_uid91_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIYZ_uid92_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIYR_uid93_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInf_uid94_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXZYZ_uid95_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIYI_uid96_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid97_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal concExc_uid98_fpDivTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal excREnc_uid99_fpDivTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal oneFracRPostExc2_uid100_fpDivTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracRPostExc_uid103_fpDivTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExc_uid103_fpDivTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExc_uid107_fpDivTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExc_uid107_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal invExcRNaN_uid108_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sRPostExc_uid109_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal divR_uid110_fpDivTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal os_uid114_invTables_q : STD_LOGIC_VECTOR (30 downto 0);
signal os_uid118_invTables_q : STD_LOGIC_VECTOR (20 downto 0);
signal yT1_uid126_invPolyEval_b : STD_LOGIC_VECTOR (11 downto 0);
signal rndBit_uid128_invPolyEval_q : STD_LOGIC_VECTOR (1 downto 0);
signal cIncludingRoundingBit_uid129_invPolyEval_q : STD_LOGIC_VECTOR (22 downto 0);
signal ts1_uid131_invPolyEval_a : STD_LOGIC_VECTOR (23 downto 0);
signal ts1_uid131_invPolyEval_b : STD_LOGIC_VECTOR (23 downto 0);
signal ts1_uid131_invPolyEval_o : STD_LOGIC_VECTOR (23 downto 0);
signal ts1_uid131_invPolyEval_q : STD_LOGIC_VECTOR (23 downto 0);
signal s1_uid132_invPolyEval_b : STD_LOGIC_VECTOR (22 downto 0);
signal rndBit_uid135_invPolyEval_q : STD_LOGIC_VECTOR (2 downto 0);
signal cIncludingRoundingBit_uid136_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal ts2_uid138_invPolyEval_a : STD_LOGIC_VECTOR (34 downto 0);
signal ts2_uid138_invPolyEval_b : STD_LOGIC_VECTOR (34 downto 0);
signal ts2_uid138_invPolyEval_o : STD_LOGIC_VECTOR (34 downto 0);
signal ts2_uid138_invPolyEval_q : STD_LOGIC_VECTOR (34 downto 0);
signal s2_uid139_invPolyEval_b : STD_LOGIC_VECTOR (33 downto 0);
signal topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (16 downto 0);
signal rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (14 downto 0);
signal aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal n0_uid177_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid178_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid179_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid180_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid185_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid186_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid187_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid188_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid193_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid194_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n0_uid195_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid196_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (18 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (37 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (38 downto 0);
signal osig_uid222_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (35 downto 0);
signal osig_uid222_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (26 downto 0);
signal nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (12 downto 0);
signal topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (3 downto 0);
signal topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (16 downto 0);
signal topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (4 downto 0);
signal topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_a0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_b0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_s1 : STD_LOGIC_VECTOR (33 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_reset : std_logic;
signal sm0_uid247_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal osig_uid248_pT1_uid127_invPolyEval_in : STD_LOGIC_VECTOR (32 downto 0);
signal osig_uid248_pT1_uid127_invPolyEval_b : STD_LOGIC_VECTOR (13 downto 0);
signal nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (14 downto 0);
signal topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (16 downto 0);
signal topRangeY_uid266_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (16 downto 0);
signal aboveLeftX_uid272_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (7 downto 0);
signal aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (7 downto 0);
signal rightBottomX_uid283_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (6 downto 0);
signal rightBottomX_uid283_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (4 downto 0);
signal rightBottomY_uid284_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomY_uid284_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (4 downto 0);
signal n0_uid293_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid294_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid301_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid302_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (2 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_a0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_b0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_s1 : STD_LOGIC_VECTOR (33 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_reset : std_logic;
signal sm0_uid315_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_a0 : STD_LOGIC_VECTOR (7 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_s1 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_reset : std_logic;
signal sm0_uid316_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (15 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_a0 : STD_LOGIC_VECTOR (2 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_b0 : STD_LOGIC_VECTOR (2 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_s1 : STD_LOGIC_VECTOR (5 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_reset : std_logic;
signal sm0_uid317_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (5 downto 0);
signal lowRangeA_uid318_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (0 downto 0);
signal lowRangeA_uid318_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (0 downto 0);
signal highABits_uid319_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (32 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0_uid321_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (34 downto 0);
signal lowRangeA_uid322_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (2 downto 0);
signal lowRangeA_uid322_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (2 downto 0);
signal highABits_uid323_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (31 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (32 downto 0);
signal lev2_a0_uid325_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (35 downto 0);
signal osig_uid326_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (32 downto 0);
signal osig_uid326_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (24 downto 0);
signal memoryC0_uid112_invTables_lutmem_reset0 : std_logic;
signal memoryC0_uid112_invTables_lutmem_ia : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC0_uid112_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid112_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid112_invTables_lutmem_ir : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC0_uid112_invTables_lutmem_r : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC0_uid113_invTables_lutmem_reset0 : std_logic;
signal memoryC0_uid113_invTables_lutmem_ia : STD_LOGIC_VECTOR (12 downto 0);
signal memoryC0_uid113_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid113_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid113_invTables_lutmem_ir : STD_LOGIC_VECTOR (12 downto 0);
signal memoryC0_uid113_invTables_lutmem_r : STD_LOGIC_VECTOR (12 downto 0);
signal memoryC1_uid116_invTables_lutmem_reset0 : std_logic;
signal memoryC1_uid116_invTables_lutmem_ia : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC1_uid116_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid116_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid116_invTables_lutmem_ir : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC1_uid116_invTables_lutmem_r : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC1_uid117_invTables_lutmem_reset0 : std_logic;
signal memoryC1_uid117_invTables_lutmem_ia : STD_LOGIC_VECTOR (2 downto 0);
signal memoryC1_uid117_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid117_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid117_invTables_lutmem_ir : STD_LOGIC_VECTOR (2 downto 0);
signal memoryC1_uid117_invTables_lutmem_r : STD_LOGIC_VECTOR (2 downto 0);
signal memoryC2_uid120_invTables_lutmem_reset0 : std_logic;
signal memoryC2_uid120_invTables_lutmem_ia : STD_LOGIC_VECTOR (11 downto 0);
signal memoryC2_uid120_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC2_uid120_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC2_uid120_invTables_lutmem_ir : STD_LOGIC_VECTOR (11 downto 0);
signal memoryC2_uid120_invTables_lutmem_r : STD_LOGIC_VECTOR (11 downto 0);
signal invY_uid54_fpDivTest_merged_bit_select_in : STD_LOGIC_VECTOR (31 downto 0);
signal invY_uid54_fpDivTest_merged_bit_select_b : STD_LOGIC_VECTOR (25 downto 0);
signal invY_uid54_fpDivTest_merged_bit_select_c : STD_LOGIC_VECTOR (0 downto 0);
signal lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c : STD_LOGIC_VECTOR (12 downto 0);
signal lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c : STD_LOGIC_VECTOR (32 downto 0);
signal redist0_lOAdded_uid58_fpDivTest_q_2_q : STD_LOGIC_VECTOR (23 downto 0);
signal redist1_fracYPostZ_uid56_fpDivTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist2_yPE_uid52_fpDivTest_b_2_q : STD_LOGIC_VECTOR (13 downto 0);
signal redist3_yPE_uid52_fpDivTest_b_4_q : STD_LOGIC_VECTOR (13 downto 0);
signal redist4_yAddr_uid51_fpDivTest_b_2_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist5_yAddr_uid51_fpDivTest_b_4_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist6_expXmY_uid47_fpDivTest_q_8_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist7_signR_uid46_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist8_fracXIsZero_uid39_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist9_expXIsMax_uid38_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist10_excZ_y_uid37_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist11_fracXIsZero_uid25_fpDivTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist12_expXIsMax_uid24_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist13_excZ_x_uid23_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist14_fracYZero_uid15_fpDivTest_q_6_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist15_fracX_uid10_fpDivTest_b_6_q : STD_LOGIC_VECTOR (22 downto 0);
begin
-- fracY_uid13_fpDivTest(BITSELECT,12)@0
fracY_uid13_fpDivTest_b <= b(22 downto 0);
-- paddingY_uid15_fpDivTest(CONSTANT,14)
paddingY_uid15_fpDivTest_q <= "00000000000000000000000";
-- fracXIsZero_uid39_fpDivTest(LOGICAL,38)@0 + 1
fracXIsZero_uid39_fpDivTest_qi <= "1" WHEN paddingY_uid15_fpDivTest_q = fracY_uid13_fpDivTest_b ELSE "0";
fracXIsZero_uid39_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid39_fpDivTest_qi, xout => fracXIsZero_uid39_fpDivTest_q, clk => clk, aclr => areset );
-- redist8_fracXIsZero_uid39_fpDivTest_q_8(DELAY,343)
redist8_fracXIsZero_uid39_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid39_fpDivTest_q, xout => redist8_fracXIsZero_uid39_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- cstAllOWE_uid18_fpDivTest(CONSTANT,17)
cstAllOWE_uid18_fpDivTest_q <= "11111111";
-- expY_uid12_fpDivTest(BITSELECT,11)@0
expY_uid12_fpDivTest_b <= b(30 downto 23);
-- expXIsMax_uid38_fpDivTest(LOGICAL,37)@0 + 1
expXIsMax_uid38_fpDivTest_qi <= "1" WHEN expY_uid12_fpDivTest_b = cstAllOWE_uid18_fpDivTest_q ELSE "0";
expXIsMax_uid38_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid38_fpDivTest_qi, xout => expXIsMax_uid38_fpDivTest_q, clk => clk, aclr => areset );
-- redist9_expXIsMax_uid38_fpDivTest_q_8(DELAY,344)
redist9_expXIsMax_uid38_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid38_fpDivTest_q, xout => redist9_expXIsMax_uid38_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excI_y_uid41_fpDivTest(LOGICAL,40)@8
excI_y_uid41_fpDivTest_q <= redist9_expXIsMax_uid38_fpDivTest_q_8_q and redist8_fracXIsZero_uid39_fpDivTest_q_8_q;
-- fracX_uid10_fpDivTest(BITSELECT,9)@0
fracX_uid10_fpDivTest_b <= a(22 downto 0);
-- redist15_fracX_uid10_fpDivTest_b_6(DELAY,350)
redist15_fracX_uid10_fpDivTest_b_6 : dspba_delay
GENERIC MAP ( width => 23, depth => 6, reset_kind => "ASYNC" )
PORT MAP ( xin => fracX_uid10_fpDivTest_b, xout => redist15_fracX_uid10_fpDivTest_b_6_q, clk => clk, aclr => areset );
-- fracXIsZero_uid25_fpDivTest(LOGICAL,24)@6 + 1
fracXIsZero_uid25_fpDivTest_qi <= "1" WHEN paddingY_uid15_fpDivTest_q = redist15_fracX_uid10_fpDivTest_b_6_q ELSE "0";
fracXIsZero_uid25_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid25_fpDivTest_qi, xout => fracXIsZero_uid25_fpDivTest_q, clk => clk, aclr => areset );
-- redist11_fracXIsZero_uid25_fpDivTest_q_2(DELAY,346)
redist11_fracXIsZero_uid25_fpDivTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid25_fpDivTest_q, xout => redist11_fracXIsZero_uid25_fpDivTest_q_2_q, clk => clk, aclr => areset );
-- expX_uid9_fpDivTest(BITSELECT,8)@0
expX_uid9_fpDivTest_b <= a(30 downto 23);
-- expXIsMax_uid24_fpDivTest(LOGICAL,23)@0 + 1
expXIsMax_uid24_fpDivTest_qi <= "1" WHEN expX_uid9_fpDivTest_b = cstAllOWE_uid18_fpDivTest_q ELSE "0";
expXIsMax_uid24_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid24_fpDivTest_qi, xout => expXIsMax_uid24_fpDivTest_q, clk => clk, aclr => areset );
-- redist12_expXIsMax_uid24_fpDivTest_q_8(DELAY,347)
redist12_expXIsMax_uid24_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid24_fpDivTest_q, xout => redist12_expXIsMax_uid24_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excI_x_uid27_fpDivTest(LOGICAL,26)@8
excI_x_uid27_fpDivTest_q <= redist12_expXIsMax_uid24_fpDivTest_q_8_q and redist11_fracXIsZero_uid25_fpDivTest_q_2_q;
-- excXIYI_uid96_fpDivTest(LOGICAL,95)@8
excXIYI_uid96_fpDivTest_q <= excI_x_uid27_fpDivTest_q and excI_y_uid41_fpDivTest_q;
-- fracXIsNotZero_uid40_fpDivTest(LOGICAL,39)@8
fracXIsNotZero_uid40_fpDivTest_q <= not (redist8_fracXIsZero_uid39_fpDivTest_q_8_q);
-- excN_y_uid42_fpDivTest(LOGICAL,41)@8
excN_y_uid42_fpDivTest_q <= redist9_expXIsMax_uid38_fpDivTest_q_8_q and fracXIsNotZero_uid40_fpDivTest_q;
-- fracXIsNotZero_uid26_fpDivTest(LOGICAL,25)@8
fracXIsNotZero_uid26_fpDivTest_q <= not (redist11_fracXIsZero_uid25_fpDivTest_q_2_q);
-- excN_x_uid28_fpDivTest(LOGICAL,27)@8
excN_x_uid28_fpDivTest_q <= redist12_expXIsMax_uid24_fpDivTest_q_8_q and fracXIsNotZero_uid26_fpDivTest_q;
-- cstAllZWE_uid20_fpDivTest(CONSTANT,19)
cstAllZWE_uid20_fpDivTest_q <= "00000000";
-- excZ_y_uid37_fpDivTest(LOGICAL,36)@0 + 1
excZ_y_uid37_fpDivTest_qi <= "1" WHEN expY_uid12_fpDivTest_b = cstAllZWE_uid20_fpDivTest_q ELSE "0";
excZ_y_uid37_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid37_fpDivTest_qi, xout => excZ_y_uid37_fpDivTest_q, clk => clk, aclr => areset );
-- redist10_excZ_y_uid37_fpDivTest_q_8(DELAY,345)
redist10_excZ_y_uid37_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid37_fpDivTest_q, xout => redist10_excZ_y_uid37_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excZ_x_uid23_fpDivTest(LOGICAL,22)@0 + 1
excZ_x_uid23_fpDivTest_qi <= "1" WHEN expX_uid9_fpDivTest_b = cstAllZWE_uid20_fpDivTest_q ELSE "0";
excZ_x_uid23_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid23_fpDivTest_qi, xout => excZ_x_uid23_fpDivTest_q, clk => clk, aclr => areset );
-- redist13_excZ_x_uid23_fpDivTest_q_8(DELAY,348)
redist13_excZ_x_uid23_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid23_fpDivTest_q, xout => redist13_excZ_x_uid23_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excXZYZ_uid95_fpDivTest(LOGICAL,94)@8
excXZYZ_uid95_fpDivTest_q <= redist13_excZ_x_uid23_fpDivTest_q_8_q and redist10_excZ_y_uid37_fpDivTest_q_8_q;
-- excRNaN_uid97_fpDivTest(LOGICAL,96)@8
excRNaN_uid97_fpDivTest_q <= excXZYZ_uid95_fpDivTest_q or excN_x_uid28_fpDivTest_q or excN_y_uid42_fpDivTest_q or excXIYI_uid96_fpDivTest_q;
-- invExcRNaN_uid108_fpDivTest(LOGICAL,107)@8
invExcRNaN_uid108_fpDivTest_q <= not (excRNaN_uid97_fpDivTest_q);
-- signY_uid14_fpDivTest(BITSELECT,13)@0
signY_uid14_fpDivTest_b <= STD_LOGIC_VECTOR(b(31 downto 31));
-- signX_uid11_fpDivTest(BITSELECT,10)@0
signX_uid11_fpDivTest_b <= STD_LOGIC_VECTOR(a(31 downto 31));
-- signR_uid46_fpDivTest(LOGICAL,45)@0 + 1
signR_uid46_fpDivTest_qi <= signX_uid11_fpDivTest_b xor signY_uid14_fpDivTest_b;
signR_uid46_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid46_fpDivTest_qi, xout => signR_uid46_fpDivTest_q, clk => clk, aclr => areset );
-- redist7_signR_uid46_fpDivTest_q_8(DELAY,342)
redist7_signR_uid46_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid46_fpDivTest_q, xout => redist7_signR_uid46_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- sRPostExc_uid109_fpDivTest(LOGICAL,108)@8
sRPostExc_uid109_fpDivTest_q <= redist7_signR_uid46_fpDivTest_q_8_q and invExcRNaN_uid108_fpDivTest_q;
-- lOAdded_uid58_fpDivTest(BITJOIN,57)@6
lOAdded_uid58_fpDivTest_q <= VCC_q & redist15_fracX_uid10_fpDivTest_b_6_q;
-- redist0_lOAdded_uid58_fpDivTest_q_2(DELAY,335)
redist0_lOAdded_uid58_fpDivTest_q_2 : dspba_delay
GENERIC MAP ( width => 24, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => lOAdded_uid58_fpDivTest_q, xout => redist0_lOAdded_uid58_fpDivTest_q_2_q, clk => clk, aclr => areset );
-- oFracXSE_bottomExtension_uid61_fpDivTest(CONSTANT,60)
oFracXSE_bottomExtension_uid61_fpDivTest_q <= "00";
-- oFracXSE_mergedSignalTM_uid63_fpDivTest(BITJOIN,62)@8
oFracXSE_mergedSignalTM_uid63_fpDivTest_q <= redist0_lOAdded_uid58_fpDivTest_q_2_q & oFracXSE_bottomExtension_uid61_fpDivTest_q;
-- aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,170)@6
aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_in <= lOAdded_uid58_fpDivTest_q(14 downto 0);
aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_in(14 downto 10);
-- n1_uid180_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,179)@6
n1_uid180_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n1_uid188_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,187)@6
n1_uid188_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid180_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n1_uid196_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,195)@6
n1_uid196_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid188_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- yAddr_uid51_fpDivTest(BITSELECT,50)@0
yAddr_uid51_fpDivTest_b <= fracY_uid13_fpDivTest_b(22 downto 14);
-- memoryC2_uid120_invTables_lutmem(DUALMEM,331)@0 + 2
memoryC2_uid120_invTables_lutmem_aa <= yAddr_uid51_fpDivTest_b;
memoryC2_uid120_invTables_lutmem_reset0 <= areset;
memoryC2_uid120_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_memoryC2_uid120_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC2_uid120_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC2_uid120_invTables_lutmem_aa,
q_a => memoryC2_uid120_invTables_lutmem_ir
);
memoryC2_uid120_invTables_lutmem_r <= memoryC2_uid120_invTables_lutmem_ir(11 downto 0);
-- topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval(CONSTANT,242)
topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval_q <= "00000";
-- topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval(BITJOIN,244)@2
topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval_q <= memoryC2_uid120_invTables_lutmem_r & topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval_q;
-- GND(CONSTANT,0)
GND_q <= "0";
-- yPE_uid52_fpDivTest(BITSELECT,51)@0
yPE_uid52_fpDivTest_b <= b(13 downto 0);
-- redist2_yPE_uid52_fpDivTest_b_2(DELAY,337)
redist2_yPE_uid52_fpDivTest_b_2 : dspba_delay
GENERIC MAP ( width => 14, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => yPE_uid52_fpDivTest_b, xout => redist2_yPE_uid52_fpDivTest_b_2_q, clk => clk, aclr => areset );
-- yT1_uid126_invPolyEval(BITSELECT,125)@2
yT1_uid126_invPolyEval_b <= redist2_yPE_uid52_fpDivTest_b_2_q(13 downto 2);
-- nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval(BITJOIN,225)@2
nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval_q <= GND_q & yT1_uid126_invPolyEval_b;
-- topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval(CONSTANT,238)
topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval_q <= "0000";
-- topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval(BITJOIN,240)@2
topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval_q <= nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval_q & topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval_q;
-- sm0_uid247_pT1_uid127_invPolyEval(MULT,246)@2 + 2
sm0_uid247_pT1_uid127_invPolyEval_a0 <= STD_LOGIC_VECTOR(topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval_q);
sm0_uid247_pT1_uid127_invPolyEval_b0 <= STD_LOGIC_VECTOR(topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval_q);
sm0_uid247_pT1_uid127_invPolyEval_reset <= areset;
sm0_uid247_pT1_uid127_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 17,
lpm_widthb => 17,
lpm_widthp => 34,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid247_pT1_uid127_invPolyEval_a0,
datab => sm0_uid247_pT1_uid127_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid247_pT1_uid127_invPolyEval_reset,
clock => clk,
result => sm0_uid247_pT1_uid127_invPolyEval_s1
);
sm0_uid247_pT1_uid127_invPolyEval_q <= sm0_uid247_pT1_uid127_invPolyEval_s1;
-- osig_uid248_pT1_uid127_invPolyEval(BITSELECT,247)@4
osig_uid248_pT1_uid127_invPolyEval_in <= STD_LOGIC_VECTOR(sm0_uid247_pT1_uid127_invPolyEval_q(32 downto 0));
osig_uid248_pT1_uid127_invPolyEval_b <= STD_LOGIC_VECTOR(osig_uid248_pT1_uid127_invPolyEval_in(32 downto 19));
-- redist4_yAddr_uid51_fpDivTest_b_2(DELAY,339)
redist4_yAddr_uid51_fpDivTest_b_2 : dspba_delay
GENERIC MAP ( width => 9, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => yAddr_uid51_fpDivTest_b, xout => redist4_yAddr_uid51_fpDivTest_b_2_q, clk => clk, aclr => areset );
-- memoryC1_uid117_invTables_lutmem(DUALMEM,330)@2 + 2
memoryC1_uid117_invTables_lutmem_aa <= redist4_yAddr_uid51_fpDivTest_b_2_q;
memoryC1_uid117_invTables_lutmem_reset0 <= areset;
memoryC1_uid117_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 3,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_memoryC1_uid117_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC1_uid117_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC1_uid117_invTables_lutmem_aa,
q_a => memoryC1_uid117_invTables_lutmem_ir
);
memoryC1_uid117_invTables_lutmem_r <= memoryC1_uid117_invTables_lutmem_ir(2 downto 0);
-- memoryC1_uid116_invTables_lutmem(DUALMEM,329)@2 + 2
memoryC1_uid116_invTables_lutmem_aa <= redist4_yAddr_uid51_fpDivTest_b_2_q;
memoryC1_uid116_invTables_lutmem_reset0 <= areset;
memoryC1_uid116_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 18,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_memoryC1_uid116_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC1_uid116_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC1_uid116_invTables_lutmem_aa,
q_a => memoryC1_uid116_invTables_lutmem_ir
);
memoryC1_uid116_invTables_lutmem_r <= memoryC1_uid116_invTables_lutmem_ir(17 downto 0);
-- os_uid118_invTables(BITJOIN,117)@4
os_uid118_invTables_q <= memoryC1_uid117_invTables_lutmem_r & memoryC1_uid116_invTables_lutmem_r;
-- rndBit_uid128_invPolyEval(CONSTANT,127)
rndBit_uid128_invPolyEval_q <= "01";
-- cIncludingRoundingBit_uid129_invPolyEval(BITJOIN,128)@4
cIncludingRoundingBit_uid129_invPolyEval_q <= os_uid118_invTables_q & rndBit_uid128_invPolyEval_q;
-- ts1_uid131_invPolyEval(ADD,130)@4
ts1_uid131_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((23 downto 23 => cIncludingRoundingBit_uid129_invPolyEval_q(22)) & cIncludingRoundingBit_uid129_invPolyEval_q));
ts1_uid131_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((23 downto 14 => osig_uid248_pT1_uid127_invPolyEval_b(13)) & osig_uid248_pT1_uid127_invPolyEval_b));
ts1_uid131_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts1_uid131_invPolyEval_a) + SIGNED(ts1_uid131_invPolyEval_b));
ts1_uid131_invPolyEval_q <= ts1_uid131_invPolyEval_o(23 downto 0);
-- s1_uid132_invPolyEval(BITSELECT,131)@4
s1_uid132_invPolyEval_b <= STD_LOGIC_VECTOR(ts1_uid131_invPolyEval_q(23 downto 1));
-- rightBottomY_uid284_pT2_uid134_invPolyEval(BITSELECT,283)@4
rightBottomY_uid284_pT2_uid134_invPolyEval_in <= s1_uid132_invPolyEval_b(5 downto 0);
rightBottomY_uid284_pT2_uid134_invPolyEval_b <= rightBottomY_uid284_pT2_uid134_invPolyEval_in(5 downto 1);
-- n1_uid294_pT2_uid134_invPolyEval(BITSELECT,293)@4
n1_uid294_pT2_uid134_invPolyEval_b <= rightBottomY_uid284_pT2_uid134_invPolyEval_b(4 downto 1);
-- n1_uid302_pT2_uid134_invPolyEval(BITSELECT,301)@4
n1_uid302_pT2_uid134_invPolyEval_b <= n1_uid294_pT2_uid134_invPolyEval_b(3 downto 1);
-- redist3_yPE_uid52_fpDivTest_b_4(DELAY,338)
redist3_yPE_uid52_fpDivTest_b_4 : dspba_delay
GENERIC MAP ( width => 14, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => redist2_yPE_uid52_fpDivTest_b_2_q, xout => redist3_yPE_uid52_fpDivTest_b_4_q, clk => clk, aclr => areset );
-- nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval(BITJOIN,251)@4
nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q <= GND_q & redist3_yPE_uid52_fpDivTest_b_4_q;
-- rightBottomX_uid283_pT2_uid134_invPolyEval(BITSELECT,282)@4
rightBottomX_uid283_pT2_uid134_invPolyEval_in <= nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q(6 downto 0);
rightBottomX_uid283_pT2_uid134_invPolyEval_b <= rightBottomX_uid283_pT2_uid134_invPolyEval_in(6 downto 2);
-- n0_uid293_pT2_uid134_invPolyEval(BITSELECT,292)@4
n0_uid293_pT2_uid134_invPolyEval_b <= rightBottomX_uid283_pT2_uid134_invPolyEval_b(4 downto 1);
-- n0_uid301_pT2_uid134_invPolyEval(BITSELECT,300)@4
n0_uid301_pT2_uid134_invPolyEval_b <= n0_uid293_pT2_uid134_invPolyEval_b(3 downto 1);
-- sm0_uid317_pT2_uid134_invPolyEval(MULT,316)@4 + 2
sm0_uid317_pT2_uid134_invPolyEval_a0 <= n0_uid301_pT2_uid134_invPolyEval_b;
sm0_uid317_pT2_uid134_invPolyEval_b0 <= n1_uid302_pT2_uid134_invPolyEval_b;
sm0_uid317_pT2_uid134_invPolyEval_reset <= areset;
sm0_uid317_pT2_uid134_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 3,
lpm_widthb => 3,
lpm_widthp => 6,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid317_pT2_uid134_invPolyEval_a0,
datab => sm0_uid317_pT2_uid134_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid317_pT2_uid134_invPolyEval_reset,
clock => clk,
result => sm0_uid317_pT2_uid134_invPolyEval_s1
);
sm0_uid317_pT2_uid134_invPolyEval_q <= sm0_uid317_pT2_uid134_invPolyEval_s1;
-- aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval(BITSELECT,273)@4
aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_in <= STD_LOGIC_VECTOR(s1_uid132_invPolyEval_b(5 downto 0));
aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_in(5 downto 0));
-- aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval(BITJOIN,274)@4
aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval_q <= aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_b & oFracXSE_bottomExtension_uid61_fpDivTest_q;
-- aboveLeftX_uid272_pT2_uid134_invPolyEval(BITSELECT,271)@4
aboveLeftX_uid272_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q(14 downto 7));
-- sm0_uid316_pT2_uid134_invPolyEval(MULT,315)@4 + 2
sm0_uid316_pT2_uid134_invPolyEval_a0 <= STD_LOGIC_VECTOR(aboveLeftX_uid272_pT2_uid134_invPolyEval_b);
sm0_uid316_pT2_uid134_invPolyEval_b0 <= '0' & aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval_q;
sm0_uid316_pT2_uid134_invPolyEval_reset <= areset;
sm0_uid316_pT2_uid134_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 8,
lpm_widthb => 9,
lpm_widthp => 17,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid316_pT2_uid134_invPolyEval_a0,
datab => sm0_uid316_pT2_uid134_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid316_pT2_uid134_invPolyEval_reset,
clock => clk,
result => sm0_uid316_pT2_uid134_invPolyEval_s1
);
sm0_uid316_pT2_uid134_invPolyEval_q <= sm0_uid316_pT2_uid134_invPolyEval_s1(15 downto 0);
-- topRangeY_uid266_pT2_uid134_invPolyEval(BITSELECT,265)@4
topRangeY_uid266_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(s1_uid132_invPolyEval_b(22 downto 6));
-- topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval(BITJOIN,263)@4
topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval_q <= nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q & oFracXSE_bottomExtension_uid61_fpDivTest_q;
-- sm0_uid315_pT2_uid134_invPolyEval(MULT,314)@4 + 2
sm0_uid315_pT2_uid134_invPolyEval_a0 <= STD_LOGIC_VECTOR(topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval_q);
sm0_uid315_pT2_uid134_invPolyEval_b0 <= STD_LOGIC_VECTOR(topRangeY_uid266_pT2_uid134_invPolyEval_b);
sm0_uid315_pT2_uid134_invPolyEval_reset <= areset;
sm0_uid315_pT2_uid134_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 17,
lpm_widthb => 17,
lpm_widthp => 34,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid315_pT2_uid134_invPolyEval_a0,
datab => sm0_uid315_pT2_uid134_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid315_pT2_uid134_invPolyEval_reset,
clock => clk,
result => sm0_uid315_pT2_uid134_invPolyEval_s1
);
sm0_uid315_pT2_uid134_invPolyEval_q <= sm0_uid315_pT2_uid134_invPolyEval_s1;
-- highABits_uid319_pT2_uid134_invPolyEval(BITSELECT,318)@6
highABits_uid319_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(sm0_uid315_pT2_uid134_invPolyEval_q(33 downto 1));
-- lev1_a0high_uid320_pT2_uid134_invPolyEval(ADD,319)@6
lev1_a0high_uid320_pT2_uid134_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((33 downto 33 => highABits_uid319_pT2_uid134_invPolyEval_b(32)) & highABits_uid319_pT2_uid134_invPolyEval_b));
lev1_a0high_uid320_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((33 downto 16 => sm0_uid316_pT2_uid134_invPolyEval_q(15)) & sm0_uid316_pT2_uid134_invPolyEval_q));
lev1_a0high_uid320_pT2_uid134_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0high_uid320_pT2_uid134_invPolyEval_a) + SIGNED(lev1_a0high_uid320_pT2_uid134_invPolyEval_b));
lev1_a0high_uid320_pT2_uid134_invPolyEval_q <= lev1_a0high_uid320_pT2_uid134_invPolyEval_o(33 downto 0);
-- lowRangeA_uid318_pT2_uid134_invPolyEval(BITSELECT,317)@6
lowRangeA_uid318_pT2_uid134_invPolyEval_in <= sm0_uid315_pT2_uid134_invPolyEval_q(0 downto 0);
lowRangeA_uid318_pT2_uid134_invPolyEval_b <= lowRangeA_uid318_pT2_uid134_invPolyEval_in(0 downto 0);
-- lev1_a0_uid321_pT2_uid134_invPolyEval(BITJOIN,320)@6
lev1_a0_uid321_pT2_uid134_invPolyEval_q <= lev1_a0high_uid320_pT2_uid134_invPolyEval_q & lowRangeA_uid318_pT2_uid134_invPolyEval_b;
-- highABits_uid323_pT2_uid134_invPolyEval(BITSELECT,322)@6
highABits_uid323_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(lev1_a0_uid321_pT2_uid134_invPolyEval_q(34 downto 3));
-- lev2_a0high_uid324_pT2_uid134_invPolyEval(ADD,323)@6
lev2_a0high_uid324_pT2_uid134_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((33 downto 32 => highABits_uid323_pT2_uid134_invPolyEval_b(31)) & highABits_uid323_pT2_uid134_invPolyEval_b));
lev2_a0high_uid324_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "000000000000000000000000000" & sm0_uid317_pT2_uid134_invPolyEval_q));
lev2_a0high_uid324_pT2_uid134_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(lev2_a0high_uid324_pT2_uid134_invPolyEval_a) + SIGNED(lev2_a0high_uid324_pT2_uid134_invPolyEval_b));
lev2_a0high_uid324_pT2_uid134_invPolyEval_q <= lev2_a0high_uid324_pT2_uid134_invPolyEval_o(32 downto 0);
-- lowRangeA_uid322_pT2_uid134_invPolyEval(BITSELECT,321)@6
lowRangeA_uid322_pT2_uid134_invPolyEval_in <= lev1_a0_uid321_pT2_uid134_invPolyEval_q(2 downto 0);
lowRangeA_uid322_pT2_uid134_invPolyEval_b <= lowRangeA_uid322_pT2_uid134_invPolyEval_in(2 downto 0);
-- lev2_a0_uid325_pT2_uid134_invPolyEval(BITJOIN,324)@6
lev2_a0_uid325_pT2_uid134_invPolyEval_q <= lev2_a0high_uid324_pT2_uid134_invPolyEval_q & lowRangeA_uid322_pT2_uid134_invPolyEval_b;
-- osig_uid326_pT2_uid134_invPolyEval(BITSELECT,325)@6
osig_uid326_pT2_uid134_invPolyEval_in <= STD_LOGIC_VECTOR(lev2_a0_uid325_pT2_uid134_invPolyEval_q(32 downto 0));
osig_uid326_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(osig_uid326_pT2_uid134_invPolyEval_in(32 downto 8));
-- redist5_yAddr_uid51_fpDivTest_b_4(DELAY,340)
redist5_yAddr_uid51_fpDivTest_b_4 : dspba_delay
GENERIC MAP ( width => 9, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => redist4_yAddr_uid51_fpDivTest_b_2_q, xout => redist5_yAddr_uid51_fpDivTest_b_4_q, clk => clk, aclr => areset );
-- memoryC0_uid113_invTables_lutmem(DUALMEM,328)@4 + 2
memoryC0_uid113_invTables_lutmem_aa <= redist5_yAddr_uid51_fpDivTest_b_4_q;
memoryC0_uid113_invTables_lutmem_reset0 <= areset;
memoryC0_uid113_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 13,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_memoryC0_uid113_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC0_uid113_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC0_uid113_invTables_lutmem_aa,
q_a => memoryC0_uid113_invTables_lutmem_ir
);
memoryC0_uid113_invTables_lutmem_r <= memoryC0_uid113_invTables_lutmem_ir(12 downto 0);
-- memoryC0_uid112_invTables_lutmem(DUALMEM,327)@4 + 2
memoryC0_uid112_invTables_lutmem_aa <= redist5_yAddr_uid51_fpDivTest_b_4_q;
memoryC0_uid112_invTables_lutmem_reset0 <= areset;
memoryC0_uid112_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 18,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_memoryC0_uid112_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC0_uid112_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC0_uid112_invTables_lutmem_aa,
q_a => memoryC0_uid112_invTables_lutmem_ir
);
memoryC0_uid112_invTables_lutmem_r <= memoryC0_uid112_invTables_lutmem_ir(17 downto 0);
-- os_uid114_invTables(BITJOIN,113)@6
os_uid114_invTables_q <= memoryC0_uid113_invTables_lutmem_r & memoryC0_uid112_invTables_lutmem_r;
-- rndBit_uid135_invPolyEval(CONSTANT,134)
rndBit_uid135_invPolyEval_q <= "001";
-- cIncludingRoundingBit_uid136_invPolyEval(BITJOIN,135)@6
cIncludingRoundingBit_uid136_invPolyEval_q <= os_uid114_invTables_q & rndBit_uid135_invPolyEval_q;
-- ts2_uid138_invPolyEval(ADD,137)@6
ts2_uid138_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((34 downto 34 => cIncludingRoundingBit_uid136_invPolyEval_q(33)) & cIncludingRoundingBit_uid136_invPolyEval_q));
ts2_uid138_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((34 downto 25 => osig_uid326_pT2_uid134_invPolyEval_b(24)) & osig_uid326_pT2_uid134_invPolyEval_b));
ts2_uid138_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid138_invPolyEval_a) + SIGNED(ts2_uid138_invPolyEval_b));
ts2_uid138_invPolyEval_q <= ts2_uid138_invPolyEval_o(34 downto 0);
-- s2_uid139_invPolyEval(BITSELECT,138)@6
s2_uid139_invPolyEval_b <= STD_LOGIC_VECTOR(ts2_uid138_invPolyEval_q(34 downto 1));
-- invY_uid54_fpDivTest_merged_bit_select(BITSELECT,332)@6
invY_uid54_fpDivTest_merged_bit_select_in <= s2_uid139_invPolyEval_b(31 downto 0);
invY_uid54_fpDivTest_merged_bit_select_b <= invY_uid54_fpDivTest_merged_bit_select_in(30 downto 5);
invY_uid54_fpDivTest_merged_bit_select_c <= invY_uid54_fpDivTest_merged_bit_select_in(31 downto 31);
-- aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,169)@6
aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_in <= invY_uid54_fpDivTest_merged_bit_select_b(7 downto 0);
aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_in(7 downto 3);
-- n0_uid179_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,178)@6
n0_uid179_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n0_uid187_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,186)@6
n0_uid187_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid179_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n0_uid195_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,194)@6
n0_uid195_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid187_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- sm1_uid211_prodDivPreNormProd_uid60_fpDivTest(MULT,210)@6 + 2
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_a0 <= n0_uid195_prodDivPreNormProd_uid60_fpDivTest_b;
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_b0 <= n1_uid196_prodDivPreNormProd_uid60_fpDivTest_b;
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_q <= sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest(ADD,219)@8
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c);
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000" & sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_q);
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_b));
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_q <= lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_o(33 downto 0);
-- rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,168)@6
rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_in <= lOAdded_uid58_fpDivTest_q(5 downto 0);
rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_in(5 downto 1);
-- n1_uid178_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,177)@6
n1_uid178_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n1_uid186_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,185)@6
n1_uid186_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid178_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n1_uid194_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,193)@6
n1_uid194_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid186_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,167)@6
rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_in <= invY_uid54_fpDivTest_merged_bit_select_b(16 downto 0);
rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_in(16 downto 12);
-- n0_uid177_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,176)@6
n0_uid177_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n0_uid185_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,184)@6
n0_uid185_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid177_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n0_uid193_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,192)@6
n0_uid193_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid185_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- sm0_uid210_prodDivPreNormProd_uid60_fpDivTest(MULT,209)@6 + 2
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_a0 <= n0_uid193_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_b0 <= n1_uid194_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_q <= sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest(ADD,214)@8
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c);
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("0000000000" & sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_q);
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_b));
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_q <= lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_o(13 downto 0);
-- rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,163)@6
rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest_b <= lOAdded_uid58_fpDivTest_q(23 downto 15);
-- rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,160)@6
rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_in <= invY_uid54_fpDivTest_merged_bit_select_b(7 downto 0);
rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_in(7 downto 0);
-- rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,161)@6
rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest_q <= rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_b & GND_q;
-- sm1_uid209_prodDivPreNormProd_uid60_fpDivTest(MULT,208)@6 + 2
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_a0 <= rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest_q;
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_b0 <= rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest_b;
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q <= sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select(BITSELECT,333)@8
lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b <= sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q(4 downto 0);
lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c <= sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q(17 downto 5);
-- lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,215)@8
lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest_q <= lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_q & lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b;
-- aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,156)@6
aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_in <= lOAdded_uid58_fpDivTest_q(5 downto 0);
aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_in(5 downto 0);
-- aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest(CONSTANT,155)
aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest_q <= "000";
-- aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,157)@6
aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest_q <= aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_b & aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest_q;
-- aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,154)@6
aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest_b <= invY_uid54_fpDivTest_merged_bit_select_b(25 downto 17);
-- sm0_uid208_prodDivPreNormProd_uid60_fpDivTest(MULT,207)@6 + 2
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_a0 <= aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_b0 <= aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest_q;
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_q <= sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_s1;
-- topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,149)@6
topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest_b <= lOAdded_uid58_fpDivTest_q(23 downto 6);
-- topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,148)@6
topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest_b <= invY_uid54_fpDivTest_merged_bit_select_b(25 downto 8);
-- sm0_uid207_prodDivPreNormProd_uid60_fpDivTest(MULT,206)@6 + 2
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_a0 <= topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_b0 <= topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 36,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_q <= sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest(ADD,211)@8
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_q);
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_q);
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_b));
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_q <= lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_o(36 downto 0);
-- lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest(ADD,216)@8
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_q);
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest_q);
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_b));
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q <= lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_o(37 downto 0);
-- lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select(BITSELECT,334)@8
lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b <= lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q(4 downto 0);
lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c <= lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q(37 downto 5);
-- lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,220)@8
lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest_q <= lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_q & lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b;
-- osig_uid222_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,221)@8
osig_uid222_prodDivPreNormProd_uid60_fpDivTest_in <= lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest_q(35 downto 0);
osig_uid222_prodDivPreNormProd_uid60_fpDivTest_b <= osig_uid222_prodDivPreNormProd_uid60_fpDivTest_in(35 downto 9);
-- divValPreNormS_uid65_fpDivTest(BITSELECT,64)@8
divValPreNormS_uid65_fpDivTest_b <= osig_uid222_prodDivPreNormProd_uid60_fpDivTest_b(26 downto 1);
-- updatedY_uid16_fpDivTest(BITJOIN,15)@0
updatedY_uid16_fpDivTest_q <= GND_q & paddingY_uid15_fpDivTest_q;
-- fracYZero_uid15_fpDivTest(LOGICAL,16)@0 + 1
fracYZero_uid15_fpDivTest_a <= STD_LOGIC_VECTOR("0" & fracY_uid13_fpDivTest_b);
fracYZero_uid15_fpDivTest_qi <= "1" WHEN fracYZero_uid15_fpDivTest_a = updatedY_uid16_fpDivTest_q ELSE "0";
fracYZero_uid15_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYZero_uid15_fpDivTest_qi, xout => fracYZero_uid15_fpDivTest_q, clk => clk, aclr => areset );
-- redist14_fracYZero_uid15_fpDivTest_q_6(DELAY,349)
redist14_fracYZero_uid15_fpDivTest_q_6 : dspba_delay
GENERIC MAP ( width => 1, depth => 5, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYZero_uid15_fpDivTest_q, xout => redist14_fracYZero_uid15_fpDivTest_q_6_q, clk => clk, aclr => areset );
-- fracYPostZ_uid56_fpDivTest(LOGICAL,55)@6 + 1
fracYPostZ_uid56_fpDivTest_qi <= redist14_fracYZero_uid15_fpDivTest_q_6_q or invY_uid54_fpDivTest_merged_bit_select_c;
fracYPostZ_uid56_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYPostZ_uid56_fpDivTest_qi, xout => fracYPostZ_uid56_fpDivTest_q, clk => clk, aclr => areset );
-- redist1_fracYPostZ_uid56_fpDivTest_q_2(DELAY,336)
redist1_fracYPostZ_uid56_fpDivTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYPostZ_uid56_fpDivTest_q, xout => redist1_fracYPostZ_uid56_fpDivTest_q_2_q, clk => clk, aclr => areset );
-- divValPreNormTrunc_uid66_fpDivTest(MUX,65)@8
divValPreNormTrunc_uid66_fpDivTest_s <= redist1_fracYPostZ_uid56_fpDivTest_q_2_q;
divValPreNormTrunc_uid66_fpDivTest_combproc: PROCESS (divValPreNormTrunc_uid66_fpDivTest_s, divValPreNormS_uid65_fpDivTest_b, oFracXSE_mergedSignalTM_uid63_fpDivTest_q)
BEGIN
CASE (divValPreNormTrunc_uid66_fpDivTest_s) IS
WHEN "0" => divValPreNormTrunc_uid66_fpDivTest_q <= divValPreNormS_uid65_fpDivTest_b;
WHEN "1" => divValPreNormTrunc_uid66_fpDivTest_q <= oFracXSE_mergedSignalTM_uid63_fpDivTest_q;
WHEN OTHERS => divValPreNormTrunc_uid66_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- norm_uid67_fpDivTest(BITSELECT,66)@8
norm_uid67_fpDivTest_b <= STD_LOGIC_VECTOR(divValPreNormTrunc_uid66_fpDivTest_q(25 downto 25));
-- rndOp_uid75_fpDivTest(BITJOIN,74)@8
rndOp_uid75_fpDivTest_q <= norm_uid67_fpDivTest_b & paddingY_uid15_fpDivTest_q & VCC_q;
-- cstBiasM1_uid6_fpDivTest(CONSTANT,5)
cstBiasM1_uid6_fpDivTest_q <= "01111110";
-- expXmY_uid47_fpDivTest(SUB,46)@0 + 1
expXmY_uid47_fpDivTest_a <= STD_LOGIC_VECTOR("0" & expX_uid9_fpDivTest_b);
expXmY_uid47_fpDivTest_b <= STD_LOGIC_VECTOR("0" & expY_uid12_fpDivTest_b);
expXmY_uid47_fpDivTest_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXmY_uid47_fpDivTest_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
expXmY_uid47_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXmY_uid47_fpDivTest_a) - UNSIGNED(expXmY_uid47_fpDivTest_b));
END IF;
END PROCESS;
expXmY_uid47_fpDivTest_q <= expXmY_uid47_fpDivTest_o(8 downto 0);
-- redist6_expXmY_uid47_fpDivTest_q_8(DELAY,341)
redist6_expXmY_uid47_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 9, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => expXmY_uid47_fpDivTest_q, xout => redist6_expXmY_uid47_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- expR_uid48_fpDivTest(ADD,47)@8
expR_uid48_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist6_expXmY_uid47_fpDivTest_q_8_q(8)) & redist6_expXmY_uid47_fpDivTest_q_8_q));
expR_uid48_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00" & cstBiasM1_uid6_fpDivTest_q));
expR_uid48_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expR_uid48_fpDivTest_a) + SIGNED(expR_uid48_fpDivTest_b));
expR_uid48_fpDivTest_q <= expR_uid48_fpDivTest_o(9 downto 0);
-- divValPreNormHigh_uid68_fpDivTest(BITSELECT,67)@8
divValPreNormHigh_uid68_fpDivTest_in <= divValPreNormTrunc_uid66_fpDivTest_q(24 downto 0);
divValPreNormHigh_uid68_fpDivTest_b <= divValPreNormHigh_uid68_fpDivTest_in(24 downto 1);
-- divValPreNormLow_uid69_fpDivTest(BITSELECT,68)@8
divValPreNormLow_uid69_fpDivTest_in <= divValPreNormTrunc_uid66_fpDivTest_q(23 downto 0);
divValPreNormLow_uid69_fpDivTest_b <= divValPreNormLow_uid69_fpDivTest_in(23 downto 0);
-- normFracRnd_uid70_fpDivTest(MUX,69)@8
normFracRnd_uid70_fpDivTest_s <= norm_uid67_fpDivTest_b;
normFracRnd_uid70_fpDivTest_combproc: PROCESS (normFracRnd_uid70_fpDivTest_s, divValPreNormLow_uid69_fpDivTest_b, divValPreNormHigh_uid68_fpDivTest_b)
BEGIN
CASE (normFracRnd_uid70_fpDivTest_s) IS
WHEN "0" => normFracRnd_uid70_fpDivTest_q <= divValPreNormLow_uid69_fpDivTest_b;
WHEN "1" => normFracRnd_uid70_fpDivTest_q <= divValPreNormHigh_uid68_fpDivTest_b;
WHEN OTHERS => normFracRnd_uid70_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- expFracRnd_uid71_fpDivTest(BITJOIN,70)@8
expFracRnd_uid71_fpDivTest_q <= expR_uid48_fpDivTest_q & normFracRnd_uid70_fpDivTest_q;
-- expFracPostRnd_uid76_fpDivTest(ADD,75)@8
expFracPostRnd_uid76_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((35 downto 34 => expFracRnd_uid71_fpDivTest_q(33)) & expFracRnd_uid71_fpDivTest_q));
expFracPostRnd_uid76_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000000000" & rndOp_uid75_fpDivTest_q));
expFracPostRnd_uid76_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracPostRnd_uid76_fpDivTest_a) + SIGNED(expFracPostRnd_uid76_fpDivTest_b));
expFracPostRnd_uid76_fpDivTest_q <= expFracPostRnd_uid76_fpDivTest_o(34 downto 0);
-- excRPreExc_uid79_fpDivTest(BITSELECT,78)@8
excRPreExc_uid79_fpDivTest_in <= expFracPostRnd_uid76_fpDivTest_q(31 downto 0);
excRPreExc_uid79_fpDivTest_b <= excRPreExc_uid79_fpDivTest_in(31 downto 24);
-- invExpXIsMax_uid43_fpDivTest(LOGICAL,42)@8
invExpXIsMax_uid43_fpDivTest_q <= not (redist9_expXIsMax_uid38_fpDivTest_q_8_q);
-- InvExpXIsZero_uid44_fpDivTest(LOGICAL,43)@8
InvExpXIsZero_uid44_fpDivTest_q <= not (redist10_excZ_y_uid37_fpDivTest_q_8_q);
-- excR_y_uid45_fpDivTest(LOGICAL,44)@8
excR_y_uid45_fpDivTest_q <= InvExpXIsZero_uid44_fpDivTest_q and invExpXIsMax_uid43_fpDivTest_q;
-- excXIYR_uid93_fpDivTest(LOGICAL,92)@8
excXIYR_uid93_fpDivTest_q <= excI_x_uid27_fpDivTest_q and excR_y_uid45_fpDivTest_q;
-- excXIYZ_uid92_fpDivTest(LOGICAL,91)@8
excXIYZ_uid92_fpDivTest_q <= excI_x_uid27_fpDivTest_q and redist10_excZ_y_uid37_fpDivTest_q_8_q;
-- expRExt_uid80_fpDivTest(BITSELECT,79)@8
expRExt_uid80_fpDivTest_b <= STD_LOGIC_VECTOR(expFracPostRnd_uid76_fpDivTest_q(34 downto 24));
-- expOvf_uid84_fpDivTest(COMPARE,83)@8
expOvf_uid84_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((12 downto 11 => expRExt_uid80_fpDivTest_b(10)) & expRExt_uid80_fpDivTest_b));
expOvf_uid84_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000" & cstAllOWE_uid18_fpDivTest_q));
expOvf_uid84_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid84_fpDivTest_a) - SIGNED(expOvf_uid84_fpDivTest_b));
expOvf_uid84_fpDivTest_n(0) <= not (expOvf_uid84_fpDivTest_o(12));
-- invExpXIsMax_uid29_fpDivTest(LOGICAL,28)@8
invExpXIsMax_uid29_fpDivTest_q <= not (redist12_expXIsMax_uid24_fpDivTest_q_8_q);
-- InvExpXIsZero_uid30_fpDivTest(LOGICAL,29)@8
InvExpXIsZero_uid30_fpDivTest_q <= not (redist13_excZ_x_uid23_fpDivTest_q_8_q);
-- excR_x_uid31_fpDivTest(LOGICAL,30)@8
excR_x_uid31_fpDivTest_q <= InvExpXIsZero_uid30_fpDivTest_q and invExpXIsMax_uid29_fpDivTest_q;
-- excXRYROvf_uid91_fpDivTest(LOGICAL,90)@8
excXRYROvf_uid91_fpDivTest_q <= excR_x_uid31_fpDivTest_q and excR_y_uid45_fpDivTest_q and expOvf_uid84_fpDivTest_n;
-- excXRYZ_uid90_fpDivTest(LOGICAL,89)@8
excXRYZ_uid90_fpDivTest_q <= excR_x_uid31_fpDivTest_q and redist10_excZ_y_uid37_fpDivTest_q_8_q;
-- excRInf_uid94_fpDivTest(LOGICAL,93)@8
excRInf_uid94_fpDivTest_q <= excXRYZ_uid90_fpDivTest_q or excXRYROvf_uid91_fpDivTest_q or excXIYZ_uid92_fpDivTest_q or excXIYR_uid93_fpDivTest_q;
-- xRegOrZero_uid87_fpDivTest(LOGICAL,86)@8
xRegOrZero_uid87_fpDivTest_q <= excR_x_uid31_fpDivTest_q or redist13_excZ_x_uid23_fpDivTest_q_8_q;
-- regOrZeroOverInf_uid88_fpDivTest(LOGICAL,87)@8
regOrZeroOverInf_uid88_fpDivTest_q <= xRegOrZero_uid87_fpDivTest_q and excI_y_uid41_fpDivTest_q;
-- expUdf_uid81_fpDivTest(COMPARE,80)@8
expUdf_uid81_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00000000000" & GND_q));
expUdf_uid81_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((12 downto 11 => expRExt_uid80_fpDivTest_b(10)) & expRExt_uid80_fpDivTest_b));
expUdf_uid81_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid81_fpDivTest_a) - SIGNED(expUdf_uid81_fpDivTest_b));
expUdf_uid81_fpDivTest_n(0) <= not (expUdf_uid81_fpDivTest_o(12));
-- regOverRegWithUf_uid86_fpDivTest(LOGICAL,85)@8
regOverRegWithUf_uid86_fpDivTest_q <= expUdf_uid81_fpDivTest_n and excR_x_uid31_fpDivTest_q and excR_y_uid45_fpDivTest_q;
-- zeroOverReg_uid85_fpDivTest(LOGICAL,84)@8
zeroOverReg_uid85_fpDivTest_q <= redist13_excZ_x_uid23_fpDivTest_q_8_q and excR_y_uid45_fpDivTest_q;
-- excRZero_uid89_fpDivTest(LOGICAL,88)@8
excRZero_uid89_fpDivTest_q <= zeroOverReg_uid85_fpDivTest_q or regOverRegWithUf_uid86_fpDivTest_q or regOrZeroOverInf_uid88_fpDivTest_q;
-- concExc_uid98_fpDivTest(BITJOIN,97)@8
concExc_uid98_fpDivTest_q <= excRNaN_uid97_fpDivTest_q & excRInf_uid94_fpDivTest_q & excRZero_uid89_fpDivTest_q;
-- excREnc_uid99_fpDivTest(LOOKUP,98)@8
excREnc_uid99_fpDivTest_combproc: PROCESS (concExc_uid98_fpDivTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExc_uid98_fpDivTest_q) IS
WHEN "000" => excREnc_uid99_fpDivTest_q <= "01";
WHEN "001" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "010" => excREnc_uid99_fpDivTest_q <= "10";
WHEN "011" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "100" => excREnc_uid99_fpDivTest_q <= "11";
WHEN "101" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "110" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "111" => excREnc_uid99_fpDivTest_q <= "00";
WHEN OTHERS => -- unreachable
excREnc_uid99_fpDivTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExc_uid107_fpDivTest(MUX,106)@8
expRPostExc_uid107_fpDivTest_s <= excREnc_uid99_fpDivTest_q;
expRPostExc_uid107_fpDivTest_combproc: PROCESS (expRPostExc_uid107_fpDivTest_s, cstAllZWE_uid20_fpDivTest_q, excRPreExc_uid79_fpDivTest_b, cstAllOWE_uid18_fpDivTest_q)
BEGIN
CASE (expRPostExc_uid107_fpDivTest_s) IS
WHEN "00" => expRPostExc_uid107_fpDivTest_q <= cstAllZWE_uid20_fpDivTest_q;
WHEN "01" => expRPostExc_uid107_fpDivTest_q <= excRPreExc_uid79_fpDivTest_b;
WHEN "10" => expRPostExc_uid107_fpDivTest_q <= cstAllOWE_uid18_fpDivTest_q;
WHEN "11" => expRPostExc_uid107_fpDivTest_q <= cstAllOWE_uid18_fpDivTest_q;
WHEN OTHERS => expRPostExc_uid107_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- oneFracRPostExc2_uid100_fpDivTest(CONSTANT,99)
oneFracRPostExc2_uid100_fpDivTest_q <= "00000000000000000000001";
-- fracRPreExc_uid78_fpDivTest(BITSELECT,77)@8
fracRPreExc_uid78_fpDivTest_in <= expFracPostRnd_uid76_fpDivTest_q(23 downto 0);
fracRPreExc_uid78_fpDivTest_b <= fracRPreExc_uid78_fpDivTest_in(23 downto 1);
-- fracRPostExc_uid103_fpDivTest(MUX,102)@8
fracRPostExc_uid103_fpDivTest_s <= excREnc_uid99_fpDivTest_q;
fracRPostExc_uid103_fpDivTest_combproc: PROCESS (fracRPostExc_uid103_fpDivTest_s, paddingY_uid15_fpDivTest_q, fracRPreExc_uid78_fpDivTest_b, oneFracRPostExc2_uid100_fpDivTest_q)
BEGIN
CASE (fracRPostExc_uid103_fpDivTest_s) IS
WHEN "00" => fracRPostExc_uid103_fpDivTest_q <= paddingY_uid15_fpDivTest_q;
WHEN "01" => fracRPostExc_uid103_fpDivTest_q <= fracRPreExc_uid78_fpDivTest_b;
WHEN "10" => fracRPostExc_uid103_fpDivTest_q <= paddingY_uid15_fpDivTest_q;
WHEN "11" => fracRPostExc_uid103_fpDivTest_q <= oneFracRPostExc2_uid100_fpDivTest_q;
WHEN OTHERS => fracRPostExc_uid103_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- divR_uid110_fpDivTest(BITJOIN,109)@8
divR_uid110_fpDivTest_q <= sRPostExc_uid109_fpDivTest_q & expRPostExc_uid107_fpDivTest_q & fracRPostExc_uid103_fpDivTest_q;
-- xOut(GPOUT,4)@8
q <= divR_uid110_fpDivTest_q;
END normal;
|
mit
|
cfbe904cfa83f5fd187477c55cdf3681
| 0.716146 | 3.299354 | false | true | false | false |
Jawanga/ece385final
|
simulation/modelsim/finalproject/altera_merlin_slave_agent/_primary.vhd
| 1 | 6,876 |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_slave_agent is
generic(
PKT_BEGIN_BURST : integer := 81;
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_LOCK : integer := 87;
PKT_TRANS_COMPRESSED_READ: integer := 67;
PKT_TRANS_POSTED: integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H: integer := 86;
PKT_PROTECTION_L: integer := 86;
PKT_RESPONSE_STATUS_H: integer := 89;
PKT_RESPONSE_STATUS_L: integer := 88;
PKT_BURST_SIZE_H: integer := 92;
PKT_BURST_SIZE_L: integer := 90;
PKT_ORI_BURST_SIZE_L: integer := 93;
PKT_ORI_BURST_SIZE_H: integer := 95;
ST_DATA_W : integer := 96;
ST_CHANNEL_W : integer := 32;
ADDR_W : vl_notype;
AVS_DATA_W : vl_notype;
AVS_BURSTCOUNT_W: integer := 4;
PKT_SYMBOLS : vl_notype;
PREVENT_FIFO_OVERFLOW: integer := 0;
SUPPRESS_0_BYTEEN_CMD: integer := 1;
USE_READRESPONSE: integer := 0;
USE_WRITERESPONSE: integer := 0;
AVS_BE_W : vl_notype;
BURST_SIZE_W : integer := 3;
FIFO_DATA_W : vl_notype
);
port(
clk : in vl_logic;
reset : in vl_logic;
m0_address : out vl_logic_vector;
m0_burstcount : out vl_logic_vector;
m0_byteenable : out vl_logic_vector;
m0_read : out vl_logic;
m0_readdata : in vl_logic_vector;
m0_waitrequest : in vl_logic;
m0_write : out vl_logic;
m0_writedata : out vl_logic_vector;
m0_readdatavalid: in vl_logic;
m0_debugaccess : out vl_logic;
m0_lock : out vl_logic;
m0_response : in vl_logic_vector(1 downto 0);
m0_writeresponsevalid: in vl_logic;
rf_source_data : out vl_logic_vector;
rf_source_valid : out vl_logic;
rf_source_startofpacket: out vl_logic;
rf_source_endofpacket: out vl_logic;
rf_source_ready : in vl_logic;
rf_sink_data : in vl_logic_vector;
rf_sink_valid : in vl_logic;
rf_sink_startofpacket: in vl_logic;
rf_sink_endofpacket: in vl_logic;
rf_sink_ready : out vl_logic;
rdata_fifo_src_data: out vl_logic_vector;
rdata_fifo_src_valid: out vl_logic;
rdata_fifo_src_ready: in vl_logic;
rdata_fifo_sink_data: in vl_logic_vector;
rdata_fifo_sink_valid: in vl_logic;
rdata_fifo_sink_ready: out vl_logic;
cp_ready : out vl_logic;
cp_valid : in vl_logic;
cp_data : in vl_logic_vector;
cp_channel : in vl_logic_vector;
cp_startofpacket: in vl_logic;
cp_endofpacket : in vl_logic;
rp_ready : in vl_logic;
rp_valid : out vl_logic;
rp_data : out vl_logic_vector;
rp_startofpacket: out vl_logic;
rp_endofpacket : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of PKT_BEGIN_BURST : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_H : constant is 1;
attribute mti_svvh_generic_type of PKT_DATA_L : constant is 1;
attribute mti_svvh_generic_type of PKT_SYMBOL_W : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTEEN_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTEEN_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_H : constant is 1;
attribute mti_svvh_generic_type of PKT_ADDR_L : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_LOCK : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_COMPRESSED_READ : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_POSTED : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_WRITE : constant is 1;
attribute mti_svvh_generic_type of PKT_TRANS_READ : constant is 1;
attribute mti_svvh_generic_type of PKT_SRC_ID_H : constant is 1;
attribute mti_svvh_generic_type of PKT_SRC_ID_L : constant is 1;
attribute mti_svvh_generic_type of PKT_DEST_ID_H : constant is 1;
attribute mti_svvh_generic_type of PKT_DEST_ID_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BURSTWRAP_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BURSTWRAP_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTE_CNT_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BYTE_CNT_L : constant is 1;
attribute mti_svvh_generic_type of PKT_PROTECTION_H : constant is 1;
attribute mti_svvh_generic_type of PKT_PROTECTION_L : constant is 1;
attribute mti_svvh_generic_type of PKT_RESPONSE_STATUS_H : constant is 1;
attribute mti_svvh_generic_type of PKT_RESPONSE_STATUS_L : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_SIZE_H : constant is 1;
attribute mti_svvh_generic_type of PKT_BURST_SIZE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ORI_BURST_SIZE_L : constant is 1;
attribute mti_svvh_generic_type of PKT_ORI_BURST_SIZE_H : constant is 1;
attribute mti_svvh_generic_type of ST_DATA_W : constant is 1;
attribute mti_svvh_generic_type of ST_CHANNEL_W : constant is 1;
attribute mti_svvh_generic_type of ADDR_W : constant is 3;
attribute mti_svvh_generic_type of AVS_DATA_W : constant is 3;
attribute mti_svvh_generic_type of AVS_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of PKT_SYMBOLS : constant is 3;
attribute mti_svvh_generic_type of PREVENT_FIFO_OVERFLOW : constant is 1;
attribute mti_svvh_generic_type of SUPPRESS_0_BYTEEN_CMD : constant is 1;
attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1;
attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1;
attribute mti_svvh_generic_type of AVS_BE_W : constant is 3;
attribute mti_svvh_generic_type of BURST_SIZE_W : constant is 1;
attribute mti_svvh_generic_type of FIFO_DATA_W : constant is 3;
end altera_merlin_slave_agent;
|
apache-2.0
|
d3fb122439a775868b57723fa760c154
| 0.60733 | 3.438 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_data_s8_diff.vhd
| 1 | 16,223 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_data_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic 1:n data receiver module with differential inputs
-- Takes in 1 bit of differential data and deserialises this to n bits
-- data is received LSB first
-- Serial input words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Parallel output word
-- DS, DS-1 ..... 1, 0
--
-- Includes state machine to control CAL and the phase detector
-- Data inversion can be accomplished via the RX_RX_SWAP_MASK
-- parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_data_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16 ; -- Set the number of inputs and outputs
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
use_phase_detector : in std_logic ; -- Set generation of phase detector logic
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclk : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
debug_in : in std_logic_vector(1 downto 0) ; -- input debug data
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end serdes_1_to_n_data_s8_diff ;
architecture arch_serdes_1_to_n_data_s8_diff of serdes_1_to_n_data_s8_diff is
signal ddly_m : std_logic_vector(D-1 downto 0) ; -- Master output from IODELAY1
signal ddly_s : std_logic_vector(D-1 downto 0) ; -- Slave output from IODELAY1
signal cascade : std_logic_vector(D-1 downto 0) ;
signal busys : std_logic_vector(D-1 downto 0) ;
signal rx_data_in : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_fix : std_logic_vector(D-1 downto 0) ;
signal state : integer range 0 to 8 ;
signal busyd : std_logic_vector(D-1 downto 0) ;
signal cal_data_sint : std_logic ;
signal ce_data_inta : std_logic ;
signal busy_data : std_logic_vector(D-1 downto 0) ;
signal busy_data_d : std_logic ;
signal counter : std_logic_vector(8 downto 0) ;
signal enable : std_logic ;
signal pd_edge : std_logic_vector(D-1 downto 0) ;
signal cal_data_slave : std_logic ;
signal cal_data_master : std_logic ;
signal valid_data : std_logic_vector(D-1 downto 0) ;
signal valid_data_d : std_logic ;
signal rst_data : std_logic ;
signal mdataout : std_logic_vector((8*D)-1 downto 0) ;
signal pdcounter : std_logic_vector(4 downto 0) ;
signal inc_data : std_logic ;
signal ce_data : std_logic_vector(D-1 downto 0) ;
signal inc_data_int : std_logic ;
signal incdec_data : std_logic_vector(D-1 downto 0) ;
signal incdec_data_d : std_logic ;
signal flag : std_logic ;
signal mux : std_logic_vector(D-1 downto 0) ;
signal incdec_data_or : std_logic_vector(D downto 0) ;
signal valid_data_or : std_logic_vector(D downto 0) ;
signal busy_data_or : std_logic_vector(D downto 0) ;
signal incdec_data_im : std_logic_vector(D-1 downto 0) ;
signal valid_data_im : std_logic_vector(D-1 downto 0) ;
signal all_ce : std_logic_vector(D-1 downto 0) ;
constant RX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
busy_data <= busys ;
debug <= mux & cal_data_master & rst_data & cal_data_slave & busy_data_d & inc_data & ce_data & valid_data_d & incdec_data_d ;
cal_data_slave <= cal_data_sint ;
process (gclk, reset)
begin
if reset = '1' then
state <= 0 ;
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
counter <= (others => '0') ;
enable <= '0' ;
counter <= (others => '0') ;
mux <= (0 => '1', others => '0') ;
elsif gclk'event and gclk = '1' then
counter <= counter + 1 ;
if counter(8) = '1' then
counter <= "000000000" ;
end if ;
if counter(5) = '1' then
enable <= '1' ;
end if ;
if state = 0 and enable = '1' then -- Wait for all IODELAYs to be available
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 1 ;
end if ;
elsif state = 1 then -- Issue calibrate command to both master and slave
cal_data_master <= '1' ;
cal_data_sint <= '1' ;
if busy_data_d = '1' then -- and wait for command to be accepted
state <= 2 ;
end if ;
elsif state = 2 then -- Now RST all master and slave IODELAYs
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
if busy_data_d = '0' then
rst_data <= '1' ;
state <= 3 ;
end if ;
elsif state = 3 then -- Wait for all IODELAYs to be available
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
elsif state = 4 then -- Hang around
if counter(8) = '1' then
state <= 5 ;
end if ;
elsif state = 5 then -- Calibrate slave only
if busy_data_d = '0' then
cal_data_sint <= '1' ;
state <= 6 ;
if D /= 1 then
mux <= mux(D-2 downto 0) & mux(D-1) ;
end if ;
end if ;
elsif state = 6 then -- Wait for command to be accepted
if busy_data_d = '1' then
cal_data_sint <= '0' ;
state <= 7 ;
end if ;
elsif state = 7 then -- Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
end if ;
end if ;
end process ;
process (gclk, reset)
begin
if reset = '1' then
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
flag <= '0' ;
elsif gclk'event and gclk = '1' then
busy_data_d <= busy_data_or(D) ;
if use_phase_detector = '1' then -- decide whther pd is used
incdec_data_d <= incdec_data_or(D) ;
valid_data_d <= valid_data_or(D) ;
if ce_data_inta = '1' then
ce_data <= mux ;
else
ce_data <= (others => '0') ;
end if ;
if state = 7 then
flag <= '0' ;
elsif state /= 4 or busy_data_d = '1' then -- Reset filter if state machine issues a cal command or unit is busy
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
elsif pdcounter = "11111" and flag = '0' then -- Filter has reached positive max - increment the tap count
ce_data_inta <= '1' ;
inc_data_int <= '1' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif pdcounter = "00000" and flag = '0' then -- Filter has reached negative max - decrement the tap count
ce_data_inta <= '1' ;
inc_data_int <= '0' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif valid_data_d = '1' then -- increment filter
ce_data_inta <= '0' ;
if incdec_data_d = '1' and pdcounter /= "11111" then
pdcounter <= pdcounter + 1 ;
elsif incdec_data_d = '0' and pdcounter /= "00000" then -- decrement filter
pdcounter <= pdcounter - 1 ;
end if ;
else
ce_data_inta <= '0' ;
end if ;
else
ce_data <= all_ce ;
inc_data_int <= debug_in(1) ;
end if ;
end if ;
end process ;
inc_data <= inc_data_int ;
incdec_data_or(0) <= '0' ; -- Input Mux - Initialise generate loop OR gates
valid_data_or(0) <= '0' ;
busy_data_or(0) <= '0' ;
loop0 : for i in 0 to (D - 1) generate
incdec_data_im(i) <= incdec_data(i) and mux(i) ; -- Input muxes
incdec_data_or(i+1) <= incdec_data_im(i) or incdec_data_or(i) ; -- AND gates to allow just one signal through at a tome
valid_data_im(i) <= valid_data(i) and mux(i) ; -- followed by an OR
valid_data_or(i+1) <= valid_data_im(i) or valid_data_or(i) ; -- for the three inputs from each PD
busy_data_or(i+1) <= busy_data(i) or busy_data_or(i) ; -- The busy signals just need an OR gate
all_ce(i) <= debug_in(0) ;
rx_data_in_fix(i) <= rx_data_in(i) xor RX_SWAP_MASK(i) ; -- Invert signals as required
iob_clk_in : IBUFDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => datain_p(i),
IB => datain_n(i),
O => rx_data_in(i));
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND" , -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN" , -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_slave, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i) , -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busys(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => pd_edge(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => valid_data(i),
INCDEC => incdec_data(i),
SHIFTOUT => cascade(i));
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => cascade(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+3),
Q3 => mdataout((8*i)+2),
Q2 => mdataout((8*i)+1),
Q1 => mdataout((8*i)+0),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge(i));
loop1 : for j in 7 downto (8-S) generate
data_out(((D*(j+S-8))+i)) <= mdataout((8*i)+j) ;
end generate ;
end generate ;
end arch_serdes_1_to_n_data_s8_diff ;
|
apache-2.0
|
184a44adb5b37adca092ac62fde3306d
| 0.589657 | 2.984364 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASliceOfReg1a.vhd
| 1 | 1,736 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Register where slices of next signal are set conditionally in multiple branches
--
ENTITY AssignToASliceOfReg1a IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg1a IS
SIGNAL r : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL r_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"0000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_15downto8 & r_next_7downto0;
assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, data_in_vld, r)
BEGIN
IF data_in_vld = '1' AND data_in_addr = "0" THEN
r_next_7downto0 <= data_in_data(7 DOWNTO 0);
r_next_15downto8 <= data_in_data(15 DOWNTO 8);
ELSIF data_in_vld = '1' AND data_in_addr = "1" THEN
r_next_7downto0 <= data_in_data(15 DOWNTO 8);
r_next_15downto8 <= data_in_data(7 DOWNTO 0);
ELSE
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_7downto0 <= r(7 DOWNTO 0);
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
6654a0274905f68c3b982c3cdb388e03
| 0.581221 | 3.214815 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASliceOfReg3c.vhd
| 1 | 2,421 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Something not assigned by index at the beggining and then whole signal assigned.
--
ENTITY AssignToASliceOfReg3c IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_mask : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg3c IS
SIGNAL r : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000";
SIGNAL r_next : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_23downto16 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_31downto24 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"00000000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_31downto24 & r_next_23downto16 & r_next_15downto8 & r_next_7downto0;
assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, r)
BEGIN
CASE data_in_addr IS
WHEN "01" =>
r_next_15downto8 <= data_in_data;
r_next_23downto16 <= r(23 DOWNTO 16);
r_next_31downto24 <= r(31 DOWNTO 24);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN "10" =>
r_next_23downto16 <= data_in_data;
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_31downto24 <= r(31 DOWNTO 24);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN "11" =>
r_next_31downto24 <= data_in_data;
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_23downto16 <= r(23 DOWNTO 16);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN OTHERS =>
r_next_7downto0 <= X"7B";
r_next_15downto8 <= X"00";
r_next_23downto16 <= X"00";
r_next_31downto24 <= X"00";
END CASE;
END PROCESS;
END ARCHITECTURE;
|
mit
|
cc51bd428fe96b46bda99ee10d9cd44c
| 0.546055 | 3.353186 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/lfsr/lfsr.vhd
| 1 | 1,385 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lfsr is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic
);
end entity lfsr;
architecture lfsr_arch of lfsr is
signal random_data: std_logic_vector(31 downto 0);
signal cs: std_logic;
begin
process(address) is
begin
if unsigned(address) = BASE_ADDRESS then
cs <= '1';
else
cs <= '0';
end if;
end process;
-- base lfsr
process(clk) is
variable q: unsigned(31 downto 0);
variable xored: std_logic;
begin
if rising_edge(clk) then
if res = '1' then
q := x"00000001";
else
xored := q(0) xor q(1) xor q(21) xor q(31);
q(31 downto 0) := q(30 downto 0) & xored;
end if;
end if;
random_data <= std_logic_vector(q);
end process;
data_miso <= random_data when (RD = '1' and cs = '1') else (others => 'Z');
ack <= '1' when (RD = '1' and cs = '1') else '0';
end architecture;
|
mit
|
bc47789be016143a51bd608b86ca13cd
| 0.535018 | 3.394608 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/statements/SimpleIfStatementPartialOverrideNopVal.vhd
| 1 | 958 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY SimpleIfStatementPartialOverrideNopVal IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD_LOGIC;
clk : IN STD_LOGIC;
e : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleIfStatementPartialOverrideNopVal IS
SIGNAL d : STD_LOGIC;
SIGNAL d_next : STD_LOGIC;
BEGIN
assig_process_d: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
d <= d_next;
END IF;
END PROCESS;
assig_process_d_next: PROCESS(a, b, c, d)
BEGIN
IF a = '1' THEN
IF b = '1' THEN
d_next <= '1';
ELSE
d_next <= d;
END IF;
IF c = '1' THEN
d_next <= '0';
END IF;
ELSE
d_next <= d;
END IF;
END PROCESS;
e <= d;
END ARCHITECTURE;
|
mit
|
f964e578be904028050fa4133cce976e
| 0.495825 | 3.561338 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASliceOfReg3b.vhd
| 1 | 2,419 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Something not assigned by index in the middle and then whole signal assigned.
--
ENTITY AssignToASliceOfReg3b IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_mask : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg3b IS
SIGNAL r : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000";
SIGNAL r_next : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_23downto16 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_31downto24 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"00000000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_31downto24 & r_next_23downto16 & r_next_15downto8 & r_next_7downto0;
assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, r)
BEGIN
CASE data_in_addr IS
WHEN "00" =>
r_next_7downto0 <= data_in_data;
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_23downto16 <= r(23 DOWNTO 16);
r_next_31downto24 <= r(31 DOWNTO 24);
WHEN "10" =>
r_next_23downto16 <= data_in_data;
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_31downto24 <= r(31 DOWNTO 24);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN "11" =>
r_next_31downto24 <= data_in_data;
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_23downto16 <= r(23 DOWNTO 16);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN OTHERS =>
r_next_7downto0 <= X"7B";
r_next_15downto8 <= X"00";
r_next_23downto16 <= X"00";
r_next_31downto24 <= X"00";
END CASE;
END PROCESS;
END ARCHITECTURE;
|
mit
|
f4a83d16554b833610b936c1e17eaeb9
| 0.54568 | 3.359722 | false | false | false | false |
nanomolina/MIPS
|
DATAPATH/dmem.vhd
| 1 | 2,219 |
-------------------------------------------------------------------------------
--
-- Title : dmem
-- Design : Mips
-- Author : Eduardo Sanchez
-- Company : Famaf
--
-------------------------------------------------------------------------------
--
-- File : dmem.vhd
--
-------------------------------------------------------------------------------
--
-- Description : Archivo con el diseño de la memoria RAM del procesador MIPS.
-- Para mantener un diseño corto, la memoria solo contiene 64 palabras de
-- 32 bits c/u (aunque podria direccionar mas memoria)
-- dump: si esta señal esta activa (1), se copia le contenido de la memoria
-- en el archivo de salida DUMP (para su posterior revision).
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_SIGNED.all;
--library WORK;
--use WORK.components.all;
entity dmem is -- data memory
port(clk, we: in STD_LOGIC;
a, wd: in STD_LOGIC_VECTOR(31 downto 0);
rd: out STD_LOGIC_VECTOR(31 downto 0);
dump: in STD_LOGIC
);
end;
architecture behave of dmem is
constant MEMORY_DUMP_FILE: string := "output.dump";
constant MAX_BOUND: Integer := 64;
type ramtype is array (MAX_BOUND-1 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
signal mem: ramtype;
procedure memDump is
file dumpfile : text open write_mode is MEMORY_DUMP_FILE;
variable dumpline : line;
variable i: natural := 0;
begin
write(dumpline, string'("Memoria RAM de Mips:"));
writeline(dumpfile,dumpline);
write(dumpline, string'("Address Data"));
writeline(dumpfile,dumpline);
while i <= MAX_BOUND-1 loop
write(dumpline, i);
write(dumpline, string'(" "));
write(dumpline, conv_integer(mem(i)));
writeline(dumpfile,dumpline);
i:=i+1;
end loop;
end procedure memDump;
begin
process(clk, a, mem)
begin
if clk'event and clk = '1' and we = '1' then
mem(conv_integer(a(7 downto 2))) <= wd;
end if;
rd <= mem(conv_integer(a(7 downto 2))); -- word aligned
end process;
process(dump)
begin
if dump = '1' then
memDump;
end if;
end process;
end;
|
gpl-3.0
|
7b81ca0502deb2ac5942f42ca89c02fc
| 0.557008 | 3.812715 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/BUFIO2 DDR/top_nto1_ddr_diff_tx.vhd
| 1 | 7,838 |
------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_ddr_diff_tx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example differential output transmitter for DDR clock and data using 2 x BUFIO2
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------/
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and signalulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_ddr_diff_tx is port (
reset : in std_logic ; -- reset (active high)
refclkin_p, refclkin_n : in std_logic ; -- frequency generator clock input
dataout_p, dataout_n : out std_logic_vector(7 downto 0) ; -- differential data outputs
clkout_p, clkout_n : out std_logic ) ; -- differential clock output
end top_nto1_ddr_diff_tx ;
architecture arch_top_nto1_ddr_diff_tx of top_nto1_ddr_diff_tx is
component clock_generator_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclkap : out std_logic ; -- A P ioclock from BUFIO2
ioclkan : out std_logic ; -- A N ioclock from BUFIO2
serdesstrobea : out std_logic ; -- A serdes strobe from BUFIO2
ioclkbp : out std_logic ; -- B P ioclock from BUFIO2 - leave open if not required
ioclkbn : out std_logic ; -- B N ioclock from BUFIO2 - leave open if not required
serdesstrobeb : out std_logic ; -- B serdes strobe from BUFIO2 - leave open if not required
gclk : out std_logic) ; -- global clock output from BUFIO2
end component ;
component serdes_n_to_1_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclkp : in std_logic ; -- IO Clock network
txioclkn : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end component ;
-- Parameters for serdes factor and number of IO pins
constant S : integer := 8 ; -- Set the serdes factor
constant D : integer := 8 ; -- Set the number of inputs and outputs
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal rst : std_logic ;
signal txd : std_logic_vector(DS downto 0) ; -- Registered Data to serdeses
signal txioclkp : std_logic ;
signal txioclkn : std_logic ;
signal tx_serdesstrobe : std_logic ;
signal tx_bufg_x1 : std_logic ;
signal clkoutp : std_logic_vector(0 downto 0) ;
signal clkoutn : std_logic_vector(0 downto 0) ;
-- Parameters for clock generation
constant TX_CLK_GEN : std_logic_vector(S-1 downto 0) := X"AA" ; -- Transmit a constant to make a clock
begin
rst <= reset ;
-- Reference Clock Input genertaes IO clocks via 2 x BUFIO2
inst_clkgen : clock_generator_ddr_s8_diff generic map(
S => S)
port map(
clkin_p => refclkin_p,
clkin_n => refclkin_n,
ioclkap => txioclkp,
ioclkan => txioclkn,
serdesstrobea => tx_serdesstrobe,
ioclkbp => open,
ioclkbn => open,
serdesstrobeb => open,
gclk => tx_bufg_x1) ;
process (tx_bufg_x1, rst) -- Generate some data to transmit
begin
if rst = '1' then
txd <= X"3000000000000001" ;
elsif tx_bufg_x1'event and tx_bufg_x1 = '1' then
txd <= txd(63 downto 60) & txd(58 downto 0) & txd(59) ;
end if ;
end process ;
-- Transmitter Logic - Instantiate serialiser to generate forwarded clock
inst_clkout : serdes_n_to_1_ddr_s8_diff generic map(
S => S,
D => 1)
port map (
dataout_p => clkoutp,
dataout_n => clkoutn,
txioclkp => txioclkp,
txioclkn => txioclkn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => TX_CLK_GEN); -- Transmit a constant to make the clock
clkout_p <= clkoutp(0) ;
clkout_n <= clkoutn(0) ;
-- Instantiate Outputs and output serialisers for output data lines
inst_dataout : serdes_n_to_1_ddr_s8_diff generic map(
S => S,
D => D)
port map (
dataout_p => dataout_p,
dataout_n => dataout_n,
txioclkp => txioclkp,
txioclkn => txioclkn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => txd);
end arch_top_nto1_ddr_diff_tx ;
|
apache-2.0
|
ac440151f2cfad58dc24a9ff4c0fb4b4
| 0.603215 | 3.602022 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/finalproject/altera_merlin_slave_translator/_primary.vhd
| 1 | 4,900 |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_slave_translator is
generic(
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W: integer := 4;
AV_READLATENCY : integer := 1;
AV_READ_WAIT_CYCLES: integer := 0;
AV_WRITE_WAIT_CYCLES: integer := 0;
AV_SETUP_WAIT_CYCLES: integer := 0;
AV_DATA_HOLD_CYCLES: integer := 0;
USE_READDATAVALID: integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE: integer := 0;
USE_WRITERESPONSE: integer := 0;
AV_SYMBOLS_PER_WORD: integer := 4;
AV_ADDRESS_SYMBOLS: integer := 0;
AV_BURSTCOUNT_SYMBOLS: integer := 0;
BITS_PER_WORD : vl_notype;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W: integer := 10;
UAV_DATA_W : integer := 32;
AV_CONSTANT_BURST_BEHAVIOR: integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR: integer := 0;
CHIPSELECT_THROUGH_READLATENCY: integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES: integer := 0
);
port(
clk : in vl_logic;
reset : in vl_logic;
uav_address : in vl_logic_vector;
uav_writedata : in vl_logic_vector;
uav_write : in vl_logic;
uav_read : in vl_logic;
uav_burstcount : in vl_logic_vector;
uav_byteenable : in vl_logic_vector;
uav_lock : in vl_logic;
uav_debugaccess : in vl_logic;
uav_clken : in vl_logic;
uav_readdatavalid: out vl_logic;
uav_waitrequest : out vl_logic;
uav_readdata : out vl_logic_vector;
uav_response : out vl_logic_vector(1 downto 0);
uav_writeresponsevalid: out vl_logic;
av_address : out vl_logic_vector;
av_writedata : out vl_logic_vector;
av_write : out vl_logic;
av_read : out vl_logic;
av_burstcount : out vl_logic_vector;
av_byteenable : out vl_logic_vector;
av_writebyteenable: out vl_logic_vector;
av_begintransfer: out vl_logic;
av_chipselect : out vl_logic;
av_beginbursttransfer: out vl_logic;
av_lock : out vl_logic;
av_clken : out vl_logic;
av_debugaccess : out vl_logic;
av_outputenable : out vl_logic;
av_readdata : in vl_logic_vector;
av_readdatavalid: in vl_logic;
av_waitrequest : in vl_logic;
av_response : in vl_logic_vector(1 downto 0);
av_writeresponsevalid: in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of AV_DATA_W : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of AV_BYTEENABLE_W : constant is 1;
attribute mti_svvh_generic_type of UAV_BYTEENABLE_W : constant is 1;
attribute mti_svvh_generic_type of AV_READLATENCY : constant is 1;
attribute mti_svvh_generic_type of AV_READ_WAIT_CYCLES : constant is 1;
attribute mti_svvh_generic_type of AV_WRITE_WAIT_CYCLES : constant is 1;
attribute mti_svvh_generic_type of AV_SETUP_WAIT_CYCLES : constant is 1;
attribute mti_svvh_generic_type of AV_DATA_HOLD_CYCLES : constant is 1;
attribute mti_svvh_generic_type of USE_READDATAVALID : constant is 1;
attribute mti_svvh_generic_type of USE_WAITREQUEST : constant is 1;
attribute mti_svvh_generic_type of USE_READRESPONSE : constant is 1;
attribute mti_svvh_generic_type of USE_WRITERESPONSE : constant is 1;
attribute mti_svvh_generic_type of AV_SYMBOLS_PER_WORD : constant is 1;
attribute mti_svvh_generic_type of AV_ADDRESS_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of AV_BURSTCOUNT_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_WORD : constant is 3;
attribute mti_svvh_generic_type of UAV_ADDRESS_W : constant is 1;
attribute mti_svvh_generic_type of UAV_BURSTCOUNT_W : constant is 1;
attribute mti_svvh_generic_type of UAV_DATA_W : constant is 1;
attribute mti_svvh_generic_type of AV_CONSTANT_BURST_BEHAVIOR : constant is 1;
attribute mti_svvh_generic_type of UAV_CONSTANT_BURST_BEHAVIOR : constant is 1;
attribute mti_svvh_generic_type of CHIPSELECT_THROUGH_READLATENCY : constant is 1;
attribute mti_svvh_generic_type of USE_UAV_CLKEN : constant is 1;
attribute mti_svvh_generic_type of AV_REQUIRE_UNALIGNED_ADDRESSES : constant is 1;
end altera_merlin_slave_translator;
|
apache-2.0
|
7754941bc42b921304ddcffed9dd2d98
| 0.619796 | 3.706505 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/rtlLvl/ComplexConditions.vhd
| 1 | 2,297 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ComplexConditions IS
PORT(
clk : IN STD_LOGIC;
ctrlFifoLast : IN STD_LOGIC;
ctrlFifoVld : IN STD_LOGIC;
rst : IN STD_LOGIC;
s_idle : OUT STD_LOGIC;
sd0 : IN STD_LOGIC;
sd1 : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF ComplexConditions IS
TYPE t_state IS (idle, tsWait, ts0Wait, ts1Wait, lenExtr);
SIGNAL st : t_state := idle;
SIGNAL st_next : t_state;
BEGIN
s_idle <= '1' WHEN (st = idle) ELSE '0';
assig_process_st: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
st <= idle;
ELSE
st <= st_next;
END IF;
END IF;
END PROCESS;
assig_process_st_next: PROCESS(ctrlFifoLast, ctrlFifoVld, sd0, sd1, st)
BEGIN
CASE st IS
WHEN idle =>
IF (sd0 AND sd1) = '1' THEN
st_next <= lenextr;
ELSIF sd0 = '1' THEN
st_next <= ts1wait;
ELSIF sd1 = '1' THEN
st_next <= ts0wait;
ELSIF ctrlFifoVld = '1' THEN
st_next <= tswait;
ELSE
st_next <= st;
END IF;
WHEN tswait =>
IF (sd0 AND sd1) = '1' THEN
st_next <= lenextr;
ELSIF sd0 = '1' THEN
st_next <= ts1wait;
ELSIF sd1 = '1' THEN
st_next <= ts0wait;
ELSE
st_next <= st;
END IF;
WHEN ts0wait =>
IF sd0 = '1' THEN
st_next <= lenextr;
ELSE
st_next <= st;
END IF;
WHEN ts1wait =>
IF sd1 = '1' THEN
st_next <= lenextr;
ELSE
st_next <= st;
END IF;
WHEN OTHERS =>
IF (ctrlFifoVld AND ctrlFifoLast) = '1' THEN
st_next <= idle;
ELSE
st_next <= st;
END IF;
END CASE;
END PROCESS;
END ARCHITECTURE;
|
mit
|
8524ce4bdfdade8d7e607858d02f6447
| 0.417501 | 4.146209 | false | false | false | false |
elahejalalpour/CoDesign
|
Phase-1/hea/hea_tb.vhd
| 1 | 2,134 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:52:28 06/27/2015
-- Design Name:
-- Module Name: hea_tb.vhd
-- Project Name: adder
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: hea
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY hea_tb IS
END hea_tb;
ARCHITECTURE behavior OF hea_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hea
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
s : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal s : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hea PORT MAP (
a => a,
b => b,
s => s
);
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
a<="1010";
b<="0110";
wait for 10 ns;
a<="0011";
b<="1000";
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
6800e1b2a91db63ceaeeacc6e2989847
| 0.550609 | 3.930018 | false | true | false | false |
nanomolina/MIPS
|
prueba/writeback.vhd
| 2 | 720 |
library ieee;
use ieee.std_logic_1164.all;
entity writeback is
port(
AluOutW, ReadDataW: in std_logic_vector(31 downto 0);
MemToReg: in std_logic;
ResultW: out std_logic_vector(31 downto 0));
end entity;
architecture wb_arq of writeback is
component mux2
generic (MAX : integer := 32);
port (
d0, d1: in std_logic_vector((MAX-1) downto 0);
s: in std_logic;
y: out std_logic_vector((MAX-1) downto 0));
end component;
begin
mux2_1: mux2 port map (
d0 => AluOutW,
d1 => ReadDataW,
s => MemToReg,
y => ResultW); --salida
end architecture;
|
gpl-3.0
|
3c7ee6a62e226abfa09129eb483042f7
| 0.531944 | 3.850267 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/MARK_II.vhd
| 1 | 14,985 |
-- Top level entity, MARK_II SoC
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MARK_II is
port(
--rs232
uart1_rts: out std_logic:= '1';
uart1_txd: out std_logic:= '1';
uart1_dtr: out std_logic:= '1';
uart1_dcd: in std_logic;
uart1_dsr: in std_logic;
uart1_rxd: in std_logic;
uart1_cts: in std_logic;
uart1_ri: in std_logic;
--vga
vga_hs: out std_logic:= '0';
vga_vs: out std_logic:= '0';
vga_r: out std_logic_vector(2 downto 0):= "000";
vga_g: out std_logic_vector(2 downto 0):= "000";
vga_b: out std_logic_vector(1 downto 0):= "00";
--ps2 keyboard
kb_clk: in std_logic;
kb_dat: in std_logic;
--ps2 mouse
ms_clk: in std_logic;
ms_dat: in std_logic;
--debug uart
uart0_txd: out std_logic:= '1';
uart0_rxd: in std_logic;
uart0_cbus: in std_logic_vector(1 downto 0);
--ethernet
enc_int: in std_logic;
enc_cs: out std_logic:= '1';
enc_si: out std_logic:= '0';
enc_so: in std_logic;
enc_sck: out std_logic:= '0';
--audio
i2s_bck: out std_logic:= '0';
i2s_din: out std_logic:= '0';
i2s_lrck: out std_logic:= '0';
--i2c devices
scl: inout std_logic:= 'Z';
sda: inout std_logic:= 'Z';
--rtc
rtc_mfp: in std_logic;
--microSD
sd_dat: inout std_logic_vector(3 downto 0):= "ZZZZ";
sd_cmd: out std_logic:= '0';
sd_clk: out std_logic:= '0';
--flash
flash_cs: out std_logic:= '0';
flash_sck: out std_logic:= '0';
flash_so: in std_logic;
flash_si: out std_logic:= '0';
--sdram
sdram_a: out std_logic_vector(12 downto 0):= '0' & x"000";
sdram_dq: inout std_logic_vector(7 downto 0):= "ZZZZZZZZ";
sdram_ba: out std_logic_vector(1 downto 0):= "00";
sdram_ras: out std_logic:= '0';
sdram_cas: out std_logic:= '0';
sdram_we: out std_logic:= '0';
sdram_clk: out std_logic:= '0';
--expansion
ex_cmd: out std_logic_vector(3 downto 0):= x"0";
ex_dq: inout std_logic_vector(7 downto 0):= "ZZZZZZZZ";
--oscil
clk_25M: in std_logic;
clk_18M432: in std_logic;
clk_22M5792: in std_logic;
--pwrmng
pwrmng_rx: in std_logic;
pwrmng_tx: out std_logic:= '1';
pwrmng_res: in std_logic;
--misc
res: buffer std_logic:= '0'
);
end entity MARK_II;
architecture MARK_II_arch of MARK_II is
component cpu is
port(
--system interface
clk: in std_logic;
res: in std_logic;
--bus interface
address: out std_logic_vector(23 downto 0);
data_mosi: out std_logic_vector(31 downto 0);
data_miso: in std_logic_vector(31 downto 0);
we: out std_logic;
oe: out std_logic;
ack: in std_logic;
swirq: out std_logic;
--interrupts
int: in std_logic;
int_address: in std_logic_vector(23 downto 0);
int_accept: out std_logic;
int_completed: out std_logic
);
end component cpu;
component intController is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
int_req: in std_logic_vector(15 downto 0); --peripherals may request interrupt with this signal
int_accept: in std_logic; --from the CPU
int_completed: in std_logic; --from the CPU
int_cpu_address: out std_logic_vector(23 downto 0); --connect this to the CPU, this is address of ISR
int_cpu_rq: out std_logic
);
end component intController;
component rom is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address of the ROM
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic
);
end component rom;
component ram is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"; --base address of the RAM
ADDRESS_WIDE: natural := 8 --default address range
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic
);
end component ram;
component systim is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
intrq: out std_logic
);
end component systim;
component uart is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address of the GPIO
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
clk_uart: in std_logic;
rx: in std_logic;
tx: out std_logic;
intrq: out std_logic
);
end component uart;
component vga is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address of the RAM
);
port(
clk_bus: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
clk_vga: in std_logic;
h_sync: out std_logic;
v_sync: out std_logic;
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(1 downto 0)
);
end component vga;
component ps2 is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_miso: out std_logic_vector(31 downto 0);
RD: in std_logic;
ack: out std_logic;
--device
ps2clk: in std_logic;
ps2dat: in std_logic;
intrq: out std_logic
);
end component ps2;
component clkgen is
port(
res: in std_logic;
clk_ext: in std_logic;
res_out: out std_logic;
clk_sdram: out std_logic;
clk_sdram_shift: out std_logic
);
end component clkgen;
component sdram is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
--bus interface
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
-- device specific interface
clk_sdram: in std_logic;
-- sdram interface
sdram_a: out std_logic_vector(12 downto 0);
sdram_ba: out std_logic_vector(1 downto 0);
sdram_dq: inout std_logic_vector(7 downto 0);
sdram_ras: out std_logic;
sdram_cas: out std_logic;
sdram_we: out std_logic
);
end component sdram;
component timer is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
intrq: out std_logic
);
end component timer;
component lfsr is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic
);
end component lfsr;
--signal for internal bus
signal bus_address: std_logic_vector(23 downto 0);
signal bus_data_mosi, bus_data_miso: std_logic_vector(31 downto 0);
signal bus_ack, bus_WR, bus_RD: std_logic;
signal int_req: std_logic_vector(15 downto 0) := x"0000";
--signal for interconnect CPU and int controller
signal intCompleted, intAccepted: std_logic;
signal intCPUReq: std_logic;
signal intAddress: std_logic_vector(23 downto 0);
signal rom_ack, ram0_ack, ram1_ack, int_ack, systim_ack, vga_ack, uart0_ack, uart1_ack, uart2_ack, ps2_0_ack, ps2_1_ack, dram0_ack, tim0_ack, tim1_ack, tim2_ack, tim3_ack, lfsr_ack: std_logic;
signal clk_uart, clk_vga, clk_sys, clk_audio, clk_sdram: std_logic;
begin
--clk def
clk_uart <= clk_18M432;
clk_vga <= clk_25M;
clk_sys <= clk_25M;
clk_audio <= clk_22M5792;
clkgen0: clkgen
port map(pwrmng_res, clk_25M, res, clk_sdram, sdram_clk);
--CPU parts
cpu0: cpu
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
bus_ack, int_req(0), intCPUReq, intAddress, intAccepted, intCompleted
);
int0: intController
generic map(x"00010F")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
int_ack, int_req, intAccepted, intCompleted, intAddress, intCPUReq
);
systim0: systim
generic map(x"000104")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
systim_ack, int_req(1)
);
--peripherals
rom0: rom
generic map(x"000000")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
rom_ack
);
ram0: ram
generic map(x"000400", 10)
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
ram0_ack
);
uart0: uart
generic map(x"000130")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
uart0_ack, clk_uart, uart0_rxd, uart0_txd, int_req(8)
);
uart1: uart
generic map(x"000134")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
uart1_ack, clk_uart, uart1_rxd, uart1_txd, int_req(9)
);
uart2: uart
generic map(x"000138")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
uart2_ack, clk_uart, pwrmng_rx, pwrmng_tx, int_req(10)
);
vga0: vga
generic map(x"001000")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
vga_ack, clk_vga, vga_hs, vga_vs, vga_r, vga_g, vga_b
);
ps2_0: ps2
generic map(x"000106")
port map(
clk_sys, res, bus_address, bus_data_miso, bus_RD,
ps2_0_ack, kb_clk, kb_dat, int_req(11)
);
ps2_1: ps2
generic map(x"000107")
port map(
clk_sys, res, bus_address, bus_data_miso, bus_RD,
ps2_1_ack, ms_clk, ms_dat, int_req(12)
);
ram1: ram
generic map(x"100000", 13)
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
ram1_ack
);
dram0: sdram
generic map(x"800000")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
dram0_ack, clk_sdram,
sdram_a, sdram_ba, sdram_dq, sdram_ras, sdram_cas, sdram_we
);
timer0: timer
generic map(x"000140")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
tim0_ack, int_req(4)
);
timer1: timer
generic map(x"000144")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
tim1_ack, int_req(5)
);
timer2: timer
generic map(x"000148")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
tim2_ack, int_req(6)
);
timer3: timer
generic map(x"00014C")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
tim3_ack, int_req(7)
);
lfsr0: lfsr
generic map(x"00010E")
port map(
clk_sys, res, bus_address, bus_data_mosi, bus_data_miso, bus_WR, bus_RD,
lfsr_ack
);
bus_ack <=
rom_ack or ram0_ack or ram1_ack or int_ack or systim_ack or vga_ack or
uart0_ack or uart1_ack or uart2_ack or ps2_0_ack or ps2_1_ack or dram0_ack or
tim0_ack or tim1_ack or tim2_ack or tim3_ack or lfsr_ack;
end architecture MARK_II_arch;
|
mit
|
96d59faf8264868108b876550833f51a
| 0.534971 | 3.318715 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/db/alt_dspbuilder_decoder.vhd
| 1 | 3,360 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNA3ETEQ66 is
generic (
DECODE : string := "00";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNA3ETEQ66;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(24-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
DECODE : string := "01";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
begin
alt_dspbuilder_decoder_GNA3ETEQ66_0: if ((DECODE = "00") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNA3ETEQ66_0: alt_dspbuilder_decoder_GNA3ETEQ66
generic map(DECODE => "00", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNSCEXJCJK_1: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_1: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNM4LOIHXZ_2: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNM4LOIHXZ_2: alt_dspbuilder_decoder_GNM4LOIHXZ
generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "00") and (PIPELINE = 1) and (WIDTH = 2)) or ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) or ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
f9df434f97a34c7b052d4cb25cc42d47
| 0.658631 | 3.149016 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/testbench/input_gen/input_gen_tb.vhd
| 1 | 3,895 |
-------------------------------------------------------------------------------
-- Title : Input generator testbench
-- Project :
-------------------------------------------------------------------------------
-- File : input_gen_tb.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-07-01
-- Last update: 2014-07-01
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Simple testbench to validate input generator
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-07-01 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
-------------------------------------------------------------------------------
entity input_gen_tb is
end entity input_gen_tb;
-------------------------------------------------------------------------------
architecture str of input_gen_tb is
constant c_input_freq : real := 120.0e6;
constant c_half_period : time := 1.0 sec / (2.0 * c_input_freq);
constant c_output_file : string := "./input_gen.samples";
constant c_ce_period : natural := 2; -- in number of clock cycles
constant c_input_width : natural := 16;
constant c_output_width : natural := 32;
constant c_ksum : natural := 10000;
-- Signals
signal clock : std_logic := '0';
signal endoffile : bit := '0';
signal ce : std_logic := '0';
-- data signals
signal x_in, y_in : std_logic_vector(c_input_width-1 downto 0);
signal a_out, b_out, c_out, d_out : std_logic_vector(c_output_width-1 downto 0);
component input_gen is
generic (
g_input_width : natural;
g_output_width : natural;
g_ksum : integer);
port (
x_i : in std_logic_vector(g_input_width-1 downto 0);
y_i : in std_logic_vector(g_input_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
a_o : out std_logic_vector(g_output_width-1 downto 0);
b_o : out std_logic_vector(g_output_width-1 downto 0);
c_o : out std_logic_vector(g_output_width-1 downto 0);
d_o : out std_logic_vector(g_output_width-1 downto 0));
end component input_gen;
begin -- architecture str
clk_gen : process
begin
clock <= '0';
wait for c_half_period;
clock <= '1';
wait for c_half_period;
end process clk_gen;
ce_gen : process(clock)
variable ce_count : natural := 0;
begin
if rising_edge(clock) then
ce_count := ce_count + 1;
if ce_count = c_ce_period then
ce <= '1';
ce_count := 0;
else
ce <= '0';
end if;
end if;
end process;
uut : input_gen
generic map (
g_input_width => c_input_width,
g_output_width => c_output_width,
g_ksum => c_ksum)
port map (
x_i => x_in,
y_i => y_in,
clk_i => clock,
ce_i => ce,
a_o => a_out,
b_o => b_out,
c_o => c_out,
d_o => d_out);
data_gen : process
begin
for x_int in -99 to 99 loop
x_in <= std_logic_vector(to_signed(x_int, c_input_width));
for y_int in -99 to 99 loop
wait until ce = '1';
y_in <= std_logic_vector(to_signed(y_int, c_input_width));
end loop;
end loop;
assert(false) report "end of input stream" severity failure;
end process data_gen;
end architecture str;
-------------------------------------------------------------------------------
|
lgpl-3.0
|
2a16814319c78eb9056c5ef5108970a5
| 0.465982 | 3.727273 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/usb_system/altera_merlin_burst_uncompressor/_primary.vhd
| 2 | 1,672 |
library verilog;
use verilog.vl_types.all;
entity altera_merlin_burst_uncompressor is
generic(
ADDR_W : integer := 16;
BURSTWRAP_W : integer := 3;
BYTE_CNT_W : integer := 4;
PKT_SYMBOLS : integer := 4;
BURST_SIZE_W : integer := 3
);
port(
clk : in vl_logic;
reset : in vl_logic;
sink_startofpacket: in vl_logic;
sink_endofpacket: in vl_logic;
sink_valid : in vl_logic;
sink_ready : out vl_logic;
sink_addr : in vl_logic_vector;
sink_burstwrap : in vl_logic_vector;
sink_byte_cnt : in vl_logic_vector;
sink_is_compressed: in vl_logic;
sink_burstsize : in vl_logic_vector;
source_startofpacket: out vl_logic;
source_endofpacket: out vl_logic;
source_valid : out vl_logic;
source_ready : in vl_logic;
source_addr : out vl_logic_vector;
source_burstwrap: out vl_logic_vector;
source_byte_cnt : out vl_logic_vector;
source_is_compressed: out vl_logic;
source_burstsize: out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ADDR_W : constant is 1;
attribute mti_svvh_generic_type of BURSTWRAP_W : constant is 1;
attribute mti_svvh_generic_type of BYTE_CNT_W : constant is 1;
attribute mti_svvh_generic_type of PKT_SYMBOLS : constant is 1;
attribute mti_svvh_generic_type of BURST_SIZE_W : constant is 1;
end altera_merlin_burst_uncompressor;
|
apache-2.0
|
5bc27cc7619b649248d87fe4ad1fb4d2
| 0.574163 | 3.611231 | false | false | false | false |
TUCircle/homework
|
VHDL/Aufgabe4.4.vhdl
| 2 | 573 |
--Aufgabe 4.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.Numeric_STD.all;
entity Aufgabe4_4 is
port(x: in STD_LOGIC_VECTOR(4 downto 1);
y: out STD_LOGIC);
end entity;
architecture test of Aufgabe4_4 is
begin
process(x)
variable z: STD_LOGIC_VECTOR(2 DOWNTO 0);
begin
--Bereich links oben
z(0) := x(1) and x(2);
z(1) := x(1) or x(2);
if x(3) = '0' then
z(2) := z(0);
else
z(2) := z(1);
end if;
--Abtastregister
if RISING_EDGE(x(4)) then
y <= z(2);
end if;
end process;
end architecture;
|
gpl-3.0
|
8424c8388df7dbfbc1bf3956e808bda6
| 0.577661 | 2.62844 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/machine/sirius_sr_130M/dds_cos_lut.vhd
| 1 | 2,363 |
-------------------------------------------------------------------------------
-- Title : Vivado DDS cos lut for SIRIUS 130M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_cos_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-04-15
-- Last update: 2015-04-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Temporary cosine lut for SIRIUS machine with 130M ADC generated
-- through Vivado.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-15 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
entity dds_cos_lut is
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end entity dds_cos_lut;
architecture str of dds_cos_lut is
component generic_rom
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
begin
cmp_cos_lut_sirius_52_203_1 : generic_rom
generic map (
g_data_width => 16,
g_size => 203,
g_init_file => "cos_lut_sirius_52_203.mif",
g_fail_if_file_not_found => true
)
port map (
rst_n_i => '1',
clk_i => clka,
a_i => addra,
q_o => douta
);
end architecture str;
|
lgpl-3.0
|
ed59e8cbac34a17e4984ac3b153ee968
| 0.404994 | 4.319927 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_orbit_intlk/orbit_intlk_cdc.vhd
| 1 | 15,655 |
------------------------------------------------------------------------------
-- Title : BPM orbit interlock CDC FIFOs
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2022-06-12
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Module for orbit interlock CDC FIFOs
-------------------------------------------------------------------------------
-- Copyright (c) 2020 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2020-06-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- General cores
use work.gencores_pkg.all;
-- Orbit interlock cores
use work.orbit_intlk_pkg.all;
entity orbit_intlk_cdc is
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Synched Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_o : out std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_o : out std_logic := '0';
decim_ds_pos_x_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_o : out std_logic;
-----------------------------
-- Synched Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_o : out std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_o : out std_logic := '0';
decim_us_pos_x_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_o : out std_logic
);
end orbit_intlk_cdc;
architecture rtl of orbit_intlk_cdc is
-- constants
constant c_ADC_WIDTH : natural := g_ADC_WIDTH;
constant c_DECIM_WIDTH : natural := g_DECIM_WIDTH;
constant c_INTLK_LMT_WIDTH : natural := g_INTLK_LMT_WIDTH;
constant c_CDC_REF_SIZE : natural := 4;
-- types
type t_bit_array is array (natural range <>) of std_logic;
type t_bit_array2d is array (natural range <>, natural range <>) of std_logic;
subtype t_adc_data is std_logic_vector(c_adc_width-1 downto 0);
type t_adc_data_array is array (natural range <>) of t_adc_data;
subtype t_adc_tag is std_logic_vector(0 downto 0);
type t_adc_tag_array is array (natural range <>) of t_adc_tag;
subtype t_decim_data is std_logic_vector(c_decim_width-1 downto 0);
type t_decim_data_array is array (natural range <>) of t_decim_data;
subtype t_intlk_lmt_data is std_logic_vector(c_intlk_lmt_width-1 downto 0);
type t_intlk_lmt_data_array is array (natural range <>) of t_intlk_lmt_data;
type t_adc_data_array2d is array (natural range <>, natural range <>) of t_adc_data;
type t_decim_data_array2d is array (natural range <>, natural range <>) of t_decim_data;
--signals
-- input mangling
signal adc_array : t_adc_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal adc_tag_array : t_adc_tag_array(c_NUM_BPMS-1 downto 0);
signal adc_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0);
signal decim_pos_array : t_decim_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal decim_pos_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0);
signal adc_synch_array : t_adc_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal adc_synch_valid_array : t_bit_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal adc_synch_tag_array : t_adc_tag_array(c_NUM_BPMS-1 downto 0);
signal adc_synch_tag_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0);
signal decim_pos_synch_array : t_decim_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal decim_pos_synch_valid_array : t_bit_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal adc_synch_rd : std_logic;
signal decim_pos_synch_rd : std_logic;
signal adc_synch_rd_and : std_logic_vector(c_NUM_BPMS downto 0);
signal decim_pos_synch_rd_and : std_logic_vector(c_NUM_BPMS downto 0);
signal fs_clk_array : std_logic_vector(c_NUM_BPMS-1 downto 0);
signal adc_synch_tag_empty : t_bit_array(c_NUM_BPMS-1 downto 0);
signal adc_synch_empty : t_bit_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal decim_pos_synch_empty : t_bit_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
begin
---------------------------------
-- Signal mangling
--------------------------------
fs_clk_array(c_BPM_DS_IDX) <= fs_clk_ds_i;
-- Downstream
adc_array(c_BPM_DS_IDX, 0) <= adc_ds_ch0_swap_i;
adc_array(c_BPM_DS_IDX, 1) <= adc_ds_ch1_swap_i;
adc_array(c_BPM_DS_IDX, 2) <= adc_ds_ch2_swap_i;
adc_array(c_BPM_DS_IDX, 3) <= adc_ds_ch3_swap_i;
adc_tag_array(c_BPM_DS_IDX) <= adc_ds_tag_i;
adc_valid_array(c_BPM_DS_IDX) <= adc_ds_swap_valid_i;
decim_pos_array(c_BPM_DS_IDX, 0) <= decim_ds_pos_x_i;
decim_pos_array(c_BPM_DS_IDX, 1) <= decim_ds_pos_y_i;
decim_pos_array(c_BPM_DS_IDX, 2) <= decim_ds_pos_q_i;
decim_pos_array(c_BPM_DS_IDX, 3) <= decim_ds_pos_sum_i;
decim_pos_valid_array(c_BPM_DS_IDX) <= decim_ds_pos_valid_i;
-- Upwnstream
fs_clk_array(c_BPM_US_IDX) <= fs_clk_us_i;
adc_array(c_BPM_US_IDX, 0) <= adc_us_ch0_swap_i;
adc_array(c_BPM_US_IDX, 1) <= adc_us_ch1_swap_i;
adc_array(c_BPM_US_IDX, 2) <= adc_us_ch2_swap_i;
adc_array(c_BPM_US_IDX, 3) <= adc_us_ch3_swap_i;
adc_tag_array(c_BPM_US_IDX) <= adc_us_tag_i;
adc_valid_array(c_BPM_US_IDX) <= adc_us_swap_valid_i;
decim_pos_array(c_BPM_US_IDX, 0) <= decim_us_pos_x_i;
decim_pos_array(c_BPM_US_IDX, 1) <= decim_us_pos_y_i;
decim_pos_array(c_BPM_US_IDX, 2) <= decim_us_pos_q_i;
decim_pos_array(c_BPM_US_IDX, 3) <= decim_us_pos_sum_i;
decim_pos_valid_array(c_BPM_US_IDX) <= decim_us_pos_valid_i;
---------------------------------
-- Decim CDC FIFOs
--------------------------------
gen_cdc_fifos_bpms : for i in 0 to c_NUM_BPMS-1 generate
cmp_orbit_intlk_adc_tag_cdc_fifo : orbit_intlk_cdc_fifo
generic map
(
g_data_width => 1,
g_size => c_CDC_REF_SIZE
)
port map
(
clk_wr_i => fs_clk_array(i),
data_i => adc_tag_array(i),
valid_i => adc_valid_array(i),
clk_rd_i => ref_clk_i,
rd_i => adc_synch_rd,
data_o => adc_synch_tag_array(i),
valid_o => adc_synch_tag_valid_array(i),
empty_o => adc_synch_tag_empty(i)
);
gen_cdc_fifos_chan : for j in 0 to c_NUM_CHANNELS-1 generate
cmp_orbit_intlk_adc_cdc_fifo : orbit_intlk_cdc_fifo
generic map
(
g_data_width => c_ADC_WIDTH,
g_size => c_CDC_REF_SIZE
)
port map
(
clk_wr_i => fs_clk_array(i),
data_i => adc_array(i, j),
valid_i => adc_valid_array(i),
clk_rd_i => ref_clk_i,
rd_i => adc_synch_rd,
data_o => adc_synch_array(i, j),
valid_o => adc_synch_valid_array(i, j),
empty_o => adc_synch_empty(i, j)
);
cmp_orbit_intlk_decim_cdc_fifo : orbit_intlk_cdc_fifo
generic map
(
g_data_width => c_DECIM_WIDTH,
g_size => c_CDC_REF_SIZE
)
port map
(
clk_wr_i => fs_clk_array(i),
data_i => decim_pos_array(i, j),
valid_i => decim_pos_valid_array(i),
clk_rd_i => ref_clk_i,
rd_i => decim_pos_synch_rd,
data_o => decim_pos_synch_array(i, j),
valid_o => decim_pos_synch_valid_array(i, j),
empty_o => decim_pos_synch_empty(i, j)
);
end generate;
end generate;
-- generate read signals based on empty FIFO flags
adc_synch_rd_and(0) <= '1';
-- ANDing all trans_bigger
gen_adc_synch_rd_and : for i in 0 to c_NUM_BPMS-1 generate
adc_synch_rd_and(i+1) <= adc_synch_rd_and(i) and not adc_synch_empty(i, 0);
end generate;
adc_synch_rd <= adc_synch_rd_and(c_NUM_BPMS);
decim_pos_synch_rd_and(0) <= '1';
-- ANDing all trans_bigger
gen_decim_pos_synch_rd_and : for i in 0 to c_NUM_BPMS-1 generate
decim_pos_synch_rd_and(i+1) <= decim_pos_synch_rd_and(i) and not decim_pos_synch_empty(i, 0);
end generate;
decim_pos_synch_rd <= decim_pos_synch_rd_and(c_NUM_BPMS);
---------------------------------
-- Signal unmangling
--------------------------------
-- Downstream
adc_ds_ch0_swap_o <= adc_synch_array(c_BPM_DS_IDX, 0);
adc_ds_ch1_swap_o <= adc_synch_array(c_BPM_DS_IDX, 1);
adc_ds_ch2_swap_o <= adc_synch_array(c_BPM_DS_IDX, 2);
adc_ds_ch3_swap_o <= adc_synch_array(c_BPM_DS_IDX, 3);
adc_ds_tag_o <= adc_synch_tag_array(c_BPM_DS_IDX);
adc_ds_swap_valid_o <= adc_synch_valid_array(c_BPM_DS_IDX, 0);
decim_ds_pos_x_o <= decim_pos_synch_array(c_BPM_DS_IDX, 0);
decim_ds_pos_y_o <= decim_pos_synch_array(c_BPM_DS_IDX, 1);
decim_ds_pos_q_o <= decim_pos_synch_array(c_BPM_DS_IDX, 2);
decim_ds_pos_sum_o <= decim_pos_synch_array(c_BPM_DS_IDX, 3);
decim_ds_pos_valid_o <= decim_pos_synch_valid_array(c_BPM_DS_IDX, 0);
-- Upstream
adc_us_ch0_swap_o <= adc_synch_array(c_BPM_US_IDX, 0);
adc_us_ch1_swap_o <= adc_synch_array(c_BPM_US_IDX, 1);
adc_us_ch2_swap_o <= adc_synch_array(c_BPM_US_IDX, 2);
adc_us_ch3_swap_o <= adc_synch_array(c_BPM_US_IDX, 3);
adc_us_tag_o <= adc_synch_tag_array(c_BPM_US_IDX);
adc_us_swap_valid_o <= adc_synch_valid_array(c_BPM_US_IDX, 0);
decim_us_pos_x_o <= decim_pos_synch_array(c_BPM_US_IDX, 0);
decim_us_pos_y_o <= decim_pos_synch_array(c_BPM_US_IDX, 1);
decim_us_pos_q_o <= decim_pos_synch_array(c_BPM_US_IDX, 2);
decim_us_pos_sum_o <= decim_pos_synch_array(c_BPM_US_IDX, 3);
decim_us_pos_valid_o <= decim_pos_synch_valid_array(c_BPM_US_IDX, 0);
end rtl;
|
lgpl-3.0
|
609bcbe17ee14bc6691e23985cdf60c8
| 0.48962 | 3.231833 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/downconv/downconv.vhd
| 1 | 4,923 |
-------------------------------------------------------------------------------
-- Title : Fofb Downconversion module
-- Project :
-------------------------------------------------------------------------------
-- File : fofb_downconv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-06
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Downconverts a button signal to FOFB rate
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-06 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.dsp_cores_pkg.all;
use work.bpm_cores_pkg.all;
entity downconv is
generic (
-- Widths for different busses
g_input_width : natural := 16;
g_mixed_width : natural := 24;
g_output_width : natural := 32;
g_phase_width : natural := 8;
-- Parameters for sin/cos dds
g_sin_file : string := "./dds_sin.nif";
g_cos_file : string := "./dds_cos.nif";
g_number_of_points : natural := 6;
-- CIC parameters
g_diff_delay : natural := 2;
g_stages : natural := 3;
g_decimation_rate : natural := 1000
);
port (
signal_i : in std_logic_vector(g_input_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
phase_i : in std_logic_vector(g_phase_width-1 downto 0);
I_o : out std_logic_vector(g_output_width-1 downto 0);
Q_o : out std_logic_vector(g_output_width-1 downto 0);
valid_o : out std_logic
);
end entity downconv;
-------------------------------------------------------------------------------
architecture str of downconv is
-- Constant values
constant c_cic_bus_width : natural := natural(ceil(log2(real(g_decimation_rate))));
-- Internal signal declarations
signal I_sig : std_logic_vector(g_mixed_width-1 downto 0);
signal Q_sig : std_logic_vector(g_mixed_width-1 downto 0);
begin -- architecture str
cmp_mixer : mixer
generic map (
g_sin_file => g_sin_file,
g_cos_file => g_cos_file,
g_number_of_points => g_number_of_points,
g_dds_width => g_phase_width, -- changed to update component
g_input_width => g_input_width,
g_output_width => g_mixed_width)
port map (
rst_i => rst_i ,
clk_i => clk_i,
ce_i => ce_i,
signal_i => signal_i,
valid_i => '1', -- chosen as default value, since this port was not used
I_out => I_sig,
Q_out => Q_sig);
cmp_cic: cic_dual
generic map (
g_input_width => g_mixed_width,
g_output_width => g_output_width,
g_stages => g_stages,
g_delay => g_diff_delay,
g_max_rate => g_decimation_rate,
g_bus_width => c_cic_bus_width)
port map (
clk_i => clk_i,
rst_i => rst_i ,
ce_i => ce_i,
valid_i => '1', -- chosen as default value, since this port was not used
-- originally
I_i => I_sig,
Q_i => Q_sig,
ratio_i => std_logic_vector(to_unsigned(g_decimation_rate, c_cic_bus_width)),
I_o => I_o,
Q_o => Q_o,
valid_o => valid_o);
--cmp_cic_I : cic_dyn
-- generic map (
-- g_input_width => g_mixed_width,
-- g_output_width => g_output_width,
-- g_stages => g_stages,
-- g_delay => g_diff_delay,
-- g_max_rate => g_decimation_rate,
-- g_bus_width => c_cic_bus_width)
-- port map (
-- clk_i => clk_i,
-- rst_i => rst_i ,
-- ce_i => ce_i,
-- data_i => I_sig,
-- ratio_i => std_logic_vector(to_unsigned(g_decimation_rate, c_cic_bus_width)),
-- data_o => I_o,
-- valid_o => valid_o);
--cmp_cic_Q : cic_dyn
-- generic map (
-- g_input_width => g_mixed_width,
-- g_output_width => g_output_width,
-- g_stages => g_stages,
-- g_delay => g_diff_delay,
-- g_max_rate => g_decimation_rate,
-- g_bus_width => c_cic_bus_width)
-- port map (
-- clk_i => clk_i,
-- rst_i => rst_i ,
-- ce_i => ce_i,
-- data_i => Q_sig,
-- ratio_i => std_logic_vector(to_unsigned(g_decimation_rate, c_cic_bus_width)),
-- data_o => Q_o,
-- valid_o => valid_o);
end architecture str;
-------------------------------------------------------------------------------
|
lgpl-3.0
|
f66c1a9fc4b1cc695dc279a4c167de40
| 0.464757 | 3.355828 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_div/fp_div.vhd
| 1 | 5,845 |
-- megafunction wizard: %ALTERA_FP_FUNCTIONS v17.0%
-- GENERATION: XML
-- fp_div.vhd
-- Generated using ACDS version 17.0 595
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fp_div is
port (
clk : in std_logic := '0'; -- clk.clk
areset : in std_logic := '0'; -- areset.reset
a : in std_logic_vector(31 downto 0) := (others => '0'); -- a.a
b : in std_logic_vector(31 downto 0) := (others => '0'); -- b.b
q : out std_logic_vector(31 downto 0) -- q.q
);
end entity fp_div;
architecture rtl of fp_div is
component fp_div_0002 is
port (
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(31 downto 0) -- q
);
end component fp_div_0002;
begin
fp_div_inst : component fp_div_0002
port map (
clk => clk, -- clk.clk
areset => areset, -- areset.reset
a => a, -- a.a
b => b, -- b.b
q => q -- q.q
);
end architecture rtl; -- of fp_div
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_fp_functions" version="17.0" >
-- Retrieval info: <generic name="FUNCTION_FAMILY" value="ARITH" />
-- Retrieval info: <generic name="ARITH_function" value="DIV" />
-- Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
-- Retrieval info: <generic name="ALL_function" value="ADD" />
-- Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
-- Retrieval info: <generic name="TRIG_function" value="SIN" />
-- Retrieval info: <generic name="COMPARE_function" value="MIN" />
-- Retrieval info: <generic name="ROOTS_function" value="SQRT" />
-- Retrieval info: <generic name="fp_format" value="single" />
-- Retrieval info: <generic name="fp_exp" value="8" />
-- Retrieval info: <generic name="fp_man" value="23" />
-- Retrieval info: <generic name="exponent_width" value="23" />
-- Retrieval info: <generic name="frequency_target" value="25" />
-- Retrieval info: <generic name="latency_target" value="2" />
-- Retrieval info: <generic name="performance_goal" value="frequency" />
-- Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
-- Retrieval info: <generic name="faithful_rounding" value="true" />
-- Retrieval info: <generic name="gen_enable" value="false" />
-- Retrieval info: <generic name="divide_type" value="0" />
-- Retrieval info: <generic name="select_signal_enable" value="false" />
-- Retrieval info: <generic name="scale_by_pi" value="false" />
-- Retrieval info: <generic name="number_of_inputs" value="2" />
-- Retrieval info: <generic name="trig_no_range_reduction" value="false" />
-- Retrieval info: <generic name="report_resources_to_xml" value="false" />
-- Retrieval info: <generic name="fxpt_width" value="32" />
-- Retrieval info: <generic name="fxpt_fraction" value="0" />
-- Retrieval info: <generic name="fxpt_sign" value="1" />
-- Retrieval info: <generic name="fp_out_format" value="single" />
-- Retrieval info: <generic name="fp_out_exp" value="8" />
-- Retrieval info: <generic name="fp_out_man" value="23" />
-- Retrieval info: <generic name="fp_in_format" value="single" />
-- Retrieval info: <generic name="fp_in_exp" value="8" />
-- Retrieval info: <generic name="fp_in_man" value="23" />
-- Retrieval info: <generic name="enable_hard_fp" value="true" />
-- Retrieval info: <generic name="manual_dsp_planning" value="true" />
-- Retrieval info: <generic name="forceRegisters" value="1111" />
-- Retrieval info: <generic name="selected_device_family" value="MAX 10" />
-- Retrieval info: <generic name="selected_device_speedgrade" value="6" />
-- Retrieval info: </instance>
-- IPFS_FILES : fp_div.vho
-- RELATED_FILES: fp_div.vhd, dspba_library_package.vhd, dspba_library.vhd, fp_div_0002.vhd
|
mit
|
becca2e79a1fdba8cd2f2156a01a0cc8
| 0.642429 | 3.491637 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/rtlLvl/SimpleRegister.vhd
| 1 | 729 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleRegister IS
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
s_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF SimpleRegister IS
SIGNAL val : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"00";
SIGNAL val_next : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
s_out <= val;
assig_process_val: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
val <= X"00";
ELSE
val <= val_next;
END IF;
END IF;
END PROCESS;
val_next <= s_in;
END ARCHITECTURE;
|
mit
|
3d42fbae792a0634b36dba98f3909190
| 0.559671 | 3.454976 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/vga/vga.vhd
| 1 | 11,142 |
-- VGA driver
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
--
-- Pixel clock: 25MHz
-- Resolution: 640x480 @ 60Hz
-- Text resolution: 80x30 chars
-- Char resolution: 16x8 px
--
-- All characters are using ASCII encoding, see full docs for more
-- details about charset.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
clk_bus: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
clk_vga: in std_logic;
h_sync: out std_logic;
v_sync: out std_logic;
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(1 downto 0)
);
end entity vga;
architecture vga_arch of vga is
component font_rom is
port(
clk: in std_logic;
addr: in unsigned(10 downto 0);
data: out unsigned(7 downto 0)
);
end component font_rom;
component vram is
port(
clk_a : in std_logic;
addr_a : in unsigned(11 downto 0);
data_a : in unsigned(15 downto 0);
we_a : in std_logic;
q_a : out unsigned(15 downto 0);
clk_b : in std_logic;
addr_b : in unsigned(11 downto 0);
q_b : out unsigned(15 downto 0)
);
end component vram;
--to vram
signal tile_line: unsigned(4 downto 0);
signal tile_col: unsigned(6 downto 0);
--to pixel generator
signal cell_line: unsigned(3 downto 0);
signal cell_line_s: unsigned(3 downto 0);
signal cell_line_ss: unsigned(3 downto 0);
signal cell_col: unsigned(2 downto 0);
signal cell_col_s: unsigned(2 downto 0);
signal char_from_vram: unsigned(15 downto 0);
signal line_from_charrom: unsigned(7 downto 0);
signal pixel: std_logic;
signal blank_r, blank, h_sync_r, v_sync_r: std_logic;
signal bg_color, fg_color: unsigned(3 downto 0);
signal cursor_en, cursor_timer: std_logic;
--BUS interface
signal addr_a : unsigned(11 downto 0);
signal data_a : unsigned(15 downto 0);
signal we_a : std_logic;
signal q_a : unsigned(15 downto 0);
signal cs: std_logic;
type ack_fsm is (idle, set);
signal ack_fsm_state: ack_fsm;
begin
process(clk_vga) is
variable h_pos: integer range 0 to 800;
variable v_pos: integer range 0 to 525;
variable posx_v: unsigned(9 downto 0);
variable posy_v: unsigned(8 downto 0);
begin
if rising_edge(clk_vga) then
if h_pos < 800 then
h_pos := h_pos + 1;
else
h_pos := 0;
if v_pos < 525 then
v_pos := v_pos + 1;
else
v_pos := 0;
end if;
end if;
if h_pos < 96 then
h_sync_r <= '0';
else
h_sync_r <= '1';
end if;
if v_pos < 2 then
v_sync_r <= '0';
else
v_sync_r <= '1';
end if;
if (h_pos > 144 and h_pos <= 784) and (v_pos > 35 and v_pos < 515) then
blank_r <= '0';
else
blank_r <= '1';
end if;
if h_pos > 144 and h_pos < 784 then
posx_v := posx_v + 1;
else
posx_v := (others => '0');
end if;
if v_pos > 35 and v_pos < 515 then
if h_pos = 784 then
posy_v := posy_v + 1;
end if;
else
posy_v := (others => '0');
end if;
end if;
tile_col <= posx_v(9 downto 3);
cell_col <= posx_v(2 downto 0);
tile_line <= posy_v(8 downto 4);
cell_line <= posy_v(3 downto 0);
end process;
process(clk_vga, cell_line) is
variable cell_line_var: unsigned(3 downto 0);
variable cell_line_var_2: unsigned(3 downto 0);
begin
if rising_edge(clk_vga) then
cell_line_var_2 := cell_line_var;
cell_line_var := cell_line;
end if;
cell_line_s <= cell_line_var;
cell_line_ss <= cell_line_var_2;
end process;
process(clk_vga, cell_col) is
variable cell_col_s1_var: unsigned(2 downto 0);
variable cell_col_s2_var: unsigned(2 downto 0);
begin
if rising_edge(clk_vga) then
cell_col_s2_var := cell_col_s1_var;
cell_col_s1_var := cell_col;
end if;
cell_col_s <= cell_col_s2_var;
end process;
process(clk_vga, h_sync_r, v_sync_r) is
variable h_sync_s1: std_logic;
variable h_sync_s2: std_logic;
variable v_sync_s1: std_logic;
variable v_sync_s2: std_logic;
variable blank_s1: std_logic;
variable blank_s2: std_logic;
begin
if rising_edge(clk_vga) then
h_sync_s2 := h_sync_s1;
h_sync_s1 := h_sync_r;
v_sync_s2 := v_sync_s1;
v_sync_s1 := v_sync_r;
blank_s2 := blank_s1;
blank_s1 := blank_r;
end if;
v_sync <= v_sync_s2;
h_sync <= h_sync_s2;
blank <= blank_s2;
end process;
vram0: vram port map(clk_bus, addr_a, data_a, we_a, q_a, clk_vga, tile_line & tile_col, char_from_vram);
font_rom0: font_rom port map(clk_vga, char_from_vram(6 downto 0) & cell_line_s, line_from_charrom);
process(clk_vga) is
variable cursor_timer_var: unsigned(24 downto 0);
begin
if rising_edge(clk_vga) then
if res = '1' then
cursor_timer_var := (others => '0');
else
cursor_timer_var := cursor_timer_var + 1;
end if;
end if;
cursor_timer <= cursor_timer_var(24);
end process;
process(cell_col_s, cell_line_ss, line_from_charrom, cursor_en, cursor_timer) is
begin
if cell_line_ss = "1111" then
case cursor_en is
when '1' =>
pixel <= cursor_timer;
when others =>
case cell_col_s is
when "000" => pixel <= line_from_charrom(7);
when "001" => pixel <= line_from_charrom(6);
when "010" => pixel <= line_from_charrom(5);
when "011" => pixel <= line_from_charrom(4);
when "100" => pixel <= line_from_charrom(3);
when "101" => pixel <= line_from_charrom(2);
when "110" => pixel <= line_from_charrom(1);
when "111" => pixel <= line_from_charrom(0);
end case;
end case;
else
case cell_col_s is
when "000" => pixel <= line_from_charrom(7);
when "001" => pixel <= line_from_charrom(6);
when "010" => pixel <= line_from_charrom(5);
when "011" => pixel <= line_from_charrom(4);
when "100" => pixel <= line_from_charrom(3);
when "101" => pixel <= line_from_charrom(2);
when "110" => pixel <= line_from_charrom(1);
when "111" => pixel <= line_from_charrom(0);
end case;
end if;
end process;
process(clk_vga, char_from_vram) is
variable fg_color_v, bg_color_v: unsigned(3 downto 0);
variable cursor_v: std_logic;
begin
if rising_edge(clk_vga) then
fg_color_v := char_from_vram(10 downto 7);
bg_color_v := char_from_vram(14 downto 11);
cursor_v := char_from_vram(15);
end if;
fg_color <= fg_color_v;
bg_color <= bg_color_v;
cursor_en <= cursor_v;
end process;
process(pixel, fg_color, bg_color, blank) is
begin
case pixel is
when '1' =>
red(0) <= fg_color(0) and not(blank);
green(0) <= fg_color(0) and not(blank);
blue(0) <= fg_color(0) and not(blank);
red(1) <= fg_color(0) and not(blank);
green(1) <= fg_color(0) and not(blank);
red(2) <= fg_color(1) and not(blank);
green(2) <= fg_color(2) and not(blank);
blue(1) <= fg_color(3) and not(blank);
when '0' =>
red(0) <= bg_color(0) and not(blank);
green(0) <= bg_color(0) and not(blank);
blue(0) <= bg_color(0) and not(blank);
red(1) <= bg_color(0) and not(blank);
green(1) <= bg_color(0) and not(blank);
red(2) <= bg_color(1) and not(blank);
green(2) <= bg_color(2) and not(blank);
blue(1) <= bg_color(3) and not(blank);
end case;
end process;
--BUS interface
process(address) is begin
if (unsigned(address) >= BASE_ADDRESS and unsigned(address) <= (BASE_ADDRESS + 4095)) then
cs <= '1';
else
cs <= '0';
end if;
end process;
process(clk_bus) is
begin
if rising_edge(clk_bus) then
if res = '1' then
ack_fsm_state <= idle;
else
case ack_fsm_state is
when idle =>
if ((WR = '1' and cs = '1') or (RD = '1' and cs = '1')) then
ack_fsm_state <= set;
else
ack_fsm_state <= idle;
end if;
when set =>
ack_fsm_state <= idle;
end case;
end if;
end if;
end process;
process(ack_fsm_state) is
begin
case ack_fsm_state is
when idle =>
ack <= '0';
when set =>
ack <= '1';
end case;
end process;
data_miso <= std_logic_vector(x"0000" & q_a) when ((RD = '1') and (cs = '1')) else (others => 'Z');
data_a <= unsigned(data_mosi(15 downto 0));
we_a <= WR and cs;
addr_a <= unsigned(address(11 downto 0));
end architecture;
|
mit
|
175ebf61d3c947edeb97c479cb67ea9f
| 0.467193 | 3.717384 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/afc_v3/test_adc_clk/dbe_bpm_dsp.vhd
| 1 | 4,016 |
------------------------------------------------------------------------------
-- Title : Top DSP design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-01
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC130M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-09-01 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_dsp is
port(
-----------------------------
-- FMC1_130m_4ch ports
-----------------------------
-- ADC0 LTC2208
fmc1_adc0_clk_i : in std_logic;
-- FMC LEDs
fmc1_led1_o : out std_logic;
fmc1_led2_o : out std_logic;
fmc1_led3_o : out std_logic;
-----------------------------
-- FMC2_130m_4ch ports
-----------------------------
-- ADC0 LTC2208
fmc2_adc0_clk_i : in std_logic;
-- FMC LEDs
fmc2_led1_o : out std_logic;
fmc2_led2_o : out std_logic;
fmc2_led3_o : out std_logic
);
end dbe_bpm_dsp;
architecture rtl of dbe_bpm_dsp is
constant c_max_count : natural := 113000000;
signal fmc1_adc0_clk_buf : std_logic;
signal fmc2_adc0_clk_buf : std_logic;
signal fmc1_adc0_clk_bufg : std_logic;
signal fmc2_adc0_clk_bufg : std_logic;
begin
cmp_ibuf_adc1_clk0 : ibuf
generic map(
IOSTANDARD => "LVCMOS25"
)
port map(
i => fmc1_adc0_clk_i,
o => fmc1_adc0_clk_buf
);
cmp_bufg_adc1_clk0 : BUFG
port map(
O => fmc1_adc0_clk_bufg,
I => fmc1_adc0_clk_buf
);
cmp_ibuf_adc2_clk0 : ibuf
generic map(
IOSTANDARD => "LVCMOS25"
)
port map(
i => fmc2_adc0_clk_i,
o => fmc2_adc0_clk_buf
);
cmp_bufg_adc2_clk0 : BUFG
port map(
O => fmc2_adc0_clk_bufg,
I => fmc2_adc0_clk_buf
);
p_counter1 : process(fmc1_adc0_clk_bufg)
variable count : natural range 0 to c_max_count;
begin
if rising_edge(fmc1_adc0_clk_bufg) then
if count < c_max_count/2 then
count := count + 1;
fmc1_led1_o <= '1';
elsif count < c_max_count then
fmc1_led1_o <= '0';
count := count + 1;
else
fmc1_led1_o <= '1';
count := 0;
end if;
end if;
end process;
fmc1_led2_o <= '0';
fmc1_led3_o <= '0';
p_counter2 : process(fmc2_adc0_clk_bufg)
variable count : natural range 0 to c_max_count;
begin
if rising_edge(fmc2_adc0_clk_bufg) then
if count < c_max_count/2 then
count := count + 1;
fmc2_led1_o <= '1';
elsif count < c_max_count then
fmc2_led1_o <= '0';
count := count + 1;
else
fmc2_led1_o <= '1';
count := 0;
end if;
end if;
end process;
fmc2_led2_o <= '0';
fmc2_led3_o <= '0';
end rtl;
|
lgpl-3.0
|
3a956e8488b3869dcece2ee54b035a77
| 0.403635 | 3.941119 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/SpiMaster.vhd
| 1 | 10,009 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Little endian encoded number to number in one-hot encoding
--
-- .. hwt-autodoc::
--
ENTITY BinToOneHot IS
GENERIC(
DATA_WIDTH : INTEGER := 1
);
PORT(
din : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
en : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF BinToOneHot IS
BEGIN
dout(0) <= en;
ASSERT DATA_WIDTH = 1 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Master for SPI interface
--
-- :ivar ~.SPI_FREQ_PESCALER: frequency prescaler to get SPI clk from main clk (Param)
-- :ivar ~.SS_WAIT_CLK_TICKS: number of SPI ticks to wait with SPI clk activation after slave select
-- :ivar ~.HAS_TX: if set true write part will be instantiated
-- :ivar ~.HAS_RX: if set true read part will be instantiated
--
-- :attention: this implementation expects that slaves are reading data on rising edge of SPI clk
-- and data from slaves are ready on risign edge as well
-- and SPI clk is kept high in idle
-- (most of them does but there are some exceptions)
--
-- .. hwt-autodoc::
--
ENTITY SpiMaster IS
GENERIC(
FREQ : INTEGER := 100000000;
HAS_MISO : BOOLEAN := TRUE;
HAS_MOSI : BOOLEAN := TRUE;
HAS_RX : BOOLEAN := TRUE;
HAS_TX : BOOLEAN := TRUE;
SLAVE_CNT : INTEGER := 1;
SPI_DATA_WIDTH : INTEGER := 1;
SPI_FREQ_PESCALER : INTEGER := 32;
SS_WAIT_CLK_TICKS : INTEGER := 4
);
PORT(
clk : IN STD_LOGIC;
data_din : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
data_dout : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_last : IN STD_LOGIC;
data_rd : OUT STD_LOGIC;
data_slave : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
data_vld : IN STD_LOGIC;
rst_n : IN STD_LOGIC;
spi_clk : OUT STD_LOGIC;
spi_cs : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
spi_miso : IN STD_LOGIC;
spi_mosi : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SpiMaster IS
--
-- Little endian encoded number to number in one-hot encoding
--
-- .. hwt-autodoc::
--
COMPONENT BinToOneHot IS
GENERIC(
DATA_WIDTH : INTEGER := 1
);
PORT(
din : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
en : IN STD_LOGIC
);
END COMPONENT;
SIGNAL clkIntern : STD_LOGIC := '1';
SIGNAL clkIntern_next : STD_LOGIC;
SIGNAL clkIntern_next_edgeDetect_last : STD_LOGIC := '1';
SIGNAL clkIntern_next_edgeDetect_last_next : STD_LOGIC;
SIGNAL clkIntern_next_falling : STD_LOGIC;
SIGNAL clkIntern_next_rising : STD_LOGIC;
SIGNAL clkOut : STD_LOGIC := '1';
SIGNAL clkOut_next : STD_LOGIC;
SIGNAL endOfWord : STD_LOGIC;
SIGNAL endOfWordDelayed : STD_LOGIC := '0';
SIGNAL endOfWordDelayed_next : STD_LOGIC;
SIGNAL endOfWordtimerCntr256 : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"FF";
SIGNAL endOfWordtimerCntr256_next : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL endOfWordtimerTick256 : STD_LOGIC;
SIGNAL rxReg : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rxReg_next : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sig_csDecoder_din : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL sig_csDecoder_dout : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL sig_csDecoder_en : STD_LOGIC;
SIGNAL slaveSelectWaitRequired : STD_LOGIC := '1';
SIGNAL slaveSelectWaitRequired_next : STD_LOGIC;
SIGNAL timersRst : STD_LOGIC;
SIGNAL txInitialized : STD_LOGIC := '0';
SIGNAL txInitialized_next : STD_LOGIC;
SIGNAL txReg : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL txReg_next : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
csDecoder_inst: BinToOneHot GENERIC MAP(
DATA_WIDTH => 1
) PORT MAP(
din => sig_csDecoder_din,
dout => sig_csDecoder_dout,
en => sig_csDecoder_en
);
assig_process_clkIntern_next: PROCESS(clkIntern, data_vld, endOfWordDelayed, endOfWordtimerCntr256)
BEGIN
IF endOfWordtimerCntr256(3 DOWNTO 0) = X"0" AND (NOT endOfWordDelayed AND data_vld) = '1' THEN
clkIntern_next <= NOT clkIntern;
ELSE
clkIntern_next <= clkIntern;
END IF;
END PROCESS;
clkIntern_next_edgeDetect_last_next <= clkIntern_next;
clkIntern_next_falling <= NOT clkIntern_next AND clkIntern_next_edgeDetect_last;
clkIntern_next_rising <= clkIntern_next AND NOT clkIntern_next_edgeDetect_last;
assig_process_clkOut_next: PROCESS(clkOut, data_vld, endOfWordDelayed, endOfWordtimerCntr256, slaveSelectWaitRequired)
BEGIN
IF slaveSelectWaitRequired = '0' AND (endOfWordtimerCntr256(3 DOWNTO 0) = X"0" AND (NOT endOfWordDelayed AND data_vld) = '1') THEN
clkOut_next <= NOT clkOut;
ELSE
clkOut_next <= clkOut;
END IF;
END PROCESS;
data_din <= rxReg;
data_rd <= endOfWordDelayed;
endOfWord <= '1' WHEN (endOfWordtimerCntr256 = X"00" AND (NOT endOfWordDelayed AND data_vld) = '1' AND timersRst = '0') ELSE '0';
endOfWordDelayed_next <= endOfWordtimerTick256;
assig_process_endOfWordtimerCntr256_next: PROCESS(data_vld, endOfWordDelayed, endOfWordtimerCntr256, timersRst)
VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
BEGIN
tmpCastExpr_0 := UNSIGNED(endOfWordtimerCntr256) - UNSIGNED'(X"01");
IF timersRst = '1' OR ((NOT endOfWordDelayed AND data_vld) = '1' AND endOfWordtimerCntr256 = X"00") THEN
endOfWordtimerCntr256_next <= X"FF";
ELSIF (NOT endOfWordDelayed AND data_vld) = '1' THEN
endOfWordtimerCntr256_next <= STD_LOGIC_VECTOR(tmpCastExpr_0);
ELSE
endOfWordtimerCntr256_next <= endOfWordtimerCntr256;
END IF;
END PROCESS;
endOfWordtimerTick256 <= endOfWord;
assig_process_rxReg_next: PROCESS(clkIntern_next_rising, rxReg, slaveSelectWaitRequired, spi_miso)
BEGIN
IF (clkIntern_next_rising AND NOT slaveSelectWaitRequired) = '1' THEN
rxReg_next <= rxReg(6 DOWNTO 0) & spi_miso;
ELSE
rxReg_next <= rxReg;
END IF;
END PROCESS;
sig_csDecoder_din <= data_slave;
sig_csDecoder_en <= data_vld;
assig_process_slaveSelectWaitRequired_next: PROCESS(data_last, data_vld, endOfWordDelayed, endOfWordtimerCntr256, endOfWordtimerTick256, slaveSelectWaitRequired)
BEGIN
IF endOfWordtimerTick256 = '1' THEN
slaveSelectWaitRequired_next <= data_last;
ELSIF endOfWordtimerCntr256(6 DOWNTO 0) = "0000000" AND (NOT endOfWordDelayed AND data_vld) = '1' THEN
slaveSelectWaitRequired_next <= '0';
ELSE
slaveSelectWaitRequired_next <= slaveSelectWaitRequired;
END IF;
END PROCESS;
spi_clk <= clkOut;
spi_cs <= NOT sig_csDecoder_dout;
spi_mosi <= txReg(7);
timersRst <= '1' WHEN ((NOT endOfWordDelayed AND data_vld) = '0' OR (slaveSelectWaitRequired = '1' AND (endOfWordtimerCntr256(6 DOWNTO 0) = "0000000" AND (NOT endOfWordDelayed AND data_vld) = '1'))) ELSE '0';
assig_process_txInitialized: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
txInitialized <= '0';
slaveSelectWaitRequired <= '1';
endOfWordtimerCntr256 <= X"FF";
endOfWordDelayed <= '0';
clkOut <= '1';
clkIntern_next_edgeDetect_last <= '1';
clkIntern <= '1';
ELSE
txInitialized <= txInitialized_next;
slaveSelectWaitRequired <= slaveSelectWaitRequired_next;
endOfWordtimerCntr256 <= endOfWordtimerCntr256_next;
endOfWordDelayed <= endOfWordDelayed_next;
clkOut <= clkOut_next;
clkIntern_next_edgeDetect_last <= clkIntern_next_edgeDetect_last_next;
clkIntern <= clkIntern_next;
END IF;
END IF;
END PROCESS;
assig_process_txInitialized_next: PROCESS(clkIntern_next_falling, data_dout, endOfWordDelayed, slaveSelectWaitRequired, txInitialized, txReg)
BEGIN
IF (clkIntern_next_falling AND NOT slaveSelectWaitRequired) = '1' THEN
IF txInitialized = '1' THEN
txReg_next <= txReg(6 DOWNTO 0) & '0';
IF endOfWordDelayed = '1' THEN
txInitialized_next <= '0';
ELSE
txInitialized_next <= txInitialized;
END IF;
ELSE
txInitialized_next <= '1';
txReg_next <= data_dout;
END IF;
ELSIF endOfWordDelayed = '1' THEN
txInitialized_next <= '0';
txReg_next <= txReg;
ELSE
txInitialized_next <= txInitialized;
txReg_next <= txReg;
END IF;
END PROCESS;
assig_process_txReg: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
txReg <= txReg_next;
rxReg <= rxReg_next;
END IF;
END PROCESS;
ASSERT FREQ = 100000000 REPORT "Generated only for this value" SEVERITY failure;
ASSERT HAS_MISO = TRUE REPORT "Generated only for this value" SEVERITY failure;
ASSERT HAS_MOSI = TRUE REPORT "Generated only for this value" SEVERITY failure;
ASSERT HAS_RX = TRUE REPORT "Generated only for this value" SEVERITY failure;
ASSERT HAS_TX = TRUE REPORT "Generated only for this value" SEVERITY failure;
ASSERT SLAVE_CNT = 1 REPORT "Generated only for this value" SEVERITY failure;
ASSERT SPI_DATA_WIDTH = 1 REPORT "Generated only for this value" SEVERITY failure;
ASSERT SPI_FREQ_PESCALER = 32 REPORT "Generated only for this value" SEVERITY failure;
ASSERT SS_WAIT_CLK_TICKS = 4 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
|
mit
|
df6a6579d72faac73fa0a62b8760868a
| 0.629434 | 4.191374 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/mem/DDR_Reg.vhd
| 1 | 794 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Double Data Rate register
--
-- .. hwt-autodoc::
--
ENTITY DDR_Reg IS
PORT(
clk : IN STD_LOGIC;
din : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rst : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF DDR_Reg IS
SIGNAL internReg : STD_LOGIC := '0';
SIGNAL internReg_0 : STD_LOGIC := '0';
BEGIN
dout <= internReg & internReg_0;
assig_process_internReg: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
internReg <= din;
END IF;
END PROCESS;
assig_process_internReg_0: PROCESS(clk)
BEGIN
IF FALLING_EDGE(clk) THEN
internReg_0 <= din;
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
fe3634bb44b9ac23d723a67c4aae8240
| 0.584383 | 3.544643 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/SimpleUnitReanamedPort4.vhd
| 1 | 1,043 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleUnitReanamedPort4 IS
PORT(
b_rx_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
b_rx_last : IN STD_LOGIC;
b_rx_ready : OUT STD_LOGIC;
b_rx_valid : IN STD_LOGIC;
b_tx_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
b_tx_last : OUT STD_LOGIC;
b_tx_ready : IN STD_LOGIC;
b_tx_valid : OUT STD_LOGIC;
rx_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rx_last : OUT STD_LOGIC;
rx_ready : IN STD_LOGIC;
rx_valid : OUT STD_LOGIC;
tx_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
tx_last : IN STD_LOGIC;
tx_ready : OUT STD_LOGIC;
tx_valid : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleUnitReanamedPort4 IS
BEGIN
b_rx_ready <= rx_ready;
b_tx_data <= tx_data;
b_tx_last <= tx_last;
b_tx_valid <= tx_valid;
rx_data <= b_rx_data;
rx_last <= b_rx_last;
rx_valid <= b_rx_valid;
tx_ready <= b_tx_ready;
END ARCHITECTURE;
|
mit
|
6bc69ed521707fbbe36372207b3ec4b2
| 0.58581 | 3.058651 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/fixed_dds/fixed_dds.vhd
| 1 | 4,335 |
-------------------------------------------------------------------------------
-- Title : Fixed sin-cos DDS
-- Project :
-------------------------------------------------------------------------------
-- File : fixed_dds.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Fixed frequency phase and quadrature DDS for use in tuned DDCs.
-- Moreover, it has an option to dynamically change the output signal phase,
-- according to the phase_i input.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.dsp_cores_pkg.all;
use work.bpm_cores_pkg.all;
-------------------------------------------------------------------------------
entity fixed_dds is
generic (
g_number_of_points : natural := 203; -- Number of points of sin and cos (each)
g_output_width : natural := 16; -- Output resolution
g_sin_file : string := "./dds_sin.ram"; -- Files with points data
g_cos_file : string := "./dds_cos.ram"
);
port (
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
valid_i : in std_logic;
sin_o : out std_logic_vector(g_output_width-1 downto 0);
cos_o : out std_logic_vector(g_output_width-1 downto 0);
valid_o : out std_logic);
end entity fixed_dds;
-------------------------------------------------------------------------------
architecture str of fixed_dds is
constant c_bus_size : natural := f_log2_size(g_number_of_points);
signal cur_address : std_logic_vector(c_bus_size-1 downto 0);
signal rst_n : std_logic;
signal cos_reg, sin_reg : std_logic_vector(g_output_width-1 downto 0);
signal cur_address_valid : std_logic_vector(0 downto 0);
signal cur_address_valid_d2 : std_logic_vector(0 downto 0);
signal valid_out_int : std_logic_vector(0 downto 0);
begin -- architecture str
cmp_lut_sweep : lut_sweep
generic map (
g_number_of_points => g_number_of_points,
g_bus_size => c_bus_size)
port map (
rst_i => rst_i,
clk_i => clk_i,
ce_i => ce_i,
valid_i => valid_i,
address_o => cur_address,
valid_o => cur_address_valid(0));
rst_n <= not(rst_i);
-- FIXME. LUT is configured to have a read latency of 2.
-- We need to compensate for that. However, this behavior
-- can change if we add additional pipeline register and
-- we wouldn't know about it.
cmp_reg_cur_address_valid : pipeline
generic map (
g_width => 1,
g_depth => 2)
port map (
data_i => cur_address_valid,
clk_i => clk_i,
ce_i => ce_i,
data_o => cur_address_valid_d2
);
cmp_sin_lut : dds_sin_lut
port map (
clka => clk_i,
addra => cur_address,
douta => sin_reg
);
cmp_cos_lut : dds_cos_lut
port map (
clka => clk_i,
addra => cur_address,
douta => cos_reg
);
cmp_reg_sin : pipeline
generic map (
g_width => g_output_width,
g_depth => 2)
port map (
data_i => sin_reg,
clk_i => clk_i,
ce_i => ce_i,
data_o => sin_o);
cmp_reg_cos : pipeline
generic map (
g_width => g_output_width,
g_depth => 2)
port map (
data_i => cos_reg,
clk_i => clk_i,
ce_i => ce_i,
data_o => cos_o);
cmp_cur_address_reg_2 : pipeline
generic map (
g_width => 1,
g_depth => 2)
port map (
data_i => cur_address_valid_d2,
clk_i => clk_i,
ce_i => ce_i,
data_o => valid_out_int);
valid_o <= valid_out_int(0);
end architecture str;
-------------------------------------------------------------------------------
|
lgpl-3.0
|
fe1f7c6d23ec9d18d934fa3e89e0731d
| 0.473126 | 3.627615 | false | false | false | false |
zeruniverse/pipelined_CPU
|
ISE project/ipcore_dir/mem_ins.vhd
| 1 | 5,714 |
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file mem_ins.vhd when simulating
-- the core, mem_ins. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY mem_ins IS
port (
a: in std_logic_vector(5 downto 0);
spo: out std_logic_vector(31 downto 0));
END mem_ins;
ARCHITECTURE mem_ins_a OF mem_ins IS
-- synthesis translate_off
component wrapped_mem_ins
port (
a: in std_logic_vector(5 downto 0);
spo: out std_logic_vector(31 downto 0));
end component;
-- Configuration specification
for all : wrapped_mem_ins use entity XilinxCoreLib.dist_mem_gen_v5_1(behavioral)
generic map(
c_has_clk => 0,
c_has_qdpo_clk => 0,
c_has_qdpo_ce => 0,
c_parser_type => 1,
c_has_d => 0,
c_has_spo => 1,
c_read_mif => 1,
c_has_qspo => 0,
c_width => 32,
c_reg_a_d_inputs => 0,
c_has_we => 0,
c_pipeline_stages => 0,
c_has_qdpo_rst => 0,
c_reg_dpra_input => 0,
c_qualify_we => 0,
c_family => "spartan3",
c_sync_enable => 1,
c_depth => 64,
c_has_qspo_srst => 0,
c_has_qdpo_srst => 0,
c_has_dpra => 0,
c_qce_joined => 0,
c_mem_type => 0,
c_has_i_ce => 0,
c_has_dpo => 0,
c_mem_init_file => "mem_ins.mif",
c_default_data => "0",
c_has_spra => 0,
c_has_qspo_ce => 0,
c_addr_width => 6,
c_has_qspo_rst => 0,
c_has_qdpo => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_mem_ins
port map (
a => a,
spo => spo);
-- synthesis translate_on
END mem_ins_a;
|
gpl-3.0
|
8a2c2531c7ce05db7857ea799bfa0f22
| 0.511901 | 4.415765 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/sw_windowing/input_conditioner.vhd
| 1 | 5,303 |
-------------------------------------------------------------------------------
-- Title : Input Conditioner
-- Project :
-------------------------------------------------------------------------------
-- File : input_conditioner.vhd
-- Author : Gustavo BM Bruno
-- Company :
-- Created : 2014-01-30
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Define the timing for the switch at the RFFE board and apply a
-- proper window at the switch to avoid the switching noise.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-30 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.genram_pkg.all;
use work.dsp_cores_pkg.all;
use work.bpm_cores_pkg.all;
entity input_conditioner is
generic (
--g_clk_freq : real := 120.0e6; -- System clock frequency
--g_sw_freq : real := 100.0e3; -- Desired switching frequency
g_sw_interval : natural := 1000;
g_input_width : natural := 16;
g_output_width : natural := 24;
g_window_width : natural := 24;
g_input_delay : natural := 2;
g_window_coef_file : string);
port (
rst_n_i : in std_logic; -- Reset data
clk_i : in std_logic; -- Main clock
adc_a_i : in std_logic_vector(g_input_width-1 downto 0);
adc_b_i : in std_logic_vector(g_input_width-1 downto 0);
adc_c_i : in std_logic_vector(g_input_width-1 downto 0);
adc_d_i : in std_logic_vector(g_input_width-1 downto 0);
switch_o : out std_logic; -- Switch position output
switch_en_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
a_o : out std_logic_vector(g_output_width-1 downto 0);
b_o : out std_logic_vector(g_output_width-1 downto 0);
c_o : out std_logic_vector(g_output_width-1 downto 0);
d_o : out std_logic_vector(g_output_width-1 downto 0);
dbg_cur_address_o : out std_logic_vector(31 downto 0));
end entity input_conditioner;
architecture structural of input_conditioner is
--constant c_mem_size : natural := natural(g_clk_freq/(g_sw_freq*2.0)) + 1;
constant c_mem_size : natural := g_sw_interval/2 + 1;
constant c_bus_size : natural := f_log2_size(c_mem_size);
signal cur_address : std_logic_vector(c_bus_size-1 downto 0) := (others => '0'); -- Current index for lookup table
signal window_factor : std_logic_vector(g_window_width-1 downto 0); -- Current value of the window
-- factor, signed int
signal reset : std_logic;
begin
reset <= not rst_n_i;
cmp_lut : sw_windowing_n_251_tukey_0_2
port map (
clka => clk_i,
addra => cur_address,
douta => window_factor
);
cmp_index : counter
generic map (
g_mem_size => c_mem_size,
g_bus_size => c_bus_size)
port map (
clk_i => clk_i,
index_o => cur_address,
ce_i => '1',
rst_n_i => rst_n_i,
switch_delay_i => switch_delay_i,
switch_o => switch_o,
switch_en_i => switch_en_i
);
dbg_cur_address_o(dbg_cur_address_o'left downto cur_address'left+1)
<= (others =>'0');
dbg_cur_address_o(cur_address'left downto 0) <= cur_address;
cmp_multiplier_a : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_a_i,
b_i => window_factor,
valid_i => '1',
p_o => a_o,
ce_i => '1',
clk_i => clk_i,
rst_i => reset);
cmp_multiplier_b : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_b_i,
b_i => window_factor,
valid_i => '1',
p_o => b_o,
ce_i => '1',
clk_i => clk_i,
rst_i => reset);
cmp_multiplier_c : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_c_i,
b_i => window_factor,
valid_i => '1',
p_o => c_o,
ce_i => '1',
clk_i => clk_i,
rst_i => reset);
cmp_multiplier_d : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_d_i,
b_i => window_factor,
valid_i => '1',
p_o => d_o,
ce_i => '1',
clk_i => clk_i,
rst_i => reset);
end structural;
|
lgpl-3.0
|
8eaf27f54ba8959608990dadbb8d976e
| 0.493306 | 3.337319 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/TernaryInConcatExample.vhd
| 1 | 1,669 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TernaryInConcatExample IS
PORT(
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF TernaryInConcatExample IS
BEGIN
assig_process_c: PROCESS(a, b)
VARIABLE tmpBool2std_logic_0 : STD_LOGIC;
VARIABLE tmpBool2std_logic_1 : STD_LOGIC;
VARIABLE tmpBool2std_logic_2 : STD_LOGIC;
VARIABLE tmpBool2std_logic_3 : STD_LOGIC;
VARIABLE tmpBool2std_logic_4 : STD_LOGIC;
VARIABLE tmpBool2std_logic_5 : STD_LOGIC;
BEGIN
IF a > b THEN
tmpBool2std_logic_0 := '1';
ELSE
tmpBool2std_logic_0 := '0';
END IF;
IF a >= b THEN
tmpBool2std_logic_1 := '1';
ELSE
tmpBool2std_logic_1 := '0';
END IF;
IF a = b THEN
tmpBool2std_logic_2 := '1';
ELSE
tmpBool2std_logic_2 := '0';
END IF;
IF a <= b THEN
tmpBool2std_logic_3 := '1';
ELSE
tmpBool2std_logic_3 := '0';
END IF;
IF a < b THEN
tmpBool2std_logic_4 := '1';
ELSE
tmpBool2std_logic_4 := '0';
END IF;
IF a /= b THEN
tmpBool2std_logic_5 := '1';
ELSE
tmpBool2std_logic_5 := '0';
END IF;
c <= X"F" & tmpBool2std_logic_5 & tmpBool2std_logic_4 & tmpBool2std_logic_3 & tmpBool2std_logic_2 & tmpBool2std_logic_1 & tmpBool2std_logic_0 & "0000000000000000000000";
END PROCESS;
END ARCHITECTURE;
|
mit
|
8e677bc01af2b706af0d76b781cb4564
| 0.548832 | 3.477083 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd
| 1 | 35,666 |
------------------------------------------------------------------------------
-- Title : Top Etherbone test design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-11-12
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top dsign for testing the integration of Etherbone and
-- MAC cores
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-12 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_ebone is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_ebone;
architecture rtl of dbe_bpm_ebone is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 10; -- LED, Button,
-- General Dual-port memory, Buffer Single-por memory, UART, DMA control port, MAC,
--Etherbone
-- Number of masters
constant c_masters : natural := 8; -- LM32 master, Data + Instruction,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"20000000"), -- 64KB RAM
--3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30014000"), -- DMA control port
--4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30015000"), -- Ethernet MAC control port
--5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30016000"), -- Ethernet Adapter control port
--6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30017000"), -- Etherbone control port
--7 => f_sdb_embed_device(c_xwb_uart_sdb, x"30018000"), -- UART control port
--8 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"30019000"), -- GPIO LED
--9 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"3001A000") -- GPIO Button
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"60000000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"70000000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"80000000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"90000000"), -- Etherbone control port
7 => f_sdb_embed_device(c_xwb_uart_sdb, x"A0000000"), -- UART control port
8 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"B0000000"), -- GPIO LED
9 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"C0000000") -- GPIO Button
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"30000000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- Counter signal
signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
constant s_counter_full : integer := 100000000;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal CONTROL2 : std_logic_vector(35 downto 0);
signal CONTROL3 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 2 signals
signal TRIG_ILA2_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 3 signals
signal TRIG_ILA3_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
--component chipscope_icon_2_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0)
--);
--end component;
component chipscope_icon_4_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => 1 -- CLK_SYS
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => false, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
cmp_lm32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug"
) -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(0), -- Data bus
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1), -- Instruction bus
iwb_i => cbar_slave_o(1)
);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
4 => irq_tx_done, others => '0');
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(4),
wb_master_out => cbar_slave_i(4),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
-- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
-- The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(5),
tx_ram_i => cbar_slave_o(5),
rx_ram_o => cbar_slave_i(6),
rx_ram_i => cbar_slave_o(6),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(7) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(7);
-- Slave 7 is the UART
cmp_uart : xwb_simple_uart
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map (
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(7),
slave_o => cbar_master_i(7),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o
);
-- Slave 8 is the LED driver
cmp_leds : xwb_gpio_port
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_pins => c_leds_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(8),
slave_o => cbar_master_i(8),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => gpio_leds_int,
gpio_in_i => gpio_leds_int,
gpio_oen_o => open
);
leds_o <= gpio_leds_int;
-- Slave 9 is the Button driver
cmp_buttons : xwb_gpio_port
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_pins => c_buttons_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(9),
slave_o => cbar_master_i(9),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => open,
gpio_in_i => buttons_i,
gpio_oen_o => open
);
---- Xilinx Chipscope
cmp_chipscope_icon_0 : chipscope_icon_4_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1,
CONTROL2 => CONTROL2,
CONTROL3 => CONTROL3
);
cmp_chipscope_ila_0_ethmac : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_sys,
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- ETHMAC master output (slave input) control data
TRIG_ILA0_0 <= cbar_slave_o(4).dat;
-- ETHMAC master input (slave output) control data
TRIG_ILA0_1 <= cbar_slave_i(4).dat;
-- ETHMAC master control input (slave output) control signals
TRIG_ILA0_2(4 downto 0) <= cbar_slave_o(4).ack &
cbar_slave_o(4).err &
cbar_slave_o(4).rty &
cbar_slave_o(4).stall &
cbar_slave_o(4).int;
TRIG_ILA0_2(31 downto 5) <= (others => '0');
-- ETHMAC master control output (slave input) control signals
-- Partial decoding. Thus, only the LSB part of address matters to
-- a specific slave core
TRIG_ILA0_3(18 downto 0) <= cbar_slave_i(4).cyc &
cbar_slave_i(4).stb &
cbar_slave_i(4).adr(11 downto 0) &
cbar_slave_i(4).sel &
cbar_slave_i(4).we;
TRIG_ILA0_3(31 downto 19) <= (others => '0');
-- Etherbone debuging signals
--cmp_chipscope_ila_1_etherbone : chipscope_ila
--port map (
-- CONTROL => CONTROL1,
-- CLK => clk_sys,
-- TRIG0 => TRIG_ILA1_0,
-- TRIG1 => TRIG_ILA1_1,
-- TRIG2 => TRIG_ILA1_2,
-- TRIG3 => TRIG_ILA1_3
--);
--TRIG_ILA1_0 <= wb_ebone_out.dat;
--TRIG_ILA1_1 <= wb_ebone_in.dat;
--TRIG_ILA1_2 <= wb_ebone_out.adr;
--TRIG_ILA1_3(6 downto 0) <= wb_ebone_out.cyc &
-- wb_ebone_out.stb &
-- wb_ebone_out.sel &
-- wb_ebone_out.we;
--TRIG_ILA1_3(11 downto 7) <= wb_ebone_in.ack &
-- wb_ebone_in.err &
-- wb_ebone_in.rty &
-- wb_ebone_in.stall &
-- wb_ebone_in.int;
--TRIG_ILA1_3(31 downto 12) <= (others => '0');
cmp_chipscope_ila_1_ethmac_rx : chipscope_ila
port map (
CONTROL => CONTROL1,
CLK => mrx_clk_pad_i,
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3
);
TRIG_ILA1_0(7 downto 0) <= mrxd_pad_i &
mrxdv_pad_i &
mrxerr_pad_i &
mcoll_pad_i &
mcrs_pad_i;
TRIG_ILA1_0(31 downto 8) <= (others => '0');
TRIG_ILA1_1 <= (others => '0');
TRIG_ILA1_2 <= (others => '0');
TRIG_ILA1_3 <= (others => '0');
cmp_chipscope_ila_1_ethmac_tx : chipscope_ila
port map (
CONTROL => CONTROL2,
CLK => mtx_clk_pad_i,
TRIG0 => TRIG_ILA2_0,
TRIG1 => TRIG_ILA2_1,
TRIG2 => TRIG_ILA2_2,
TRIG3 => TRIG_ILA2_3
);
TRIG_ILA2_0(5 downto 0) <= mtxd_pad_int &
mtxen_pad_int &
mtxerr_pad_int;
TRIG_ILA2_0(31 downto 6) <= (others => '0');
TRIG_ILA2_1 <= (others => '0');
TRIG_ILA2_2 <= (others => '0');
TRIG_ILA2_3 <= (others => '0');
cmp_chipscope_ila_1_ethmac_miim : chipscope_ila
port map (
CONTROL => CONTROL3,
CLK => clk_sys,
TRIG0 => TRIG_ILA3_0,
TRIG1 => TRIG_ILA3_1,
TRIG2 => TRIG_ILA3_2,
TRIG3 => TRIG_ILA3_3
);
TRIG_ILA3_0(4 downto 0) <= mdc_pad_int &
ethmac_md_in &
ethmac_md_out &
ethmac_md_oe &
ethmac_int;
TRIG_ILA3_0(31 downto 6) <= (others => '0');
TRIG_ILA3_1 <= (others => '0');
TRIG_ILA3_2 <= (others => '0');
TRIG_ILA3_3 <= (others => '0');
end rtl;
|
lgpl-3.0
|
b4c97b11fc8f75a6588aff5093a8ca08
| 0.405288 | 4.332604 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/rtlLvl/arithmetic/LeadingZero.vhd
| 1 | 955 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY LeadingZero IS
PORT(
s_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_indexOfFirstZero : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF LeadingZero IS
BEGIN
assig_process_s_indexOfFirstZero: PROCESS(s_in)
BEGIN
IF s_in(0) = '0' THEN
s_indexOfFirstZero <= X"00";
ELSIF s_in(1) = '0' THEN
s_indexOfFirstZero <= X"01";
ELSIF s_in(2) = '0' THEN
s_indexOfFirstZero <= X"02";
ELSIF s_in(3) = '0' THEN
s_indexOfFirstZero <= X"03";
ELSIF s_in(4) = '0' THEN
s_indexOfFirstZero <= X"04";
ELSIF s_in(5) = '0' THEN
s_indexOfFirstZero <= X"05";
ELSIF s_in(6) = '0' THEN
s_indexOfFirstZero <= X"06";
ELSE
s_indexOfFirstZero <= X"07";
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
940cc1386dcc90c9648fdb8b7387faa5
| 0.547644 | 3.460145 | false | false | false | false |
nanomolina/MIPS
|
prueba/mux2.vhd
| 3 | 439 |
library ieee;
use ieee.std_logic_1164.all;
entity mux2 is
generic (MAX : integer := 32);
port (
d0, d1: in std_logic_vector((MAX-1) downto 0);
s: in std_logic;
y: out std_logic_vector((MAX-1) downto 0));
end entity;
architecture behavior of mux2 is
begin
process (d0, d1, s) begin
if (s = '0') then
y <= d0;
elsif (s = '1') then
y <= d1;
end if;
end process;
end behavior;
|
gpl-3.0
|
62ee75db330351cbe8f32391eda0f751
| 0.567198 | 2.926667 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/tb_Gray_Binarization.vhd
| 2 | 16,021 |
-- tb_Gray_Binarization.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Gray_Binarization is
end entity tb_Gray_Binarization;
architecture rtl of tb_Gray_Binarization is
component Gray_Binarization_GN is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset_n
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Avalon_ST_Sink_endofpacket : in std_logic := 'X'; -- wire
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_valid : out std_logic; -- wire
Avalon_ST_Sink_valid : in std_logic := 'X'; -- wire
Avalon_ST_Source_endofpacket : out std_logic; -- wire
Avalon_ST_Source_startofpacket : out std_logic; -- wire
Avalon_ST_Source_ready : in std_logic := 'X'; -- wire
Avalon_MM_Slave_write : in std_logic := 'X'; -- wire
Avalon_ST_Sink_ready : out std_logic; -- wire
Avalon_ST_Sink_startofpacket : in std_logic := 'X'; -- wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0) -- wire
);
end component Gray_Binarization_GN;
component alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic (
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic; -- reset
clock_out : out std_logic; -- clk
reg_aclr_out : out std_logic; -- reset
tb_aclr : out std_logic -- reset
);
end component alt_dspbuilder_testbench_clock_GNCGUFKHRR;
component alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GNOXVOQUET;
component alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic -- wire
);
end component alt_dspbuilder_testbench_salt_GNDBMPYDND;
component alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN6DKNTQ5M;
component alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN7Z4SHGOK;
component alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_testbench_capture_GNQX2JTRTZ;
component alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_testbench_capture_GNHCRI5YMO;
signal salt_avalon_st_sink_data_output_wire : std_logic_vector(23 downto 0); -- salt_Avalon_ST_Sink_data:output -> dut:Avalon_ST_Sink_data
signal clock_clock_tb_reset : std_logic; -- Clock:tb_aclr -> [salt_Avalon_MM_Slave_address:aclr, salt_Avalon_MM_Slave_write:aclr, salt_Avalon_MM_Slave_writedata:aclr, salt_Avalon_ST_Sink_data:aclr, salt_Avalon_ST_Sink_endofpacket:aclr, salt_Avalon_ST_Sink_startofpacket:aclr, salt_Avalon_ST_Sink_valid:aclr, salt_Avalon_ST_Source_ready:aclr]
signal clock_clock_tb_clk : std_logic; -- Clock:clock_out -> [capture_Avalon_ST_Sink_ready:clock, capture_Avalon_ST_Source_data:clock, capture_Avalon_ST_Source_endofpacket:clock, capture_Avalon_ST_Source_startofpacket:clock, capture_Avalon_ST_Source_valid:clock, dut:Clock, salt_Avalon_MM_Slave_address:clock, salt_Avalon_MM_Slave_write:clock, salt_Avalon_MM_Slave_writedata:clock, salt_Avalon_ST_Sink_data:clock, salt_Avalon_ST_Sink_endofpacket:clock, salt_Avalon_ST_Sink_startofpacket:clock, salt_Avalon_ST_Sink_valid:clock, salt_Avalon_ST_Source_ready:clock]
signal salt_avalon_st_sink_endofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_endofpacket:output -> dut:Avalon_ST_Sink_endofpacket
signal salt_avalon_mm_slave_address_output_wire : std_logic_vector(1 downto 0); -- salt_Avalon_MM_Slave_address:output -> dut:Avalon_MM_Slave_address
signal salt_avalon_mm_slave_writedata_output_wire : std_logic_vector(31 downto 0); -- salt_Avalon_MM_Slave_writedata:output -> dut:Avalon_MM_Slave_writedata
signal salt_avalon_st_sink_valid_output_wire : std_logic; -- salt_Avalon_ST_Sink_valid:output -> dut:Avalon_ST_Sink_valid
signal salt_avalon_st_source_ready_output_wire : std_logic; -- salt_Avalon_ST_Source_ready:output -> dut:Avalon_ST_Source_ready
signal salt_avalon_mm_slave_write_output_wire : std_logic; -- salt_Avalon_MM_Slave_write:output -> dut:Avalon_MM_Slave_write
signal salt_avalon_st_sink_startofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_startofpacket:output -> dut:Avalon_ST_Sink_startofpacket
signal dut_avalon_st_source_valid_wire : std_logic; -- dut:Avalon_ST_Source_valid -> capture_Avalon_ST_Source_valid:input
signal clock_clock_reg_reset_reset : std_logic; -- Clock:reg_aclr_out -> [capture_Avalon_ST_Sink_ready:aclr, capture_Avalon_ST_Source_data:aclr, capture_Avalon_ST_Source_endofpacket:aclr, capture_Avalon_ST_Source_startofpacket:aclr, capture_Avalon_ST_Source_valid:aclr]
signal dut_avalon_st_source_endofpacket_wire : std_logic; -- dut:Avalon_ST_Source_endofpacket -> capture_Avalon_ST_Source_endofpacket:input
signal dut_avalon_st_source_startofpacket_wire : std_logic; -- dut:Avalon_ST_Source_startofpacket -> capture_Avalon_ST_Source_startofpacket:input
signal dut_avalon_st_sink_ready_wire : std_logic; -- dut:Avalon_ST_Sink_ready -> capture_Avalon_ST_Sink_ready:input
signal dut_avalon_st_source_data_wire : std_logic_vector(23 downto 0); -- dut:Avalon_ST_Source_data -> capture_Avalon_ST_Source_data:input
signal clock_clock_output_reset : std_logic; -- Clock:aclr_out -> clock_clock_output_reset:in
signal clock_clock_output_reset_ports_inv : std_logic; -- clock_clock_output_reset:inv -> dut:aclr
begin
dut : component Gray_Binarization_GN
port map (
Clock => clock_clock_tb_clk, -- Clock.clk
aclr => clock_clock_output_reset_ports_inv, -- .reset_n
Avalon_ST_Sink_data => salt_avalon_st_sink_data_output_wire, -- Avalon_ST_Sink_data.wire
Avalon_ST_Sink_endofpacket => salt_avalon_st_sink_endofpacket_output_wire, -- Avalon_ST_Sink_endofpacket.wire
Avalon_MM_Slave_address => salt_avalon_mm_slave_address_output_wire, -- Avalon_MM_Slave_address.wire
Avalon_MM_Slave_writedata => salt_avalon_mm_slave_writedata_output_wire, -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Source_valid => dut_avalon_st_source_valid_wire, -- Avalon_ST_Source_valid.wire
Avalon_ST_Sink_valid => salt_avalon_st_sink_valid_output_wire, -- Avalon_ST_Sink_valid.wire
Avalon_ST_Source_endofpacket => dut_avalon_st_source_endofpacket_wire, -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Source_startofpacket => dut_avalon_st_source_startofpacket_wire, -- Avalon_ST_Source_startofpacket.wire
Avalon_ST_Source_ready => salt_avalon_st_source_ready_output_wire, -- Avalon_ST_Source_ready.wire
Avalon_MM_Slave_write => salt_avalon_mm_slave_write_output_wire, -- Avalon_MM_Slave_write.wire
Avalon_ST_Sink_ready => dut_avalon_st_sink_ready_wire, -- Avalon_ST_Sink_ready.wire
Avalon_ST_Sink_startofpacket => salt_avalon_st_sink_startofpacket_output_wire, -- Avalon_ST_Sink_startofpacket.wire
Avalon_ST_Source_data => dut_avalon_st_source_data_wire -- Avalon_ST_Source_data.wire
);
clock : component alt_dspbuilder_testbench_clock_GNCGUFKHRR
generic map (
SIMULATION_START_CYCLE => 5,
RESET_LATENCY => 0,
RESET_REGISTER_CASCADE_DEPTH => 0
)
port map (
clock_out => clock_clock_tb_clk, -- clock_tb.clk
tb_aclr => clock_clock_tb_reset, -- .reset
aclr_out => clock_clock_output_reset, -- clock_output.reset
reg_aclr_out => clock_clock_reg_reset_reset -- clock_reg_reset.reset
);
salt_avalon_st_sink_data : component alt_dspbuilder_testbench_salt_GNOXVOQUET
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_data.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_data_output_wire -- output.wire
);
salt_avalon_st_sink_endofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_endofpacket.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_endofpacket_output_wire -- output.wire
);
salt_avalon_mm_slave_address : component alt_dspbuilder_testbench_salt_GN6DKNTQ5M
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_address.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_address_output_wire -- output.wire
);
salt_avalon_mm_slave_writedata : component alt_dspbuilder_testbench_salt_GN7Z4SHGOK
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_writedata.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_writedata_output_wire -- output.wire
);
salt_avalon_st_sink_valid : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_valid.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_valid_output_wire -- output.wire
);
salt_avalon_st_source_ready : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_ready.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_source_ready_output_wire -- output.wire
);
salt_avalon_mm_slave_write : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_write.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_write_output_wire -- output.wire
);
salt_avalon_st_sink_startofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_startofpacket.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_startofpacket_output_wire -- output.wire
);
capture_avalon_st_source_valid : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_valid.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_valid_wire -- input.wire
);
capture_avalon_st_source_endofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_endofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_endofpacket_wire -- input.wire
);
capture_avalon_st_source_startofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_startofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_startofpacket_wire -- input.wire
);
capture_avalon_st_sink_ready : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_ready.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_sink_ready_wire -- input.wire
);
capture_avalon_st_source_data : component alt_dspbuilder_testbench_capture_GNHCRI5YMO
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_data.capture.msim",
DSPBTYPE => "UINT [24, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_data_wire -- input.wire
);
clock_clock_output_reset_ports_inv <= not clock_clock_output_reset;
end architecture rtl; -- of tb_Gray_Binarization
|
mit
|
e1315eb24228ba2e1af31e627e9206eb
| 0.594595 | 3.440936 | false | true | false | false |
nanomolina/MIPS
|
prueba/fetch.vhd
| 2 | 2,208 |
library ieee;
use ieee.std_logic_1164.all;
entity fetch is
port(
jumpM, PcSrcM, clk, reset: in std_logic;
PcBranchM: in std_logic_vector(31 downto 0);
InstrF, PCF, PCPlus4F: out std_logic_vector(31 downto 0));
end entity;
architecture f_arq of fetch is
component mux2
generic (MAX : integer := 32);
port (
d0, d1: in std_logic_vector((MAX-1) downto 0);
s: in std_logic;
y: out std_logic_vector((MAX-1) downto 0));
end component;
component flopr
port (
d: in std_logic_vector(31 downto 0);
rst, clk: in std_logic;
q: out std_logic_vector(31 downto 0));
end component;
component imem
port (
a: in std_logic_vector (5 downto 0);
rd: out std_logic_vector (31 downto 0));
end component;
component adder
port (
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
y : out std_logic_vector(31 downto 0));
end component;
signal PCNext, PCPlus4F1, PCJump, PC1, PCF_s,
Instrf_s: std_logic_vector(31 downto 0);
signal QUATRO: std_logic_vector(31 downto 0) := x"00000004";
signal IMEMIN: std_logic_vector(5 downto 0);
begin
mux2_1: mux2 port map(
d0 => PCPlus4F1,
d1 => PcBranchM,
s => PCSrcM,
y => PCNext);
mux2_2: mux2 port map(
d0 => PCNext,
d1 => PCJump,
s => jumpM,
y => PC1);
flopr1: flopr port map(
d => PC1,
clk => clk,
rst => reset,
q => PCF_s);
adder1: adder port map(
a => PCF_s,
b => QUATRO,
y => PCPlus4F1);
imem1: imem port map(
a => IMEMIN,
rd => Instrf_s);
PCJump <= PCPlus4F1(31 downto 28) & Instrf_s(25 downto 0) & "00";
IMEMIN <= PCF_s(7 downto 2);
InstrF <= Instrf_s;
PCF <= PCF_s;
PCPlus4F <= PCPlus4F1;
end architecture;
|
gpl-3.0
|
796cc81a0cedc9b33b41a074d99653ea
| 0.48279 | 3.748727 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/PLL/top_nto1_pll_diff_rx.vhd
| 1 | 7,960 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_pll_diff_rx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example differential input receiver for clock and data using PLL
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_pll_diff_rx is port (
reset : in std_logic ; -- reset (active high)
clkin_p, clkin_n : in std_logic ; -- lvds clock input
datain_p, datain_n : in std_logic_vector(5 downto 0) ; -- lvds data inputs
dummy_out : out std_logic_vector(41 downto 0)) ; -- dummy outputs
end top_nto1_pll_diff_rx ;
architecture arch_top_nto1_pll_diff_rx of top_nto1_pll_diff_rx is
component serdes_1_to_n_data_s8_diff generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic ; -- Set generation of phase detector logic
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclk : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
debug_in : in std_logic_vector(1 downto 0) ; -- input debug data
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end component ;
component serdes_1_to_n_clk_pll_s8_diff generic (
PLLD : integer := 1 ; -- Parameter to set division for PLL
CLKIN_PERIOD : real := 6.700 ; -- Set PLL multiplier
PLLX : integer := 2 ; -- Set PLL multiplier
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
BS : boolean := FALSE) ; -- Parameter to enable bitslip TRUE or FALSE
port (
clkin_p : in std_logic ; -- Input from LVDS receiver pin
clkin_n : in std_logic ; -- Input from LVDS receiver pin
reset : in std_logic ; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0) ; -- Data to define pattern that bitslip should search for
pattern2 : in std_logic_vector(S-1 downto 0) ; -- Data to define alternate pattern that bitslip should search for
rxioclk : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_pll_x1 : out std_logic ; -- Global clock
bitslip : out std_logic ; -- Bitslip control line
datain : out std_logic_vector(S-1 downto 0) ; -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end component ;
-- Parameters for serdes factor and number of IO pins
constant S : integer := 7 ; -- Set the serdes factor to be 4
constant D : integer := 6 ; -- Set the number of inputs and outputs to be 6
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal clk_iserdes_data : std_logic_vector(6 downto 0) ;
signal rx_bufg_x1 : std_logic ;
signal rxd : std_logic_vector(DS downto 0) ;
signal capture : std_logic_vector(6 downto 0) ;
signal counter : std_logic_vector(3 downto 0) ;
signal bitslip : std_logic ;
signal rst : std_logic ;
signal rx_serdesstrobe : std_logic ;
signal rx_bufpll_clk_xn : std_logic ;
signal rx_bufpll_lckd : std_logic ;
signal not_bufpll_lckd : std_logic ;
begin
rst <= reset ; -- active high reset pin
-- Clock Input, Generate ioclocks via PLL
clkin : serdes_1_to_n_clk_pll_s8_diff generic map(
CLKIN_PERIOD => 6.700,
PLLD => 1,
PLLX => S,
S => S,
BS => TRUE) -- Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
port map (
clkin_p => clkin_p,
clkin_n => clkin_n,
rxioclk => rx_bufpll_clk_xn,
pattern1 => "1100001", -- default values for 7:1 video applications
pattern2 => "1100011",
rx_serdesstrobe => rx_serdesstrobe,
rx_bufg_pll_x1 => rx_bufg_x1,
bitslip => bitslip,
reset => rst,
datain => clk_iserdes_data,
rx_bufpll_lckd => rx_bufpll_lckd) ;
-- 6 Video Data Inputs
not_bufpll_lckd <= not rx_bufpll_lckd ;
datain : serdes_1_to_n_data_s8_diff generic map(
S => S,
D => D)
port map (
use_phase_detector => '1',
datain_p => datain_p,
datain_n => datain_n,
rxioclk => rx_bufpll_clk_xn,
rxserdesstrobe => rx_serdesstrobe,
gclk => rx_bufg_x1,
bitslip => bitslip,
reset => not_bufpll_lckd,
debug_in => "00",
data_out => rxd,
debug => open) ;
process (rx_bufg_x1)
begin
if rx_bufg_x1'event and rx_bufg_x1 = '1' then
dummy_out <= rxd ;
end if ;
end process ;
end arch_top_nto1_pll_diff_rx ;
|
apache-2.0
|
6f8bc3989058072f90abad21e0eb89b6
| 0.617337 | 3.345944 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd
| 1 | 62,720 |
------------------------------------------------------------------------------
-- Title : Top FMC516 design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-02-25
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the FMC516
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-25 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_fmc516 is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------
-- FMC516 ports
-----------------------------
-- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM,
-- AD7417 temperature diodes and AD7417 supply rails
sys_i2c_scl_b : inout std_logic;
sys_i2c_sda_b : inout std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i : in std_logic;
adc_clk0_n_i : in std_logic;
adc_clk1_p_i : in std_logic;
adc_clk1_n_i : in std_logic;
adc_clk2_p_i : in std_logic;
adc_clk2_n_i : in std_logic;
adc_clk3_p_i : in std_logic;
adc_clk3_n_i : in std_logic;
-- DDR ADC data channels.
adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o : out std_logic;
adc_clk_div_rst_n_o : out std_logic;
-- FMC Front leds. Typical uses: Over Range or Full Scale
-- condition.
fmc_leds_o : out std_logic_vector(1 downto 0);
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o : out std_logic;
sys_spi_data_b : inout std_logic;
sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- External Trigger To/From FMC
m2c_trig_p_i : in std_logic;
m2c_trig_n_i : in std_logic;
c2m_trig_p_o : out std_logic;
c2m_trig_n_o : out std_logic;
-- LMK (National Semiconductor) is the clock and distribution IC,
-- programmable via Microwire Interface
lmk_lock_i : in std_logic;
lmk_sync_o : out std_logic;
lmk_uwire_latch_en_o : out std_logic;
lmk_uwire_data_o : out std_logic;
lmk_uwire_clock_o : out std_logic;
-- Programable VCXO via I2C
vcxo_i2c_sda_b : inout std_logic;
vcxo_i2c_scl_b : inout std_logic;
vcxo_pd_l_o : out std_logic;
-- One-wire To/From DS2431 (VMETRO Data)
fmc_id_dq_b : inout std_logic;
-- One-wire To/From DS2432 SHA-1 (SP-Devices key)
fmc_key_dq_b : inout std_logic;
-- General board pins
fmc_pwr_good_i : in std_logic;
-- Internal/External clock distribution selection
fmc_clk_sel_o : out std_logic;
-- Reset ADCs
fmc_reset_adcs_n_o : out std_logic;
--FMC Present status
fmc_prsnt_m2c_l_i : in std_logic;
-- General board status
fmc_mmcm_lock_o : out std_logic;
fmc_lmk_lock_o : out std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_fmc516;
architecture rtl of dbe_bpm_fmc516 is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 9;
-- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC,
--Etherbone, FMC516, Peripherals
-- Number of masters
constant c_masters : natural := 8; -- LM32 master, Data + Instruction,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- TICs counter period. 100MHz clock -> msec granularity
constant c_tics_cntr_period : natural := 100000;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_adc_ref_clk : natural := 1;
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- FMC516 layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter
constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400");
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"20000000"), -- 64KB RAM
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port
7 => f_sdb_embed_bridge(c_fmc516_bridge_sdb, x"30010000"), -- FMC516 control port
8 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000") -- General peripherals control port
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"30000000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- FMC516 Signals
signal wbs_fmc516_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc516_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc516_mmcm_lock_int : std_logic;
signal fmc516_lmk_lock_int : std_logic;
signal fmc516_fs_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_fs_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_adc_data : std_logic_vector(c_num_adc_channels*16-1 downto 0);
signal fmc516_adc_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_debug : std_logic;
signal reset_adc_counter : unsigned(6 downto 0) := (others => '0');
signal fmc516_fs_rst_n : std_logic;
-- FMC516 Debug
signal fmc516_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
signal sys_spi_clk_int : std_logic;
--signal sys_spi_data_int : std_logic;
signal sys_spi_dout_int : std_logic;
signal sys_spi_din_int : std_logic;
signal sys_spi_miosio_oe_n_int : std_logic;
signal sys_spi_cs_adc0_n_int : std_logic;
signal sys_spi_cs_adc1_n_int : std_logic;
signal sys_spi_cs_adc2_n_int : std_logic;
signal sys_spi_cs_adc3_n_int : std_logic;
signal lmk_lock_int : std_logic;
signal lmk_sync_int : std_logic;
signal lmk_uwire_latch_en_int : std_logic;
signal lmk_uwire_data_int : std_logic;
signal lmk_uwire_clock_int : std_logic;
signal fmc_reset_adcs_n_int : std_logic;
signal fmc_reset_adcs_n_out : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- Counter signal
--signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
--constant s_counter_full : integer := 100000000;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal CONTROL2 : std_logic_vector(35 downto 0);
signal CONTROL3 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
--signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
--signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
--signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
--signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(15 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(15 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(15 downto 0);
signal TRIG_ILA0_4 : std_logic_vector(15 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 2 signals
signal TRIG_ILA2_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 3 signals
signal TRIG_ILA3_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
--component chipscope_icon_2_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0)
--);
--end component;
component chipscope_icon_4_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
component chipscope_ila_131072
port (
control: inout std_logic_vector(35 downto 0);
clk: in std_logic;
trig0: in std_logic_vector(7 downto 0);
trig1: in std_logic_vector(15 downto 0);
trig2: in std_logic_vector(15 downto 0);
trig3: in std_logic_vector(15 downto 0);
trig4: in std_logic_vector(15 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => 1 -- CLK_SYS
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
cmp_lm32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug"
) -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(0), -- Data bus
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1), -- Instruction bus
iwb_i => cbar_slave_o(1)
);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
4 => irq_tx_done, others => '0');
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(4),
wb_master_out => cbar_slave_i(4),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
-- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
-- The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(5),
tx_ram_i => cbar_slave_o(5),
rx_ram_o => cbar_slave_i(6),
rx_ram_i => cbar_slave_o(6),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(7) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(7);
-- The FMC516 is slave 7
cmp_xwb_fmc516 : xwb_fmc516
generic map(
g_fpga_device => "VIRTEX6",
g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
g_address_granularity => BYTE,
g_adc_clk_period_values => default_adc_clk_period_values,
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from FMC516 (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from FMC516.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "0011",
g_use_data_chains => "1111",
g_map_clk_data_chains => (1,0,0,1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_adc_ref_clk,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(7),
wb_slv_o => cbar_master_i(7),
-----------------------------
-- External ports
-----------------------------
-- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM,
-- AD7417 temperature diodes and AD7417 supply rails
sys_i2c_scl_b => sys_i2c_scl_b,
sys_i2c_sda_b => sys_i2c_sda_b,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i => adc_clk0_p_i,
adc_clk0_n_i => adc_clk0_n_i,
adc_clk1_p_i => adc_clk1_p_i,
adc_clk1_n_i => adc_clk1_n_i,
adc_clk2_p_i => adc_clk2_p_i,
adc_clk2_n_i => adc_clk2_n_i,
adc_clk3_p_i => adc_clk3_p_i,
adc_clk3_n_i => adc_clk3_n_i,
-- DDR ADC data channels.
adc_data_ch0_p_i => adc_data_ch0_p_i,
adc_data_ch0_n_i => adc_data_ch0_n_i,
adc_data_ch1_p_i => adc_data_ch1_p_i,
adc_data_ch1_n_i => adc_data_ch1_n_i,
adc_data_ch2_p_i => adc_data_ch2_p_i,
adc_data_ch2_n_i => adc_data_ch2_n_i,
adc_data_ch3_p_i => adc_data_ch3_p_i,
adc_data_ch3_n_i => adc_data_ch3_n_i,
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o => adc_clk_div_rst_p_o,
adc_clk_div_rst_n_o => adc_clk_div_rst_n_o,
-- FMC Front leds. Typical uses: Over Range or Full Scale
-- condition.
fmc_leds_o => fmc_leds_o,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o => sys_spi_clk_int,
sys_spi_data_b => sys_spi_data_b,
--sys_spi_dout_o => sys_spi_dout_int,
--sys_spi_din_i => sys_spi_din_int,
sys_spi_cs_adc0_n_o => sys_spi_cs_adc0_n_int, -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o => sys_spi_cs_adc1_n_int, -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o => sys_spi_cs_adc2_n_int, -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o => sys_spi_cs_adc3_n_int, -- SPI ADC CS channel 3
--sys_spi_miosio_oe_n_o => sys_spi_miosio_oe_n_int,
-- External Trigger To/From FMC
m2c_trig_p_i => m2c_trig_p_i,
m2c_trig_n_i => m2c_trig_n_i,
c2m_trig_p_o => c2m_trig_p_o,
c2m_trig_n_o => c2m_trig_n_o,
-- LMK (National Semiconductor) is the clock and distribution IC.
-- uWire interface
lmk_lock_i => lmk_lock_int,--lmk_lock_i,
lmk_sync_o => lmk_sync_int,--lmk_sync_o,
lmk_uwire_latch_en_o => lmk_uwire_latch_en_int,--lmk_uwire_latch_en_o,
lmk_uwire_data_o => lmk_uwire_data_int,--lmk_uwire_data_o,
lmk_uwire_clock_o => lmk_uwire_clock_int,--lmk_uwire_clock_o,
-- Programable VCXO via I2C
vcxo_i2c_sda_b => vcxo_i2c_sda_b,
vcxo_i2c_scl_b => vcxo_i2c_scl_b,
vcxo_pd_l_o => vcxo_pd_l_o,
-- One-wire To/From DS2431 (VMETRO Data)
fmc_id_dq_b => fmc_id_dq_b,
-- One-wire To/From DS2432 SHA-1 (SP-Devices key)
fmc_key_dq_b => fmc_key_dq_b,
-- General board pins
fmc_pwr_good_i => fmc_pwr_good_i,
-- Internal/External clock distribution selection
fmc_clk_sel_o => fmc_clk_sel_o,
-- Reset ADCs
fmc_reset_adcs_n_o => fmc_reset_adcs_n_int,--fmc_reset_adcs_n_o,
--fmc_reset_adcs_n_o => open,--fmc_reset_adcs_n_o,
--FMC Present status
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_l_i,
-----------------------------
-- ADC output signals. Continuous flow.
-----------------------------
adc_clk_o => fmc516_fs_clk,
adc_clk2x_o => fmc516_fs_clk2x,
adc_data_o => fmc516_adc_data,
adc_data_valid_o => fmc516_adc_valid,
-----------------------------
-- General ADC output signals
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => '0',
-- General board status
fmc_mmcm_lock_o => fmc516_mmcm_lock_int,
fmc_lmk_lock_o => fmc516_lmk_lock_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc516_in_array,
wbs_source_o => wbs_fmc516_out_array,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc516_debug_valid_int,
fifo_debug_full_o => fmc516_debug_full_int,
fifo_debug_empty_o => fmc516_debug_empty_int
);
gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc516_in_array(i) <= cc_dummy_src_com_in;
end generate;
fmc_mmcm_lock_o <= fmc516_mmcm_lock_int;
fmc_lmk_lock_o <= fmc516_lmk_lock_int;
-- Tri-state buffer for SPI three-wire mode
--sys_spi_data_b <= sys_spi_dout_int when sys_spi_miosio_oe_n_int = '0' else 'Z';
--sys_spi_din_int <= sys_spi_data_b;
sys_spi_clk_o <= sys_spi_clk_int;
sys_spi_cs_adc0_n_o <= sys_spi_cs_adc0_n_int;
sys_spi_cs_adc1_n_o <= sys_spi_cs_adc1_n_int;
sys_spi_cs_adc2_n_o <= sys_spi_cs_adc2_n_int;
sys_spi_cs_adc3_n_o <= sys_spi_cs_adc3_n_int;
lmk_lock_int <= lmk_lock_i;
lmk_sync_o <= lmk_sync_int;
lmk_uwire_latch_en_o <= lmk_uwire_latch_en_int;
lmk_uwire_data_o <= lmk_uwire_data_int;
lmk_uwire_clock_o <= lmk_uwire_clock_int;
-- Reset FMC516 ADCs
fmc_reset_adcs_n_o <= fmc_reset_adcs_n_out;
--fmc516_fs_rst_n <= clk_sys_rstn and fmc516_mmcm_lock_int;
-- Do not use mmcm_lock as reset.
fmc516_fs_rst_n <= clk_sys_rstn;
p_fmc516_reset_adcs : process(fmc516_fs_clk(c_adc_ref_clk))
begin
if rising_edge(fmc516_fs_clk(c_adc_ref_clk)) then
if (fmc516_fs_rst_n = '0' or fmc_reset_adcs_n_int = '0') then
fmc_reset_adcs_n_out <= '1';
reset_adc_counter <= (others => '0');
elsif reset_adc_counter = "1111111" then
fmc_reset_adcs_n_out <= '1';
else
reset_adc_counter <= reset_adc_counter + 1;
fmc_reset_adcs_n_out <= '0';
end if;
end if;
end process;
--p_debug : process(sys_spi_clk_int)
--begin
-- if rising_edge(sys_spi_clk_int) then
-- if (clk_sys_rstn = '0') then
-- fmc_debug <= '0';
-- else
-- fmc_debug <= sys_spi_dout_int and
-- ((not sys_spi_cs_adc0_n_int) or
-- (not sys_spi_cs_adc1_n_int) or
-- (not sys_spi_cs_adc2_n_int) or
-- (not sys_spi_cs_adc3_n_int));
-- end if;
-- end if;
--end process;
-- The board peripherals components is slave 8
cmp_xwb_dbe_periph : xwb_dbe_periph
generic map(
-- NOT used!
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period => c_tics_cntr_period,
g_num_leds => c_leds_num_pins,
g_num_buttons => c_buttons_num_pins
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- UART
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- LEDs
led_out_o => gpio_leds_int,
led_in_i => gpio_leds_int,
led_oen_o => open,
-- Buttons
button_out_o => open,
button_in_i => buttons_i,
button_oen_o => open,
-- Wishbone
slave_i => cbar_master_o(8),
slave_o => cbar_master_i(8)
);
leds_o <= gpio_leds_int;
---- Slave 7 is the UART
--cmp_uart : xwb_simple_uart
--generic map (
-- g_interface_mode => PIPELINED,
-- g_address_granularity => BYTE
--)
--port map (
-- clk_sys_i => clk_sys,
-- rst_n_i => clk_sys_rstn,
-- slave_i => cbar_master_o(7),
-- slave_o => cbar_master_i(7),
-- uart_rxd_i => uart_rxd_i,
-- uart_txd_o => uart_txd_o
--);
--
---- Slave 8 is the LED driver
--cmp_leds : xwb_gpio_port
--generic map(
-- g_interface_mode => CLASSIC,
-- g_address_granularity => BYTE,
-- g_num_pins => c_leds_num_pins,
-- g_with_builtin_tristates => false
--)
--port map(
-- clk_sys_i => clk_sys,
-- rst_n_i => clk_sys_rstn,
--
-- -- Wishbone
-- slave_i => cbar_master_o(8),
-- slave_o => cbar_master_i(8),
-- desc_o => open, -- Not implemented
--
-- --gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
--
-- gpio_out_o => gpio_leds_int,
-- gpio_in_i => gpio_leds_int,
-- gpio_oen_o => open
--);
--
--leds_o <= gpio_leds_int;
--
---- Slave 9 is the Button driver
--cmp_buttons : xwb_gpio_port
--generic map(
-- g_interface_mode => CLASSIC,
-- g_address_granularity => BYTE,
-- g_num_pins => c_buttons_num_pins,
-- g_with_builtin_tristates => false
--)
--port map(
-- clk_sys_i => clk_sys,
-- rst_n_i => clk_sys_rstn,
--
-- -- Wishbone
-- slave_i => cbar_master_o(9),
-- slave_o => cbar_master_i(9),
-- desc_o => open, -- Not implemented
--
-- --gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
--
-- gpio_out_o => open,
-- gpio_in_i => buttons_i,
-- gpio_oen_o => open
--);
---- Xilinx Chipscope
cmp_chipscope_icon_0 : chipscope_icon_4_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1,
CONTROL2 => CONTROL2,
CONTROL3 => CONTROL3
);
--cmp_chipscope_ila_0_fmc516_clk0 : chipscope_ila
--port map (
-- CONTROL => CONTROL0,
-- --CLK => clk_sys,
-- CLK => fmc516_fs_clk(c_adc_ref_clk),
-- --CLK => fmc516_fs_clk(1),
-- TRIG0 => TRIG_ILA0_0,
-- TRIG1 => TRIG_ILA0_1,
-- TRIG2 => TRIG_ILA0_2,
-- TRIG3 => TRIG_ILA0_3
--);
cmp_chipscope_ila_131072_0_adc : chipscope_ila_131072
port map (
CONTROL => CONTROL0,
CLK => fmc516_fs_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3,
TRIG4 => TRIG_ILA0_4
);
TRIG_ILA0_0(0) <= '0';
TRIG_ILA0_0(1) <= '0';
TRIG_ILA0_0(2) <= '0';
TRIG_ILA0_0(3) <= '0';
TRIG_ILA0_0(4) <= '0';
TRIG_ILA0_0(5) <= '0';
TRIG_ILA0_0(6) <= '0';
TRIG_ILA0_0(7) <= '0';
-- ADC Data
TRIG_ILA0_1 <= fmc516_adc_data(15 downto 0);
TRIG_ILA0_2 <= fmc516_adc_data(31 downto 16);
TRIG_ILA0_3 <= fmc516_adc_data(47 downto 32);
TRIG_ILA0_4 <= fmc516_adc_data(63 downto 48);
---- FMC516 WBS master output data
----TRIG_ILA0_0 <= wbs_fmc516_out_array(3).dat &
---- wbs_fmc516_out_array(2).dat;
--
--TRIG_ILA0_0 <= fmc516_adc_data(31 downto 16) &
-- fmc516_adc_data(15 downto 0);
--TRIG_ILA0_1 <= fmc516_adc_data(63 downto 48) &
-- fmc516_adc_data(47 downto 32);
--
---- FMC516 WBS master output data
----TRIG_ILA0_1 <= wbs_fmc516_out_array(1).dat &
---- wbs_fmc516_out_array(0).dat;
----TRIG_ILA0_1 <= fmc516_adc_data(15 downto 0) &
---- fmc516_adc_data(47 downto 32);
----TRIG_ILA0_1(11 downto 0) <= adc_dly_debug_int(1).clk_chain.idelay.pulse &
---- adc_dly_debug_int(1).data_chain.idelay.pulse &
---- adc_dly_debug_int(1).clk_chain.idelay.val &
---- adc_dly_debug_int(1).data_chain.idelay.val;
----TRIG_ILA0_1(31 downto 12) <= (others => '0');
--
---- FMC516 WBS master output control signals
--TRIG_ILA0_2(17 downto 0) <= wbs_fmc516_out_array(1).cyc &
-- wbs_fmc516_out_array(1).stb &
-- wbs_fmc516_out_array(1).adr &
-- wbs_fmc516_out_array(1).sel &
-- wbs_fmc516_out_array(1).we &
-- wbs_fmc516_out_array(2).cyc &
-- wbs_fmc516_out_array(2).stb &
-- wbs_fmc516_out_array(2).adr &
-- wbs_fmc516_out_array(2).sel &
-- wbs_fmc516_out_array(2).we;
--TRIG_ILA0_2(18) <= fmc_reset_adcs_n_out;
--TRIG_ILA0_2(22 downto 19) <= fmc516_adc_valid;
--TRIG_ILA0_2(23) <= fmc516_mmcm_lock_int;
--TRIG_ILA0_2(24) <= fmc516_lmk_lock_int;
--TRIG_ILA0_2(25) <= fmc516_debug_valid_int(1);
--TRIG_ILA0_2(26) <= fmc516_debug_full_int(1);
--TRIG_ILA0_2(27) <= fmc516_debug_empty_int(1);
--TRIG_ILA0_2(31 downto 28) <= (others => '0');
--
---- FMC516 WBS master output control signals
----TRIG_ILA0_3(17 downto 0) <= wbs_fmc516_out_array(1).cyc &
---- wbs_fmc516_out_array(1).stb &
---- wbs_fmc516_out_array(1).adr &
---- wbs_fmc516_out_array(1).sel &
---- wbs_fmc516_out_array(1).we &
---- wbs_fmc516_out_array(0).cyc &
---- wbs_fmc516_out_array(0).stb &
---- wbs_fmc516_out_array(0).adr &
---- wbs_fmc516_out_array(0).sel &
---- wbs_fmc516_out_array(0).we;
----TRIG_ILA0_3(18) <= fmc_reset_adcs_n_out;
----TRIG_ILA0_3(22 downto 19) <= fmc516_adc_valid;
----TRIG_ILA0_3(23) <= fmc516_mmcm_lock_int;
----TRIG_ILA0_3(24) <= fmc516_lmk_lock_int;
----TRIG_ILA0_3(25) <= fmc516_debug_valid_int(1);
----TRIG_ILA0_3(26) <= fmc516_debug_full_int(1);
----TRIG_ILA0_3(27) <= fmc516_debug_empty_int(1);
----TRIG_ILA0_3(31 downto 28) <= (others => '0');
--TRIG_ILA0_3 <= (others => '0');
--
---- Etherbone debuging signals
----cmp_chipscope_ila_1_etherbone : chipscope_ila
----port map (
---- CONTROL => CONTROL1,
---- CLK => clk_sys,
---- TRIG0 => TRIG_ILA1_0,
---- TRIG1 => TRIG_ILA1_1,
---- TRIG2 => TRIG_ILA1_2,
---- TRIG3 => TRIG_ILA1_3
----);
--
----TRIG_ILA1_0 <= wb_ebone_out.dat;
----TRIG_ILA1_1 <= wb_ebone_in.dat;
----TRIG_ILA1_2 <= wb_ebone_out.adr;
----TRIG_ILA1_3(6 downto 0) <= wb_ebone_out.cyc &
---- wb_ebone_out.stb &
---- wb_ebone_out.sel &
---- wb_ebone_out.we;
----TRIG_ILA1_3(11 downto 7) <= wb_ebone_in.ack &
---- wb_ebone_in.err &
---- wb_ebone_in.rty &
---- wb_ebone_in.stall &
---- wb_ebone_in.int;
----TRIG_ILA1_3(31 downto 12) <= (others => '0');
--
----cmp_chipscope_ila_1_ethmac_rx : chipscope_ila
----port map (
---- CONTROL => CONTROL1,
---- CLK => mrx_clk_pad_i,
---- TRIG0 => TRIG_ILA1_0,
---- TRIG1 => TRIG_ILA1_1,
---- TRIG2 => TRIG_ILA1_2,
---- TRIG3 => TRIG_ILA1_3
----);
----
----TRIG_ILA1_0(7 downto 0) <= mrxd_pad_i &
---- mrxdv_pad_i &
---- mrxerr_pad_i &
---- mcoll_pad_i &
---- mcrs_pad_i;
----
----TRIG_ILA1_0(31 downto 8) <= (others => '0');
----TRIG_ILA1_1 <= (others => '0');
----TRIG_ILA1_2 <= (others => '0');
----TRIG_ILA1_3 <= (others => '0');
cmp_chipscope_ila_1_fmc516_clk1 : chipscope_ila
port map (
CONTROL => CONTROL1,
--CLK => fmc516_fs_clk(1),
CLK => fmc516_fs_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3
);
-- FMC516 WBS master output data
TRIG_ILA1_0 <= fmc516_adc_data(15 downto 0) &
fmc516_adc_data(63 downto 48);
-- FMC516 WBS master output data
TRIG_ILA1_1 <= (others => '0');
-- FMC516 WBS master output control signals
TRIG_ILA1_2(17 downto 0) <= wbs_fmc516_out_array(0).cyc &
wbs_fmc516_out_array(0).stb &
wbs_fmc516_out_array(0).adr &
wbs_fmc516_out_array(0).sel &
wbs_fmc516_out_array(0).we &
wbs_fmc516_out_array(3).cyc &
wbs_fmc516_out_array(3).stb &
wbs_fmc516_out_array(3).adr &
wbs_fmc516_out_array(3).sel &
wbs_fmc516_out_array(3).we;
TRIG_ILA1_2(18) <= fmc_reset_adcs_n_out;
TRIG_ILA1_2(22 downto 19) <= fmc516_adc_valid;
TRIG_ILA1_2(23) <= fmc516_mmcm_lock_int;
TRIG_ILA1_2(24) <= fmc516_lmk_lock_int;
TRIG_ILA1_2(25) <= fmc516_debug_valid_int(0);
TRIG_ILA1_2(26) <= fmc516_debug_full_int(0);
TRIG_ILA1_2(27) <= fmc516_debug_empty_int(0);
TRIG_ILA1_2(31 downto 28) <= (others => '0');
TRIG_ILA1_3 <= (others => '0');
cmp_chipscope_ila_2_ethmac_tx : chipscope_ila
port map (
CONTROL => CONTROL2,
CLK => mtx_clk_pad_i,
TRIG0 => TRIG_ILA2_0,
TRIG1 => TRIG_ILA2_1,
TRIG2 => TRIG_ILA2_2,
TRIG3 => TRIG_ILA2_3
);
TRIG_ILA2_0(5 downto 0) <= mtxd_pad_int &
mtxen_pad_int &
mtxerr_pad_int;
TRIG_ILA2_0(31 downto 6) <= (others => '0');
TRIG_ILA2_1 <= (others => '0');
TRIG_ILA2_2 <= (others => '0');
TRIG_ILA2_3 <= (others => '0');
--cmp_chipscope_ila_3_ethmac_miim : chipscope_ila
--port map (
-- CONTROL => CONTROL3,
-- CLK => clk_sys,
-- TRIG0 => TRIG_ILA3_0,
-- TRIG1 => TRIG_ILA3_1,
-- TRIG2 => TRIG_ILA3_2,
-- TRIG3 => TRIG_ILA3_3
--);
--
--TRIG_ILA3_0(4 downto 0) <= mdc_pad_int &
-- ethmac_md_in &
-- ethmac_md_out &
-- ethmac_md_oe &
-- ethmac_int;
--
--TRIG_ILA3_0(31 downto 6) <= (others => '0');
--TRIG_ILA3_1 <= (others => '0');
--TRIG_ILA3_2 <= (others => '0');
--TRIG_ILA3_3 <= (others => '0');
-- The clocks to/from peripherals are derived from the bus clock.
-- Therefore we don't have to worry about synchronization here, just
-- keep in mind that the data/ss lines will appear longer than normal
cmp_chipscope_ila_3_fmc516_periph : chipscope_ila
port map (
CONTROL => CONTROL3,
CLK => clk_sys,
TRIG0 => TRIG_ILA3_0,
TRIG1 => TRIG_ILA3_1,
TRIG2 => TRIG_ILA3_2,
TRIG3 => TRIG_ILA3_3
);
TRIG_ILA3_0(7 downto 0) <= sys_spi_clk_int &
--sys_spi_data_int &
sys_spi_din_int &
sys_spi_dout_int &
sys_spi_miosio_oe_n_int &
sys_spi_cs_adc0_n_int & -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_int & -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_int & -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_int; -- SPI ADC CS channel 3
TRIG_ILA3_0(31 downto 8) <= (others => '0');
TRIG_ILA3_1(4 downto 0) <= lmk_lock_int &
lmk_sync_int &
lmk_uwire_latch_en_int &
lmk_uwire_data_int &
lmk_uwire_clock_int;
TRIG_ILA3_1(31 downto 5) <= (others => '0');
TRIG_ILA3_2 <= (others => '0');
TRIG_ILA3_3 <= (others => '0');
end rtl;
|
lgpl-3.0
|
73f7ba8e5410d56dfcdab84ef1b65ace
| 0.407159 | 4.032144 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/uart/uart.vhd
| 1 | 11,245 |
-- Top level entity of UART peripheral.
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address of UART
);
port(
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
clk_uart: in std_logic;
rx: in std_logic;
tx: out std_logic;
intrq: out std_logic
);
end entity uart;
architecture uart_arch of uart is
component flag is
port(
clk: in std_logic;
res: in std_logic;
set: in std_logic;
clear: in std_logic;
q: out std_logic
);
end component flag;
component uart_core is
port(
clk_sys: in std_logic; --system clock
clk_uart: in std_logic; --uart clock (14,4?)
res: in std_logic; --reset
tx: out std_logic; --tx TLE pin
rx: in std_logic; --rx TLE pin
rx_data_output: out unsigned(7 downto 0); --rx data read from fifo
rx_data_count: out unsigned(5 downto 0); --byte count in fifo
rx_data_rdreq: in std_logic; --request read from rx fifo
tx_data_input: in unsigned(7 downto 0); --tx data write into fifo
tx_data_count: out unsigned(5 downto 0); --byte count in tx fifo
tx_data_wrreq: in std_logic; --request write into tx fifo
n: in unsigned(15 downto 0); --control signals
txen: in std_logic;
rxen: in std_logic;
tx_done: out std_logic; --byte sended
rx_done: out std_logic --byte recieved
);
end component uart_core;
signal reg_sel: std_logic_vector(3 downto 0);
signal rx_data_output: unsigned(7 downto 0);
signal rx_data_count: unsigned(5 downto 0);
signal rx_data_rdreq: std_logic;
signal tx_data_input: unsigned(7 downto 0);
signal tx_data_count: unsigned(5 downto 0);
signal tx_data_wrreq: std_logic;
signal n: unsigned(15 downto 0);
signal txen: std_logic;
signal rxen: std_logic;
signal tx_done: std_logic;
signal rx_done: std_logic;
signal control_reg: std_logic_vector(24 downto 0);
signal tx_intrq, tx_halfbuff_intrq, tx_emptybuff_intrq: std_logic;
signal rx_intrq, rx_halfbuff_intrq, rx_fullbuff_intrq: std_logic;
signal tx_int_flag, tx_int_buffhalf_flag, tx_int_buffempty_flag: std_logic;
signal rx_int_flag, rx_int_buffhalf_flag, rx_int_bufffull_flag: std_logic;
signal tx_buff_empty, tx_buff_half, rx_buff_full, rx_buff_half: std_logic;
signal status_reg: std_logic_vector(17 downto 0);
signal flagread: std_logic;
type fsm_state_type is (idle, write0, write1, write2, read0, read1, read2);
signal fsm_state: fsm_state_type;
begin
--chip select
process(address) is begin
if (unsigned(address) = BASE_ADDRESS)then
reg_sel <= "0001"; --TX reg
elsif (unsigned(address) = (BASE_ADDRESS + 1)) then
reg_sel <= "0010"; --RX reg
elsif (unsigned(address) = (BASE_ADDRESS + 2)) then
reg_sel <= "0100"; --status reg
elsif (unsigned(address) = (BASE_ADDRESS + 3)) then
reg_sel <= "1000"; --control reg
else
reg_sel <= "0000";
end if;
end process;
uart_core0: uart_core
port map(clk, clk_uart, res, tx, rx, rx_data_output, rx_data_count, rx_data_rdreq,
tx_data_input, tx_data_count, tx_data_wrreq, unsigned(control_reg(15 downto 0)),
control_reg(17), control_reg(16), tx_done, rx_done);
intrq <= control_reg(18) and (tx_intrq or tx_halfbuff_intrq or tx_emptybuff_intrq
or rx_intrq or rx_halfbuff_intrq or rx_fullbuff_intrq);
tx_intrq <= control_reg(24) and tx_done and not(tx_int_flag);
tx_halfbuff_intrq <= control_reg(23) and tx_buff_half and not(tx_int_buffhalf_flag);
tx_emptybuff_intrq <= control_reg(22) and tx_buff_empty and not(tx_int_buffempty_flag);
rx_intrq <= control_reg(21) and rx_done and not(rx_int_flag);
rx_halfbuff_intrq <= control_reg(20) and rx_buff_half and not(rx_int_buffhalf_flag);
rx_fullbuff_intrq <= control_reg(19) and rx_buff_full and not(rx_int_bufffull_flag);
process(tx_data_count) is
begin
if tx_data_count = "000000" then
tx_buff_empty <= '1';
else
tx_buff_empty <= '0';
end if;
end process;
process(tx_data_count) is
begin
if tx_data_count = "010000" then
tx_buff_half <= '1';
else
tx_buff_half <= '0';
end if;
end process;
process(rx_data_count) is
begin
if rx_data_count = "100000" then
rx_buff_full <= '1';
else
rx_buff_full <= '0';
end if;
end process;
process(rx_data_count) is
begin
if rx_data_count = "010000" then
rx_buff_half <= '1';
else
rx_buff_half <= '0';
end if;
end process;
flag_tx_int: flag
port map(clk, res, tx_intrq, flagread, tx_int_flag);
flag_tx_buffhalf_int: flag
port map(clk, res, tx_halfbuff_intrq, flagread, tx_int_buffhalf_flag);
flag_tx_bufffull_int: flag
port map(clk, res, tx_emptybuff_intrq, flagread, tx_int_buffempty_flag);
flag_rx_int: flag
port map(clk, res, rx_intrq, flagread, rx_int_flag);
flag_rx_buffhalf_int: flag
port map(clk, res, rx_halfbuff_intrq, flagread, rx_int_buffhalf_flag);
flag_rx_bufffull_int: flag
port map(clk, res, rx_fullbuff_intrq, flagread, rx_int_bufffull_flag);
process(clk) is
variable control_reg_v: std_logic_vector(24 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
control_reg_v := (others => '0');
elsif ((WR = '1') and (reg_sel = "1000")) then
control_reg_v := data_mosi(24 downto 0);
end if;
end if;
control_reg <= control_reg_v;
end process;
status_reg(5 downto 0) <= std_logic_vector(rx_data_count);
status_reg(11 downto 6) <= std_logic_vector(tx_data_count);
status_reg(12) <= rx_int_bufffull_flag;
status_reg(13) <= rx_int_buffhalf_flag;
status_reg(14) <= rx_int_flag;
status_reg(15) <= tx_int_buffempty_flag;
status_reg(16) <= tx_int_buffhalf_flag;
status_reg(17) <= tx_int_flag;
process(RD, reg_sel) is
begin
if((RD = '1') and (reg_sel = "0100")) then
flagread <= '1';
else
flagread <= '0';
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
if res = '1' then
fsm_state <= idle;
else
case fsm_state is
when idle =>
if ((RD = '1') and (reg_sel /= "0000")) then
case reg_sel is
when "0010" => fsm_state <= read1;
when others => fsm_state <= read0;
end case;
elsif ((WR = '1') and (reg_sel /= "0000")) then
case reg_sel is
when "0001" => fsm_state <= write1;
when others => fsm_state <= write0;
end case;
else
fsm_state <= idle;
end if;
when write0 => fsm_state <= idle;
when write1 => fsm_state <= write2;
when write2 => fsm_state <= idle;
when read0 => fsm_state <= idle;
when read1 => fsm_state <= read2;
when read2 => fsm_state <= idle;
end case;
end if;
end if;
end process;
process(fsm_state, reg_sel, rx_data_output, status_reg, control_reg) is
begin
case fsm_state is
when idle=>
data_miso <= (others => 'Z');
ack <= '0';
tx_data_wrreq <= '0';
rx_data_rdreq <= '0';
when write0=>
data_miso <= (others => 'Z');
ack <= '1';
tx_data_wrreq <= '0';
rx_data_rdreq <= '0';
when write1=>
data_miso <= (others => 'Z');
ack <= '0';
tx_data_wrreq <= '1';
rx_data_rdreq <= '0';
when write2=>
data_miso <= (others => 'Z');
ack <= '1';
tx_data_wrreq <= '0';
rx_data_rdreq <= '0';
when read0=>
case reg_sel is
when "0001" => data_miso <= (others => 'Z');
when "0100" => data_miso <= x"00" & "000000" & status_reg;
when "1000" => data_miso <= "0000000" & control_reg;
when others => data_miso <= (others => 'Z');
end case;
ack <= '1';
tx_data_wrreq <= '0';
rx_data_rdreq <= '0';
when read1=>
data_miso <= x"000000" & std_logic_vector(rx_data_output);
ack <= '0';
tx_data_wrreq <= '0';
rx_data_rdreq <= '1';
when read2=>
data_miso <= x"000000" & std_logic_vector(rx_data_output);
ack <= '1';
tx_data_wrreq <= '0';
rx_data_rdreq <= '0';
end case;
end process;
tx_data_input <= unsigned(data_mosi(7 downto 0));
end architecture uart_arch;
library ieee;
use ieee.std_logic_1164.all;
entity flag is
port(
clk: in std_logic;
res: in std_logic;
set: in std_logic;
clear: in std_logic;
q: out std_logic
);
end entity flag;
architecture flag_arch of flag is
begin
process(clk) is
variable flag_v: std_logic;
begin
if rising_edge(clk) then
if ((res = '1') or (clear = '1')) then
flag_v := '0';
elsif set = '1' then
flag_v := '1';
end if;
end if;
q <= flag_v;
end process;
end architecture flag_arch;
|
mit
|
dc34a6e360a9e41599bd613aee5a5079
| 0.494486 | 3.761793 | false | false | false | false |
nanomolina/MIPS
|
prueba/datapath_illak.vhd
| 1 | 12,226 |
library ieee;
use ieee.std_logic_1164.all;
entity datapath is
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
AluSrc : in std_logic;
RegDst : in std_logic;
RegWrite : in std_logic;
Jump : in std_logic;
AluControl : in std_logic_vector(2 downto 0);
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic);
end entity;
architecture arq_datapath of datapath is
component fetch
port(
jumpM, PcSrcM, clk, reset: in std_logic;
PcBranchM: in std_logic_vector(31 downto 0);
InstrF, PCF, PCPlus4F: out std_logic_vector(31 downto 0));
end component;
component decode
port(
A3: in std_logic_vector(4 downto 0);
InstrD, Wd3: in std_logic_vector(31 downto 0);
RegWrite, clk: in std_logic;
RtD, RdD: out std_logic_vector(4 downto 0);
SignImmD, RD1D, RD2D: out std_logic_vector(31 downto 0));
end component;
component execute
port(
RD1E, RD2E, PCPlus4E, SignImmE: in std_logic_vector(31 downto 0);
RtE, RdE: in std_logic_vector(4 downto 0);
RegDst, AluSrc : in std_logic;
AluControl: in std_logic_vector(2 downto 0);
WriteRegE: out std_logic_vector(4 downto 0);
ZeroE: out std_logic;
AluOutE, WriteDataE, PCBranchE: out std_logic_vector(31 downto 0));
end component;
component memory
port(
AluOutM, WriteDataM: in std_logic_vector(31 downto 0);
ZeroM, MemWrite, Branch, clk, dump: in std_logic;
ReadDataM: out std_logic_vector(31 downto 0);
PCSrcM: out std_logic);
end component;
component writeback
port(
AluOutW, ReadDataW: in std_logic_vector(31 downto 0);
MemToReg: in std_logic;
ResultW: out std_logic_vector(31 downto 0));
end component;
--CLOCKS
component IF_ID
port(
clk : in std_logic;
instr_in : in std_logic_vector(31 downto 0);
pcplus4_in : in std_logic_vector(31 downto 0);
instr_out : out std_logic_vector(31 downto 0);
pcplus4_out : out std_logic_vector(31 downto 0)
);
end component;
component ID_EX
port(
RtD_in : in std_logic_vector(4 downto 0);
RdD_in : in std_logic_vector(4 downto 0);
SignImm_in : in std_logic_vector(31 downto 0);
RD1_in : in std_logic_vector(31 downto 0);
RD2_in : in std_logic_vector(31 downto 0);
PCPlus4_in : in std_logic_vector(31 downto 0);
MemToReg_in: in std_logic;
MemWrite_in: in std_logic;
Branch_in: in std_logic;
AluSrc_in: in std_logic;
RegDst_in: in std_logic;
RegWrite_in: in std_logic;
Jump_in: in std_logic;
alucontrol_in: in std_logic_vector (2 downto 0);
clk : in std_logic;
PCPlus4_out : out std_logic_vector(31 downto 0);
MemToReg_out: out std_logic;
MemWrite_out: out std_logic;
Branch_out: out std_logic;
AluSrc_out: out std_logic;
RegDst_out: out std_logic;
RegWrite_out: out std_logic;
Jump_out: out std_logic;
alucontrol_out: out std_logic_vector (2 downto 0);
RtD_out : out std_logic_vector(4 downto 0);
RdD_out : out std_logic_vector(4 downto 0);
SignImm_out : out std_logic_vector(31 downto 0);
RD1_out : out std_logic_vector(31 downto 0);
RD2_out : out std_logic_vector(31 downto 0)
);
end component;
component EX_MEM
port(
Zero_in : in std_logic;
AluOut_in : in std_logic_vector(31 downto 0);
WriteData_in : in std_logic_vector(31 downto 0);
WriteReg_in : in std_logic_vector(4 downto 0);
PCBranch_in : in std_logic_vector(31 downto 0);
RegWrite_in: in std_logic;
MemToReg_in: in std_logic;
MemWrite_in: in std_logic;
Jump_in: in std_logic;
Branch_in: in std_logic;
clk : in std_logic;
RegWrite_out: out std_logic;
MemToReg_out: out std_logic;
MemWrite_out: out std_logic;
Jump_out: out std_logic;
Branch_out: out std_logic;
Zero_out : out std_logic;
AluOut_out : out std_logic_vector(31 downto 0);
WriteData_out : out std_logic_vector(31 downto 0);
WriteReg_out : out std_logic_vector(4 downto 0);
PCBranch_out : out std_logic_vector(31 downto 0)
);
end component;
component MEM_WB
port(
AluOut_in : in std_logic_vector(31 downto 0);
ReadData_in : in std_logic_vector(31 downto 0);
WriteReg_in : in std_logic_vector(4 downto 0);
RegWrite_in: in std_logic;
MemToReg_in: in std_logic;
clk : in std_logic;
RegWrite_out: out std_logic;
MemToReg_out: out std_logic;
AluOut_out : out std_logic_vector(31 downto 0);
ReadData_out : out std_logic_vector(31 downto 0);
WriteReg_out : out std_logic_vector(4 downto 0)
);
end component;
--FIN CLOCKS
--signal CLOCKS
signal InstrC_s, PCPlus4C_s, RD1DC_s, RD2DC_s, SignImmC_s, AluOutC_s,
WriteDataC_s, PCBranchC_s, AluOut2C_s, ReadDataC_s, PCPlus4F_s, PCPlus4D_s : std_logic_vector(31 downto 0);
signal RtDC_s, RdDC_s, WriteRegC_s, WriteReg2C_s , WriteRegM_s: std_logic_vector(4 downto 0);
signal ZeroC_s, RegWriteE_s, MemToRegE_s, MemWriteE_s, JumpE_s, BranchE_s,
RegWriteM_s, MemToRegM_s, BranchM_s, MemWriteM_s, AluSrcE_s, RegDstE_s,
JumpM_s, RegWriteW_s, MemToRegW_s , WriteRegW_s : std_logic;
signal AluControlE_s : std_logic_vector(2 downto 0);
signal PcBranchM_s, InstrF_s, PCF_s,
InstrD_s,RD2E_s, RD1E_s, SignImmE_s,
AluOutM_s, WriteDataM_s, ReadDataW_s,
ResultW_s : std_logic_vector(31 downto 0);
signal ZeroM_s, PcSrcM_s : std_logic;
signal A3_s, RtE_s, RdE_s : std_logic_vector(4 downto 0);
begin
Fetch1: fetch port map(
jumpM => JumpM_s,
PcSrcM => PCSrcM_s, --changing
clk => clk,
reset => reset,
PcBranchM => PCBranchC_s,
InstrF => InstrD_s, --changing
PCF => pc,
PCPlus4F => PCPlus4F_s --changing
);
IF_ID1: IF_ID port map(
clk => clk,
instr_in => InstrD_s,
pcplus4_in => PCPlus4F_s,
instr_out => InstrC_s,--senial de salida
pcplus4_out => PCPlus4D_s --senial de salida
);
Decode1: decode port map(
A3 => A3_s, --changing
InstrD => InstrC_s, --changing
Wd3 => ResultW_s,
RegWrite => RegWriteW_s,
clk => clk,
RtD => RtE_s,
RdD => RdE_s,
SignImmD => SignImmE_s,
RD1D => RD1E_s,
RD2D => RD2E_s
);
ID_EX1: ID_EX port map(
RtD_in => RtE_s,
RdD_in => RdE_s,
SignImm_in => SignImmE_s,
RD1_in => RD1E_s,
RD2_in => RD2E_s,
PCPlus4_in => PCPlus4D_s,
MemToReg_in => MemToReg, --REVISAR! de aca hasta clk
MemWrite_in => MemWrite,
Branch_in => Branch,
AluSrc_in => AluSrc,
RegDst_in => RegDst,
RegWrite_in => RegWrite,
Jump_in => Jump,
alucontrol_in => AluControl,
clk => clk,
MemToReg_out => MemToRegE_s,
MemWrite_out => MemWriteE_s,
Branch_out => BranchE_s,
AluSrc_out => AluSrcE_s,
RegDst_out => RegDstE_s,
RegWrite_out => RegWriteE_s,
Jump_out => JumpE_s,
alucontrol_out => AluControlE_s,
RtD_out => RtDC_s,
RdD_out => RdDC_s,
SignImm_out => SignImmC_s,
RD1_out => RD1DC_s,
RD2_out => RD2DC_s,
PCPlus4_out => PCPlus4C_s
);
Execute1: execute port map(
RD1E => RD1DC_s, --changing
RD2E => RD2DC_s,
PCPlus4E => PCPlus4C_s,
SignImmE => SignImmC_s, --changing
RtE => RtDC_s, --changing
RdE => RdDC_s,
RegDst => RegDstE_s,
AluSrc => AluSrcE_s,
AluControl => AluControlE_s,
WriteRegE => WriteRegM_s,
ZeroE => ZeroM_s,
AluOutE => AluOutM_s,
WriteDataE => WriteDataM_s,
PCBranchE => PCBranchM_s
);
EX_MEM1: EX_MEM port map(
Zero_in => ZeroM_s,
AluOut_in => AluOutM_s,
WriteData_in => WriteDataM_s,
WriteReg_in => WriteRegM_s,
PCBranch_in => PCBranchM_s,
RegWrite_in => RegWriteE_s,
MemToReg_in => MemToRegE_s,
MemWrite_in => MemWriteE_s,
Jump_in => JumpE_s,
Branch_in => BranchE_s,
clk => clk,
RegWrite_out => RegWriteM_s,
MemToReg_out => MemToRegM_s,
MemWrite_out => MemWriteM_s,
Jump_out => JumpM_s,
Branch_out => BranchM_s,
Zero_out => ZeroC_s,
AluOut_out => AluOutC_s,
WriteData_out => WriteDataC_s,
WriteReg_out => WriteRegC_s,
PCBranch_out => PCBranchC_s
);
Memory1: memory port map(
AluOutM => AluOutC_s, --changing
WriteDataM => WriteDataC_s, --changing
ZeroM => ZeroC_s, --changing
MemWrite => MemWriteM_s,
Branch => BranchM_s, --PREGUNTAR
clk => clk,
dump => dump,
ReadDataM => ReadDataW_s,
PCSrcM => PCSrcM_s --Posee el mismo nombre (posible conflicto futuro) illak:Para nada!
);
MEM_WB1: MEM_WB port map(
AluOut_in => AluOut2C_s,
ReadData_in => ReadDataW_s,
WriteReg_in => WriteRegC_s,
RegWrite_in => RegWriteM_s,
MemToReg_in => MemToRegM_s,
clk => clk,
RegWrite_out => RegWriteW_s,
MemToReg_out => MemToRegW_s,
AluOut_out => AluOut2C_s,
ReadData_out => ReadDataC_s,
WriteReg_out => A3_s
);
WriteBack1: writeback port map(
AluOutW => AluOut2C_s, --changing
ReadDataW => ReadDataC_s, --changing
MemToReg => MemToRegW_s,
ResultW => ResultW_s --changing
);
instr <= instrD_s;
end arq_datapath;
|
gpl-3.0
|
373923a19f5c6f76253373e6781aa9d6
| 0.472845 | 4.065846 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/db/Gray_Binarization.vhd
| 1 | 3,014 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
--altera translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Gray_Binarization is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0) := (others=>'0');
Avalon_MM_Slave_write : in std_logic := '0';
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0) := (others=>'0');
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0) := (others=>'0');
Avalon_ST_Sink_endofpacket : in std_logic := '0';
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic := '0';
Avalon_ST_Sink_valid : in std_logic := '0';
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic := '0';
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic := '0';
aclr : in std_logic := '0'
);
end entity Gray_Binarization;
architecture rtl of Gray_Binarization is
component Gray_Binarization_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0) := (others=>'0');
Avalon_MM_Slave_write : in std_logic := '0';
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0) := (others=>'0');
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0) := (others=>'0');
Avalon_ST_Sink_endofpacket : in std_logic := '0';
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic := '0';
Avalon_ST_Sink_valid : in std_logic := '0';
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic := '0';
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic := '0';
aclr : in std_logic := '0'
);
end component Gray_Binarization_GN;
begin
Gray_Binarization_GN_0: if true generate
inst_Gray_Binarization_GN_0: Gray_Binarization_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
--altera translate_on
|
mit
|
a3c1a7106edaf8c47c3f0366cbc6fc8a
| 0.710683 | 3.069246 | false | false | false | false |
Godoakos/conway-vhdl
|
DualPortBRAM.vhd
| 1 | 1,795 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:49:30 01/16/2015
-- Design Name:
-- Module Name: DualPortBRAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use ieee.std_logic_unsigned.all;
entity DualPortBRAM is
port (CLK : in std_logic;
WE : in std_logic;
EN : in std_logic;
ADDRW : in std_logic_vector(7 downto 0);
ADDRR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(0 downto 0);
DO : out std_logic_vector(0 downto 0));
end DualPortBRAM;
architecture Behavioral of DualPortBRAM is
constant ADDR_WIDTH : integer := 8;
constant DATA_WIDTH : integer := 1;
type DPBRAM is array (2**ADDR_WIDTH-1 downto 0) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal BRAM: DPBRAM;
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
if (EN = '1') then
if (WE = '1') then
BRAM(conv_integer(ADDRW)) <= DI;
end if;
--<ram_outputA> <= <ram_name>(conv_integer(<addressA>));
DO <= BRAM(conv_integer(ADDRR));
end if;
end if;
end process;
end Behavioral;
|
mit
|
c469add9dfb1dfbe71bc40ce364c28e9
| 0.564345 | 3.701031 | false | false | false | false |
nanomolina/MIPS
|
DATAPATH/regfile.vhd
| 1 | 1,136 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity regfile is
port (
--revisar las imputs son 5 BITS para MIPS??
ra1, ra2, wa3: in std_logic_vector(4 downto 0);
wd3: in std_logic_vector(31 downto 0);
we3, clk: in std_logic;
rd1, rd2: out std_logic_vector(31 downto 0)
);
end entity;
architecture BH of regfile is
constant ZERO : std_logic_vector (5 downto 0) := "000000";
--memoria: 64 palabras de 32 bits--
type mem_reg is array (63 downto 0) of std_logic_vector(31 downto 0);
--signal
begin
process (we3, clk)
variable temp1, temp2, temp3 : integer;
variable mem_r : mem_reg;
begin
if (clk'event and clk='1') then
if (ra1 = ZERO or ra2 = ZERO ) then
rd1 <= x"00000000";
rd2 <= x"00000000";
else
temp2 := conv_integer(ra1);
temp3 := conv_integer(ra2);
--leo de mem
rd1 <= mem_r(temp2);
rd2 <= mem_r(temp3);
end if;
end if;
if (clk'event and clk='1' and we3='1') then
temp1 := conv_integer(wa3);
--escribo en mem
mem_r(temp1) := wd3;
end if;
end process;
end BH;
|
gpl-3.0
|
985fc199d8ac4893711a87fa76d1bc19
| 0.643486 | 2.611494 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module.vhd
| 2 | 14,812 |
-- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module is
port (
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
data_in : in std_logic_vector(23 downto 0) := (others => '0'); -- data_in.wire
data_out : out std_logic_vector(23 downto 0) -- data_out.wire
);
end entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module;
architecture rtl of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNJGR7GQ2L is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(17 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNJGR7GQ2L;
component alt_dspbuilder_cast_GNKXX25S2S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKXX25S2S;
component alt_dspbuilder_cast_GN6OMCQQS7 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN6OMCQQS7;
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
a : in std_logic_vector(WIDTH-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
direction : in std_logic := 'X'; -- wire
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
r : out std_logic_vector(WIDTH-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_multiply_add_GNKLXFKAO3 is
generic (
family : string := "Stratix";
direction : string := "AddAdd";
data3b_const : string := "00000000";
data2b_const : string := "00000000";
representation : string := "SIGNED";
dataWidth : integer := 8;
data4b_const : string := "00000000";
number_multipliers : integer := 2;
pipeline_register : string := "NoRegister";
use_dedicated_circuitry : integer := 0;
data1b_const : string := "00000000";
use_b_consts : natural := 0
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data1a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data2a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
data3a : in std_logic_vector(7 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(17 downto 0); -- wire
user_aclr : in std_logic := 'X'; -- wire
ena : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiply_add_GNKLXFKAO3;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_constant_GNPXZ5JSVR is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNPXZ5JSVR;
component alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN55ETJ4VI;
component alt_dspbuilder_cast_GN7IAAYCSZ is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(7 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7IAAYCSZ;
signal barrel_shifteruser_aclrgnd_output_wire : std_logic; -- Barrel_Shifteruser_aclrGND:output -> Barrel_Shifter:user_aclr
signal barrel_shifterenavcc_output_wire : std_logic; -- Barrel_ShifterenaVCC:output -> Barrel_Shifter:ena
signal multiply_adduser_aclrgnd_output_wire : std_logic; -- Multiply_Adduser_aclrGND:output -> Multiply_Add:user_aclr
signal multiply_addenavcc_output_wire : std_logic; -- Multiply_AddenaVCC:output -> Multiply_Add:ena
signal bus_concatenation_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation:output -> Bus_Concatenation1:b
signal barrel_shifter_r_wire : std_logic_vector(17 downto 0); -- Barrel_Shifter:r -> Bus_Conversion2:input
signal bus_conversion2_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion2:output -> [Bus_Concatenation1:a, Bus_Concatenation:a, Bus_Concatenation:b]
signal data_in_0_output_wire : std_logic_vector(23 downto 0); -- data_in_0:output -> [Bus_Conversion3:input, Bus_Conversion4:input, Bus_Conversion5:input]
signal constant5_output_wire : std_logic_vector(3 downto 0); -- Constant5:output -> Barrel_Shifter:distance
signal bus_conversion5_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion5:output -> Multiply_Add:data1a
signal bus_conversion4_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion4:output -> Multiply_Add:data2a
signal bus_conversion3_output_wire : std_logic_vector(7 downto 0); -- Bus_Conversion3:output -> Multiply_Add:data3a
signal multiply_add_result_wire : std_logic_vector(17 downto 0); -- Multiply_Add:result -> Barrel_Shifter:a
signal bus_concatenation1_output_wire : std_logic_vector(23 downto 0); -- Bus_Concatenation1:output -> data_out_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Barrel_Shifter:aclr, Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Multiply_Add:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Barrel_Shifter:clock, Bus_Concatenation1:clock, Bus_Concatenation:clock, Multiply_Add:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion2 : component alt_dspbuilder_cast_GNJGR7GQ2L
generic map (
round => 0,
saturate => 0
)
port map (
input => barrel_shifter_r_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNKXX25S2S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
bus_conversion4 : component alt_dspbuilder_cast_GN6OMCQQS7
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion4_output_wire -- output.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map (
widthB => 8,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion2_output_wire, -- a.wire
b => bus_conversion2_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
barrel_shifter : component alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map (
DISTANCE_WIDTH => 4,
NDIRECTION => 1,
SIGNED => 0,
use_dedicated_circuitry => "false",
PIPELINE => 0,
WIDTH => 18
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => multiply_add_result_wire, -- a.wire
r => barrel_shifter_r_wire, -- r.wire
distance => constant5_output_wire, -- distance.wire
ena => barrel_shifterenavcc_output_wire, -- ena.wire
user_aclr => barrel_shifteruser_aclrgnd_output_wire -- user_aclr.wire
);
barrel_shifteruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => barrel_shifteruser_aclrgnd_output_wire -- output.wire
);
barrel_shifterenavcc : component alt_dspbuilder_vcc_GN
port map (
output => barrel_shifterenavcc_output_wire -- output.wire
);
multiply_add : component alt_dspbuilder_multiply_add_GNKLXFKAO3
generic map (
family => "Cyclone V",
direction => "AddAdd",
data3b_const => "00011110",
data2b_const => "10010110",
representation => "UNSIGNED",
dataWidth => 8,
data4b_const => "01001100",
number_multipliers => 3,
pipeline_register => "NoRegister",
use_dedicated_circuitry => 1,
data1b_const => "01001100",
use_b_consts => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data1a => bus_conversion5_output_wire, -- data1a.wire
data2a => bus_conversion4_output_wire, -- data2a.wire
data3a => bus_conversion3_output_wire, -- data3a.wire
result => multiply_add_result_wire, -- result.wire
user_aclr => multiply_adduser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiply_addenavcc_output_wire -- ena.wire
);
multiply_adduser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiply_adduser_aclrgnd_output_wire -- output.wire
);
multiply_addenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiply_addenavcc_output_wire -- output.wire
);
data_out_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => bus_concatenation1_output_wire, -- input.wire
output => data_out -- output.wire
);
constant5 : component alt_dspbuilder_constant_GNPXZ5JSVR
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "1000",
width => 4
)
port map (
output => constant5_output_wire -- output.wire
);
data_in_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data_in, -- input.wire
output => data_in_0_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN55ETJ4VI
generic map (
widthB => 16,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion2_output_wire, -- a.wire
b => bus_concatenation_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
bus_conversion5 : component alt_dspbuilder_cast_GN7IAAYCSZ
generic map (
round => 0,
saturate => 0
)
port map (
input => data_in_0_output_wire, -- input.wire
output => bus_conversion5_output_wire -- output.wire
);
end architecture rtl; -- of Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Gray_Module
|
mit
|
dbc2038aeb61a9a7da595d00950b0770
| 0.56542 | 3.401148 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_orbit_intlk/orbit_intlk.vhd
| 1 | 28,568 |
------------------------------------------------------------------------------
-- Title : BPM orbit interlock
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2022-06-12
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Module for orbit interlock
-------------------------------------------------------------------------------
-- Copyright (c) 2020 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2020-06-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- General cores
use work.gencores_pkg.all;
-- Orbit interlock cores
use work.orbit_intlk_pkg.all;
entity orbit_intlk is
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Interlock enable and limits signals
-----------------------------
intlk_en_i : in std_logic;
intlk_clr_i : in std_logic;
-- Minimum threshold interlock on/off
intlk_min_sum_en_i : in std_logic;
-- Minimum threshold to interlock
intlk_min_sum_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-- Translation interlock on/off
intlk_trans_en_i : in std_logic;
-- Translation interlock clear
intlk_trans_clr_i : in std_logic;
intlk_trans_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-- Angular interlock on/off
intlk_ang_en_i : in std_logic;
-- Angular interlock clear
intlk_ang_clr_i : in std_logic;
intlk_ang_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_trans_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_trans_o : out std_logic;
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ang_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_ang_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_o : out std_logic
);
end orbit_intlk;
architecture rtl of orbit_intlk is
-- constants
constant c_ADC_WIDTH : natural := g_ADC_WIDTH;
constant c_DECIM_WIDTH : natural := g_DECIM_WIDTH;
constant c_INTLK_LMT_WIDTH : natural := g_INTLK_LMT_WIDTH;
-- types
type t_bit_array is array (natural range <>) of std_logic;
subtype t_decim_data is std_logic_vector(c_DECIM_WIDTH-1 downto 0);
type t_decim_data_array is array (natural range <>) of t_decim_data;
--signals
signal decim_pos_sum_array : t_decim_data_array(c_NUM_BPMS-1 downto 0);
signal decim_pos_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0);
signal intlk_trans_bigger_ltc : std_logic;
signal intlk_trans_bigger : std_logic;
signal intlk_trans_smaller_ltc : std_logic;
signal intlk_trans_smaller : std_logic;
signal intlk_trans_ltc : std_logic;
signal intlk_trans : std_logic;
signal intlk_ang_bigger_ltc : std_logic;
signal intlk_ang_bigger : std_logic;
signal intlk_ang_smaller_ltc : std_logic;
signal intlk_ang_smaller : std_logic;
signal intlk_ang_ltc : std_logic;
signal intlk_ang : std_logic;
signal intlk_all : std_logic;
signal intlk_ltc : std_logic;
signal intlk : std_logic;
signal intlk_min_sum_n : std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
signal intlk_min_sum_valid : t_bit_array(c_NUM_BPMS-1 downto 0);
signal intlk_sum_bigger : t_bit_array(c_NUM_BPMS-1 downto 0);
signal intlk_sum_bigger_valid : t_bit_array(c_NUM_BPMS-1 downto 0);
signal intlk_sum_bigger_reg : t_bit_array(c_NUM_BPMS-1 downto 0);
signal intlk_sum_bigger_or : t_bit_array(c_NUM_BPMS downto 0);
signal intlk_sum_bigger_any : std_logic;
signal intlk_sum_bigger_en : std_logic;
signal intlk_trans_master_en : std_logic;
signal intlk_ang_master_en : std_logic;
-- synched signals
signal adc_ds_ch0_swap : std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
signal adc_ds_ch1_swap : std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
signal adc_ds_ch2_swap : std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
signal adc_ds_ch3_swap : std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
signal adc_ds_tag : std_logic_vector(0 downto 0) := (others => '0');
signal adc_ds_swap_valid : std_logic := '0';
signal decim_ds_pos_x : std_logic_vector(g_DECIM_WIDTH-1 downto 0);
signal decim_ds_pos_y : std_logic_vector(g_DECIM_WIDTH-1 downto 0);
signal decim_ds_pos_q : std_logic_vector(g_DECIM_WIDTH-1 downto 0);
signal decim_ds_pos_sum : std_logic_vector(g_DECIM_WIDTH-1 downto 0);
signal decim_ds_pos_valid : std_logic;
signal adc_us_ch0_swap : std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
signal adc_us_ch1_swap : std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
signal adc_us_ch2_swap : std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
signal adc_us_ch3_swap : std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
signal adc_us_tag : std_logic_vector(0 downto 0) := (others => '0');
signal adc_us_swap_valid : std_logic := '0';
signal decim_us_pos_x : std_logic_vector(g_DECIM_WIDTH-1 downto 0);
signal decim_us_pos_y : std_logic_vector(g_DECIM_WIDTH-1 downto 0);
signal decim_us_pos_q : std_logic_vector(g_DECIM_WIDTH-1 downto 0);
signal decim_us_pos_sum : std_logic_vector(g_DECIM_WIDTH-1 downto 0);
signal decim_us_pos_valid : std_logic;
begin
cmp_orbit_intlk_cdc : orbit_intlk_cdc
generic map
(
g_ADC_WIDTH => g_ADC_WIDTH,
g_DECIM_WIDTH => g_DECIM_WIDTH,
g_INTLK_LMT_WIDTH => g_INTLK_LMT_WIDTH
)
port map
(
-----------------------------
-- Clocks and resets
-----------------------------
ref_rst_n_i => ref_rst_n_i,
ref_clk_i => ref_clk_i,
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i => fs_clk_ds_i,
adc_ds_ch0_swap_i => adc_ds_ch0_swap_i,
adc_ds_ch1_swap_i => adc_ds_ch1_swap_i,
adc_ds_ch2_swap_i => adc_ds_ch2_swap_i,
adc_ds_ch3_swap_i => adc_ds_ch3_swap_i,
adc_ds_tag_i => adc_ds_tag_i,
adc_ds_swap_valid_i => adc_ds_swap_valid_i,
decim_ds_pos_x_i => decim_ds_pos_x_i,
decim_ds_pos_y_i => decim_ds_pos_y_i,
decim_ds_pos_q_i => decim_ds_pos_q_i,
decim_ds_pos_sum_i => decim_ds_pos_sum_i,
decim_ds_pos_valid_i => decim_ds_pos_valid_i,
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i => fs_clk_us_i,
adc_us_ch0_swap_i => adc_us_ch0_swap_i,
adc_us_ch1_swap_i => adc_us_ch1_swap_i,
adc_us_ch2_swap_i => adc_us_ch2_swap_i,
adc_us_ch3_swap_i => adc_us_ch3_swap_i,
adc_us_tag_i => adc_us_tag_i,
adc_us_swap_valid_i => adc_us_swap_valid_i,
decim_us_pos_x_i => decim_us_pos_x_i,
decim_us_pos_y_i => decim_us_pos_y_i,
decim_us_pos_q_i => decim_us_pos_q_i,
decim_us_pos_sum_i => decim_us_pos_sum_i,
decim_us_pos_valid_i => decim_us_pos_valid_i,
-----------------------------
-- Synched Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_o => adc_ds_ch0_swap,
adc_ds_ch1_swap_o => adc_ds_ch1_swap,
adc_ds_ch2_swap_o => adc_ds_ch2_swap,
adc_ds_ch3_swap_o => adc_ds_ch3_swap,
adc_ds_tag_o => adc_ds_tag,
adc_ds_swap_valid_o => adc_ds_swap_valid,
decim_ds_pos_x_o => decim_ds_pos_x,
decim_ds_pos_y_o => decim_ds_pos_y,
decim_ds_pos_q_o => decim_ds_pos_q,
decim_ds_pos_sum_o => decim_ds_pos_sum,
decim_ds_pos_valid_o => decim_ds_pos_valid,
-----------------------------
-- Synched Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_o => adc_us_ch0_swap,
adc_us_ch1_swap_o => adc_us_ch1_swap,
adc_us_ch2_swap_o => adc_us_ch2_swap,
adc_us_ch3_swap_o => adc_us_ch3_swap,
adc_us_tag_o => adc_us_tag,
adc_us_swap_valid_o => adc_us_swap_valid,
decim_us_pos_x_o => decim_us_pos_x,
decim_us_pos_y_o => decim_us_pos_y,
decim_us_pos_q_o => decim_us_pos_q,
decim_us_pos_sum_o => decim_us_pos_sum,
decim_us_pos_valid_o => decim_us_pos_valid
);
---------------------------------
-- Signal mangling
--------------------------------
-- Downstream
decim_pos_sum_array(c_BPM_DS_IDX) <= decim_ds_pos_sum;
decim_pos_valid_array(c_BPM_DS_IDX) <= decim_ds_pos_valid;
-- Upstream
decim_pos_sum_array(c_BPM_US_IDX) <= decim_us_pos_sum;
decim_pos_valid_array(c_BPM_US_IDX) <= decim_us_pos_valid;
intlk_min_sum_n <= not intlk_min_sum_i;
gen_sum_intlk : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
----------------------------------
-- Detect sum >= Threshold
----------------------------------
-- Compare with threshold. Use the simple identity that:
-- A >= B is the same A + (-B) and we check if MSB Carry
-- is 1
cmp_trans_thold_bigger : gc_big_adder2
generic map (
g_data_bits => c_DECIM_WIDTH
)
port map (
clk_i => ref_clk_i,
stall_i => '0',
valid_i => decim_pos_valid_array(i),
a_i => decim_pos_sum_array(i),
b_i => intlk_min_sum_n,
c_i => '1',
c2_o => intlk_sum_bigger(i),
c2x2_valid_o => intlk_sum_bigger_valid(i)
);
-- gc_big_adder2 outputs are unregistered. So register them.
p_sum_thold_bigger_reg : process(ref_clk_i)
begin
if rising_edge(ref_clk_i) then
if ref_rst_n_i = '0' then
intlk_sum_bigger_reg(i) <= '0';
elsif intlk_sum_bigger_valid(i) = '1' then
intlk_sum_bigger_reg(i) <= intlk_sum_bigger(i);
end if;
end if;
end process;
end generate;
intlk_sum_bigger_or(0) <= '0';
-- ORing all trans_bigger
gen_intlk_sum_bigger : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
intlk_sum_bigger_or(i+1) <= intlk_sum_bigger_or(i) or intlk_sum_bigger_reg(i);
end generate;
p_reg_enable : process(ref_clk_i)
begin
if rising_edge(ref_clk_i) then
if ref_rst_n_i = '0' then
intlk_sum_bigger_any <= '0';
intlk_trans_master_en <= '0';
intlk_ang_master_en <= '0';
else
intlk_sum_bigger_any <= intlk_sum_bigger_or(c_INTLK_GEN_UPTO_CHANNEL+1);
intlk_trans_master_en <= intlk_trans_en_i and intlk_sum_bigger_en;
intlk_ang_master_en <= intlk_ang_en_i and intlk_sum_bigger_en;
end if;
end if;
end process;
intlk_sum_bigger_en <= '1' when intlk_min_sum_en_i = '0' else intlk_sum_bigger_any;
-----------------------------
-- Translation interlock
-----------------------------
cmp_orbit_intlk_trans : orbit_intlk_trans
generic map
(
g_ADC_WIDTH => g_ADC_WIDTH,
g_DECIM_WIDTH => g_DECIM_WIDTH,
-- interlock limits
g_INTLK_LMT_WIDTH => g_INTLK_LMT_WIDTH
)
port map
(
-----------------------------
-- Clocks and resets
-----------------------------
fs_rst_n_i => ref_rst_n_i,
fs_clk_i => ref_clk_i,
-----------------------------
-- Interlock enable and limits signals
-----------------------------
-- Translation interlock on/off
intlk_trans_en_i => intlk_trans_master_en,
-- Translation interlock clear
intlk_trans_clr_i => intlk_trans_clr_i,
intlk_trans_max_x_i => intlk_trans_max_x_i,
intlk_trans_max_y_i => intlk_trans_max_y_i,
intlk_trans_min_x_i => intlk_trans_min_x_i,
intlk_trans_min_y_i => intlk_trans_min_y_i,
-----------------------------
-- Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_i => adc_ds_ch0_swap,
adc_ds_ch1_swap_i => adc_ds_ch1_swap,
adc_ds_ch2_swap_i => adc_ds_ch2_swap,
adc_ds_ch3_swap_i => adc_ds_ch3_swap,
adc_ds_tag_i => adc_ds_tag,
adc_ds_swap_valid_i => adc_ds_swap_valid,
decim_ds_pos_x_i => decim_ds_pos_x,
decim_ds_pos_y_i => decim_ds_pos_y,
decim_ds_pos_q_i => decim_ds_pos_q,
decim_ds_pos_sum_i => decim_ds_pos_sum,
decim_ds_pos_valid_i => decim_ds_pos_valid,
-----------------------------
-- Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_i => adc_us_ch0_swap,
adc_us_ch1_swap_i => adc_us_ch1_swap,
adc_us_ch2_swap_i => adc_us_ch2_swap,
adc_us_ch3_swap_i => adc_us_ch3_swap,
adc_us_tag_i => adc_us_tag,
adc_us_swap_valid_i => adc_us_swap_valid,
decim_us_pos_x_i => decim_us_pos_x,
decim_us_pos_y_i => decim_us_pos_y,
decim_us_pos_q_i => decim_us_pos_q,
decim_us_pos_sum_i => decim_us_pos_sum,
decim_us_pos_valid_i => decim_us_pos_valid,
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o => intlk_trans_bigger_x_o,
intlk_trans_bigger_y_o => intlk_trans_bigger_y_o,
intlk_trans_bigger_ltc_x_o => intlk_trans_bigger_ltc_x_o,
intlk_trans_bigger_ltc_y_o => intlk_trans_bigger_ltc_y_o,
intlk_trans_bigger_any_o => intlk_trans_bigger_any_o,
intlk_trans_bigger_ltc_o => intlk_trans_bigger_ltc,
intlk_trans_bigger_o => intlk_trans_bigger,
intlk_trans_smaller_x_o => intlk_trans_smaller_x_o,
intlk_trans_smaller_y_o => intlk_trans_smaller_y_o,
intlk_trans_smaller_ltc_x_o => intlk_trans_smaller_ltc_x_o,
intlk_trans_smaller_ltc_y_o => intlk_trans_smaller_ltc_y_o,
intlk_trans_smaller_any_o => intlk_trans_smaller_any_o,
intlk_trans_smaller_ltc_o => intlk_trans_smaller_ltc,
intlk_trans_smaller_o => intlk_trans_smaller
);
intlk_trans_ltc <= intlk_trans_bigger_ltc or intlk_trans_smaller_ltc;
intlk_trans <= intlk_trans_bigger or intlk_trans_smaller;
-- Outputs
intlk_trans_ltc_o <= intlk_trans_ltc;
intlk_trans_o <= intlk_trans;
intlk_trans_bigger_ltc_o <= intlk_trans_bigger_ltc;
intlk_trans_bigger_o <= intlk_trans_bigger;
intlk_trans_smaller_ltc_o <= intlk_trans_smaller_ltc;
intlk_trans_smaller_o <= intlk_trans_smaller;
-----------------------------
-- Angular interlock
-----------------------------
cmp_orbit_intlk_ang : orbit_intlk_ang
generic map
(
g_ADC_WIDTH => g_ADC_WIDTH,
g_DECIM_WIDTH => g_DECIM_WIDTH,
-- interlock limits
g_INTLK_LMT_WIDTH => g_INTLK_LMT_WIDTH
)
port map
(
-----------------------------
-- Clocks and resets
-----------------------------
fs_rst_n_i => ref_rst_n_i,
fs_clk_i => ref_clk_i,
-----------------------------
-- Interlock enable and limits signals
-----------------------------
-- Angular interlock on/off
intlk_ang_en_i => intlk_ang_master_en,
-- Angular interlock clear
intlk_ang_clr_i => intlk_ang_clr_i,
intlk_ang_max_x_i => intlk_ang_max_x_i,
intlk_ang_max_y_i => intlk_ang_max_y_i,
intlk_ang_min_x_i => intlk_ang_min_x_i,
intlk_ang_min_y_i => intlk_ang_min_y_i,
-----------------------------
-- Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_i => adc_ds_ch0_swap,
adc_ds_ch1_swap_i => adc_ds_ch1_swap,
adc_ds_ch2_swap_i => adc_ds_ch2_swap,
adc_ds_ch3_swap_i => adc_ds_ch3_swap,
adc_ds_tag_i => adc_ds_tag,
adc_ds_swap_valid_i => adc_ds_swap_valid,
decim_ds_pos_x_i => decim_ds_pos_x,
decim_ds_pos_y_i => decim_ds_pos_y,
decim_ds_pos_q_i => decim_ds_pos_q,
decim_ds_pos_sum_i => decim_ds_pos_sum,
decim_ds_pos_valid_i => decim_ds_pos_valid,
-----------------------------
-- Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_i => adc_us_ch0_swap,
adc_us_ch1_swap_i => adc_us_ch1_swap,
adc_us_ch2_swap_i => adc_us_ch2_swap,
adc_us_ch3_swap_i => adc_us_ch3_swap,
adc_us_tag_i => adc_us_tag,
adc_us_swap_valid_i => adc_us_swap_valid,
decim_us_pos_x_i => decim_us_pos_x,
decim_us_pos_y_i => decim_us_pos_y,
decim_us_pos_q_i => decim_us_pos_q,
decim_us_pos_sum_i => decim_us_pos_sum,
decim_us_pos_valid_i => decim_us_pos_valid,
-----------------------------
-- Interlock outputs
-----------------------------
intlk_ang_bigger_x_o => intlk_ang_bigger_x_o,
intlk_ang_bigger_y_o => intlk_ang_bigger_y_o,
intlk_ang_bigger_ltc_x_o => intlk_ang_bigger_ltc_x_o,
intlk_ang_bigger_ltc_y_o => intlk_ang_bigger_ltc_y_o,
intlk_ang_bigger_any_o => intlk_ang_bigger_any_o,
intlk_ang_bigger_ltc_o => intlk_ang_bigger_ltc,
intlk_ang_bigger_o => intlk_ang_bigger,
intlk_ang_smaller_x_o => intlk_ang_smaller_x_o,
intlk_ang_smaller_y_o => intlk_ang_smaller_y_o,
intlk_ang_smaller_ltc_x_o => intlk_ang_smaller_ltc_x_o,
intlk_ang_smaller_ltc_y_o => intlk_ang_smaller_ltc_y_o,
intlk_ang_smaller_any_o => intlk_ang_smaller_any_o,
intlk_ang_smaller_ltc_o => intlk_ang_smaller_ltc,
intlk_ang_smaller_o => intlk_ang_smaller
);
intlk_ang_ltc <= intlk_ang_bigger_ltc or intlk_ang_smaller_ltc;
intlk_ang <= intlk_ang_bigger or intlk_ang_smaller;
-- Outputs
intlk_ang_ltc_o <= intlk_ang_ltc;
intlk_ang_o <= intlk_ang;
intlk_ang_bigger_ltc_o <= intlk_ang_bigger_ltc;
intlk_ang_bigger_o <= intlk_ang_bigger;
intlk_ang_smaller_ltc_o <= intlk_ang_smaller_ltc;
intlk_ang_smaller_o <= intlk_ang_smaller;
-------------------------------------------------------------------------
-- General interlock detector. Only for X and Y.
-------------------------------------------------------------------------
intlk_all <= (intlk_trans or intlk_ang) and intlk_en_i;
p_out : process(ref_clk_i)
begin
if rising_edge(ref_clk_i) then
if ref_rst_n_i = '0' then
intlk_ltc <= '0';
intlk <= '0';
else
-- latch up translation interlock status
-- only clear on "clear" signal
if intlk_clr_i = '1' then
intlk_ltc <= '0';
elsif intlk_all = '1' then
intlk_ltc <= '1';
end if;
-- register translation interlock when active
if intlk_clr_i = '1' or intlk_en_i = '0' then
intlk <= '0';
elsif intlk_en_i = '1' then
intlk <= intlk_all;
end if;
end if;
end if;
end process;
intlk_ltc_o <= intlk_ltc;
intlk_o <= intlk;
end rtl;
|
lgpl-3.0
|
78030580b32b32233c6eadbc1e83bf47
| 0.459465 | 3.586692 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_orbit_intlk/orbit_intlk_ang.vhd
| 1 | 21,929 |
------------------------------------------------------------------------------
-- Title : BPM orbit angular interlock
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2022-06-12
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Module for angular orbit interlock
-------------------------------------------------------------------------------
-- Copyright (c) 2020 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2020-06-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- General cores
use work.gencores_pkg.all;
-- Orbit interlock cores
use work.orbit_intlk_pkg.all;
entity orbit_intlk_ang is
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Interlock enable and limits signals
-----------------------------
-- Angular interlock on/off
intlk_ang_en_i : in std_logic;
-- Angular interlock clear
intlk_ang_clr_i : in std_logic;
intlk_ang_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-----------------------------
-- Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic
);
end orbit_intlk_ang;
architecture rtl of orbit_intlk_ang is
-- constants
constant c_ADC_WIDTH : natural := g_ADC_WIDTH;
constant c_DECIM_WIDTH : natural := g_DECIM_WIDTH;
constant c_INTLK_LMT_WIDTH : natural := g_INTLK_LMT_WIDTH;
-- types
type t_bit_array is array (natural range <>) of std_logic;
subtype t_adc_data is std_logic_vector(c_adc_width-1 downto 0);
type t_adc_data_array is array (natural range <>) of t_adc_data;
subtype t_adc_tag is std_logic_vector(0 downto 0);
type t_adc_tag_array is array (natural range <>) of t_adc_tag;
subtype t_decim_data is std_logic_vector(c_decim_width-1 downto 0);
type t_decim_data_array is array (natural range <>) of t_decim_data;
subtype t_intlk_lmt_data is std_logic_vector(c_intlk_lmt_width-1 downto 0);
type t_intlk_lmt_data_array is array (natural range <>) of t_intlk_lmt_data;
type t_adc_data_array2d is array (natural range <>, natural range <>) of t_adc_data;
type t_decim_data_array2d is array (natural range <>, natural range <>) of t_decim_data;
--signals
-- input mangling
signal adc_array : t_adc_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal adc_tag_array : t_adc_tag_array(c_NUM_BPMS-1 downto 0);
signal adc_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0);
signal decim_pos_array : t_decim_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal decim_pos_array_n : t_decim_data_array2d(c_NUM_BPMS-1 downto 0, c_NUM_CHANNELS-1 downto 0);
signal decim_pos_valid_array : t_bit_array(c_NUM_BPMS-1 downto 0);
-- interlock limits
signal intlk_ang_max : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0);
signal intlk_ang_max_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal intlk_ang_max_n : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0);
signal intlk_ang_min : t_intlk_lmt_data_array(c_NUM_CHANNELS-1 downto 0);
signal intlk_ang_min_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0);
-- valid AND
signal adc_valid_and : t_bit_array(c_NUM_BPMS downto 0);
signal adc_valid : std_logic;
signal decim_pos_valid_and : t_bit_array(c_NUM_BPMS downto 0);
signal decim_pos_valid : std_logic;
-- angular interlock
signal ang_sum : t_decim_data_array(c_NUM_CHANNELS-1 downto 0);
signal ang_sum_reg : t_decim_data_array(c_NUM_CHANNELS-1 downto 0);
signal ang_sum_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_sum_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang : t_decim_data_array(c_NUM_CHANNELS-1 downto 0);
signal ang_high_bit : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_n : t_decim_data_array(c_NUM_CHANNELS-1 downto 0);
signal ang_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_bigger : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_bigger_comb : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_bigger_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_bigger_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_bigger_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_smaller : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_smaller_comb : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_smaller_n : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_smaller_valid : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_smaller_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_smaller_valid_reg : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_intlk_det_bigger_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_intlk_bigger_ltc_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_intlk_bigger_or : t_bit_array(c_NUM_CHANNELS downto 0);
signal ang_intlk_bigger_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_intlk_bigger_ltc_or : t_bit_array(c_NUM_CHANNELS downto 0);
signal ang_intlk_bigger_ltc : std_logic;
signal ang_intlk_bigger_any : std_logic;
signal ang_intlk_bigger : std_logic;
signal ang_intlk_det_smaller_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_intlk_smaller_ltc_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_intlk_smaller_or : t_bit_array(c_NUM_CHANNELS downto 0);
signal ang_intlk_smaller_all : t_bit_array(c_NUM_CHANNELS-1 downto 0);
signal ang_intlk_smaller_ltc_or : t_bit_array(c_NUM_CHANNELS downto 0);
signal ang_intlk_smaller_ltc : std_logic;
signal ang_intlk_smaller_any : std_logic;
signal ang_intlk_smaller : std_logic;
begin
---------------------------------
-- Signal mangling
--------------------------------
-- Downstream
adc_array(c_BPM_DS_IDX, 0) <= adc_ds_ch0_swap_i;
adc_array(c_BPM_DS_IDX, 1) <= adc_ds_ch1_swap_i;
adc_array(c_BPM_DS_IDX, 2) <= adc_ds_ch2_swap_i;
adc_array(c_BPM_DS_IDX, 3) <= adc_ds_ch3_swap_i;
adc_tag_array(c_BPM_DS_IDX) <= adc_ds_tag_i;
adc_valid_array(c_BPM_DS_IDX) <= adc_ds_swap_valid_i;
decim_pos_array(c_BPM_DS_IDX, 0) <= decim_ds_pos_x_i;
decim_pos_array(c_BPM_DS_IDX, 1) <= decim_ds_pos_y_i;
decim_pos_array(c_BPM_DS_IDX, 2) <= decim_ds_pos_q_i;
decim_pos_array(c_BPM_DS_IDX, 3) <= decim_ds_pos_sum_i;
decim_pos_valid_array(c_BPM_DS_IDX) <= decim_ds_pos_valid_i;
decim_pos_array_n(c_BPM_DS_IDX, 0) <= not decim_ds_pos_x_i;
decim_pos_array_n(c_BPM_DS_IDX, 1) <= not decim_ds_pos_y_i;
decim_pos_array_n(c_BPM_DS_IDX, 2) <= not decim_ds_pos_q_i;
decim_pos_array_n(c_BPM_DS_IDX, 3) <= not decim_ds_pos_sum_i;
-- Upwnstream
adc_array(c_BPM_US_IDX, 0) <= adc_us_ch0_swap_i;
adc_array(c_BPM_US_IDX, 1) <= adc_us_ch1_swap_i;
adc_array(c_BPM_US_IDX, 2) <= adc_us_ch2_swap_i;
adc_array(c_BPM_US_IDX, 3) <= adc_us_ch3_swap_i;
adc_tag_array(c_BPM_US_IDX) <= adc_us_tag_i;
adc_valid_array(c_BPM_US_IDX) <= adc_us_swap_valid_i;
decim_pos_array(c_BPM_US_IDX, 0) <= decim_us_pos_x_i;
decim_pos_array(c_BPM_US_IDX, 1) <= decim_us_pos_y_i;
decim_pos_array(c_BPM_US_IDX, 2) <= decim_us_pos_q_i;
decim_pos_array(c_BPM_US_IDX, 3) <= decim_us_pos_sum_i;
decim_pos_valid_array(c_BPM_US_IDX) <= decim_us_pos_valid_i;
decim_pos_array_n(c_BPM_US_IDX, 0) <= not decim_us_pos_x_i;
decim_pos_array_n(c_BPM_US_IDX, 1) <= not decim_us_pos_y_i;
decim_pos_array_n(c_BPM_US_IDX, 2) <= not decim_us_pos_q_i;
decim_pos_array_n(c_BPM_US_IDX, 3) <= not decim_us_pos_sum_i;
-- Interlock limits
-- X limits
intlk_ang_max(0) <= intlk_ang_max_x_i;
intlk_ang_min(0) <= intlk_ang_min_x_i;
-- Y limits
intlk_ang_max(1) <= intlk_ang_max_y_i;
intlk_ang_min(1) <= intlk_ang_min_y_i;
----------------------------------
-- Calculate angular
----------------------------------
-- ANDing ADC valids
adc_valid_and(0) <= '1';
gen_adc_valid : for i in 0 to c_NUM_BPMS-1 generate
adc_valid_and(i+1) <= adc_valid_and(i) and adc_valid_array(i);
end generate;
adc_valid <= adc_valid_and(c_NUM_BPMS);
-- ANDing DECIM valids
decim_pos_valid_and(0) <= '1';
gen_decim_pos_valid : for i in 0 to c_NUM_BPMS-1 generate
decim_pos_valid_and(i+1) <= decim_pos_valid_and(i) and decim_pos_valid_array(i);
end generate;
decim_pos_valid <= decim_pos_valid_and(c_NUM_BPMS);
-------------------------------------------------------------------------
-- Angular interlock detector. Only for X and Y.
-- Calculation is a simple (us = upstream, ds = downstream):
-- x_ang = x_us - x_ds / distance_between_bpms OR
-- x_ang * distance_between_bpms = x_us - x_ds
--
-- y_ang = y_us - y_ds / distance_between_bpms OR
-- y_ang * distance_between_bpms = y_us - y_ds
-------------------------------------------------------------------------
gen_ang_intlk : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
----------------------------------
-- Calculate angle
----------------------------------
cmp_ang_adder : gc_big_adder2
generic map (
g_data_bits => c_DECIM_WIDTH
)
port map (
clk_i => fs_clk_i,
stall_i => '0',
valid_i => decim_pos_valid,
a_i => decim_pos_array(c_BPM_US_IDX, i),
b_i => decim_pos_array_n(c_BPM_DS_IDX, i),
c_i => '1',
x2_o => ang_sum(i),
c2x2_valid_o => ang_sum_valid(i)
);
-- gc_big_adder2 outputs are unregistered. So register them.
p_ang_reg : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
ang_sum_valid_reg(i) <= '0';
else
if ang_sum_valid(i) = '1' then
ang_sum_reg(i) <= ang_sum(i);
end if;
ang_sum_valid_reg(i) <= ang_sum_valid(i);
end if;
end if;
end process;
ang(i) <= ang_sum_reg(i);
ang_valid(i) <= ang_sum_valid_reg(i);
----------------------------------
-- Detect position > Threshold
----------------------------------
-- Compare with threshold. Use the simple identity that:
-- A > B is the same as A + (-B) and we check if MSB Carry
-- is 1
cmp_ang_thold_bigger : gc_big_adder2
generic map (
g_data_bits => c_DECIM_WIDTH
)
port map (
clk_i => fs_clk_i,
stall_i => '0',
valid_i => ang_valid(i),
a_i => ang(i),
b_i => intlk_ang_max_n(i),
c_i => '1',
c2_o => ang_bigger_comb(i),
c2x2_valid_o => ang_bigger_valid(i)
);
intlk_ang_max_n(i) <= not intlk_ang_max(i);
-- comparison of different sign operands fails with the above method.
-- Just compare the sign bits, for these cases.
ang_high_bit(i) <= ang(i)(ang(i)'high);
intlk_ang_max_high_bit(i) <= intlk_ang_max(i)(intlk_ang_max(i)'high);
ang_bigger(i) <= ang_bigger_comb(i) when
(ang_high_bit(i) xnor intlk_ang_max_high_bit(i)) = '1' else
intlk_ang_max_high_bit(i);
-- gc_big_adder2 outputs are unregistered. So register them.
p_ang_thold_bigger_reg : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
ang_bigger_valid_reg(i) <= '0';
else
if ang_bigger_valid(i) = '1' then
ang_bigger_reg(i) <= ang_bigger(i);
end if;
ang_bigger_valid_reg(i) <= ang_bigger_valid(i);
end if;
end if;
end process;
----------------------------------
-- Detect position < Threshold
----------------------------------
-- Compare with threshold. Use the simple identity that:
-- A < B is the same as -A > -B = -A + B > 0 and we check
-- if MSB Carry is 1
cmp_ang_thold_smaller : gc_big_adder2
generic map (
g_data_bits => c_DECIM_WIDTH
)
port map (
clk_i => fs_clk_i,
stall_i => '0',
valid_i => ang_valid(i),
a_i => ang_n(i),
b_i => intlk_ang_min(i),
c_i => '1',
c2_o => ang_smaller_comb(i),
c2x2_valid_o => ang_smaller_valid(i)
);
ang_n(i) <= not ang(i);
-- comparison of different sign operands fails with the above method.
-- Just compare the sign bits, for these cases.
intlk_ang_min_high_bit(i) <= intlk_ang_min(i)(intlk_ang_min(i)'high);
ang_smaller(i) <= ang_smaller_comb(i) when
(ang_high_bit(i) xnor intlk_ang_min_high_bit(i)) = '1' else
ang_high_bit(i);
-- gc_big_adder2 outputs are unregistered. So register them.
p_ang_thold_smaller_reg : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
ang_smaller_valid_reg(i) <= '0';
else
if ang_smaller_valid(i) = '1' then
ang_smaller_reg(i) <= ang_smaller(i);
end if;
ang_smaller_valid_reg(i) <= ang_smaller_valid(i);
end if;
end if;
end process;
----------------------------------
-- Latch interlocks
----------------------------------
ang_intlk_det_bigger_all(i) <= ang_bigger_reg(i) and ang_bigger_valid_reg(i);
ang_intlk_det_smaller_all(i) <= ang_smaller_reg(i) and ang_smaller_valid_reg(i);
-- latch all interlocks
p_latch : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
ang_intlk_bigger_ltc_all(i) <= '0';
ang_intlk_smaller_ltc_all(i) <= '0';
else
-- latch up anglation interlock status
-- only clear on "clear" signal
if intlk_ang_clr_i = '1' then
ang_intlk_bigger_ltc_all(i) <= '0';
elsif ang_intlk_det_bigger_all(i) = '1' and
intlk_ang_en_i = '1' then
ang_intlk_bigger_ltc_all(i) <= '1';
end if;
if intlk_ang_clr_i = '1' then
ang_intlk_smaller_ltc_all(i) <= '0';
elsif ang_intlk_det_smaller_all(i) = '1' and
intlk_ang_en_i = '1' then
ang_intlk_smaller_ltc_all(i) <= '1';
end if;
-- register anglation interlock when active
if intlk_ang_clr_i = '1' or intlk_ang_en_i = '0' then
ang_intlk_bigger_all(i) <= '0';
else
ang_intlk_bigger_all(i) <= ang_intlk_det_bigger_all(i);
end if;
if intlk_ang_clr_i = '1' or intlk_ang_en_i = '0' then
ang_intlk_smaller_all(i) <= '0';
else
ang_intlk_smaller_all(i) <= ang_intlk_det_smaller_all(i);
end if;
end if;
end if;
end process;
end generate;
intlk_ang_bigger_ltc_x_o <= ang_intlk_bigger_ltc_all(c_CHAN_X_IDX);
intlk_ang_bigger_ltc_y_o <= ang_intlk_bigger_ltc_all(c_CHAN_Y_IDX);
intlk_ang_bigger_x_o <= ang_intlk_bigger_all(c_CHAN_X_IDX);
intlk_ang_bigger_y_o <= ang_intlk_bigger_all(c_CHAN_Y_IDX);
intlk_ang_smaller_ltc_x_o <= ang_intlk_smaller_ltc_all(c_CHAN_X_IDX);
intlk_ang_smaller_ltc_y_o <= ang_intlk_smaller_ltc_all(c_CHAN_Y_IDX);
intlk_ang_smaller_x_o <= ang_intlk_smaller_all(c_CHAN_X_IDX);
intlk_ang_smaller_y_o <= ang_intlk_smaller_all(c_CHAN_Y_IDX);
----------------------------------
-- Angular interlock merging
----------------------------------
----------------------------------
-- Bigger
----------------------------------
ang_intlk_bigger_or(0) <= '0';
-- ORing all ang_bigger
gen_ang_intlk_bigger : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
ang_intlk_bigger_or(i+1) <= ang_intlk_bigger_or(i) or ang_intlk_bigger_all(i);
end generate;
ang_intlk_bigger <= ang_intlk_bigger_or(c_INTLK_GEN_UPTO_CHANNEL+1);
intlk_ang_bigger_o <= ang_intlk_bigger;
intlk_ang_bigger_any_o <= ang_intlk_bigger;
ang_intlk_bigger_ltc_or(0) <= '0';
-- ORing all ang_bigger_ltc
gen_ang_intlk_bigger_ltc : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
ang_intlk_bigger_ltc_or(i+1) <= ang_intlk_bigger_ltc_or(i) or ang_intlk_bigger_ltc_all(i);
end generate;
ang_intlk_bigger_ltc <= ang_intlk_bigger_ltc_or(c_INTLK_GEN_UPTO_CHANNEL+1);
intlk_ang_bigger_ltc_o <= ang_intlk_bigger_ltc;
----------------------------------
-- Smaller
----------------------------------
ang_intlk_smaller_or(0) <= '0';
-- ORing all ang_smaller
gen_ang_intlk_smaller : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
ang_intlk_smaller_or(i+1) <= ang_intlk_smaller_or(i) or ang_intlk_smaller_all(i);
end generate;
ang_intlk_smaller <= ang_intlk_smaller_or(c_INTLK_GEN_UPTO_CHANNEL+1);
intlk_ang_smaller_o <= ang_intlk_smaller;
intlk_ang_smaller_any_o <= ang_intlk_smaller;
ang_intlk_smaller_ltc_or(0) <= '0';
-- ORing all ang_smaller_ltc
gen_ang_intlk_smaller_ltc : for i in 0 to c_INTLK_GEN_UPTO_CHANNEL generate
ang_intlk_smaller_ltc_or(i+1) <= ang_intlk_smaller_ltc_or(i) or ang_intlk_smaller_ltc_all(i);
end generate;
ang_intlk_smaller_ltc <= ang_intlk_smaller_ltc_or(c_INTLK_GEN_UPTO_CHANNEL+1);
intlk_ang_smaller_ltc_o <= ang_intlk_smaller_ltc;
end rtl;
|
lgpl-3.0
|
27f21f6a266b3801df6c168f40e35f8d
| 0.536687 | 3.123789 | false | false | false | false |
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