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int64 137
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| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
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float64 1.51
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bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_01.vhd
| 4 | 1,751 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_07_01 is
end entity fg_07_01;
architecture test of fg_07_01 is
shared variable average : real := 0.0;
type sample_array is array (positive range <>) of real;
constant samples : sample_array :=
( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0 );
-- code from book
procedure average_samples is
variable total : real := 0.0;
begin
assert samples'length > 0 severity failure;
for index in samples'range loop
total := total + samples(index);
end loop;
average := total / real(samples'length);
end procedure average_samples;
-- end code from book
begin
-- code from book (in text)
average_samples;
-- end code from book
end architecture test;
|
gpl-2.0
|
f92d238d7c6865979b6f6563d6ec0ada
| 0.631068 | 3.823144 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket11/signalevents.vhdl
| 3 | 394 |
entity tb is
end entity;
architecture arch of tb is
signal s: integer := 0;
begin
process is
begin
wait for 1 us;
s <= 1;
s <= 2 after 1 us;
assert s = 0;
wait on s;
report "s = " & integer'image(s);
assert s = 2 severity failure;
assert now = 2 us severity failure;
wait;
end process;
end architecture;
|
gpl-2.0
|
ab2691ac9c2cd23d21e95ef23d31c36d
| 0.535533 | 3.862745 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/building_blocks/invSubByte_tb.vhd
| 1 | 1,692 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 10:49:35 PM
-- Design Name:
-- Module Name: invSubByte_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity invSubByte_tb is
end invSubByte_tb;
architecture Behavioral of invSubByte_tb is
component invSubByte is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
constant clk_period : time := 2ns;
signal CLK, RESET : STD_LOGIC := '0';
signal byteIn, byteOut : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
uut: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => byteIn,
byteOut => byteOut);
clk_process: process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process;
stim_process: process
begin
byteIn <= x"05";
wait for clk_period;
byteIn <= x"70";
wait for clk_period;
RESET <= '1';
byteIn <= x"80";
wait for clk_period;
RESET <= '0';
wait for clk_period;
end process;
end Behavioral;
|
gpl-2.0
|
ae0cfde56ba2696a3845edc0c4c3ccb8
| 0.477541 | 4.316327 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc221.vhd
| 4 | 1,785 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc221.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p07n01i00221ent IS
END c03s01b01x00p07n01i00221ent;
ARCHITECTURE c03s01b01x00p07n01i00221arch OF c03s01b01x00p07n01i00221ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if ('0' = '0') then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c03s01b01x00p07n01i00221"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c03s01b01x00p07n01i00221 - The type of the overloaded enumeration literal is not determined form the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p07n01i00221arch;
|
gpl-2.0
|
ad492b943170c4104c27e656df0debd8
| 0.664426 | 3.657787 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/sr2940/GCD.vhd
| 3 | 5,298 |
-- module GCD where
--
--
-- $wmygcd::*Int# -> *Int# -> *Int#
-- $wmygcd ww ww1 =
-- let wild::GHC.Types.Bool = (GHC.Prim.==# ww ww1) in
-- case wild of :: *Int#
-- GHC.Types.False ->
-- let wild1::GHC.Types.Bool = (GHC.Prim.<# ww ww1) in
-- case wild1 of :: *Int#
-- GHC.Types.False -> ($wmygcd (GHC.Prim.-# ww ww1) ww1)
-- GHC.Types.True -> ($wmygcd ww (GHC.Prim.-# ww1 ww))
-- GHC.Types.True -> ww
--
-- mygcd::GHC.Types.Int -> GHC.Types.Int -> GHC.Types.Int
-- mygcd w w1 =
-- let w2::GHC.Types.Int = w in
-- case w2 of :: GHC.Types.Int
-- GHC.Types.I# ww::*Int# ->
-- let w3::GHC.Types.Int = w1 in
-- case w3 of :: GHC.Types.Int
-- GHC.Types.I# ww1::*Int# ->
-- let ww2::*Int# = ($wmygcd ww ww1) in
-- case ww2 of :: GHC.Types.Int DEFAULT -> (GHC.Types.I# ww2)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.\Prim\.all;
package \GCD\ is
end \GCD\;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.\Prim\.all;
use work.\GCD\.all;
entity \$wmygcd\ is
port (clk : in std_logic;
s1_call : in std_logic;
s1_ret : out std_logic;
s1_ww : in \Int#\;
s1_ww1 : in \Int#\;
res : out \Int#\);
end entity;
architecture rtl of \$wmygcd\ is
signal tail_call : std_logic;
signal tail_ww : \Int#\;
signal tail_ww1 : \Int#\;
signal core_call : std_logic;
signal core_ret : std_logic;
signal core_ww : \Int#\;
signal core_ww1 : \Int#\;
signal s1_act : std_logic;
signal s1_wait : std_logic;
signal s1_saved_ww : \Int#\;
signal s1_saved_ww1 : \Int#\;
begin
process (core_call, core_ww, core_ww1)
variable wild : \GHC.Types.Bool\;
variable wild1 : \GHC.Types.Bool\;
variable ww : \Int#\;
variable ww1 : \Int#\;
begin
ww := core_ww;
ww1 := core_ww1;
wild := \GHC.Prim.==#\(ww, ww1);
if \is_GHC.Types.False\(wild) then
wild1 := \GHC.Prim.<#\(ww, ww1);
if \is_GHC.Types.False\(wild1) then
res <= \$wmygcd\(\GHC.Prim.-#\(ww, ww1), ww1);
elsif \is_GHC.Types.True\(wild1) then
res <= \$wmygcd\(ww, \GHC.Prim.-#\(ww1, ww));
end if;
elsif \is_GHC.Types.True\(wild) then res <= ww;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
core_call <= '0';
if s1_call = '1' then
s1_wait <= '1';
s1_saved_ww <= s1_ww;
s1_saved_ww1 <= s1_ww1;
end if;
if tail_call = '1' then
core_call <= '1';
core_ww <= tail_ww;
core_ww1 <= tail_ww1;
elsif core_ret = '1' or s1_act = '1' then
s1_act <= '0';
if s1_wait = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_ww <= s1_saved_ww;
core_ww1 <= s1_saved_ww1;
elsif s1_call = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_ww <= s1_ww;
core_ww1 <= s1_ww1;
end if;
end if;
end if;
end process;
s1_ret <= core_ret and s1_act;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.\Prim\.all;
use work.\GCD\.all;
entity mygcd is
port (clk : in std_logic;
s1_call : in std_logic;
s1_ret : out std_logic;
s1_w : in \GHC.Types.Int\;
s1_w1 : in \GHC.Types.Int\;
res : out \GHC.Types.Int\);
end entity;
architecture rtl of mygcd is
signal tail_call : std_logic;
signal tail_w : \GHC.Types.Int\;
signal tail_w1 : \GHC.Types.Int\;
signal core_call : std_logic;
signal core_ret : std_logic;
signal core_w : \GHC.Types.Int\;
signal core_w1 : \GHC.Types.Int\;
signal s1_act : std_logic;
signal s1_wait : std_logic;
signal s1_saved_w : \GHC.Types.Int\;
signal s1_saved_w1 : \GHC.Types.Int\;
begin
process (core_call, core_w, core_w1)
variable w2 : \GHC.Types.Int\;
variable ww : \Int#\;
variable w3 : \GHC.Types.Int\;
variable ww1 : \Int#\;
variable ww2 : \Int#\;
variable w : \GHC.Types.Int\;
variable w1 : \GHC.Types.Int\;
begin
w := core_w;
w1 := core_w1;
w2 := w;
if \is_GHC.Types.I#\(w2) then
\expand_GHC.Types.I#\(w2, ww);
w3 := w1;
if \is_GHC.Types.I#\(w3) then
\expand_GHC.Types.I#\(w3, ww1);
ww2 := \$wmygcd\(ww, ww1);
res <= \GHC.Types.I#\(ww2);
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
core_call <= '0';
if s1_call = '1' then
s1_wait <= '1';
s1_saved_w <= s1_w;
s1_saved_w1 <= s1_w1;
end if;
if tail_call = '1' then
core_call <= '1';
core_w <= tail_w;
core_w1 <= tail_w1;
elsif core_ret = '1' or s1_act = '1' then
s1_act <= '0';
if s1_wait = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_w <= s1_saved_w;
core_w1 <= s1_saved_w1;
elsif s1_call = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_w <= s1_w;
core_w1 <= s1_w1;
end if;
end if;
end if;
end process;
s1_ret <= core_ret and s1_act;
end architecture;
|
gpl-2.0
|
1e2a4f493a9cb4dbc7a79936b1124f27
| 0.521895 | 2.730928 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/perf02/sub_143.vhd
| 3 | 1,829 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_143 is
port (
output : out std_logic_vector(63 downto 0);
lt : out std_logic;
le : out std_logic;
sign : in std_logic;
gt : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end sub_143;
architecture augh of sub_143 is
signal carry_inA : std_logic_vector(65 downto 0);
signal carry_inB : std_logic_vector(65 downto 0);
signal carry_res : std_logic_vector(65 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(64 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(63) & in_b(63) & carry_res(64);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "001" or msb_abr = "111") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011" or msb_abr = "111") else
'0';
gt <= not(tmp_le);
lt <= not(tmp_ge);
le <= tmp_le;
end architecture;
|
gpl-2.0
|
e629c09a6f781a45328c71d0d7013de8
| 0.620011 | 2.554469 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/example_entity.vhd
| 4 | 2,001 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity example_entity is
end entity example_entity;
-- end not in book
architecture contrived of example_entity is
constant sig_width : positive := 16;
signal s1, s2, s3 : bit_vector (0 to sig_width - 1);
signal sel : bit;
-- . . .
begin
mux : block is
generic ( width : positive );
generic map ( width => sig_width );
port ( d0, d1 : in bit_vector(0 to width - 1);
y : out bit_vector(0 to width - 1);
sel : in bit);
port map ( d0 => s1, d1=> s2, y => s3, sel => sel );
constant zero : bit_vector(0 to width - 1) := ( others => '0' );
signal gated_d0, gated_d1 : bit_vector(0 to width - 1);
begin
gated_d0 <= d0 when sel = '0' else zero;
gated_d1 <= d1 when sel = '1' else zero;
y <= gated_d0 or gated_d1;
end block mux;
-- . . .
-- not in book
stimulus : process is
begin
s1 <= X"1111"; s2 <= X"2222"; sel <= '0'; wait for 10 ns;
s1 <= X"0101"; wait for 10 ns;
s2 <= X"0202"; wait for 10 ns;
sel <= '1'; wait for 10 ns;
s1 <= X"0001"; wait for 10 ns;
s2 <= X"0002"; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture contrived;
|
gpl-2.0
|
f0999ad7efb34b3511a41bf1039de132
| 0.633183 | 3.403061 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1363.vhd
| 4 | 6,577 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1363.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01363ent IS
END c08s05b00x00p03n01i01363ent;
ARCHITECTURE c08s05b00x00p03n01i01363arch OF c08s05b00x00p03n01i01363ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_rec3 : st_rec3 := c_st_rec3_1 ;
--
BEGIN
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2));
assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01363"
severity NOTE;
assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01363 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01363arch;
|
gpl-2.0
|
c4ba1e1f034d2ccd6a72c50f0d00d0f8
| 0.583701 | 2.933541 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/util/clock_duty.vhd
| 4 | 1,340 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- This digital clock allows user to specify the duty cycle using
-- the parameters "on_time" and "off_time"
library ieee; use ieee.std_logic_1164.all;
entity clock_duty is
generic ( on_time : time := 20 us;
off_time : time := 19.98 ms );
port ( clock_out : out std_logic := 'Z' );
end entity clock_duty;
architecture ideal of clock_duty is
begin
process
begin
wait for 1 us;
clock_out <= '1';
wait for on_time;
clock_out <= '0';
wait for off_time;
end process;
end architecture ideal;
|
gpl-2.0
|
87ba54cae597560d9cfb69535dc7a3a4
| 0.697015 | 3.839542 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2882.vhd
| 4 | 2,377 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2882.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p07n01i02882ent IS
procedure proc2(constant flag:in integer; variable ret:inout integer);
procedure proc3(constant flag:in integer; variable ret:inout integer);
procedure proc2(constant flag:in integer; variable ret:inout integer) is
begin
if (flag = 0) then
ret:= -1;
else
proc3((flag-1),ret);
end if;
ret:= ret + 1;
end proc2;
procedure proc3(constant flag:in integer; variable ret:inout integer) is
begin
if (flag = 0) then
ret:= -1;
else
proc2((flag-1),ret);
end if;
ret:= ret + 1;
end proc3;
END c02s01b00x00p07n01i02882ent;
ARCHITECTURE c02s01b00x00p07n01i02882arch OF c02s01b00x00p07n01i02882ent IS
BEGIN
TESTING: PROCESS
variable x:integer;
BEGIN
x:=99;
assert (x=99) report "Initialization of integer variables incorrect"
severity failure;
proc2(3,x);
assert NOT( x=3 )
report "***PASSED TEST: c02s01b00x00p07n01i02882"
severity NOTE;
assert ( x=3 )
report "***FAILED TEST: c02s01b00x00p07n01i02882 - Procedures resursion call test incorrect (A-B-A type)."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p07n01i02882arch;
|
gpl-2.0
|
66c2b02ce6c245f69d0d633ab10de06d
| 0.663021 | 3.651306 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd
| 3 | 98,836 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo;
architecture rudder_servo of rudder_servo is
-- Component declarations
-- Signal declarations
terminal error : electrical;
terminal ll_in : electrical;
terminal ll_out : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
servo_limiter : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => ll_out,
output => servo_out
);
lead_lag : entity work.lead_lag_e(simple)
generic map(
k => 400.0,
f1 => 5.0,
f2 => 2000.0
)
port map(
input => ll_in,
output => ll_out
);
end rudder_servo;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
-- w2 == w1*ratio;
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Constant Voltage Source (Includes Frequency Domain settings)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY v_constant IS
-- Initialize parameters
GENERIC (
level : VOLTAGE; -- Constant voltage value (V)
ac_mag : VOLTAGE := 1.0; -- AC magnitude (V)
ac_phase : real := 0.0); -- AC phase (degrees)
-- Define ports as electrical terminals
PORT (
TERMINAL pos, neg : ELECTRICAL);
END ENTITY v_constant;
-- Ideal Architecture (I = constant)
ARCHITECTURE ideal OF v_constant IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH pos TO neg;
-- Declare quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
v == level;
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical sinusoidal voltage source (stick.vhd)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY stick IS
-- Initialize parameters
GENERIC (
freq : real; -- frequency, [Hertz]
amplitude : real; -- amplitude, [Volt]
phase : real := 0.0; -- initial phase, [Degree]
offset : real := 0.0; -- DC value, [Volt]
df : real := 0.0; -- damping factor, [1/second]
ac_mag : real := 1.0; -- AC magnitude, [Volt]
ac_phase : real := 0.0); -- AC phase, [Degree]
-- Define ports as electrical terminals
PORT (
TERMINAL v_out : ELECTRICAL);
END ENTITY stick;
-- Ideal Architecture
ARCHITECTURE ideal OF stick IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
-- Declare Quantity for Phase in radians (calculated below)
QUANTITY phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity RF_xmtr_rcvr is
generic (td : time := 0ns);
port
(
tdm_in : in std_logic ;
tdm_out : out std_logic
);
end RF_xmtr_rcvr;
architecture behavioral of RF_xmtr_rcvr is
begin
tdm_out <= tdm_in after td;
end;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Simple Digital-Controlled Two-position Switch Model
-- Switch position 1 ('0') or switch position 2 ('1')
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
ENTITY switch_dig_2in is
GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance
r_closed : RESISTANCE := 0.001; -- Closed switch resistance
trans_time : real := 0.00001); -- Transition time to each position
PORT (sw_state : in std_logic; -- Digital control input
TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output
END ENTITY switch_dig_2in;
ARCHITECTURE ideal OF switch_dig_2in IS
-- CONSTANT log_r_open : real := log10(r_open);
-- CONSTANT log_r_closed : real := log10(r_closed);
-- SIGNAL r_sig1 : RESISTANCE := log_r_closed; -- Variable to accept switch resistance
-- SIGNAL r_sig2 : RESISTANCE := log_r_open; -- Variable to accept switch resistance
SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance
SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance
QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out
QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out
QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out
QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out
BEGIN
PROCESS (sw_state) -- Sensitivity to digital control input
BEGIN
IF (sw_state'event AND sw_state = '0') THEN -- Close sig1, open sig2
r_sig1 <= r_closed;
r_sig2 <= r_open;
ELSIF (sw_state'event AND sw_state = '1') THEN -- Open sig1, close sig2
r_sig1 <= r_open;
r_sig2 <= r_closed;
END IF;
END PROCESS;
r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
v1 == r1*i1; -- Apply Ohm's law to in1
v2 == r2*i2; -- Apply Ohm's law to in2
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Digital clock with 50% duty cycle
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clock IS
GENERIC (
period : time); -- Clock period
PORT (
clk_out : OUT std_logic);
END ENTITY clock;
ARCHITECTURE ideal OF clock IS
BEGIN
-- clock process
process
begin
clk_out <= '0';
wait for period/2;
clk_out <= '1';
wait for period/2;
end process;
END ARCHITECTURE ideal;
--
-- This digital clock allows user to specify the duty cycle using
-- the parameters "on_time" and "off_time"
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
ENTITY clock_duty IS
GENERIC (
on_time : time := 20 us;
off_time : time := 19.98 ms
);
PORT (
clock_out : OUT std_logic := '0');
END ENTITY clock_duty;
ARCHITECTURE ideal OF clock_duty IS
BEGIN
-- clock process
process
begin
clock_out <= '1';
wait for on_time;
clock_out <= '0';
wait for off_time;
end process;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rc_clk is
port(
clk_100k : out std_logic;
clk_6K : out std_logic;
clk_50 : out std_logic
);
end rc_clk;
architecture rc_clk of rc_clk is
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.clock(ideal)
generic map(
period => 10us
)
port map(
CLK_OUT => clk_100k
);
XCMP2 : entity work.clock(ideal)
generic map(
period => 150us
)
port map(
CLK_OUT => clk_6K
);
clk_50Hz : entity work.clock_duty(ideal)
generic map(
on_time => 20 us,
off_time => 19.98 ms
)
port map(
CLOCK_OUT => clk_50
);
end rc_clk;
--
-- This model counts the number of input clock transitions and outputs
-- a '1' when this number equals the value of the user-defined constant 'count'
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity bit_cnt is
generic (
count : integer -- User-defined value to count up to
);
port
(
bit_in : in std_logic ;
clk : in std_logic ;
dly_out : out std_logic
);
end bit_cnt;
architecture behavioral of bit_cnt is
begin
serial_clock : process is
begin
wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H');
FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions
wait until clk'event AND (clk = '1' OR clk = 'H');
END LOOP ;
dly_out <= '1'; -- After count is reached, set output high
wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L');
dly_out <= '0'; -- Reset output to '0' on next clock input
end process serial_clock;
end;
--
--//////////////////////////////////////////////////////////////////
-- NOTE: This is an intermediate file for HDL inspection only.
-- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach1.sdg.
-- Generated by sde2hdl version 16.1.0.2
--//////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.all;
USE IEEE_proposed.mechanical_systems.all;
ENTITY state_mach1 IS
PORT (
a2d_eoc : IN std_logic;
clk_50 : IN std_logic;
clk_100k : IN std_logic;
clk_6k : IN std_logic;
ser_done : IN std_logic;
ch_sel : OUT std_logic;
frm_gen : OUT std_logic;
a2d_oe : OUT std_logic;
a2d_start : OUT std_logic;
p2s_oe : OUT std_logic;
p2s_load : OUT std_logic;
parity_oe : OUT std_logic;
ser_cnt : OUT std_logic;
p2s_clr : OUT std_logic);
END state_mach1;
ARCHITECTURE state_diagram OF state_mach1 IS
ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2
, load, ad_ch2, delay);
SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1;
SIGNAL FB_frm_gen : std_logic;
SIGNAL FB_p2s_load : std_logic;
SIGNAL FB_ch_sel : std_logic;
BEGIN
frm_gen <= FB_frm_gen ;
p2s_load <= FB_p2s_load ;
ch_sel <= FB_ch_sel ;
sm1:
PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel)
BEGIN
CASE CS_state_mach1_sm1 IS
WHEN V_begin =>
FB_frm_gen <= ('1');
a2d_start <= ('0');
a2d_oe <= ('0');
FB_p2s_load <= ('0');
p2s_clr <= ('0');
p2s_oe <= ('0');
FB_ch_sel <= ('0');
parity_oe <= ('0');
ser_cnt <= ('0');
IF ((FB_frm_gen = '1')) THEN
NS_state_mach1_sm1 <= frm_rd;
ELSE
NS_state_mach1_sm1 <= V_begin;
END IF;
WHEN frm_rd =>
FB_p2s_load <= ('1');
IF ((FB_p2s_load = '1')) THEN
NS_state_mach1_sm1 <= ser_oe;
ELSE
NS_state_mach1_sm1 <= frm_rd;
END IF;
WHEN ser_oe =>
p2s_oe <= ('1');
FB_frm_gen <= ('0');
FB_p2s_load <= ('0');
ser_cnt <= ('1');
IF ((ser_done = '1')) THEN
NS_state_mach1_sm1 <= ch1;
ELSE
NS_state_mach1_sm1 <= ser_oe;
END IF;
WHEN ch1 =>
p2s_oe <= ('0');
FB_ch_sel <= ('0');
a2d_start <= ('1');
ser_cnt <= ('0');
IF ((a2d_eoc = '1')) THEN
NS_state_mach1_sm1 <= data_en;
ELSE
NS_state_mach1_sm1 <= ch1;
END IF;
WHEN data_en =>
a2d_start <= ('0');
a2d_oe <= ('1');
parity_oe <= ('1');
NS_state_mach1_sm1 <= load;
WHEN tdm_oe =>
a2d_oe <= ('0');
parity_oe <= ('0');
p2s_oe <= ('1');
FB_p2s_load <= ('0');
ser_cnt <= ('1');
IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN
NS_state_mach1_sm1 <= ch2;
ELSE
NS_state_mach1_sm1 <= tdm_oe;
END IF;
WHEN ch2 =>
p2s_oe <= ('0');
ser_cnt <= ('0');
FB_ch_sel <= ('1');
NS_state_mach1_sm1 <= delay;
WHEN load =>
FB_p2s_load <= ('1');
NS_state_mach1_sm1 <= tdm_oe;
WHEN ad_ch2 =>
a2d_start <= ('1');
IF ((a2d_eoc = '1')) THEN
NS_state_mach1_sm1 <= data_en;
ELSE
NS_state_mach1_sm1 <= ad_ch2;
END IF;
WHEN delay =>
NS_state_mach1_sm1 <= ad_ch2;
END CASE;
END PROCESS;
sm1_CTL:
PROCESS (clk_100k, clk_50)
BEGIN
IF (clk_100k'event AND clk_100k='1') THEN
IF (clk_50= '1' ) THEN
CS_state_mach1_sm1 <= V_begin;
ELSE
CS_state_mach1_sm1 <= NS_state_mach1_sm1;
END IF;
END IF;
END PROCESS;
END state_diagram;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sm_cnt is
port(
a2d_eoc : in std_logic;
clk_50 : in std_logic;
clk_100k : in std_logic;
clk_6k : in std_logic;
p2s_load : out std_logic;
p2s_oe : out std_logic;
parity_oe : out std_logic;
a2d_start : out std_logic;
a2d_oe : out std_logic;
frm_gen : out std_logic;
ch_sel : out std_logic;
p2s_clr : out std_logic
);
end sm_cnt;
architecture sm_cnt of sm_cnt is
-- Component declarations
-- Signal declarations
signal ser_done : std_logic;
signal serial_cnt : std_logic;
begin
-- Signal assignments
-- Component instances
bit_cnt1 : entity work.bit_cnt(behavioral)
generic map(
count => 15
)
port map(
bit_in => serial_cnt,
clk => clk_6k,
dly_out => ser_done
);
state_mach16 : entity work.state_mach1
port map(
ser_cnt => serial_cnt,
ch_sel => ch_sel,
frm_gen => frm_gen,
a2d_oe => a2d_oe,
a2d_start => a2d_start,
parity_oe => parity_oe,
p2s_oe => p2s_oe,
p2s_load => p2s_load,
p2s_clr => p2s_clr,
clk_6k => clk_6k,
clk_100k => clk_100k,
clk_50 => clk_50,
a2d_eoc => a2d_eoc,
ser_done => ser_done
);
end sm_cnt;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Analog to Digital Converter (Successive Aproximation Register) model with sar architecture (a2d_nbit.vhd)
--DESCRIPTION:
--
--This is a VHDL-AMS model of a simple analog to digital converter. The model
--describes the general behavior of A/D converters for system level design and
--verification.
--The format of the digital output is binary coding.
--
--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
--
-- Use IEEE natures and packages
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity a2d_nbit is
generic (
Vmax: REAL := 5.0 ; -- ADC's maximum range
Nbits: INTEGER := 10 ; -- number bits in ADC's output
delay: TIME := 10 us -- ADC's conversion time
);
port (
signal start: in std_logic ; -- Start signal
signal clk: in std_logic ; -- Strobe clock
signal oe: in std_logic ; -- Output enable
terminal ain: ELECTRICAL ; -- ADC's analog input terminal
signal eoc: out std_logic := '0' ; -- End Of Conversion pin
signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal
end entity a2d_nbit;
architecture sar of a2d_nbit is
type states is (input, convert, output) ; -- Three states of A2D Conversion
constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout
quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
begin
sa_adc: process
variable thresh: REAL := Vmax ; -- Threshold to test input voltage against
variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts
variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data
variable status: states := input ; -- Begin with "input" CASE
variable bit_cnt: integer := Nbits -1 ;
begin
CASE status is
when input => -- Read input voltages when start goes high
wait on start until start = '1' or start = 'H' ;
thresh := Vmax ;
Vtmp := Vin ;
eoc <= '0' ;
status := convert ; -- Go to convert state
when convert => -- Begin successive approximation conversion
thresh := thresh / 2.0 ; -- Get value of MSB
wait on clk until clk = '1' OR clk = 'H';
if Vtmp > thresh then
dtmp(bit_cnt) := '1' ;
Vtmp := Vtmp - thresh ;
else
dtmp(bit_cnt) := '0' ;
end if ;
bit_cnt := bit_cnt - 1 ;
if (bit_cnt + 1) < 1 then
status := output ; -- Go to output state
end if;
when output => -- Wait for output enable, then put data on output pins
eoc <= '1' after delay ;
wait on oe until oe = '1' OR oe = 'H' ;
FOR i in bit_range DOWNTO 0 LOOP
dout(i) <= dtmp(i) ;
END LOOP ;
wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low
FOR i in bit_range DOWNTO 0 LOOP
dout <= "ZZZZZZZZZZ" ;
END LOOP ;
bit_cnt := bit_range ;
status := input ; -- Set up for next conversion
END CASE ;
end process sa_adc ;
Iin == 0.0 ; -- Ideal input draws no current
end architecture sar ;
--
-- Parallel input/serial output shift register
-- With 4 trailing zeros
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity shift_reg is
generic ( td : time := 0 ns);
port
(
bus_in : in std_logic_vector ; -- Input bus
clk : in std_logic ; -- Shift clock
oe : in std_logic ; -- Output enable
ser_out : out std_logic := '0'; -- Output port
load : in std_logic ; -- Parallel input load
clr : in std_logic -- Clear register
);
end entity shift_reg;
architecture behavioral of shift_reg is
begin
control_proc : process
VARIABLE bit_val : std_logic_vector(11 downto 0); -- Default 12-bit input
begin
IF (clr = '1' OR clr = 'H') then
bit_val := "000000000000"; -- Set all input bits to zero
ELSE
wait until load'event AND (load = '1' OR load = 'H');
FOR i IN bus_in'high DOWNTO bus_in'low LOOP
bit_val(i) := bus_in(i) ; -- Transfer input data to variable
END LOOP ;
END IF;
wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled
FOR i IN bit_val'high DOWNTO bit_val'low LOOP
wait until clk'event AND (clk = '1' OR clk = 'H');
ser_out <= bit_val(i) ;
END LOOP ;
FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros
wait until clk'event AND (clk = '1' OR clk = 'H');
ser_out <= '0';
END LOOP;
END process;
end architecture behavioral;
--
-- This model generates a 12-bit data frame synchronization code
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity frame_gen is
port
(
oe : in std_logic := '0';
sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ");
end entity frame_gen;
architecture simple of frame_gen is
begin
enbl: PROCESS
BEGIN
WAIT ON OE;
IF OE = '1' THEN
sync_out <= "010101010101"; -- Sync code
ELSE
sync_out <= "ZZZZZZZZZZZZ";
END IF;
END PROCESS;
end architecture simple;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Two input XOR gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY xor2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY xor2;
ARCHITECTURE ideal OF xor2 IS
BEGIN
output <= in1 XOR in2 AFTER delay;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- level_set_tri.vhd
-- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z')
-- If OE = '0' set output to high impedance
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY level_set_tri IS
GENERIC (
logic_val : std_logic := 'Z');
PORT (
OE : IN std_logic;
level : OUT std_logic := 'Z');
END ENTITY level_set_tri;
-- Simple architecture
ARCHITECTURE ideal OF level_set_tri IS
BEGIN
oe_ctl: PROCESS
BEGIN
WAIT ON OE;
IF OE = '1' THEN
level <= logic_val;
ELSE
level <= 'Z';
END IF;
END PROCESS;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Simple Tri-state Buffer with delay time
-- If OE = 1, output = input after delay
-- If OE /= 1, output = Z after delay
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY buffer_tri IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
input : IN std_logic;
OE : IN std_logic;
output : OUT std_logic);
END ENTITY buffer_tri;
ARCHITECTURE ideal OF buffer_tri IS
BEGIN
oe_ctl: PROCESS
BEGIN
WAIT ON OE, input;
IF OE = '1' THEN
output <= input AFTER delay;
ELSE
output <= 'Z' AFTER delay;
END IF;
END PROCESS;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- ideal one bit D/A converter
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY d2a_bit IS
GENERIC (vlow : real :=0.0; -- output high voltage
vhigh : real :=5.0); -- output low voltage
PORT (D : IN std_logic; -- digital (std_logic) intout
TERMINAL A : electrical); -- analog (electrical) output
END ENTITY d2a_bit;
ARCHITECTURE ideal OF d2a_bit IS
QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF;
SIGNAL vin : real := 0.0;
BEGIN
vin <= vhigh WHEN D = '1' ELSE vlow;
-- Use 'RAMP for discontinuous signal
vout == vin'RAMP(1.0e-9);
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity parity_gen is
port(
parity : in std_logic_vector(1 to 10);
oe : in std_logic;
parity_out : out std_logic_vector(0 to 11)
);
end parity_gen;
architecture parity_gen of parity_gen is
-- Component declarations
-- Signal declarations
terminal par_bit_gen_a : electrical;
signal XSIG010002 : std_logic;
signal XSIG010003 : std_logic;
signal XSIG010004 : std_logic;
signal XSIG010005 : std_logic;
signal XSIG010006 : std_logic;
signal XSIG010007 : std_logic;
signal XSIG010008 : std_logic;
signal XSIG010009 : std_logic;
signal XSIG010098 : std_logic;
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.xor2(ideal)
port map(
in1 => parity(1),
in2 => parity(2),
output => XSIG010002
);
XCMP2 : entity work.xor2(ideal)
port map(
in1 => parity(3),
in2 => parity(4),
output => XSIG010003
);
XCMP3 : entity work.xor2(ideal)
port map(
in1 => parity(5),
in2 => parity(6),
output => XSIG010004
);
XCMP4 : entity work.xor2(ideal)
port map(
in1 => parity(7),
in2 => parity(8),
output => XSIG010005
);
XCMP5 : entity work.xor2(ideal)
port map(
in1 => parity(9),
in2 => parity(10),
output => XSIG010008
);
XCMP6 : entity work.xor2(ideal)
port map(
in1 => XSIG010002,
in2 => XSIG010003,
output => XSIG010006
);
XCMP7 : entity work.xor2(ideal)
port map(
in1 => XSIG010004,
in2 => XSIG010005,
output => XSIG010007
);
XCMP8 : entity work.xor2(ideal)
port map(
in1 => XSIG010006,
in2 => XSIG010007,
output => XSIG010009
);
XCMP9 : entity work.xor2(ideal)
port map(
in1 => XSIG010009,
in2 => XSIG010008,
output => XSIG010098
);
XCMP18 : entity work.level_set_tri(ideal)
generic map(
logic_val => '1'
)
port map(
level => parity_out(11),
oe => oe
);
XCMP19 : entity work.buffer_tri(ideal)
port map(
input => parity(1),
output => parity_out(1),
oe => oe
);
XCMP20 : entity work.buffer_tri(ideal)
port map(
input => parity(2),
output => parity_out(2),
oe => oe
);
XCMP21 : entity work.buffer_tri(ideal)
port map(
input => parity(3),
output => parity_out(3),
oe => oe
);
XCMP22 : entity work.buffer_tri(ideal)
port map(
input => parity(4),
output => parity_out(4),
oe => oe
);
XCMP23 : entity work.buffer_tri(ideal)
port map(
input => parity(5),
output => parity_out(5),
oe => oe
);
XCMP24 : entity work.buffer_tri(ideal)
port map(
input => parity(6),
output => parity_out(6),
oe => oe
);
XCMP25 : entity work.buffer_tri(ideal)
port map(
input => parity(7),
output => parity_out(7),
oe => oe
);
XCMP26 : entity work.buffer_tri(ideal)
port map(
input => parity(8),
output => parity_out(8),
oe => oe
);
XCMP27 : entity work.buffer_tri(ideal)
port map(
input => parity(9),
output => parity_out(9),
oe => oe
);
XCMP28 : entity work.buffer_tri(ideal)
port map(
input => parity(10),
output => parity_out(10),
oe => oe
);
XCMP29 : entity work.buffer_tri(ideal)
port map(
input => XSIG010098,
output => parity_out(0),
oe => oe
);
XCMP30 : entity work.d2a_bit(ideal)
port map(
D => XSIG010098,
A => par_bit_gen_a
);
end parity_gen;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tdm_encoder is
port(
clk : in std_logic;
p2s_oe : in std_logic;
p2s_load : in std_logic;
frm_gen : in std_logic;
parity_oe : in std_logic;
tdm_out : out std_logic;
p2s_clr : in std_logic;
a2d_data : in std_logic_vector(1 to 10)
);
end tdm_encoder;
architecture tdm_encoder of tdm_encoder is
-- Component declarations
-- Signal declarations
signal sync_par : std_logic_vector(0 to 11);
begin
-- Signal assignments
-- Component instances
p2s1 : entity work.shift_reg(behavioral)
port map(
bus_in => sync_par,
clk => clk,
oe => p2s_oe,
ser_out => tdm_out,
load => p2s_load,
clr => p2s_clr
);
sync_gen1 : entity work.frame_gen(simple)
port map(
oe => frm_gen,
sync_out => sync_par
);
par_gen1 : entity work.parity_gen
port map(
parity => a2d_data,
parity_out => sync_par,
oe => parity_oe
);
end tdm_encoder;
--
-- Manchester Encoder
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY menc_rsc IS
port ( dig_in : in STD_LOGIC; -- digital input
clk : in STD_LOGIC; -- TX internal clock
reset: in STD_LOGIC; -- not reset
-- bit_out : inout real); -- real output
bit_out : out std_logic); -- real output
END ENTITY menc_rsc;
ARCHITECTURE bhv OF menc_rsc IS
-- signal bhigh:real:= 1.0; -- bit encoding
-- signal blow:real:= -1.0; -- bit encoding
-- signal bnormal:real:=0.0; -- bit encoding
signal bit1:STD_LOGIC;
signal bhigh:std_logic:= '1'; -- bit encoding
signal blow:std_logic:= '0'; -- bit encoding
begin
-- proc1: process (dig_in, clk, bit1,bhigh,blow,bnormal)
proc1: process (dig_in, clk, bit1,bhigh,blow)
begin
if (reset = '1') then
bit1 <= '0';
else
bit1 <= dig_in XOR clk; -- manchester encoding
end if;
if (bit1 = '1') then
bit_out <= bhigh;
else
bit_out <= blow;
-- elsif bit1 = '0' then
-- bit_out <= blow;
-- else
-- bit_out <= bnormal;
end if;
end process;
end architecture bhv;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity Digitize_Encode_Man is
port(
tdm_out : out std_logic;
terminal ch1_in : electrical;
terminal ch2_in : electrical
);
end Digitize_Encode_Man;
architecture Digitize_Encode_Man of Digitize_Encode_Man is
-- Component declarations
-- Signal declarations
terminal a2d_ana_in : electrical;
signal ch_bus : std_logic_vector(1 to 10);
signal clk_6K : std_logic;
signal dig_in : std_logic;
signal frm_gen_ctl : std_logic;
signal p2s_clr : std_logic;
signal p2s_load : std_logic;
signal p2s_oe : std_logic;
signal par_oe : std_logic;
signal reset : std_logic;
signal reset_m : std_logic;
signal start_a2d1 : std_logic;
signal sw_ctl : std_logic;
signal XSIG010091 : std_logic;
signal XSIG010190 : std_logic;
signal XSIG010196 : std_logic;
begin
-- Signal assignments
-- Component instances
A_SWITCH1 : entity work.switch_dig_2in(ideal)
port map(
p_in1 => ch1_in,
p_out => a2d_ana_in,
sw_state => sw_ctl,
p_in2 => ch2_in
);
rc_clk2 : entity work.rc_clk
port map(
clk_50 => reset,
clk_6K => clk_6K,
clk_100k => XSIG010190
);
sm_xmtr1 : entity work.sm_cnt
port map(
clk_100k => XSIG010190,
a2d_start => start_a2d1,
a2d_eoc => XSIG010091,
p2s_oe => p2s_oe,
p2s_load => p2s_load,
ch_sel => sw_ctl,
frm_gen => frm_gen_ctl,
parity_oe => par_oe,
a2d_oe => XSIG010196,
clk_50 => reset,
clk_6k => clk_6K,
p2s_clr => p2s_clr
);
a2d1 : entity work.a2d_nbit(sar)
generic map(
Vmax => 4.8
)
port map(
dout => ch_bus,
ain => a2d_ana_in,
clk => XSIG010190,
start => start_a2d1,
eoc => XSIG010091,
oe => XSIG010196
);
tdm_enc1 : entity work.tdm_encoder
port map(
clk => clk_6K,
p2s_oe => p2s_oe,
tdm_out => dig_in,
p2s_load => p2s_load,
a2d_data => ch_bus,
frm_gen => frm_gen_ctl,
parity_oe => par_oe,
p2s_clr => p2s_clr
);
menc_rsc3 : entity work.menc_rsc(bhv)
port map(
dig_in => dig_in,
clk => clk_6K,
reset => reset_m,
bit_out => tdm_out
);
XCMP90 : entity work.clock_duty(ideal)
generic map(
off_time => 19.98 sec
)
port map(
CLOCK_OUT => reset_m
);
end Digitize_Encode_Man;
--
-------------------------------------------------------------------------------
-- Second Order Lowpass filter
--
-- Transfer Function:
--
-- w1*w2
-- H(s) = k * ----------------
-- (s + w1)(s + w2)
--
-- DC Gain = k
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lpf_2_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (pole)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lpf_2_e;
architecture simple of lpf_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
-- constant num : real := k;
constant num : real_vector := (0 => w1*w2*k); -- 0=> is needed to give
-- index when only a single
-- element is used.
constant den : real_vector := (w1*w2, w1+w2, 1.0);
begin
vin_temp == vin; -- intermediate variable (vin) req'd for now
vout == vin_temp'ltf(num, den);
end architecture simple;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Two input AND gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY and2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY and2;
ARCHITECTURE ideal OF and2 IS
BEGIN
output <= in1 AND in2 AFTER delay;
END ARCHITECTURE ideal;
--
-- D Flip Flop with reset (negative edge triggered)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY d_latch_n_edge_rst IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
data, clk : IN std_logic;
q : OUT std_logic := '0';
qn : OUT std_logic := '1';
rst : IN std_logic := '0'); -- reset
END ENTITY d_latch_n_edge_rst ;
ARCHITECTURE behav OF d_latch_n_edge_rst IS
BEGIN
data_in : PROCESS(clk, rst) IS
BEGIN
IF clk = '0' AND clk'event AND rst /= '1' THEN
q <= data AFTER delay;
qn <= NOT data AFTER delay;
ELSIF rst = '1' THEN
q <= '0';
qn <= '1';
END IF;
END PROCESS data_in; -- End of process data_in
END ARCHITECTURE behav;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity counter_12 is
port(
cnt : out std_logic_vector(0 to 11);
reset : in std_logic;
enable : in std_logic;
clk : in std_logic
);
end counter_12;
architecture counter_12 of counter_12 is
-- Component declarations
-- Signal declarations
signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11);
signal XSIG010078 : std_logic;
signal XSIG010081 : std_logic;
signal XSIG010083 : std_logic;
signal XSIG010085 : std_logic;
signal XSIG010087 : std_logic;
signal XSIG010101 : std_logic;
signal XSIG010102 : std_logic;
signal XSIG010103 : std_logic;
signal XSIG010104 : std_logic;
signal XSIG010115 : std_logic;
signal XSIG010116 : std_logic;
signal XSIG010117 : std_logic;
signal XSIG010132 : std_logic;
begin
-- Signal assignments
cnt(0) <= cdb2vhdl_tmp_1(0);
cnt(1) <= cdb2vhdl_tmp_1(1);
cnt(2) <= cdb2vhdl_tmp_1(2);
cnt(3) <= cdb2vhdl_tmp_1(3);
cnt(4) <= cdb2vhdl_tmp_1(4);
cnt(5) <= cdb2vhdl_tmp_1(5);
cnt(6) <= cdb2vhdl_tmp_1(6);
cnt(7) <= cdb2vhdl_tmp_1(7);
cnt(8) <= cdb2vhdl_tmp_1(8);
cnt(9) <= cdb2vhdl_tmp_1(9);
cnt(10) <= cdb2vhdl_tmp_1(10);
cnt(11) <= cdb2vhdl_tmp_1(11);
-- Component instances
XCMP92 : entity work.and2(ideal)
port map(
in1 => clk,
in2 => enable,
output => XSIG010132
);
XCMP93 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => XSIG010132,
DATA => XSIG010078,
QN => XSIG010078,
Q => cdb2vhdl_tmp_1(0),
RST => reset
);
XCMP94 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(0),
DATA => XSIG010081,
QN => XSIG010081,
Q => cdb2vhdl_tmp_1(1),
RST => reset
);
XCMP95 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(1),
DATA => XSIG010083,
QN => XSIG010083,
Q => cdb2vhdl_tmp_1(2),
RST => reset
);
XCMP96 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(2),
DATA => XSIG010085,
QN => XSIG010085,
Q => cdb2vhdl_tmp_1(3),
RST => reset
);
XCMP97 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(3),
DATA => XSIG010087,
QN => XSIG010087,
Q => cdb2vhdl_tmp_1(4),
RST => reset
);
XCMP98 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(4),
DATA => XSIG010101,
QN => XSIG010101,
Q => cdb2vhdl_tmp_1(5),
RST => reset
);
XCMP99 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(5),
DATA => XSIG010102,
QN => XSIG010102,
Q => cdb2vhdl_tmp_1(6),
RST => reset
);
XCMP100 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(6),
DATA => XSIG010103,
QN => XSIG010103,
Q => cdb2vhdl_tmp_1(7),
RST => reset
);
XCMP101 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(7),
DATA => XSIG010104,
QN => XSIG010104,
Q => cdb2vhdl_tmp_1(8),
RST => reset
);
XCMP102 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(8),
DATA => XSIG010115,
QN => XSIG010115,
Q => cdb2vhdl_tmp_1(9),
RST => reset
);
XCMP103 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(9),
DATA => XSIG010116,
QN => XSIG010116,
Q => cdb2vhdl_tmp_1(10),
RST => reset
);
XCMP104 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(10),
DATA => XSIG010117,
QN => XSIG010117,
Q => cdb2vhdl_tmp_1(11),
RST => reset
);
end counter_12;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- ideal one bit A/D converter
LIBRARY IEEE;
USE IEEE.math_real.ALL;
USE IEEE.std_logic_1164.ALL;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
ENTITY a2d_bit IS
GENERIC (
thres : real := 2.5); -- Threshold to determine logic output
PORT (
TERMINAL a : electrical; -- analog input
SIGNAL d : OUT std_logic); -- digital (std_logic) output
END ENTITY a2d_bit;
ARCHITECTURE ideal OF a2d_bit IS
QUANTITY vin ACROSS a;
BEGIN -- threshold
-- Process needed to detect threshold crossing and assign output (d)
PROCESS (vin'ABOVE(thres)) IS
BEGIN -- PROCESS
IF vin'ABOVE(thres) THEN
d <= '1';
ELSE
d <= '0';
END IF;
END PROCESS;
END ideal;
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Digital clock with 50% duty cycle and enable pin
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clock_en IS
GENERIC (
pw : time); -- Clock pulse width
PORT (
enable : IN std_logic ;
clock_out : INOUT std_logic := '0');
END ENTITY clock_en;
ARCHITECTURE ideal OF clock_en IS
BEGIN
-- clock process
process (clock_out, enable) is
begin
if clock_out = '0' AND enable = '1' THEN
clock_out <= '1' after pw, '0' after 2*pw;
end if;
end process;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Inverter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY inverter IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
input : IN std_logic;
output : OUT std_logic);
END ENTITY inverter;
ARCHITECTURE ideal OF inverter IS
BEGIN
output <= NOT input AFTER delay;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Two input OR gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY or2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY or2;
ARCHITECTURE ideal OF or2 IS
BEGIN
output <= in1 OR in2 AFTER delay;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
ENTITY d2a_nbit IS
GENERIC (
vmax : real := 5.0; -- High output
vmin : real := 0.0; -- Low output
high_bit : integer := 9; -- High end of bit range for D/A
low_bit : integer := 0); -- Low end of bit range for D/A
PORT (
SIGNAL bus_in : IN STD_LOGIC_VECTOR; -- variable width vector input
SIGNAL latch : IN STD_LOGIC;
TERMINAL ana_out : electrical); -- analog output
END ENTITY d2a_nbit ;
ARCHITECTURE behavioral OF d2a_nbit IS
SIGNAL sout : real := 0.0;
QUANTITY vout across iout through ana_out TO electrical_ref;
BEGIN -- ARCHITECTURE behavioral
proc : PROCESS
VARIABLE v_sum : real; -- Sum of voltage contribution from each bit
VARIABLE delt_v : real; -- Represents the voltage value of each bit
BEGIN
WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high
v_sum := vmin;
delt_v := vmax - vmin;
FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions
delt_v := delt_v / 2.0;
IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN
v_sum := v_sum + delt_v;
END IF;
END LOOP;
sout <= v_sum;
END PROCESS;
vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels
END ARCHITECTURE behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity pw2ana is
port(
terminal ana_out : electrical;
terminal pw_in : electrical
);
end pw2ana;
architecture pw2ana of pw2ana is
-- Component declarations
-- Signal declarations
signal bus_servo : std_logic_vector(0 to 11);
signal XSIG010008 : std_logic;
signal XSIG010013 : std_logic;
signal XSIG010019 : std_logic;
signal XSIG010020 : std_logic;
signal XSIG010021 : std_logic;
signal XSIG010022 : std_logic;
begin
-- Signal assignments
-- Component instances
counter_rudder : entity work.counter_12
port map(
enable => XSIG010022,
cnt => bus_servo,
reset => XSIG010021,
clk => XSIG010008
);
XCMP3 : entity work.a2d_bit(ideal)
port map(
D => XSIG010022,
A => pw_in
);
clk_en_rudder : entity work.clock_en(ideal)
generic map(
pw => 500ns
)
port map(
CLOCK_OUT => XSIG010008,
enable => XSIG010022
);
XCMP5 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => XSIG010022,
output => XSIG010013
);
XCMP8 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => XSIG010020,
output => XSIG010021
);
XCMP9 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => XSIG010022,
output => XSIG010019
);
or_rudder : entity work.or2(ideal)
port map(
in1 => XSIG010022,
in2 => XSIG010019,
output => XSIG010020
);
XCMP11 : entity work.d2a_nbit(behavioral)
generic map(
vmax => 4.8,
high_bit => 9,
low_bit => 0
)
port map(
bus_in => bus_servo,
ana_out => ana_out,
latch => XSIG010013
);
end pw2ana;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang'above(ang_max) use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang'above(ang_min) use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-- 12-bit digital comparator model
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity dig_cmp is
port
(
eq : out std_logic := '0';
in1 : in std_logic_vector (0 to 11);
in2 : in std_logic_vector (0 to 11);
latch_in1 : in std_logic := '0'; -- Currently unused
latch_in2 : in std_logic := '0';
cmp : in std_logic := '0';
clk : in std_logic
);
end entity dig_cmp ;
architecture simple of dig_cmp is
begin
compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list
variable in2_hold : std_logic_vector (0 to 11) := "000000000000";
BEGIN
if latch_in2 = '1' then -- in2 data is latched and stored
in2_hold := in2;
end if;
if cmp = '1' then
if in1 = in2_hold then -- latched in2 checked against current in1
eq <= '0';
else eq <= '1';
end if;
end if;
END PROCESS;
end architecture simple;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical Resistor Model
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY resistor IS
-- Initialize parameters
GENERIC (
res : RESISTANCE); -- resistance (no initial value)
-- Define ports as electrical terminals
PORT (
TERMINAL p1, p2 : ELECTRICAL);
END ENTITY resistor;
-- Ideal Architecture (V = I*R)
ARCHITECTURE ideal OF resistor IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH p1 TO p2;
BEGIN
-- Characteristic equations
v == i*res;
END ARCHITECTURE ideal;
--
-- Set/reset flip flop
-- When S goes high, Q is set high until reset
-- When R goes high, Q is set low until set
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sr_ff is
port
(
S : in std_logic ;
R : in std_logic ;
Q : out std_logic
);
end sr_ff ;
architecture simple of sr_ff is
begin
set_reset: PROCESS(S, R) IS
BEGIN
-- assert S='1' nand R='1' -- Warning if both inputs are high
-- report "S and R are both active. Use with caution"
-- severity warning;
if S'event AND S = '1' then
Q <= '1';
end if;
if R'event AND R = '1' then
Q <= '0';
end if;
END PROCESS set_reset;
end;
--
--//////////////////////////////////////////////////////////////////
-- NOTE: This is an intermediate file for HDL inspection only.
-- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach_rcvr.sdg.
-- Generated by sde2hdl version 16.1.0.2
--//////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.all;
USE IEEE_proposed.mechanical_systems.all;
USE IEEE_proposed.fluidic_systems.all;
USE IEEE_proposed.thermal_systems.all;
USE IEEE_proposed.radiant_systems.all;
ENTITY state_mach_rcvr IS
PORT (
clk_50 : IN std_logic;
clk_100k : IN std_logic;
ser_done : IN std_logic;
par_det : IN std_logic;
frm_det : IN std_logic;
clk_6k : IN std_logic;
start_pulse : IN std_logic;
dly_done : IN std_logic;
s2p_rst : OUT std_logic;
s2p_en : OUT std_logic;
cnt1_en : OUT std_logic;
cnt1_rst : OUT std_logic;
cmp1_ltch1 : OUT std_logic;
cmp1_ltch2 : OUT std_logic;
cnt2_en : OUT std_logic;
cnt2_rst : OUT std_logic;
cmp2_ltch1 : OUT std_logic;
cmp2_ltch2 : OUT std_logic;
da_latch : OUT std_logic;
ser_cnt : OUT std_logic;
dly_cnt : OUT std_logic;
par_oe : OUT std_logic);
END state_mach_rcvr;
ARCHITECTURE state_diagram OF state_mach_rcvr IS
ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt
, s_bit, par1, par2);
SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1;
BEGIN
sm1:
PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det)
BEGIN
CASE CS_state_mach_rcvr_sm1 IS
WHEN V_begin =>
cnt1_en <= ('0');
cnt1_rst <= ('1');
cmp1_ltch1 <= ('0');
cmp1_ltch2 <= ('0');
cnt2_en <= ('0');
cnt2_rst <= ('1');
cmp2_ltch1 <= ('0');
cmp2_ltch2 <= ('0');
s2p_en <= ('1');
s2p_rst <= ('0');
da_latch <= ('0');
ser_cnt <= ('0');
dly_cnt <= ('0');
par_oe <= ('0');
IF ((frm_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= s_bit;
ELSE
NS_state_mach_rcvr_sm1 <= V_begin;
END IF;
WHEN cnt =>
ser_cnt <= ('1');
cnt1_rst <= ('0');
cnt2_rst <= ('0');
IF ((ser_done = '1')) THEN
NS_state_mach_rcvr_sm1 <= par1;
ELSE
NS_state_mach_rcvr_sm1 <= cnt;
END IF;
WHEN ch1 =>
cmp1_ltch2 <= ('1');
ser_cnt <= ('0');
dly_cnt <= ('1');
IF (((start_pulse = '1') AND (dly_done = '1'))) THEN
NS_state_mach_rcvr_sm1 <= rst1;
ELSE
NS_state_mach_rcvr_sm1 <= ch1;
END IF;
WHEN rst1 =>
cmp1_ltch2 <= ('0');
ser_cnt <= ('1');
dly_cnt <= ('0');
par_oe <= ('0');
IF ((ser_done = '1')) THEN
NS_state_mach_rcvr_sm1 <= par2;
ELSE
NS_state_mach_rcvr_sm1 <= rst1;
END IF;
WHEN ch2 =>
cmp2_ltch2 <= ('1');
ser_cnt <= ('0');
da_latch <= ('1');
NS_state_mach_rcvr_sm1 <= rst2;
WHEN rst2 =>
cmp2_ltch2 <= ('0');
s2p_en <= ('0');
par_oe <= ('0');
da_latch <= ('0');
NS_state_mach_rcvr_sm1 <= cnt_cmp;
WHEN cnt_cmp =>
cnt1_en <= ('1');
cmp1_ltch1 <= ('1');
cnt2_en <= ('1');
cmp2_ltch1 <= ('1');
NS_state_mach_rcvr_sm1 <= rst_cnt;
WHEN rst_cnt =>
cnt1_en <= ('0');
cmp1_ltch1 <= ('0');
cnt2_en <= ('0');
cmp2_ltch1 <= ('0');
NS_state_mach_rcvr_sm1 <= rst_cnt;
WHEN s_bit =>
IF ((start_pulse = '1')) THEN
NS_state_mach_rcvr_sm1 <= cnt;
ELSE
NS_state_mach_rcvr_sm1 <= s_bit;
END IF;
WHEN par1 =>
par_oe <= ('1');
IF ((par_det = '0')) THEN
NS_state_mach_rcvr_sm1 <= ch1;
ELSIF ((par_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= rst1;
ELSE
NS_state_mach_rcvr_sm1 <= par1;
END IF;
WHEN par2 =>
par_oe <= ('1');
IF ((par_det = '0')) THEN
NS_state_mach_rcvr_sm1 <= ch2;
ELSIF ((par_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= rst2;
ELSE
NS_state_mach_rcvr_sm1 <= par2;
END IF;
END CASE;
END PROCESS;
sm1_CTL:
PROCESS (clk_100k, clk_50)
BEGIN
IF (clk_100k'event AND clk_100k='1') THEN
IF (clk_50= '1' ) THEN
CS_state_mach_rcvr_sm1 <= V_begin;
ELSE
CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1;
END IF;
END IF;
END PROCESS;
END state_diagram;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sm_cnt_rcvr is
port(
cmp1_ltch1 : out std_logic;
cmp2_ltch1 : out std_logic;
s2p_en : out std_logic;
s2p_rst : out std_logic;
frm_det : in std_logic;
par_det : in std_logic;
clk_100k : in std_logic;
clk_6k : in std_logic;
clk_50 : in std_logic;
start_pulse : in std_logic;
cnt1_en : out std_logic;
cnt1_rst : out std_logic;
cmp1_ltch2 : out std_logic;
cnt2_en : out std_logic;
cnt2_rst : out std_logic;
cmp2_ltch2 : out std_logic;
da_latch : out std_logic;
par_oe : out std_logic
);
end sm_cnt_rcvr;
architecture sm_cnt_rcvr of sm_cnt_rcvr is
-- Component declarations
-- Signal declarations
terminal dly_cnt_a : electrical;
terminal dly_done_a : electrical;
terminal ser_cnt_a : electrical;
terminal ser_done_a : electrical;
signal XSIG010001 : std_logic;
signal XSIG010002 : std_logic;
signal XSIG010145 : std_logic;
signal XSIG010146 : std_logic;
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.d2a_bit(ideal)
port map(
D => XSIG010001,
A => ser_cnt_a
);
XCMP2 : entity work.d2a_bit(ideal)
port map(
D => XSIG010002,
A => ser_done_a
);
bit_cnt3 : entity work.bit_cnt(behavioral)
generic map(
count => 2
)
port map(
bit_in => XSIG010145,
clk => clk_6k,
dly_out => XSIG010146
);
bit_cnt4 : entity work.bit_cnt(behavioral)
generic map(
count => 10
)
port map(
bit_in => XSIG010001,
clk => clk_6k,
dly_out => XSIG010002
);
XCMP8 : entity work.d2a_bit(ideal)
port map(
D => XSIG010145,
A => dly_cnt_a
);
XCMP9 : entity work.d2a_bit(ideal)
port map(
D => XSIG010146,
A => dly_done_a
);
state_mach_rcvr8 : entity work.state_mach_rcvr
port map(
clk_100k => clk_100k,
clk_50 => clk_50,
s2p_rst => s2p_rst,
s2p_en => s2p_en,
cnt1_en => cnt1_en,
cnt1_rst => cnt1_rst,
cmp1_ltch1 => cmp1_ltch1,
cmp1_ltch2 => cmp1_ltch2,
cnt2_en => cnt2_en,
cnt2_rst => cnt2_rst,
cmp2_ltch1 => cmp2_ltch1,
cmp2_ltch2 => cmp2_ltch2,
da_latch => da_latch,
ser_cnt => XSIG010001,
ser_done => XSIG010002,
par_det => par_det,
frm_det => frm_det,
clk_6k => clk_6k,
start_pulse => start_pulse,
dly_done => XSIG010146,
dly_cnt => XSIG010145,
par_oe => par_oe
);
end sm_cnt_rcvr;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- level_set.vhd
-- Set digital output "level" with parameter "logic_val" (default is '1')
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY level_set IS
GENERIC (
logic_val : std_logic := '1');
PORT (
level : OUT std_logic);
END ENTITY level_set;
-- Simple architecture
ARCHITECTURE ideal OF level_set IS
BEGIN
level <= logic_val;
END ARCHITECTURE ideal;
--
-- Serial to parallel data converter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity ser2par is
port
(
par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ";
clk : in std_logic ;
load_en : in std_logic ;
ser_in : in std_logic ;
reset : in std_logic
);
begin
end ser2par;
architecture a1 of ser2par is
BEGIN
sr_sm: PROCESS (load_en, clk, reset, ser_in)
BEGIN
if (reset = '1' and load_en = '1') then
par_out <= "000000000000"; -- Reset the parallel data out
elsif (clk'event and clk = '1') then
if (load_en ='1') then
-- The register will shift when load is enabled
-- and will shift at rising edge of clock
par_out(0) <= ser_in; -- Input data shifts into bit 0
par_out(1) <= par_out(0);
par_out(2) <= par_out(1);
par_out(3) <= par_out(2);
par_out(4) <= par_out(3);
par_out(5) <= par_out(4);
par_out(6) <= par_out(5);
par_out(7) <= par_out(6);
par_out(8) <= par_out(7);
par_out(9) <= par_out(8);
par_out(10) <= par_out(9);
par_out(11) <= par_out(10);
else
-- The otput data will not change
-- if load_en is not enabled
par_out <= "ZZZZZZZZZZZZ";
end if;
end if;
END PROCESS;
end;
--
-- This model ouputs a '1' when a specific bit pattern is encountered
-- Otherwise, it outputs a zero
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity frame_det is
port
(
bus_in : in std_logic_vector (0 to 11);
clk : in std_logic;
frm_bit : out std_logic := '0' -- Initialize output to zero
);
end entity frame_det;
architecture simple of frame_det is
begin
enbl: PROCESS (bus_in, clk) -- Sensitivity list
BEGIN
if bus_in = "010101010101" then -- This is the pre-defined bit pattern
if clk'event AND clk = '0' then -- Output updated synchronously
frm_bit <= '1';
end if;
else frm_bit <= '0';
end if;
END PROCESS;
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity parity_det is
port(
bus_in : in std_logic_vector(0 to 11);
par_bit : out std_logic;
oe : in std_logic
);
end parity_det;
architecture parity_det of parity_det is
-- Component declarations
-- Signal declarations
signal cdb2vhdl_tmp_1 : std_logic;
terminal par_bit_a : electrical;
signal XSIG010010 : std_logic;
signal XSIG010011 : std_logic;
signal XSIG010012 : std_logic;
signal XSIG010013 : std_logic;
signal XSIG010014 : std_logic;
signal XSIG010015 : std_logic;
signal XSIG010016 : std_logic;
signal XSIG010017 : std_logic;
signal XSIG010019 : std_logic;
signal XSIG010057 : std_logic;
begin
-- Signal assignments
par_bit <= cdb2vhdl_tmp_1;
-- Component instances
XCMP1 : entity work.xor2(ideal)
port map(
in1 => bus_in(1),
in2 => bus_in(2),
output => XSIG010010
);
XCMP2 : entity work.xor2(ideal)
port map(
in1 => bus_in(3),
in2 => bus_in(4),
output => XSIG010011
);
XCMP3 : entity work.xor2(ideal)
port map(
in1 => bus_in(5),
in2 => bus_in(6),
output => XSIG010012
);
XCMP4 : entity work.xor2(ideal)
port map(
in1 => bus_in(7),
in2 => bus_in(8),
output => XSIG010013
);
XCMP5 : entity work.xor2(ideal)
port map(
in1 => bus_in(9),
in2 => bus_in(10),
output => XSIG010016
);
XCMP6 : entity work.xor2(ideal)
port map(
in1 => XSIG010010,
in2 => XSIG010011,
output => XSIG010014
);
XCMP7 : entity work.xor2(ideal)
port map(
in1 => XSIG010012,
in2 => XSIG010013,
output => XSIG010015
);
XCMP8 : entity work.xor2(ideal)
port map(
in1 => XSIG010014,
in2 => XSIG010015,
output => XSIG010017
);
XCMP9 : entity work.xor2(ideal)
port map(
in1 => XSIG010017,
in2 => XSIG010016,
output => XSIG010019
);
XCMP10 : entity work.xor2(ideal)
port map(
in1 => XSIG010019,
in2 => bus_in(0),
output => XSIG010057
);
XCMP11 : entity work.d2a_bit(ideal)
port map(
D => cdb2vhdl_tmp_1,
A => par_bit_a
);
XCMP12 : entity work.and2(ideal)
port map(
in1 => oe,
in2 => XSIG010057,
output => cdb2vhdl_tmp_1
);
end parity_det;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TDM_Demux_dbg is
port(
s2p_en : in std_logic;
tdm_in : in std_logic;
clk_6k : in std_logic;
s2p_rst : in std_logic;
par_det : out std_logic;
frm_det : out std_logic;
da_latch : in std_logic;
par_oe : in std_logic;
data_bus : out std_logic_vector(1 to 10);
start_bit : out std_logic
);
end TDM_Demux_dbg;
architecture TDM_Demux_dbg of TDM_Demux_dbg is
-- Component declarations
-- Signal declarations
terminal d2a_out : electrical;
signal rcvr_bus : std_logic_vector(0 to 11);
begin
-- Signal assignments
data_bus(1) <= rcvr_bus(1);
data_bus(2) <= rcvr_bus(2);
data_bus(3) <= rcvr_bus(3);
data_bus(4) <= rcvr_bus(4);
data_bus(5) <= rcvr_bus(5);
data_bus(6) <= rcvr_bus(6);
data_bus(7) <= rcvr_bus(7);
data_bus(8) <= rcvr_bus(8);
data_bus(9) <= rcvr_bus(9);
data_bus(10) <= rcvr_bus(10);
start_bit <= rcvr_bus(0);
-- Component instances
s2p1 : entity work.ser2par(a1)
port map(
par_out => rcvr_bus,
clk => clk_6k,
load_en => s2p_en,
ser_in => tdm_in,
reset => s2p_rst
);
frm_det1 : entity work.frame_det(simple)
port map(
bus_in => rcvr_bus,
frm_bit => frm_det,
clk => clk_6k
);
par_det1 : entity work.parity_det
port map(
bus_in => rcvr_bus,
par_bit => par_det,
oe => par_oe
);
XCMP113 : entity work.d2a_nbit(behavioral)
generic map(
low_bit => 1,
high_bit => 10,
vmax => 4.8
)
port map(
bus_in => rcvr_bus(1 to 10),
ana_out => d2a_out,
latch => da_latch
);
end TDM_Demux_dbg;
--
-- Manchester Decoder with clock recovery using 8x referenced clock
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mdec_rsc is
-- port ( din: in real; -- real input
port ( din: in std_logic; -- real input
clk16x: in std_logic; -- 16x referenced clock
reset: in std_logic; -- not reset
bout: out std_logic := '0'; -- digital output
clk_out: inout std_logic := '0'); -- recovered clock
end entity mdec_rsc;
architecture bhv of mdec_rsc is
-- signal bhigh:real:= 1.0; -- bit decoding
-- signal blow:real:= -1.0; -- bit decoding
-- signal bnormal:real:=0.0; -- bit decoding
signal bhigh:std_logic:= '1'; -- bit decoding
signal blow:std_logic:= '0'; -- bit decoding
signal bout1:std_logic;
signal clk_div:std_logic_vector(3 downto 0):="0000"; -- clock counter
signal trans:std_logic; -- transisition trigger
begin
-- bit decoding
proc1: process (reset,din,clk16x)
begin
if (reset = '1') then
bout1 <= 'X';
elsif (clk16x'event and clk16x = '1') then
if (din = bhigh) then
bout1 <= '1';
elsif (din = blow) then
bout1 <= '0';
else
bout1 <= 'X';
end if;
end if;
end process;
-- clock counter
proc2: process (reset, clk16x, clk_div)
begin
if (reset = '1') then
clk_div <= "0000";
elsif (clk16x'event and clk16x = '1') then
clk_div <= clk_div + "0001";
end if;
end process;
-- recovered clock
-- clk_out <= not clk_div(3);
clk_out <= clk_div(3);
-- transition trigger
trans <= ((not clk_div(3)) and (not clk_div(2)) and clk_div(1) and clk_div(0)) or
(clk_div(3) and clk_div(2) and (not clk_div(1)) and (not clk_div(0)));
-- Manchester decoder
proc3: process (reset, trans, bout1, clk_out, clk16x)
begin
if (reset = '1') then
bout <= '0';
elsif (clk16x'event and clk16x = '1') then
if (trans = '1') then
bout <= bout1 XOR clk_out;
end if;
end if;
end process;
end architecture bhv;
architecture bhv_8 of mdec_rsc is
-- signal bhigh:real:= 1.0; -- bit decoding
-- signal blow:real:= -1.0; -- bit decoding
-- signal bnormal:real:=0.0; -- bit decoding
signal bhigh:std_logic:= '1'; -- bit decoding
signal blow:std_logic:= '0'; -- bit decoding
signal bout1:std_logic;
signal clk_div:std_logic_vector(2 downto 0):="000"; -- clock counter
signal trans:std_logic; -- transisition trigger
begin
-- bit decoding
proc1: process (reset,din,clk16x)
begin
if (reset = '1') then
bout1 <= 'X';
elsif (clk16x'event and clk16x = '1') then
if (din = bhigh) then
bout1 <= '1';
elsif (din = blow) then
bout1 <= '0';
else
bout1 <= 'X';
end if;
end if;
end process;
-- clock counter
proc2: process (reset, clk16x, clk_div)
begin
if (reset = '1') then
clk_div <= "000";
elsif (clk16x'event and clk16x = '1') then
clk_div <= clk_div + "001";
end if;
end process;
-- recovered clock
clk_out <= not clk_div(2);
-- transition trigger
trans <= ((not clk_div(1)) and clk_div(0)) or (clk_div(1) and (not clk_div(0)));
-- Manchester decoder
proc3: process (reset, trans, bout1, clk_out, clk16x)
begin
if (reset = '1') then
bout <= '0';
elsif (clk16x'event and clk16x = '1') then
if (trans = '1') then
bout <= bout1 XOR clk_out;
end if;
end if;
end process;
end architecture bhv_8;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity Decode_PW_Man is
port(
terminal power : electrical;
terminal ch1_pw : electrical;
terminal ch2_pw : electrical;
bit_stream_in : in std_logic
);
end Decode_PW_Man;
architecture Decode_PW_Man of Decode_PW_Man is
-- Component declarations
-- Signal declarations
signal bit_stream_in_mdec : std_logic;
signal clk16x : std_logic;
signal clk6k : std_logic;
signal clk_100k : std_logic;
signal cmp_bus : std_logic_vector(0 to 11);
signal cnt1 : std_logic_vector(0 to 11);
signal cnt2 : std_logic_vector(0 to 11);
signal mdec_clk : std_logic;
signal mdec_out : std_logic;
signal reset : std_logic;
signal reset_m : std_logic;
signal XSIG010228 : std_logic;
signal XSIG010229 : std_logic;
signal XSIG010256 : std_logic;
signal XSIG010263 : std_logic;
signal XSIG010264 : std_logic;
signal XSIG010266 : std_logic;
signal XSIG010267 : std_logic;
signal XSIG010268 : std_logic;
signal XSIG010320 : std_logic;
signal XSIG010330 : std_logic;
signal XSIG010334 : std_logic;
signal XSIG010339 : std_logic;
signal XSIG010349 : std_logic;
signal XSIG010357 : std_logic;
signal XSIG010371 : std_logic;
signal XSIG010372 : std_logic;
signal XSIG010373 : std_logic;
signal XSIG010383 : std_logic;
signal XSIG010384 : std_logic;
signal XSIG010385 : std_logic;
signal XSIG010386 : std_logic;
signal XSIG010390 : std_logic;
signal XSIG010433 : std_logic;
begin
-- Signal assignments
bit_stream_in_mdec <= bit_stream_in;
-- Component instances
cntr1 : entity work.counter_12
port map(
enable => XSIG010384,
cnt => cnt1,
reset => XSIG010357,
clk => XSIG010433
);
cntr2 : entity work.counter_12
port map(
enable => XSIG010349,
cnt => cnt2,
reset => XSIG010385,
clk => XSIG010320
);
cmp1 : entity work.dig_cmp(simple)
port map(
in1 => cnt1,
eq => XSIG010371,
clk => XSIG010433,
in2 => cmp_bus,
cmp => XSIG010384,
latch_in1 => XSIG010256,
latch_in2 => XSIG010383
);
cmp2 : entity work.dig_cmp(simple)
port map(
in1 => cnt2,
eq => XSIG010372,
clk => XSIG010320,
in2 => cmp_bus,
cmp => XSIG010349,
latch_in1 => XSIG010263,
latch_in2 => XSIG010264
);
XCMP109 : entity work.resistor(ideal)
generic map(
res => 1000000.0
)
port map(
p1 => power,
p2 => ELECTRICAL_REF
);
clk_1M2 : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => XSIG010320,
enable => XSIG010349
);
clk_1M1 : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => XSIG010433,
enable => XSIG010384
);
XCMP134 : entity work.d2a_bit(ideal)
port map(
D => XSIG010371,
A => ch1_pw
);
XCMP135 : entity work.d2a_bit(ideal)
port map(
D => XSIG010372,
A => ch2_pw
);
XCMP137 : entity work.SR_FF(simple)
port map(
S => XSIG010330,
R => XSIG010334,
Q => XSIG010349
);
XCMP138 : entity work.inverter(ideal)
port map(
input => XSIG010372,
output => XSIG010334
);
XCMP139 : entity work.SR_FF(simple)
port map(
S => XSIG010373,
R => XSIG010339,
Q => XSIG010384
);
XCMP140 : entity work.inverter(ideal)
port map(
input => XSIG010371,
output => XSIG010339
);
rc_clk2 : entity work.rc_clk
port map(
clk_50 => reset,
clk_6K => clk6k,
clk_100k => clk_100k
);
sm_rcvr1 : entity work.sm_cnt_rcvr
port map(
cnt1_en => XSIG010373,
cmp1_ltch1 => XSIG010256,
cnt2_rst => XSIG010385,
clk_100k => clk_100k,
cnt1_rst => XSIG010357,
cnt2_en => XSIG010330,
cmp2_ltch1 => XSIG010263,
frm_det => XSIG010229,
par_det => XSIG010228,
s2p_en => XSIG010266,
s2p_rst => XSIG010267,
clk_6k => mdec_clk,
clk_50 => reset,
da_latch => XSIG010268,
cmp1_ltch2 => XSIG010383,
cmp2_ltch2 => XSIG010264,
start_pulse => XSIG010390,
par_oe => XSIG010386
);
XCMP155 : entity work.level_set(ideal)
generic map(
logic_val => '0'
)
port map(
level => cmp_bus(11)
);
XCMP157 : entity work.TDM_Demux_dbg
port map(
data_bus => cmp_bus(0 to 9),
tdm_in => mdec_out,
clk_6k => mdec_clk,
s2p_en => XSIG010266,
s2p_rst => XSIG010267,
da_latch => XSIG010268,
frm_det => XSIG010229,
par_det => XSIG010228,
par_oe => XSIG010386,
start_bit => XSIG010390
);
XCMP172 : entity work.level_set(ideal)
generic map(
logic_val => '1'
)
port map(
level => cmp_bus(10)
);
clock1 : entity work.clock(ideal)
generic map(
period => 9.375us
)
port map(
CLK_OUT => clk16x
);
mdec_rsc7 : entity work.mdec_rsc(bhv)
port map(
din => bit_stream_in_mdec,
clk16x => clk16x,
reset => reset_m,
bout => mdec_out,
clk_out => mdec_clk
);
XCMP181 : entity work.clock_duty(ideal)
generic map(
off_time => 19.98 sec
)
port map(
CLOCK_OUT => reset_m
);
end Decode_PW_Man;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CS5_CC_Rudder is
end tb_CS5_CC_Rudder;
architecture TB_CS5_CC_Rudder of tb_CS5_CC_Rudder is
-- Component declarations
-- Signal declarations
terminal gear_out : rotational;
terminal link_in : translational;
terminal link_out : translational;
terminal pot_fb : electrical;
signal rf_in : std_logic;
signal rf_out : std_logic;
terminal rudder : rotational;
terminal rudder_ana : electrical;
terminal rudder_cmd : electrical;
terminal rudder_mtr_in : electrical;
terminal rudder_mtr_out : rotational_v;
terminal rudder_pw : electrical;
terminal rudder_servo_in : electrical;
terminal throttle_ana : electrical;
terminal throttle_cmd : electrical;
terminal throttle_pw : electrical;
terminal XSIG010013 : electrical;
begin
-- Signal assignments
-- Component instances
rudder_servo1 : entity work.rudder_servo
port map(
servo_out => rudder_mtr_in,
servo_in => rudder_servo_in,
pos_fb => pot_fb
);
gear1 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => rudder_mtr_out,
rot2 => gear_out
);
potentiometer : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => pot_fb,
input => gear_out
);
g_horn : entity work.horn_r2t(bhv)
port map(
theta => gear_out,
pos => link_in
);
r_horn : entity work.horn_t2r(bhv)
port map(
theta => rudder,
pos => link_out
);
\linkage\ : entity work.tran_linkage(a1)
port map(
p2 => link_out,
p1 => link_in
);
rudder_1 : entity work.rudder(bhv)
generic map(
k => 0.2
)
port map(
rot => rudder
);
XCMP6 : entity work.v_constant(ideal)
generic map(
level => 5.0
)
port map(
pos => XSIG010013,
neg => ELECTRICAL_REF
);
t_stick : entity work.stick(ideal)
generic map(
offset => 2.397,
phase => 0.0,
amplitude => 2.397,
freq => 1.0
)
port map(
v_out => throttle_cmd
);
r_stick : entity work.stick(ideal)
generic map(
freq => 1.0,
amplitude => 2.397,
phase => 270.0,
offset => 2.397
)
port map(
v_out => rudder_cmd
);
RF : entity work.rf_xmtr_rcvr(behavioral)
port map(
tdm_in => rf_in,
tdm_out => rf_out
);
Digitize_Encode1 : entity work.Digitize_Encode_Man
port map(
ch2_in => rudder_cmd,
ch1_in => throttle_cmd,
tdm_out => rf_in
);
filter : entity work.lpf_2_e(simple)
generic map(
f2 => 10.0,
f1 => 10.0
)
port map(
input => rudder_ana,
output => rudder_servo_in
);
t_pw2ana : entity work.pw2ana
port map(
ana_out => throttle_ana,
pw_in => throttle_pw
);
r_pw2ana : entity work.pw2ana
port map(
ana_out => rudder_ana,
pw_in => rudder_pw
);
motor2 : entity work.DC_Motor(basic)
generic map(
r_wind => 2.2,
kt => 3.43e-3,
l => 2.03e-3,
d => 5.63e-6,
j => 168.0e-9
)
port map(
p1 => rudder_mtr_in,
p2 => ELECTRICAL_REF,
shaft_rotv => rudder_mtr_out
);
stop3 : entity work.stop_r(ideal)
generic map(
k_stop => 1.0e6,
ang_max => 1.05,
ang_min => -1.05,
damp_stop => 1.0e2
)
port map(
ang1 => gear_out,
ang2 => ROTATIONAL_REF
);
Decode_PW_Man2 : entity work.Decode_PW_Man
port map(
bit_stream_in => rf_out,
ch2_pw => rudder_pw,
ch1_pw => throttle_pw,
power => XSIG010013
);
end TB_CS5_CC_Rudder;
--
|
gpl-2.0
|
a1965b91a26d8aaf0a1789bf7e685225
| 0.564177 | 3.604917 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc364.vhd
| 4 | 1,995 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc364.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n01i00364ent IS
END c03s02b01x01p03n01i00364ent;
ARCHITECTURE c03s02b01x01p03n01i00364arch OF c03s02b01x01p03n01i00364ent IS
subtype decade is integer;
type MVL_vector is array (positive range 1 to 50) of decade range 2 to 5;
BEGIN
TESTING: PROCESS
variable k : MVL_vector;
BEGIN
k(1) := 2;
k(50) := 5;
assert NOT (k(1)=2 and k(50)=5)
report "***PASSED TEST: c03s02b01x01p03n01i00364"
severity NOTE;
assert (k(1)=2 and k(50)=5)
report "***FAILED TEST: c03s02b01x01p03n01i00364 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n01i00364arch;
|
gpl-2.0
|
d8f55fb44f4cd5e7c4a8c28298f82881
| 0.671679 | 3.680812 | false | true | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.a-Alu.vhd
| 1 | 5,350 |
--------------------------------------------------------------------------------
-- FILE: Alu
-- DESC: ALU with multiple functions:
-- ADD/SUB/CMP
-- SHIFT
-- AND/OR/XOR
--
-- Author:
-- Create: 2015-05-25
-- Update: 2015-05-27
-- Status: TESTED
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Encode of FUNCTION (f) signal:
-- 00000 -- [ADD] Addition, or NOP
-- 00001 -- [AND]
-- 00010 -- [OR]
-- 00011 -- [XOR]
-- 00100 -- [SLL] Logic Shift LEFT
-- 00101 -- [SRL] Logic Shift RIGHT
-- 00110 -- NOT USED
-- 00111 -- [SRA] Arithmetic Shift RIGHT
-- 01000 -- [MULTU] Unsigned Multiply -- IN MUL MODULE
-- 01001 -- [MULT] Multiply -- IN MUL MODULE
-- 01010 -- [DIVU] Unsigned Division -- IN DIV MODULE
-- 01011 -- [DIV] Division -- IN DIV MODULE
-- 01100 -- [SQRT] Square root -- IN DIV MODULE
-- 01101 -- NOT USED
-- 01110 -- NOT USED
-- 01111 -- NOT USED
-- 10000 -- [SUB] Substraction
-- 10001 -- [SGT] SET If GREAT, For SIGNED
-- 10010 -- [SGE] SET If GREAT AND EQUAL, For SIGNED
-- 10011 -- [SLT] SET If LESS, For SIGNED
-- 10100 -- [SLE] SET If LESS AND EQUAL, For SIGNED
-- 10101 -- [SGTU] SET If GREAT, For UNSIGNED
-- 10110 -- [SGEU] SET If GREAT AND EQUAL, For UNSIGNED
-- 10111 -- [SLTU] SET If LESS, For UNSIGNED
-- 11000 -- [SLEU] SET If LESS AND EQUAL, For UNSIGNED
-- 11001 -- [SEQ] SET If EQUAL
-- 11010 -- [SNE] SET If NOT EQUAL
-- 11011 -- NOT USED
-- 11100 -- NOT USED
-- 11101 -- NOT USED
-- 11110 -- NOT USED
-- 11111 -- NOT USED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Alu is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
f : in std_logic_vector(4 downto 0):=(others=>'0'); -- Function
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0') -- Data Out
);
end Alu;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture alu_arch of Alu is
component Adder is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
cin : in std_logic;
a, b : in std_logic_vector(DATA_SIZE-1 downto 0);
s : out std_logic_vector(DATA_SIZE-1 downto 0);
cout : out std_logic
);
end component;
component Shifter is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
l_r : in std_logic; -- LEFT/RIGHT
l_a : in std_logic; -- LOGIC/ARITHMETIC
s_r : in std_logic; -- SHIFT/ROTATE
a : in std_logic_vector(DATA_SIZE-1 downto 0);
b : in std_logic_vector(DATA_SIZE-1 downto 0);
o : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
constant FUNC_SIZE : integer := 5;
constant FUNC_NUM : integer := 2**FUNC_SIZE;
signal b_new : std_logic_vector(DATA_SIZE-1 downto 0);
signal as_arr: std_logic_vector(DATA_SIZE-1 downto 0);
signal ado : std_logic_vector(DATA_SIZE-1 downto 0); -- adder output
signal sho : std_logic_vector(DATA_SIZE-1 downto 0); -- shifter output
signal c_f, o_f, s_f, z_f, b_f : std_logic := '0'; -- Flags of ADDER outputs: Carry, Overflow, Sign, Zero, Borrow
type OutMem_t is array (FUNC_NUM-1 downto 0) of std_logic_vector(DATA_SIZE-1 downto 0);
signal outputs : OutMem_t;
signal zeros : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
begin
as_arr <= (others=>f(FUNC_SIZE-1));
b_new <= b xor as_arr;
ADD0: Adder
generic map (DATA_SIZE)
port map (f(FUNC_SIZE-1), a, b_new, ado, c_f);
SHF0: Shifter
generic map (DATA_SIZE)
port map (f(0), f(1), '0', a, b, sho);
-- CAUTION: the concept of CF is different from the CF in 8086 structure, a
-- BF is needed to determin the Borrow Bit of a substraction.
b_f <= not c_f;
s_f <= ado(DATA_SIZE-1);
o_f <= (not (a(DATA_SIZE-1) xor b_new(DATA_SIZE-1))) and (a(DATA_SIZE-1) xor s_f);
P0: process(ado)
begin
if ado = zeros then
z_f <= '1';
else
z_f <= '0';
end if;
end process;
outputs(0) <= ado;
outputs(1) <= a and b;
outputs(2) <= a or b;
outputs(3) <= a xor b;
outputs(4) <= sho;
outputs(5) <= sho;
outputs(7) <= sho;
outputs(16) <= ado;
outputs(17) <= (0 => (not z_f) and (not (s_f xor o_f)), others => '0'); -- ZF=0 & SF=OF
outputs(18) <= (0 => (not (s_f xor o_f)), others => '0'); -- SF=OF
outputs(19) <= (0 => (s_f xor o_f), others => '0'); -- SF!=OF
outputs(20) <= (0 => (z_f or (s_f xor o_f)), others => '0'); -- ZF=1 | SF!=OF
outputs(21) <= (0 => ((not b_f) and (not z_f)), others => '0'); -- BF=0 & ZF=0
outputs(22) <= (0 => (not b_f), others => '0'); -- BF=0
outputs(23) <= (0 => b_f, others => '0'); -- BF=1
outputs(24) <= (0 => (b_f or z_f), others => '0'); -- BF=1 | ZF=1
outputs(25) <= (0 => z_f, others => '0'); -- ZF=1
outputs(26) <= (0 => (not z_f), others => '0'); -- ZF=0
o <= outputs(to_integer(unsigned(f)));
end alu_arch;
|
mit
|
155d88f02912f436e7473dde5f5848a8
| 0.524673 | 2.983826 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd
| 4 | 1,366 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity transmission_line_wa is
port ( quantity vin : in voltage;
quantity vout : out voltage);
end entity transmission_line_wa;
----------------------------------------------------------------
architecture abstract of transmission_line_wa is
constant propagation_time : real := 2.5E-9;
constant attenuation : real := 0.8;
quantity vin_temp : real;
begin
vin_temp == vin;
vout == attenuation * vin_temp'delayed(propagation_time);
end architecture abstract;
|
gpl-2.0
|
d6cc6fd9f19198a29068eb0acef2156c
| 0.690337 | 4.309148 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_freq_gen.vhd
| 1 | 10,756 |
-- #################################################################################################
-- # << NEO430 - Arbitrary Frequency Generator >> #
-- # ********************************************************************************************* #
-- # Number controlled oscillator-based frequency generator with three independent channels. Each #
-- # channel has its enable flag, 16-bit tuning word register and prescaler selector. The phase #
-- # accumulator of each channel is 17 bit wide. #
-- # f_out(x) = ((f_cpu / nco_prsc(x)) * tuning_word(x)) / 2^17 for channels x = 0,1,2 #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_freq_gen is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- frequency generator --
freq_gen_o : out std_ulogic_vector(02 downto 0) -- programmable frequency output
);
end neo430_freq_gen;
architecture neo430_freq_gen_rtl of neo430_freq_gen is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(freq_gen_size_c); -- low address boundary bit
-- control reg bits --
constant ctrl_en_ch0_c : natural := 0; -- r/w: enable NCO channel 0
constant ctrl_en_ch1_c : natural := 1; -- r/w: enable NCO channel 1
constant ctrl_en_ch2_c : natural := 2; -- r/w: enable NCO channel 2
constant ctrl_ch0_prsc0_c : natural := 3; -- r/w: prescaler select bit 0 for channel 0
constant ctrl_ch0_prsc1_c : natural := 4; -- r/w: prescaler select bit 1 for channel 0
constant ctrl_ch0_prsc2_c : natural := 5; -- r/w: prescaler select bit 2 for channel 0
constant ctrl_ch1_prsc0_c : natural := 6; -- r/w: prescaler select bit 0 for channel 1
constant ctrl_ch1_prsc1_c : natural := 7; -- r/w: prescaler select bit 1 for channel 1
constant ctrl_ch1_prsc2_c : natural := 8; -- r/w: prescaler select bit 2 for channel 1
constant ctrl_ch2_prsc0_c : natural := 9; -- r/w: prescaler select bit 0 for channel 2
constant ctrl_ch2_prsc1_c : natural := 10; -- r/w: prescaler select bit 1 for channel 2
constant ctrl_ch2_prsc2_c : natural := 11; -- r/w: prescaler select bit 2 for channel 2
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wren : std_ulogic; -- word write enable
signal rden : std_ulogic; -- word read enable
-- accessible regs --
signal ctrl : std_ulogic_vector(11 downto 0); -- r/w: control register
type tuning_word_t is array (0 to 2) of std_ulogic_vector(15 downto 0);
signal tuning_word : tuning_word_t; -- -/w: tuning word channel 0,1,2
-- nco core --
type phase_accu_t is array (0 to 2) of std_ulogic_vector(16 downto 0);
signal nco_phase_accu : phase_accu_t;
signal nco_prsc_tick : std_ulogic_vector(2 downto 0);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = freq_gen_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= freq_gen_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wren <= acc_en and wren_i;
rden <= acc_en and rden_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wren = '1') then
if (addr = freq_gen_ctrl_addr_c) then
ctrl(ctrl_en_ch0_c) <= data_i(ctrl_en_ch0_c);
ctrl(ctrl_en_ch1_c) <= data_i(ctrl_en_ch1_c);
ctrl(ctrl_en_ch2_c) <= data_i(ctrl_en_ch2_c);
ctrl(ctrl_ch0_prsc0_c) <= data_i(ctrl_ch0_prsc0_c);
ctrl(ctrl_ch0_prsc1_c) <= data_i(ctrl_ch0_prsc1_c);
ctrl(ctrl_ch0_prsc2_c) <= data_i(ctrl_ch0_prsc2_c);
ctrl(ctrl_ch1_prsc0_c) <= data_i(ctrl_ch1_prsc0_c);
ctrl(ctrl_ch1_prsc1_c) <= data_i(ctrl_ch1_prsc1_c);
ctrl(ctrl_ch1_prsc2_c) <= data_i(ctrl_ch1_prsc2_c);
ctrl(ctrl_ch2_prsc0_c) <= data_i(ctrl_ch2_prsc0_c);
ctrl(ctrl_ch2_prsc1_c) <= data_i(ctrl_ch2_prsc1_c);
ctrl(ctrl_ch2_prsc2_c) <= data_i(ctrl_ch2_prsc2_c);
end if;
if (addr = freq_gen_tw_ch0_addr_c) then
tuning_word(0) <= data_i;
end if;
if (addr = freq_gen_tw_ch1_addr_c) then
tuning_word(1) <= data_i;
end if;
if (addr = freq_gen_tw_ch2_addr_c) then
tuning_word(2) <= data_i;
end if;
end if;
end if;
end process wr_access;
-- NCO core (number controlled oscillator) ----------------------------------
-- -----------------------------------------------------------------------------
nco_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- enable external clock generator --
clkgen_en_o <= ctrl(ctrl_en_ch0_c) or ctrl(ctrl_en_ch1_c) or ctrl(ctrl_en_ch2_c);
-- NCOs --
for i in 0 to 2 loop
-- NCO clock enable --
nco_prsc_tick(i) <= clkgen_i(to_integer(unsigned(ctrl(ctrl_ch0_prsc2_c + 3*i downto ctrl_ch0_prsc0_c + 3*i))));
-- phase accu --
if (ctrl(ctrl_en_ch0_c + i) = '0') then -- disabled
nco_phase_accu(i) <= (others => '0');
elsif (nco_prsc_tick(i) = '1') then -- enabled; wait for clock enable tick
nco_phase_accu(i) <= std_ulogic_vector(unsigned(nco_phase_accu(i)) + unsigned('0' & tuning_word(i)));
end if;
-- output --
freq_gen_o(i) <= nco_phase_accu(i)(16); -- MSB (carry_out) is output
end loop; -- i - NCO channel
end if;
end process nco_core;
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rden = '1') then
-- if (addr = freq_gen_ctrl_addr_c) then
data_o(ctrl_en_ch0_c) <= ctrl(ctrl_en_ch0_c);
data_o(ctrl_en_ch1_c) <= ctrl(ctrl_en_ch1_c);
data_o(ctrl_en_ch2_c) <= ctrl(ctrl_en_ch2_c);
data_o(ctrl_ch0_prsc0_c) <= ctrl(ctrl_ch0_prsc0_c);
data_o(ctrl_ch0_prsc1_c) <= ctrl(ctrl_ch0_prsc1_c);
data_o(ctrl_ch0_prsc2_c) <= ctrl(ctrl_ch0_prsc2_c);
data_o(ctrl_ch1_prsc0_c) <= ctrl(ctrl_ch1_prsc0_c);
data_o(ctrl_ch1_prsc1_c) <= ctrl(ctrl_ch1_prsc1_c);
data_o(ctrl_ch1_prsc2_c) <= ctrl(ctrl_ch1_prsc2_c);
data_o(ctrl_ch2_prsc0_c) <= ctrl(ctrl_ch2_prsc0_c);
data_o(ctrl_ch2_prsc1_c) <= ctrl(ctrl_ch2_prsc1_c);
data_o(ctrl_ch2_prsc2_c) <= ctrl(ctrl_ch2_prsc2_c);
-- end if;
end if;
end if;
end process rd_access;
end neo430_freq_gen_rtl;
|
bsd-3-clause
|
10515196119e09040c91a7b363a7ef43
| 0.497769 | 3.781997 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2430.vhd
| 4 | 1,953 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2430.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n04i02430ent IS
END c07s03b02x01p01n04i02430ent;
ARCHITECTURE c07s03b02x01p01n04i02430arch OF c07s03b02x01p01n04i02430ent IS
type sigrec1 is
record
B1 : bit;
B2 : integer;
B3 : bit;
end record;
signal S1 : sigrec1;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= (('0' and '1'), 2, '1');
wait for 1 ns;
assert NOT(S1.B1='0' and S1.B2=2 and S1.B3='1')
report "***PASSED TEST: c07s03b02x01p01n04i02430"
severity NOTE;
assert (S1.B1='0' and S1.B2=2 and S1.B3='1')
report "***FAILED TEST: c07s03b02x01p01n04i02430 - Expression of an element association must have the same type as the associated record element."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n04i02430arch;
|
gpl-2.0
|
318163584b03b4438f0b83a62741d96a
| 0.65745 | 3.468917 | false | true | false | false |
stnolting/neo430
|
rtl/core/neo430_spi.vhd
| 1 | 12,898 |
-- #################################################################################################
-- # << NEO430 - Serial Peripheral Interface >> #
-- # ********************************************************************************************* #
-- # Frame format: 8-bit or 16-bit, MSB or LSB first, 2 clock modes, 8 clock speeds, 6 CS lines. #
-- # Interrupt: SPI_transfer_done #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_spi is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- com lines --
spi_sclk_o : out std_ulogic; -- SPI serial clock
spi_mosi_o : out std_ulogic; -- SPI master out, slave in
spi_miso_i : in std_ulogic; -- SPI master in, slave out
spi_cs_o : out std_ulogic_vector(05 downto 0); -- SPI CS
-- interrupt --
spi_irq_o : out std_ulogic -- transmission done interrupt
);
end neo430_spi;
architecture neo430_spi_rtl of neo430_spi is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(spi_size_c); -- low address boundary bit
-- control reg bits --
constant ctrl_spi_cs_sel0_c : natural := 0; -- r/w: spi CS 0
constant ctrl_spi_cs_sel1_c : natural := 1; -- r/w: spi CS 1
constant ctrl_spi_cs_sel2_c : natural := 2; -- r/w: spi CS 2
constant ctrl_spi_cs_sel3_c : natural := 3; -- r/w: spi CS 3
constant ctrl_spi_cs_sel4_c : natural := 4; -- r/w: spi CS 4
constant ctrl_spi_cs_sel5_c : natural := 5; -- r/w: spi CS 5
constant ctrl_spi_en_c : natural := 6; -- r/w: spi enable
constant ctrl_spi_cpha_c : natural := 7; -- r/w: spi clock phase
constant ctrl_spi_irq_en_c : natural := 8; -- r/w: spi transmission done interrupt enable
constant ctrl_spi_prsc0_c : natural := 9; -- r/w: spi prescaler select bit 0
constant ctrl_spi_prsc1_c : natural := 10; -- r/w: spi prescaler select bit 1
constant ctrl_spi_prsc2_c : natural := 11; -- r/w: spi prescaler select bit 2
constant ctrl_spi_dir_c : natural := 12; -- r/w: shift direction (0: MSB first, 1: LSB first)
constant ctrl_spi_size_c : natural := 13; -- r/w: data size(0: 8-bit, 1: 16-bit)
-- reserved : natural := 14;
constant ctrl_spi_busy_c : natural := 15; -- r/-: spi transceiver is busy
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wr_en : std_ulogic; -- word write enable
signal rd_en : std_ulogic; -- read enable
-- accessible regs --
signal ctrl : std_ulogic_vector(15 downto 0);
-- clock generator --
signal spi_clk : std_ulogic;
-- spi transceiver --
signal spi_busy : std_ulogic;
signal spi_state0 : std_ulogic;
signal spi_state1 : std_ulogic;
signal spi_rtx_sreg : std_ulogic_vector(15 downto 0);
signal spi_rx_data : std_ulogic_vector(15 downto 0);
signal spi_bitcnt : std_ulogic_vector(04 downto 0);
signal spi_miso_ff0 : std_ulogic;
signal spi_miso_ff1 : std_ulogic;
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = spi_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= spi_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wr_en <= acc_en and wren_i;
rd_en <= acc_en and rden_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wr_en = '1') then
if (addr = spi_ctrl_addr_c) then
ctrl <= data_i;
end if;
end if;
end if;
end process wr_access;
-- Clock Selection ----------------------------------------------------------
-- -----------------------------------------------------------------------------
-- clock enable --
clkgen_en_o <= ctrl(ctrl_spi_en_c);
-- spi clock select --
spi_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_spi_prsc2_c downto ctrl_spi_prsc0_c))));
-- SPI transceiver ----------------------------------------------------------
-- -----------------------------------------------------------------------------
spi_rtx_unit: process(clk_i)
begin
if rising_edge(clk_i) then
-- input (MISO) synchronizer --
spi_miso_ff0 <= spi_miso_i;
spi_miso_ff1 <= spi_miso_ff0;
-- arbiter --
spi_irq_o <= '0';
if (spi_state0 = '0') or (ctrl(ctrl_spi_en_c) = '0') then -- idle or disabled
if (ctrl(ctrl_spi_size_c) = '0') then -- 8 bit mode
spi_bitcnt <= "01000";
else -- 16 bit mode
spi_bitcnt <= "10000";
end if;
spi_state1 <= '0';
spi_mosi_o <= '0';
spi_sclk_o <= '0';
if (ctrl(ctrl_spi_en_c) = '0') then -- disabled
spi_busy <= '0';
elsif (wr_en = '1') and (addr = spi_rtx_addr_c) then
if (ctrl(ctrl_spi_size_c) = '0') then -- 8 bit mode
spi_rtx_sreg <= data_i(7 downto 0) & "00000000";
else -- 16 bit mode
spi_rtx_sreg <= data_i(15 downto 0);
end if;
spi_busy <= '1';
end if;
spi_state0 <= spi_busy and spi_clk; -- start with next new clock pulse
else -- transmission in progress
if (spi_state1 = '0') then -- first half of transmission
spi_sclk_o <= ctrl(ctrl_spi_cpha_c);
if (ctrl(ctrl_spi_dir_c) = '0') then
spi_mosi_o <= spi_rtx_sreg(15); -- MSB first
else
spi_mosi_o <= spi_rtx_sreg(0); -- LSB first
end if;
if (spi_clk = '1') then
spi_state1 <= '1';
if (ctrl(ctrl_spi_cpha_c) = '0') then
if (ctrl(ctrl_spi_dir_c) = '0') then
spi_rtx_sreg <= spi_rtx_sreg(14 downto 0) & spi_miso_ff1; -- MSB first
else
spi_rtx_sreg <= spi_miso_ff1 & spi_rtx_sreg(15 downto 1); -- LSB first
end if;
end if;
spi_bitcnt <= std_ulogic_vector(unsigned(spi_bitcnt) - 1);
end if;
else -- second half of transmission
spi_sclk_o <= not ctrl(ctrl_spi_cpha_c);
if (spi_clk = '1') then
spi_state1 <= '0';
if (ctrl(ctrl_spi_cpha_c) = '1') then
if (ctrl(ctrl_spi_dir_c) = '0') then
spi_rtx_sreg <= spi_rtx_sreg(14 downto 0) & spi_miso_ff1; -- MSB first
else
spi_rtx_sreg <= spi_miso_ff1 & spi_rtx_sreg(15 downto 1); -- LSB first
end if;
end if;
if (spi_bitcnt = "00000") then
spi_state0 <= '0';
spi_busy <= '0';
spi_irq_o <= ctrl(ctrl_spi_irq_en_c);
end if;
end if;
end if;
end if;
end if;
end process spi_rtx_unit;
-- SPI receiver output --
spi_rx_data <= (x"00" & spi_rtx_sreg(7 downto 0)) when (ctrl(ctrl_spi_size_c) = '0') else spi_rtx_sreg(15 downto 0);
-- direct user-defined CS --
spi_cs_o(0) <= '0' when (ctrl(ctrl_spi_cs_sel0_c) = '1') else '1';
spi_cs_o(1) <= '0' when (ctrl(ctrl_spi_cs_sel1_c) = '1') else '1';
spi_cs_o(2) <= '0' when (ctrl(ctrl_spi_cs_sel2_c) = '1') else '1';
spi_cs_o(3) <= '0' when (ctrl(ctrl_spi_cs_sel3_c) = '1') else '1';
spi_cs_o(4) <= '0' when (ctrl(ctrl_spi_cs_sel4_c) = '1') else '1';
spi_cs_o(5) <= '0' when (ctrl(ctrl_spi_cs_sel5_c) = '1') else '1';
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rd_en = '1') then
if (addr = spi_ctrl_addr_c) then
data_o(ctrl_spi_en_c) <= ctrl(ctrl_spi_en_c);
data_o(ctrl_spi_cpha_c) <= ctrl(ctrl_spi_cpha_c);
data_o(ctrl_spi_irq_en_c) <= ctrl(ctrl_spi_irq_en_c);
data_o(ctrl_spi_prsc0_c) <= ctrl(ctrl_spi_prsc0_c);
data_o(ctrl_spi_prsc1_c) <= ctrl(ctrl_spi_prsc1_c);
data_o(ctrl_spi_prsc2_c) <= ctrl(ctrl_spi_prsc2_c);
data_o(ctrl_spi_dir_c) <= ctrl(ctrl_spi_dir_c);
data_o(ctrl_spi_size_c) <= ctrl(ctrl_spi_size_c);
data_o(ctrl_spi_cs_sel0_c) <= ctrl(ctrl_spi_cs_sel0_c);
data_o(ctrl_spi_cs_sel1_c) <= ctrl(ctrl_spi_cs_sel1_c);
data_o(ctrl_spi_cs_sel2_c) <= ctrl(ctrl_spi_cs_sel2_c);
data_o(ctrl_spi_cs_sel3_c) <= ctrl(ctrl_spi_cs_sel3_c);
data_o(ctrl_spi_cs_sel4_c) <= ctrl(ctrl_spi_cs_sel4_c);
data_o(ctrl_spi_cs_sel5_c) <= ctrl(ctrl_spi_cs_sel5_c);
data_o(ctrl_spi_busy_c) <= spi_busy;
else -- spi_rtx_addr_c
data_o(15 downto 0) <= spi_rx_data;
end if;
end if;
end if;
end process rd_access;
end neo430_spi_rtl;
|
bsd-3-clause
|
494883b49fb0f2459cfd795772883dee
| 0.476586 | 3.73206 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc860.vhd
| 4 | 10,626 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc860.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00860pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00860pkg_b;
package body c01s03b01x00p12n01i00860pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00860pkg_b;
use work.c01s03b01x00p12n01i00860pkg_b.all;
package c01s03b01x00p12n01i00860pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant dumy : bit_vector(zero to three) := "1010" ;
signal Sin1 : bit_vector(zero to six) ;
signal Sin2 : boolean_vector(zero to six) ;
signal Sin4 : severity_level_vector(zero to six) ;
signal Sin5 : integer_vector(zero to six) ;
signal Sin6 : real_vector(zero to six) ;
signal Sin7 : time_vector(zero to six) ;
signal Sin8 : natural_vector(zero to six) ;
signal Sin9 : positive_vector(zero to six) ;
signal Sin10: array_rec_std(zero to six) ;
end c01s03b01x00p12n01i00860pkg_a;
use work.c01s03b01x00p12n01i00860pkg_a.all;
use work.c01s03b01x00p12n01i00860pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00860pkg_a.all;
use work.c01s03b01x00p12n01i00860pkg_b.all;
ENTITY c01s03b01x00p12n01i00860ent IS
END c01s03b01x00p12n01i00860ent;
ARCHITECTURE c01s03b01x00p12n01i00860arch OF c01s03b01x00p12n01i00860ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
Gif : if fifteen = 15 generate
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
end generate;
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00860"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00860 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00860arch;
configuration c01s03b01x00p12n01i00860cfg of c01s03b01x00p12n01i00860ent is
for c01s03b01x00p12n01i00860arch
for K
for GIF
for T5:test use configuration work.testbench;
end for;
end for;
for G(zero)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(one)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(two)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(three)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
|
gpl-2.0
|
65640606a616e5693ce0b8f7cc182129
| 0.589027 | 3.381922 | false | true | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/memory/bram_sync_tdp_tb.vhd
| 1 | 1,968 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: BRAM_SYNC_TDP_TB
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BRAM_SYNC_TDP_TB is
end BRAM_SYNC_TDP_TB;
architecture behavior of BRAM_SYNC_TDP_TB is
-- CLK and RST
signal CLK : STD_LOGIC := '0';
signal WE_A : STD_LOGIC := '0';
-- Block memory signals
signal ADDR_A : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
signal DATAIN_A : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal DATAOUT_A : STD_LOGIC_VECTOR(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
begin
uut : entity work.BRAM_SYNC_TDP
port map (
-- Port A
CLK => CLK,
WE_A => WE_A,
ADDR_A => ADDR_A,
DATAIN_A => DATAIN_A,
DATAOUT_A => DATAOUT_A,
-- Port B
WE_A => '0',
ADDR_A => (others => '0'),
DATAIN_A => (others => '0'),
DATAOUT_A => open
);
clk_process : process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
sim_proc : process
begin
wait for 100 ns;
wait until rising_edge(CLK);
WE_A <= '1';
ADDR_A <= "0000011111";
DATAIN_A <= "1111111111000000";
wait until rising_edge(CLK);
WE_A <= '0';
ADDR_A <= "0000011110";
wait until rising_edge(CLK);
WE_A <= '0';
ADDR_A <= "0000011111";
wait;
end process;
end;
|
mit
|
9ca0f70f4e4d3f7724ab054667fc2f5a
| 0.466463 | 3.89703 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1443.vhd
| 4 | 1,828 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1443.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01443ent IS
END c08s07b00x00p02n01i01443ent;
ARCHITECTURE c08s07b00x00p02n01i01443arch OF c08s07b00x00p02n01i01443ent IS
begin
transmit: process
variable k : integer := 10;
variable m : integer := 6;
begin
if m > 5 then
while (k > 5) loop
k := k - 1;
end loop;
end if;
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01443 - WHILE statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01443"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01443arch;
|
gpl-2.0
|
68cf926298c84498c07577ba35e19076
| 0.655361 | 3.648703 | false | true | false | false |
123gmax/Digital-Lab
|
Lab1/Alex/counter/adder_4_bit.vhd
| 1 | 1,763 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_4_bit is
Port( CLK : in STD_LOGIC;
direction : in STD_LOGIC;
auto : in STD_LOGIC;
tick : in STD_LOGIC;
load : in STD_LOGIC;
load_input : in STD_LOGIC_VECTOR(3 downto 0);
output : out STD_LOGIC_VECTOR(3 downto 0) := (others => '0')
);
end counter_4_bit;
architecture Behavioral of counter_4_bit is
signal clk_divider : unsigned(31 downto 0) := (others => '0');
signal clk_1s : STD_LOGIC := '0';
signal count : unsigned(3 downto 0) := (others => '0');
begin
process(CLK) begin
if (rising_edge(CLK)) then
clk_divider <= clk_divider + 1;
-- if(clk_divider >= 1) then -- Use this clock divider for simulation purposes
if(clk_divider >= 50000000) then -- The new clock's frequency will be 1s. Therefore: two 0.5s H/L periods.
clk_1s <= NOT clk_1s;
clk_divider <= (others => '0');
end if;
end if;
end process;
process(clk_1s, load, tick) begin
if(rising_edge(clk_1s) AND (auto = '1')) then
if(direction = '1') then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
if(rising_edge(tick) AND (auto = '0')) then
if(direction = '1') then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
if(rising_edge(load)) then
count <= unsigned(load_input);
end if;
end process;
output <= std_logic_vector(count);
end Behavioral;
|
gpl-2.0
|
2e954e0fb0944b1c99f6b6e517873a8a
| 0.505389 | 3.775161 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu-b.vhd
| 4 | 2,944 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_alu-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture behavior of alu is
begin
alu_op: process ( s1, s2, func ) is
variable bv_s1, bv_s2 : dlx_bv_word;
variable temp_result : dlx_bv_word;
variable temp_overflow : boolean;
type boolean_to_X01_table is array (boolean) of X01;
constant boolean_to_X01 : boolean_to_X01_table := ( '0', '1' );
begin
bv_s1 := To_bitvector(s1);
bv_s2 := To_bitvector(s2);
temp_overflow := false;
case func is
when alu_pass_s1 =>
temp_result := bv_s1;
when alu_pass_s2 =>
temp_result := bv_s2;
when alu_and =>
temp_result := bv_s1 and bv_s2;
when alu_or =>
temp_result := bv_s1 or bv_s2;
when alu_xor =>
temp_result := bv_s1 xor bv_s2;
when alu_sll =>
temp_result := bv_s1 sll bv_to_natural(bv_s2(27 to 31));
when alu_srl =>
temp_result := bv_s1 srl bv_to_natural(bv_s2(27 to 31));
when alu_sra =>
temp_result := bv_s1 sra bv_to_natural(bv_s2(27 to 31));
when alu_add =>
bv_add(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_addu =>
bv_addu(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_sub =>
bv_sub(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_subu =>
bv_subu(bv_s1, bv_s2, temp_result, temp_overflow);
when others =>
report "illegal function code" severity error;
temp_result := X"0000_0000";
end case;
result <= To_X01(temp_result) after Tpd;
zero <= boolean_to_X01(temp_result = X"0000_0000") after Tpd;
negative <= To_X01(temp_result(0)) after Tpd;
overflow <= boolean_to_X01(temp_overflow) after Tpd;
end process alu_op;
end architecture behavior;
|
gpl-2.0
|
c43540c9f6359e489bfcc8a6ec089d4e
| 0.574389 | 3.546988 | false | false | false | false |
mmoraless/ecc_vhdl
|
ecc_add/lut3inadd_163.vhd
| 1 | 8,977 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------------------------
entity lut_3inadd is
generic(
NUM_BITS: positive := 163
);
port (
I: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
B: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
C: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
D: out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end;
---------------------------------------------------------------------------------------------
architecture behave of lut_3inadd is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
constant a : std_logic_vector(NUM_BITS-1 downto 0):= "1111011011010001000001011001010101011101111101010000100111110010101010101001111111110000100001010001011110110001000111000100100011011010010011110000010101011100010";
begin
D(0) <= I(0) xor B(0) xor C(0) xor a(0);
D(1) <= I(1) xor B(1) xor C(1) xor a(1);
D(2) <= I(2) xor B(2) xor C(2) xor a(2);
D(3) <= I(3) xor B(3) xor C(3) xor a(3);
D(4) <= I(4) xor B(4) xor C(4) xor a(4);
D(5) <= I(5) xor B(5) xor C(5) xor a(5);
D(6) <= I(6) xor B(6) xor C(6) xor a(6);
D(7) <= I(7) xor B(7) xor C(7) xor a(7);
D(8) <= I(8) xor B(8) xor C(8) xor a(8);
D(9) <= I(9) xor B(9) xor C(9) xor a(9);
D(10) <= I(10) xor B(10) xor C(10) xor a(10);
D(11) <= I(11) xor B(11) xor C(11) xor a(11);
D(12) <= I(12) xor B(12) xor C(12) xor a(12);
D(13) <= I(13) xor B(13) xor C(13) xor a(13);
D(14) <= I(14) xor B(14) xor C(14) xor a(14);
D(15) <= I(15) xor B(15) xor C(15) xor a(15);
D(16) <= I(16) xor B(16) xor C(16) xor a(16);
D(17) <= I(17) xor B(17) xor C(17) xor a(17);
D(18) <= I(18) xor B(18) xor C(18) xor a(18);
D(19) <= I(19) xor B(19) xor C(19) xor a(19);
D(20) <= I(20) xor B(20) xor C(20) xor a(20);
D(21) <= I(21) xor B(21) xor C(21) xor a(21);
D(22) <= I(22) xor B(22) xor C(22) xor a(22);
D(23) <= I(23) xor B(23) xor C(23) xor a(23);
D(24) <= I(24) xor B(24) xor C(24) xor a(24);
D(25) <= I(25) xor B(25) xor C(25) xor a(25);
D(26) <= I(26) xor B(26) xor C(26) xor a(26);
D(27) <= I(27) xor B(27) xor C(27) xor a(27);
D(28) <= I(28) xor B(28) xor C(28) xor a(28);
D(29) <= I(29) xor B(29) xor C(29) xor a(29);
D(30) <= I(30) xor B(30) xor C(30) xor a(30);
D(31) <= I(31) xor B(31) xor C(31) xor a(31);
D(32) <= I(32) xor B(32) xor C(32) xor a(32);
D(33) <= I(33) xor B(33) xor C(33) xor a(33);
D(34) <= I(34) xor B(34) xor C(34) xor a(34);
D(35) <= I(35) xor B(35) xor C(35) xor a(35);
D(36) <= I(36) xor B(36) xor C(36) xor a(36);
D(37) <= I(37) xor B(37) xor C(37) xor a(37);
D(38) <= I(38) xor B(38) xor C(38) xor a(38);
D(39) <= I(39) xor B(39) xor C(39) xor a(39);
D(40) <= I(40) xor B(40) xor C(40) xor a(40);
D(41) <= I(41) xor B(41) xor C(41) xor a(41);
D(42) <= I(42) xor B(42) xor C(42) xor a(42);
D(43) <= I(43) xor B(43) xor C(43) xor a(43);
D(44) <= I(44) xor B(44) xor C(44) xor a(44);
D(45) <= I(45) xor B(45) xor C(45) xor a(45);
D(46) <= I(46) xor B(46) xor C(46) xor a(46);
D(47) <= I(47) xor B(47) xor C(47) xor a(47);
D(48) <= I(48) xor B(48) xor C(48) xor a(48);
D(49) <= I(49) xor B(49) xor C(49) xor a(49);
D(50) <= I(50) xor B(50) xor C(50) xor a(50);
D(51) <= I(51) xor B(51) xor C(51) xor a(51);
D(52) <= I(52) xor B(52) xor C(52) xor a(52);
D(53) <= I(53) xor B(53) xor C(53) xor a(53);
D(54) <= I(54) xor B(54) xor C(54) xor a(54);
D(55) <= I(55) xor B(55) xor C(55) xor a(55);
D(56) <= I(56) xor B(56) xor C(56) xor a(56);
D(57) <= I(57) xor B(57) xor C(57) xor a(57);
D(58) <= I(58) xor B(58) xor C(58) xor a(58);
D(59) <= I(59) xor B(59) xor C(59) xor a(59);
D(60) <= I(60) xor B(60) xor C(60) xor a(60);
D(61) <= I(61) xor B(61) xor C(61) xor a(61);
D(62) <= I(62) xor B(62) xor C(62) xor a(62);
D(63) <= I(63) xor B(63) xor C(63) xor a(63);
D(64) <= I(64) xor B(64) xor C(64) xor a(64);
D(65) <= I(65) xor B(65) xor C(65) xor a(65);
D(66) <= I(66) xor B(66) xor C(66) xor a(66);
D(67) <= I(67) xor B(67) xor C(67) xor a(67);
D(68) <= I(68) xor B(68) xor C(68) xor a(68);
D(69) <= I(69) xor B(69) xor C(69) xor a(69);
D(70) <= I(70) xor B(70) xor C(70) xor a(70);
D(71) <= I(71) xor B(71) xor C(71) xor a(71);
D(72) <= I(72) xor B(72) xor C(72) xor a(72);
D(73) <= I(73) xor B(73) xor C(73) xor a(73);
D(74) <= I(74) xor B(74) xor C(74) xor a(74);
D(75) <= I(75) xor B(75) xor C(75) xor a(75);
D(76) <= I(76) xor B(76) xor C(76) xor a(76);
D(77) <= I(77) xor B(77) xor C(77) xor a(77);
D(78) <= I(78) xor B(78) xor C(78) xor a(78);
D(79) <= I(79) xor B(79) xor C(79) xor a(79);
D(80) <= I(80) xor B(80) xor C(80) xor a(80);
D(81) <= I(81) xor B(81) xor C(81) xor a(81);
D(82) <= I(82) xor B(82) xor C(82) xor a(82);
D(83) <= I(83) xor B(83) xor C(83) xor a(83);
D(84) <= I(84) xor B(84) xor C(84) xor a(84);
D(85) <= I(85) xor B(85) xor C(85) xor a(85);
D(86) <= I(86) xor B(86) xor C(86) xor a(86);
D(87) <= I(87) xor B(87) xor C(87) xor a(87);
D(88) <= I(88) xor B(88) xor C(88) xor a(88);
D(89) <= I(89) xor B(89) xor C(89) xor a(89);
D(90) <= I(90) xor B(90) xor C(90) xor a(90);
D(91) <= I(91) xor B(91) xor C(91) xor a(91);
D(92) <= I(92) xor B(92) xor C(92) xor a(92);
D(93) <= I(93) xor B(93) xor C(93) xor a(93);
D(94) <= I(94) xor B(94) xor C(94) xor a(94);
D(95) <= I(95) xor B(95) xor C(95) xor a(95);
D(96) <= I(96) xor B(96) xor C(96) xor a(96);
D(97) <= I(97) xor B(97) xor C(97) xor a(97);
D(98) <= I(98) xor B(98) xor C(98) xor a(98);
D(99) <= I(99) xor B(99) xor C(99) xor a(99);
D(100) <= I(100) xor B(100) xor C(100) xor a(100);
D(101) <= I(101) xor B(101) xor C(101) xor a(101);
D(102) <= I(102) xor B(102) xor C(102) xor a(102);
D(103) <= I(103) xor B(103) xor C(103) xor a(103);
D(104) <= I(104) xor B(104) xor C(104) xor a(104);
D(105) <= I(105) xor B(105) xor C(105) xor a(105);
D(106) <= I(106) xor B(106) xor C(106) xor a(106);
D(107) <= I(107) xor B(107) xor C(107) xor a(107);
D(108) <= I(108) xor B(108) xor C(108) xor a(108);
D(109) <= I(109) xor B(109) xor C(109) xor a(109);
D(110) <= I(110) xor B(110) xor C(110) xor a(110);
D(111) <= I(111) xor B(111) xor C(111) xor a(111);
D(112) <= I(112) xor B(112) xor C(112) xor a(112);
D(113) <= I(113) xor B(113) xor C(113) xor a(113);
D(114) <= I(114) xor B(114) xor C(114) xor a(114);
D(115) <= I(115) xor B(115) xor C(115) xor a(115);
D(116) <= I(116) xor B(116) xor C(116) xor a(116);
D(117) <= I(117) xor B(117) xor C(117) xor a(117);
D(118) <= I(118) xor B(118) xor C(118) xor a(118);
D(119) <= I(119) xor B(119) xor C(119) xor a(119);
D(120) <= I(120) xor B(120) xor C(120) xor a(120);
D(121) <= I(121) xor B(121) xor C(121) xor a(121);
D(122) <= I(122) xor B(122) xor C(122) xor a(122);
D(123) <= I(123) xor B(123) xor C(123) xor a(123);
D(124) <= I(124) xor B(124) xor C(124) xor a(124);
D(125) <= I(125) xor B(125) xor C(125) xor a(125);
D(126) <= I(126) xor B(126) xor C(126) xor a(126);
D(127) <= I(127) xor B(127) xor C(127) xor a(127);
D(128) <= I(128) xor B(128) xor C(128) xor a(128);
D(129) <= I(129) xor B(129) xor C(129) xor a(129);
D(130) <= I(130) xor B(130) xor C(130) xor a(130);
D(131) <= I(131) xor B(131) xor C(131) xor a(131);
D(132) <= I(132) xor B(132) xor C(132) xor a(132);
D(133) <= I(133) xor B(133) xor C(133) xor a(133);
D(134) <= I(134) xor B(134) xor C(134) xor a(134);
D(135) <= I(135) xor B(135) xor C(135) xor a(135);
D(136) <= I(136) xor B(136) xor C(136) xor a(136);
D(137) <= I(137) xor B(137) xor C(137) xor a(137);
D(138) <= I(138) xor B(138) xor C(138) xor a(138);
D(139) <= I(139) xor B(139) xor C(139) xor a(139);
D(140) <= I(140) xor B(140) xor C(140) xor a(140);
D(141) <= I(141) xor B(141) xor C(141) xor a(141);
D(142) <= I(142) xor B(142) xor C(142) xor a(142);
D(143) <= I(143) xor B(143) xor C(143) xor a(143);
D(144) <= I(144) xor B(144) xor C(144) xor a(144);
D(145) <= I(145) xor B(145) xor C(145) xor a(145);
D(146) <= I(146) xor B(146) xor C(146) xor a(146);
D(147) <= I(147) xor B(147) xor C(147) xor a(147);
D(148) <= I(148) xor B(148) xor C(148) xor a(148);
D(149) <= I(149) xor B(149) xor C(149) xor a(149);
D(150) <= I(150) xor B(150) xor C(150) xor a(150);
D(151) <= I(151) xor B(151) xor C(151) xor a(151);
D(152) <= I(152) xor B(152) xor C(152) xor a(152);
D(153) <= I(153) xor B(153) xor C(153) xor a(153);
D(154) <= I(154) xor B(154) xor C(154) xor a(154);
D(155) <= I(155) xor B(155) xor C(155) xor a(155);
D(156) <= I(156) xor B(156) xor C(156) xor a(156);
D(157) <= I(157) xor B(157) xor C(157) xor a(157);
D(158) <= I(158) xor B(158) xor C(158) xor a(158);
D(159) <= I(159) xor B(159) xor C(159) xor a(159);
D(160) <= I(160) xor B(160) xor C(160) xor a(160);
D(161) <= I(161) xor B(161) xor C(161) xor a(161);
D(162) <= I(162) xor B(162) xor C(162) xor a(162);
end;
|
gpl-3.0
|
d327e62fcb839569d38c409abaea7d23
| 0.520998 | 2.010526 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxr.vhd
| 4 | 3,693 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxr.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
configuration dlx_rtl of dlx is
for rtl
for alu_s1_reg : latch
use entity work.latch(behavior)
generic map ( Tpd => 2 ns );
end for;
for alu_s2_reg : latch
use entity work.latch(behavior)
generic map ( Tpd => 2 ns );
end for;
for the_alu : alu
use entity work.alu(behavior)
generic map ( Tpd => 4 ns );
end for;
for the_reg_file : reg_file
use entity work.reg_file(behavior)
generic map ( Tac => 4 ns );
end for;
for c_reg : latch
use entity work.latch(behavior)
generic map ( Tpd => 2 ns );
end for;
for a_reg : reg_multiple_out
use entity work.reg_multiple_out(behavior)
generic map ( num_outputs => num_outputs, Tpd => 2 ns );
end for;
for b_reg : reg_multiple_out
use entity work.reg_multiple_out(behavior)
generic map ( num_outputs => num_outputs, Tpd => 2 ns );
end for;
for temp_reg : reg_multiple_out
use entity work.reg_multiple_out(behavior)
generic map ( num_outputs => num_outputs, Tpd => 2 ns );
end for;
for iar_reg : reg_multiple_out
use entity work.reg_multiple_out(behavior)
generic map ( num_outputs => num_outputs, Tpd => 2 ns );
end for;
for pc_reg :reg_multiple_plus_one_out_reset
use entity work.reg_multiple_plus_one_out_reset(behavior)
generic map ( num_outputs => num_outputs, Tpd => 2 ns );
end for;
for mar_reg : reg_multiple_plus_one_out
use entity work.reg_multiple_plus_one_out(behavior)
generic map ( num_outputs => num_outputs, Tpd => 2 ns );
end for;
for mem_addr_mux : mux2
use entity work.mux2(behavior)
generic map ( Tpd => 1 ns );
end for;
for mdr_reg : reg_multiple_out
use entity work.reg_multiple_out(behavior)
generic map ( num_outputs => num_outputs, Tpd => 2 ns );
end for;
for mdr_mux : mux2
use entity work.mux2(behavior)
generic map ( Tpd => 1 ns );
end for;
for instr_reg : latch
use entity work.latch(behavior)
generic map ( Tpd => 2 ns );
end for;
for ir_extender1 : ir_extender
use entity work.ir_extender(behavior)
generic map ( Tpd => 2 ns );
end for;
for ir_extender2 : ir_extender
use entity work.ir_extender(behavior)
generic map ( Tpd => 2 ns );
end for;
for the_controller : controller
use entity work.controller(behavior)
generic map ( Tpd_clk_ctrl => 2 ns, Tpd_clk_const => 4 ns,
debug => debug );
end for;
end for; -- rtl of dlx
end configuration dlx_rtl;
|
gpl-2.0
|
e0bc0e264cb42d99d54a3fabc956cbe2
| 0.5987 | 3.795478 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc166.vhd
| 4 | 2,297 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc166.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x00p01n01i00166ent IS
END c04s03b03x00p01n01i00166ent;
ARCHITECTURE c04s03b03x00p01n01i00166arch OF c04s03b03x00p01n01i00166ent IS
BEGIN
TESTING: PROCESS
variable V1 : INTEGER := 1;
alias V1_A1 : INTEGER is V1;
variable pass : integer := 0;
BEGIN
assert V1 = 1;
assert V1_A1 = 1;
if (V1 /= 1 or V1_A1 /= 1) then
pass := 1;
end if;
V1 := 2; -- change value...
assert V1 = 2;
assert V1_A1 = 2; -- ... check read
if (V1 /= 2 or V1_A1 /= 2) then
pass := 1;
end if;
V1_A1 := 3; -- change value using alias
assert V1 = 3; -- ... check that value changed
assert V1_A1 = 3;
if (V1 /= 3 or V1_A1 /= 3) then
pass := 1;
end if;
wait for 5 ns;
assert NOT( pass = 0 )
report "***PASSED TEST: c04s03b03x00p01n01i00166"
severity NOTE;
assert ( pass = 0 )
report "***FAILED TEST: c04s03b03x00p01n01i00166 - Alias for variable object test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x00p01n01i00166arch;
|
gpl-2.0
|
0ac022c0aff16cba542e7001ac659032
| 0.609055 | 3.413076 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/SingleFile/divmul_163.vhd
| 1 | 3,750 |
-- Este bloque puede realizar la inversion de un elemento de F2m
-- o la multiplicación de dos elementos de F2m. Dicha operacion
-- es determinada por una señal de entrada. La inversión se realiza
-- implementando el Teorema de Fermat como una máquina de estados,
-- la multiplicación se realiza en m/4 ciclos de reloj con el
-- multiplicador serial a nivel de digito.
----------------------------------------------------------------
library IEEE;
----------------------------------------------------------------
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
----------------------------------------------------------------
entity inv_mul is
generic(
NUM_BITS : positive := 163
);
port(
A_x : in std_logic_vector(NUM_BITS-1 downto 0);
B_x : in std_logic_vector(NUM_BITS-1 downto 0);
clk : in std_logic;
rst : in std_logic;
op : in std_logic;
C_x : out std_logic_vector(NUM_BITS-1 downto 0);
done : out std_logic
);
end;
--------------------------------------------------------------
architecture behave of inv_mul is
--------------------------------------------------------------
-- Para la máquina de estados
type CurrentState_type is (END_STATE, SPEND_CYCLE1, SPEND_CYCLE2, WAIT_MUL, LAST_MUL);
signal CurrentState: CurrentState_type;
-- Señales de control para el multiplicador serial a nivel de digito
signal doneMul, rstMul : std_logic;
signal MUL, MUX1, MUX3 : std_logic_vector(NUM_BITS-1 downto 0);
signal counter: std_logic_vector(7 downto 0);
signal REG_Bx, MUX2, SQR: std_logic_vector(NUM_BITS-1 downto 0);
begin
MULTIPLIER1: ENTITY work.serial_multiplier_163(behave)
Generic Map (NUM_BITS)
PORT MAP(MUX1,MUX3, MUL, rstMul, clk, doneMul);
SQUARER1: ENTITY work.squarer_163(behave)
Generic Map (9,325,NUM_BITS)
PORT MAP(REG_Bx,SQR);
MUX1 <= B_x when op = '0' or CurrentState = LAST_MUL else -- solo cuando es una multiplicacion o se trata de la ultima multiplicacion
A_x;
MUX2 <= A_x when rst = '1' else
MUL;
MUX3 <= SQR when op = '1' else -- siempre que se trate de una division, de lo contrario Ax
A_x;
SEQ_PROC: process (CLK)
Begin
if CLK'event and CLK = '1' then
if rst = '1' then -- Se debe asegurar que al llegar la señal rst, los datos a la entrada son validos
C_x <= (others => '0');
Counter <= (others => '0');
Done <= '0';
rstMul <= '1';
if op = '1' then --division
REG_Bx <= MUX2;
CurrentState <= SPEND_CYCLE2;
else
CurrentState <= SPEND_CYCLE1;
end if;
else
case CurrentState is
when SPEND_CYCLE1 =>
rstMul <= '0';
CurrentState <= LAST_MUL;
when SPEND_CYCLE2 =>
rstMul <= '0';
CurrentState <= WAIT_MUL;
when LAST_MUL =>
if doneMul = '1' then
done <= '1';
C_x <= MUL;
currentState <= END_STATE;
end if;
when WAIT_MUL =>
if doneMul = '1' then
Counter <= Counter + "00000001";
REG_Bx <= MUX2;
if (Counter = "10100000") then -- lo tiene que hacer m -2 veces = 160
--ya termino la inversion, ahora tiene que realizar la multiplicacion para realizar la division
rstMul <= '1';
CurrentState <= SPEND_CYCLE1;
else
rstMul <= '1';
CurrentState <= SPEND_CYCLE2;
end if;
end if;
when END_STATE =>
CurrentState <= END_STATE;
when others =>
NULL;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
b92e4f4159f402869a867ea8da0c66d0
| 0.538667 | 3.561254 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/mb_lite/mem.vhd
| 3 | 4,137 |
----------------------------------------------------------------------------------------------
--
-- Input file : mem.vhd
-- Design name : mem
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Memory retrieves data words from a data memory. Memory file
-- access of byte, halfword and word sizes is supported. The sel_o
-- signal indicates which bytes should be read or written. The
-- responsibility for writing the right memory address is not within
-- this integer unit but should be handled by the external memory
-- device. This facilitates the addition of devices with different
-- bus sizes.
--
-- The dmem_i signals are directly connected to the decode and
-- execute components.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.core_Pkg.ALL;
USE work.std_Pkg.ALL;
ENTITY mem IS PORT
(
mem_o : OUT mem_out_type;
dmem_dat_o : OUT std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dmem_adr_o : OUT std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0);
dmem_sel_o : OUT std_ulogic_vector(3 DOWNTO 0);
dmem_we_o : OUT std_ulogic;
dmem_ena_o : OUT std_ulogic;
mem_i : IN mem_in_type;
ena_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END mem;
ARCHITECTURE arch OF mem IS
SIGNAL r, rin : mem_out_type;
SIGNAL mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
-- connect pipline signals
mem_o.ctrl_wb <= r.ctrl_wb;
mem_o.ctrl_mem_wb <= r.ctrl_mem_wb;
mem_o.alu_result <= r.alu_result;
-- connect memory interface signals
dmem_dat_o <= mem_result;
dmem_sel_o <= decode_mem_store(mem_i.alu_result(1 DOWNTO 0), mem_i.ctrl_mem.transfer_size);
dmem_we_o <= mem_i.ctrl_mem.mem_write;
dmem_adr_o <= mem_i.alu_result(CFG_DMEM_SIZE - 1 DOWNTO 0);
dmem_ena_o <= mem_i.ctrl_mem.mem_read OR mem_i.ctrl_mem.mem_write;
mem_comb: PROCESS(mem_i, mem_i.ctrl_wb, mem_i.ctrl_mem, r, r.ctrl_wb, r.ctrl_mem_wb)
VARIABLE v : mem_out_type;
VARIABLE intermediate : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
v := r;
v.ctrl_wb := mem_i.ctrl_wb;
IF mem_i.branch = '1' THEN
-- set alu result for branch and load instructions
v.alu_result := sign_extend(mem_i.program_counter, '0', 32);
ELSE
v.alu_result := mem_i.alu_result;
END IF;
-- Forward memory result
IF CFG_MEM_FWD_WB = true AND ( r.ctrl_mem_wb.mem_read AND compare(mem_i.ctrl_wb.reg_d, r.ctrl_wb.reg_d)) = '1' THEN
intermediate := align_mem_load(mem_i.mem_result, r.ctrl_mem_wb.transfer_size, r.alu_result(1 DOWNTO 0));
mem_result <= align_mem_store(intermediate, mem_i.ctrl_mem.transfer_size);
ELSE
mem_result <= mem_i.dat_d;
END IF;
v.ctrl_mem_wb.mem_read := mem_i.ctrl_mem.mem_read;
v.ctrl_mem_wb.transfer_size := mem_i.ctrl_mem.transfer_size;
rin <= v;
END PROCESS;
mem_seq: PROCESS(clk_i)
PROCEDURE proc_mem_reset IS
BEGIN
r.alu_result <= (OTHERS => '0');
r.ctrl_wb.reg_d <= (OTHERS => '0');
r.ctrl_wb.reg_write <= '0';
r.ctrl_mem_wb.mem_read <= '0';
r.ctrl_mem_wb.transfer_size <= WORD;
END PROCEDURE proc_mem_reset;
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
proc_mem_reset;
ELSIF ena_i = '1' THEN
r <= rin;
END IF;
END IF;
END PROCESS;
END arch;
|
mit
|
89c253d5079b66a75ed76deb2c97cbfe
| 0.534204 | 3.532878 | false | false | false | false |
mmoraless/ecc_vhdl
|
ecc_add/Lut_3in_131.vhd
| 1 | 5,569 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------------------------
entity lut_3in is
generic(
NUM_BITS: positive := 131
);
port (
A: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
s0: in STD_LOGIC;
B: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
D: out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end;
---------------------------------------------------------------------------------------------
architecture behave of lut_3in is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
begin
D(0) <= (A(0) and s0) xor B(0);
D(1) <= (A(1) and s0) xor B(1);
D(2) <= (A(2) and s0) xor B(2);
D(3) <= (A(3) and s0) xor B(3);
D(4) <= (A(4) and s0) xor B(4);
D(5) <= (A(5) and s0) xor B(5);
D(6) <= (A(6) and s0) xor B(6);
D(7) <= (A(7) and s0) xor B(7);
D(8) <= (A(8) and s0) xor B(8);
D(9) <= (A(9) and s0) xor B(9);
D(10) <= (A(10) and s0) xor B(10);
D(11) <= (A(11) and s0) xor B(11);
D(12) <= (A(12) and s0) xor B(12);
D(13) <= (A(13) and s0) xor B(13);
D(14) <= (A(14) and s0) xor B(14);
D(15) <= (A(15) and s0) xor B(15);
D(16) <= (A(16) and s0) xor B(16);
D(17) <= (A(17) and s0) xor B(17);
D(18) <= (A(18) and s0) xor B(18);
D(19) <= (A(19) and s0) xor B(19);
D(20) <= (A(20) and s0) xor B(20);
D(21) <= (A(21) and s0) xor B(21);
D(22) <= (A(22) and s0) xor B(22);
D(23) <= (A(23) and s0) xor B(23);
D(24) <= (A(24) and s0) xor B(24);
D(25) <= (A(25) and s0) xor B(25);
D(26) <= (A(26) and s0) xor B(26);
D(27) <= (A(27) and s0) xor B(27);
D(28) <= (A(28) and s0) xor B(28);
D(29) <= (A(29) and s0) xor B(29);
D(30) <= (A(30) and s0) xor B(30);
D(31) <= (A(31) and s0) xor B(31);
D(32) <= (A(32) and s0) xor B(32);
D(33) <= (A(33) and s0) xor B(33);
D(34) <= (A(34) and s0) xor B(34);
D(35) <= (A(35) and s0) xor B(35);
D(36) <= (A(36) and s0) xor B(36);
D(37) <= (A(37) and s0) xor B(37);
D(38) <= (A(38) and s0) xor B(38);
D(39) <= (A(39) and s0) xor B(39);
D(40) <= (A(40) and s0) xor B(40);
D(41) <= (A(41) and s0) xor B(41);
D(42) <= (A(42) and s0) xor B(42);
D(43) <= (A(43) and s0) xor B(43);
D(44) <= (A(44) and s0) xor B(44);
D(45) <= (A(45) and s0) xor B(45);
D(46) <= (A(46) and s0) xor B(46);
D(47) <= (A(47) and s0) xor B(47);
D(48) <= (A(48) and s0) xor B(48);
D(49) <= (A(49) and s0) xor B(49);
D(50) <= (A(50) and s0) xor B(50);
D(51) <= (A(51) and s0) xor B(51);
D(52) <= (A(52) and s0) xor B(52);
D(53) <= (A(53) and s0) xor B(53);
D(54) <= (A(54) and s0) xor B(54);
D(55) <= (A(55) and s0) xor B(55);
D(56) <= (A(56) and s0) xor B(56);
D(57) <= (A(57) and s0) xor B(57);
D(58) <= (A(58) and s0) xor B(58);
D(59) <= (A(59) and s0) xor B(59);
D(60) <= (A(60) and s0) xor B(60);
D(61) <= (A(61) and s0) xor B(61);
D(62) <= (A(62) and s0) xor B(62);
D(63) <= (A(63) and s0) xor B(63);
D(64) <= (A(64) and s0) xor B(64);
D(65) <= (A(65) and s0) xor B(65);
D(66) <= (A(66) and s0) xor B(66);
D(67) <= (A(67) and s0) xor B(67);
D(68) <= (A(68) and s0) xor B(68);
D(69) <= (A(69) and s0) xor B(69);
D(70) <= (A(70) and s0) xor B(70);
D(71) <= (A(71) and s0) xor B(71);
D(72) <= (A(72) and s0) xor B(72);
D(73) <= (A(73) and s0) xor B(73);
D(74) <= (A(74) and s0) xor B(74);
D(75) <= (A(75) and s0) xor B(75);
D(76) <= (A(76) and s0) xor B(76);
D(77) <= (A(77) and s0) xor B(77);
D(78) <= (A(78) and s0) xor B(78);
D(79) <= (A(79) and s0) xor B(79);
D(80) <= (A(80) and s0) xor B(80);
D(81) <= (A(81) and s0) xor B(81);
D(82) <= (A(82) and s0) xor B(82);
D(83) <= (A(83) and s0) xor B(83);
D(84) <= (A(84) and s0) xor B(84);
D(85) <= (A(85) and s0) xor B(85);
D(86) <= (A(86) and s0) xor B(86);
D(87) <= (A(87) and s0) xor B(87);
D(88) <= (A(88) and s0) xor B(88);
D(89) <= (A(89) and s0) xor B(89);
D(90) <= (A(90) and s0) xor B(90);
D(91) <= (A(91) and s0) xor B(91);
D(92) <= (A(92) and s0) xor B(92);
D(93) <= (A(93) and s0) xor B(93);
D(94) <= (A(94) and s0) xor B(94);
D(95) <= (A(95) and s0) xor B(95);
D(96) <= (A(96) and s0) xor B(96);
D(97) <= (A(97) and s0) xor B(97);
D(98) <= (A(98) and s0) xor B(98);
D(99) <= (A(99) and s0) xor B(99);
D(100) <= (A(100) and s0) xor B(100);
D(101) <= (A(101) and s0) xor B(101);
D(102) <= (A(102) and s0) xor B(102);
D(103) <= (A(103) and s0) xor B(103);
D(104) <= (A(104) and s0) xor B(104);
D(105) <= (A(105) and s0) xor B(105);
D(106) <= (A(106) and s0) xor B(106);
D(107) <= (A(107) and s0) xor B(107);
D(108) <= (A(108) and s0) xor B(108);
D(109) <= (A(109) and s0) xor B(109);
D(110) <= (A(110) and s0) xor B(110);
D(111) <= (A(111) and s0) xor B(111);
D(112) <= (A(112) and s0) xor B(112);
D(113) <= (A(113) and s0) xor B(113);
D(114) <= (A(114) and s0) xor B(114);
D(115) <= (A(115) and s0) xor B(115);
D(116) <= (A(116) and s0) xor B(116);
D(117) <= (A(117) and s0) xor B(117);
D(118) <= (A(118) and s0) xor B(118);
D(119) <= (A(119) and s0) xor B(119);
D(120) <= (A(120) and s0) xor B(120);
D(121) <= (A(121) and s0) xor B(121);
D(122) <= (A(122) and s0) xor B(122);
D(123) <= (A(123) and s0) xor B(123);
D(124) <= (A(124) and s0) xor B(124);
D(125) <= (A(125) and s0) xor B(125);
D(126) <= (A(126) and s0) xor B(126);
D(127) <= (A(127) and s0) xor B(127);
D(128) <= (A(128) and s0) xor B(128);
D(129) <= (A(129) and s0) xor B(129);
D(130) <= (A(130) and s0) xor B(130);
end;
|
gpl-3.0
|
ca5d24730b09e51dae168a4889168d91
| 0.460226 | 1.902631 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/float_generic_pkg-body.vhdl
| 4 | 231,104 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Floating-point package (Generic package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body float_generic_pkg is
-- Author David Bishop ([email protected])
-----------------------------------------------------------------------------
-- type declarations
-----------------------------------------------------------------------------
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant
-- types of boundary conditions
type boundary_type is (normal, infinity, zero, denormal);
-- null range array constant
constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- Special version of "minimum" to do some boundary checking
function mine (L, R : INTEGER)
return INTEGER is
begin -- function minimum
if (L = INTEGER'low or R = INTEGER'low) then
report float_generic_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- Generates the base number for the exponent normalization offset.
function gen_expon_base (
constant exponent_width : NATURAL)
return SIGNED
is
variable result : SIGNED (exponent_width-1 downto 0);
begin
result := (others => '1');
result (exponent_width-1) := '0';
return result;
end function gen_expon_base;
-- Integer version of the "log2" command (contributed by Peter Ashenden)
function log2 (A : NATURAL) return NATURAL is
variable quotient : NATURAL;
variable result : NATURAL := 0;
begin
quotient := A / 2;
while quotient > 0 loop
quotient := quotient / 2;
result := result + 1;
end loop;
return result;
end function log2;
-- Function similar to the ILOGB function in MATH_REAL
function log2 (A : REAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if (A = 1.0 or A = 0.0) then
return 0;
end if;
Y := A;
if(A > 1.0) then
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y * 2.0;
N := N - 1;
end loop;
return N;
end function log2;
-- purpose: Test the boundary conditions of a Real number
procedure test_boundary (
arg : in REAL; -- Input, converted to real
constant fraction_width : in NATURAL; -- length of FP output fraction
constant exponent_width : in NATURAL; -- length of FP exponent
constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP
variable btype : out boundary_type;
variable log2i : out INTEGER
) is
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
constant exp_min : SIGNED (12 downto 0) :=
-(resize(expon_base, 13)) + 1; -- Minimum normal exponent
constant exp_ext_min : SIGNED (12 downto 0) :=
exp_min - fraction_width; -- Minimum for denormal exponent
variable log2arg : INTEGER; -- log2 of argument
begin -- function test_boundary
-- Check to see if the exponent is big enough
-- Note that the argument is always an absolute value at this point.
log2arg := log2(arg);
if arg = 0.0 then
btype := zero;
elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)
btype := normal;
else
if log2arg < to_integer(exp_min) then
if denormalize then
if log2arg < to_integer(exp_ext_min) then
btype := zero;
else
btype := denormal;
end if;
else
if log2arg < to_integer(exp_min)-1 then
btype := zero;
else
btype := normal; -- Can still represent this number
end if;
end if;
elsif exponent_width < 11 then
if log2arg > to_integer(expon_base)+1 then
btype := infinity;
else
btype := normal;
end if;
else
btype := normal;
end if;
end if;
log2i := log2arg;
end procedure test_boundary;
-- purpose: Rounds depending on the state of the "round_style"
-- Logic taken from
-- "What Every Computer Scientist Should Know About Floating Point Arithmetic"
-- by David Goldberg (1991)
function check_round (
fract_in : STD_ULOGIC; -- input fraction
sign : STD_ULOGIC; -- sign bit
remainder : UNSIGNED; -- remainder to round from
sticky : STD_ULOGIC := '0'; -- Sticky bit
constant round_style : round_type) -- rounding type
return BOOLEAN
is
variable result : BOOLEAN;
variable or_reduced : STD_ULOGIC;
begin -- function check_round
result := false;
if (remainder'length > 0) then -- if remainder in a null array
or_reduced := or (remainder & sticky);
rounding_case : case round_style is
when round_nearest => -- Round Nearest, default mode
if remainder(remainder'high) = '1' then -- round
if (remainder'length > 1) then
if ((or (remainder(remainder'high-1
downto remainder'low)) = '1'
or sticky = '1')
or fract_in = '1') then
-- Make the bottom bit zero if possible if we are at 1/2
result := true;
end if;
else
result := (fract_in = '1' or sticky = '1');
end if;
end if;
when round_inf => -- round up if positive, else truncate.
if or_reduced = '1' and sign = '0' then
result := true;
end if;
when round_neginf => -- round down if negative, else truncate.
if or_reduced = '1' and sign = '1' then
result := true;
end if;
when round_zero => -- round toward 0 Truncate
null;
end case rounding_case;
end if;
return result;
end function check_round;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
procedure fp_round (
fract_in : in UNSIGNED; -- input fraction
expon_in : in SIGNED; -- input exponent
fract_out : out UNSIGNED; -- output fraction
expon_out : out SIGNED) is -- output exponent
begin -- procedure fp_round
if and (fract_in) = '1' then -- Fraction is all "1"
expon_out := expon_in + 1;
fract_out := to_unsigned(0, fract_out'high+1);
else
expon_out := expon_in;
fract_out := fract_in + 1;
end if;
end procedure fp_round;
-- This version of break_number doesn't call "classfp"
procedure break_number ( -- internal version
arg : in UNRESOLVED_float;
fptyp : in valid_fpstate;
denormalize : in BOOLEAN := true;
fract : out UNSIGNED;
expon : out SIGNED) is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable exp : SIGNED (expon'range);
begin
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (fraction_width) := '1';
exp := SIGNED(arg(exponent_width-1 downto 0));
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert NO_WARNING
report FLOAT_GENERIC_PKG'instance_name
& "BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a NAN goes in, a NAN comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- purpose: floating point to UNSIGNED
-- Used by to_integer, to_unsigned, and to_signed functions
procedure float_to_unsigned (
arg : in UNRESOLVED_float; -- floating point input
variable sign : out STD_ULOGIC; -- sign of output
variable frac : out UNSIGNED; -- unsigned biased output
constant denormalize : in BOOLEAN; -- turn on denormalization
constant bias : in NATURAL; -- bias for fixed point
constant round_style : in round_type) is -- rounding method
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable fract : UNSIGNED (frac'range); -- internal version of frac
variable isign : STD_ULOGIC; -- internal version of sign
variable exp : INTEGER; -- Exponent
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
-- Base to divide fraction by
variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable remainder : UNSIGNED (2 downto 0);
variable round : STD_ULOGIC; -- round BIT
begin
isign := to_x01(arg(arg'high));
-- exponent /= '0', normal floating point
expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (expon);
-- Figure out the fraction
fract := (others => '0'); -- fill with zero
fract (fract'high) := '1'; -- Add the "1.0".
shift := (fract'high-1) - exp;
if fraction_width > fract'high then -- Can only use size-2 bits
fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-fract'high)));
else -- can use all bits
fract (fract'high-1 downto fract'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := fract & "000";
if shift < 0 then -- Overflow
fract := (others => '1');
else
frac_shift := shift_right (frac_shift, shift);
fract := frac_shift (frac_shift'high downto 3);
remainder := frac_shift (2 downto 0);
-- round (round_zero will bypass this and truncate)
case round_style is
when round_nearest =>
round := remainder(2) and
(fract (0) or (or (remainder (1 downto 0))));
when round_inf =>
round := remainder(2) and not isign;
when round_neginf =>
round := remainder(2) and isign;
when others =>
round := '0';
end case;
if round = '1' then
fract := fract + 1;
end if;
end if;
frac := fract;
sign := isign;
end procedure float_to_unsigned;
-- purpose: returns a part of a vector, this function is here because
-- or (fractr (to_integer(shiftx) downto 0));
-- can't be synthesized in some synthesis tools.
function smallfract (
arg : UNSIGNED;
shift : NATURAL)
return STD_ULOGIC
is
variable orx : STD_ULOGIC;
begin
orx := arg(shift);
for i in arg'range loop
if i < shift then
orx := arg(i) or orx;
end if;
end loop;
return orx;
end function smallfract;
---------------------------------------------------------------------------
-- Visible functions
---------------------------------------------------------------------------
-- purpose: converts the negative index to a positive one
-- negative indices are illegal in 1164 and 1076.3
function to_sulv (
arg : UNRESOLVED_float) -- fp vector
return STD_ULOGIC_VECTOR
is
subtype result_subtype is STD_ULOGIC_VECTOR (arg'length-1 downto 0);
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin -- function to_std_ulogic_vector
if arg'length < 1 then
return NSLV;
end if;
result := result_subtype (arg);
return result;
end function to_sulv;
-- Converts an fp into an SULV
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_slv;
-- purpose: normalizes a floating point number
-- This version assumes an "unsigned" input with
function normalize (
fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign BIT
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction
variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction
variable exp : SIGNED (exponent_width+1 downto 0); -- exponent
variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent
variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result
variable shiftr : INTEGER; -- shift amount
variable stickyx : STD_ULOGIC; -- version of sticky
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round, zerores, infres : BOOLEAN;
begin -- function normalize
zerores := false;
infres := false;
round := false;
shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1"
- fraction_width - nguard; -- subtract the length we want
exp := resize (expon, exp'length) + shiftr;
if (or (fract) = '0') then -- Zero
zerores := true;
elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)
or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then
if (exp >= -resize(expon_base, exp'length)-fraction_width-1)
and denormalize then
exp := -resize(expon_base, exp'length)-1;
shiftr := -to_integer (expon + expon_base); -- new shift
else -- return zero
zerores := true;
end if;
elsif (exp > expon_base-1) then -- infinity
infres := true;
end if;
if zerores then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif infres then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
sfract := fract srl shiftr; -- shift
if shiftr > 0 then
-- stickyx := sticky or (or (fract (shiftr-1 downto 0)));
stickyx := sticky or smallfract (fract, shiftr-1);
else
stickyx := sticky;
end if;
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
sticky => stickyx,
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp(rexp'range),
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp(rexp'range);
end if;
-- result
rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));
rexpon (exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := UNRESOLVED_float(rexpon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
result (exponent_width) := sign; -- sign BIT
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with a "size_res" input
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -size_res'low;
constant exponent_width : NATURAL := size_res'high;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- Regular "normalize" function with a "size_res" input.
function normalize (
fract : UNRESOLVED_UNSIGNED; -- unsigned
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
begin
return normalize (fract => fract,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
end function normalize;
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate
is
constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : INTEGER := x'high; -- length of FP output exponent
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- classfp
if (arg'length < 1 or fraction_width < 3 or exponent_width < 3
or x'left < x'right) then
report FLOAT_GENERIC_PKG'instance_name
& "CLASSFP: " &
"Floating point number detected with a bad range"
severity error;
return isx;
end if;
-- Check for "X".
arg := to_01 (x, 'X');
if (arg(0) = 'X') then
return isx; -- If there is an X in the number
-- Special cases, check for illegal number
elsif check_error and
(and (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '1') then -- Exponent is all "1".
if or (to_slv (arg (-1 downto -fraction_width)))
/= '0' then -- Fraction must be all "0" or this is not a number.
if (arg(-1) = '1') then -- From "W. Khan - IEEE standard
return nan; -- 754 binary FP Signaling nan (Not a number)
else
return quiet_nan;
end if;
-- Check for infinity
elsif arg(exponent_width) = '0' then
return pos_inf; -- Positive infinity
else
return neg_inf; -- Negative infinity
end if;
-- check for "0"
elsif or (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '0' then -- Exponent is all "0"
if or (to_slv (arg (-1 downto -fraction_width)))
= '0' then -- Fraction is all "0"
if arg(exponent_width) = '0' then
return pos_zero; -- Zero
else
return neg_zero;
end if;
else
if arg(exponent_width) = '0' then
return pos_denormal; -- Denormal number (ieee extended fp)
else
return neg_denormal;
end if;
end if;
else
if arg(exponent_width) = '0' then
return pos_normal; -- Normal FP number
else
return neg_normal;
end if;
end if;
end function Classfp;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_UNSIGNED;
expon : out UNRESOLVED_SIGNED;
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => fract,
expon => expon);
end procedure break_number;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_ufixed; -- 1 downto -fraction_width
expon : out UNRESOLVED_SIGNED; -- exponent_width-1 downto 0
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => ufract,
expon => expon);
fract (0 downto -fraction_width) := ufixed (ufract);
end procedure break_number;
-- Arithmetic functions
function "abs" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := '0'; -- set the sign bit to positive
return result;
else
return NAFP;
end if;
end function "abs";
-- IEEE 754 "negative" function
function "-" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := not result (arg'high); -- invert sign bit
return result;
else
return NAFP;
end if;
end function "-";
-- Addition, adds two floating point numbers
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant addguard : NATURAL := guard; -- add one guard bit
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions
variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables
variable urfract, ulfract : UNSIGNED (fraction_width downto 0);
variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions
variable sign : STD_ULOGIC; -- sign of the output
variable leftright : BOOLEAN; -- left or right used
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- addition
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf and rfptype = neg_inf)
or (lfptype = neg_inf and rfptype = pos_inf) then
-- Return quiet NAN, IEEE754-1985-7.1,2
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0
fpresult := neg_zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl := (others => '0');
fractl (fraction_width+addguard downto addguard) := ulfract;
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr := (others => '0');
fractr (fraction_width+addguard downto addguard) := urfract;
shiftx := (exponl(exponent_width-1) & exponl) - exponr;
if shiftx < -fractl'high then
rexpon := exponr(exponent_width-1) & exponr;
fractc := fractr;
fracts := (others => '0'); -- add zero
leftright := false;
sticky := or (fractl);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (fractl, to_integer(shiftx));
fractc := fractr;
rexpon := exponr(exponent_width-1) & exponr;
leftright := false;
-- sticky := or (fractl (to_integer(shiftx) downto 0));
sticky := smallfract (fractl, to_integer(shiftx));
elsif shiftx = 0 then
rexpon := exponl(exponent_width-1) & exponl;
sticky := '0';
if fractr > fractl then
fractc := fractr;
fracts := fractl;
leftright := false;
else
fractc := fractl;
fracts := fractr;
leftright := true;
end if;
elsif shiftx > fractr'high then
rexpon := exponl(exponent_width-1) & exponl;
fracts := (others => '0'); -- add zero
fractc := fractl;
leftright := true;
sticky := or (fractr);
elsif shiftx > 0 then
fracts := shift_right (fractr, to_integer(shiftx));
fractc := fractl;
rexpon := exponl(exponent_width-1) & exponl;
leftright := true;
-- sticky := or (fractr (to_integer(shiftx) downto 0));
sticky := smallfract (fractr, to_integer(shiftx));
end if;
-- add
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if l(l'high) = r(r'high) then
ufract := fractc + fracts;
sign := l(l'high);
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
sign := l(l'high);
else
sign := r(r'high);
end if;
end if;
if or (ufract) = '0' then
sign := '0'; -- IEEE 854, 6.3, paragraph 2.
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => addguard);
end if;
return fpresult;
end function add;
-- Subtraction, Calls "add".
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable negr : UNRESOLVED_float (r'range); -- negative version of r
begin
negr := -r; -- r := -r
return add (l => l,
r => negr,
round_style => round_style,
guard => guard,
check_error => check_error,
denormalize => denormalize);
end function subtract;
-- Floating point multiply
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant multguard : NATURAL := guard; -- guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction
variable shifty : INTEGER; -- denormal shift
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif ((lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
fpresult (exponent_width) := fp_sign;
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
rfract := fractl * fractr; -- Multiply the fraction
sfract := rfract (rfract'high downto
rfract'high - (fraction_width+1+multguard));
sticky := or (rfract (rfract'high-(fraction_width+1+multguard)
downto 0));
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => multguard);
end if;
return fpresult;
end function multiply;
function short_divide (
lx, rx : UNSIGNED)
return UNSIGNED
is
-- This is a special divider for the floating point routines.
-- For a true unsigned divider, "stages" needs to = lx'high
constant stages : INTEGER := lx'high - rx'high; -- number of stages
variable partial : UNSIGNED (lx'range);
variable q : UNSIGNED (stages downto 0);
variable partial_argl : SIGNED (rx'high + 2 downto 0);
variable partial_arg : SIGNED (rx'high + 2 downto 0);
begin
partial := lx;
for i in stages downto 0 loop
partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)),
partial_argl'length);
partial_arg := partial_argl - SIGNED ("0" & rx);
if (partial_arg (partial_arg'high) = '1') then -- negative
q(i) := '0';
else
q(i) := '1';
partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=
UNSIGNED (partial_arg(rx'range));
end if;
end loop;
-- to make the output look like that of the unsigned IEEE divide.
return resize (q, lx'length);
end function short_divide;
-- 1/X function. Needed for algorithm development.
function reciprocal (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant divguard : NATURAL := guard; -- guard bits
function onedivy (
arg : UNSIGNED)
return UNSIGNED
is
variable q : UNSIGNED((2*arg'high)+1 downto 0);
variable one : UNSIGNED (q'range);
begin
one := (others => '0');
one(one'high) := '1';
q := short_divide (one, arg); -- Unsigned divide
return resize (q, arg'length+1);
end function onedivy;
variable fptype : valid_fpstate;
variable expon : SIGNED (exponent_width-1 downto 0); -- exponents
variable denorm_offset : NATURAL range 0 to 2;
variable fract : UNSIGNED (fraction_width downto 0);
variable fractg : UNSIGNED (fraction_width+divguard downto 0);
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- reciprocal
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- 1/inf, return 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_zero | pos_zero => -- 1/0
report FLOAT_GENERIC_PKG'instance_name
& "RECIPROCAL: Floating Point divide by zero"
severity error;
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
if (fptype = pos_denormal or fptype = neg_denormal)
and ((arg (-1) or arg(-2)) /= '1') then
-- 1/denormal = infinity, with the exception of 2**-expon_base
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult (exponent_width) := to_x01 (arg (exponent_width));
else
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => fract,
expon => expon);
fractg := (others => '0');
if (fptype = pos_denormal or fptype = neg_denormal) then
-- The reciprocal of a denormal number is typically zero,
-- except for two special cases which are trapped here.
if (to_x01(arg (-1)) = '1') then
fractg (fractg'high downto divguard+1) :=
fract (fract'high-1 downto 0); -- Shift to not denormal
denorm_offset := 1; -- add 1 to exponent compensate
else -- arg(-2) = '1'
fractg (fractg'high downto divguard+2) :=
fract (fract'high-2 downto 0); -- Shift to not denormal
denorm_offset := 2; -- add 2 to exponent compensate
end if;
else
fractg (fractg'high downto divguard) := fract;
denorm_offset := 0;
end if;
expon := - expon - 3 + denorm_offset;
sfract := onedivy (fractg);
-- normalize
fpresult := normalize (fract => sfract,
expon => expon,
sign => arg(exponent_width),
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end if;
end case classcase;
return fpresult;
end function reciprocal;
-- floating point division
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left
variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractl'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign, sticky : STD_ULOGIC; -- sign of result
variable shifty, shiftx : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divide
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf -- inf / inf
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_generic_pkg'instance_name
& "DIVIDE: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
-- Compute the exponent
rexpon := resize (exponl, rexpon'length) - exponr - 2;
if (rfptype = pos_denormal or rfptype = neg_denormal) then
-- Do the shifting here not after. That way we have a smaller
-- shifter, and need a smaller divider, because the top
-- bit in the divisor will always be a "1".
shifty := fraction_width - find_leftmost(urfract, '1');
urfract := shift_left (urfract, shifty);
rexpon := rexpon + shifty;
end if;
fractr := (others => '0');
fractr (fraction_width+divguard downto divguard) := urfract;
if (lfptype = pos_denormal or lfptype = neg_denormal) then
shiftx := fraction_width - find_leftmost(ulfract, '1');
ulfract := shift_left (ulfract, shiftx);
rexpon := rexpon - shiftx;
end if;
fractl := (others => '0');
fractl (fractl'high downto fractl'high-fraction_width) := ulfract;
-- divide
rfract := short_divide (fractl, fractr); -- unsigned divide
sfract := rfract (sfract'range); -- lower bits
sticky := '1';
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end case classcase2;
end case classcase;
return fpresult;
end function divide;
-- division by a power of 2
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divisionbyp2
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report FLOAT_GENERIC_PKG'instance_name
& "DIVIDEBYP2: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
assert (or (urfract (fraction_width-1 downto 0)) = '0')
report FLOAT_GENERIC_PKG'instance_name
& "DIVIDEBYP2: "
& "Dividebyp2 called with a non power of two divisor"
severity error;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 1;
-- normalize
fpresult := normalize (fract => ulfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase2;
end case classcase;
return fpresult;
end function dividebyp2;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL :=
-mine (mine(l'low, r'low), c'low); -- length of FP output fraction
constant exponent_width : NATURAL :=
maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent
variable lfptype, rfptype, cfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable fractx : UNSIGNED (fraction_width+guard downto 0);
variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction
variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent
variable shifty : INTEGER; -- denormal shift
variable shiftx : SIGNED (rexpon'range); -- shift fractions
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);
variable leftright : BOOLEAN; -- left or right used
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
cfptype := classfp (c, check_error);
end if;
if (lfptype = isx or rfptype = isx or cfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
cfptype = nan or cfptype = quiet_nan) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf
or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
cresize := resize (arg => to_x01(c),
exponent_width => exponent_width,
fraction_width => -cresize'low,
denormalize_in => denormalize,
denormalize => denormalize);
cfptype := classfp (cresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
break_number (
arg => cresize,
fptyp => cfptype,
denormalize => denormalize,
fract => fractx,
expon => exponc);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
shiftx := rexpon - exponc;
if shiftx < -fractl'high then
rexpon2 := resize (exponc, rexpon2'length);
fractc := "0" & fractx;
fracts := (others => '0');
sticky := or (rfract);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (rfract (rfract'high downto rfract'high
- fracts'length+1),
to_integer(shiftx));
fractc := "0" & fractx;
rexpon2 := resize (exponc, rexpon2'length);
leftright := false;
sticky := or (rfract (to_integer(shiftx)+rfract'high
- fracts'length downto 0));
elsif shiftx = 0 then
rexpon2 := resize (exponc, rexpon2'length);
sticky := or (rfract (rfract'high - fractc'length downto 0));
if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx
then
fractc := "0" & fractx;
fracts := rfract (rfract'high downto rfract'high
- fracts'length+1);
leftright := false;
else
fractc := rfract (rfract'high downto rfract'high
- fractc'length+1);
fracts := "0" & fractx;
leftright := true;
end if;
elsif shiftx > fractx'high then
rexpon2 := rexpon;
fracts := (others => '0');
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or (fractx & rfract (rfract'high - fractc'length
downto 0));
else -- fractx'high > shiftx > 0
rexpon2 := rexpon;
fracts := "0" & shift_right (fractx, to_integer (shiftx));
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or (fractx (to_integer (shiftx) downto 0)
& rfract (rfract'high - fractc'length downto 0));
end if;
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if fp_sign = to_X01(c(c'high)) then
ufract := fractc + fracts;
fp_sign := fp_sign;
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
fp_sign := fp_sign;
else
fp_sign := c(c'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon2,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end if;
return fpresult;
end function mac;
-- "rem" function
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractr'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (abs(l) < abs(r)) then
fpresult := l;
else
fp_sign := to_X01(l(l'high)); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fraction_width+divguard downto divguard) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponr(exponr'high)&exponr);
shifty := to_integer(exponl - rexpon);
if (shifty > 0) then
fractr := shift_right (fractr, shifty);
rexpon := rexpon + shifty;
end if;
if (fractr /= 0) then
-- rem
rfract := fractl rem fractr; -- unsigned rem
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
else
-- If we shift "fractr" so far that it becomes zero, return zero.
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
end if;
return fpresult;
end function remainder;
-- "mod" function
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
remres := remainder (l => abs(l),
r => abs(r),
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
-- MOD is the same as REM, but you do something different with
-- negative values
if (is_negative (l)) then
remres := - remres;
end if;
if (is_negative (l) = is_negative (r) or remres = 0) then
fpresult := remres;
else
fpresult := add (l => remres,
r => r,
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
end if;
end if;
return fpresult;
end function modulo;
-- Square root of a floating point number. Done using Newton's Iteration.
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable sign : STD_ULOGIC;
variable fpresult : float (arg'range);
variable fptype : valid_fpstate;
variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents
variable expon : SIGNED(exponent_width downto 0); -- exponents
variable ufact : ufixed (0 downto arg'low);
variable fact : ufixed (2 downto -fraction_width); -- fraction
variable resb : ufixed (fact'high+1 downto fact'low);
begin -- square root
fptype := Classfp (arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan |
-- Return quiet NAN, IEEE754-1985-7.1,1
neg_normal | neg_denormal | neg_inf => -- sqrt (neg)
-- Return quiet NAN, IEEE754-1985-7.1.6
fpresult := qnanfp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_inf => -- Sqrt (inf), return infinity
fpresult := pos_inffp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_zero => -- return 0
fpresult := zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when neg_zero => -- IEEE754-1985-6.3 return -0
fpresult := neg_zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when others =>
break_number (arg => arg,
denormalize => denormalize,
check_error => false,
fract => ufact,
expon => iexpon,
sign => sign);
expon := resize (iexpon+1, expon'length); -- get exponent
fact := resize (ufact, fact'high, fact'low);
if (expon(0) = '1') then
fact := fact sla 1; -- * 2.0
end if;
expon := shift_right (expon, 1); -- exponent/2
-- Newton's iteration - root := (1 + arg) / 2
resb := (fact + 1) sra 1;
for j in 0 to fraction_width/4 loop
-- root := (root + (arg/root))/2
resb := resize (arg => (resb + (fact/resb)) sra 1,
left_index => resb'high,
right_index => resb'low,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
end loop;
fpresult := normalize (fract => resb,
expon => expon-1,
sign => '0',
exponent_width => arg'high,
fraction_width => -arg'low,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end case classcase;
return fpresult;
end function sqrt;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is
-- Technically -0 should return "false", but I'm leaving that case out.
begin
return (to_x01(arg(arg'high)) = '1');
end function Is_Negative;
-- compare functions
-- =, /=, >=, <=, <, >
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : BOOLEAN;
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- equal
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return false;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := true;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
is_equal := (to_slv(lresize) = to_slv(rresize));
end if;
if (check_error) then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_equal and not is_unordered;
end function eq;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_less_than, is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_less_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (fractl < fractr);
else
is_less_than := (fractl > fractr); -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (expl < expr);
else
is_less_than := (expl > expr); -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = neg_zero and rfptype = pos_zero) then
is_less_than := false; -- -0 < 0 returns false.
else
is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_less_than and not is_unordered;
end function lt;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_greater_than : BOOLEAN;
variable is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- greater_than
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_greater_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := fractl > fractr;
else
is_greater_than := fractl < fractr; -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := expl > expr;
else
is_greater_than := expl < expr; -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = pos_zero and rfptype = neg_zero) then
is_greater_than := false; -- 0 > -0 returns false.
else
is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_greater_than and not is_unordered;
end function gt;
-- purpose: /= function
function ne ( -- not equal /=
l, r : UNRESOLVED_float;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_equal, is_unordered : BOOLEAN;
begin
is_equal := eq (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not (is_equal and not is_unordered);
end function ne;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_greater_than, is_unordered : BOOLEAN;
begin
is_greater_than := gt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_greater_than and not is_unordered;
end function le;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN
is
variable is_less_than, is_unordered : BOOLEAN;
begin
is_less_than := lt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_less_than and not is_unordered;
end function ge;
function "?=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := to_sulv(lresize) ?= to_sulv(rresize);
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return is_equal and not is_unordered;
end function "?=";
function "?/=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?/=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := to_sulv(lresize) ?= to_sulv(rresize);
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return not (is_equal and not is_unordered);
end function "?/=";
function "?>" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?>"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function "?>";
function "?>=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?>="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
function "?<" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?<"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function "?<";
function "?<=" (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_generic_pkg'instance_name
& " ""?<="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
function std_match (L, R : UNRESOLVED_float) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
report float_generic_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
-- These override the defaults for the compare operators.
function "=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return eq(l, r);
end function "=";
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ne(l, r);
end function "/=";
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ge(l, r);
end function ">=";
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return le(l, r);
end function "<=";
function ">" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return gt(l, r);
end function ">";
function "<" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return lt(l, r);
end function "<";
-- purpose: maximum of two numbers (overrides default)
function maximum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
-----------------------------------------------------------------------------
-- conversion functions
-----------------------------------------------------------------------------
-- Converts a floating point number of one format into another format
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
-- result value
variable fptype : valid_fpstate;
variable expon_in : SIGNED (in_exponent_width-1 downto 0);
variable fract_in : UNSIGNED (in_fraction_width downto 0);
variable round : BOOLEAN;
variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract
variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract
variable passguard : NATURAL;
begin
fptype := classfp(arg, check_error);
if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in
and (in_exponent_width < exponent_width
or in_fraction_width < fraction_width))
or in_exponent_width > exponent_width
or in_fraction_width > fraction_width then
-- size reduction
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf =>
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_inf =>
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero =>
result := zerofp (fraction_width => fraction_width, -- hate -0
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize_in,
fract => fract_in,
expon => expon_in);
if fraction_width > in_fraction_width and denormalize_in then
-- You only get here if you have a denormal input
fract_out := (others => '0'); -- pad with zeros
fract_out (fraction_width downto
fraction_width - in_fraction_width) := fract_in;
result := normalize (
fract => fract_out,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
else
result := normalize (
fract => fract_in,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => in_fraction_width - fraction_width);
end if;
end case classcase;
else -- size increase or the same size
if exponent_width > in_exponent_width then
expon_in := SIGNED(arg (in_exponent_width-1 downto 0));
if fptype = pos_zero or fptype = neg_zero then
result (exponent_width-1 downto 0) := (others => '0');
elsif expon_in = -1 then -- inf or nan (shorts out check_error)
result (exponent_width-1 downto 0) := (others => '1');
else
-- invert top BIT
expon_in(expon_in'high) := not expon_in(expon_in'high);
expon_out := resize (expon_in, expon_out'length); -- signed expand
-- Flip it back.
expon_out(expon_out'high) := not expon_out(expon_out'high);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);
end if;
result (exponent_width) := arg (in_exponent_width); -- sign
else -- exponent_width = in_exponent_width
result (exponent_width downto 0) := arg (in_exponent_width downto 0);
end if;
if fraction_width > in_fraction_width then
result (-1 downto -fraction_width) := (others => '0'); -- zeros
result (-1 downto -in_fraction_width) :=
arg (-1 downto -in_fraction_width);
else -- fraction_width = in_fraciton_width
result (-1 downto -fraction_width) :=
arg (-1 downto -in_fraction_width);
end if;
end if;
return result;
end function resize;
function resize (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
return result;
end if;
end function resize;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32 is
begin
return resize (arg => arg,
exponent_width => float32'high,
fraction_width => -float32'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64 is
begin
return resize (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128 is
begin
return resize (arg => arg,
exponent_width => float128'high,
fraction_width => -float128'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float128;
-- to_float (Real)
-- typically not Synthesizable unless the input is a constant.
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_real : REAL; -- Real version of argument
variable validfp : boundary_type; -- Check for valid results
variable exp : INTEGER; -- Integer version of exponent
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable frac : REAL; -- Real version of fraction
constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding
variable round : BOOLEAN; -- to round or not to round
begin
result := (others => '0');
arg_real := arg;
if arg_real < 0.0 then
result (exponent_width) := '1';
arg_real := - arg_real; -- Make it positive.
else
result (exponent_width) := '0';
end if;
test_boundary (arg => arg_real,
fraction_width => fraction_width,
exponent_width => exponent_width,
denormalize => denormalize,
btype => validfp,
log2i => exp);
if validfp = zero then
return result; -- Result initialized to "0".
elsif validfp = infinity then
result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1"
-- return infinity.
return result;
else
if validfp = denormal then -- Exponent will default to "0".
expon := (others => '0');
frac := arg_real * (2.0 ** (to_integer(expon_base)-1));
else -- Number less than 1. "normal" number
expon := UNSIGNED (to_signed (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.
end if;
for i in 0 to fract'high loop
if frac >= 2.0 ** (-1 - i) then
fract (fract'high - i) := '1';
frac := frac - 2.0 ** (-1 - i);
else
fract (fract'high - i) := '0';
end if;
end loop;
round := false;
case round_style is
when round_nearest =>
if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if frac /= 0.0 and result(exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if frac /= 0.0 and result(exponent_width) = '1' then
round := true;
end if;
when others =>
null; -- don't round
end case;
if (round) then
if and(fract) = '1' then -- fraction is all "1"
expon := expon + 1;
fract := (others => '0');
else
fract := fract + 1;
end if;
end if;
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
return result;
end if;
end function to_float;
-- to_float (Integer)
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : NATURAL; -- Natural version of argument
variable expon : SIGNED (exponent_width-1 downto 0);
variable exptmp : SIGNED (exponent_width-1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');
variable fracttmp : UNSIGNED (fraction_width-1 downto 0);
variable round : BOOLEAN;
variable shift : NATURAL;
variable shiftr : NATURAL;
variable roundfrac : NATURAL; -- used in rounding
begin
if arg < 0 then
result (exponent_width) := '1';
arg_int := -arg; -- Make it positive.
else
result (exponent_width) := '0';
arg_int := arg;
end if;
if arg_int = 0 then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- If the number is larger than we can represent in this number system
-- we need to return infinity.
shift := log2(arg_int);
if shift > to_integer(expon_base) then
-- worry about infinity
if result (exponent_width) = '0' then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- return negative infinity.
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
else -- Normal number (can't be denormal)
-- Compute Exponent
expon := to_signed (shift-1, expon'length); -- positive fraction.
-- Compute Fraction
arg_int := arg_int - 2**shift; -- Subtract off the 1.0
shiftr := shift;
for I in fract'high downto maximum (fract'high - shift + 1, 0) loop
shiftr := shiftr - 1;
if (arg_int >= 2**shiftr) then
arg_int := arg_int - 2**shiftr;
fract(I) := '1';
else
fract(I) := '0';
end if;
end loop;
-- Rounding routine
round := false;
if arg_int > 0 then
roundfrac := 2**(shiftr-1);
case round_style is
when round_nearest =>
if arg_int > roundfrac or
((arg_int = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if arg_int /= 0 and result (exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if arg_int /= 0 and result (exponent_width) = '1' then
round := true;
end if;
when others =>
null;
end case;
end if;
if round then
fp_round(fract_in => fract,
expon_in => expon,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
expon := exptmp;
end if;
-- Put the number together and return
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
end if;
return result;
end function to_float;
-- to_float (unsigned)
function to_float (
arg : UNRESOLVED_UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg
begin
if arg'length < 1 then
return NAFP;
end if;
sarg (XARG'range) := SIGNED (XARG);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style);
return result;
end function to_float;
-- to_float (signed)
function to_float (
arg : UNRESOLVED_SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable arg_int : UNSIGNED(xarg'range); -- Real version of argument
variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable rfract : UNSIGNED (fraction_width-1 downto 0);
variable sign : STD_ULOGIC; -- sign bit
begin
if arg'length < 1 then
return NAFP;
end if;
if Is_X (xarg) then
result := (others => 'X');
elsif (xarg = 0) then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- Normal number (can't be denormal)
sign := to_X01(xarg (xarg'high));
arg_int := UNSIGNED(abs (to_01(xarg)));
-- Compute Exponent
argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2
if argb2 > UNSIGNED(expon_base) then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
result (exponent_width) := sign;
else
exp := SIGNED(resize(argb2, exp'length));
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract (0),
sign => sign,
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := (others => '0');
rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
result (exponent_width) := sign;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
end if;
return result;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float
is
variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if arg'length < 1 then
return NAFP;
end if;
fpvar := UNRESOLVED_float(arg);
return fpvar;
end function to_float;
-- purpose: converts a ufixed to a floating point
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float
is
variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- function to_float
if (arg'length < 1) then
return NAFP;
end if;
sarg (arg'range) := sfixed (arg);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style,
denormalize => denormalize);
return result;
end function to_float;
function to_float (
arg : UNRESOLVED_sfixed; -- signed fixed point
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float
is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : sfixed (integer_width downto in_fraction_width);
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width - 1
downto 0); -- signed version of argument
variable argx : SIGNED (integer_width - in_fraction_width downto 0);
variable exp, exptmp : SIGNED (exponent_width downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin
if (arg'length < 1) then
return NAFP;
end if;
xresult := to_01(arg, 'X');
argx := SIGNED(to_slv(xresult));
if (Is_X (arg)) then
result := (others => 'X');
elsif (argx = 0) then
result := (others => '0');
else
result := (others => '0'); -- zero out the result
if argx(argx'left) = '1' then -- toss the sign bit
result (exponent_width) := '1'; -- Negative number
argx := -argx; -- Make it positive.
else
result (exponent_width) := '0';
end if;
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx(arg_int'range))));
-- Compute Exponent
exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result (-1 downto -fraction_width) := (others => '0');
result (exponent_width -1 downto 0) := (others => '1');
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize(exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
return result;
end function to_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- to_integer (float)
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER
is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (-arg'low downto 0); -- Fraction
variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction
variable expon : SIGNED (arg'high-1 downto 0);
variable isign : STD_ULOGIC; -- internal version of sign
variable round : STD_ULOGIC; -- is rounding needed?
variable result : INTEGER;
variable base : INTEGER; -- Integer exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := 0; -- return 0
when pos_inf =>
result := INTEGER'high;
when neg_inf =>
result := INTEGER'low;
when others =>
break_number (
arg => arg,
fptyp => validfp,
denormalize => false,
fract => frac,
expon => expon);
fract (fract'high) := '0'; -- Add extra bit for 0.6 case
fract (fract'high-1 downto 0) := frac;
isign := to_x01 (arg (arg'high));
base := to_integer (expon) + 1;
if base < -1 then
result := 0;
elsif base >= frac'high then
result := to_integer (fract) * 2**(base - frac'high);
else -- We need to round
if base = -1 then -- trap for 0.6 case.
result := 0;
else
result := to_integer (fract (frac'high downto frac'high-base));
end if;
-- rounding routine
case round_style is
when round_nearest =>
if frac'high - base > 1 then
round := fract (frac'high - base - 1) and
(fract (frac'high - base)
or (or (fract (frac'high - base - 2 downto 0))));
else
round := fract (frac'high - base - 1) and
fract (frac'high - base);
end if;
when round_inf =>
round := fract(frac'high - base - 1) and not isign;
when round_neginf =>
round := fract(frac'high - base - 1) and isign;
when others =>
round := '0';
end case;
if round = '1' then
result := result + 1;
end if;
end if;
if isign = '1' then
result := - result;
end if;
end case classcase;
return result;
end function to_integer;
-- to_unsigned (float)
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED
is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction
variable sign : STD_ULOGIC; -- not used
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1');
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
end case classcase;
return (frac);
end function to_unsigned;
-- to_signed (float)
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED
is
variable sign : STD_ULOGIC; -- true if negative
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNRESOLVED_UNSIGNED (size-1 downto 0); -- Fraction
variable result : UNRESOLVED_SIGNED (size-1 downto 0);
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := (others => '0'); -- return 0
when pos_inf =>
result := (others => '1');
result (result'high) := '0';
when neg_inf =>
result := (others => '0');
result (result'high) := '1';
when others =>
float_to_unsigned (
arg => arg,
sign => sign,
frac => frac,
denormalize => false,
bias => 0,
round_style => round_style);
result (size-1) := '0';
result (size-2 downto 0) := UNRESOLVED_SIGNED(frac (size-2 downto 0));
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if frac(frac'high) = '1' then -- return most negative number
result := (others => '0');
result (result'high) := '1';
else
result := -result;
end if;
else
if frac(frac'high) = '1' then -- return most positive number
result := (others => '1');
result (result'high) := '0';
end if;
end if;
end case classcase;
return result;
end function to_signed;
-- purpose: Converts a float to ufixed
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);
variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result
begin -- function to_ufixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1'); -- always saturate
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
-- Figure out the fraction
if (validfp = pos_denormal) and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Remove the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
end case classcase;
result_big := to_ufixed (
arg => STD_ULOGIC_VECTOR(frac),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- purpose: Converts a float to sfixed
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable sign : BOOLEAN; -- true if negative
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable rsigned : SIGNED (size-1 downto 0); -- signed version of result
variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);
variable result : UNRESOLVED_sfixed (left_index downto right_index)
:= (others => '0'); -- result
begin -- function to_sfixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero =>
result := (others => '0'); -- return 0
when neg_inf =>
result (left_index) := '1'; -- return smallest negative number
when pos_inf =>
result := (others => '1'); -- return largest number
result (left_index) := '0';
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
if arg(exponent_width) = '0' then
sign := false;
else
sign := true;
end if;
-- Figure out the fraction
if (validfp = pos_denormal or validfp = neg_denormal)
and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
if not sign then
rsigned := SIGNED("0" & frac);
else
rsigned := -(SIGNED("0" & frac));
end if;
result_big := to_sfixed (
arg => STD_LOGIC_VECTOR(rsigned),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
end case classcase;
return result;
end function to_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED
is
variable result : UNRESOLVED_UNSIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_unsigned (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_unsigned;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED
is
variable result : UNRESOLVED_SIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_signed (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_signed;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_sfixed;
-- to_real (float)
-- typically not Synthesizable unless the input is a constant.
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL
is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable validfp : valid_fpstate; -- Valid FP state
variable expon : UNSIGNED (exponent_width - 1 downto 0)
:= (others => '1'); -- Vectorized exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | pos_zero | neg_zero | nan | quiet_nan =>
return 0.0;
when neg_inf =>
return REAL'low; -- Negative infinity.
when pos_inf =>
return REAL'high; -- Positive infinity
when others =>
expon_base := 2**(exponent_width-1) -1;
if to_X01(arg(exponent_width)) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
-- Figure out the fraction
for i in 0 to fraction_width-1 loop
if to_X01(arg (-1 - i)) = '1' then
frac := frac + (2.0 **(-1 - i));
end if;
end loop; -- i
if validfp = pos_normal or validfp = neg_normal or not denormalize then
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
sign := sign * (2.0 ** exp) * (1.0 + frac);
else -- exponent = '0', IEEE extended floating point
exp := 1 - expon_base;
sign := sign * (2.0 ** exp) * frac;
end if;
return sign;
end case classcase;
end function to_real;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_sulv (result);
end function realtobits;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
-- purpose: Removes meta-logical values from FP string
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (arg'range);
begin -- function to_01
if (arg'length < 1) then
assert NO_WARNING
report FLOAT_GENERIC_PKG'instance_name
& "TO_01: null detected, returning NULL"
severity warning;
return NAFP;
end if;
result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));
return result;
end function to_01;
function Is_X
(arg : UNRESOLVED_float)
return BOOLEAN is
begin
return Is_X (to_slv(arg));
end function Is_X;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report FLOAT_GENERIC_PKG'instance_name
& "TO_X01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01(to_slv(arg)));
return result;
end if;
end function to_X01;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report FLOAT_GENERIC_PKG'instance_name
& "TO_X01Z: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01Z(to_slv(arg)));
return result;
end if;
end function to_X01Z;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report FLOAT_GENERIC_PKG'instance_name
& "TO_UX01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_UX01(to_slv(arg)));
return result;
end if;
end function to_UX01;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return add (l, r);
end function "+";
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return subtract (l, r);
end function "-";
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return multiply (l, r);
end function "*";
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return divide (l, r);
end function "/";
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return remainder (l, r);
end function "rem";
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return modulo (l, r);
end function "mod";
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
-- ?= overloads
function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?= r_float;
end function "?=";
function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?/= r_float;
end function "?/=";
function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?> r_float;
end function "?>";
function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?>= r_float;
end function "?>=";
function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?< r_float;
end function "?<";
function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?<= r_float;
end function "?<=";
-- real and float
function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?= r;
end function "?=";
function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?/= r;
end function "?/=";
function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?> r;
end function "?>";
function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?>= r;
end function "?>=";
function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?< r;
end function "?<";
function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?<= r;
end function "?<=";
-- ?= overloads
function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?= r_float;
end function "?=";
function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?/= r_float;
end function "?/=";
function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?> r_float;
end function "?>";
function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?>= r_float;
end function "?>=";
function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?< r_float;
end function "?<";
function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return l ?<= r_float;
end function "?<=";
-- integer and float
function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?= r;
end function "?=";
function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?/= r;
end function "?/=";
function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?> r;
end function "?>";
function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?>= r;
end function "?>=";
function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?< r;
end function "?<";
function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return l_float ?<= r;
end function "?<=";
-- minimum and maximum overloads
function minimum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
function minimum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float
is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float
is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_float (RESULT, L'high, -L'low);
end function "not";
function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report float_generic_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "and";
function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report float_generic_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report float_generic_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report float_generic_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report float_generic_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report float_generic_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L and to_sulv(R));
return result;
end function "and";
function "and" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) and R);
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L or to_sulv(R));
return result;
end function "or";
function "or" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) or R);
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L nand to_sulv(R));
return result;
end function "nand";
function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) nand R);
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L nor to_sulv(R));
return result;
end function "nor";
function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) nor R);
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L xor to_sulv(R));
return result;
end function "xor";
function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) xor R);
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (R'range);
begin
result := UNRESOLVED_float (L xnor to_sulv(R));
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (L'range);
begin
result := UNRESOLVED_float (to_sulv(L) xnor R);
return result;
end function "xnor";
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return and to_sulv(l);
end function "and";
function "nand" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nand to_sulv(l);
end function "nand";
function "or" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return or to_sulv(l);
end function "or";
function "nor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nor to_sulv(l);
end function "nor";
function "xor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xor to_sulv(l);
end function "xor";
function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xnor to_sulv(l);
end function "xnor";
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (
x, y : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
begin
return y(y'high) & x (x'high-1 downto x'low);
end function Copysign;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction
constant exponent_width : NATURAL := y'high; -- length of FP output exponent
variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
variable exp : SIGNED (exponent_width downto 0);
variable ufract : UNSIGNED (fraction_width downto 0);
constant expon_base : SIGNED (exponent_width-1 downto 0)
:= gen_expon_base(exponent_width); -- exponent offset
variable fptype : valid_fpstate;
begin
-- This can be done by simply adding N to the exponent.
arg := to_01 (y, 'X');
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => ufract,
expon => expon);
exp := resize (expon, exp'length) + N;
result := normalize (
fract => ufract,
expon => exp,
sign => to_x01 (arg (arg'high)),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase;
return result;
end function Scalb;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : UNRESOLVED_SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float
is
variable n_int : INTEGER;
begin
n_int := to_integer(N);
return Scalb (y => y,
N => n_int,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
end function Scalb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return INTEGER
is
constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : INTEGER; -- result
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width - 1 downto 0);
variable fract : UNSIGNED (fraction_width downto 0);
constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent
-- offset +1
variable fptype : valid_fpstate;
begin
-- Just return the exponent.
arg := to_01 (x, 'X');
fptype := classfp(arg);
classcase : case fptype is
when isx | nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := 0;
when pos_denormal | neg_denormal =>
fract (fraction_width) := '0';
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
result := find_leftmost (fract, '1') -- Find the first "1"
- fraction_width; -- subtract the length we want
result := -expon_base + 1 + result;
when others =>
expon := SIGNED(arg (exponent_width - 1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
expon := expon + 1;
result := to_integer (expon);
end case classcase;
return result;
end function Logb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return UNRESOLVED_SIGNED
is
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : SIGNED (exponent_width - 1 downto 0); -- result
begin
-- Just return the exponent.
result := to_signed (Logb (x), exponent_width);
return result;
end function Logb;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float
is
constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
function "=" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function "="
return eq (l => l,
r => r,
check_error => false);
end function "=";
function ">" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function ">"
return gt (l => l,
r => r,
check_error => false);
end function ">";
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable expon : UNSIGNED (exponent_width-1 downto 0);
variable sign : STD_ULOGIC;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable validfpx, validfpy : valid_fpstate; -- Valid FP state
begin -- fp_Nextafter
-- If Y > X, add one to the fraction, otherwise subtract.
validfpx := classfp (x, check_error);
validfpy := classfp (y, check_error);
if validfpx = isx or validfpy = isx then
result := (others => 'X');
return result;
elsif (validfpx = nan or validfpy = nan) then
return nanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (validfpx = quiet_nan or validfpy = quiet_nan) then
return qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif x = y then -- Return X
return x;
else
fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction
expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent
sign := x(exponent_width); -- sign bit
if (y > x) then
-- Increase the number given
if validfpx = neg_inf then
-- return most negative number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero or validfpx = neg_zero then
-- return smallest denormal number
sign := '0';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = pos_normal then
if and (fract) = '1' then -- fraction is all "1".
if and (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report FLOAT_GENERIC_PKG'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1;
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = pos_denormal then
if and (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = neg_normal then
if or (fract) = '0' then -- fraction is all "0".
if or (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest negative denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = neg_denormal then
if or (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
else
-- Decrease the number
if validfpx = pos_inf then
-- return most positive number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero
or classfp (x) = neg_zero then
-- return smallest negative denormal number
sign := '1';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = neg_normal then
if and (fract) = '1' then -- fraction is all "1".
if and (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report FLOAT_GENERIC_PKG'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1; -- Fraction overflow
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = neg_denormal then
if and (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = pos_normal then
if or (fract) = '0' then -- fraction is all "0".
if or (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest positive denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = pos_denormal then
if or (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
end if;
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);
result (exponent_width) := sign;
return result;
end if;
end function Nextafter;
-- Returns True if X is unordered with Y.
function Unordered (
x, y : UNRESOLVED_float) -- floating point input
return BOOLEAN
is
variable lfptype, rfptype : valid_fpstate;
begin
lfptype := classfp (x);
rfptype := classfp (y);
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
lfptype = isx or rfptype = isx) then
return true;
else
return false;
end if;
end function Unordered;
function Finite (
x : UNRESOLVED_float)
return BOOLEAN
is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = pos_inf) or (fp_state = neg_inf) then
return true;
else
return false;
end if;
end function Finite;
function Isnan (
x : UNRESOLVED_float)
return BOOLEAN
is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = nan) or (fp_state = quiet_nan) then
return true;
else
return false;
end if;
end function Isnan;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
return result;
end function zerofp;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-1) := '1'; -- MSB of Fraction "1"
-- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point"
-- The difference between a signaling NAN and a quiet NAN is that
-- the MSB of the Fraction is a "1" in a Signaling NAN, and is a
-- "0" in a quiet NAN.
return result;
end function nanfp;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-fraction_width) := '1'; -- LSB of Fraction "1"
-- (Could have been any bit)
return result;
end function qnanfp;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1"
return result;
end function pos_inffp;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width downto 0) := (others => '1'); -- top bits all "1"
return result;
end function neg_inffp;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width) := '1';
return result;
end function neg_zerofp;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function zerofp;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return nanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function nanfp;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return qnanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function qnanfp;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return pos_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function pos_inffp;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_inffp;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_zerofp;
-- Textio functions
-- purpose: writes float into a line (NOTE changed basetype)
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
c := l (l'left);
if (c = ' ' or c = NBSP or c = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- purpose: Checks the punctuation in a line
procedure check_punctuation (
arg : in STRING;
colon : out BOOLEAN; -- There was a colon in the line
dot : out BOOLEAN; -- There was a dot in the line
good : out BOOLEAN; -- True if enough characters found
chars : in INTEGER) is
-- Examples. Legal inputs are "0000000", "0000.000", "0:000:000"
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable icolon, idot : BOOLEAN; -- internal
variable j : INTEGER := 0; -- charters read
begin
good := false;
icolon := false;
idot := false;
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then
exit;
elsif xarg(i) = ':' then
icolon := true;
elsif xarg(i) = '.' then
idot := true;
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
if j = chars then
good := true; -- There are enough charactes to read
end if;
colon := icolon;
if idot and icolon then
dot := false;
else
dot := idot;
end if;
end procedure check_punctuation;
-- purpose: Searches a line for a ":" and replaces it with a ".".
procedure fix_colon (
arg : inout STRING;
chars : in integer) is
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable j : INTEGER := 0; -- charters read
begin
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then
exit;
elsif xarg(i) = ':' then
xarg (i) := '.';
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
end procedure fix_colon;
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_float; -- floating point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
WRITE (L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable readOk : BOOLEAN;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report float_generic_pkg'instance_name
& "READ(float): "
& "Error end of file encountered."
severity error;
return;
elsif c = ' ' or c = CR or c = HT then -- reading done.
if (i /= value'low) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Warning: Value truncated."
severity warning;
return;
end if;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
report float_generic_pkg'instance_name
& "READ(float): "
& "String begins with an ""_""" severity error;
return;
elsif lastu then -- "__" detected
report float_generic_pkg'instance_name
& "READ(float): "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
if not (i = -1 or i = value'high-1) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Warning: Separator point does not match number format: '"
& c & "' encountered at location " & INTEGER'image(i) & "."
severity warning;
end if;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
report float_generic_pkg'instance_name
& "READ(float): "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
good := false;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
return;
elsif c = ' ' or c = CR or c = HT then -- reading done
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
-- good := (i = -1 or i = value'high-1);
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/3)
& " valid octal characters."
severity error;
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (2 downto 1) /= "00" then
report float_generic_pkg'instance_name & "OREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
report float_generic_pkg'instance_name & "OREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_generic_pkg'instance_name & "OREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (2 downto 1) /= "00" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure OREAD;
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/4)
& " valid hex characters."
severity error;
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (3 downto 1) /= "000" then
report float_generic_pkg'instance_name & "HREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
report float_generic_pkg'instance_name & "HREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_generic_pkg'instance_name & "HREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (3 downto 1) /= "000" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
return;
end if;
if (or (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_float) return STRING is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
return s;
end function to_string;
function to_hstring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_hstring (slv);
end function to_hstring;
function to_ostring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_ostring (slv);
end function to_ostring;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report FLOAT_GENERIC_PKG'instance_name
& "from_string: Bad string " & bstring
severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report FLOAT_GENERIC_PKG'instance_name
& "from_ostring: Bad string " & ostring
severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float
is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report FLOAT_GENERIC_PKG'instance_name
& "from_hstring: Bad string " & hstring
severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_string (bstring => bstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_ostring (ostring => ostring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_hstring (hstring => hstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_hstring;
end package body float_generic_pkg;
|
gpl-2.0
|
3ce7ea408c2a22f6155dc7261423250e
| 0.54559 | 4.252378 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a-Dlx.vhd
| 1 | 5,719 |
--------------------------------------------------------------------------------
-- FILE: Dlx
-- DESC: Toplevel of DLX micro-processor
--
-- Author:
-- Create: 2015-05-24
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Dlx is
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
DRCW_SIZE : integer := C_CTR_DRCW_SIZE
);
port (
clk : in std_logic := '0';
rst : in std_logic := '0'; -- Active Low
en_iram: out std_logic:='1';
pc_bus : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
ir_bus : in std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
en_dram : out std_logic:='1';
addr_bus : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
di_bus : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
do_bus : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
dr_cw : out std_logic_vector(DRCW_SIZE-1 downto 0):=(others=>'0')
);
end Dlx;
architecture dlx_arch of Dlx is
-- Control Unit
component ControlUnit is
generic(
ISTR_SIZE : integer := C_SYS_ISTR_SIZE; -- Instruction Register Size
DATA_SIZE : integer := C_SYS_DATA_SIZE; -- Data Size
OPCD_SIZE : integer := C_SYS_OPCD_SIZE; -- Op Code Size
FUNC_SIZE : integer := C_SYS_FUNC_SIZE; -- Func Field Size for R-Type Ops
CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Control Word Size
CALU_SIZE : integer := C_CTR_CALU_SIZE; -- ALU Op Code Word Size
ADDR_SIZE : integer := C_SYS_ADDR_SIZE -- Address size
);
port(
clk : in std_logic;
rst : in std_logic;
ir : in std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
pc : in std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
reg_a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
ld_a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
sig_bal : in std_logic:='0';
sig_bpw : out std_logic:='0';
sig_jral: in std_logic:='0';
sig_ral : in std_logic;
sig_mul : in std_logic;
sig_div : in std_logic;
sig_sqrt: in std_logic;
cw : out std_logic_vector(CWRD_SIZE-1 downto 0);
calu : out std_logic_vector(CALU_SIZE-1 downto 0)
);
end component;
-- Datapath (MISSING!You must include it in your final project!)
component DataPath is
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
OPCD_SIZE : integer := C_SYS_OPCD_SIZE;
IMME_SIZE : integer := C_SYS_IMME_SIZE;
CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Datapath Contrl Word
CALU_SIZE : integer := C_CTR_CALU_SIZE;
DRCW_SIZE : integer := C_CTR_DRCW_SIZE
);
port (
clk : in std_logic;
rst : in std_logic;
istr_addr : out std_logic_vector(ADDR_SIZE-1 downto 0);
istr_val : in std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
ir_out : out std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
pc_out : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
reg_a_out : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
ld_a_out : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
data_addr : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
data_i_val : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
data_o_val : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
cw : in std_logic_vector(CWRD_SIZE-1 downto 0):=(others=>'0');
dr_cw : out std_logic_vector(DRCW_SIZE-1 downto 0):=(others=>'0');
calu : in std_logic_vector(CALU_SIZE-1 downto 0):=(others=>'0');
sig_bal : out std_logic:='0';
sig_bpw : in std_logic:='0';
sig_jral : out std_logic:='0';
sig_ral : out std_logic:='0';
sig_mul : out std_logic:='0';
sig_div : out std_logic:='0';
sig_sqrt : out std_logic:='0'
);
end component;
-- CONSTANTS
constant FUNC_SIZE : integer := C_SYS_FUNC_SIZE;
constant OPCD_SIZE : integer := C_SYS_OPCD_SIZE;
constant CWRD_SIZE : integer := C_SYS_CWRD_SIZE;
constant CALU_SIZE : integer := C_CTR_CALU_SIZE;
constant IMME_SIZE : integer := C_SYS_IMME_SIZE;
-- SIGNALS
signal ir : std_logic_vector(ISTR_SIZE-1 downto 0);
signal pc : std_logic_vector(ADDR_SIZE-1 downto 0);
signal cw : std_logic_vector(CWRD_SIZE-1 downto 0);
signal calu : std_logic_vector(CALU_SIZE-1 downto 0);
signal reg_a_val: std_logic_vector(DATA_SIZE-1 downto 0);
signal ld_a_val : std_logic_vector(DATA_SIZE-1 downto 0);
signal sig_bal : std_logic:='0';
signal sig_bpw : std_logic:='0';
signal sig_jral : std_logic:='0';
signal sig_ral : std_logic:='0';
signal sig_mul : std_logic:='0';
signal sig_div : std_logic:='0';
signal sig_sqrt : std_logic:='0';
begin
CU0: ControlUnit
generic map(ISTR_SIZE, DATA_SIZE, OPCD_SIZE, FUNC_SIZE, CWRD_SIZE, CALU_SIZE)
port map(clk, rst, ir, pc, reg_a_val, ld_a_val, sig_bal, sig_bpw, sig_jral, sig_ral, sig_mul, sig_div, sig_sqrt, cw, calu);
DP0: DataPath
generic map(ADDR_SIZE, DATA_SIZE, ISTR_SIZE, OPCD_SIZE, IMME_SIZE, CWRD_SIZE, CALU_SIZE, DRCW_SIZE)
port map(clk, rst, pc_bus, ir_bus, ir, pc, reg_a_val, ld_a_val, addr_bus, do_bus, di_bus, cw, dr_cw, calu, sig_bal, sig_bpw, sig_jral, sig_ral, sig_mul, sig_div, sig_sqrt);
en_iram <= cw(CW_S1_LATCH);
en_dram <= '1';
end dlx_arch;
|
mit
|
ea4f4f9e5c8d62f6cce9c0b6053cef3f
| 0.59346 | 2.79248 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/disputed/tc737.vhd
| 4 | 3,447 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc737.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x01p04n01i00737ent_a is
generic (
constant gc1 : in integer;
constant gc2 : in real;
constant gc3 : in boolean
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n01i00737ent_a;
architecture c01s01b01x01p04n01i00737arch_a of c01s01b01x01p04n01i00737ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1 = 5) AND (gc2 = 0.1234) AND (gc3) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00737"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00737 - Simple generic association in component instantiation (type conversion done on actual in generic map failed)."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00737arch_a;
ENTITY c01s01b01x01p04n01i00737ent IS
generic ( constant gen_con : integer := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n01i00737ent;
ARCHITECTURE c01s01b01x01p04n01i00737arch OF c01s01b01x01p04n01i00737ent IS
constant c1 : integer := 33;
constant c2 : real := 1.23557;
constant c3 : boolean := FALSE;
signal s1 : integer;
signal s2 : integer;
signal s3 : integer;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : real;
constant dgc3 : boolean
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00737ent_a(c01s01b01x01p04n01i00737_arch_a)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
function BoolToInt(bin : boolean) return integer is
begin
if bin then
return 5;
else
return 99;
end if;
end;
function IntegerToReal(iin : integer) return real is
begin
return 0.1234;
end;
function BitToBool(bin : bit) return boolean is
begin
if (bin = '1') then
return TRUE;
else
return FALSE;
end if;
end;
BEGIN
u1 : comp1
generic map (BoolToInt(TRUE), IntegerToReal(1234), BitToBool('1'))
port map (ee1,ee2);
END c01s01b01x01p04n01i00737arch;
|
gpl-2.0
|
ccc9e2bd148abbd9752db95e3c69efd6
| 0.644038 | 3.471299 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_crc.vhd
| 1 | 8,084 |
-- #################################################################################################
-- # << NEO430 - CRC Module >> #
-- # ********************************************************************************************* #
-- # This module generates CRC16 and CRC32 check sums with variable polynomial masks. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_crc is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_crc;
architecture neo430_crc_rtl of neo430_crc is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(crc_size_c); -- low address boundary bit
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wren : std_ulogic;
-- accessible registers --
signal idata : std_ulogic_vector(07 downto 0);
signal poly : std_ulogic_vector(31 downto 0);
signal start : std_ulogic;
signal mode : std_ulogic;
-- core --
signal cnt : std_ulogic_vector(02 downto 0);
signal run : std_ulogic;
signal crc_bit : std_ulogic;
signal crc_sr : std_ulogic_vector(31 downto 0);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = crc_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= crc_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wren <= acc_en and wren_i;
-- Write Access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
write_access: process(clk_i)
begin
if rising_edge(clk_i) then
start <= '0';
if (wren = '1') then
-- operands --
if (addr = crc_crc16_in_addr_c) or (addr = crc_crc32_in_addr_c) then -- write data & start operation
idata <= data_i(7 downto 0);
start <= '1'; -- start operation
end if;
if (addr = crc_poly_lo_addr_c) then -- low (part) polynomial
poly(15 downto 00) <= data_i;
end if;
if (addr = crc_poly_hi_addr_c) then -- high (part) polynomial
poly(31 downto 16) <= data_i;
end if;
-- operation selection --
if (addr = crc_crc16_in_addr_c) then
mode <= '0'; -- crc16 mode
else
mode <= '1'; -- crc32 mode
end if;
end if;
end if;
end process write_access;
-- CRC Core -----------------------------------------------------------------
-- -----------------------------------------------------------------------------
crc_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- arbitration --
if (start = '1') then
run <= '1';
elsif (cnt = "000") then -- all done?
run <= '0';
end if;
if (start = '1') then
cnt <= "111"; -- start with MSB
elsif (run = '1') then
cnt <= std_ulogic_vector(unsigned(cnt) - 1);
end if;
-- computation --
if ((wren = '1') and (addr = crc_resx_addr_c)) then -- write low part of CRC shift reg
crc_sr(15 downto 0) <= data_i;
elsif ((wren = '1') and (addr = crc_resy_addr_c)) then -- write high part of CRC shift reg
crc_sr(31 downto 16) <= data_i;
elsif (run = '1') then -- compute new CRC
if (crc_bit /= idata(to_integer(unsigned(cnt(2 downto 0))))) then
crc_sr <= (crc_sr(30 downto 0) & '0') xor poly;
else
crc_sr <= (crc_sr(30 downto 0) & '0');
end if;
end if;
end if;
end process crc_core;
-- select compare bit according to selected mode --
crc_bit <= crc_sr(31) when (mode = '1') else crc_sr(15);
-- Read Access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
read_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (acc_en = '1') and (rden_i = '1') then
if (addr = crc_resx_addr_c) then
data_o <= crc_sr(15 downto 00);
else -- if addr = crc_resy_addr_c
data_o <= crc_sr(31 downto 16);
end if;
end if;
end if;
end process read_access;
end neo430_crc_rtl;
|
bsd-3-clause
|
78858f6cedec7306000a297153c09559
| 0.448046 | 4.643308 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/building_blocks/invMixColumn_tb.vhd
| 1 | 1,889 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 03:36:03 PM
-- Design Name:
-- Module Name: invMixColumn_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity invMixColumn_tb is
end invMixColumn_tb;
architecture Behavioral of invMixColumn_tb is
component invMixColumn is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
constant clk_period : time := 2ns;
signal CLK, RESET : STD_LOGIC := '0';
signal wordIn, wordOut : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
uut: invMixColumn port map( CLK => CLK,
RESET => RESET,
wordIn => wordIn,
wordOut => wordOut);
clk_process: process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process;
--Samples based on http://kavaliro.com/wp-content/uploads/2014/03/AES.pdf
stim_process: process
begin
wait for 5* clk_period;
wordIn <= x"BA75F47A";
--Expected output: x"632FAFA2"
wait for clk_period;
wordIn <= x"84A48D32";
--Expected output: x"EB93C720"
wait for clk_period;
wordIn <= x"E88D060E";
--Expected output: x"9F92ABCB"
wait for 5*clk_period;
end process;
end Behavioral;
|
gpl-2.0
|
d784db2232193a5a50c41427b354ad88
| 0.506617 | 4.124454 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_19.vhd
| 4 | 2,012 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_19.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book (in text)
entity nand3 is
port ( a, b, c : in bit; y : out bit );
end entity nand3;
-- end code from book
architecture behavioral of nand3 is
begin
y <= not (a and b and c);
end architecture behavioral;
entity logic_block is
end entity logic_block;
-- code from book
library gate_lib;
architecture ideal of logic_block is
component nand2 is
port ( in1, in2 : in bit; result : out bit );
end component nand2;
for all : nand2
use entity gate_lib.nand3(behavioral)
port map ( a => in1, b => in2, c => '1', y => result );
-- . . . -- other declarations
-- not in book
signal s1, s2, s3 : bit := '0';
begin
gate1 : component nand2
port map ( in1 => s1, in2 => s2, result => s3 );
-- . . . -- other concurrent statements
-- not in book
s1 <= '1' after 20 ns;
s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
-- end not in book
end architecture ideal;
-- end code from book
|
gpl-2.0
|
bd74a888d09339445dfdbf4add3144c6
| 0.610338 | 3.664845 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1450.vhd
| 4 | 1,953 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1450.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p01n01i01450ent IS
END c08s07b00x00p01n01i01450ent;
ARCHITECTURE c08s07b00x00p01n01i01450arch OF c08s07b00x00p01n01i01450ent IS
begin
p: process
variable j : integer := 1;
variable i : integer := 0;
variable k : integer := 0;
variable m : integer := 0;
begin
if j = 1 then
i := 1;
elsif j = 2 then
k := 1;
else
m := 1;
end if;
assert (i = 0) and (k = 1) and (m = 1)
report "***PASSED TEST: c08s07b00x00p01n01i01450"
severity NOTE;
assert NOT((i = 0) and (k = 1) and (m = 1))
report "***FAILED TEST: c08s07b00x00p01n01i01450 - An expression specifying a condition must be of type BOOLEAN"
severity ERROR;
wait;
end process;
END c08s07b00x00p01n01i01450arch;
|
gpl-2.0
|
7119b385efec8b2db5d0eb33e4333a94
| 0.637993 | 3.557377 | false | true | false | false |
peteut/ghdl
|
libraries/std/textio_body.vhdl
| 2 | 44,547 |
-- Std.Textio package body. This file is part of GHDL.
-- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING3. If not see
-- <http://www.gnu.org/licenses/>.
package body textio is
--START-V08
-- LRM08 16.4
-- The JUSTIFY operation formats a string value within a field that is at
-- least at long as required to contain the value. Parameter FIELD
-- specifies the desired field width. Since the actual field width will
-- always be at least large enough to hold the string value, the default
-- value 0 for the FIELD parameter has the effect of causing the string
-- value to be contained in a field of exactly the right widteh (i.e., no
-- additional leading or tailing spaces). Parameter JUSTIFIED specified
-- wether the string value is to be right- or left-justified within the
-- field; the default is right-justified. If the FIELD parameter describes
-- a field width larger than the number of characters in the string value,
-- space characters are used to fill the remaining characters in the field.
--
-- TG: Note that the bounds of the result are not specified!
function Justify (Value: String;
Justified : Side := Right;
Field: Width := 0 ) return String
is
constant len : Width := Value'Length;
begin
if Field <= Len then
return Value;
else
case Justified is
when Right =>
return (1 to Field - Len => ' ') & Value;
when Left =>
return Value & (1 to Field - Len => ' ');
end case;
end if;
end Justify;
--END-V08
-- output routines for standard types
-- TIME_NAMES associates time units with textual names.
-- Textual names are in lower cases, since according to LRM93 14.3:
-- when written, the identifier is expressed in lowercase characters.
-- The length of the names are 3 characters, the last one may be a space
-- for 2 characters long names.
type time_unit is
record
val : time;
name : string (1 to 3);
end record;
type time_names_type is array (1 to 8) of time_unit;
constant time_names : time_names_type :=
((fs, "fs "), (ps, "ps "), (ns, "ns "), (us, "us "),
(ms, "ms "), (sec, "sec"), (min, "min"), (hr, "hr "));
-- Non breaking space character. --!V87
constant nbsp : character := character'val (160); --!V87
function is_whitespace (c : character) return Boolean is
begin
case c is
when ' '
| NBSP --!V87
| HT =>
return True;
when others =>
return False;
end case;
end is_Whitespace;
procedure writeline (variable f: out text; l: inout line) is --V87
procedure writeline (file f: text; l: inout line) is --!V87
begin
if l = null then
-- LRM93 14.3
-- If parameter L contains a null access value at the start of the call,
-- the a null string is written to the file.
null;
else
-- LRM93 14.3
-- Procedure WRITELINE causes the current line designated by parameter L
-- to be written to the file and returns with the value of parameter L
-- designating a null string.
write (f, l.all);
deallocate (l);
l := new string'("");
end if;
write (f, (1 => LF));
end writeline;
--START-V08
procedure Tee (file f : Text; L : inout LINE) is
begin
-- LRM08 16.4 Package TEXTIO
-- The procedure TEE additionally causes the current line to be written
-- to the file OUTPUT.
if l = null then
null;
else
write (f, l.all);
write (Output, l.all);
deallocate (l);
l := new string'("");
end if;
write (f, (1 => LF));
write (output, (1 => LF));
end Tee;
--END-V08
procedure write
(l: inout line; value: in string;
justified: in side := right; field: in width := 0)
is
variable length: natural;
variable nl: line;
begin
-- l can be null.
if l = null then
length := 0;
else
length := l.all'length;
end if;
if value'length < field then
nl := new string (1 to length + field);
if length /= 0 then
nl (1 to length) := l.all;
end if;
if justified = right then
nl (length + 1 to length + field - value'length) := (others => ' ');
nl (nl.all'high - value'length + 1 to nl.all'high) := value;
else
nl (length + 1 to length + value'length) := value;
nl (length + value'length + 1 to nl.all'high) := (others => ' ');
end if;
else
nl := new string (1 to length + value'length);
if length /= 0 then
nl (1 to length) := l.all;
end if;
nl (length + 1 to nl.all'high) := value;
end if;
deallocate (l);
l := nl;
end write;
procedure write
(l: inout line; value: in integer;
justified: in side := right; field: in width := 0)
is
variable str: string (11 downto 1);
variable val: integer := value;
variable digit: natural;
variable index: natural := 0;
begin
-- Note: the absolute value of VAL cannot be directly taken, since
-- it may be greather that the maximum value of an INTEGER.
loop
-- LRM93 7.2.6
-- (A rem B) has the sign of A and an absolute value less then
-- the absoulte value of B.
digit := abs (val rem 10);
val := val / 10;
index := index + 1;
str (index) := character'val(48 + digit);
exit when val = 0;
end loop;
if value < 0 then
index := index + 1;
str(index) := '-';
end if;
write (l, str (index downto 1), justified, field);
end write;
procedure write
(l: inout line; value: in boolean;
justified: in side := right; field: in width := 0)
is
begin
if value then
write (l, string'("TRUE"), justified, field);
else
write (l, string'("FALSE"), justified, field);
end if;
end write;
procedure write
(l: inout line; value: in character;
justified: in side := right; field: in width := 0)
is
variable str: string (1 to 1);
begin
str (1) := value;
write (l, str, justified, field);
end write;
function bit_to_char (value : in bit) return character is
begin
case value is
when '0' =>
return '0';
when '1' =>
return '1';
end case;
end bit_to_char;
procedure write
(l: inout line; value: in bit;
justified: in side := right; field: in width := 0)
is
variable str : string (1 to 1);
begin
str (1) := bit_to_char (value);
write (l, str, justified, field);
end write;
procedure write
(l: inout line; value: in bit_vector;
justified: in side := right; field: in width := 0)
is
constant length : natural := value'length;
alias n_value : bit_vector (1 to value'length) is value;
variable str : string (1 to length);
begin
for i in str'range loop
str (i) := bit_to_char (n_value (i));
end loop;
write (l, str, justified, field);
end write;
procedure write
(l: inout line; value : in time;
justified: in side := right; field: in width := 0; unit : in TIME := ns)
is
-- Copy of VALUE on which we are working.
variable val : time := value;
-- Copy of UNIT on which we are working.
variable un : time := unit;
-- Digit extract from VAL/UN.
variable d : integer; -- natural range 0 to 9;
-- Index for unit name.
variable n : integer;
-- Result.
variable str : string (1 to 28);
-- Current character in RES.
variable pos : natural := 1;
-- Add a character to STR.
procedure add_char (c : character) is
begin
str (pos) := c;
pos := pos + 1;
end add_char;
begin
-- Note:
-- Care is taken to avoid overflow. Time may be 64 bits while integer
-- may be only 32 bits.
-- Handle sign.
-- Note: VAL cannot be negated since its range may be not symetric
-- around 0.
if val < 0 ns then
add_char ('-');
end if;
-- Search for the first digit.
-- Note: we must start from unit, since all units are not a power of 10.
-- Note: UN can be multiplied only after we know it is possible. This
-- is a to avoid overflow.
if un <= 0 fs then
assert false report "UNIT argument is not positive" severity error;
un := 1 ns;
end if;
while val / 10 >= un or val / 10 <= -un loop
un := un * 10;
end loop;
-- Extract digits one per one.
loop
d := val / un;
add_char (character'val (abs d + character'pos ('0')));
val := val - d * un;
exit when val = 0 ns and un <= unit;
if un = unit then
add_char ('.');
end if;
-- Stop as soon as precision will be lost.
-- This can happen only for hr and min.
-- FIXME: change the algorithm to display all the digits.
exit when (un / 10) * 10 /= un;
un := un / 10;
end loop;
add_char (' ');
-- Search the time unit name in the time table.
n := 0;
for i in time_names'range loop
if time_names (i).val = unit then
n := i;
exit;
end if;
end loop;
assert n /= 0 report "UNIT argument is not a unit name" severity error;
if n = 0 then
add_char ('?');
else
add_char (time_names (n).name (1));
add_char (time_names (n).name (2));
if time_names (n).name (3) /= ' ' then
add_char (time_names (n).name (3));
end if;
end if;
-- Write the result.
write (l, str (1 to pos - 1), justified, field);
end write;
-- Parameter DIGITS specifies how many digits to the right of the decimal
-- point are to be output when writing a real number; the default value 0
-- indicates that the number should be output in standard form, consisting
-- of a normalized mantissa plus exponent (e.g., 1.079236E23). If DIGITS is
-- nonzero, then the real number is output as an integer part followed by
-- '.' followed by the fractional part, using the specified number of digits
-- (e.g., 3.14159).
-- Note: Nan, +Inf, -Inf are not to be considered, since these numbers are
-- not in the bounds defined by any real range.
procedure write (L: inout line; value: in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0)
is
-- STR contains the result of the conversion.
variable str : string (1 to 320);
-- POS is the index of the next character to be put in STR.
variable pos : positive := str'left;
-- VAL contains the value to be converted.
variable val : real;
-- The exponent or mantissa computed is stored in MANTISSA. This is
-- a signed number.
variable mantissa : integer;
variable b : boolean;
variable d : natural;
-- Append character C in STR.
procedure add_char (c : character) is
begin
str (pos) := c;
pos := pos + 1;
end add_char;
-- Add digit V in STR.
procedure add_digit (v : natural) is
begin
add_char (character'val (character'pos ('0') + v));
end add_digit;
-- Add leading digit and substract it.
procedure extract_leading_digit is
variable d : natural range 0 to 10;
begin
-- Note: We need truncation but type conversion does rounding.
-- FIXME: should consider precision.
d := natural (val);
if real (d) > val then
d := d - 1;
end if;
val := (val - real (d)) * 10.0;
add_digit (d);
end extract_leading_digit;
begin
-- Handle sign.
-- There is no overflow here, since with IEEE implementations, sign is
-- independant of the mantissa.
-- LRM93 14.3
-- The sign is never written if the value is non-negative.
if value < 0.0 then
add_char ('-');
val := -value;
else
val := value;
end if;
-- Compute the mantissa.
-- FIXME: should do a dichotomy.
if val = 0.0 then
mantissa := 0;
elsif val < 1.0 then
mantissa := -1;
while val * (10.0 ** (-mantissa)) < 1.0 loop
mantissa := mantissa - 1;
end loop;
else
mantissa := 0;
while val / (10.0 ** mantissa) >= 10.0 loop
mantissa := mantissa + 1;
end loop;
end if;
-- Normalize VAL: in [0; 10[
if mantissa >= 0 then
val := val / (10.0 ** mantissa);
else
val := val * 10.0 ** (-mantissa);
end if;
if digits = 0 then
for i in 0 to 15 loop
extract_leading_digit;
if i = 0 then
add_char ('.');
end if;
exit when i > 0 and val < 10.0 ** (i + 1 - 15);
end loop;
-- LRM93 14.3
-- if the exponent is present, the `e' is written as a lower case
-- character.
add_char ('e');
if mantissa < 0 then
add_char ('-');
mantissa := -mantissa;
end if;
b := false;
for i in 4 downto 0 loop
d := (mantissa / 10000) mod 10;
if d /= 0 or b or i = 0 then
add_digit (d);
b := true;
end if;
mantissa := (mantissa - d * 10000) * 10;
end loop;
else
if mantissa < 0 then
add_char ('0');
mantissa := mantissa + 1;
else
loop
extract_leading_digit;
exit when mantissa = 0;
mantissa := mantissa - 1;
end loop;
end if;
add_char ('.');
for i in 1 to digits loop
if mantissa = 0 then
extract_leading_digit;
else
add_char ('0');
mantissa := mantissa + 1;
end if;
end loop;
end if;
write (l, str (1 to pos - 1), justified, field);
end write;
--START-V08
procedure Owrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0) is
begin
write (l, to_ostring (value), justified, field);
end Owrite;
procedure Hwrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0) is
begin
write (l, to_hstring (value), justified, field);
end Hwrite;
--END-V08
procedure untruncated_text_read --V87
(variable f : text; str : out string; len : out natural); --V87
procedure untruncated_text_read --!V87
(file f : text; str : out string; len : out natural); --!V87
attribute foreign : string; --V87
attribute foreign of untruncated_text_read : procedure is "GHDL intrinsic";
procedure untruncated_text_read
(variable f : text; str : out string; len : out natural) is --V87
(file f : text; str : out string; len : out natural) is --!V87
begin
assert false report "must not be called" severity failure;
end untruncated_text_read;
procedure readline (variable f: in text; l: inout line) --V87
procedure readline (file f: text; l: inout line) --!V87
is
variable len, nlen, posn : natural;
variable nl, old_l : line;
variable str : string (1 to 128);
variable is_eol : boolean;
begin
-- LRM93 14.3
-- If parameter L contains a non-null access value at the start of the
-- call, the object designated by that value is deallocated before the
-- new object is created.
if l /= null then
deallocate (l);
end if;
-- We read the input in 128-byte chunks.
-- We keep reading until we reach a newline or there is no more input.
-- The loop invariant is that old_l is allocated and contains the
-- previous chunks read, and posn = old_l.all'length.
posn := 0;
loop
untruncated_text_read (f, str, len);
exit when len = 0;
if str (len) = LF or str (len) = CR then
-- LRM 14.3
-- The representation of the line does not contain the representation
-- of the end of the line.
is_eol := true;
len := len - 1;
-- End of line is any of LF/CR/CR+LF/LF+CR.
if len > 0 and (str (len) = LF or str (len) = CR) then
len := len - 1;
end if;
elsif endfile (f) then
is_eol := true;
else
is_eol := false;
end if;
l := new string (1 to posn + len);
if old_l /= null then
l (1 to posn) := old_l (1 to posn);
deallocate (old_l);
end if;
l (posn + 1 to posn + len) := str (1 to len);
exit when is_eol;
posn := posn + len;
old_l := l;
end loop;
end readline;
-- Replaces L with L (LEFT to/downto L'RIGHT)
procedure trim (l : inout line; left : natural)
is
variable nl : line;
begin
if l = null then
return;
end if;
if l'left < l'right then
-- Ascending.
if left > l'right then
nl := new string'("");
else
nl := new string (left to l'right);
-- nl := new string (1 to l'right + 1 - left);
nl.all := l (left to l'right);
end if;
else
-- Descending
if left < l'right then
nl := new string'("");
else
nl := new string (left downto l'right);
-- nl := new string (left - l'right + 1 downto 1);
nl.all := l (left downto l'right);
end if;
end if;
deallocate (l);
l := nl;
end trim;
-- Replaces L with L (LEFT + 1 to L'RIGHT or LEFT - 1 downto L'RIGHT)
procedure trim_next (l : inout line; left : natural)
is
variable nl : line;
begin
if l = null then
return;
end if;
if l'left < l'right then
-- Ascending.
trim (l, left + 1);
else
-- Descending
trim (l, left - 1);
end if;
end trim_next;
function to_lower (c : character) return character is
begin
if c >= 'A' and c <= 'Z' then
return character'val (character'pos (c) + 32);
else
return c;
end if;
end to_lower;
procedure read (l: inout line; value: out character; good: out boolean)
is
variable nl : line;
begin
if l = null or l'length = 0 then
good := false;
else
value := l (l'left);
trim_next (l, l'left);
good := true;
end if;
end read;
procedure read (l: inout line; value: out character)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "character read failure"
severity failure;
end read;
procedure read (l: inout line; value: out bit; good: out boolean)
is
begin
good := false;
for i in l'range loop
case l(i) is
when ' '
| NBSP --!V87
| HT =>
null;
when '1' =>
value := '1';
good := true;
trim_next (l, i);
return;
when '0' =>
value := '0';
good := true;
trim_next (l, i);
return;
when others =>
return;
end case;
end loop;
return;
end read;
procedure read (l: inout line; value: out bit)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "bit read failure"
severity failure;
end read;
procedure read (l: inout line; value: out bit_vector; good: out boolean)
is
-- Number of bit to parse.
variable len : natural;
variable pos, last : natural;
variable res : bit_vector (1 to value'length);
-- State of the previous byte:
-- LEADING: blank before the bit vector.
-- FOUND: bit of the vector.
type state_type is (leading, found);
variable state : state_type;
begin
-- Initialization.
len := value'length;
if len = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := leading;
pos := res'left;
for i in l'range loop
case l(i) is
when ' '
| NBSP --!V87
| HT =>
case state is
when leading =>
null;
when found =>
return;
end case;
when '1' | '0' =>
case state is
when leading =>
state := found;
when found =>
null;
end case;
if l(i) = '0' then
res (pos) := '0';
else
res (pos) := '1';
end if;
pos := pos + 1;
len := len - 1;
last := i;
exit when len = 0;
when others =>
return;
end case;
end loop;
if len /= 0 then
-- Not enough bits.
return;
end if;
-- Note: if LEN = 0, then FIRST and LAST have been set.
good := true;
value := res;
trim_next (l, last);
return;
end read;
procedure read (l: inout line; value: out bit_vector)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "bit_vector read failure"
severity failure;
end read;
procedure read (l: inout line; value: out boolean; good: out boolean)
is
-- State:
-- BLANK: space are being scaned.
-- L_TF : T(rue) or F(alse) has been scanned.
-- L_RA : (t)R(ue) or (f)A(lse) has been scanned.
-- L_UL : (tr)U(e) or (fa)L(se) has been scanned.
-- L_ES : (tru)E or (fal)S(e) has been scanned.
type state_type is (blank, l_tf, l_ra, l_ul, l_es);
variable state : state_type;
-- Set to TRUE if T has been scanned, to FALSE if F has been scanned.
variable res : boolean;
begin
-- By default, it is a failure.
good := false;
state := blank;
for i in l'range loop
case state is
when blank =>
if is_whitespace (l (i)) then
null;
elsif to_lower (l (i)) = 't' then
res := true;
state := l_tf;
elsif to_lower (l (i)) = 'f' then
res := false;
state := l_tf;
else
return;
end if;
when l_tf =>
if res = true and to_lower (l (i)) = 'r' then
state := l_ra;
elsif res = false and to_lower (l (i)) = 'a' then
state := l_ra;
else
return;
end if;
when l_ra =>
if res = true and to_lower (l (i)) = 'u' then
state := l_ul;
elsif res = false and to_lower (l (i)) = 'l' then
state := l_ul;
else
return;
end if;
when l_ul =>
if res = true and to_lower (l (i)) = 'e' then
trim_next (l, i);
good := true;
value := true;
return;
elsif res = false and to_lower (l (i)) = 's' then
state := l_es;
else
return;
end if;
when l_es =>
if res = false and to_lower (l (i)) = 'e' then
trim_next (l, i);
good := true;
value := false;
return;
else
return;
end if;
end case;
end loop;
return;
end read;
procedure read (l: inout line; value: out boolean)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "boolean read failure"
severity failure;
end read;
function char_to_nat (c : character) return natural
is
begin
return character'pos (c) - character'pos ('0');
end char_to_nat;
procedure read (l: inout line; value: out integer; good: out boolean)
is
variable val : integer;
variable d : natural;
type state_t is (leading, sign, digits);
variable cur_state : state_t := leading;
begin
val := 1;
for i in l'range loop
case cur_state is
when leading =>
case l(i) is
when ' '
| NBSP --!V87
| ht =>
null;
when '+' =>
cur_state := sign;
when '-' =>
val := -1;
cur_state := sign;
when '0' to '9' =>
val := char_to_nat (l(i));
cur_state := digits;
when others =>
good := false;
return;
end case;
when sign =>
case l(i) is
when '0' to '9' =>
val := val * char_to_nat (l(i));
cur_state := digits;
when others =>
good := false;
return;
end case;
when digits =>
case l(i) is
when '0' to '9' =>
d := char_to_nat (l(i));
val := val * 10;
if val < 0 then
val := val - d;
else
val := val + d;
end if;
when others =>
trim (l, i);
good := true;
value := val;
return;
end case;
end case;
end loop;
deallocate (l);
l := new string'("");
if cur_state /= leading then
good := true;
value := val;
else
good := false;
end if;
end read;
procedure read (l: inout line; value: out integer)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "integer read failure"
severity failure;
end read;
procedure read (l: inout line; value: out real; good: out boolean)
is
-- The result.
variable val : real;
-- True if the result is negative.
variable val_neg : boolean;
-- Number of digits after the dot.
variable nbr_dec : natural;
-- Value of the exponent.
variable exp : integer;
-- True if the exponent is negative.
variable exp_neg : boolean;
-- The parsing is done with a state machine.
-- LEADING: leading blank suppression.
-- SIGN: a sign has been found.
-- DIGITS: integer parts
-- DECIMALS: digits after the dot.
-- EXPONENT_SIGN: sign after "E"
-- EXPONENT_1: first digit of the exponent.
-- EXPONENT: digits of the exponent.
type state_t is (leading, sign, digits, decimals,
exponent_sign, exponent_1, exponent);
variable cur_state : state_t := leading;
-- Set VALUE to the result, and set GOOD to TRUE.
procedure set_value is
begin
good := true;
if exp_neg then
val := val * 10.0 ** (-exp);
else
val := val * 10.0 ** exp;
end if;
if val_neg then
value := -val;
else
value := val;
end if;
end set_value;
begin
-- Initialization.
val_neg := false;
nbr_dec := 1;
exp := 0;
exp_neg := false;
-- By default, parsing has failed.
good := false;
-- Iterate over all characters of the string.
-- Return immediatly in case of parse error.
-- Trim L and call SET_VALUE and return in case of success.
for i in l'range loop
case cur_state is
when leading =>
case l(i) is
when ' '
| NBSP --!V87
| ht =>
null;
when '+' =>
cur_state := sign;
when '-' =>
val_neg := true;
cur_state := sign;
when '0' to '9' =>
val := real (char_to_nat (l(i)));
cur_state := digits;
when others =>
return;
end case;
when sign =>
case l(i) is
when '0' to '9' =>
val := real (char_to_nat (l(i)));
cur_state := digits;
when others =>
return;
end case;
when digits =>
case l(i) is
when '0' to '9' =>
val := val * 10.0 + real (char_to_nat (l(i)));
when '.' =>
cur_state := decimals;
when others =>
-- A "." (dot) is required in the string.
return;
end case;
when decimals =>
case l(i) is
when '0' to '9' =>
val := val + real (char_to_nat (l(i))) / (10.0 ** nbr_dec);
nbr_dec := nbr_dec + 1;
when 'e' | 'E' =>
-- "nnn.E" is erroneous.
if nbr_dec = 1 then
return;
end if;
cur_state := exponent_sign;
when others =>
-- "nnn.XX" is erroneous.
if nbr_dec = 1 then
return;
end if;
trim (l, i);
set_value;
return;
end case;
when exponent_sign =>
case l(i) is
when '+' =>
cur_state := exponent_1;
when '-' =>
exp_neg := true;
cur_state := exponent_1;
when '0' to '9' =>
exp := char_to_nat (l(i));
cur_state := exponent;
when others =>
-- Error.
return;
end case;
when exponent_1 | exponent =>
case l(i) is
when '0' to '9' =>
exp := exp * 10 + char_to_nat (l(i));
cur_state := exponent;
when others =>
trim (l, i);
set_value;
return;
end case;
end case;
end loop;
-- End of string.
case cur_state is
when leading | sign | digits =>
-- Erroneous.
return;
when decimals =>
-- "nnn.XX" is erroneous.
if nbr_dec = 1 then
return;
end if;
when exponent_sign =>
-- Erroneous ("NNN.NNNE")
return;
when exponent_1 =>
-- "NNN.NNNE-"
return;
when exponent =>
null;
end case;
deallocate (l);
l := new string'("");
set_value;
end read;
procedure read (l: inout line; value: out real)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "real read failure"
severity failure;
end read;
procedure read (l: inout line; value: out time; good: out boolean)
is
-- The result.
variable res : time;
-- UNIT is computed from the unit name, the exponent and the number of
-- digits before the dot. UNIT is the weight of the current digit.
variable unit : time;
-- Number of digits before the dot.
variable nbr_digits : integer;
-- True if a unit name has been found. Used temporaly to know the status
-- at the end of the search loop.
variable unit_found : boolean;
-- True if the number is negative.
variable is_neg : boolean;
-- Value of the exponent.
variable exp : integer;
-- True if the exponent is negative.
variable exp_neg : boolean;
-- Unit name extracted from the string.
variable unit_name : string (1 to 3);
-- state is the kind of the previous character parsed.
-- LEADING: leading blanks
-- SIGN: + or - as the first character of the number.
-- DIGITS: digit of the integer part of the number.
-- DOT: dot (.) after the integer part and before the decimal part.
-- DECIMALS: digit of the decimal part.
-- EXPONENT_MARK: e or E.
-- EXPONENT_SIGN: + or - just after the exponent mark (E).
-- EXPONENT: digit of the exponent.
-- UNIT_BLANK: blank after the exponent.
-- UNIT_1, UNIT_2, UNIT_3: first, second, third character of the unit.
type state_type is (leading, sign, digits, dot, decimals,
exponent_mark, exponent_sign, exponent,
unit_blank, unit_1, unit_2, unit_3);
variable state : state_type;
-- Used during the second scan of the string, TRUE is digits is being
-- scaned.
variable has_digits : boolean;
-- Position at the end of the string.
variable pos : integer;
-- Used to compute POS.
variable length : integer;
begin
-- Initialization.
-- Fail by default; therefore, in case of error, a return statement is
-- ok.
good := false;
nbr_digits := 0;
is_neg := false;
exp := 0;
exp_neg := false;
res := 0 fs;
-- Look for exponent and unit name.
-- Parse the string: this loop checks the correctness of the format, and
-- must return (GOOD has been set to FALSE) in case of error.
-- Set: NBR_DIGITS, IS_NEG, EXP, EXP_NEG.
state := leading;
for i in l'range loop
case l (i) is
when ' '
| NBSP --!V87
| HT =>
case state is
when leading | unit_blank =>
null;
when sign | dot | exponent_mark | exponent_sign =>
return;
when digits | decimals | exponent =>
state := unit_blank;
when unit_1 | unit_2 =>
exit;
when unit_3 =>
-- Cannot happen, since an exit is performed at unit_3.
assert false report "internal error" severity failure;
end case;
when '+' | '-' =>
case state is
when leading =>
if l(i) = '-' then
is_neg := true;
end if;
state := sign;
when exponent_mark =>
if l(i) = '-' then
exp_neg := true;
end if;
state := exponent_sign;
when others =>
return;
end case;
when '0' to '9' =>
case state is
when exponent_mark | exponent_sign | exponent =>
exp := exp * 10 + char_to_nat (l (i));
state := exponent;
when leading | sign | digits =>
-- Leading "0" are not significant.
if nbr_digits > 0 or l (i) /= '0' then
nbr_digits := nbr_digits + 1;
end if;
state := digits;
when decimals =>
null;
when dot =>
state := decimals;
when others =>
return;
end case;
when 'a' to 'z' | 'A' to 'Z' =>
case state is
when digits | decimals =>
-- "E" has exponent mark.
if l (i) = 'e' or l(i) = 'E' then
state := exponent_mark;
else
return;
end if;
when unit_blank =>
unit_name (1) := to_lower (l(i));
state := unit_1;
when unit_1 =>
unit_name (2) := to_lower (l(i));
state := unit_2;
pos := i;
when unit_2 =>
unit_name (3) := to_lower (l(i));
state := unit_3;
exit;
when others =>
return;
end case;
when '.' =>
case state is
when digits =>
state := decimals;
when others =>
exit;
end case;
when others =>
exit;
end case;
end loop;
-- A unit name (2 or 3 letters) must have been found.
-- The string may end anywhere.
if state /= unit_2 and state /= unit_3 then
return;
end if;
-- Compute EXP with the sign.
if exp_neg then
exp := -exp;
end if;
-- Search the unit name in the list of time names.
unit_found := false;
for i in time_names'range loop
-- The first two characters must match (case insensitive).
-- The third character must match if:
-- * the unit name is a three characters identifier (ie, not a blank).
-- * there is a third character in STR.
if time_names (i).name (1) = unit_name (1)
and time_names (i).name (2) = unit_name (2)
and (time_names (i).name (3) = ' '
or time_names (i).name (3) = unit_name (3))
then
unit := time_names (i).val;
unit_found := true;
-- POS is set to the position of the first invalid character.
if time_names (i).name (3) = ' ' then
length := 1;
else
length := 2;
end if;
if l'left < l'right then
pos := pos + length;
else
pos := pos - length;
end if;
exit;
end if;
end loop;
if not unit_found then
return;
end if;
-- Compute UNIT, the weight of the first non-significant character.
nbr_digits := nbr_digits + exp - 1;
if nbr_digits < 0 then
unit := unit / 10 ** (-nbr_digits);
else
unit := unit * 10 ** nbr_digits;
end if;
-- HAS_DIGITS will be set as soon as a digit is found.
-- No error is expected here (this has been checked during the first
-- pass).
has_digits := false;
for i in l'range loop
case l (i) is
when ' '
| NBSP --!V87
| HT =>
if has_digits then
exit;
end if;
when '+' | '-' =>
if not has_digits then
has_digits := true;
else
assert false report "internal error" severity failure;
return;
end if;
when '0' to '9' =>
-- Leading "0" are not significant.
if l (i) /= '0' or res /= 0 fs then
res := res + char_to_nat (l (i)) * unit;
unit := unit / 10;
end if;
has_digits := true;
when 'a' to 'z' | 'A' to 'Z' =>
if has_digits then
exit;
else
assert false report "internal error" severity failure;
return;
end if;
when '.' =>
if not has_digits then
assert false report "internal error" severity failure;
return;
end if;
when others =>
assert false report "internal error" severity failure;
return;
end case;
end loop;
-- Set VALUE.
if is_neg then
value := -res;
else
value := res;
end if;
good := true;
trim (l, pos);
return;
end read;
procedure read (l: inout line; value: out time)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "time read failure"
severity failure;
end read;
procedure read (l: inout line; value: out string; good: out boolean)
is
constant len : natural := value'length;
begin
if l'length < len then
good := false;
return;
end if;
good := true;
if len = 0 then
return;
end if;
if l'left < l'right then
-- Ascending (expected common case).
value := l (l'left to l'left + len - 1);
trim (l, l'left + len);
elsif l'left = l'right then
-- String of 1 character. We don't know the direction and therefore
-- can't use the code below which does a slice.
value := l.all;
deallocate (l);
l := new string'("");
else
-- Descending.
value := l (l'left downto l'left - len + 1);
trim (l, l'left - len);
end if;
end read;
procedure read (l: inout line; value: out string)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "string read failure"
severity failure;
end read;
--START-V08
procedure Sread (L : inout Line; Value : out String; Strlen : out Natural)
is
constant maxlen : natural := Value'Length;
alias value1 : string (1 to maxlen) is Value;
variable skipping : boolean := True;
variable f, len, nl_left : natural;
variable nl : line;
begin
-- Skip leading spaces. F designates the index of the first non-space
-- character, LEN the length of the extracted string.
len := 0;
for i in l'range loop
if skipping then
if not is_whitespace (l (i)) then
skipping := false;
f := i;
len := 1;
end if;
else
exit when is_whitespace (l (i));
len := len + 1;
exit when len = maxlen;
end if;
end loop;
-- Copy string.
if l'ascending then
value1 (1 to len) := l (f to f + len - 1);
else
value1 (1 to len) := l (f downto f - len + 1);
end if;
strlen := len;
if l'ascending then
if len = 0 then
f := l'right + 1;
end if;
nl_left := f + len;
nl := new string (nl_left to l'right);
nl.all := l (nl_left to l'right);
else
if len = 0 then
f := l'right - 1;
end if;
nl_left := f - len;
nl := new string (nl_left downto l'right);
nl.all := l (nl_left downto l'right);
end if;
deallocate (l);
l := nl;
end sread;
subtype bv4 is bit_vector (1 to 4);
function char_to_bv4 (c : character) return bv4 is
begin
case c is
when '0' => return "0000";
when '1' => return "0001";
when '2' => return "0010";
when '3' => return "0011";
when '4' => return "0100";
when '5' => return "0101";
when '6' => return "0110";
when '7' => return "0111";
when '8' => return "1000";
when '9' => return "1001";
when 'a' | 'A' => return "1010";
when 'b' | 'B' => return "1011";
when 'c' | 'C' => return "1100";
when 'd' | 'D' => return "1101";
when 'e' | 'E' => return "1110";
when 'f' | 'F' => return "1111";
when others =>
assert false report "bad hexa digit" severity failure;
end case;
end char_to_bv4;
procedure Oread (L : inout Line; Value : out Bit_Vector; Good : out Boolean)
is
-- Length of Value
constant vlen : natural := value'length;
-- Number of octal digits for Value
constant olen : natural := (vlen + 2) / 3;
variable res : bit_vector (1 to olen * 3);
-- Number of bit to parse.
variable len : natural;
variable pos : natural;
-- Last character from LEN to be removed
variable last : integer;
-- State of the previous byte:
-- SKIP: blank before the bit vector.
-- DIGIT: previous character was a digit
-- UNDERSCORE: was '_'
type state_type is (skip, digit, underscore);
variable state : state_type;
begin
-- Initialization.
if vlen = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := skip;
pos := res'left;
if l'ascending then
last := l'left - 1;
else
last := l'left + 1;
end if;
for i in l'range loop
case l (i) is
when ' '
| NBSP
| HT =>
exit when state /= skip;
when '_' =>
exit when state /= digit;
state := underscore;
when '0' to '7' =>
res (pos to pos + 2) := char_to_bv4 (l (i)) (2 to 4);
last := i;
state := digit;
pos := pos + 3;
-- LRM08 16.4
-- Character removal and compostion also stops when the expected
-- number of digits have been removed.
exit when pos = res'right + 1;
when others =>
exit;
end case;
end loop;
-- LRM08 16.4
-- The OREAD or HEAD procedure does not succeed if less than the expected
-- number of digits are removed.
if pos /= res'right + 1 then
return;
end if;
-- LRM08 16.4
-- The rightmost value'length bits of the binary number are used to form
-- the result for the VALUE parameter, [with a '0' element corresponding
-- to a 0 bit and a '1' element corresponding to a 1 bit]. The OREAD or
-- HREAD procedure does not succeed if any unused bits are 1.
for i in 1 to res'right - vlen loop
if res (i) = '1' then
return;
end if;
end loop;
Value := res (res'right - vlen + 1 to res'right);
good := true;
trim_next (l, last);
end Oread;
procedure Oread (L : inout Line; Value : out Bit_Vector)
is
variable res : boolean;
begin
Oread (l, value, res);
assert res = true
report "octal bit_vector read failure"
severity failure;
end Oread;
procedure Hread (L : inout Line; Value : out Bit_Vector; Good : out Boolean)
is
-- Length of Value
constant vlen : natural := value'length;
-- Number of hexa digits for Value
constant hlen : natural := (vlen + 3) / 4;
variable res : bit_vector (1 to hlen * 4);
-- Number of bit to parse.
variable len : natural;
variable pos : natural;
-- Last character from LEN to be removed
variable last : integer;
-- State of the previous byte:
-- SKIP: blank before the bit vector.
-- DIGIT: previous character was a digit
-- UNDERSCORE: was '_'
type state_type is (skip, digit, underscore);
variable state : state_type;
begin
-- Initialization.
if vlen = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := skip;
pos := res'left;
if l'ascending then
last := l'left - 1;
else
last := l'left + 1;
end if;
for i in l'range loop
case l (i) is
when ' '
| NBSP
| HT =>
exit when state /= skip;
when '_' =>
exit when state /= digit;
state := underscore;
when '0' to '9' | 'a' to 'f' | 'A' to 'F' =>
res (pos to pos + 3) := char_to_bv4 (l (i));
last := i;
state := digit;
pos := pos + 4;
-- LRM08 16.4
-- Character removal and compostion also stops when the expected
-- number of digits have been removed.
exit when pos = res'right + 1;
when others =>
exit;
end case;
end loop;
-- LRM08 16.4
-- The OREAD or HEAD procedure does not succeed if less than the expected
-- number of digits are removed.
if pos /= res'right + 1 then
return;
end if;
-- LRM08 16.4
-- The rightmost value'length bits of the binary number are used to form
-- the result for the VALUE parameter, [with a '0' element corresponding
-- to a 0 bit and a '1' element corresponding to a 1 bit]. The OREAD or
-- HREAD procedure does not succeed if any unused bits are 1.
for i in 1 to res'right - vlen loop
if res (i) = '1' then
return;
end if;
end loop;
Value := res (res'right - vlen + 1 to res'right);
good := true;
trim_next (l, last);
end Hread;
procedure Hread (L : inout Line; Value : out Bit_Vector)
is
variable res : boolean;
begin
Hread (l, value, res);
assert res = true
report "hexa bit_vector read failure"
severity failure;
end Hread;
--END-V08
end textio;
|
gpl-2.0
|
8e5cfde7daffe88555b2a8bb13990d23
| 0.562125 | 3.577498 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket70/bug.vhdl
| 3 | 579 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity;
architecture a of ent is
begin
main : process
procedure proc(constant value : unsigned) is
variable a : integer := value'length;
variable b : integer := (value'length - 1)/2;
begin
report "x = " & integer'image(a);
report "(x-1)/2 = " & integer'image(b);
assert a = 0 and b = 0 severity failure;
end procedure;
variable value : unsigned(0 downto 1);
begin
proc(unsigned'(""));
proc(value);
wait;
end process;
end architecture;
|
gpl-2.0
|
3b87a50c6717cca83f940cedb79b6a77
| 0.642487 | 3.467066 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc484.vhd
| 4 | 5,318 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc484.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p19n01i00484ent_a IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END c03s02b01x01p19n01i00484ent_a;
architecture c03s02b01x01p19n01i00484arch_a of c03s02b01x01p19n01i00484ent_a is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00484ent IS
END c03s02b01x01p19n01i00484ent;
ARCHITECTURE c03s02b01x01p19n01i00484arch OF c03s02b01x01p19n01i00484ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type array_rec_cons is array (integer range <>) of record_cons_array;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
function resolution11(i:in array_rec_cons) return record_cons_array is
variable temp : record_cons_array := C51;
begin
return temp;
end resolution11;
subtype array_rec_cons_state is resolution11 record_cons_array;
constant C66 : array_rec_cons_state := C51;
function complex_scalar(s : array_rec_cons_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_cons_state is
begin
return C66;
end scalar_complex;
component c03s02b01x01p19n01i00484ent_a1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : c03s02b01x01p19n01i00484ent_a1 use entity work.c03s02b01x01p19n01i00484ent_a(c03s02b01x01p19n01i00484arch_a);
signal S1 : array_rec_cons_state;
signal S2 : array_rec_cons_state;
signal S3 : array_rec_cons_state:= C66;
BEGIN
T1: c03s02b01x01p19n01i00484ent_a1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00484"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00484 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00484arch;
|
gpl-2.0
|
3fd3e60182c13c24d37ca4964f3d231c
| 0.640466 | 3.446533 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug16695/lfsr_updown.vhd
| 3 | 2,090 |
-------------------------------------------------------
-- Design Name : lfsr
-- File Name : lfsr_updown.vhd
-- Function : Linear feedback shift register
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lfsr_updown is
generic (
WIDTH :integer := 8
);
port (
clk :in std_logic; -- Clock input
reset :in std_logic; -- Reset input
enable :in std_logic; -- Enable input
up_down :in std_logic; -- Up Down input
count :out std_logic_vector (WIDTH-1 downto 0); -- Count output
overflow :out std_logic -- Overflow output
);
end entity;
architecture rtl of lfsr_updown is
signal cnt :std_logic_vector (WIDTH-1 downto 0);
begin
process (up_down, cnt) begin
if (((up_down = '1') and (cnt(WIDTH-1) = '1')) or
((up_down = '0') and ((cnt(WIDTH-1) = '1') and
(cnt(WIDTH-2 downto 0) = "0")))) then
overflow <= '1';
else
overflow <= '0';
end if;
end process;
process (clk, reset, cnt, enable, up_down)
variable temp_a :std_logic_vector (WIDTH-1 downto 0);
variable temp_b :std_logic :='1';
begin
temp_a := cnt and "01100011";
temp_b :='1';
for i in 0 to WIDTH-1 loop
temp_b := temp_a(i) xnor temp_b;
end loop;
if (rising_edge(clk)) then
if (reset = '1') then
cnt <= (others=>'0');
elsif (enable = '1') then
if (up_down = '1') then
cnt <= (temp_b & cnt(WIDTH-1 downto 1));
else
cnt <= (cnt(WIDTH-2 downto 0) & temp_b);
end if;
end if;
end if;
end process;
count <= cnt;
end architecture;
|
gpl-2.0
|
2684d28bea5bb0c481e2fa1329982ba3
| 0.451675 | 4.003831 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2160.vhd
| 4 | 2,035 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2160.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02160ent IS
END c07s02b04x00p22n01i02160ent;
ARCHITECTURE c07s02b04x00p22n01i02160arch OF c07s02b04x00p22n01i02160ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_2 is boolean_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : boolean_2;
variable l_operand : boolean := true;
variable r_operand : boolean := false;
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (true,false)) and (result(1) = true))
report "***PASSED TEST: c07s02b04x00p22n01i02160"
severity NOTE;
assert ((result = (true,false)) and (result(1) = true))
report "***FAILED TEST: c07s02b04x00p22n01i02160 - Concatenation of element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02160arch;
|
gpl-2.0
|
923cf8533f7d11105742fb3c71e9b907
| 0.666339 | 3.673285 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_571.vhd
| 1 | 5,088 |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_571 is
generic (
NUM_BITS : positive := 571 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_571;
-----------------------------------------------------------
architecture behave of serial_multiplier_571 is
-----------------------------------------------------------
-- m = 571 x571 + x10 + x5 + x2 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(9 downto 0); -- 8-bit counter, controling the number of iterations: m
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "1000111010"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
if counter = "0000000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
Done <= '1';
else
bx_int <= bx_shift;
end if;
when END_STATE =>
CurrentState <= END_STATE;
Done <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
baa3637519800fd4ab4b9c09f19bcdb6
| 0.52103 | 4.689401 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.a.b-tbStallGenerator.vhd
| 1 | 1,540 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
entity tbStallGenerator is
end tbStallGenerator;
architecture tb_stall_generator_arch of tbStallGenerator is
constant CWRD_SIZE : integer := C_SYS_CWRD_SIZE;
component StallGenerator is
generic(
CWRD_SIZE : integer := C_SYS_CWRD_SIZE
);
port(
rst : in std_logic;
clk : in std_logic;
s2_branch_taken : in std_logic := '0';
s2_branch_wait : in std_logic := '0';
s3_reg_a_wait : in std_logic := '0';
s3_reg_b_wait : in std_logic := '0';
stall_flag : out std_logic_vector(4 downto 0)
);
end component;
signal rst : std_logic;
signal clk : std_logic:='1';
signal s2_branch_taken : std_logic := '0';
signal s2_branch_wait : std_logic := '0';
signal s3_reg_a_wait : std_logic := '0';
signal s3_reg_b_wait : std_logic := '0';
signal stall_flag : std_logic_vector(4 downto 0);
begin
SG0: StallGenerator
generic map(CWRD_SIZE)
port map(rst, clk, s2_branch_taken, s2_branch_wait, s3_reg_a_wait, s3_reg_b_wait, stall_flag);
CLK0: process(clk)
begin
clk <= not (clk) after 0.5 ns;
end process;
rst <= '0', '1' after 1 ns;
s3_reg_a_wait <= '0', '1' after 3 ns, '0' after 4 ns;
s3_reg_b_wait <= '0', '1' after 8 ns, '0' after 9 ns;
s2_branch_wait <= '0', '1' after 15 ns, '0' after 16 ns;
end tb_stall_generator_arch;
configuration tb_stall_generator_cfg of tbStallGenerator is
for tb_stall_generator_arch
end for;
end tb_stall_generator_cfg;
|
mit
|
61cb2b9b368b7f09c92e2701ea07ed6b
| 0.658442 | 2.512235 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_163.vhd
| 1 | 4,675 |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
-- One file, finite state machine
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_163 is
generic (
NUM_BITS : positive := 163 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_163;
-----------------------------------------------------------
architecture behave of serial_multiplier_163 is
-----------------------------------------------------------
-- m = 163 x163 + x7 + x6 + x3 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10100010"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
if counter = "00000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
Done <= '1';
else
bx_int <= bx_shift;
end if;
when END_STATE =>
CurrentState <= END_STATE;
Done <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
93576d2d6e2c2cdb43c21c9070a7799d
| 0.484064 | 4.28506 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Guerric/SingleFile/guerric_divider_1.vhd
| 1 | 5,908 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Different to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
----------------------------------------------------------------------------------------------------
-- control signals
signal en_VS, C_0, C_3, ISPos: std_logic;
signal V, S, to_V, to_S : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, R, to_U, to_R : STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- Internal registers
signal u_div_2, v_div_2, r_div_2, s_div_2, p_div_2, op1: STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- Internal registers
signal D: STD_LOGIC_VECTOR(3 downto 0); -- Internal registers
signal counter: STD_LOGIC_VECTOR(8 downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, LOAD2, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
U_div_2 <= '0' & U(NUM_BITS-1 downto 1);
R_div_2 <= '0' & R(NUM_BITS-1 downto 1);
P_div_2 <= p(NUM_BITS downto 1);
S_div_2 <= S(NUM_BITS downto 1);
V_div_2 <= V(NUM_BITS downto 1);
to_U <= U_div_2 xor V_div_2 when c_0 = '1' else
U_div_2;
op1 <= R_div_2 xor P_div_2 when c_3 = '1' else
R_div_2;
to_R <= op1 xor S_div_2 when c_0 = '1' else
op1;
to_V <= Y & '0' when rst = '1' else
p when CurrentState = LOAD1 else
'0' & U;
to_S <= X & '0' when rst = '1' else
(others => '0') when CurrentState = LOAD1 else
'0' & R;
en_VS <= '1' when rst = '1' or CurrentState = LOAD1 or (U(0) = '1' and IsPos = '0') else
'0';
c_0 <= '1' when CurrentState = LOAD1 or U(0) = '1' else
'0';
c_3 <= '0' when (CurrentState = LOAD1 or R(0) = '0') else
'1';
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
R <= (others => '0');
U <= (others => '0');
x_div_y <= (others => '0');
if en_VS = '1' then
V <= to_V;
S <= to_S;
end if;
done <= '0';
counter <= "101000110"; --2*m - 2
IsPos <= '0';
D <= "0001";
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
R <= to_R;
U <= to_U;
if en_VS = '1' then
V <= to_V;
S <= to_S;
end if;
currentState <= Cycle;
when CYCLE =>
counter <= counter - 1;
R <= to_R;
U <= to_U;
if en_VS = '1' then
V <= to_V;
S <= to_S;
end if;
if U(0) = '0' then
if IsPos = '0' then D <= D + 1;
elsif D = "0000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
elsif IsPos = '1' then
if D = "0000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
else
D <= D - 1;
IsPos <= '1';
end if;
if counter = "000000000" then
done <= '1';
x_div_y <= S(NUM_BITS-1 downto 0);
CurrentState <= END_STATE;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
927bb0cd5b90fbeab81f091e83edbb8a
| 0.386933 | 3.957133 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc493.vhd
| 4 | 5,019 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc493.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p01n01i00493ent IS
END c03s02b02x00p01n01i00493ent;
ARCHITECTURE c03s02b02x00p01n01i00493arch OF c03s02b02x00p01n01i00493ent IS
type etype is (one,two,three,four,five,six,seven);
type TR is record
i : integer;
b : bit;
bo : boolean;
bv : bit_vector (0 to 3);
r : real;
t : time;
e : etype;
c : character;
end record;
type T1 is record
t : time;
b : bit;
i : integer;
bo : boolean;
r : real;
bv : bit_vector (0 to 3);
e : etype;
c : character;
end record;
function FUNC1(recd1: TR) return T1 is
variable recd2:T1;
begin
recd2.bv := recd1.bv;
recd2.b := recd1.b;
recd2.bo := recd1.bo;
recd2.i := recd1.i;
recd2.r := recd1.r;
recd2.t := recd1.t;
recd2.e := recd1.e;
recd2.c := recd1.c;
return recd2;
end FUNC1;
function FUNC2(recd1: TR) return integer is
begin
return recd1.i;
end;
function FUNC3(recd1: TR) return bit is
begin
return recd1.b;
end;
function FUNC4(recd1: TR) return boolean is
begin
return recd1.bo;
end;
function FUNC5(recd1: TR) return bit_vector is
begin
return recd1.bv;
end;
function FUNC6(recd1: TR) return real is
begin
return recd1.r;
end;
function FUNC7(recd1: TR) return time is
begin
return recd1.t;
end;
function FUNC8(recd1: TR) return etype is
begin
return recd1.e;
end;
function FUNC9(recd1: TR) return character is
begin
return recd1.c;
end;
BEGIN
TESTING: PROCESS
variable var1: TR;
variable var2: T1;
variable OkayCount: integer := 0;
BEGIN
wait for 1 ns;
var2 := (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
var1 := (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%');
var2 := FUNC1(var1);
if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
OkayCount := OkayCount + 1;
else
assert false report "bad return on FUNC1" severity note;
end if;
var2 := (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
if var2 = (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a') then
OkayCount := OkayCount + 1;
end if;
var2.i := FUNC2(var1);wait for 1 ns;assert var2.i=777 report "i no good" severity note;
var2.b := FUNC3(var1);wait for 1 ns;assert var2.b='1' report "b no good" severity note;
var2.bo := FUNC4(var1);wait for 1 ns;assert var2.bo=true report "bo no good" severity note;
var2.bv := FUNC5(var1);wait for 1 ns;assert var2.bv="0001" report "bv no good" severity note;
var2.r := FUNC6(var1);wait for 1 ns;assert var2.r=333.767 report "r no good" severity note;
var2.t := FUNC7(var1);wait for 1 ns;assert var2.t=44 ms report "t no good" severity note;
var2.e := FUNC8(var1);wait for 1 ns;assert var2.e=seven report "e no good" severity note;
var2.c := FUNC9(var1);wait for 1 ns;assert var2.c='%' report "c no good" severity note;
if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
OkayCount := OkayCount + 1;
else
assert false report "bad return on FUNC2-9" severity note;
end if;
wait for 1 ns;
assert NOT( OkayCount = 3 )
report "***PASSED TEST: c03s02b02x00p01n01i00493"
severity NOTE;
assert ( OkayCount = 3 )
report "***FAILED TEST: c03s02b02x00p01n01i00493 - Problem assigning record subelements in function."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p01n01i00493arch;
|
gpl-2.0
|
5ccb587e41e3444864095ab3a4a466b8
| 0.591353 | 3.209079 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_09.vhd
| 4 | 1,702 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_09.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_09 is
end entity ap_a_09;
library ieee; use ieee.std_logic_1164.all;
architecture test of ap_a_09 is
signal a, b, c, d : integer := 0;
begin
b1 : block is
signal y : integer;
begin
-- code from book
y <= a + b + c + d;
-- end code from book
end block b1;
b2 : block is
signal y : integer;
begin
-- code from book
y <= ( a + b ) + ( c + d );
-- end code from book
end block b2;
stimulus : process is
begin
a <= 1; wait for 10 ns;
b <= 2; wait for 10 ns;
c <= 3; wait for 10 ns;
d <= 4; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
0c7aad688d0d2c3d37230676bd6772fc
| 0.587544 | 3.773836 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd
| 3 | 62,178 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- Simple Digital-Controlled Two-position Switch Model
-- Switch position 1 ('0') or switch position 2 ('1')
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
ENTITY switch_dig_2in is
GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance
r_closed : RESISTANCE := 0.001; -- Closed switch resistance
trans_time : real := 0.00001); -- Transition time to each position
PORT (sw_state : in std_logic; -- Digital control input
TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output
END ENTITY switch_dig_2in;
ARCHITECTURE ideal OF switch_dig_2in IS
SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance
SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance
QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out
QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out
QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out
QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out
BEGIN
PROCESS (sw_state) -- Sensitivity to digital control input
BEGIN
IF (sw_state = '0') THEN -- Close sig1, open sig2
r_sig1 <= r_closed;
r_sig2 <= r_open;
ELSIF (sw_state = '1') THEN -- Open sig1, close sig2
r_sig1 <= r_open;
r_sig2 <= r_closed;
END IF;
END PROCESS;
r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
v1 == r1*i1; -- Apply Ohm's law to in1
v2 == r2*i2; -- Apply Ohm's law to in2
END ARCHITECTURE ideal;
--
-- Digital clock with 50% duty cycle
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clock IS
GENERIC (
period : time); -- Clock period
PORT (
clk_out : OUT std_logic);
END ENTITY clock;
ARCHITECTURE ideal OF clock IS
BEGIN
-- clock process
process
begin
clk_out <= '0';
wait for period/2;
clk_out <= '1';
wait for period/2;
end process;
END ARCHITECTURE ideal;
--
-- This digital clock allows user to specify the duty cycle using
-- the parameters "on_time" and "off_time"
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
ENTITY clock_duty IS
GENERIC (
on_time : time := 20 us;
off_time : time := 19.98 ms
);
PORT (
clock_out : OUT std_logic := '0');
END ENTITY clock_duty;
ARCHITECTURE ideal OF clock_duty IS
BEGIN
-- clock process
process
begin
clock_out <= '1';
wait for on_time;
clock_out <= '0';
wait for off_time;
end process;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rc_clk is
port(
clk_100k : out std_logic;
clk_6K : out std_logic;
clk_50 : out std_logic
);
end rc_clk;
architecture rc_clk of rc_clk is
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.clock(ideal)
generic map(
period => 10us
)
port map(
CLK_OUT => clk_100k
);
XCMP2 : entity work.clock(ideal)
generic map(
period => 150us
)
port map(
CLK_OUT => clk_6K
);
clk_50Hz : entity work.clock_duty(ideal)
generic map(
on_time => 20 us,
off_time => 19.98 ms
)
port map(
CLOCK_OUT => clk_50
);
end rc_clk;
--
-- This model counts the number of input clock transitions and outputs
-- a '1' when this number equals the value of the user-defined constant 'count'
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity bit_cnt is
generic (
count : integer -- User-defined value to count up to
);
port
(
bit_in : in std_logic ;
clk : in std_logic ;
dly_out : out std_logic
);
end bit_cnt;
architecture behavioral of bit_cnt is
begin
serial_clock : process is
begin
wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H');
FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions
wait until clk'event AND (clk = '1' OR clk = 'H');
END LOOP ;
dly_out <= '1'; -- After count is reached, set output high
wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L');
dly_out <= '0'; -- Reset output to '0' on next clock input
end process serial_clock;
end;
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.all;
USE IEEE_proposed.mechanical_systems.all;
ENTITY state_mach1 IS
PORT (
a2d_eoc : IN std_logic;
clk_50 : IN std_logic;
clk_100k : IN std_logic;
clk_6k : IN std_logic;
ser_done : IN std_logic;
ch_sel : OUT std_logic;
frm_gen : OUT std_logic;
a2d_oe : OUT std_logic;
a2d_start : OUT std_logic;
p2s_oe : OUT std_logic;
p2s_load : OUT std_logic;
parity_oe : OUT std_logic;
ser_cnt : OUT std_logic;
p2s_clr : OUT std_logic);
END state_mach1;
ARCHITECTURE state_diagram OF state_mach1 IS
ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2
, load, ad_ch2, delay);
SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1;
SIGNAL FB_frm_gen : std_logic;
SIGNAL FB_p2s_load : std_logic;
SIGNAL FB_ch_sel : std_logic;
BEGIN
frm_gen <= FB_frm_gen ;
p2s_load <= FB_p2s_load ;
ch_sel <= FB_ch_sel ;
sm1:
PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel)
BEGIN
CASE CS_state_mach1_sm1 IS
WHEN V_begin =>
FB_frm_gen <= ('1');
a2d_start <= ('0');
a2d_oe <= ('0');
FB_p2s_load <= ('0');
p2s_clr <= ('0');
p2s_oe <= ('0');
FB_ch_sel <= ('0');
parity_oe <= ('0');
ser_cnt <= ('0');
IF ((FB_frm_gen = '1')) THEN
NS_state_mach1_sm1 <= frm_rd;
ELSE
NS_state_mach1_sm1 <= V_begin;
END IF;
WHEN frm_rd =>
FB_p2s_load <= ('1');
IF ((FB_p2s_load = '1')) THEN
NS_state_mach1_sm1 <= ser_oe;
ELSE
NS_state_mach1_sm1 <= frm_rd;
END IF;
WHEN ser_oe =>
p2s_oe <= ('1');
FB_frm_gen <= ('0');
FB_p2s_load <= ('0');
ser_cnt <= ('1');
IF ((ser_done = '1')) THEN
NS_state_mach1_sm1 <= ch1;
ELSE
NS_state_mach1_sm1 <= ser_oe;
END IF;
WHEN ch1 =>
p2s_oe <= ('0');
FB_ch_sel <= ('0');
a2d_start <= ('1');
ser_cnt <= ('0');
IF ((a2d_eoc = '1')) THEN
NS_state_mach1_sm1 <= data_en;
ELSE
NS_state_mach1_sm1 <= ch1;
END IF;
WHEN data_en =>
a2d_start <= ('0');
a2d_oe <= ('1');
parity_oe <= ('1');
NS_state_mach1_sm1 <= load;
WHEN tdm_oe =>
a2d_oe <= ('0');
parity_oe <= ('0');
p2s_oe <= ('1');
FB_p2s_load <= ('0');
ser_cnt <= ('1');
IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN
NS_state_mach1_sm1 <= ch2;
ELSE
NS_state_mach1_sm1 <= tdm_oe;
END IF;
WHEN ch2 =>
p2s_oe <= ('0');
ser_cnt <= ('0');
FB_ch_sel <= ('1');
NS_state_mach1_sm1 <= delay;
WHEN load =>
FB_p2s_load <= ('1');
NS_state_mach1_sm1 <= tdm_oe;
WHEN ad_ch2 =>
a2d_start <= ('1');
IF ((a2d_eoc = '1')) THEN
NS_state_mach1_sm1 <= data_en;
ELSE
NS_state_mach1_sm1 <= ad_ch2;
END IF;
WHEN delay =>
NS_state_mach1_sm1 <= ad_ch2;
END CASE;
END PROCESS;
sm1_CTL:
PROCESS (clk_100k, clk_50)
BEGIN
IF (clk_100k'event AND clk_100k='1') THEN
IF (clk_50= '1' ) THEN
CS_state_mach1_sm1 <= V_begin;
ELSE
CS_state_mach1_sm1 <= NS_state_mach1_sm1;
END IF;
END IF;
END PROCESS;
END state_diagram;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sm_cnt is
port(
a2d_eoc : in std_logic;
clk_50 : in std_logic;
clk_100k : in std_logic;
clk_6k : in std_logic;
p2s_load : out std_logic;
p2s_oe : out std_logic;
parity_oe : out std_logic;
a2d_start : out std_logic;
a2d_oe : out std_logic;
frm_gen : out std_logic;
ch_sel : out std_logic;
p2s_clr : out std_logic
);
end sm_cnt;
architecture sm_cnt of sm_cnt is
-- Component declarations
-- Signal declarations
signal serial_cnt : std_logic;
signal XSIG010022 : std_logic;
begin
-- Signal assignments
-- Component instances
bit_cnt1 : entity work.bit_cnt(behavioral)
generic map(
count => 15
)
port map(
bit_in => serial_cnt,
clk => clk_6k,
dly_out => XSIG010022
);
state_mach16 : entity work.state_mach1
port map(
ser_cnt => serial_cnt,
ch_sel => ch_sel,
frm_gen => frm_gen,
a2d_oe => a2d_oe,
a2d_start => a2d_start,
parity_oe => parity_oe,
p2s_oe => p2s_oe,
p2s_load => p2s_load,
p2s_clr => p2s_clr,
clk_6k => clk_6k,
clk_100k => clk_100k,
clk_50 => clk_50,
a2d_eoc => a2d_eoc,
ser_done => XSIG010022
);
end sm_cnt;
--
--This is a VHDL-AMS model of a simple analog to digital converter. The model
--describes the general behavior of A/D converters for system level design and
--verification.
--The format of the digital output is binary coding.
--
--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
--
-- Use IEEE natures and packages
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity a2d_nbit is
generic (
Vmax: REAL := 5.0 ; -- ADC's maximum range
Nbits: INTEGER := 10 ; -- number bits in ADC's output
delay: TIME := 10 us -- ADC's conversion time
);
port (
signal start: in std_logic ; -- Start signal
signal clk: in std_logic ; -- Strobe clock
signal oe: in std_logic ; -- Output enable
terminal ain: ELECTRICAL ; -- ADC's analog input terminal
signal eoc: out std_logic := '0' ; -- End Of Conversion pin
signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal
end entity a2d_nbit;
architecture sar of a2d_nbit is
type states is (input, convert, output) ; -- Three states of A2D Conversion
constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout
quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
begin
sa_adc: process
variable thresh: REAL := Vmax ; -- Threshold to test input voltage against
variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts
variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data
variable status: states := input ; -- Begin with "input" CASE
variable bit_cnt: integer := Nbits -1 ;
begin
CASE status is
when input => -- Read input voltages when start goes high
wait on start until start = '1' or start = 'H' ;
thresh := Vmax ;
Vtmp := Vin ;
eoc <= '0' ;
status := convert ; -- Go to convert state
when convert => -- Begin successive approximation conversion
thresh := thresh / 2.0 ; -- Get value of MSB
wait on clk until clk = '1' OR clk = 'H';
if Vtmp > thresh then
dtmp(bit_cnt) := '1' ;
Vtmp := Vtmp - thresh ;
else
dtmp(bit_cnt) := '0' ;
end if ;
if bit_cnt < 1 then
status := output ; -- Go to output state
end if;
bit_cnt := bit_cnt - 1 ;
when output => -- Wait for output enable, then put data on output pins
eoc <= '1' after delay ;
wait on oe until oe = '1' OR oe = 'H' ;
dout <= dtmp ;
wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low
dout <= (others => 'Z') ;
bit_cnt := bit_range ;
status := input ; -- Set up for next conversion
END CASE ;
end process sa_adc ;
Iin == 0.0 ; -- Ideal input draws no current
end architecture sar ;
--
-- Parallel input/serial output shift register
-- With 4 trailing zeros
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity shift_reg is
generic ( td : time := 0 ns);
port
(
bus_in : in std_logic_vector ; -- Input bus
clk : in std_logic ; -- Shift clock
oe : in std_logic ; -- Output enable
ser_out : out std_logic := '0'; -- Output port
load : in std_logic ; -- Parallel input load
clr : in std_logic -- Clear register
);
end entity shift_reg;
architecture behavioral of shift_reg is
begin
control_proc : process
VARIABLE bit_val : std_logic_vector(11 downto 0); -- Default 12-bit input
begin
IF (clr = '1' OR clr = 'H') then
bit_val := "000000000000"; -- Set all input bits to zero
ELSE
wait until load'event AND (load = '1' OR load = 'H');
FOR i IN bus_in'high DOWNTO bus_in'low LOOP
bit_val(i) := bus_in(i) ; -- Transfer input data to variable
END LOOP ;
END IF;
wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled
FOR i IN bit_val'high DOWNTO bit_val'low LOOP
wait until clk'event AND (clk = '1' OR clk = 'H');
ser_out <= bit_val(i) ;
END LOOP ;
FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros
wait until clk'event AND (clk = '1' OR clk = 'H');
ser_out <= '0';
END LOOP;
END process;
end architecture behavioral;
--
-- This model generates a 12-bit data frame synchronization code
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity frame_gen is
port
(
oe : in std_logic := '0';
sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ");
end entity frame_gen;
architecture simple of frame_gen is
begin
enbl: PROCESS
BEGIN
WAIT ON OE;
IF OE = '1' THEN
sync_out <= "010101010101"; -- Sync code
ELSE
sync_out <= "ZZZZZZZZZZZZ";
END IF;
END PROCESS;
end architecture simple;
--
-- Two input XOR gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY xor2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY xor2;
ARCHITECTURE ideal OF xor2 IS
BEGIN
output <= in1 XOR in2 AFTER delay;
END ARCHITECTURE ideal;
--
-- level_set_tri.vhd
-- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z')
-- If OE = '0' set output to high impedance
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY level_set_tri IS
GENERIC (
logic_val : std_logic := 'Z');
PORT (
OE : IN std_logic;
level : OUT std_logic := 'Z');
END ENTITY level_set_tri;
-- Simple architecture
ARCHITECTURE ideal OF level_set_tri IS
BEGIN
oe_ctl: PROCESS
BEGIN
WAIT ON OE;
IF OE = '1' THEN
level <= logic_val;
ELSE
level <= 'Z';
END IF;
END PROCESS;
END ARCHITECTURE ideal;
--
-- Simple Tri-state Buffer with delay time
-- If OE = 1, output = input after delay
-- If OE /= 1, output = Z after delay
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY buffer_tri IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
input : IN std_logic;
OE : IN std_logic;
output : OUT std_logic);
END ENTITY buffer_tri;
ARCHITECTURE ideal OF buffer_tri IS
BEGIN
oe_ctl: PROCESS
BEGIN
WAIT ON OE, input;
IF OE = '1' THEN
output <= input AFTER delay;
ELSE
output <= 'Z' AFTER delay;
END IF;
END PROCESS;
END ARCHITECTURE ideal;
--
-- ideal one bit D/A converter
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY d2a_bit IS
GENERIC (vlow : real :=0.0; -- output high voltage
vhigh : real :=5.0); -- output low voltage
PORT (D : IN std_logic; -- digital (std_logic) intout
TERMINAL A : electrical); -- analog (electrical) output
END ENTITY d2a_bit;
ARCHITECTURE ideal OF d2a_bit IS
QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF;
SIGNAL vin : real := 0.0;
BEGIN
vin <= vhigh WHEN D = '1' ELSE vlow;
-- Use 'RAMP for discontinuous signal
vout == vin'RAMP(1.0e-9);
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity parity_gen is
port(
parity : in std_logic_vector(1 to 10);
oe : in std_logic;
parity_out : out std_logic_vector(0 to 11)
);
end parity_gen;
architecture parity_gen of parity_gen is
-- Component declarations
-- Signal declarations
terminal par_bit_gen_a : electrical;
signal XSIG010002 : std_logic;
signal XSIG010003 : std_logic;
signal XSIG010004 : std_logic;
signal XSIG010005 : std_logic;
signal XSIG010006 : std_logic;
signal XSIG010007 : std_logic;
signal XSIG010008 : std_logic;
signal XSIG010009 : std_logic;
signal XSIG010098 : std_logic;
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.xor2(ideal)
port map(
in1 => parity(1),
in2 => parity(2),
output => XSIG010002
);
XCMP2 : entity work.xor2(ideal)
port map(
in1 => parity(3),
in2 => parity(4),
output => XSIG010003
);
XCMP3 : entity work.xor2(ideal)
port map(
in1 => parity(5),
in2 => parity(6),
output => XSIG010004
);
XCMP4 : entity work.xor2(ideal)
port map(
in1 => parity(7),
in2 => parity(8),
output => XSIG010005
);
XCMP5 : entity work.xor2(ideal)
port map(
in1 => parity(9),
in2 => parity(10),
output => XSIG010008
);
XCMP6 : entity work.xor2(ideal)
port map(
in1 => XSIG010002,
in2 => XSIG010003,
output => XSIG010006
);
XCMP7 : entity work.xor2(ideal)
port map(
in1 => XSIG010004,
in2 => XSIG010005,
output => XSIG010007
);
XCMP8 : entity work.xor2(ideal)
port map(
in1 => XSIG010006,
in2 => XSIG010007,
output => XSIG010009
);
XCMP9 : entity work.xor2(ideal)
port map(
in1 => XSIG010009,
in2 => XSIG010008,
output => XSIG010098
);
XCMP18 : entity work.level_set_tri(ideal)
generic map(
logic_val => '1'
)
port map(
level => parity_out(11),
oe => oe
);
XCMP19 : entity work.buffer_tri(ideal)
port map(
input => parity(1),
output => parity_out(1),
oe => oe
);
XCMP20 : entity work.buffer_tri(ideal)
port map(
input => parity(2),
output => parity_out(2),
oe => oe
);
XCMP21 : entity work.buffer_tri(ideal)
port map(
input => parity(3),
output => parity_out(3),
oe => oe
);
XCMP22 : entity work.buffer_tri(ideal)
port map(
input => parity(4),
output => parity_out(4),
oe => oe
);
XCMP23 : entity work.buffer_tri(ideal)
port map(
input => parity(5),
output => parity_out(5),
oe => oe
);
XCMP24 : entity work.buffer_tri(ideal)
port map(
input => parity(6),
output => parity_out(6),
oe => oe
);
XCMP25 : entity work.buffer_tri(ideal)
port map(
input => parity(7),
output => parity_out(7),
oe => oe
);
XCMP26 : entity work.buffer_tri(ideal)
port map(
input => parity(8),
output => parity_out(8),
oe => oe
);
XCMP27 : entity work.buffer_tri(ideal)
port map(
input => parity(9),
output => parity_out(9),
oe => oe
);
XCMP28 : entity work.buffer_tri(ideal)
port map(
input => parity(10),
output => parity_out(10),
oe => oe
);
XCMP29 : entity work.buffer_tri(ideal)
port map(
input => XSIG010098,
output => parity_out(0),
oe => oe
);
XCMP30 : entity work.d2a_bit(ideal)
port map(
D => XSIG010098,
A => par_bit_gen_a
);
end parity_gen;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tdm_encoder is
port(
clk : in std_logic;
p2s_oe : in std_logic;
p2s_load : in std_logic;
frm_gen : in std_logic;
parity_oe : in std_logic;
tdm_out : out std_logic;
p2s_clr : in std_logic;
a2d_data : in std_logic_vector(1 to 10)
);
end tdm_encoder;
architecture tdm_encoder of tdm_encoder is
-- Component declarations
-- Signal declarations
signal sync_par : std_logic_vector(0 to 11);
begin
-- Signal assignments
-- Component instances
p2s1 : entity work.shift_reg(behavioral)
port map(
bus_in => sync_par,
clk => clk,
oe => p2s_oe,
ser_out => tdm_out,
load => p2s_load,
clr => p2s_clr
);
sync_gen1 : entity work.frame_gen(simple)
port map(
oe => frm_gen,
sync_out => sync_par
);
par_gen1 : entity work.parity_gen
port map(
parity => a2d_data,
parity_out => sync_par,
oe => parity_oe
);
end tdm_encoder;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity Digitize_Encode is
port(
tdm_out : out std_logic;
terminal ch1_in : electrical;
terminal ch2_in : electrical
);
end Digitize_Encode;
architecture Digitize_Encode of Digitize_Encode is
-- Component declarations
-- Signal declarations
terminal a2d_ana_in : electrical;
signal a2d_oe : std_logic;
signal ch_bus : std_logic_vector(1 to 10);
signal frm_gen_ctl : std_logic;
signal p2s_clr : std_logic;
signal p2s_load : std_logic;
signal p2s_oe : std_logic;
signal par_oe : std_logic;
signal start_a2d1 : std_logic;
signal sw_ctl : std_logic;
signal XSIG010091 : std_logic;
signal XSIG010173 : std_logic;
signal XSIG010180 : std_logic;
signal XSIG010181 : std_logic;
begin
-- Signal assignments
-- Component instances
A_SWITCH1 : entity work.switch_dig_2in(ideal)
port map(
p_in1 => ch1_in,
p_out => a2d_ana_in,
sw_state => sw_ctl,
p_in2 => ch2_in
);
rc_clk2 : entity work.rc_clk
port map(
clk_50 => XSIG010180,
clk_6K => XSIG010173,
clk_100k => XSIG010181
);
sm_xmtr1 : entity work.sm_cnt
port map(
clk_100k => XSIG010181,
a2d_start => start_a2d1,
a2d_eoc => XSIG010091,
p2s_oe => p2s_oe,
p2s_load => p2s_load,
ch_sel => sw_ctl,
frm_gen => frm_gen_ctl,
parity_oe => par_oe,
a2d_oe => a2d_oe,
clk_50 => XSIG010180,
clk_6k => XSIG010173,
p2s_clr => p2s_clr
);
a2d1 : entity work.a2d_nbit(sar)
generic map(
Vmax => 4.8
)
port map(
dout => ch_bus,
ain => a2d_ana_in,
clk => XSIG010181,
start => start_a2d1,
eoc => XSIG010091,
oe => a2d_oe
);
tdm_enc1 : entity work.tdm_encoder
port map(
clk => XSIG010173,
p2s_oe => p2s_oe,
tdm_out => tdm_out,
p2s_load => p2s_load,
a2d_data => ch_bus,
frm_gen => frm_gen_ctl,
parity_oe => par_oe,
p2s_clr => p2s_clr
);
end Digitize_Encode;
--
-- Electrical sinusoidal voltage source (stick.vhd)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY stick IS
-- Initialize parameters
GENERIC (
freq : real; -- frequency, [Hertz]
amplitude : real; -- amplitude, [Volt]
phase : real := 0.0; -- initial phase, [Degree]
offset : real := 0.0; -- DC value, [Volt]
df : real := 0.0; -- damping factor, [1/second]
ac_mag : real := 1.0; -- AC magnitude, [Volt]
ac_phase : real := 0.0); -- AC phase, [Degree]
-- Define ports as electrical terminals
PORT (
TERMINAL v_out : ELECTRICAL);
END ENTITY stick;
-- Ideal Architecture
ARCHITECTURE ideal OF stick IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
-- Declare Quantity for Phase in radians (calculated below)
QUANTITY phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
-- Two input AND gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY and2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY and2;
ARCHITECTURE ideal OF and2 IS
BEGIN
output <= in1 AND in2 AFTER delay;
END ARCHITECTURE ideal;
--
-- D Flip Flop with reset (negative edge triggered)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY d_latch_n_edge_rst IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
data, clk : IN std_logic;
q : OUT std_logic := '0';
qn : OUT std_logic := '1';
rst : IN std_logic := '0'); -- reset
END ENTITY d_latch_n_edge_rst ;
ARCHITECTURE behav OF d_latch_n_edge_rst IS
BEGIN
data_in : PROCESS(clk, rst) IS
BEGIN
IF clk = '0' AND clk'event AND rst /= '1' THEN
q <= data AFTER delay;
qn <= NOT data AFTER delay;
ELSIF rst = '1' THEN
q <= '0';
qn <= '1';
END IF;
END PROCESS data_in; -- End of process data_in
END ARCHITECTURE behav;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity counter_12 is
port(
cnt : out std_logic_vector(0 to 11);
reset : in std_logic;
enable : in std_logic;
clk : in std_logic
);
end counter_12;
architecture counter_12 of counter_12 is
-- Component declarations
-- Signal declarations
signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11);
signal XSIG010078 : std_logic;
signal XSIG010081 : std_logic;
signal XSIG010083 : std_logic;
signal XSIG010085 : std_logic;
signal XSIG010087 : std_logic;
signal XSIG010101 : std_logic;
signal XSIG010102 : std_logic;
signal XSIG010103 : std_logic;
signal XSIG010104 : std_logic;
signal XSIG010115 : std_logic;
signal XSIG010116 : std_logic;
signal XSIG010117 : std_logic;
signal XSIG010132 : std_logic;
begin
-- Signal assignments
cnt(0) <= cdb2vhdl_tmp_1(0);
cnt(1) <= cdb2vhdl_tmp_1(1);
cnt(2) <= cdb2vhdl_tmp_1(2);
cnt(3) <= cdb2vhdl_tmp_1(3);
cnt(4) <= cdb2vhdl_tmp_1(4);
cnt(5) <= cdb2vhdl_tmp_1(5);
cnt(6) <= cdb2vhdl_tmp_1(6);
cnt(7) <= cdb2vhdl_tmp_1(7);
cnt(8) <= cdb2vhdl_tmp_1(8);
cnt(9) <= cdb2vhdl_tmp_1(9);
cnt(10) <= cdb2vhdl_tmp_1(10);
cnt(11) <= cdb2vhdl_tmp_1(11);
-- Component instances
XCMP92 : entity work.and2(ideal)
port map(
in1 => clk,
in2 => enable,
output => XSIG010132
);
XCMP93 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => XSIG010132,
DATA => XSIG010078,
QN => XSIG010078,
Q => cdb2vhdl_tmp_1(0),
RST => reset
);
XCMP94 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(0),
DATA => XSIG010081,
QN => XSIG010081,
Q => cdb2vhdl_tmp_1(1),
RST => reset
);
XCMP95 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(1),
DATA => XSIG010083,
QN => XSIG010083,
Q => cdb2vhdl_tmp_1(2),
RST => reset
);
XCMP96 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(2),
DATA => XSIG010085,
QN => XSIG010085,
Q => cdb2vhdl_tmp_1(3),
RST => reset
);
XCMP97 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(3),
DATA => XSIG010087,
QN => XSIG010087,
Q => cdb2vhdl_tmp_1(4),
RST => reset
);
XCMP98 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(4),
DATA => XSIG010101,
QN => XSIG010101,
Q => cdb2vhdl_tmp_1(5),
RST => reset
);
XCMP99 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(5),
DATA => XSIG010102,
QN => XSIG010102,
Q => cdb2vhdl_tmp_1(6),
RST => reset
);
XCMP100 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(6),
DATA => XSIG010103,
QN => XSIG010103,
Q => cdb2vhdl_tmp_1(7),
RST => reset
);
XCMP101 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(7),
DATA => XSIG010104,
QN => XSIG010104,
Q => cdb2vhdl_tmp_1(8),
RST => reset
);
XCMP102 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(8),
DATA => XSIG010115,
QN => XSIG010115,
Q => cdb2vhdl_tmp_1(9),
RST => reset
);
XCMP103 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(9),
DATA => XSIG010116,
QN => XSIG010116,
Q => cdb2vhdl_tmp_1(10),
RST => reset
);
XCMP104 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(10),
DATA => XSIG010117,
QN => XSIG010117,
Q => cdb2vhdl_tmp_1(11),
RST => reset
);
end counter_12;
--
-- ideal one bit A/D converter
LIBRARY IEEE;
USE IEEE.math_real.ALL;
USE IEEE.std_logic_1164.ALL;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
ENTITY a2d_bit IS
GENERIC (
thres : real := 2.5); -- Threshold to determine logic output
PORT (
TERMINAL a : electrical; -- analog input
SIGNAL d : OUT std_logic); -- digital (std_logic) output
END ENTITY a2d_bit;
ARCHITECTURE ideal OF a2d_bit IS
QUANTITY vin ACROSS a;
BEGIN -- threshold
-- Process needed to detect threshold crossing and assign output (d)
PROCESS (vin'ABOVE(thres)) IS
BEGIN -- PROCESS
IF vin'ABOVE(thres) THEN
d <= '1';
ELSE
d <= '0';
END IF;
END PROCESS;
END ideal;
-- Digital clock with 50% duty cycle and enable pin
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clock_en IS
GENERIC (
pw : time); -- Clock pulse width
PORT (
enable : IN std_logic ;
clock_out : INOUT std_logic := '0');
END ENTITY clock_en;
ARCHITECTURE ideal OF clock_en IS
BEGIN
-- clock process
process (clock_out, enable) is
begin
if clock_out = '0' AND enable = '1' THEN
clock_out <= '1' after pw, '0' after 2*pw;
end if;
end process;
END ARCHITECTURE ideal;
--
-- Inverter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY inverter IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
input : IN std_logic;
output : OUT std_logic);
END ENTITY inverter;
ARCHITECTURE ideal OF inverter IS
BEGIN
output <= NOT input AFTER delay;
END ARCHITECTURE ideal;
--
-- Two input OR gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY or2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY or2;
ARCHITECTURE ideal OF or2 IS
BEGIN
output <= in1 OR in2 AFTER delay;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
ENTITY d2a_nbit IS
GENERIC (
vmax : real := 5.0; -- High output
vmin : real := 0.0; -- Low output
high_bit : integer := 9; -- High end of bit range for D/A
low_bit : integer := 0); -- Low end of bit range for D/A
PORT (
SIGNAL bus_in : IN STD_LOGIC_VECTOR; -- variable width vector input
SIGNAL latch : IN STD_LOGIC;
TERMINAL ana_out : electrical); -- analog output
END ENTITY d2a_nbit ;
ARCHITECTURE behavioral OF d2a_nbit IS
SIGNAL sout : real := 0.0;
QUANTITY vout across iout through ana_out TO electrical_ref;
BEGIN -- ARCHITECTURE behavioral
proc : PROCESS
VARIABLE v_sum : real; -- Sum of voltage contribution from each bit
VARIABLE delt_v : real; -- Represents the voltage value of each bit
BEGIN
WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high
v_sum := vmin;
delt_v := vmax - vmin;
FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions
delt_v := delt_v / 2.0;
IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN
v_sum := v_sum + delt_v;
END IF;
END LOOP;
sout <= v_sum;
END PROCESS;
vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels
END ARCHITECTURE behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity pw2ana is
port(
terminal ana_out : electrical;
terminal pw_in : electrical
);
end pw2ana;
architecture pw2ana of pw2ana is
-- Component declarations
-- Signal declarations
signal bus_servo : std_logic_vector(0 to 11);
signal XSIG010008 : std_logic;
signal XSIG010013 : std_logic;
signal XSIG010019 : std_logic;
signal XSIG010020 : std_logic;
signal XSIG010021 : std_logic;
signal XSIG010022 : std_logic;
begin
-- Signal assignments
-- Component instances
counter_rudder : entity work.counter_12
port map(
enable => XSIG010022,
cnt => bus_servo,
reset => XSIG010021,
clk => XSIG010008
);
XCMP3 : entity work.a2d_bit(ideal)
port map(
D => XSIG010022,
A => pw_in
);
clk_en_rudder : entity work.clock_en(ideal)
generic map(
pw => 500ns
)
port map(
CLOCK_OUT => XSIG010008,
enable => XSIG010022
);
XCMP5 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => XSIG010022,
output => XSIG010013
);
XCMP8 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => XSIG010020,
output => XSIG010021
);
XCMP9 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => XSIG010022,
output => XSIG010019
);
or_rudder : entity work.or2(ideal)
port map(
in1 => XSIG010022,
in2 => XSIG010019,
output => XSIG010020
);
DA1 : entity work.d2a_nbit(behavioral)
generic map(
vmax => 4.8,
high_bit => 9,
low_bit => 0
)
port map(
bus_in => bus_servo,
ana_out => ana_out,
latch => XSIG010013
);
end pw2ana;
--
-- 12-bit digital comparator model
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity dig_cmp is
port
(
eq : out std_logic := '0';
in1 : in std_logic_vector (0 to 11);
in2 : in std_logic_vector (0 to 11);
latch_in1 : in std_logic := '0'; -- Currently unused
latch_in2 : in std_logic := '0';
cmp : in std_logic := '0';
clk : in std_logic
);
end entity dig_cmp ;
architecture simple of dig_cmp is
begin
compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list
variable in2_hold : std_logic_vector (0 to 11) := "000000000000";
BEGIN
if latch_in2 = '1' then -- in2 data is latched and stored
in2_hold := in2;
end if;
if cmp = '1' then
if in1 = in2_hold then -- latched in2 checked against current in1
eq <= '0';
else eq <= '1';
end if;
end if;
END PROCESS;
end architecture simple;
-- Set/reset flip flop
-- When S goes high, Q is set high until reset
-- When R goes high, Q is set low until set
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sr_ff is
port
(
S : in std_logic ;
R : in std_logic ;
Q : out std_logic
);
end sr_ff ;
architecture simple of sr_ff is
begin
set_reset: PROCESS(S, R) IS
BEGIN
-- assert S='1' nand R='1' -- Warning if both inputs are high
-- report "S and R are both active. Use with caution"
-- severity warning;
if S'event AND S = '1' then
Q <= '1';
end if;
if R'event AND R = '1' then
Q <= '0';
end if;
END PROCESS set_reset;
end;
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.all;
USE IEEE_proposed.mechanical_systems.all;
ENTITY state_mach_rcvr IS
PORT (
clk_50 : IN std_logic;
clk_100k : IN std_logic;
ser_done : IN std_logic;
par_det : IN std_logic;
frm_det : IN std_logic;
clk_6k : IN std_logic;
start_pulse : IN std_logic;
dly_done : IN std_logic;
s2p_rst : OUT std_logic;
s2p_en : OUT std_logic;
cnt1_en : OUT std_logic;
cnt1_rst : OUT std_logic;
cmp1_ltch1 : OUT std_logic;
cmp1_ltch2 : OUT std_logic;
cnt2_en : OUT std_logic;
cnt2_rst : OUT std_logic;
cmp2_ltch1 : OUT std_logic;
cmp2_ltch2 : OUT std_logic;
da_latch : OUT std_logic;
ser_cnt : OUT std_logic;
dly_cnt : OUT std_logic;
par_oe : OUT std_logic);
END state_mach_rcvr;
ARCHITECTURE state_diagram OF state_mach_rcvr IS
ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt
, s_bit, par1, par2);
SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1;
BEGIN
sm1:
PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det)
BEGIN
CASE CS_state_mach_rcvr_sm1 IS
WHEN V_begin =>
cnt1_en <= ('0');
cnt1_rst <= ('1');
cmp1_ltch1 <= ('0');
cmp1_ltch2 <= ('0');
cnt2_en <= ('0');
cnt2_rst <= ('1');
cmp2_ltch1 <= ('0');
cmp2_ltch2 <= ('0');
s2p_en <= ('1');
s2p_rst <= ('0');
da_latch <= ('0');
ser_cnt <= ('0');
dly_cnt <= ('0');
par_oe <= ('0');
IF ((frm_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= s_bit;
ELSE
NS_state_mach_rcvr_sm1 <= V_begin;
END IF;
WHEN cnt =>
ser_cnt <= ('1');
cnt1_rst <= ('0');
cnt2_rst <= ('0');
IF ((ser_done = '1')) THEN
NS_state_mach_rcvr_sm1 <= par1;
ELSE
NS_state_mach_rcvr_sm1 <= cnt;
END IF;
WHEN ch1 =>
cmp1_ltch2 <= ('1');
ser_cnt <= ('0');
dly_cnt <= ('1');
IF (((start_pulse = '1') AND (dly_done = '1'))) THEN
NS_state_mach_rcvr_sm1 <= rst1;
ELSE
NS_state_mach_rcvr_sm1 <= ch1;
END IF;
WHEN rst1 =>
cmp1_ltch2 <= ('0');
ser_cnt <= ('1');
dly_cnt <= ('0');
par_oe <= ('0');
IF ((ser_done = '1')) THEN
NS_state_mach_rcvr_sm1 <= par2;
ELSE
NS_state_mach_rcvr_sm1 <= rst1;
END IF;
WHEN ch2 =>
cmp2_ltch2 <= ('1');
ser_cnt <= ('0');
da_latch <= ('1');
NS_state_mach_rcvr_sm1 <= rst2;
WHEN rst2 =>
cmp2_ltch2 <= ('0');
s2p_en <= ('0');
par_oe <= ('0');
da_latch <= ('0');
NS_state_mach_rcvr_sm1 <= cnt_cmp;
WHEN cnt_cmp =>
cnt1_en <= ('1');
cmp1_ltch1 <= ('1');
cnt2_en <= ('1');
cmp2_ltch1 <= ('1');
NS_state_mach_rcvr_sm1 <= rst_cnt;
WHEN rst_cnt =>
cnt1_en <= ('0');
cmp1_ltch1 <= ('0');
cnt2_en <= ('0');
cmp2_ltch1 <= ('0');
NS_state_mach_rcvr_sm1 <= rst_cnt;
WHEN s_bit =>
IF ((start_pulse = '1')) THEN
NS_state_mach_rcvr_sm1 <= cnt;
ELSE
NS_state_mach_rcvr_sm1 <= s_bit;
END IF;
WHEN par1 =>
par_oe <= ('1');
IF ((par_det = '0')) THEN
NS_state_mach_rcvr_sm1 <= ch1;
ELSIF ((par_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= rst1;
ELSE
NS_state_mach_rcvr_sm1 <= par1;
END IF;
WHEN par2 =>
par_oe <= ('1');
IF ((par_det = '0')) THEN
NS_state_mach_rcvr_sm1 <= ch2;
ELSIF ((par_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= rst2;
ELSE
NS_state_mach_rcvr_sm1 <= par2;
END IF;
END CASE;
END PROCESS;
sm1_CTL:
PROCESS (clk_100k, clk_50)
BEGIN
IF (clk_100k'event AND clk_100k='1') THEN
IF (clk_50= '1' ) THEN
CS_state_mach_rcvr_sm1 <= V_begin;
ELSE
CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1;
END IF;
END IF;
END PROCESS;
END state_diagram;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sm_cnt_rcvr is
port(
cmp1_ltch1 : out std_logic;
cmp2_ltch1 : out std_logic;
s2p_en : out std_logic;
s2p_rst : out std_logic;
frm_det : in std_logic;
par_det : in std_logic;
clk_100k : in std_logic;
clk_6k : in std_logic;
clk_50 : in std_logic;
start_pulse : in std_logic;
cnt1_en : out std_logic;
cnt1_rst : out std_logic;
cmp1_ltch2 : out std_logic;
cnt2_en : out std_logic;
cnt2_rst : out std_logic;
cmp2_ltch2 : out std_logic;
da_latch : out std_logic;
par_oe : out std_logic
);
end sm_cnt_rcvr;
architecture sm_cnt_rcvr of sm_cnt_rcvr is
-- Component declarations
-- Signal declarations
signal ser_cnt : std_logic;
signal XSIG010002 : std_logic;
signal XSIG010145 : std_logic;
signal XSIG010146 : std_logic;
begin
-- Signal assignments
-- Component instances
bit_cnt3 : entity work.bit_cnt(behavioral)
generic map(
count => 2
)
port map(
bit_in => XSIG010145,
clk => clk_6k,
dly_out => XSIG010146
);
bit_cnt4 : entity work.bit_cnt(behavioral)
generic map(
count => 10
)
port map(
bit_in => ser_cnt,
clk => clk_6k,
dly_out => XSIG010002
);
state_mach_rcvr8 : entity work.state_mach_rcvr
port map(
clk_100k => clk_100k,
clk_50 => clk_50,
s2p_rst => s2p_rst,
s2p_en => s2p_en,
cnt1_en => cnt1_en,
cnt1_rst => cnt1_rst,
cmp1_ltch1 => cmp1_ltch1,
cmp1_ltch2 => cmp1_ltch2,
cnt2_en => cnt2_en,
cnt2_rst => cnt2_rst,
cmp2_ltch1 => cmp2_ltch1,
cmp2_ltch2 => cmp2_ltch2,
da_latch => da_latch,
ser_cnt => ser_cnt,
ser_done => XSIG010002,
par_det => par_det,
frm_det => frm_det,
clk_6k => clk_6k,
start_pulse => start_pulse,
dly_done => XSIG010146,
dly_cnt => XSIG010145,
par_oe => par_oe
);
end sm_cnt_rcvr;
--
-- level_set.vhd
-- Set digital output "level" with parameter "logic_val" (default is '1')
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY level_set IS
GENERIC (
logic_val : std_logic := '1');
PORT (
level : OUT std_logic);
END ENTITY level_set;
-- Simple architecture
ARCHITECTURE ideal OF level_set IS
BEGIN
level <= logic_val;
END ARCHITECTURE ideal;
--
-- Serial to parallel data converter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity ser2par is
port
(
par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ";
clk : in std_logic ;
load_en : in std_logic ;
ser_in : in std_logic ;
reset : in std_logic
);
begin
end ser2par;
architecture a1 of ser2par is
BEGIN
sr_sm: PROCESS (load_en, clk, reset, ser_in)
BEGIN
if (reset = '1' and load_en = '1') then
par_out <= "000000000000"; -- Reset the parallel data out
elsif (reset = '0' and load_en = '1') then
if (clk'event and clk = '1') then
-- The register will shift when load is enabled
-- and will shift at rising edge of clock
par_out(0) <= ser_in; -- Input data shifts into bit 0
par_out(1) <= par_out(0);
par_out(2) <= par_out(1);
par_out(3) <= par_out(2);
par_out(4) <= par_out(3);
par_out(5) <= par_out(4);
par_out(6) <= par_out(5);
par_out(7) <= par_out(6);
par_out(8) <= par_out(7);
par_out(9) <= par_out(8);
par_out(10) <= par_out(9);
par_out(11) <= par_out(10);
end if;
else
par_out <= "ZZZZZZZZZZZZ"; -- No change in output. Tri-state if load_en = 0.
end if;
END PROCESS;
end;
--
-- This model ouputs a '1' when a specific bit pattern is encountered
-- Otherwise, it outputs a zero
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity frame_det is
port
(
bus_in : in std_logic_vector (0 to 11);
clk : in std_logic;
frm_bit : out std_logic := '0' -- Initialize output to zero
);
end entity frame_det;
architecture simple of frame_det is
begin
enbl: PROCESS (bus_in, clk) -- Sensitivity list
BEGIN
if bus_in = "010101010101" then -- This is the pre-defined bit pattern
if clk'event AND clk = '0' then -- Output updated synchronously
frm_bit <= '1';
end if;
else frm_bit <= '0';
end if;
END PROCESS;
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity parity_det is
port(
bus_in : in std_logic_vector(0 to 11);
par_bit : out std_logic;
oe : in std_logic
);
end parity_det;
architecture parity_det of parity_det is
-- Component declarations
-- Signal declarations
signal XSIG010010 : std_logic;
signal XSIG010011 : std_logic;
signal XSIG010012 : std_logic;
signal XSIG010013 : std_logic;
signal XSIG010014 : std_logic;
signal XSIG010015 : std_logic;
signal XSIG010016 : std_logic;
signal XSIG010017 : std_logic;
signal XSIG010019 : std_logic;
signal XSIG010057 : std_logic;
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.xor2(ideal)
port map(
in1 => bus_in(1),
in2 => bus_in(2),
output => XSIG010010
);
XCMP2 : entity work.xor2(ideal)
port map(
in1 => bus_in(3),
in2 => bus_in(4),
output => XSIG010011
);
XCMP3 : entity work.xor2(ideal)
port map(
in1 => bus_in(5),
in2 => bus_in(6),
output => XSIG010012
);
XCMP4 : entity work.xor2(ideal)
port map(
in1 => bus_in(7),
in2 => bus_in(8),
output => XSIG010013
);
XCMP5 : entity work.xor2(ideal)
port map(
in1 => bus_in(9),
in2 => bus_in(10),
output => XSIG010016
);
XCMP6 : entity work.xor2(ideal)
port map(
in1 => XSIG010010,
in2 => XSIG010011,
output => XSIG010014
);
XCMP7 : entity work.xor2(ideal)
port map(
in1 => XSIG010012,
in2 => XSIG010013,
output => XSIG010015
);
XCMP8 : entity work.xor2(ideal)
port map(
in1 => XSIG010014,
in2 => XSIG010015,
output => XSIG010017
);
XCMP9 : entity work.xor2(ideal)
port map(
in1 => XSIG010017,
in2 => XSIG010016,
output => XSIG010019
);
XCMP10 : entity work.xor2(ideal)
port map(
in1 => XSIG010019,
in2 => bus_in(0),
output => XSIG010057
);
XCMP12 : entity work.and2(ideal)
port map(
in1 => oe,
in2 => XSIG010057,
output => par_bit
);
end parity_det;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TDM_Demux_dbg is
port(
s2p_en : in std_logic;
tdm_in : in std_logic;
clk_6k : in std_logic;
s2p_rst : in std_logic;
par_det : out std_logic;
frm_det : out std_logic;
da_latch : in std_logic;
par_oe : in std_logic;
data_bus : out std_logic_vector(1 to 10);
start_bit : out std_logic
);
end TDM_Demux_dbg;
architecture TDM_Demux_dbg of TDM_Demux_dbg is
-- Component declarations
-- Signal declarations
terminal d2a_out : electrical;
signal rcvr_bus : std_logic_vector(0 to 11);
begin
-- Signal assignments
data_bus(1) <= rcvr_bus(1);
data_bus(2) <= rcvr_bus(2);
data_bus(3) <= rcvr_bus(3);
data_bus(4) <= rcvr_bus(4);
data_bus(5) <= rcvr_bus(5);
data_bus(6) <= rcvr_bus(6);
data_bus(7) <= rcvr_bus(7);
data_bus(8) <= rcvr_bus(8);
data_bus(9) <= rcvr_bus(9);
data_bus(10) <= rcvr_bus(10);
start_bit <= rcvr_bus(0);
-- Component instances
s2p1 : entity work.ser2par(a1)
port map(
par_out => rcvr_bus,
clk => clk_6k,
load_en => s2p_en,
ser_in => tdm_in,
reset => s2p_rst
);
frm_det1 : entity work.frame_det(simple)
port map(
bus_in => rcvr_bus,
frm_bit => frm_det,
clk => clk_6k
);
par_det1 : entity work.parity_det
port map(
bus_in => rcvr_bus,
par_bit => par_det,
oe => par_oe
);
XCMP113 : entity work.d2a_nbit(behavioral)
generic map(
low_bit => 1,
high_bit => 10,
vmax => 4.8
)
port map(
bus_in => rcvr_bus(1 to 10),
ana_out => d2a_out,
latch => da_latch
);
end TDM_Demux_dbg;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity Decode_PW is
port(
bit_stream_in : in std_logic;
terminal ch1_pw : electrical;
terminal ch2_pw : electrical
);
end Decode_PW;
architecture Decode_PW of Decode_PW is
-- Component declarations
-- Signal declarations
signal cmp_bus : std_logic_vector(0 to 11);
signal cnt1 : std_logic_vector(0 to 11);
signal cnt2 : std_logic_vector(0 to 11);
signal rud_clk : std_logic;
signal rud_cmp : std_logic;
signal rud_eq : std_logic;
signal rud_ff_rst : std_logic;
signal rud_ff_set : std_logic;
signal rud_ltch1 : std_logic;
signal rud_ltch2 : std_logic;
signal XSIG010225 : std_logic;
signal XSIG010228 : std_logic;
signal XSIG010229 : std_logic;
signal XSIG010256 : std_logic;
signal XSIG010266 : std_logic;
signal XSIG010267 : std_logic;
signal XSIG010268 : std_logic;
signal XSIG010289 : std_logic;
signal XSIG010315 : std_logic;
signal XSIG010339 : std_logic;
signal XSIG010357 : std_logic;
signal XSIG010371 : std_logic;
signal XSIG010373 : std_logic;
signal XSIG010383 : std_logic;
signal XSIG010384 : std_logic;
signal XSIG010385 : std_logic;
signal XSIG010386 : std_logic;
signal XSIG010390 : std_logic;
signal XSIG010433 : std_logic;
begin
-- Signal assignments
-- Component instances
cntr1 : entity work.counter_12
port map(
enable => XSIG010384,
cnt => cnt1,
reset => XSIG010357,
clk => XSIG010433
);
cntr2 : entity work.counter_12
port map(
enable => rud_cmp,
cnt => cnt2,
reset => XSIG010385,
clk => rud_clk
);
cmp1 : entity work.dig_cmp(simple)
port map(
in1 => cnt1,
eq => XSIG010371,
clk => XSIG010433,
in2 => cmp_bus,
cmp => XSIG010384,
latch_in1 => XSIG010256,
latch_in2 => XSIG010383
);
cmp2 : entity work.dig_cmp(simple)
port map(
in1 => cnt2,
eq => rud_eq,
clk => rud_clk,
in2 => cmp_bus,
cmp => rud_cmp,
latch_in1 => rud_ltch1,
latch_in2 => rud_ltch2
);
clk_1M2 : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => rud_clk,
enable => rud_cmp
);
clk_1M1 : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => XSIG010433,
enable => XSIG010384
);
XCMP134 : entity work.d2a_bit(ideal)
port map(
D => XSIG010371,
A => ch1_pw
);
XCMP135 : entity work.d2a_bit(ideal)
port map(
D => rud_eq,
A => ch2_pw
);
XCMP137 : entity work.SR_FF(simple)
port map(
S => rud_ff_set,
R => rud_ff_rst,
Q => rud_cmp
);
XCMP138 : entity work.inverter(ideal)
port map(
input => rud_eq,
output => rud_ff_rst
);
XCMP139 : entity work.SR_FF(simple)
port map(
S => XSIG010373,
R => XSIG010339,
Q => XSIG010384
);
XCMP140 : entity work.inverter(ideal)
port map(
input => XSIG010371,
output => XSIG010339
);
rc_clk2 : entity work.rc_clk
port map(
clk_50 => XSIG010289,
clk_6K => XSIG010225,
clk_100k => XSIG010315
);
sm_rcvr1 : entity work.sm_cnt_rcvr
port map(
cnt1_en => XSIG010373,
cmp1_ltch1 => XSIG010256,
cnt2_rst => XSIG010385,
clk_100k => XSIG010315,
cnt1_rst => XSIG010357,
cnt2_en => rud_ff_set,
cmp2_ltch1 => rud_ltch1,
frm_det => XSIG010229,
par_det => XSIG010228,
s2p_en => XSIG010266,
s2p_rst => XSIG010267,
clk_6k => XSIG010225,
clk_50 => XSIG010289,
da_latch => XSIG010268,
cmp1_ltch2 => XSIG010383,
cmp2_ltch2 => rud_ltch2,
start_pulse => XSIG010390,
par_oe => XSIG010386
);
XCMP155 : entity work.level_set(ideal)
generic map(
logic_val => '0'
)
port map(
level => cmp_bus(11)
);
XCMP157 : entity work.TDM_Demux_dbg
port map(
data_bus => cmp_bus(0 to 9),
tdm_in => bit_stream_in,
clk_6k => XSIG010225,
s2p_en => XSIG010266,
s2p_rst => XSIG010267,
da_latch => XSIG010268,
frm_det => XSIG010229,
par_det => XSIG010228,
par_oe => XSIG010386,
start_bit => XSIG010390
);
XCMP172 : entity work.level_set(ideal)
generic map(
logic_val => '1'
)
port map(
level => cmp_bus(10)
);
end Decode_PW;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CS1 is
end tb_CS1;
architecture TB_CS1 of tb_CS1 is
-- Component declarations
-- Signal declarations
terminal rudder : electrical;
terminal rudder_out : electrical;
terminal rudder_servo : electrical;
signal tdm_stream2 : std_logic;
terminal throttle : electrical;
terminal throttle_out : electrical;
terminal throttle_servo : electrical;
begin
-- Signal assignments
-- Component instances
Digitize_Encode1 : entity work.Digitize_Encode
port map(
ch2_in => rudder,
ch1_in => throttle,
tdm_out => tdm_stream2
);
throttle_1 : entity work.stick(ideal)
generic map(
freq => 1.0,
amplitude => 2.397,
phase => 0.0,
offset => 2.397
)
port map(
v_out => throttle
);
rudder_1 : entity work.stick(ideal)
generic map(
offset => 2.397,
phase => 90.0,
amplitude => 2.397,
freq => 1.0
)
port map(
v_out => rudder
);
pw2ana1 : entity work.pw2ana
port map(
ana_out => throttle_out,
pw_in => throttle_servo
);
pw2ana2 : entity work.pw2ana
port map(
ana_out => rudder_out,
pw_in => rudder_servo
);
Decode_PW10 : entity work.Decode_PW
port map(
bit_stream_in => tdm_stream2,
ch2_pw => rudder_servo,
ch1_pw => throttle_servo
);
end TB_CS1;
--
|
gpl-2.0
|
461a7700825ce5859e59c2130ff88f01
| 0.554022 | 3.398448 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc973.vhd
| 4 | 2,640 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc973.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00973ent IS
END c06s03b00x00p05n01i00973ent;
ARCHITECTURE c06s03b00x00p05n01i00973arch OF c06s03b00x00p05n01i00973ent IS
TYPE simple_record_2_type IS
RECORD
a2 : integer;
b2 : integer;
END RECORD;
TYPE array_of_records_type IS
ARRAY (20 TO 30) OF simple_record_2_type;
SIGNAL sr : array_of_records_type;
BEGIN
TESTING: PROCESS
VARIABLE ar,br : array_of_records_type;
FUNCTION convert (ain : array_of_records_type) RETURN integer IS
BEGIN
RETURN (ain(25).b2);
END;
BEGIN
wait for 1 ns;
br(20).b2 := 8;
ar(30).b2 := br(20).b2;
ar(30).b2 := 8;
ar(20).a2 := ar(30).b2;
sr(30).b2 <= 8;
wait for 1 ns;
sr(20).a2 <= sr(30).b2;
wait for 1 ns;
ar(25).b2 := 3;
sr(25).b2 <= 3;
wait for 1 ns;
assert NOT((ar(30).b2 = 8) AND
(ar(20).a2 = 8) AND
(sr(20).a2 = 8) AND
(convert(ar) = 3) AND
(convert(sr) = 3))
report "***PASSED TEST: c06s03b00x00p05n01i00973"
severity NOTE;
assert ((ar(30).b2 = 8) AND
(ar(20).a2 = 8) AND
(sr(20).a2 = 8) AND
(convert(ar) = 3) AND
(convert(sr) = 3))
report "***FAILED TEST: c06s03b00x00p05n01i00973 - The prefix fo the selected names can be an array."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00973arch;
|
gpl-2.0
|
0dc118dc4ade3787ffcd01d1f4ea0165
| 0.596591 | 3.32913 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/Modular/celda_V.vhd
| 1 | 1,457 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_V is
generic(
NUM_BITS : positive := 163
);
port(
R : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
X2 : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c1 : in STD_LOGIC;
c2 : in STD_LOGIC;
c3 : in STD_LOGIC;
clk : in STD_LOGIC;
RegV : out STD_LOGIC_VECTOR(NUM_BITS downto 0)
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_V is
----------------------------------------------------------------------------------------------------
signal toV : STD_LOGIC_VECTOR(NUM_BITS downto 0);
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
toV <= X2 when c1 = '0' and c2 = '0' else
(others => '0') when c1 = '0' and c2 = '1' else
R;
celda_V_process: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if c3 = '1' then
RegV <= toV;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
008bc7e2daf5207c0016fdc7636af851
| 0.356211 | 4.524845 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter-1.vhd
| 4 | 2,207 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity instruction_interpreter is
end entity instruction_interpreter;
architecture test of instruction_interpreter is
subtype word is bit_vector(31 downto 0);
signal address_bus, data_bus_in : word := X"0000_0000";
signal mem_read, mem_request, mem_ready, reset : bit := '0';
begin
-- code from book
instruction_interpreter : process is
-- . . .
-- not in book
variable mem_address_reg, mem_data_reg : word;
-- end not in book
procedure read_memory is
begin
address_bus <= mem_address_reg;
mem_read <= '1';
mem_request <= '1';
wait until mem_ready = '1' or reset = '1';
if reset = '1' then
return;
end if;
mem_data_reg := data_bus_in;
mem_request <= '0';
wait until mem_ready = '0';
end procedure read_memory;
begin
-- . . . -- initialization
-- not in book
if reset = '1' then
wait until reset = '0';
end if;
-- end not in book
loop
-- . . .
read_memory;
exit when reset = '1';
-- . . .
end loop;
end process instruction_interpreter;
-- end code from book
memory : process is
begin
wait until mem_request = '1';
data_bus_in <= X"1111_1111";
mem_ready <= '1' after 10 ns;
wait until mem_request = '0';
mem_ready <= '0' after 10 ns;
end process memory;
reset <= '1' after 85 ns;
end architecture test;
|
gpl-2.0
|
9c8051b28359a3baf19c94fc5d1858d9
| 0.639783 | 3.805172 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc464.vhd
| 4 | 3,395 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc464.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00464ent IS
END c03s02b01x01p19n01i00464ent;
ARCHITECTURE c03s02b01x01p19n01i00464arch OF c03s02b01x01p19n01i00464ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
constant C66: boolean_vector_range := (others => true);
function complex_scalar(s : boolean_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_vector_range;
signal S2 : boolean_vector_range;
signal S3 : boolean_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00464"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00464 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00464arch;
|
gpl-2.0
|
4a11f014064effb6f7b00cae80a04fed
| 0.656259 | 3.686211 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_01.vhd
| 4 | 2,419 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_11_01 is
end entity fg_11_01;
architecture test of fg_11_01 is
-- code from book (in text)
type tri_state_logic is ('0', '1', 'Z');
type tri_state_logic_array is array (integer range <>) of tri_state_logic;
-- end code from book
-- code from book
function resolve_tri_state_logic ( values : in tri_state_logic_array )
return tri_state_logic is
variable result : tri_state_logic := 'Z';
begin
for index in values'range loop
if values(index) /= 'Z' then
result := values(index);
end if;
end loop;
return result;
end function resolve_tri_state_logic;
-- end code from book
-- code from book (in text)
signal s1 : resolve_tri_state_logic tri_state_logic;
subtype resolved_logic is resolve_tri_state_logic tri_state_logic;
signal s2, s3 : resolved_logic;
-- end code from book
begin
source_1 : s1 <= 'Z',
'0' after 10 ns,
'Z' after 20 ns,
'1' after 30 ns,
'Z' after 40 ns,
'1' after 200 ns,
'Z' after 220 ns;
source_2 : s1 <= 'Z',
'0' after 110 ns,
'Z' after 120 ns,
'1' after 130 ns,
'Z' after 140 ns,
'1' after 200 ns,
'0' after 210 ns,
'Z' after 220 ns;
end architecture test;
|
gpl-2.0
|
0db45f3ae93c3daa2d5170ba90ee00d9
| 0.574618 | 3.8704 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_06.vhd
| 4 | 2,781 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
use work.words.all;
entity cpu is
port ( address : out uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity cpu;
-- not in book
architecture behavioral of cpu is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
use work.words.all;
entity memory is
port ( address : in uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity memory;
-- not in book
architecture behavioral of memory is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
-- not in book
use work.words.all;
entity ROM is
port ( a : in uword; d : out ubyte; other_port : in X01Z := 'Z' );
end entity ROM;
architecture behavioral of ROM is
begin
end architecture behavioral;
entity computer_system is
end entity computer_system;
-- end not in book
architecture top_level of computer_system is
use work.words.all;
signal address : uword;
signal data : word;
-- . . .
begin
the_cpu : entity work.cpu(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
the_memory : entity work.memory(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
-- . . .
-- code from book (in text)
-- boot_rom : entity work.ROM(behavioral)
-- port map ( a => address, d => data(24 to 31), -- . . . ); -- illegal
-- -- not in book
-- other_port => open );
-- -- end not in book
-- end code from book
end architecture top_level;
|
gpl-2.0
|
157202e18c34216121bd593067097cdd
| 0.581086 | 3.84116 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1727.vhd
| 4 | 1,970 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1727.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b01x00p04n03i01727ent IS
END c12s06b01x00p04n03i01727ent;
ARCHITECTURE c12s06b01x00p04n03i01727arch OF c12s06b01x00p04n03i01727ent IS
signal B : BIT := '1';
BEGIN
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
B <= '1','0' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on B;
assert NOT(( NOW = ShouldBeTime ) and ( B = '0' ))
report "***PASSED TEST: c12s06b01x00p04n03i01727"
severity NOTE;
assert (( NOW = ShouldBeTime ) and ( B = '0' ))
report "***FAILED TEST: c12s06b01x00p04n03i01727 - As time passes, the current transaction is deleted from the projected output waveform of that driver and the new tra nsaction takes its place."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b01x00p04n03i01727arch;
|
gpl-2.0
|
92ae476dcd9424d6826bd46e743a8b5e
| 0.66599 | 3.759542 | false | true | false | false |
stnolting/neo430
|
rtl/core/neo430_gpio.vhd
| 1 | 7,342 |
-- #################################################################################################
-- # << NEO430 - General Purpose Parallel IO Unit >> #
-- # ********************************************************************************************* #
-- # 16-bit parallel input & output unit. Any pin-change (HI->LO or LO->HI) triggers the IRQ. #
-- # Pins used for the pin change interrupt are selected using a 16-bit mask. #
-- # The PWM controller can be used to module the GPIO controller's output. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_gpio is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- parallel io --
gpio_o : out std_ulogic_vector(15 downto 0);
gpio_i : in std_ulogic_vector(15 downto 0);
-- GPIO PWM --
gpio_pwm_i : in std_ulogic;
-- interrupt --
irq_o : out std_ulogic
);
end neo430_gpio;
architecture neo430_gpio_rtl of neo430_gpio is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(gpio_size_c); -- low address boundary bit
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wren : std_ulogic; -- word write enable
signal rden : std_ulogic; -- read enable
-- accessible regs --
signal dout, din : std_ulogic_vector(15 downto 0); -- r/w
signal irq_mask : std_ulogic_vector(15 downto 0); -- -/w
-- misc --
signal irq_raw, sync_in, in_buf : std_ulogic_vector(15 downto 0);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = gpio_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= gpio_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wren <= acc_en and wren_i;
rden <= acc_en and rden_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wren = '1') then
if (addr = gpio_out_addr_c) then
dout <= data_i;
end if;
if (addr = gpio_irqmask_addr_c) then
irq_mask <= data_i;
end if;
end if;
end if;
end process wr_access;
-- (PWM modulated) output --
gpio_o <= dout when (gpio_pwm_i = '1') else (others => '0');
-- IRQ Generator ------------------------------------------------------------
-- -----------------------------------------------------------------------------
irq_generator: process(clk_i)
begin
if rising_edge(clk_i) then
-- input synchronizer --
in_buf <= gpio_i;
din <= in_buf;
sync_in <= din;
-- IRQ --
irq_o <= or_all_f(irq_raw);
end if;
end process irq_generator;
-- any transition triggers an interrupt (if enabled for according input pin) --
irq_raw <= (din xor sync_in) and irq_mask;
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
-- read access --
data_o <= (others => '0');
if (rden = '1') then
if (addr = gpio_in_addr_c) then
data_o <= din;
else -- gpio_out_addr_c
data_o <= dout;
end if;
end if;
end if;
end process rd_access;
end neo430_gpio_rtl;
|
bsd-3-clause
|
fd8ffe111a64c8b3c8427836b85f73ec
| 0.444702 | 4.839815 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug21497/repro.vhdl
| 3 | 501 |
entity tb is
generic (low : integer := 1 ; high : integer := 10);
end;
architecture behav of tb is
begin
process
type st_arr1 is array (low to high) of integer;
type st_arr2 is array (low to high) of st_arr1;
constant c_st_arr2 : st_arr2 := (others => (others => 1));
type a_st_arr2 is access st_arr2;
variable v_st_arr2 : a_st_arr2 := new st_arr2'(c_st_arr2) ;
begin
assert v_st_arr2.all = c_st_arr2 severity failure;
wait;
end process ;
end behav;
|
gpl-2.0
|
7cd0eb44b847e6a67ac4343e6a40ffd6
| 0.618762 | 2.947059 | false | false | false | false |
mmoraless/ecc_vhdl
|
ecc_add/lut3inadd_113.vhd
| 1 | 6,325 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------------------------
entity lut_3inadd is
generic(
NUM_BITS: positive := 113
);
port (
I: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
B: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
C: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
D: out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end;
---------------------------------------------------------------------------------------------
architecture behave of lut_3inadd is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
constant a : std_logic_vector(NUM_BITS-1 downto 0):= "00011000010001000001001010000110010100110111001111100011111111110011001001001110011101000010110000010000011110111";
begin
D(0) <= I(0) xor B(0) xor C(0) xor a(0);
D(1) <= I(1) xor B(1) xor C(1) xor a(1);
D(2) <= I(2) xor B(2) xor C(2) xor a(2);
D(3) <= I(3) xor B(3) xor C(3) xor a(3);
D(4) <= I(4) xor B(4) xor C(4) xor a(4);
D(5) <= I(5) xor B(5) xor C(5) xor a(5);
D(6) <= I(6) xor B(6) xor C(6) xor a(6);
D(7) <= I(7) xor B(7) xor C(7) xor a(7);
D(8) <= I(8) xor B(8) xor C(8) xor a(8);
D(9) <= I(9) xor B(9) xor C(9) xor a(9);
D(10) <= I(10) xor B(10) xor C(10) xor a(10);
D(11) <= I(11) xor B(11) xor C(11) xor a(11);
D(12) <= I(12) xor B(12) xor C(12) xor a(12);
D(13) <= I(13) xor B(13) xor C(13) xor a(13);
D(14) <= I(14) xor B(14) xor C(14) xor a(14);
D(15) <= I(15) xor B(15) xor C(15) xor a(15);
D(16) <= I(16) xor B(16) xor C(16) xor a(16);
D(17) <= I(17) xor B(17) xor C(17) xor a(17);
D(18) <= I(18) xor B(18) xor C(18) xor a(18);
D(19) <= I(19) xor B(19) xor C(19) xor a(19);
D(20) <= I(20) xor B(20) xor C(20) xor a(20);
D(21) <= I(21) xor B(21) xor C(21) xor a(21);
D(22) <= I(22) xor B(22) xor C(22) xor a(22);
D(23) <= I(23) xor B(23) xor C(23) xor a(23);
D(24) <= I(24) xor B(24) xor C(24) xor a(24);
D(25) <= I(25) xor B(25) xor C(25) xor a(25);
D(26) <= I(26) xor B(26) xor C(26) xor a(26);
D(27) <= I(27) xor B(27) xor C(27) xor a(27);
D(28) <= I(28) xor B(28) xor C(28) xor a(28);
D(29) <= I(29) xor B(29) xor C(29) xor a(29);
D(30) <= I(30) xor B(30) xor C(30) xor a(30);
D(31) <= I(31) xor B(31) xor C(31) xor a(31);
D(32) <= I(32) xor B(32) xor C(32) xor a(32);
D(33) <= I(33) xor B(33) xor C(33) xor a(33);
D(34) <= I(34) xor B(34) xor C(34) xor a(34);
D(35) <= I(35) xor B(35) xor C(35) xor a(35);
D(36) <= I(36) xor B(36) xor C(36) xor a(36);
D(37) <= I(37) xor B(37) xor C(37) xor a(37);
D(38) <= I(38) xor B(38) xor C(38) xor a(38);
D(39) <= I(39) xor B(39) xor C(39) xor a(39);
D(40) <= I(40) xor B(40) xor C(40) xor a(40);
D(41) <= I(41) xor B(41) xor C(41) xor a(41);
D(42) <= I(42) xor B(42) xor C(42) xor a(42);
D(43) <= I(43) xor B(43) xor C(43) xor a(43);
D(44) <= I(44) xor B(44) xor C(44) xor a(44);
D(45) <= I(45) xor B(45) xor C(45) xor a(45);
D(46) <= I(46) xor B(46) xor C(46) xor a(46);
D(47) <= I(47) xor B(47) xor C(47) xor a(47);
D(48) <= I(48) xor B(48) xor C(48) xor a(48);
D(49) <= I(49) xor B(49) xor C(49) xor a(49);
D(50) <= I(50) xor B(50) xor C(50) xor a(50);
D(51) <= I(51) xor B(51) xor C(51) xor a(51);
D(52) <= I(52) xor B(52) xor C(52) xor a(52);
D(53) <= I(53) xor B(53) xor C(53) xor a(53);
D(54) <= I(54) xor B(54) xor C(54) xor a(54);
D(55) <= I(55) xor B(55) xor C(55) xor a(55);
D(56) <= I(56) xor B(56) xor C(56) xor a(56);
D(57) <= I(57) xor B(57) xor C(57) xor a(57);
D(58) <= I(58) xor B(58) xor C(58) xor a(58);
D(59) <= I(59) xor B(59) xor C(59) xor a(59);
D(60) <= I(60) xor B(60) xor C(60) xor a(60);
D(61) <= I(61) xor B(61) xor C(61) xor a(61);
D(62) <= I(62) xor B(62) xor C(62) xor a(62);
D(63) <= I(63) xor B(63) xor C(63) xor a(63);
D(64) <= I(64) xor B(64) xor C(64) xor a(64);
D(65) <= I(65) xor B(65) xor C(65) xor a(65);
D(66) <= I(66) xor B(66) xor C(66) xor a(66);
D(67) <= I(67) xor B(67) xor C(67) xor a(67);
D(68) <= I(68) xor B(68) xor C(68) xor a(68);
D(69) <= I(69) xor B(69) xor C(69) xor a(69);
D(70) <= I(70) xor B(70) xor C(70) xor a(70);
D(71) <= I(71) xor B(71) xor C(71) xor a(71);
D(72) <= I(72) xor B(72) xor C(72) xor a(72);
D(73) <= I(73) xor B(73) xor C(73) xor a(73);
D(74) <= I(74) xor B(74) xor C(74) xor a(74);
D(75) <= I(75) xor B(75) xor C(75) xor a(75);
D(76) <= I(76) xor B(76) xor C(76) xor a(76);
D(77) <= I(77) xor B(77) xor C(77) xor a(77);
D(78) <= I(78) xor B(78) xor C(78) xor a(78);
D(79) <= I(79) xor B(79) xor C(79) xor a(79);
D(80) <= I(80) xor B(80) xor C(80) xor a(80);
D(81) <= I(81) xor B(81) xor C(81) xor a(81);
D(82) <= I(82) xor B(82) xor C(82) xor a(82);
D(83) <= I(83) xor B(83) xor C(83) xor a(83);
D(84) <= I(84) xor B(84) xor C(84) xor a(84);
D(85) <= I(85) xor B(85) xor C(85) xor a(85);
D(86) <= I(86) xor B(86) xor C(86) xor a(86);
D(87) <= I(87) xor B(87) xor C(87) xor a(87);
D(88) <= I(88) xor B(88) xor C(88) xor a(88);
D(89) <= I(89) xor B(89) xor C(89) xor a(89);
D(90) <= I(90) xor B(90) xor C(90) xor a(90);
D(91) <= I(91) xor B(91) xor C(91) xor a(91);
D(92) <= I(92) xor B(92) xor C(92) xor a(92);
D(93) <= I(93) xor B(93) xor C(93) xor a(93);
D(94) <= I(94) xor B(94) xor C(94) xor a(94);
D(95) <= I(95) xor B(95) xor C(95) xor a(95);
D(96) <= I(96) xor B(96) xor C(96) xor a(96);
D(97) <= I(97) xor B(97) xor C(97) xor a(97);
D(98) <= I(98) xor B(98) xor C(98) xor a(98);
D(99) <= I(99) xor B(99) xor C(99) xor a(99);
D(100) <= I(100) xor B(100) xor C(100) xor a(100);
D(101) <= I(101) xor B(101) xor C(101) xor a(101);
D(102) <= I(102) xor B(102) xor C(102) xor a(102);
D(103) <= I(103) xor B(103) xor C(103) xor a(103);
D(104) <= I(104) xor B(104) xor C(104) xor a(104);
D(105) <= I(105) xor B(105) xor C(105) xor a(105);
D(106) <= I(106) xor B(106) xor C(106) xor a(106);
D(107) <= I(107) xor B(107) xor C(107) xor a(107);
D(108) <= I(108) xor B(108) xor C(108) xor a(108);
D(109) <= I(109) xor B(109) xor C(109) xor a(109);
D(110) <= I(110) xor B(110) xor C(110) xor a(110);
D(111) <= I(111) xor B(111) xor C(111) xor a(111);
D(112) <= I(112) xor B(112) xor C(112) xor a(112);
end;
|
gpl-3.0
|
03d54068d390c2e65572fb256e453033
| 0.502292 | 2.001582 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/Architecture1_Pipeline/decryptionLoopCore_V1_tb.vhd
| 1 | 3,479 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 08:22:22 PM
-- Design Name:
-- Module Name: decryptionLoopCore_V1_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decryptionLoopCore_V1_tb is
end decryptionLoopCore_V1_tb;
architecture Behavioral of decryptionLoopCore_V1_tb is
component decryptionLoopCore_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
memorySourceSelector : in STD_LOGIC;
keySelector : in STD_LOGIC_VECTOR (1 downto 0);
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component controlUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
loadSourceSelector : out STD_LOGIC;
addRoundKeySelector1 : out STD_LOGIC_VECTOR(1 downto 0);
addRoundKeySelector2 : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
constant clk_period : time := 2ns;
signal CLK, RESET, ENABLE, memorySourceSelector : STD_LOGIC := '0';
signal keySelector : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal cipherKey : STD_LOGIC_VECTOR(127 downto 0) := (others => '0');
signal WORD_IN, WORD_OUT : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
ENABLE <= '1';
uut: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => memorySourceSelector,
keySelector => keySelector,
cipherKey => cipherKey,
WORD_IN => WORD_IN,
WORD_OUT => WORD_OUT);
controlUnit0: controlUnit port map( CLK => CLK,
RESET => RESET,
ENABLE => ENABLE,
loadSourceSelector => memorySourceSelector,
addRoundKeySelector1 => open,
addRoundKeySelector2 => keySelector);
clk_process: process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process;
--Source http://kavaliro.com/wp-content/uploads/2014/03/AES.pdf decrypt ROUND 10
stim_process: process
begin
--Wait for one clk_period to synchronize the control unit.
--During this clk_period, the first addRoundKey would occur.
wait for clk_period;
cipherKey <= x"BFE2BF904559FAB2A16480B4F7F1CBD8";
WORD_IN <= x"013E8EA7";
wait for clk_period;
WORD_IN <= x"3AB004BC";
wait for clk_period;
WORD_IN <= x"8CE23D4D";
wait for clk_period;
WORD_IN <= x"2133B81C";
wait for clk_period;
WORD_IN <= (others => '0');
end process;
end Behavioral;
|
gpl-2.0
|
9846362c6ac55c49c29846e7adeaac70
| 0.509342 | 4.601852 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1981.vhd
| 4 | 1,828 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1981.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p01n03i01981ent IS
END c07s02b02x00p01n03i01981ent;
ARCHITECTURE c07s02b02x00p01n03i01981arch OF c07s02b02x00p01n03i01981ent IS
BEGIN
TESTING: PROCESS
variable i, j, k, l, m, n, o, p : integer := 1;
BEGIN
if (i<j or (i>= 0) ) then -- No_failure_here
k := 5;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p01n03i01981"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p01n03i01981 - The result type of each relational operator is the predefined type BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p01n03i01981arch;
|
gpl-2.0
|
dd29db811fb8678cb127f8548b671de9
| 0.65919 | 3.570313 | false | true | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/shifter.vhd
| 1 | 785 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity shifter is
port (in1: in std_logic_vector(23 downto 0);
in2: in unsigned(4 downto 0);
clk,rst: in std_logic;
res: out std_logic_vector (47 downto 0)
);
end shifter;
architecture arch_shifter_1 of shifter is
signal a:unsigned(47 downto 0);
signal r:unsigned(47 downto 0);
begin
a<="000000000000000000000000" & unsigned(in1);
res<=std_logic_vector(r);
process (clk, rst)
begin
if rst='0' then
r <= (others => '0');
elsif(in2="00000") then
r <= (others => '0');
else
if (rising_edge(clk)) then
r<=a sll to_integer(in2);
end if;
end if;
end process;
end arch_shifter_1;
|
mit
|
be6c30f6b02e2851f602bd92377f7b1c
| 0.611465 | 3.15261 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1834.vhd
| 4 | 1,836 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1834.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01834ent IS
type small_int is range 0 to 7;
END c07s01b00x00p08n01i01834ent;
ARCHITECTURE c07s01b00x00p08n01i01834arch OF c07s01b00x00p08n01i01834ent IS
BEGIN
TESTING : PROCESS
variable tmp : small_int := 0;
BEGIN
case c07s01b00x00p08n01i01834ent is -- entity name illegal here
when 0 => tmp := 0;
when others => tmp := 1;
end case;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01834 - Entity name are not permitted as primaries in a case expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01834arch;
|
gpl-2.0
|
0d56130727960780f761154c02566adb
| 0.662309 | 3.709091 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1505.vhd
| 4 | 1,836 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1505.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n03i01505ent IS
END c08s08b00x00p14n03i01505ent;
ARCHITECTURE c08s08b00x00p14n03i01505arch OF c08s08b00x00p14n03i01505ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 19;
variable k : integer := 0;
BEGIN
case x is
when others => k:=5;
end case;
assert NOT( k=5 )
report "***PASSED TEST: c08s08b00x00p14n03i01505"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s08b00x00p14n03i01505 - OTHERS choice may stand foe the full set of values of the expression in a case statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n03i01505arch;
|
gpl-2.0
|
a6394fbff54b01906c17924df8dc3bc8
| 0.663943 | 3.672 | false | true | false | false |
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.b.f-tbMul.vhd
| 1 | 2,061 |
--------------------------------------------------------------------------------
-- FILE: tbMul
-- DESC: Testbench for Multiplier
--
-- Author:
-- Create: 2015-05-24
-- Update: 2015-05-24
-- Status: UNTESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity tbMul is
end tbMul;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture behav of tbMul is
constant N: integer :=16;
constant S: integer :=4;
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal ia: std_logic_vector(N-1 downto 0):=x"0000";
signal ib: std_logic_vector(N-1 downto 0):=x"0000";
signal oy: std_logic_vector(2*N-1 downto 0):=x"00000000";
component Mul is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE/2;
STAGE : integer := C_MUL_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE*2-1 downto 0):=(others=>'0') -- Data Out
);
end component;
begin
MUL0: Mul
generic map (N, S)
port map (rst, clk, ia, ib, oy);
-- Clock generator
PCLOCK : process(clk)
begin
clk <= not(clk) after 0.5 ns;
end process;
-- Reset test
rst <= '0', '1' after 2 ns;
ia<=x"0000", x"0001" after 1 ns, x"f010" after 2 ns, x"84d2" after 3 ns, x"3952" after 4 ns, x"ffff" after 5 ns, x"efff" after 6 ns;
ib<=x"0000", x"0001" after 1 ns, x"00e0" after 2 ns, x"5a25" after 3 ns, x"a7ff" after 4 ns, x"ffff" after 5 ns, x"efff" after 6 ns;
end behav;
configuration tb_mul_cfg of tbMul is
for behav
end for;
end tb_mul_cfg;
|
mit
|
a87f16719865b7e7af618ffb56fd0f56
| 0.491509 | 3.287081 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc298.vhd
| 4 | 1,838 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc298.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n03i00298ent IS
END c03s01b03x01p01n03i00298ent;
ARCHITECTURE c03s01b03x01p01n03i00298arch OF c03s01b03x01p01n03i00298ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( (us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) )
report "***PASSED TEST: c03s01b03x01p01n03i00298"
severity NOTE;
assert ( (us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) )
report "***FAILED TEST: c03s01b03x01p01n03i00298 - Type TIME is defined with an ascending ragne."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n03i00298arch;
|
gpl-2.0
|
d22f860d90cdc0aaee9ff9d4b63091a0
| 0.642002 | 3.728195 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc31.vhd
| 4 | 20,716 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc31.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p01n01i00031ent IS
END c04s03b01x01p01n01i00031ent;
ARCHITECTURE c04s03b01x01p01n01i00031arch OF c04s03b01x01p01n01i00031ent IS
--
--
-- Declaration of composite types
-- - array types and subtypes
--
TYPE ut_chary IS ARRAY (CHARACTER RANGE <>) OF INTEGER; -- unconstrained array type
TYPE ct_word IS ARRAY (0 TO 15) OF BIT; -- constrained array type
SUBTYPE ust_subchary IS ut_chary; -- unconstrained array subtype
SUBTYPE cst_str10 IS STRING ( 1 TO 10 ); -- constrained array subtype
SUBTYPE cst_digit IS ut_chary ('0' TO '9'); -- constrained array subtype
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE rt_date IS
RECORD
day : INTEGER RANGE 1 TO 31;
month : month_name;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
SUBTYPE rst_date IS rt_date;
BEGIN
TESTING: PROCESS
--
-- Constant declarations - without range constraint
--
CONSTANT STRING_con_1 : STRING := "sailing";
CONSTANT STRING_con_2 : STRING := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
CONSTANT BIT_VECTOR_con_1 : BIT_VECTOR := B"10101110";
CONSTANT BIT_VECTOR_con_2 : BIT_VECTOR := ( '1', '0', '1', '0', '1', '1', '1', '0');
CONSTANT ut_chary_con : ut_chary := ( 1, 2, 3, 9, 8, 7);
CONSTANT ct_word_con : ct_word := ( '0', '0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0', '0');
CONSTANT cst_str10_con_1 : cst_str10 := "abcdefghij";
CONSTANT cst_str10_con_2 : cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j');
CONSTANT cst_digit_con : cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
CONSTANT rt_date_con : rt_date := (1, Jan, 1989);
CONSTANT rst_date_con : rst_date := (1, Apr, 2000);
----------------------------------------------------------------------------------------------------------
BEGIN
ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(NUL) = 1 REPORT "ut_chary_con('a') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(SOH) = 2 REPORT "ut_chary_con('b') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(STX) = 3 REPORT "ut_chary_con('c') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(ETX) = 9 REPORT "ut_chary_con('d') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(EOT) = 8 REPORT "ut_chary_con('e') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con(ENQ) = 7 REPORT "ut_chary_con('f') not properly intialized" SEVERITY FAILURE;
FOR I IN 0 TO 15
LOOP
ASSERT ct_word_con(I) = '0' REPORT "ct_word_con(I) not properly intialized" SEVERITY FAILURE;
END LOOP;
ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('0') = 0 REPORT "cst_digit_con('0') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('1') = 1 REPORT "cst_digit_con('1') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('2') = 2 REPORT "cst_digit_con('2') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('3') = 3 REPORT "cst_digit_con('3') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('4') = 4 REPORT "cst_digit_con('4') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('5') = 5 REPORT "cst_digit_con('5') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('6') = 6 REPORT "cst_digit_con('6') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('7') = 7 REPORT "cst_digit_con('7') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('8') = 8 REPORT "cst_digit_con('8') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con('9') = 9 REPORT "cst_digit_con('9') not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con.day = 1 REPORT "rt_date_con.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con.month = Jan REPORT "rt_date_con.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con.year = 1989 REPORT "rt_date_con.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con.day = 1 REPORT "rst_date_con.day not properly intialized" SEVERITY
FAILURE;
ASSERT rst_date_con.month = Apr REPORT "rst_date_con.month not properly intialized" SEVERITY
FAILURE;
ASSERT rst_date_con.year = 2000 REPORT "rst_date_con.year not properly intialized" SEVERITY
FAILURE;
---------------------------------------------------------------------------------------------
assert NOT( STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con(NUL) = 1 and
ut_chary_con(SOH) = 2 and
ut_chary_con(STX) = 3 and
ut_chary_con(ETX) = 9 and
ut_chary_con(EOT) = 8 and
ut_chary_con(ENQ) = 7 and
ct_word_con(0) = '0' and
ct_word_con(1) = '0' and
ct_word_con(2) = '0' and
ct_word_con(3) = '0' and
ct_word_con(4) = '0' and
ct_word_con(5) = '0' and
ct_word_con(6) = '0' and
ct_word_con(7) = '0' and
ct_word_con(8) = '0' and
ct_word_con(9) = '0' and
ct_word_con(10) = '0' and
ct_word_con(11) = '0' and
ct_word_con(12) = '0' and
ct_word_con(13) = '0' and
ct_word_con(14) = '0' and
ct_word_con(15) = '0' and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con('0') = 0 and
cst_digit_con('1') = 1 and
cst_digit_con('2') = 2 and
cst_digit_con('3') = 3 and
cst_digit_con('4') = 4 and
cst_digit_con('5') = 5 and
cst_digit_con('6') = 6 and
cst_digit_con('7') = 7 and
cst_digit_con('8') = 8 and
cst_digit_con('9') = 9 and
rt_date_con.day = 1 and
rt_date_con.month = Jan and
rt_date_con.year = 1989 and
rst_date_con.day = 1 and
rst_date_con.month = Apr and
rst_date_con.year = 2000 )
report "***PASSED TEST: /src/ch04/sc03/sb01/ss01/p001/s010101.vhd"
severity NOTE;
assert ( STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con(NUL) = 1 and
ut_chary_con(SOH) = 2 and
ut_chary_con(STX) = 3 and
ut_chary_con(ETX) = 9 and
ut_chary_con(EOT) = 8 and
ut_chary_con(ENQ) = 7 and
ct_word_con(0) = '0' and
ct_word_con(1) = '0' and
ct_word_con(2) = '0' and
ct_word_con(3) = '0' and
ct_word_con(4) = '0' and
ct_word_con(5) = '0' and
ct_word_con(6) = '0' and
ct_word_con(7) = '0' and
ct_word_con(8) = '0' and
ct_word_con(9) = '0' and
ct_word_con(10) = '0' and
ct_word_con(11) = '0' and
ct_word_con(12) = '0' and
ct_word_con(13) = '0' and
ct_word_con(14) = '0' and
ct_word_con(15) = '0' and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con('0') = 0 and
cst_digit_con('1') = 1 and
cst_digit_con('2') = 2 and
cst_digit_con('3') = 3 and
cst_digit_con('4') = 4 and
cst_digit_con('5') = 5 and
cst_digit_con('6') = 6 and
cst_digit_con('7') = 7 and
cst_digit_con('8') = 8 and
cst_digit_con('9') = 9 and
rt_date_con.day = 1 and
rt_date_con.month = Jan and
rt_date_con.year = 1989 and
rst_date_con.day = 1 and
rst_date_con.month = Apr and
rst_date_con.year = 2000 )
report "***FAILED TEST: c04s03b01x01p01n01i00031 - A constant declares a constant of the specified type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p01n01i00031arch;
|
gpl-2.0
|
b32c9ce1f369e1f70e5941db7f3ef8e2
| 0.503138 | 3.345607 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_uart.vhd
| 1 | 13,738 |
-- #################################################################################################
-- # << NEO430 - Universal Asynchronous Receiver and Transmitter >> #
-- # ********************************************************************************************* #
-- # Fixed frame config: 8-bit, no parity bit, 1 stop bit, variable BAUD rate. #
-- # Interrupt: UART_RX_available [OR] UART_TX_done #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_uart is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- com lines --
uart_txd_o : out std_ulogic;
uart_rxd_i : in std_ulogic;
-- interrupts --
uart_irq_o : out std_ulogic -- uart rx/tx interrupt
);
end neo430_uart;
architecture neo430_uart_rtl of neo430_uart is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(uart_size_c); -- low address boundary bit
-- accessible regs --
signal ctrl : std_ulogic_vector(15 downto 0);
-- control reg bits --
constant ctrl_uart_baud0_c : natural := 0; -- r/w: UART baud config bit 0
constant ctrl_uart_baud1_c : natural := 1; -- r/w: UART baud config bit 1
constant ctrl_uart_baud2_c : natural := 2; -- r/w: UART baud config bit 2
constant ctrl_uart_baud3_c : natural := 3; -- r/w: UART baud config bit 3
constant ctrl_uart_baud4_c : natural := 4; -- r/w: UART baud config bit 4
constant ctrl_uart_baud5_c : natural := 5; -- r/w: UART baud config bit 5
constant ctrl_uart_baud6_c : natural := 6; -- r/w: UART baud config bit 6
constant ctrl_uart_baud7_c : natural := 7; -- r/w: UART baud config bit 7
constant ctrl_uart_prsc0_c : natural := 8; -- r/w: UART baud prsc bit 0
constant ctrl_uart_prsc1_c : natural := 9; -- r/w: UART baud prsc bit 1
constant ctrl_uart_prsc2_c : natural := 10; -- r/w: UART baud prsc bit 2
constant ctrl_uart_rxovr_c : natural := 11; -- r/-: UART RX overrun
constant ctrl_uart_en_c : natural := 12; -- r/w: UART enable
constant ctrl_uart_rx_irq_c : natural := 13; -- r/w: UART rx done interrupt enable
constant ctrl_uart_tx_irq_c : natural := 14; -- r/w: UART tx done interrupt enable
constant ctrl_uart_tx_busy_c : natural := 15; -- r/-: UART transmitter is busy
-- data register flags --
constant data_rx_avail_c : natural := 15; -- r/-: Rx data available/valid
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wr_en : std_ulogic; -- word write enable
signal rd_en : std_ulogic; -- read enable
-- clock generator --
signal uart_clk : std_ulogic;
-- uart tx unit --
signal uart_tx_busy : std_ulogic;
signal uart_tx_done : std_ulogic;
signal uart_tx_bitcnt : std_ulogic_vector(3 downto 0);
signal uart_tx_sreg : std_ulogic_vector(9 downto 0);
signal uart_tx_baud_cnt : std_ulogic_vector(7 downto 0);
-- uart rx unit --
signal uart_rx_sync : std_ulogic_vector(4 downto 0);
signal uart_rx_avail : std_ulogic_vector(1 downto 0);
signal uart_rx_busy : std_ulogic;
signal uart_rx_busy_ff : std_ulogic;
signal uart_rx_bitcnt : std_ulogic_vector(3 downto 0);
signal uart_rx_sreg : std_ulogic_vector(8 downto 0);
signal uart_rx_reg : std_ulogic_vector(7 downto 0);
signal uart_rx_baud_cnt : std_ulogic_vector(7 downto 0);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = uart_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= uart_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wr_en <= acc_en and wren_i;
rd_en <= acc_en and rden_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wr_en = '1') then
if (addr = uart_ctrl_addr_c) then
ctrl <= data_i;
end if;
end if;
end if;
end process wr_access;
-- Clock Selection ----------------------------------------------------------
-- -----------------------------------------------------------------------------
-- clock enable --
clkgen_en_o <= ctrl(ctrl_uart_en_c);
-- uart clock select --
uart_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c))));
-- UART transmitter ---------------------------------------------------------
-- -----------------------------------------------------------------------------
uart_tx_unit: process(clk_i)
begin
if rising_edge(clk_i) then
uart_tx_done <= '0';
if (uart_tx_busy = '0') or (ctrl(ctrl_uart_en_c) = '0') then -- idle or disabled
uart_tx_busy <= '0';
uart_tx_baud_cnt <= ctrl(ctrl_uart_baud7_c downto ctrl_uart_baud0_c);
uart_tx_bitcnt <= "1010"; -- 10 bit
if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_rtx_addr_c) then
uart_tx_sreg <= '1' & data_i(7 downto 0) & '0'; -- stopbit & data & startbit
uart_tx_busy <= '1';
end if;
elsif (uart_clk = '1') then
if (uart_tx_baud_cnt = x"00") then
uart_tx_baud_cnt <= ctrl(ctrl_uart_baud7_c downto ctrl_uart_baud0_c);
uart_tx_bitcnt <= std_ulogic_vector(unsigned(uart_tx_bitcnt) - 1);
uart_tx_sreg <= '1' & uart_tx_sreg(9 downto 1);
if (uart_tx_bitcnt = "0000") then
uart_tx_busy <= '0'; -- done
uart_tx_done <= '1';
end if;
else
uart_tx_baud_cnt <= std_ulogic_vector(unsigned(uart_tx_baud_cnt) - 1);
end if;
end if;
-- transmitter output --
uart_txd_o <= uart_tx_sreg(0);
end if;
end process uart_tx_unit;
-- UART receiver ------------------------------------------------------------
-- -----------------------------------------------------------------------------
uart_rx_unit: process(clk_i)
begin
if rising_edge(clk_i) then
-- synchronizer --
uart_rx_sync <= uart_rxd_i & uart_rx_sync(4 downto 1);
-- arbiter --
if (uart_rx_busy = '0') or (ctrl(ctrl_uart_en_c) = '0') then -- idle or disabled
uart_rx_busy <= '0';
uart_rx_baud_cnt <= '0' & ctrl(ctrl_uart_baud7_c downto ctrl_uart_baud1_c); -- half baud rate to sample in middle of bit
uart_rx_bitcnt <= "1001"; -- 9 bit (startbit + 8 data bits, ignore stop bit/s)
if (ctrl(ctrl_uart_en_c) = '0') then
uart_rx_reg <= (others => '0'); -- to ensure defined state when reading
elsif (uart_rx_sync(2 downto 0) = "001") then -- start bit? (falling edge)
uart_rx_busy <= '1';
end if;
elsif (uart_clk = '1') then
if (uart_rx_baud_cnt = x"00") then
uart_rx_baud_cnt <= ctrl(ctrl_uart_baud7_c downto ctrl_uart_baud0_c);
uart_rx_bitcnt <= std_ulogic_vector(unsigned(uart_rx_bitcnt) - 1);
uart_rx_sreg <= uart_rx_sync(0) & uart_rx_sreg(8 downto 1);
if (uart_rx_bitcnt = "0000") then
uart_rx_busy <= '0'; -- done
uart_rx_reg <= uart_rx_sreg(8 downto 1);
end if;
else
uart_rx_baud_cnt <= std_ulogic_vector(unsigned(uart_rx_baud_cnt) - 1);
end if;
end if;
-- RX available flag --
uart_rx_busy_ff <= uart_rx_busy;
if (ctrl(ctrl_uart_en_c) = '0') or (((uart_rx_avail(0) = '1') or (uart_rx_avail(1) = '1')) and (rd_en = '1') and (addr = uart_rtx_addr_c)) then
uart_rx_avail <= "00";
elsif (uart_rx_busy_ff = '1') and (uart_rx_busy = '0') then
uart_rx_avail <= uart_rx_avail(0) & '1';
end if;
end if;
end process uart_rx_unit;
-- Interrupt ----------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- UART Rx data available [OR] UART Tx complete
uart_irq_o <= (uart_rx_busy_ff and (not uart_rx_busy) and ctrl(ctrl_uart_rx_irq_c)) or (uart_tx_done and ctrl(ctrl_uart_tx_irq_c));
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rd_en = '1') then
if (addr = uart_ctrl_addr_c) then
data_o(ctrl_uart_baud0_c) <= ctrl(ctrl_uart_baud0_c);
data_o(ctrl_uart_baud1_c) <= ctrl(ctrl_uart_baud1_c);
data_o(ctrl_uart_baud2_c) <= ctrl(ctrl_uart_baud2_c);
data_o(ctrl_uart_baud3_c) <= ctrl(ctrl_uart_baud3_c);
data_o(ctrl_uart_baud4_c) <= ctrl(ctrl_uart_baud4_c);
data_o(ctrl_uart_baud5_c) <= ctrl(ctrl_uart_baud5_c);
data_o(ctrl_uart_baud6_c) <= ctrl(ctrl_uart_baud6_c);
data_o(ctrl_uart_baud7_c) <= ctrl(ctrl_uart_baud7_c);
data_o(ctrl_uart_prsc0_c) <= ctrl(ctrl_uart_prsc0_c);
data_o(ctrl_uart_prsc1_c) <= ctrl(ctrl_uart_prsc1_c);
data_o(ctrl_uart_prsc2_c) <= ctrl(ctrl_uart_prsc2_c);
data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c);
data_o(ctrl_uart_rx_irq_c) <= ctrl(ctrl_uart_rx_irq_c);
data_o(ctrl_uart_tx_irq_c) <= ctrl(ctrl_uart_tx_irq_c);
data_o(ctrl_uart_rxovr_c) <= uart_rx_avail(0) and uart_rx_avail(1);
data_o(ctrl_uart_tx_busy_c) <= uart_tx_busy;
else -- uart_rtx_addr_c
data_o(data_rx_avail_c) <= uart_rx_avail(0);
data_o(07 downto 0) <= uart_rx_reg;
end if;
end if;
end if;
end process rd_access;
end neo430_uart_rtl;
|
bsd-3-clause
|
d99a41de798b3b92aaf0bc2da7147951
| 0.490319 | 3.786659 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_02.vhd
| 4 | 2,125 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity control_processor is
generic ( Tpd : delay_length := 3 ns );
end entity control_processor;
-- end not in book
architecture rtl of control_processor is
type func_code is (add, subtract);
signal op1, op2, dest : integer;
signal Z_flag : boolean;
signal func : func_code;
-- . . .
begin
alu : process is
procedure do_arith_op is
variable result : integer;
begin
case func is
when add =>
result := op1 + op2;
when subtract =>
result := op1 - op2;
end case;
dest <= result after Tpd;
Z_flag <= result = 0 after Tpd;
end procedure do_arith_op;
begin
-- . . .
do_arith_op;
-- . . .
-- not in book
wait on op1, op2, func;
-- end not in book
end process alu;
-- . . .
-- not in book
stimulus : process is
begin
op1 <= 0; op2 <= 0; wait for 10 ns;
op1 <= 10; op2 <= 3; wait for 10 ns;
func <= subtract; wait for 10 ns;
op2 <= 10; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture rtl;
|
gpl-2.0
|
eaa38818b28de2a3cc5703206f4469bc
| 0.592471 | 3.774423 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd
| 4 | 2,157 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_10 is
end entity inline_10;
----------------------------------------------------------------
library ieee; use ieee.std_logic_1164.std_ulogic;
architecture test of inline_10 is
-- code from book:
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
--
subtype std_ulogic_word is std_ulogic_vector(0 to 31);
--
signal csr_offset : std_ulogic_vector(2 downto 1);
-- end of code from book
begin
process_2_b : process is
-- code from book:
type string is array (positive range <>) of character;
--
constant LCD_display_len : positive := 20;
subtype LCD_display_string is string(1 to LCD_display_len);
variable LCD_display : LCD_display_string := (others => ' ');
--
type bit_vector is array (natural range <>) of bit;
--
subtype byte is bit_vector(7 downto 0);
--
variable channel_busy_register : bit_vector(1 to 4);
--
constant ready_message : string := "Ready ";
--
variable current_test : std_ulogic_vector(0 to 13) := "ZZZZZZZZZZ----";
--
constant all_ones : std_ulogic_vector(15 downto 0) := X"FFFF";
-- end of code from book
begin
-- code from book:
channel_busy_register := b"0000";
-- end of code from book
wait;
end process process_2_b;
end architecture test;
|
gpl-2.0
|
4fbd8e9bc1b4335bceb83c7b51fa8bbb
| 0.644877 | 3.994444 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_131.vhd
| 1 | 4,619 |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_131 is
generic (
NUM_BITS : positive := 131 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_131;
-----------------------------------------------------------
architecture behave of serial_multiplier_131 is
-----------------------------------------------------------
-- m = 131 f (x) = x^131 + x^8 + x^3 + x^2 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001101";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10000010"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
if counter = "00000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
Done <= '1';
else
bx_int <= bx_shift;
end if;
when END_STATE =>
CurrentState <= END_STATE;
Done <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
7cdde62434ed751d0fdb50c79cc3c5dc
| 0.478026 | 4.229853 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc531.vhd
| 4 | 3,585 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc531.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00531ent IS
END c03s03b00x00p03n04i00531ent;
ARCHITECTURE c03s03b00x00p03n04i00531arch OF c03s03b00x00p03n04i00531ent IS
BEGIN
TESTING : PROCESS
type bool_ptr is access boolean;
variable v_bool_ptr1: bool_ptr := new boolean'(true);
variable v_bool_ptr2: bool_ptr;
variable v_bool_ptr3: bool_ptr := v_bool_ptr1;
variable v_bool_ptr4: bool_ptr := new boolean'(false);
variable v_bool_ptr5: bool_ptr := v_bool_ptr4;
variable OKtest : integer := 0;
BEGIN
assert v_bool_ptr1.all = true;
if (v_bool_ptr1.all = true) then
OKtest := Oktest + 1;
end if;
assert v_bool_ptr2 = null;
if (v_bool_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_bool_ptr3.all = true;
if (v_bool_ptr3.all = true) then
OKtest := Oktest + 1;
end if;
assert v_bool_ptr4.all = false;
if (v_bool_ptr4.all = false) then
OKtest := Oktest + 1;
end if;
assert v_bool_ptr5.all = false;
if (v_bool_ptr5.all = false) then
OKtest := Oktest + 1;
end if;
v_bool_ptr2 := new boolean'(true);
assert v_bool_ptr2.all = true;
if (v_bool_ptr2.all = true) then
OKtest := Oktest + 1;
end if;
assert (v_bool_ptr1.all and v_bool_ptr5.all) = false;
if ((v_bool_ptr1.all and v_bool_ptr5.all) = false) then
OKtest := Oktest + 1;
end if;
assert (v_bool_ptr1.all and v_bool_ptr2.all) = true;
if ((v_bool_ptr1.all and v_bool_ptr2.all) = true) then
OKtest := Oktest + 1;
end if;
assert (v_bool_ptr3.all or v_bool_ptr5.all) = true;
if ((v_bool_ptr3.all or v_bool_ptr5.all) = true) then
OKtest := Oktest + 1;
end if;
assert (v_bool_ptr3.all > v_bool_ptr5.all) = true;
if ((v_bool_ptr3.all > v_bool_ptr5.all) = true) then
OKtest := Oktest + 1;
end if;
assert (not v_bool_ptr3.all) = false;
if ((not v_bool_ptr3.all) = false) then
OKtest := Oktest + 1;
end if;
deallocate(v_bool_ptr1);
deallocate(v_bool_ptr2);
deallocate(v_bool_ptr4);
assert NOT(OKtest = 11)
report "***PASSED TEST: c03s03b00x00p03n04i00531"
severity NOTE;
assert (OKtest = 11)
report "***FAILED TEST: c03s03b00x00p03n04i00531 - Boolean type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00531arch;
|
gpl-2.0
|
bd101682aed57a78abe6c990ce6302c4
| 0.624547 | 3.198037 | false | true | false | false |
nczempin/NICNAC16
|
ipcore_dir/ROM01/simulation/bmg_stim_gen.vhd
| 1 | 12,635 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
DATA_IN : IN STD_LOGIC_VECTOR (15 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0):= hex_to_std_logic_vector("0",16);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(15 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"ROM01.mif",
DEFAULT_DATA,
16,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
ENA <= DO_READ ;
END ARCHITECTURE;
|
mit
|
421d8ae846669fa6d4a367da01b662e4
| 0.546577 | 3.6826 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc559.vhd
| 4 | 2,890 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc559.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:30 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:27 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:03 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00559ent IS
END c03s04b01x00p01n01i00559ent;
ARCHITECTURE c03s04b01x00p01n01i00559arch OF c03s04b01x00p01n01i00559ent IS
type natural_vector is array (natural range <>) of natural;
type natural_vector_file is file of natural_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : natural_vector_file open read_mode is "iofile.25";
variable v : natural_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= (1,2,3,4)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00559"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00559 - File reading operation (natural_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00559arch;
|
gpl-2.0
|
3ec722e05d9d30c4c8d64aef45580559
| 0.564706 | 3.931973 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3068.vhd
| 4 | 4,087 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3068.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03068pkg is
type severity_level_cons_vector is array (15 downto 0) of severity_level;
constant C19 : severity_level_cons_vector := (others => note);
end c12s06b02x00p06n01i03068pkg;
use work.c12s06b02x00p06n01i03068pkg.all;
ENTITY c12s06b02x00p06n01i03068ent_a IS
PORT
(
F1: OUT integer ;
F3: IN severity_level_cons_vector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03068ent_a;
ARCHITECTURE c12s06b02x00p06n01i03068arch_a OF c12s06b02x00p06n01i03068ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03068arch_a;
use work.c12s06b02x00p06n01i03068pkg.all;
ENTITY c12s06b02x00p06n01i03068ent IS
END c12s06b02x00p06n01i03068ent;
ARCHITECTURE c12s06b02x00p06n01i03068arch OF c12s06b02x00p06n01i03068ent IS
function scalar_complex(s : integer) return severity_level_cons_vector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN severity_level_cons_vector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03068ent_a(c12s06b02x00p06n01i03068arch_a);
signal S1 : severity_level_cons_vector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03068"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03068 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03068arch;
|
gpl-2.0
|
24a76300714281d3bd1be5143298a0c2
| 0.66528 | 3.311994 | false | true | false | false |
stnolting/neo430
|
rtl/core/neo430_imem.vhd
| 1 | 9,171 |
-- #################################################################################################
-- # << NEO430 - Instruction memory ("IMEM") >> #
-- # ********************************************************************************************* #
-- # This memory includes the in-place executable image of the application. See the #
-- # processor's documentary to get more information. #
-- # Note: IMEM is split up into two 8-bit memories - some EDA tools have problems to synthesize #
-- # a pre-initialized 16-bit memory with byte-enable signals. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
use neo430.neo430_application_image.all; -- this file is generated by the image generator
entity neo430_imem is
generic (
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory?
BOOTLD_USE : boolean := true -- implement and use bootloader?
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic_vector(01 downto 0); -- write enable
upen_i : in std_ulogic; -- update enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_imem;
architecture neo430_imem_rtl of neo430_imem is
-- ROM types --
type imem_file8_t is array (0 to IMEM_SIZE/2-1) of std_ulogic_vector(07 downto 0);
-- init function and split 1x16-bit memory into 2x8-bit memories --
impure function init_imem(hilo : std_ulogic; init : application_init_image_t) return imem_file8_t is
variable mem_v : imem_file8_t;
begin
for i in 0 to IMEM_SIZE/2-1 loop
if (hilo = '0') then -- low byte
mem_v(i) := init(i)(07 downto 00);
else -- high byte
mem_v(i) := init(i)(15 downto 08);
end if;
end loop; -- i
return mem_v;
end function init_imem;
-- local signals --
signal acc_en : std_ulogic;
signal rdata : std_ulogic_vector(15 downto 0);
signal rden : std_ulogic;
signal addr : integer;
-- internal "RAM" type - implemented if bootloader is used and IMEM is RAM and initialized with app code --
signal imem_file_init_ram_l : imem_file8_t := init_imem('0', application_init_image);
signal imem_file_init_ram_h : imem_file8_t := init_imem('1', application_init_image);
-- internal "ROM" type - implemented if bootloader is NOT used; always initialize with app code --
constant imem_file_rom_l : imem_file8_t := init_imem('0', application_init_image);
constant imem_file_rom_h : imem_file8_t := init_imem('1', application_init_image);
-- internal "RAM" type - implemented if bootloader is used and IMEM is RAM --
signal imem_file_ram_l : imem_file8_t;
signal imem_file_ram_h : imem_file8_t;
-- RAM attribute to inhibit bypass-logic - Intel only! --
attribute ramstyle : string;
attribute ramstyle of imem_file_init_ram_l : signal is "no_rw_check";
attribute ramstyle of imem_file_init_ram_h : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_l : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_h : signal is "no_rw_check";
-- RAM attribute to inhibit bypass-logic - Lattice only! --
attribute syn_ramstyle : string;
attribute syn_ramstyle of imem_file_init_ram_l : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_init_ram_h : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_ram_l : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_ram_h : signal is "no_rw_check";
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i >= imem_base_c) and (addr_i < std_ulogic_vector(unsigned(imem_base_c) + IMEM_SIZE)) else '0';
addr <= to_integer(unsigned(addr_i(index_size_f(IMEM_SIZE/2) downto 1))); -- word aligned
-- Memory Access ------------------------------------------------------------
-- -----------------------------------------------------------------------------
imem_file_access: process(clk_i)
begin
-- check max size --
if (IMEM_SIZE > imem_max_size_c) then
assert false report "I-mem size out of range! Max 48kB!" severity error;
end if;
-- actual memory access --
if rising_edge(clk_i) then
rden <= rden_i and acc_en;
if (acc_en = '1') then -- reduce switching activity when not accessed
if (IMEM_AS_ROM = true) then -- implement IMEM as true ROM
rdata(07 downto 0) <= imem_file_rom_l(addr);
rdata(15 downto 8) <= imem_file_rom_h(addr);
elsif (BOOTLD_USE = true) then -- implement IMEM as non-initialized RAM
if (wren_i(0) = '1') and (upen_i = '1') then
imem_file_ram_l(addr) <= data_i(07 downto 0);
end if;
rdata(07 downto 0) <= imem_file_ram_l(addr);
if (wren_i(1) = '1') and (upen_i = '1') then
imem_file_ram_h(addr) <= data_i(15 downto 8);
end if;
rdata(15 downto 8) <= imem_file_ram_h(addr);
else -- implement IMEM as PRE-INITIALIZED RAM
if (wren_i(0) = '1') and (upen_i = '1') then
imem_file_init_ram_l(addr) <= data_i(07 downto 0);
end if;
rdata(07 downto 0) <= imem_file_init_ram_l(addr);
if (wren_i(1) = '1') and (upen_i = '1') then
imem_file_init_ram_h(addr) <= data_i(15 downto 8);
end if;
rdata(15 downto 8) <= imem_file_init_ram_h(addr);
end if;
end if;
end if;
end process imem_file_access;
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
end neo430_imem_rtl;
|
bsd-3-clause
|
b9ac679ebc849ae91332a562825f6202
| 0.514666 | 4.305634 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1729.vhd
| 4 | 1,808 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1729.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s03b00x00p02n01i01729ent IS
END c09s03b00x00p02n01i01729ent;
ARCHITECTURE c09s03b00x00p02n01i01729arch OF c09s03b00x00p02n01i01729ent IS
procedure check (x: in integer; y: in boolean) is
begin
assert NOT( x=3 and y=true )
report "***PASSED TEST: c09s03b00x00p02n01i01729"
severity NOTE;
assert ( x=3 and y=true )
report "***FAILED TEST: c09s03b00x00p02n01i01729 - A label can be used before a procedure call statement."
severity ERROR;
end;
signal p: integer := 3;
signal q: boolean := true;
BEGIN
L1 : check (p,q); -- No_failure_here
END c09s03b00x00p02n01i01729arch;
|
gpl-2.0
|
a5e1ff50c6358953711d351fdd5ca831
| 0.666482 | 3.623246 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_05.vhd
| 4 | 2,243 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_05.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_05 is
end entity ch_07_05;
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture test of ch_07_05 is
begin
process_07_5_a : process is
-- code from book:
procedure increment ( a : inout integer; n : in integer := 1 ) is -- . . .
-- not in book
begin
a := a + n;
end procedure increment;
-- end not in book;
procedure increment ( a : inout bit_vector; n : in bit_vector := B"1" ) is -- . . .
-- not in book
begin
a := a + n;
end procedure increment;
-- end not in book;
procedure increment ( a : inout bit_vector; n : in integer := 1 ) is -- . . .
-- not in book
begin
a := a + integer_to_bv(n, a'length);
end procedure increment;
-- end not in book;
variable count_int : integer := 2;
variable count_bv : bit_vector (15 downto 0) := X"0002";
-- end of code from book
begin
-- code from book:
increment ( count_int, 2 );
increment ( count_int );
increment ( count_bv, X"0002");
increment ( count_bv, 1 );
-- increment ( count_bv );
-- end of code from book
wait;
end process process_07_5_a;
end architecture test;
|
gpl-2.0
|
000bda40220b278d8e388667a32f8351
| 0.593402 | 3.834188 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/basic_cell.vhd
| 1 | 1,087 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity basic_cell is
port(
ai : in std_logic;
bi : in std_logic;
c_i: in std_logic;
clk: in std_logic;
rst: in std_logic;
ci : out std_logic
);
end basic_cell;
-----------------------------------------------------------
architecture behave of basic_cell is
-----------------------------------------------------------
signal and_gate : std_logic;
signal xor_gate : std_logic;
signal fflop : std_logic;
-----------------------------------------------------------
begin
-----------------------------------------------------------
and_gate <= ai and bi;
xor_gate <= and_gate xor c_i;
ci <= fflop;
------------------------------------------------------------
PROCESS_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Rst = '1' then
fflop <= '0';
else
fflop <= xor_gate;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
2908218e5b943f0ab309193f84b72622
| 0.399264 | 3.722603 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2964.vhd
| 4 | 5,109 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2964.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b00x00p03n01i02964ent IS
END c02s03b00x00p03n01i02964ent;
ARCHITECTURE c02s03b00x00p03n01i02964arch OF c02s03b00x00p03n01i02964ent IS
function f1a(constant c1 : in integer) return integer is
begin
return 12;
end;
function f1a(constant c1,c2 : in integer) return integer is
begin
return 25;
end;
function f2b(constant c1 : in integer) return integer is
begin
return 22;
end;
function f2b(constant c1 : in real) return integer is
begin
return 28;
end;
function f3c(constant c0:integer; constant c1:real) return integer is
begin
return 32;
end;
function f3c(constant c1:real; constant c0:integer) return integer is
begin
return 38;
end;
function f4d(constant c1 : in integer) return integer is
begin
return 42;
end;
function f4d(constant c1 : in integer) return real is
begin
return 48.0;
end;
function f5e(constant c1 : in integer) return integer is
begin
return 52;
end;
procedure f5e(constant c1 : in integer) is
begin
return;
end;
function f6f(constant c0 : in real;constant c1 : in integer) return integer is
begin
return 62;
end;
function f6f(constant c2 : in integer;constant c3 : in real) return integer is
begin
return 68;
end;
BEGIN
TESTING: PROCESS
variable i1 : integer;
variable r1 : real;
variable k : integer := 0;
BEGIN
i1 := 8;
if (i1 /= 8) then
k := 1;
end if;
assert (i1=8)
report "Error in initial conditions detected"
severity failure;
i1:= f1a(4);
if (i1 /= 12) then
k := 1;
end if;
assert (i1=12)
report "Error differentiating overloaded subprog by number of formals"
severity failure;
i1:=f1a(16,23);
if (i1 /= 25) then
k := 1;
end if;
assert (i1=25)
report "Error differentiating overloaded subprog by number of formals"
severity failure;
i1:= f2b(4);
if (i1 /= 22) then
k := 1;
end if;
assert (i1=22)
report "Error differentiating overloaded subprog by type of formals"
severity failure;
i1:=f2b(4.0);
if (i1 /= 28) then
k := 1;
end if;
assert (i1=28)
report "Error differentiating overloaded subprog by type of formals"
severity failure;
i1:= f3c(4,4.0);
if (i1 /= 32) then
k := 1;
end if;
assert (i1=32)
report "Error differentiating overloaded subprog by order of formals"
severity failure;
i1:= f3c(4.0,4);
if (i1 /= 38) then
k := 1;
end if;
assert (i1=38)
report "Error differentiating overloaded subprog by order of formals"
severity failure;
i1:= f4d(4);
if (i1 /= 42) then
k := 1;
end if;
assert (i1=42)
report "Error differentiating overloaded subprog by return type"
severity failure;
r1:= f4d(4);
if (r1 /= 48.0) then
k := 1;
end if;
assert (r1=48.0)
report "Error differentiating overloaded subprog by return type"
severity failure;
i1:= f5e(4);
if (i1 /= 52) then
k := 1;
end if;
assert (i1=52)
report "Error differentiating overloaded subprog by having a return"
severity failure;
i1:= f6f(c1 => 4, c0 => 4.4);
if (i1 /= 62) then
k := 1;
end if;
assert (i1=62)
report "Error differentiating overloaded subprog by name of formals"
severity failure;
i1:= f6f(c3 => 4.4, c2 => 4);
if (i1 /= 68) then
k := 1;
end if;
assert (i1=68)
report "Error differentiating overloaded subprog by name of formals"
severity failure;
wait for 5 ns;
assert NOT( k=0 )
report "***PASSED TEST: c02s03b00x00p03n01i02964"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c02s03b00x00p03n01i02964 - Overload subprogram call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p03n01i02964arch;
|
gpl-2.0
|
609eb8cd284ffb8841800bb3d1aec184
| 0.629477 | 3.504115 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc149.vhd
| 4 | 3,940 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc149.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p14n01i00149ent IS
PORT ( ii: INOUT integer);
PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
BEGIN
IF add THEN
i4 := (i1+i2+i3);
ELSE
i4 := (i1-i2)-i3;
END IF;
END;
END c04s03b02x02p14n01i00149ent;
ARCHITECTURE c04s03b02x02p14n01i00149arch OF c04s03b02x02p14n01i00149ent IS
BEGIN
TESTING: PROCESS
VARIABLE a1 : INTEGER := 57;
VARIABLE a11: INTEGER := 57;
VARIABLE a12: INTEGER := 57;
VARIABLE a13: INTEGER := 57;
VARIABLE a2 : INTEGER := 68;
VARIABLE a3 : INTEGER := 77;
VARIABLE b1 : BIT := '1';
VARIABLE b2 : BIT := '0';
FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
BEGIN
IF (inp > 0) THEN
RETURN (TRUE);
ELSE
RETURN (FALSE);
END IF;
END;
FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
BEGIN
IF (inp = '1') THEN
RETURN (22);
ELSE
RETURN (23);
END IF;
END;
BEGIN
WAIT FOR 1 ns;
addup(i2=>conv1(b1),add=>convb(INTEGER'HIGH),i1=>conv1(b2),i3=>a1,i4=>a1);
WAIT FOR 1 ns;
IF (a1 = 102) THEN
ASSERT false REPORT "PASS: Function call uses function to convert type of actual" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(add=>convb(-33),i3=>2,i1=>a3,i2=>a2,i4=>a11);
WAIT FOR 1 ns;
IF (a11 = 7) THEN
ASSERT false REPORT "PASS: Function call uses function to convert actual to false" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(add=>TRUE,i3=>conv1('1'),i2=>conv1('1'),i1=>conv1('0'),i4=>a12);
WAIT FOR 1 ns;
IF (a12 = 67) THEN
ASSERT false REPORT "PASS: Function call uses same actual twice" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(15,5,5,convb(-1),a13);
WAIT FOR 1 ns;
IF (a13 = 5) THEN
ASSERT false REPORT "PASS: No named association used" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
assert NOT( a1 = 102 and
a11= 7 and
a12= 67 and
a13= 5 )
report "***PASSED TEST: c04s03b02x02p14n01i00149"
severity NOTE;
assert ( a1 = 102 and
a11= 7 and
a12= 67 and
a13= 5 )
report "***FAILED TEST: c04s03b02x02p14n01i00149 - Function call uses function to convert type of actual."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p14n01i00149arch;
|
gpl-2.0
|
191cf01c3a244cf68f18eb289a5a1ad3
| 0.608883 | 3.555957 | false | false | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/multiplier.vhd
| 1 | 3,676 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplier is
port (clk : in std_logic;
reset : in std_logic;
addrA : in std_logic_vector(2 downto 0);
addrB : in std_logic_vector(2 downto 0);
showAB: in std_logic;
start: in std_logic;
result: inout std_logic_vector(31 downto 0);
outAB : out std_logic_vector(31 downto 0);
ready : out std_logic_vector(7 downto 0)
);
end multiplier;
architecture synt of multiplier is
signal romAOut : std_logic_vector (31 downto 0);
signal romBOut : std_logic_vector (31 downto 0);
component graph_driver
port (in_graph : in std_logic_vector(31 downto 0);
out_graph : out std_logic_vector(31 downto 0)
);
end component;
signal outAB_graph_s: std_logic_vector(31 downto 0);
signal result_graph_s: std_logic_vector(31 downto 0);
component romMemOpA
port(
addr : in std_logic_vector (2 downto 0);
dataOut : out std_logic_vector (31 downto 0)
);
end component;
component romMemOpB
port(
addr : in std_logic_vector (2 downto 0);
dataOut : out std_logic_vector (31 downto 0)
);
end component;
component device
port (a,b: in std_logic_vector(31 downto 0);
clk,en,rst: in std_logic;
c: out std_logic_vector(31 downto 0);
done: out std_logic
);
end component;
signal en_mul:std_logic;
signal rst_mul:std_logic;
signal result_graph_ss: std_logic_vector(31 downto 0);
signal res: std_logic_vector(31 downto 0);
signal done_mult: std_logic;
signal graph: std_logic_vector(31 downto 0);
type state is (initial, multiply, view_result);
signal CurrentState, NextState : state;
begin
process(CurrentState) begin
NextState<=initial;
result_graph_s<=(others=>'0');
case CurrentState is
when initial =>
en_mul<='0';
rst_mul<='0';
-----result<="11110000010000000010010011110001";
if(start='0') then
NextState<=multiply;
else
NextState<=initial;
end if;
when multiply =>
en_mul<='1';
rst_mul<='1';
if(done_mult='1') then
NextState<=view_result;
else
NextState<=multiply;
end if;
when view_result =>
--en_mul<='1';
--if(reset='0') then
--NextState<=initial;
--else
--NextState<=view_result;
--end if;
NextState<=multiply;
end case;
end process;
transitions:process (clk, reset) begin
if reset='0'then
CurrentState <= initial;
elsif (clk'event and clk='1')then
CurrentState <= NextState;
end if;
end process;
uOpA: romMemOpA
port map (
addr => addrA,
dataOut => romAOut
);
uOpB: romMemOpB
port map (
addr => addrB,
dataOut => romBOut
);
uMult: device
port map (
a => romAOut,
b => romBOut,
clk=>clk ,
en=> en_mul,
rst=> rst_mul,
c => result_graph_ss,
done=>done_mult
);
outtAB_graph: graph_driver port map(in_graph=>outAB_graph_s,out_graph=>outAB);
result_graph: graph_driver port map(in_graph=>result_graph_ss,out_graph=>res);
with currentState select
result<="11110000010000000010010011110001" when initial,
res when others ;
-- When the button assoiciated to outAB is pushed romAOut is displayed
outAB_graph_s<= romAOut when showAB = '0'
else romBOut;
ready(7 downto 0) <= (others => done_mult);
end synt;
|
mit
|
7819dbf3ae761389b175418723d68d6a
| 0.59222 | 3.636004 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/cache.vhd
| 4 | 3,188 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity cache is
end entity cache;
-- end not in book
architecture behavioral of cache is
-- not in book
subtype word is bit_vector(0 to 31);
signal mem_addr : natural;
signal mem_data_in : word;
signal mem_read, mem_ack : bit := '0';
-- end not in book
begin
behavior : process is
-- not in book
constant block_size : positive := 4;
type cache_block is array (0 to block_size - 1) of word;
type store_array is array (0 to 15) of cache_block;
variable data_store : store_array;
variable entry_index : natural := 1;
variable miss_base_address : natural := 16;
-- end not in book
-- . . .
procedure read_block( start_address : natural;
entry : out cache_block ) is
variable memory_address_reg : natural;
variable memory_data_reg : word;
procedure read_memory_word is
begin
mem_addr <= memory_address_reg;
mem_read <= '1';
wait until mem_ack = '1';
memory_data_reg := mem_data_in;
mem_read <= '0';
wait until mem_ack = '0';
end procedure read_memory_word;
begin -- read_block
for offset in 0 to block_size - 1 loop
memory_address_reg := start_address + offset;
read_memory_word;
entry(offset) := memory_data_reg;
end loop;
end procedure read_block;
begin -- behavior
-- . . .
read_block( miss_base_address, data_store(entry_index) );
-- . . .
-- not in book
wait;
-- end not in book
end process behavior;
-- not in book
memory : process is
type store_array is array (0 to 31) of word;
constant store : store_array :=
( X"00000000", X"00000001", X"00000002", X"00000003",
X"00000004", X"00000005", X"00000006", X"00000007",
X"00000008", X"00000009", X"0000000a", X"0000000b",
X"0000000c", X"0000000d", X"0000000e", X"0000000f",
X"00000010", X"00000011", X"00000012", X"00000013",
X"00000014", X"00000015", X"00000016", X"00000017",
X"00000018", X"00000019", X"0000001a", X"0000001b",
X"0000001c", X"0000001d", X"0000001e", X"0000001f" );
begin
wait until mem_read = '1';
mem_data_in <= store(mem_addr);
mem_ack <= '1';
wait until mem_read = '0';
mem_ack <= '0';
end process memory;
-- end not in book
end architecture behavioral;
|
gpl-2.0
|
c48611a44f053dbef3feda64e65a53c8
| 0.630176 | 3.711292 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_163_1.vhd
| 1 | 21,133 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- Con celda y sin maquina de estados
--------------------------------------------------------
-- x^163 + x^7 + x^6 + x^3 + 1
entity serial_multiplier_163 is
generic (
NUM_BITS : positive := 163 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_163;
-----------------------------------------------------------
architecture behave of serial_multiplier_163 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
signal xor_2 : std_logic;
signal xor_3 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
--type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
--signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
-- Result of the multiplication
xor_1 <= Cx_int(2) xor Cx_int(NUM_BITS-1);
xor_2 <= Cx_int(5) xor Cx_int(NUM_BITS-1);
xor_3 <= Cx_int(6) xor Cx_int(NUM_BITS-1);
--Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
bx_int <= Bx_shift; -- Shift Bx to left one position
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
CELL_0: ENTITY basic_cell(behave)
PORT MAP(Ax(0),Bx_int(NUM_BITS-1),Cx_int(NUM_BITS-1),clk,reset,Cx_int(0));
CELL_1: ENTITY basic_cell(behave)
PORT MAP(Ax(1),Bx_int(NUM_BITS-1),Cx_int(0),clk,reset,Cx_int(1));
CELL_2: ENTITY basic_cell(behave)
PORT MAP(Ax(2),Bx_int(NUM_BITS-1),Cx_int(1),clk,reset,Cx_int(2));
CELL_3: ENTITY basic_cell(behave)
PORT MAP(Ax(3),Bx_int(NUM_BITS-1),xor_1,clk,reset,Cx_int(3));
CELL_4: ENTITY basic_cell(behave)
PORT MAP(Ax(4),Bx_int(NUM_BITS-1),Cx_int(3),clk,reset,Cx_int(4));
CELL_5: ENTITY basic_cell(behave)
PORT MAP(Ax(5),Bx_int(NUM_BITS-1),Cx_int(4),clk,reset,Cx_int(5));
CELL_6: ENTITY basic_cell(behave)
PORT MAP(Ax(6),Bx_int(NUM_BITS-1),xor_2,clk,reset,Cx_int(6));
CELL_7: ENTITY basic_cell(behave)
PORT MAP(Ax(7),Bx_int(NUM_BITS-1),xor_3,clk,reset,Cx_int(7));
CELL_8: ENTITY basic_cell(behave)
PORT MAP(Ax(8),Bx_int(NUM_BITS-1),Cx_int(7),clk,reset,Cx_int(8));
CELL_9: ENTITY basic_cell(behave)
PORT MAP(Ax(9),Bx_int(NUM_BITS-1),Cx_int(8),clk,reset,Cx_int(9));
CELL_10: ENTITY basic_cell(behave)
PORT MAP(Ax(10),Bx_int(NUM_BITS-1),Cx_int(9),clk,reset,Cx_int(10));
CELL_11: ENTITY basic_cell(behave)
PORT MAP(Ax(11),Bx_int(NUM_BITS-1),Cx_int(10),clk,reset,Cx_int(11));
CELL_12: ENTITY basic_cell(behave)
PORT MAP(Ax(12),Bx_int(NUM_BITS-1),Cx_int(11),clk,reset,Cx_int(12));
CELL_13: ENTITY basic_cell(behave)
PORT MAP(Ax(13),Bx_int(NUM_BITS-1),Cx_int(12),clk,reset,Cx_int(13));
CELL_14: ENTITY basic_cell(behave)
PORT MAP(Ax(14),Bx_int(NUM_BITS-1),Cx_int(13),clk,reset,Cx_int(14));
CELL_15: ENTITY basic_cell(behave)
PORT MAP(Ax(15),Bx_int(NUM_BITS-1),Cx_int(14),clk,reset,Cx_int(15));
CELL_16: ENTITY basic_cell(behave)
PORT MAP(Ax(16),Bx_int(NUM_BITS-1),Cx_int(15),clk,reset,Cx_int(16));
CELL_17: ENTITY basic_cell(behave)
PORT MAP(Ax(17),Bx_int(NUM_BITS-1),Cx_int(16),clk,reset,Cx_int(17));
CELL_18: ENTITY basic_cell(behave)
PORT MAP(Ax(18),Bx_int(NUM_BITS-1),Cx_int(17),clk,reset,Cx_int(18));
CELL_19: ENTITY basic_cell(behave)
PORT MAP(Ax(19),Bx_int(NUM_BITS-1),Cx_int(18),clk,reset,Cx_int(19));
CELL_20: ENTITY basic_cell(behave)
PORT MAP(Ax(20),Bx_int(NUM_BITS-1),Cx_int(19),clk,reset,Cx_int(20));
CELL_21: ENTITY basic_cell(behave)
PORT MAP(Ax(21),Bx_int(NUM_BITS-1),Cx_int(20),clk,reset,Cx_int(21));
CELL_22: ENTITY basic_cell(behave)
PORT MAP(Ax(22),Bx_int(NUM_BITS-1),Cx_int(21),clk,reset,Cx_int(22));
CELL_23: ENTITY basic_cell(behave)
PORT MAP(Ax(23),Bx_int(NUM_BITS-1),Cx_int(22),clk,reset,Cx_int(23));
CELL_24: ENTITY basic_cell(behave)
PORT MAP(Ax(24),Bx_int(NUM_BITS-1),Cx_int(23),clk,reset,Cx_int(24));
CELL_25: ENTITY basic_cell(behave)
PORT MAP(Ax(25),Bx_int(NUM_BITS-1),Cx_int(24),clk,reset,Cx_int(25));
CELL_26: ENTITY basic_cell(behave)
PORT MAP(Ax(26),Bx_int(NUM_BITS-1),Cx_int(25),clk,reset,Cx_int(26));
CELL_27: ENTITY basic_cell(behave)
PORT MAP(Ax(27),Bx_int(NUM_BITS-1),Cx_int(26),clk,reset,Cx_int(27));
CELL_28: ENTITY basic_cell(behave)
PORT MAP(Ax(28),Bx_int(NUM_BITS-1),Cx_int(27),clk,reset,Cx_int(28));
CELL_29: ENTITY basic_cell(behave)
PORT MAP(Ax(29),Bx_int(NUM_BITS-1),Cx_int(28),clk,reset,Cx_int(29));
CELL_30: ENTITY basic_cell(behave)
PORT MAP(Ax(30),Bx_int(NUM_BITS-1),Cx_int(29),clk,reset,Cx_int(30));
CELL_31: ENTITY basic_cell(behave)
PORT MAP(Ax(31),Bx_int(NUM_BITS-1),Cx_int(30),clk,reset,Cx_int(31));
CELL_32: ENTITY basic_cell(behave)
PORT MAP(Ax(32),Bx_int(NUM_BITS-1),Cx_int(31),clk,reset,Cx_int(32));
CELL_33: ENTITY basic_cell(behave)
PORT MAP(Ax(33),Bx_int(NUM_BITS-1),Cx_int(32),clk,reset,Cx_int(33));
CELL_34: ENTITY basic_cell(behave)
PORT MAP(Ax(34),Bx_int(NUM_BITS-1),Cx_int(33),clk,reset,Cx_int(34));
CELL_35: ENTITY basic_cell(behave)
PORT MAP(Ax(35),Bx_int(NUM_BITS-1),Cx_int(34),clk,reset,Cx_int(35));
CELL_36: ENTITY basic_cell(behave)
PORT MAP(Ax(36),Bx_int(NUM_BITS-1),Cx_int(35),clk,reset,Cx_int(36));
CELL_37: ENTITY basic_cell(behave)
PORT MAP(Ax(37),Bx_int(NUM_BITS-1),Cx_int(36),clk,reset,Cx_int(37));
CELL_38: ENTITY basic_cell(behave)
PORT MAP(Ax(38),Bx_int(NUM_BITS-1),Cx_int(37),clk,reset,Cx_int(38));
CELL_39: ENTITY basic_cell(behave)
PORT MAP(Ax(39),Bx_int(NUM_BITS-1),Cx_int(38),clk,reset,Cx_int(39));
CELL_40: ENTITY basic_cell(behave)
PORT MAP(Ax(40),Bx_int(NUM_BITS-1),Cx_int(39),clk,reset,Cx_int(40));
CELL_41: ENTITY basic_cell(behave)
PORT MAP(Ax(41),Bx_int(NUM_BITS-1),Cx_int(40),clk,reset,Cx_int(41));
CELL_42: ENTITY basic_cell(behave)
PORT MAP(Ax(42),Bx_int(NUM_BITS-1),Cx_int(41),clk,reset,Cx_int(42));
CELL_43: ENTITY basic_cell(behave)
PORT MAP(Ax(43),Bx_int(NUM_BITS-1),Cx_int(42),clk,reset,Cx_int(43));
CELL_44: ENTITY basic_cell(behave)
PORT MAP(Ax(44),Bx_int(NUM_BITS-1),Cx_int(43),clk,reset,Cx_int(44));
CELL_45: ENTITY basic_cell(behave)
PORT MAP(Ax(45),Bx_int(NUM_BITS-1),Cx_int(44),clk,reset,Cx_int(45));
CELL_46: ENTITY basic_cell(behave)
PORT MAP(Ax(46),Bx_int(NUM_BITS-1),Cx_int(45),clk,reset,Cx_int(46));
CELL_47: ENTITY basic_cell(behave)
PORT MAP(Ax(47),Bx_int(NUM_BITS-1),Cx_int(46),clk,reset,Cx_int(47));
CELL_48: ENTITY basic_cell(behave)
PORT MAP(Ax(48),Bx_int(NUM_BITS-1),Cx_int(47),clk,reset,Cx_int(48));
CELL_49: ENTITY basic_cell(behave)
PORT MAP(Ax(49),Bx_int(NUM_BITS-1),Cx_int(48),clk,reset,Cx_int(49));
CELL_50: ENTITY basic_cell(behave)
PORT MAP(Ax(50),Bx_int(NUM_BITS-1),Cx_int(49),clk,reset,Cx_int(50));
CELL_51: ENTITY basic_cell(behave)
PORT MAP(Ax(51),Bx_int(NUM_BITS-1),Cx_int(50),clk,reset,Cx_int(51));
CELL_52: ENTITY basic_cell(behave)
PORT MAP(Ax(52),Bx_int(NUM_BITS-1),Cx_int(51),clk,reset,Cx_int(52));
CELL_53: ENTITY basic_cell(behave)
PORT MAP(Ax(53),Bx_int(NUM_BITS-1),Cx_int(52),clk,reset,Cx_int(53));
CELL_54: ENTITY basic_cell(behave)
PORT MAP(Ax(54),Bx_int(NUM_BITS-1),Cx_int(53),clk,reset,Cx_int(54));
CELL_55: ENTITY basic_cell(behave)
PORT MAP(Ax(55),Bx_int(NUM_BITS-1),Cx_int(54),clk,reset,Cx_int(55));
CELL_56: ENTITY basic_cell(behave)
PORT MAP(Ax(56),Bx_int(NUM_BITS-1),Cx_int(55),clk,reset,Cx_int(56));
CELL_57: ENTITY basic_cell(behave)
PORT MAP(Ax(57),Bx_int(NUM_BITS-1),Cx_int(56),clk,reset,Cx_int(57));
CELL_58: ENTITY basic_cell(behave)
PORT MAP(Ax(58),Bx_int(NUM_BITS-1),Cx_int(57),clk,reset,Cx_int(58));
CELL_59: ENTITY basic_cell(behave)
PORT MAP(Ax(59),Bx_int(NUM_BITS-1),Cx_int(58),clk,reset,Cx_int(59));
CELL_60: ENTITY basic_cell(behave)
PORT MAP(Ax(60),Bx_int(NUM_BITS-1),Cx_int(59),clk,reset,Cx_int(60));
CELL_61: ENTITY basic_cell(behave)
PORT MAP(Ax(61),Bx_int(NUM_BITS-1),Cx_int(60),clk,reset,Cx_int(61));
CELL_62: ENTITY basic_cell(behave)
PORT MAP(Ax(62),Bx_int(NUM_BITS-1),Cx_int(61),clk,reset,Cx_int(62));
CELL_63: ENTITY basic_cell(behave)
PORT MAP(Ax(63),Bx_int(NUM_BITS-1),Cx_int(62),clk,reset,Cx_int(63));
CELL_64: ENTITY basic_cell(behave)
PORT MAP(Ax(64),Bx_int(NUM_BITS-1),Cx_int(63),clk,reset,Cx_int(64));
CELL_65: ENTITY basic_cell(behave)
PORT MAP(Ax(65),Bx_int(NUM_BITS-1),Cx_int(64),clk,reset,Cx_int(65));
CELL_66: ENTITY basic_cell(behave)
PORT MAP(Ax(66),Bx_int(NUM_BITS-1),Cx_int(65),clk,reset,Cx_int(66));
CELL_67: ENTITY basic_cell(behave)
PORT MAP(Ax(67),Bx_int(NUM_BITS-1),Cx_int(66),clk,reset,Cx_int(67));
CELL_68: ENTITY basic_cell(behave)
PORT MAP(Ax(68),Bx_int(NUM_BITS-1),Cx_int(67),clk,reset,Cx_int(68));
CELL_69: ENTITY basic_cell(behave)
PORT MAP(Ax(69),Bx_int(NUM_BITS-1),Cx_int(68),clk,reset,Cx_int(69));
CELL_70: ENTITY basic_cell(behave)
PORT MAP(Ax(70),Bx_int(NUM_BITS-1),Cx_int(69),clk,reset,Cx_int(70));
CELL_71: ENTITY basic_cell(behave)
PORT MAP(Ax(71),Bx_int(NUM_BITS-1),Cx_int(70),clk,reset,Cx_int(71));
CELL_72: ENTITY basic_cell(behave)
PORT MAP(Ax(72),Bx_int(NUM_BITS-1),Cx_int(71),clk,reset,Cx_int(72));
CELL_73: ENTITY basic_cell(behave)
PORT MAP(Ax(73),Bx_int(NUM_BITS-1),Cx_int(72),clk,reset,Cx_int(73));
CELL_74: ENTITY basic_cell(behave)
PORT MAP(Ax(74),Bx_int(NUM_BITS-1),Cx_int(73),clk,reset,Cx_int(74));
CELL_75: ENTITY basic_cell(behave)
PORT MAP(Ax(75),Bx_int(NUM_BITS-1),Cx_int(74),clk,reset,Cx_int(75));
CELL_76: ENTITY basic_cell(behave)
PORT MAP(Ax(76),Bx_int(NUM_BITS-1),Cx_int(75),clk,reset,Cx_int(76));
CELL_77: ENTITY basic_cell(behave)
PORT MAP(Ax(77),Bx_int(NUM_BITS-1),Cx_int(76),clk,reset,Cx_int(77));
CELL_78: ENTITY basic_cell(behave)
PORT MAP(Ax(78),Bx_int(NUM_BITS-1),Cx_int(77),clk,reset,Cx_int(78));
CELL_79: ENTITY basic_cell(behave)
PORT MAP(Ax(79),Bx_int(NUM_BITS-1),Cx_int(78),clk,reset,Cx_int(79));
CELL_80: ENTITY basic_cell(behave)
PORT MAP(Ax(80),Bx_int(NUM_BITS-1),Cx_int(79),clk,reset,Cx_int(80));
CELL_81: ENTITY basic_cell(behave)
PORT MAP(Ax(81),Bx_int(NUM_BITS-1),Cx_int(80),clk,reset,Cx_int(81));
CELL_82: ENTITY basic_cell(behave)
PORT MAP(Ax(82),Bx_int(NUM_BITS-1),Cx_int(81),clk,reset,Cx_int(82));
CELL_83: ENTITY basic_cell(behave)
PORT MAP(Ax(83),Bx_int(NUM_BITS-1),Cx_int(82),clk,reset,Cx_int(83));
CELL_84: ENTITY basic_cell(behave)
PORT MAP(Ax(84),Bx_int(NUM_BITS-1),Cx_int(83),clk,reset,Cx_int(84));
CELL_85: ENTITY basic_cell(behave)
PORT MAP(Ax(85),Bx_int(NUM_BITS-1),Cx_int(84),clk,reset,Cx_int(85));
CELL_86: ENTITY basic_cell(behave)
PORT MAP(Ax(86),Bx_int(NUM_BITS-1),Cx_int(85),clk,reset,Cx_int(86));
CELL_87: ENTITY basic_cell(behave)
PORT MAP(Ax(87),Bx_int(NUM_BITS-1),Cx_int(86),clk,reset,Cx_int(87));
CELL_88: ENTITY basic_cell(behave)
PORT MAP(Ax(88),Bx_int(NUM_BITS-1),Cx_int(87),clk,reset,Cx_int(88));
CELL_89: ENTITY basic_cell(behave)
PORT MAP(Ax(89),Bx_int(NUM_BITS-1),Cx_int(88),clk,reset,Cx_int(89));
CELL_90: ENTITY basic_cell(behave)
PORT MAP(Ax(90),Bx_int(NUM_BITS-1),Cx_int(89),clk,reset,Cx_int(90));
CELL_91: ENTITY basic_cell(behave)
PORT MAP(Ax(91),Bx_int(NUM_BITS-1),Cx_int(90),clk,reset,Cx_int(91));
CELL_92: ENTITY basic_cell(behave)
PORT MAP(Ax(92),Bx_int(NUM_BITS-1),Cx_int(91),clk,reset,Cx_int(92));
CELL_93: ENTITY basic_cell(behave)
PORT MAP(Ax(93),Bx_int(NUM_BITS-1),Cx_int(92),clk,reset,Cx_int(93));
CELL_94: ENTITY basic_cell(behave)
PORT MAP(Ax(94),Bx_int(NUM_BITS-1),Cx_int(93),clk,reset,Cx_int(94));
CELL_95: ENTITY basic_cell(behave)
PORT MAP(Ax(95),Bx_int(NUM_BITS-1),Cx_int(94),clk,reset,Cx_int(95));
CELL_96: ENTITY basic_cell(behave)
PORT MAP(Ax(96),Bx_int(NUM_BITS-1),Cx_int(95),clk,reset,Cx_int(96));
CELL_97: ENTITY basic_cell(behave)
PORT MAP(Ax(97),Bx_int(NUM_BITS-1),Cx_int(96),clk,reset,Cx_int(97));
CELL_98: ENTITY basic_cell(behave)
PORT MAP(Ax(98),Bx_int(NUM_BITS-1),Cx_int(97),clk,reset,Cx_int(98));
CELL_99: ENTITY basic_cell(behave)
PORT MAP(Ax(99),Bx_int(NUM_BITS-1),Cx_int(98),clk,reset,Cx_int(99));
CELL_100: ENTITY basic_cell(behave)
PORT MAP(Ax(100),Bx_int(NUM_BITS-1),Cx_int(99),clk,reset,Cx_int(100));
CELL_101: ENTITY basic_cell(behave)
PORT MAP(Ax(101),Bx_int(NUM_BITS-1),Cx_int(100),clk,reset,Cx_int(101));
CELL_102: ENTITY basic_cell(behave)
PORT MAP(Ax(102),Bx_int(NUM_BITS-1),Cx_int(101),clk,reset,Cx_int(102));
CELL_103: ENTITY basic_cell(behave)
PORT MAP(Ax(103),Bx_int(NUM_BITS-1),Cx_int(102),clk,reset,Cx_int(103));
CELL_104: ENTITY basic_cell(behave)
PORT MAP(Ax(104),Bx_int(NUM_BITS-1),Cx_int(103),clk,reset,Cx_int(104));
CELL_105: ENTITY basic_cell(behave)
PORT MAP(Ax(105),Bx_int(NUM_BITS-1),Cx_int(104),clk,reset,Cx_int(105));
CELL_106: ENTITY basic_cell(behave)
PORT MAP(Ax(106),Bx_int(NUM_BITS-1),Cx_int(105),clk,reset,Cx_int(106));
CELL_107: ENTITY basic_cell(behave)
PORT MAP(Ax(107),Bx_int(NUM_BITS-1),Cx_int(106),clk,reset,Cx_int(107));
CELL_108: ENTITY basic_cell(behave)
PORT MAP(Ax(108),Bx_int(NUM_BITS-1),Cx_int(107),clk,reset,Cx_int(108));
CELL_109: ENTITY basic_cell(behave)
PORT MAP(Ax(109),Bx_int(NUM_BITS-1),Cx_int(108),clk,reset,Cx_int(109));
CELL_110: ENTITY basic_cell(behave)
PORT MAP(Ax(110),Bx_int(NUM_BITS-1),Cx_int(109),clk,reset,Cx_int(110));
CELL_111: ENTITY basic_cell(behave)
PORT MAP(Ax(111),Bx_int(NUM_BITS-1),Cx_int(110),clk,reset,Cx_int(111));
CELL_112: ENTITY basic_cell(behave)
PORT MAP(Ax(112),Bx_int(NUM_BITS-1),Cx_int(111),clk,reset,Cx_int(112));
CELL_113: ENTITY basic_cell(behave)
PORT MAP(Ax(113),Bx_int(NUM_BITS-1),Cx_int(112),clk,reset,Cx_int(113));
CELL_114: ENTITY basic_cell(behave)
PORT MAP(Ax(114),Bx_int(NUM_BITS-1),Cx_int(113),clk,reset,Cx_int(114));
CELL_115: ENTITY basic_cell(behave)
PORT MAP(Ax(115),Bx_int(NUM_BITS-1),Cx_int(114),clk,reset,Cx_int(115));
CELL_116: ENTITY basic_cell(behave)
PORT MAP(Ax(116),Bx_int(NUM_BITS-1),Cx_int(115),clk,reset,Cx_int(116));
CELL_117: ENTITY basic_cell(behave)
PORT MAP(Ax(117),Bx_int(NUM_BITS-1),Cx_int(116),clk,reset,Cx_int(117));
CELL_118: ENTITY basic_cell(behave)
PORT MAP(Ax(118),Bx_int(NUM_BITS-1),Cx_int(117),clk,reset,Cx_int(118));
CELL_119: ENTITY basic_cell(behave)
PORT MAP(Ax(119),Bx_int(NUM_BITS-1),Cx_int(118),clk,reset,Cx_int(119));
CELL_120: ENTITY basic_cell(behave)
PORT MAP(Ax(120),Bx_int(NUM_BITS-1),Cx_int(119),clk,reset,Cx_int(120));
CELL_121: ENTITY basic_cell(behave)
PORT MAP(Ax(121),Bx_int(NUM_BITS-1),Cx_int(120),clk,reset,Cx_int(121));
CELL_122: ENTITY basic_cell(behave)
PORT MAP(Ax(122),Bx_int(NUM_BITS-1),Cx_int(121),clk,reset,Cx_int(122));
CELL_123: ENTITY basic_cell(behave)
PORT MAP(Ax(123),Bx_int(NUM_BITS-1),Cx_int(122),clk,reset,Cx_int(123));
CELL_124: ENTITY basic_cell(behave)
PORT MAP(Ax(124),Bx_int(NUM_BITS-1),Cx_int(123),clk,reset,Cx_int(124));
CELL_125: ENTITY basic_cell(behave)
PORT MAP(Ax(125),Bx_int(NUM_BITS-1),Cx_int(124),clk,reset,Cx_int(125));
CELL_126: ENTITY basic_cell(behave)
PORT MAP(Ax(126),Bx_int(NUM_BITS-1),Cx_int(125),clk,reset,Cx_int(126));
CELL_127: ENTITY basic_cell(behave)
PORT MAP(Ax(127),Bx_int(NUM_BITS-1),Cx_int(126),clk,reset,Cx_int(127));
CELL_128: ENTITY basic_cell(behave)
PORT MAP(Ax(128),Bx_int(NUM_BITS-1),Cx_int(127),clk,reset,Cx_int(128));
CELL_129: ENTITY basic_cell(behave)
PORT MAP(Ax(129),Bx_int(NUM_BITS-1),Cx_int(128),clk,reset,Cx_int(129));
CELL_130: ENTITY basic_cell(behave)
PORT MAP(Ax(130),Bx_int(NUM_BITS-1),Cx_int(129),clk,reset,Cx_int(130));
CELL_131: ENTITY basic_cell(behave)
PORT MAP(Ax(131),Bx_int(NUM_BITS-1),Cx_int(130),clk,reset,Cx_int(131));
CELL_132: ENTITY basic_cell(behave)
PORT MAP(Ax(132),Bx_int(NUM_BITS-1),Cx_int(131),clk,reset,Cx_int(132));
CELL_133: ENTITY basic_cell(behave)
PORT MAP(Ax(133),Bx_int(NUM_BITS-1),Cx_int(132),clk,reset,Cx_int(133));
CELL_134: ENTITY basic_cell(behave)
PORT MAP(Ax(134),Bx_int(NUM_BITS-1),Cx_int(133),clk,reset,Cx_int(134));
CELL_135: ENTITY basic_cell(behave)
PORT MAP(Ax(135),Bx_int(NUM_BITS-1),Cx_int(134),clk,reset,Cx_int(135));
CELL_136: ENTITY basic_cell(behave)
PORT MAP(Ax(136),Bx_int(NUM_BITS-1),Cx_int(135),clk,reset,Cx_int(136));
CELL_137: ENTITY basic_cell(behave)
PORT MAP(Ax(137),Bx_int(NUM_BITS-1),Cx_int(136),clk,reset,Cx_int(137));
CELL_138: ENTITY basic_cell(behave)
PORT MAP(Ax(138),Bx_int(NUM_BITS-1),Cx_int(137),clk,reset,Cx_int(138));
CELL_139: ENTITY basic_cell(behave)
PORT MAP(Ax(139),Bx_int(NUM_BITS-1),Cx_int(138),clk,reset,Cx_int(139));
CELL_140: ENTITY basic_cell(behave)
PORT MAP(Ax(140),Bx_int(NUM_BITS-1),Cx_int(139),clk,reset,Cx_int(140));
CELL_141: ENTITY basic_cell(behave)
PORT MAP(Ax(141),Bx_int(NUM_BITS-1),Cx_int(140),clk,reset,Cx_int(141));
CELL_142: ENTITY basic_cell(behave)
PORT MAP(Ax(142),Bx_int(NUM_BITS-1),Cx_int(141),clk,reset,Cx_int(142));
CELL_143: ENTITY basic_cell(behave)
PORT MAP(Ax(143),Bx_int(NUM_BITS-1),Cx_int(142),clk,reset,Cx_int(143));
CELL_144: ENTITY basic_cell(behave)
PORT MAP(Ax(144),Bx_int(NUM_BITS-1),Cx_int(143),clk,reset,Cx_int(144));
CELL_145: ENTITY basic_cell(behave)
PORT MAP(Ax(145),Bx_int(NUM_BITS-1),Cx_int(144),clk,reset,Cx_int(145));
CELL_146: ENTITY basic_cell(behave)
PORT MAP(Ax(146),Bx_int(NUM_BITS-1),Cx_int(145),clk,reset,Cx_int(146));
CELL_147: ENTITY basic_cell(behave)
PORT MAP(Ax(147),Bx_int(NUM_BITS-1),Cx_int(146),clk,reset,Cx_int(147));
CELL_148: ENTITY basic_cell(behave)
PORT MAP(Ax(148),Bx_int(NUM_BITS-1),Cx_int(147),clk,reset,Cx_int(148));
CELL_149: ENTITY basic_cell(behave)
PORT MAP(Ax(149),Bx_int(NUM_BITS-1),Cx_int(148),clk,reset,Cx_int(149));
CELL_150: ENTITY basic_cell(behave)
PORT MAP(Ax(150),Bx_int(NUM_BITS-1),Cx_int(149),clk,reset,Cx_int(150));
CELL_151: ENTITY basic_cell(behave)
PORT MAP(Ax(151),Bx_int(NUM_BITS-1),Cx_int(150),clk,reset,Cx_int(151));
CELL_152: ENTITY basic_cell(behave)
PORT MAP(Ax(152),Bx_int(NUM_BITS-1),Cx_int(151),clk,reset,Cx_int(152));
CELL_153: ENTITY basic_cell(behave)
PORT MAP(Ax(153),Bx_int(NUM_BITS-1),Cx_int(152),clk,reset,Cx_int(153));
CELL_154: ENTITY basic_cell(behave)
PORT MAP(Ax(154),Bx_int(NUM_BITS-1),Cx_int(153),clk,reset,Cx_int(154));
CELL_155: ENTITY basic_cell(behave)
PORT MAP(Ax(155),Bx_int(NUM_BITS-1),Cx_int(154),clk,reset,Cx_int(155));
CELL_156: ENTITY basic_cell(behave)
PORT MAP(Ax(156),Bx_int(NUM_BITS-1),Cx_int(155),clk,reset,Cx_int(156));
CELL_157: ENTITY basic_cell(behave)
PORT MAP(Ax(157),Bx_int(NUM_BITS-1),Cx_int(156),clk,reset,Cx_int(157));
CELL_158: ENTITY basic_cell(behave)
PORT MAP(Ax(158),Bx_int(NUM_BITS-1),Cx_int(157),clk,reset,Cx_int(158));
CELL_159: ENTITY basic_cell(behave)
PORT MAP(Ax(159),Bx_int(NUM_BITS-1),Cx_int(158),clk,reset,Cx_int(159));
CELL_160: ENTITY basic_cell(behave)
PORT MAP(Ax(160),Bx_int(NUM_BITS-1),Cx_int(159),clk,reset,Cx_int(160));
CELL_161: ENTITY basic_cell(behave)
PORT MAP(Ax(161),Bx_int(NUM_BITS-1),Cx_int(160),clk,reset,Cx_int(161));
CELL_162: ENTITY basic_cell(behave)
PORT MAP(Ax(162),Bx_int(NUM_BITS-1),Cx_int(161),clk,reset,Cx_int(162));
done <= done_int;
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10100011"; -- m-1 value, in this case, it is 112, be sure to set the correct value
cx <= (others => '0');
Done_int <= '0';
else
if counter = "0000000" then -- The done signal is asserted at the same time that the result is computed.
if (done_int = '0') then
done_int <= '1';
Cx <= Cx_int;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
SHIFT_REGISTER: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
Bx_shift <= Bx;
else
Bx_shift <= Bx_shift(NUM_BITS-2 downto 0) & '0'; -- carga paralela
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
6fb418287bf4985a5e01d06ea236869f
| 0.650594 | 2.3777 | false | false | false | false |
nczempin/NICNAC16
|
ipcore_dir/ROM01/simulation/ROM01_tb.vhd
| 1 | 4,337 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ROM01_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ROM01_tb IS
END ENTITY;
ARCHITECTURE ROM01_tb_ARCH OF ROM01_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ROM01_synth_inst:ENTITY work.ROM01_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
mit
|
76238ab66a45a25e17227663210f7986
| 0.618861 | 4.633547 | false | false | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/graph _driver.vhd
| 1 | 936 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity graph_driver is
port (in_graph : in std_logic_vector(31 downto 0);
out_graph : out std_logic_vector(31 downto 0)
);
end graph_driver;
architecture synt of graph_driver is
begin
process(in_graph )
begin
if(in_graph="00000000000000000000000000000000")then --- zero
out_graph<="00001100000100100001001000001100";
elsif(in_graph="01111111100000000000000000000000")then
out_graph<="00001010000101010001010100001010"; -- + Inf
elsif(in_graph="11111111100000000000000000000000")then
out_graph<="00001010110101010001010100001010"; -- - Inf
elsif (in_graph(30 downto 23)="11111111" and in_graph(22 downto 0 )/= "00000000000000000000000") then
out_graph<="01001000010110000110100001001000"; --- not a number
else
out_graph<=in_graph;
end if ;
end process;
end synt;
|
mit
|
8fa022eb03a6194276bc34027610fab9
| 0.724359 | 3.586207 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_10a.vhd
| 4 | 1,691 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_10a is
end entity inline_10a;
----------------------------------------------------------------
architecture test of inline_10a is
-- code from book:
type stick_position is (down, center, up);
-- end of code from book
signal throttle : stick_position;
begin
process_3_a : process (throttle) is
variable speed : integer := 0;
constant decrement : integer := 1;
constant increment : integer := 1;
begin
-- code from book:
case throttle is
when down =>
speed := speed - decrement;
when up =>
speed := speed + increment;
when center =>
null; -- no change to speed
end case;
-- end of code from book
end process process_3_a;
stimulus : process is
begin
throttle <= down after 10 ns, center after 20 ns, up after 30 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
e091b3ae4a79ab264e6daa1669879c3d
| 0.655825 | 4.302799 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/bpm_cores_pkg.vhd
| 1 | 62,146 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
package bpm_cores_pkg is
-------------------------------------------------------------------------------
-- Types
-------------------------------------------------------------------------------
subtype t_swap_mode is std_logic_vector(1 downto 0);
constant c_swmode_rffe_swap : t_swap_mode := "00";
constant c_swmode_static_direct : t_swap_mode := "01";
constant c_swmode_static_inverted : t_swap_mode := "10";
constant c_swmode_swap_deswap : t_swap_mode := "11";
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component downconv is
generic (
g_input_width : natural := 16;
g_mixed_width : natural := 24;
g_output_width : natural := 32;
g_phase_width : natural := 8;
g_sin_file : string := "./dds_sin.nif";
g_cos_file : string := "./dds_cos.nif";
g_number_of_points : natural := 6;
g_diff_delay : natural := 2;
g_stages : natural := 3;
g_decimation_rate : natural := 1000);
port (
signal_i : in std_logic_vector(g_input_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
phase_i : in std_logic_vector(g_phase_width-1 downto 0);
I_o : out std_logic_vector(g_output_width-1 downto 0);
Q_o : out std_logic_vector(g_output_width-1 downto 0);
valid_o : out std_logic);
end component downconv;
component hpf_adcinput
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
data_i : in std_logic_vector(15 downto 0);
data_o : out std_logic_vector(15 downto 0)
);
end component hpf_adcinput;
component input_gen is
generic (
g_input_width : natural := 16;
g_output_width : natural := 16;
g_ksum : integer := 1);
port (
x_i : in std_logic_vector(g_input_width-1 downto 0);
y_i : in std_logic_vector(g_input_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
a_o : out std_logic_vector(g_output_width-1 downto 0);
b_o : out std_logic_vector(g_output_width-1 downto 0);
c_o : out std_logic_vector(g_output_width-1 downto 0);
d_o : out std_logic_vector(g_output_width-1 downto 0));
end component input_gen;
component fixed_dds is
generic (
g_number_of_points : natural := 203;
g_output_width : natural := 16;
g_sin_file : string := "./dds_sin.ram";
g_cos_file : string := "./dds_cos.ram");
port (
clk_i : in std_logic;
ce_i : in std_logic;
rst_i : in std_logic;
valid_i : in std_logic;
sin_o : out std_logic_vector(g_output_width-1 downto 0);
cos_o : out std_logic_vector(g_output_width-1 downto 0);
valid_o : out std_logic);
end component fixed_dds;
component lut_sweep is
generic (
g_number_of_points : natural := 203;
g_bus_size : natural := 16);
port (
rst_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
address_o : out std_logic_vector(g_bus_size-1 downto 0);
valid_o : out std_logic);
end component lut_sweep;
component dds_sin_lut
port (
clka : in std_logic;
addra : in std_logic_vector;
douta : out std_logic_vector);
end component dds_sin_lut;
component dds_cos_lut
port (
clka : in std_logic;
addra : in std_logic_vector;
douta : out std_logic_vector);
end component dds_cos_lut;
component sw_windowing_n_251_tukey_0_2
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(23 downto 0)
);
end component sw_windowing_n_251_tukey_0_2;
component mixer is
generic (
g_sin_file : string;
g_cos_file : string;
g_number_of_points : natural := 6;
g_input_width : natural := 16;
g_dds_width : natural := 16;
g_output_width : natural := 32;
g_tag_width : natural := 1;
g_mult_levels : natural := 7);
port (
rst_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
signal_i : in std_logic_vector(g_input_width-1 downto 0);
valid_i : in std_logic;
tag_i : in std_logic_vector(g_tag_width-1 downto 0) := (others => '0');
I_out : out std_logic_vector(g_output_width-1 downto 0);
I_tag_out : out std_logic_vector(g_tag_width-1 downto 0);
Q_out : out std_logic_vector(g_output_width-1 downto 0);
Q_tag_out : out std_logic_vector(g_tag_width-1 downto 0);
valid_o : out std_logic);
end component mixer;
component input_conditioner is
generic (
g_sw_interval : natural := 1000;
g_input_width : natural := 16;
g_output_width : natural := 24;
g_window_width : natural := 24;
g_input_delay : natural := 2;
g_window_coef_file : string);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
adc_a_i : in std_logic_vector(g_input_width-1 downto 0);
adc_b_i : in std_logic_vector(g_input_width-1 downto 0);
adc_c_i : in std_logic_vector(g_input_width-1 downto 0);
adc_d_i : in std_logic_vector(g_input_width-1 downto 0);
switch_o : out std_logic;
switch_en_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
a_o : out std_logic_vector(g_output_width-1 downto 0);
b_o : out std_logic_vector(g_output_width-1 downto 0);
c_o : out std_logic_vector(g_output_width-1 downto 0);
d_o : out std_logic_vector(g_output_width-1 downto 0);
dbg_cur_address_o : out std_logic_vector(31 downto 0));
end component input_conditioner;
component counter is
generic (
g_mem_size : natural := 601;
g_bus_size : natural := 15);
port (
clk_i : in std_logic;
ce_i : in std_logic;
rst_n_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
switch_en_i : in std_logic;
switch_o : out std_logic;
index_o : out std_logic_vector(g_bus_size-1 downto 0));
end component counter;
component position_calc is
generic (
g_with_downconv : boolean := true;
g_input_width : natural := 16;
g_mixed_width : natural := 16;
g_adc_ratio : natural := 1;
g_dds_width : natural := 16;
g_dds_points : natural := 35;
g_sin_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_sin.nif";
g_cos_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_cos.nif";
g_tbt_tag_desync_cnt_width : natural := 14;
g_tbt_cic_mask_samples_width : natural := 16;
g_tbt_cic_delay : natural := 1;
g_tbt_cic_stages : natural := 2;
g_tbt_ratio : natural := 35;
g_tbt_decim_width : natural := 32;
g_fofb_cic_delay : natural := 1;
g_fofb_cic_stages : natural := 2;
g_fofb_ratio : natural := 980;
g_fofb_decim_width : natural := 32;
g_fofb_decim_desync_cnt_width : natural := 14;
g_fofb_cic_mask_samples_width : natural := 16;
g_monit1_cic_delay : natural := 1;
g_monit1_cic_stages : natural := 1;
g_monit1_ratio : natural := 100;
g_monit1_cic_ratio : positive := 8;
g_monit1_tag_desync_cnt_width : natural := 14;
g_monit1_cic_mask_samples_width : natural := 16;
g_monit2_cic_delay : natural := 1;
g_monit2_cic_stages : natural := 1;
g_monit2_ratio : natural := 100;
g_monit2_cic_ratio : positive := 8;
g_monit2_tag_desync_cnt_width : natural := 14;
g_monit2_cic_mask_samples_width : natural := 16;
g_monit_decim_width : natural := 32;
g_tbt_cordic_stages : positive := 12;
g_tbt_cordic_iter_per_clk : positive := 3;
g_tbt_cordic_ratio : positive := 4;
g_fofb_cordic_stages : positive := 15;
g_fofb_cordic_iter_per_clk : positive := 3;
g_fofb_cordic_ratio : positive := 4;
g_k_width : natural := 25;
g_offset_width : natural := 32;
g_IQ_width : natural := 32);
port (
adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch2_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch3_i : in std_logic_vector(g_input_width-1 downto 0);
adc_tag_i : in std_logic_vector(0 downto 0);
adc_tag_en_i : in std_logic := '0';
adc_valid_i : in std_logic;
clk_i : in std_logic;
rst_i : in std_logic;
ksum_i : in std_logic_vector(g_k_width-1 downto 0);
kx_i : in std_logic_vector(g_k_width-1 downto 0);
ky_i : in std_logic_vector(g_k_width-1 downto 0);
offset_x_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
offset_y_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_valid_o : out std_logic;
mix_ce_o : out std_logic;
tbt_tag_i : in std_logic_vector(0 downto 0);
tbt_tag_en_i : in std_logic := '0';
tbt_tag_desync_cnt_rst_i : in std_logic := '0';
tbt_tag_desync_cnt_o : out std_logic_vector(g_tbt_tag_desync_cnt_width-1 downto 0);
tbt_decim_mask_en_i : in std_logic := '0';
tbt_decim_mask_num_samples_beg_i : in unsigned(g_tbt_cic_mask_samples_width-1 downto 0) := (others => '0');
tbt_decim_mask_num_samples_end_i : in unsigned(g_tbt_cic_mask_samples_width-1 downto 0) := (others => '0');
tbt_decim_ch0_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_decim_ce_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_amp_ce_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_valid_o : out std_logic;
tbt_pha_ce_o : out std_logic;
fofb_decim_desync_cnt_rst_i : in std_logic := '0';
fofb_decim_desync_cnt_o : out std_logic_vector(g_fofb_decim_desync_cnt_width-1 downto 0);
fofb_decim_mask_en_i : in std_logic := '0';
fofb_decim_mask_num_samples_i : in unsigned(g_fofb_cic_mask_samples_width-1 downto 0) := (others => '0');
fofb_decim_ch0_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_decim_ce_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_amp_ce_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_valid_o : out std_logic;
fofb_pha_ce_o : out std_logic;
monit1_tag_i : in std_logic_vector(0 downto 0);
monit1_tag_en_i : in std_logic := '0';
monit1_tag_desync_cnt_rst_i : in std_logic := '0';
monit1_tag_desync_cnt_o : out std_logic_vector(g_monit1_tag_desync_cnt_width-1 downto 0);
monit1_decim_mask_en_i : in std_logic := '0';
monit1_decim_mask_num_samples_beg_i : in unsigned(g_monit1_cic_mask_samples_width-1 downto 0) := (others => '0');
monit1_decim_mask_num_samples_end_i : in unsigned(g_monit1_cic_mask_samples_width-1 downto 0) := (others => '0');
monit1_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_valid_o : out std_logic;
monit1_amp_ce_o : out std_logic;
monit_tag_i : in std_logic_vector(0 downto 0);
monit_tag_en_i : in std_logic := '0';
monit_tag_desync_cnt_rst_i : in std_logic := '0';
monit_tag_desync_cnt_o : out std_logic_vector(g_monit2_tag_desync_cnt_width-1 downto 0);
monit_decim_mask_en_i : in std_logic := '0';
monit_decim_mask_num_samples_beg_i : in unsigned(g_monit2_cic_mask_samples_width-1 downto 0) := (others => '0');
monit_decim_mask_num_samples_end_i : in unsigned(g_monit2_cic_mask_samples_width-1 downto 0) := (others => '0');
monit_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_valid_o : out std_logic;
monit_amp_ce_o : out std_logic;
tbt_pos_x_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_y_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_sum_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_valid_o : out std_logic;
tbt_pos_ce_o : out std_logic;
fofb_pos_x_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_y_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_sum_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_valid_o : out std_logic;
fofb_pos_ce_o : out std_logic;
monit1_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_valid_o : out std_logic;
monit1_pos_ce_o : out std_logic;
monit_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_valid_o : out std_logic;
monit_pos_ce_o : out std_logic);
end component position_calc;
component swap_freqgen
generic(
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
sync_trig_i : in std_logic;
-- Swap and de-swap signals
swap_o : out std_logic;
deswap_o : out std_logic;
-- Swap mode setting
swap_mode_i : in t_swap_mode;
-- Swap frequency settings
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
swap_div_f_cnt_en_i : in std_logic := '1';
-- De-swap delay setting
deswap_delay_i : in std_logic_vector(g_delay_vec_width-1 downto 0)
);
end component;
component deswap_channels
generic(
g_ch_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
deswap_i : in std_logic;
ch1_i : in std_logic_vector(g_ch_width-1 downto 0);
ch2_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
ch1_o : out std_logic_vector(g_ch_width-1 downto 0);
ch2_o : out std_logic_vector(g_ch_width-1 downto 0);
deswap_o : out std_logic;
ch_valid_o : out std_logic
);
end component;
component swmode_sel
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
-- Swap master clock
clk_swap_i : in std_logic;
-- Swap and de-swap signals
swap_o : out std_logic;
deswap_o : out std_logic;
-- Swap mode setting
swap_mode_i : in t_swap_mode
);
end component;
component bpm_swap
generic(
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16;
g_ch_width : natural := 16
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Input data from ADCs
cha_i : in std_logic_vector(g_ch_width-1 downto 0);
chb_i : in std_logic_vector(g_ch_width-1 downto 0);
chc_i : in std_logic_vector(g_ch_width-1 downto 0);
chd_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
-- Output data to BPM DSP chain
cha_o : out std_logic_vector(g_ch_width-1 downto 0);
chb_o : out std_logic_vector(g_ch_width-1 downto 0);
chc_o : out std_logic_vector(g_ch_width-1 downto 0);
chd_o : out std_logic_vector(g_ch_width-1 downto 0);
ch_tag_o : out std_logic_vector(0 downto 0);
ch_valid_o : out std_logic;
-- RFFE swap clock (or switchwing clock)
rffe_swclk_o : out std_logic;
-- RFFE swap clock synchronization trigger
sync_trig_i : in std_logic;
-- Swap mode setting
swap_mode_i : in std_logic_vector(1 downto 0);
-- Swap frequency settings
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
-- De-swap delay setting
deswap_delay_i : in std_logic_vector(g_delay_vec_width-1 downto 0)
);
end component;
component wb_bpm_swap is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16;
g_ch_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
-- Input data from ADCs
cha_i : in std_logic_vector(g_ch_width-1 downto 0);
chb_i : in std_logic_vector(g_ch_width-1 downto 0);
chc_i : in std_logic_vector(g_ch_width-1 downto 0);
chd_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
-- Output data to BPM DSP chain
cha_o : out std_logic_vector(g_ch_width-1 downto 0);
chb_o : out std_logic_vector(g_ch_width-1 downto 0);
chc_o : out std_logic_vector(g_ch_width-1 downto 0);
chd_o : out std_logic_vector(g_ch_width-1 downto 0);
ch_tag_o : out std_logic_vector(0 downto 0);
ch_valid_o : out std_logic;
-- RFFE swap clock (or switchwing clock)
rffe_swclk_o : out std_logic;
-- RFFE swap clock synchronization trigger
sync_trig_i : in std_logic
);
end component wb_bpm_swap;
component xwb_bpm_swap
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_ch_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- Input data from ADCs
cha_i : in std_logic_vector(g_ch_width-1 downto 0);
chb_i : in std_logic_vector(g_ch_width-1 downto 0);
chc_i : in std_logic_vector(g_ch_width-1 downto 0);
chd_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
-- Output data to BPM DSP chain
cha_o : out std_logic_vector(g_ch_width-1 downto 0);
chb_o : out std_logic_vector(g_ch_width-1 downto 0);
chc_o : out std_logic_vector(g_ch_width-1 downto 0);
chd_o : out std_logic_vector(g_ch_width-1 downto 0);
ch_tag_o : out std_logic_vector(0 downto 0);
ch_valid_o : out std_logic;
-- RFFE swap clock (or switchwing clock)
rffe_swclk_o : out std_logic;
-- RFFE swap clock synchronization trigger
sync_trig_i : in std_logic
);
end component;
component position_calc_cdc_fifo is
generic (
g_data_width : natural;
g_size : natural);
port (
clk_wr_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
valid_i : in std_logic;
clk_rd_i : in std_logic;
data_o : out std_logic_vector(g_data_width-1 downto 0);
valid_o : out std_logic);
end component position_calc_cdc_fifo;
component wb_position_calc_core
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false;
g_rffe_version : string := "V2";
-- selection of position_calc stages
g_with_downconv : boolean := true;
-- input sizes
g_input_width : natural := 16;
g_mixed_width : natural := 16;
g_adc_ratio : natural := 1;
-- mixer
g_dds_width : natural := 16;
g_dds_points : natural := 35;
g_sin_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_sin.nif";
g_cos_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_cos.nif";
-- CIC setup
g_tbt_cic_delay : natural := 1;
g_tbt_cic_stages : natural := 2;
g_tbt_ratio : natural := 35; -- ratio between
g_tbt_decim_width : natural := 32;
g_fofb_cic_delay : natural := 1;
g_fofb_cic_stages : natural := 2;
g_fofb_ratio : natural := 980; -- ratio between adc and fofb rates
g_fofb_decim_width : natural := 32;
g_monit1_cic_delay : natural := 1;
g_monit1_cic_stages : natural := 1;
g_monit1_ratio : natural := 100; --ratio between fofb and monit 1
g_monit1_cic_ratio : positive := 8;
g_monit2_cic_delay : natural := 1;
g_monit2_cic_stages : natural := 1;
g_monit2_ratio : natural := 100; -- ratio between monit 1 and 2
g_monit2_cic_ratio : positive := 8;
g_monit_decim_width : natural := 32;
-- Cordic setup
g_tbt_cordic_stages : positive := 12;
g_tbt_cordic_iter_per_clk : positive := 3;
g_tbt_cordic_ratio : positive := 4;
g_fofb_cordic_stages : positive := 15;
g_fofb_cordic_iter_per_clk : positive := 3;
g_fofb_cordic_ratio : positive := 4;
-- width of K constants
g_k_width : natural := 25;
-- width of offset constants
g_offset_width : natural := 32;
--width for IQ output
g_IQ_width : natural := 32;
-- Swap/de-swap setup
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch2_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch3_i : in std_logic_vector(g_input_width-1 downto 0);
adc_valid_i : in std_logic;
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch1_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch2_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch3_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_tag_o : out std_logic_vector(0 downto 0);
adc_swap_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit1_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_valid_o : out std_logic;
monit_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
tbt_pos_x_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_y_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_sum_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_valid_o : out std_logic;
fofb_pos_x_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_y_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_sum_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_valid_o : out std_logic;
monit1_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_valid_o : out std_logic;
monit_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
rffe_swclk_o : out std_logic;
-----------------------------
-- Synchronization trigger for all rates. Slow clock
-----------------------------
sync_trig_slow_i : in std_logic;
-----------------------------
-- Debug signals
-----------------------------
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(g_input_width-1 downto 0)
);
end component;
component xwb_position_calc_core
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false;
g_rffe_version : string := "V2";
-- selection of position_calc stages
g_with_downconv : boolean := true;
-- input sizes
g_input_width : natural := 16;
g_mixed_width : natural := 16;
g_adc_ratio : natural := 1;
-- mixer
g_dds_width : natural := 16;
g_dds_points : natural := 35;
g_sin_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_sin.nif";
g_cos_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_cos.nif";
-- CIC setup
g_tbt_cic_delay : natural := 1;
g_tbt_cic_stages : natural := 2;
g_tbt_ratio : natural := 35; -- ratio between
g_tbt_decim_width : natural := 32;
g_fofb_cic_delay : natural := 1;
g_fofb_cic_stages : natural := 2;
g_fofb_ratio : natural := 980; -- ratio between adc and fofb rates
g_fofb_decim_width : natural := 32;
g_monit1_cic_delay : natural := 1;
g_monit1_cic_stages : natural := 1;
g_monit1_ratio : natural := 100; --ratio between fofb and monit 1
g_monit1_cic_ratio : positive := 8;
g_monit2_cic_delay : natural := 1;
g_monit2_cic_stages : natural := 1;
g_monit2_ratio : natural := 100; -- ratio between monit 1 and 2
g_monit2_cic_ratio : positive := 8;
-- Cordic setup
g_tbt_cordic_stages : positive := 12;
g_tbt_cordic_iter_per_clk : positive := 3;
g_tbt_cordic_ratio : positive := 4;
g_fofb_cordic_stages : positive := 15;
g_fofb_cordic_iter_per_clk : positive := 3;
g_fofb_cordic_ratio : positive := 4;
g_monit_decim_width : natural := 32;
-- width of K constants
g_k_width : natural := 25;
-- width of offset constants
g_offset_width : natural := 32;
--width for IQ output
g_IQ_width : natural := 32;
-- Swap/de-swap setup
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch2_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch3_i : in std_logic_vector(g_input_width-1 downto 0);
adc_valid_i : in std_logic;
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch1_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch2_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch3_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_tag_o : out std_logic_vector(0 downto 0);
adc_swap_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit1_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_valid_o : out std_logic;
monit_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
tbt_pos_x_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_y_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_sum_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_valid_o : out std_logic;
fofb_pos_x_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_y_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_sum_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_valid_o : out std_logic;
monit1_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_valid_o : out std_logic;
monit_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
rffe_swclk_o : out std_logic;
-----------------------------
-- Synchronization trigger for all rates. Slow clock
-----------------------------
sync_trig_slow_i : in std_logic;
-----------------------------
-- Debug signals
-----------------------------
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(g_input_width-1 downto 0)
);
end component;
component wb_orbit_intlk
generic
(
-- Wishbone
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_WITH_EXTRA_WB_REG : boolean := false;
-- Position
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_WISHBONE_ADDRESS_WIDTH-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_WISHBONE_DATA_WIDTH-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_WISHBONE_DATA_WIDTH-1 downto 0);
wb_sel_i : in std_logic_vector(c_WISHBONE_DATA_WIDTH/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic;
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_o : out std_logic
);
end component;
component xwb_orbit_intlk
generic
(
-- Wishbone
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_WITH_EXTRA_WB_REG : boolean := false;
-- Position
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic;
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_o : out std_logic
);
end component;
end bpm_cores_pkg;
package body bpm_cores_pkg is
end bpm_cores_pkg;
|
lgpl-3.0
|
07bb0b32dae90bffed0f80f2e052aba2
| 0.515769 | 3.279299 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/sim/test_pkg/test_pkg.vhd
| 2 | 11,544 |
-------------------------------------------------------------------------------
-- Title : Useful functions for testbenches
-- Project :
-------------------------------------------------------------------------------
-- File : test_pkg.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-05-07
-- Last update: 2015-11-30
-- Last update: 2015-07-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This package contains useful functions and procedures for
-- testbenches: clock, reset and ce generators, data reader and writer from
-- files, etc...>
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-05-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
package test_pkg is
-- generate basic clock signals : clock and clock enable
procedure p_clk_gen(signal clk : out std_ulogic;
constant c_FREQ : real);
procedure p_ce_gen(signal clk : in std_ulogic;
signal ce : out std_ulogic;
signal rst : in std_ulogic;
constant c_CYCLES : positive);
procedure p_rst_gen(signal clk : in std_ulogic;
signal rst : out std_ulogic;
constant c_CYCLES : positive);
procedure p_pwm_gen(signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal pwm : out std_ulogic;
constant c_on_CYCLE : positive;
constant c_off_CYCLE : positive);
-- Read and write integer data from/to TSV, easily read/written by Octave:
type array_signed is array(natural range <>) of signed;
procedure p_read_tsv_file_signed (
constant c_INPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal req : in std_ulogic;
signal sample : out array_signed;
signal valid : out std_ulogic;
signal end_of_file : out std_ulogic);
procedure p_write_tsv_file_signed (
constant c_OUTPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal sample : in array_signed;
signal valid : in std_ulogic;
signal end_of_file : in std_ulogic);
end test_pkg;
package body test_pkg is
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: clk_gen
-- Generates clock signal, given any frequency.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_clk_gen(
signal clk : out std_ulogic;
constant c_FREQ : real) is
constant c_PERIOD : time := 1 sec / c_FREQ; -- Full period
constant c_HIGH_TIME : time := c_PERIOD / 2; -- High time
constant c_LOW_TIME : time := c_PERIOD - c_HIGH_TIME; -- Low time; always >= HIGH_TIME
begin
-- Check the arguments
assert (c_HIGH_TIME /= 0 fs) report "clk: High time is zero; time resolution to large for frequency" severity failure;
-- Generate a clock cycle
loop
clk <= '1';
wait for c_HIGH_TIME;
clk <= '0';
wait for c_LOW_TIME;
end loop;
end procedure;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: p_rst_gen
-- Keeps reset up until c_CYCLES clock cycles
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_rst_gen (
signal clk : in std_ulogic;
signal rst : out std_ulogic;
constant c_CYCLES : positive) is
variable v_cycle_count : natural := c_CYCLES;
begin -- procedure p_rst_gen
loop
wait until rising_edge(clk);
if v_cycle_count = 0 then
rst <= '0';
else
v_cycle_count := v_cycle_count -1;
end if;
end loop;
end procedure p_rst_gen;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: ce_gen
-- Generates one clock enable signals every c_CYCLES number of clock periods.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_ce_gen (
signal clk : in std_ulogic;
signal ce : out std_ulogic;
signal rst : in std_ulogic;
constant c_CYCLES : positive) is
variable ce_count : natural := c_CYCLES;
begin -- procedure p_ce_gen
loop -- generate one ce every ce_CYCLES clocks
wait until rising_edge(clk) and rst = '0';
ce_count := ce_count - 1;
if ce_count = 0 then
ce <= '1';
ce_count := c_CYCLES;
else
ce <= '0';
end if;
end loop;
end procedure p_ce_gen;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: pwm_gen
-- Generates a clock dependent PWM signal with configurable ON and OFF cycles.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_pwm_gen(
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal pwm : out std_ulogic;
constant c_on_CYCLE : positive;
constant c_off_CYCLE : positive) is
variable on_count : natural := c_on_CYCLE;
variable off_count : natural := c_off_CYCLE;
begin -- procedure p_ce_gen
loop -- generate one ce every ce_CYCLES clocks
wait until rising_edge(clk) and rst = '0';
if on_count > 0 then
on_count := on_count-1;
pwm <= '1';
elsif off_count > 1 then
off_count := off_count-1;
pwm <= '0';
else
on_count := c_on_CYCLE;
off_count := c_off_CYCLE;
pwm <= '0';
end if;
end loop;
end procedure;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: p_read_tsv_file_signed
-- Given a file name and clock, output signed vectors representing stimulus
-- in the file.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_read_tsv_file_signed (
constant c_INPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal req : in std_ulogic;
signal sample : out array_signed;
signal valid : out std_ulogic;
signal end_of_file : out std_ulogic) is
file input_file : text open read_mode is c_INPUT_FILE_NAME;
variable cur_line : line;
variable input : integer;
begin -- procedure p_read_tsv_file_signed
end_of_file <= '0';
valid <= '0';
wait until rst = '0';
loop
wait until falling_edge(clk) and ce = '1';
if endfile(input_file) then
end_of_file <= '1';
else
if req = '1' then
valid <= '1';
readline(input_file, cur_line);
for cur_sample in 0 to c_SAMPLES_PER_LINE-1 loop
read(cur_line, input);
sample(cur_sample) <= to_signed(input, c_OUTPUT_WIDTH);
end loop;
else
valid <= '0';
end if;
end if;
end loop;
end procedure p_read_tsv_file_signed;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: p_write_tsv_file_signed
-- Given a file name and clock, write data from signed vectors to an output
-- file, until end_of_file is set.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_write_tsv_file_signed (
constant c_OUTPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal sample : in array_signed;
signal valid : in std_ulogic;
signal end_of_file : in std_ulogic) is
file output_file : text open write_mode is c_OUTPUT_FILE_NAME;
variable cur_line : line;
variable output : integer;
begin -- procedure p_write_tsv_file_signed
wait until rst = '0';
loop
wait until rising_edge(clk) and ce = '1';
if valid = '1' then
for cur_sample in 0 to c_SAMPLES_PER_LINE-1 loop
output := to_integer(sample(cur_sample));
write(cur_line, output);
write(cur_line, ht);
end loop;
writeline(output_file, cur_line);
end if;
if end_of_file = '1' then
assert(false) report "End of file signal received" severity failure;
end if;
end loop;
end procedure p_write_tsv_file_signed;
end package body test_pkg;
|
lgpl-3.0
|
7bd31a1116eca1c14c0138a168750b69
| 0.45071 | 4.736972 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASliceOfReg2b.vhd
| 1 | 2,898 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Register where an overlapping slices of next signal are set conditionally
--
ENTITY AssignToASliceOfReg2b IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_mask : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg2b IS
SIGNAL r : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL r_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL r_next_11downto8 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL r_next_15downto12 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL r_next_3downto0 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL r_next_7downto4 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"0000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_15downto12 & r_next_11downto8 & r_next_7downto4 & r_next_3downto0;
assig_process_r_next_11downto8: PROCESS(data_in_addr, data_in_data, data_in_mask, data_in_vld, r)
BEGIN
IF data_in_vld = '1' AND data_in_addr = "1" THEN
IF data_in_mask = X"FF" THEN
r_next_11downto8 <= data_in_data(3 DOWNTO 0);
r_next_15downto12 <= data_in_data(7 DOWNTO 4);
ELSIF data_in_mask = X"0F" THEN
r_next_15downto12 <= data_in_data(3 DOWNTO 0);
r_next_11downto8 <= r(11 DOWNTO 8);
ELSE
r_next_11downto8 <= r(11 DOWNTO 8);
r_next_15downto12 <= r(15 DOWNTO 12);
END IF;
ELSE
r_next_11downto8 <= r(11 DOWNTO 8);
r_next_15downto12 <= r(15 DOWNTO 12);
END IF;
END PROCESS;
assig_process_r_next_3downto0: PROCESS(data_in_addr, data_in_data, data_in_mask, data_in_vld, r)
BEGIN
IF data_in_vld = '1' AND data_in_addr = "0" THEN
IF data_in_mask = X"FF" THEN
r_next_3downto0 <= data_in_data(3 DOWNTO 0);
r_next_7downto4 <= data_in_data(7 DOWNTO 4);
ELSIF data_in_mask = X"0F" THEN
r_next_7downto4 <= data_in_data(3 DOWNTO 0);
r_next_3downto0 <= r(3 DOWNTO 0);
ELSE
r_next_3downto0 <= r(3 DOWNTO 0);
r_next_7downto4 <= r(7 DOWNTO 4);
END IF;
ELSE
r_next_3downto0 <= r(3 DOWNTO 0);
r_next_7downto4 <= r(7 DOWNTO 4);
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
8061fd8d215743d8c29e271ae730721d
| 0.55314 | 3.234375 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/pcie/top_ml605.vhd
| 1 | 7,914 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
use work.bpm_pcie_ml605_priv_pkg.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE";
--***************************************************************************
-- Necessary parameters for DDR core support
-- (dependent on memory chip connected to FPGA, not to be modified at will)
--***************************************************************************
constant DDR_DQ_WIDTH : integer := 64;
constant DDR_PAYLOAD_WIDTH : integer := 256;
constant DDR_DQS_WIDTH : integer := 8;
constant DDR_DM_WIDTH : integer := 8;
constant DDR_ROW_WIDTH : integer := 14;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
ddr_sys_clk_n : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic --Reset to PCIe core
);
end entity top;
architecture arch of top is
-- WISHBONE SLAVE interface:
-- Single-Port RAM with Asynchronous Read
--
component WB_MEM is
generic(
AWIDTH : natural range 2 to 29 := 7;
DWIDTH : natural range 8 to 128 := 64
);
port(
CLK_I : in std_logic;
ACK_O : out std_logic;
ADR_I : in std_logic_vector(AWIDTH-1 downto 0);
DAT_I : in std_logic_vector(DWIDTH-1 downto 0);
DAT_O : out std_logic_vector(DWIDTH-1 downto 0);
STB_I : in std_logic;
WE_I : in std_logic
);
end component;
signal ddr_sys_clk_i : std_logic;
signal ddr_sys_rst_i : std_logic;
signal ddr_ui_clk : std_logic;
signal pll_clkin : std_logic;
signal pll_clkfbout : std_logic;
signal pll_clkout0 : std_logic;
signal pll_locked : std_logic;
signal wbone_clk : std_logic;
signal wbone_addr : std_logic_vector(31 downto 0);
signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_we : std_logic;
signal wbone_sel : std_logic_vector(0 downto 0);
signal wbone_stb : std_logic;
signal wbone_ack : std_logic;
signal wbone_cyc : std_logic;
signal wbone_rst : std_logic;
begin
bpm_pcie : bpm_pcie_ml605
generic map(
SIMULATION => SIMULATION,
-- ****
-- PCIe core parameters
-- ****
pcieLanes => pcieLanes,
PL_FAST_TRAIN => PL_FAST_TRAIN,
PIPE_SIM_MODE => PIPE_SIM_MODE
)
port map(
--DDR3 memory pins
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cs_n => ddr3_cs_n,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
-- PCIe transceivers
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- Necessity signals
ddr_sys_clk_p => ddr_sys_clk_i,
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_rst_n => sys_rst_n,
-- DDR memory controller interface --
-- uncomment when instantiating in another project
ddr_core_rst => ddr_sys_rst_i,
memc_ui_clk => ddr_ui_clk,
memc_ui_rst => open,
memc_cmd_rdy => open,
memc_cmd_en => '0',
memc_cmd_instr => (others => '0'),
memc_cmd_addr => (others => '0'),
memc_wr_en => '0',
memc_wr_end => '0',
memc_wr_mask => (others => '0'),
memc_wr_data => (others => '0'),
memc_wr_rdy => open,
memc_rd_data => open,
memc_rd_valid => open,
---- memory arbiter interface
memarb_acc_req => '0',
memarb_acc_gnt => open,
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I => wbone_clk,
RST_I => wbone_rst,
ACK_I => wbone_ack,
DAT_I => wbone_mdin,
ADDR_O => wbone_addr(28 downto 0),
DAT_O => wbone_mdout,
WE_O => wbone_we,
STB_O => wbone_stb,
SEL_O => wbone_sel(0),
CYC_O => wbone_cyc,
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o => wbone_rst
);
Wishbone_mem_large: if (SIMULATION = "TRUE") generate
wb_mem_sim :
wb_mem
generic map(
AWIDTH => 16,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
Wishbone_mem_sample: if (SIMULATION = "FALSE") generate
wb_mem_syn :
wb_mem
generic map(
AWIDTH => 7,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
--temporary clock assignment
wbone_clk <= ddr_ui_clk;
ddr_inclk_bufgds : IBUFGDS
generic map(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE
)
port map(
O => ddr_sys_clk_i,
I => ddr_sys_clk_p,
IB => ddr_sys_clk_n
);
ddr_sys_rst_i <= wbone_rst;
end architecture;
|
lgpl-3.0
|
37964fdeb302572cb5c7ccc5f6fa6f30
| 0.554587 | 3.202752 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_clk_sdr_s8_diff.vhd
| 1 | 6,818 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_sdr_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n DDR clock receiver module for serdes factors from 2 to 8 with differential inputs
-- Instantiates necessary BUFIO2 clock buffers
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_clk_sdr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic ; -- Input from LVDS receiver pin
clkin_n : in std_logic ; -- Input from LVDS receiver pin
reset : in std_logic ; -- Reset line
rxioclk : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_x1 : out std_logic) ; -- Global clock
end serdes_1_to_n_clk_sdr_s8_diff ;
architecture arch_serdes_1_to_n_clk_sdr_s8_diff of serdes_1_to_n_clk_sdr_s8_diff is
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal rx_clk_in : std_logic; --
signal iob_data_in_p : std_logic; --
signal iob_data_in_n : std_logic; --
signal rx_clk_in_p : std_logic; --
signal rx_clk_in_n : std_logic; --
signal rx_bufio2_x1 : std_logic; --
constant RX_SWAP_CLK : std_logic := '0' ; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
iob_clk_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => rx_clk_in_p) ;
iob_data_in_p <= rx_clk_in_p xor RX_SWAP_CLK ; -- Invert clock as required
-- IODELAY for the differential inputs.
--
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 49, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in_p, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line to 1/2 max in this case
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
bufg_pll_x1 : BUFG port map (I => rx_bufio2_x1, O => rx_bufg_x1) ;
bufio2_2clk_inst : BUFIO2 generic map(
DIVIDE => S,
DIVIDE_BYPASS => FALSE) -- The DIVCLK divider divide-by value; default 1
port map (
I => ddly_m, -- Input source clock 0 degrees
IOCLK => rxioclk, -- Output Clock for IO
DIVCLK => rx_bufio2_x1, -- Output Divided Clock
SERDESSTROBE => rx_serdesstrobe) ; -- Output SERDES strobe (Clock Enable)
end arch_serdes_1_to_n_clk_sdr_s8_diff ;
|
apache-2.0
|
9d7ebbe32a92e99ee2c76058c7180dc9
| 0.603549 | 3.46972 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_mul/fp_mul_sim/fp_mul.vhd
| 1 | 48,915 |
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_mul
-- VHDL created on Thu Feb 15 13:10:22 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_mul is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(31 downto 0); -- float32_m23
clk : in std_logic;
areset : in std_logic
);
end fp_mul;
architecture normal of fp_mul is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal expX_uid6_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expY_uid7_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal signX_uid8_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signY_uid9_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid10_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid11_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid12_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal frac_x_uid14_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_x_uid15_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_x_uid15_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid16_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid16_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid17_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid17_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid18_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_x_uid19_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid20_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid21_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid22_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_x_uid23_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal frac_y_uid28_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_y_uid29_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid29_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid30_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid30_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid31_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid31_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid32_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_y_uid33_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid34_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid35_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid36_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_y_uid37_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal ofracX_uid40_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal ofracY_uid43_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal expSum_uid44_fpMulTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal biasInc_uid45_fpMulTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal expSumMBias_uid46_fpMulTest_a : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_o : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_q : STD_LOGIC_VECTOR (10 downto 0);
signal signR_uid48_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid48_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal normalizeBit_uid49_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPostNormHigh_uid51_fpMulTest_in : STD_LOGIC_VECTOR (25 downto 0);
signal fracRPostNormHigh_uid51_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPostNormLow_uid52_fpMulTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal fracRPostNormLow_uid52_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPostNorm_uid53_fpMulTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPostNorm_uid53_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal expFracPreRound_uid55_fpMulTest_q : STD_LOGIC_VECTOR (34 downto 0);
signal roundBitAndNormalizationOp_uid57_fpMulTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_a : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_b : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_o : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_q : STD_LOGIC_VECTOR (35 downto 0);
signal fracRPreExc_uid59_fpMulTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExc_uid59_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcExt_uid60_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal expRPreExc_uid61_fpMulTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal expRPreExc_uid61_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expUdf_uid62_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal expUdf_uid62_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal expUdf_uid62_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal expUdf_uid62_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal expOvf_uid64_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal expOvf_uid64_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal expOvf_uid64_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal expOvf_uid64_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYZ_uid65_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYR_uid66_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXR_uid67_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excZC3_uid68_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid69_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIAndExcYI_uid70_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXRAndExcYI_uid71_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYRAndExcXI_uid72_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal ExcROvfAndInReg_uid73_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInf_uid74_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXI_uid75_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYI_uid76_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal ZeroTimesInf_uid77_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid78_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal concExc_uid79_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal excREnc_uid80_fpMulTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal oneFracRPostExc2_uid81_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracRPostExc_uid84_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExc_uid84_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExc_uid89_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExc_uid89_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal invExcRNaN_uid90_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExc_uid91_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal R_uid92_fpMulTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal topRangeX_uid102_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal topRangeY_uid103_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal aboveLeftX_uid108_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomY_uid117_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_uid121_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (14 downto 0);
signal rightBottomX_uid121_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal rightBottomY_uid122_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomY_uid122_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftX_uid123_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftX_uid123_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftY_uid124_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (14 downto 0);
signal aboveLeftY_uid124_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal n0_uid130_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid131_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid132_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid133_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid138_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid139_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid140_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid141_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid146_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid147_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n0_uid148_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid149_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_reset : std_logic;
signal sm0_uid160_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_reset : std_logic;
signal sm0_uid161_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_reset : std_logic;
signal sm1_uid162_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_reset : std_logic;
signal sm0_uid163_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_reset : std_logic;
signal sm1_uid164_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1_uid169_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (18 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (37 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0_uid174_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (38 downto 0);
signal osig_uid175_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (35 downto 0);
signal osig_uid175_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (26 downto 0);
signal lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_c : STD_LOGIC_VECTOR (12 downto 0);
signal lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_c : STD_LOGIC_VECTOR (32 downto 0);
signal redist0_signR_uid48_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist1_expSum_uid44_fpMulTest_q_2_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist2_fracXIsZero_uid31_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist3_expXIsMax_uid30_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist4_excZ_y_uid29_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_fracXIsZero_uid17_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist6_expXIsMax_uid16_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist7_excZ_x_uid15_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
begin
-- frac_x_uid14_fpMulTest(BITSELECT,13)@0
frac_x_uid14_fpMulTest_b <= a(22 downto 0);
-- cstZeroWF_uid11_fpMulTest(CONSTANT,10)
cstZeroWF_uid11_fpMulTest_q <= "00000000000000000000000";
-- fracXIsZero_uid17_fpMulTest(LOGICAL,16)@0 + 1
fracXIsZero_uid17_fpMulTest_qi <= "1" WHEN cstZeroWF_uid11_fpMulTest_q = frac_x_uid14_fpMulTest_b ELSE "0";
fracXIsZero_uid17_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_qi, xout => fracXIsZero_uid17_fpMulTest_q, clk => clk, aclr => areset );
-- redist5_fracXIsZero_uid17_fpMulTest_q_2(DELAY,183)
redist5_fracXIsZero_uid17_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q, xout => redist5_fracXIsZero_uid17_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- cstAllOWE_uid10_fpMulTest(CONSTANT,9)
cstAllOWE_uid10_fpMulTest_q <= "11111111";
-- expX_uid6_fpMulTest(BITSELECT,5)@0
expX_uid6_fpMulTest_b <= a(30 downto 23);
-- expXIsMax_uid16_fpMulTest(LOGICAL,15)@0 + 1
expXIsMax_uid16_fpMulTest_qi <= "1" WHEN expX_uid6_fpMulTest_b = cstAllOWE_uid10_fpMulTest_q ELSE "0";
expXIsMax_uid16_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid16_fpMulTest_qi, xout => expXIsMax_uid16_fpMulTest_q, clk => clk, aclr => areset );
-- redist6_expXIsMax_uid16_fpMulTest_q_2(DELAY,184)
redist6_expXIsMax_uid16_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q, xout => redist6_expXIsMax_uid16_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excI_x_uid19_fpMulTest(LOGICAL,18)@2
excI_x_uid19_fpMulTest_q <= redist6_expXIsMax_uid16_fpMulTest_q_2_q and redist5_fracXIsZero_uid17_fpMulTest_q_2_q;
-- cstAllZWE_uid12_fpMulTest(CONSTANT,11)
cstAllZWE_uid12_fpMulTest_q <= "00000000";
-- expY_uid7_fpMulTest(BITSELECT,6)@0
expY_uid7_fpMulTest_b <= b(30 downto 23);
-- excZ_y_uid29_fpMulTest(LOGICAL,28)@0 + 1
excZ_y_uid29_fpMulTest_qi <= "1" WHEN expY_uid7_fpMulTest_b = cstAllZWE_uid12_fpMulTest_q ELSE "0";
excZ_y_uid29_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid29_fpMulTest_qi, xout => excZ_y_uid29_fpMulTest_q, clk => clk, aclr => areset );
-- redist4_excZ_y_uid29_fpMulTest_q_2(DELAY,182)
redist4_excZ_y_uid29_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid29_fpMulTest_q, xout => redist4_excZ_y_uid29_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excYZAndExcXI_uid75_fpMulTest(LOGICAL,74)@2
excYZAndExcXI_uid75_fpMulTest_q <= redist4_excZ_y_uid29_fpMulTest_q_2_q and excI_x_uid19_fpMulTest_q;
-- frac_y_uid28_fpMulTest(BITSELECT,27)@0
frac_y_uid28_fpMulTest_b <= b(22 downto 0);
-- fracXIsZero_uid31_fpMulTest(LOGICAL,30)@0 + 1
fracXIsZero_uid31_fpMulTest_qi <= "1" WHEN cstZeroWF_uid11_fpMulTest_q = frac_y_uid28_fpMulTest_b ELSE "0";
fracXIsZero_uid31_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_qi, xout => fracXIsZero_uid31_fpMulTest_q, clk => clk, aclr => areset );
-- redist2_fracXIsZero_uid31_fpMulTest_q_2(DELAY,180)
redist2_fracXIsZero_uid31_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q, xout => redist2_fracXIsZero_uid31_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- expXIsMax_uid30_fpMulTest(LOGICAL,29)@0 + 1
expXIsMax_uid30_fpMulTest_qi <= "1" WHEN expY_uid7_fpMulTest_b = cstAllOWE_uid10_fpMulTest_q ELSE "0";
expXIsMax_uid30_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid30_fpMulTest_qi, xout => expXIsMax_uid30_fpMulTest_q, clk => clk, aclr => areset );
-- redist3_expXIsMax_uid30_fpMulTest_q_2(DELAY,181)
redist3_expXIsMax_uid30_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q, xout => redist3_expXIsMax_uid30_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excI_y_uid33_fpMulTest(LOGICAL,32)@2
excI_y_uid33_fpMulTest_q <= redist3_expXIsMax_uid30_fpMulTest_q_2_q and redist2_fracXIsZero_uid31_fpMulTest_q_2_q;
-- excZ_x_uid15_fpMulTest(LOGICAL,14)@0 + 1
excZ_x_uid15_fpMulTest_qi <= "1" WHEN expX_uid6_fpMulTest_b = cstAllZWE_uid12_fpMulTest_q ELSE "0";
excZ_x_uid15_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid15_fpMulTest_qi, xout => excZ_x_uid15_fpMulTest_q, clk => clk, aclr => areset );
-- redist7_excZ_x_uid15_fpMulTest_q_2(DELAY,185)
redist7_excZ_x_uid15_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid15_fpMulTest_q, xout => redist7_excZ_x_uid15_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excXZAndExcYI_uid76_fpMulTest(LOGICAL,75)@2
excXZAndExcYI_uid76_fpMulTest_q <= redist7_excZ_x_uid15_fpMulTest_q_2_q and excI_y_uid33_fpMulTest_q;
-- ZeroTimesInf_uid77_fpMulTest(LOGICAL,76)@2
ZeroTimesInf_uid77_fpMulTest_q <= excXZAndExcYI_uid76_fpMulTest_q or excYZAndExcXI_uid75_fpMulTest_q;
-- fracXIsNotZero_uid32_fpMulTest(LOGICAL,31)@2
fracXIsNotZero_uid32_fpMulTest_q <= not (redist2_fracXIsZero_uid31_fpMulTest_q_2_q);
-- excN_y_uid34_fpMulTest(LOGICAL,33)@2
excN_y_uid34_fpMulTest_q <= redist3_expXIsMax_uid30_fpMulTest_q_2_q and fracXIsNotZero_uid32_fpMulTest_q;
-- fracXIsNotZero_uid18_fpMulTest(LOGICAL,17)@2
fracXIsNotZero_uid18_fpMulTest_q <= not (redist5_fracXIsZero_uid17_fpMulTest_q_2_q);
-- excN_x_uid20_fpMulTest(LOGICAL,19)@2
excN_x_uid20_fpMulTest_q <= redist6_expXIsMax_uid16_fpMulTest_q_2_q and fracXIsNotZero_uid18_fpMulTest_q;
-- excRNaN_uid78_fpMulTest(LOGICAL,77)@2
excRNaN_uid78_fpMulTest_q <= excN_x_uid20_fpMulTest_q or excN_y_uid34_fpMulTest_q or ZeroTimesInf_uid77_fpMulTest_q;
-- invExcRNaN_uid90_fpMulTest(LOGICAL,89)@2
invExcRNaN_uid90_fpMulTest_q <= not (excRNaN_uid78_fpMulTest_q);
-- signY_uid9_fpMulTest(BITSELECT,8)@0
signY_uid9_fpMulTest_b <= STD_LOGIC_VECTOR(b(31 downto 31));
-- signX_uid8_fpMulTest(BITSELECT,7)@0
signX_uid8_fpMulTest_b <= STD_LOGIC_VECTOR(a(31 downto 31));
-- signR_uid48_fpMulTest(LOGICAL,47)@0 + 1
signR_uid48_fpMulTest_qi <= signX_uid8_fpMulTest_b xor signY_uid9_fpMulTest_b;
signR_uid48_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid48_fpMulTest_qi, xout => signR_uid48_fpMulTest_q, clk => clk, aclr => areset );
-- redist0_signR_uid48_fpMulTest_q_2(DELAY,178)
redist0_signR_uid48_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid48_fpMulTest_q, xout => redist0_signR_uid48_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- signRPostExc_uid91_fpMulTest(LOGICAL,90)@2
signRPostExc_uid91_fpMulTest_q <= redist0_signR_uid48_fpMulTest_q_2_q and invExcRNaN_uid90_fpMulTest_q;
-- GND(CONSTANT,0)
GND_q <= "0";
-- ofracY_uid43_fpMulTest(BITJOIN,42)@0
ofracY_uid43_fpMulTest_q <= VCC_q & frac_y_uid28_fpMulTest_b;
-- aboveLeftY_uid124_prod_uid47_fpMulTest(BITSELECT,123)@0
aboveLeftY_uid124_prod_uid47_fpMulTest_in <= ofracY_uid43_fpMulTest_q(14 downto 0);
aboveLeftY_uid124_prod_uid47_fpMulTest_b <= aboveLeftY_uid124_prod_uid47_fpMulTest_in(14 downto 10);
-- n1_uid133_prod_uid47_fpMulTest(BITSELECT,132)@0
n1_uid133_prod_uid47_fpMulTest_b <= aboveLeftY_uid124_prod_uid47_fpMulTest_b(4 downto 1);
-- n1_uid141_prod_uid47_fpMulTest(BITSELECT,140)@0
n1_uid141_prod_uid47_fpMulTest_b <= n1_uid133_prod_uid47_fpMulTest_b(3 downto 1);
-- n1_uid149_prod_uid47_fpMulTest(BITSELECT,148)@0
n1_uid149_prod_uid47_fpMulTest_b <= n1_uid141_prod_uid47_fpMulTest_b(2 downto 1);
-- ofracX_uid40_fpMulTest(BITJOIN,39)@0
ofracX_uid40_fpMulTest_q <= VCC_q & frac_x_uid14_fpMulTest_b;
-- aboveLeftX_uid123_prod_uid47_fpMulTest(BITSELECT,122)@0
aboveLeftX_uid123_prod_uid47_fpMulTest_in <= ofracX_uid40_fpMulTest_q(5 downto 0);
aboveLeftX_uid123_prod_uid47_fpMulTest_b <= aboveLeftX_uid123_prod_uid47_fpMulTest_in(5 downto 1);
-- n0_uid132_prod_uid47_fpMulTest(BITSELECT,131)@0
n0_uid132_prod_uid47_fpMulTest_b <= aboveLeftX_uid123_prod_uid47_fpMulTest_b(4 downto 1);
-- n0_uid140_prod_uid47_fpMulTest(BITSELECT,139)@0
n0_uid140_prod_uid47_fpMulTest_b <= n0_uid132_prod_uid47_fpMulTest_b(3 downto 1);
-- n0_uid148_prod_uid47_fpMulTest(BITSELECT,147)@0
n0_uid148_prod_uid47_fpMulTest_b <= n0_uid140_prod_uid47_fpMulTest_b(2 downto 1);
-- sm1_uid164_prod_uid47_fpMulTest(MULT,163)@0 + 2
sm1_uid164_prod_uid47_fpMulTest_a0 <= n0_uid148_prod_uid47_fpMulTest_b;
sm1_uid164_prod_uid47_fpMulTest_b0 <= n1_uid149_prod_uid47_fpMulTest_b;
sm1_uid164_prod_uid47_fpMulTest_reset <= areset;
sm1_uid164_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid164_prod_uid47_fpMulTest_a0,
datab => sm1_uid164_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm1_uid164_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm1_uid164_prod_uid47_fpMulTest_s1
);
sm1_uid164_prod_uid47_fpMulTest_q <= sm1_uid164_prod_uid47_fpMulTest_s1;
-- lev3_a0high_uid173_prod_uid47_fpMulTest(ADD,172)@2
lev3_a0high_uid173_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_c);
lev3_a0high_uid173_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000" & sm1_uid164_prod_uid47_fpMulTest_q);
lev3_a0high_uid173_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev3_a0high_uid173_prod_uid47_fpMulTest_a) + UNSIGNED(lev3_a0high_uid173_prod_uid47_fpMulTest_b));
lev3_a0high_uid173_prod_uid47_fpMulTest_q <= lev3_a0high_uid173_prod_uid47_fpMulTest_o(33 downto 0);
-- rightBottomY_uid122_prod_uid47_fpMulTest(BITSELECT,121)@0
rightBottomY_uid122_prod_uid47_fpMulTest_in <= ofracY_uid43_fpMulTest_q(5 downto 0);
rightBottomY_uid122_prod_uid47_fpMulTest_b <= rightBottomY_uid122_prod_uid47_fpMulTest_in(5 downto 1);
-- n1_uid131_prod_uid47_fpMulTest(BITSELECT,130)@0
n1_uid131_prod_uid47_fpMulTest_b <= rightBottomY_uid122_prod_uid47_fpMulTest_b(4 downto 1);
-- n1_uid139_prod_uid47_fpMulTest(BITSELECT,138)@0
n1_uid139_prod_uid47_fpMulTest_b <= n1_uid131_prod_uid47_fpMulTest_b(3 downto 1);
-- n1_uid147_prod_uid47_fpMulTest(BITSELECT,146)@0
n1_uid147_prod_uid47_fpMulTest_b <= n1_uid139_prod_uid47_fpMulTest_b(2 downto 1);
-- rightBottomX_uid121_prod_uid47_fpMulTest(BITSELECT,120)@0
rightBottomX_uid121_prod_uid47_fpMulTest_in <= ofracX_uid40_fpMulTest_q(14 downto 0);
rightBottomX_uid121_prod_uid47_fpMulTest_b <= rightBottomX_uid121_prod_uid47_fpMulTest_in(14 downto 10);
-- n0_uid130_prod_uid47_fpMulTest(BITSELECT,129)@0
n0_uid130_prod_uid47_fpMulTest_b <= rightBottomX_uid121_prod_uid47_fpMulTest_b(4 downto 1);
-- n0_uid138_prod_uid47_fpMulTest(BITSELECT,137)@0
n0_uid138_prod_uid47_fpMulTest_b <= n0_uid130_prod_uid47_fpMulTest_b(3 downto 1);
-- n0_uid146_prod_uid47_fpMulTest(BITSELECT,145)@0
n0_uid146_prod_uid47_fpMulTest_b <= n0_uid138_prod_uid47_fpMulTest_b(2 downto 1);
-- sm0_uid163_prod_uid47_fpMulTest(MULT,162)@0 + 2
sm0_uid163_prod_uid47_fpMulTest_a0 <= n0_uid146_prod_uid47_fpMulTest_b;
sm0_uid163_prod_uid47_fpMulTest_b0 <= n1_uid147_prod_uid47_fpMulTest_b;
sm0_uid163_prod_uid47_fpMulTest_reset <= areset;
sm0_uid163_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid163_prod_uid47_fpMulTest_a0,
datab => sm0_uid163_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm0_uid163_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm0_uid163_prod_uid47_fpMulTest_s1
);
sm0_uid163_prod_uid47_fpMulTest_q <= sm0_uid163_prod_uid47_fpMulTest_s1;
-- lev1_a1high_uid168_prod_uid47_fpMulTest(ADD,167)@2
lev1_a1high_uid168_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_c);
lev1_a1high_uid168_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("0000000000" & sm0_uid163_prod_uid47_fpMulTest_q);
lev1_a1high_uid168_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a1high_uid168_prod_uid47_fpMulTest_a) + UNSIGNED(lev1_a1high_uid168_prod_uid47_fpMulTest_b));
lev1_a1high_uid168_prod_uid47_fpMulTest_q <= lev1_a1high_uid168_prod_uid47_fpMulTest_o(13 downto 0);
-- rightBottomY_uid117_prod_uid47_fpMulTest(BITSELECT,116)@0
rightBottomY_uid117_prod_uid47_fpMulTest_b <= ofracY_uid43_fpMulTest_q(23 downto 15);
-- rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest(BITSELECT,113)@0
rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_in <= ofracX_uid40_fpMulTest_q(5 downto 0);
rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_b <= rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_in(5 downto 0);
-- aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest(CONSTANT,108)
aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q <= "000";
-- rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest(BITJOIN,114)@0
rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest_q <= rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_b & aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q;
-- sm1_uid162_prod_uid47_fpMulTest(MULT,161)@0 + 2
sm1_uid162_prod_uid47_fpMulTest_a0 <= rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest_q;
sm1_uid162_prod_uid47_fpMulTest_b0 <= rightBottomY_uid117_prod_uid47_fpMulTest_b;
sm1_uid162_prod_uid47_fpMulTest_reset <= areset;
sm1_uid162_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid162_prod_uid47_fpMulTest_a0,
datab => sm1_uid162_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm1_uid162_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm1_uid162_prod_uid47_fpMulTest_s1
);
sm1_uid162_prod_uid47_fpMulTest_q <= sm1_uid162_prod_uid47_fpMulTest_s1;
-- lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select(BITSELECT,176)@2
lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_b <= sm1_uid162_prod_uid47_fpMulTest_q(4 downto 0);
lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_c <= sm1_uid162_prod_uid47_fpMulTest_q(17 downto 5);
-- lev1_a1_uid169_prod_uid47_fpMulTest(BITJOIN,168)@2
lev1_a1_uid169_prod_uid47_fpMulTest_q <= lev1_a1high_uid168_prod_uid47_fpMulTest_q & lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_b;
-- aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest(BITSELECT,109)@0
aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_in <= ofracY_uid43_fpMulTest_q(5 downto 0);
aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_b <= aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_in(5 downto 0);
-- aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest(BITJOIN,110)@0
aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest_q <= aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_b & aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q;
-- aboveLeftX_uid108_prod_uid47_fpMulTest(BITSELECT,107)@0
aboveLeftX_uid108_prod_uid47_fpMulTest_b <= ofracX_uid40_fpMulTest_q(23 downto 15);
-- sm0_uid161_prod_uid47_fpMulTest(MULT,160)@0 + 2
sm0_uid161_prod_uid47_fpMulTest_a0 <= aboveLeftX_uid108_prod_uid47_fpMulTest_b;
sm0_uid161_prod_uid47_fpMulTest_b0 <= aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest_q;
sm0_uid161_prod_uid47_fpMulTest_reset <= areset;
sm0_uid161_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid161_prod_uid47_fpMulTest_a0,
datab => sm0_uid161_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm0_uid161_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm0_uid161_prod_uid47_fpMulTest_s1
);
sm0_uid161_prod_uid47_fpMulTest_q <= sm0_uid161_prod_uid47_fpMulTest_s1;
-- topRangeY_uid103_prod_uid47_fpMulTest(BITSELECT,102)@0
topRangeY_uid103_prod_uid47_fpMulTest_b <= ofracY_uid43_fpMulTest_q(23 downto 6);
-- topRangeX_uid102_prod_uid47_fpMulTest(BITSELECT,101)@0
topRangeX_uid102_prod_uid47_fpMulTest_b <= ofracX_uid40_fpMulTest_q(23 downto 6);
-- sm0_uid160_prod_uid47_fpMulTest(MULT,159)@0 + 2
sm0_uid160_prod_uid47_fpMulTest_a0 <= topRangeX_uid102_prod_uid47_fpMulTest_b;
sm0_uid160_prod_uid47_fpMulTest_b0 <= topRangeY_uid103_prod_uid47_fpMulTest_b;
sm0_uid160_prod_uid47_fpMulTest_reset <= areset;
sm0_uid160_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 36,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid160_prod_uid47_fpMulTest_a0,
datab => sm0_uid160_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm0_uid160_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm0_uid160_prod_uid47_fpMulTest_s1
);
sm0_uid160_prod_uid47_fpMulTest_q <= sm0_uid160_prod_uid47_fpMulTest_s1;
-- lev1_a0_uid165_prod_uid47_fpMulTest(ADD,164)@2
lev1_a0_uid165_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & sm0_uid160_prod_uid47_fpMulTest_q);
lev1_a0_uid165_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & sm0_uid161_prod_uid47_fpMulTest_q);
lev1_a0_uid165_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a0_uid165_prod_uid47_fpMulTest_a) + UNSIGNED(lev1_a0_uid165_prod_uid47_fpMulTest_b));
lev1_a0_uid165_prod_uid47_fpMulTest_q <= lev1_a0_uid165_prod_uid47_fpMulTest_o(36 downto 0);
-- lev2_a0_uid170_prod_uid47_fpMulTest(ADD,169)@2
lev2_a0_uid170_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & lev1_a0_uid165_prod_uid47_fpMulTest_q);
lev2_a0_uid170_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & lev1_a1_uid169_prod_uid47_fpMulTest_q);
lev2_a0_uid170_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev2_a0_uid170_prod_uid47_fpMulTest_a) + UNSIGNED(lev2_a0_uid170_prod_uid47_fpMulTest_b));
lev2_a0_uid170_prod_uid47_fpMulTest_q <= lev2_a0_uid170_prod_uid47_fpMulTest_o(37 downto 0);
-- lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select(BITSELECT,177)@2
lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_b <= lev2_a0_uid170_prod_uid47_fpMulTest_q(4 downto 0);
lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_c <= lev2_a0_uid170_prod_uid47_fpMulTest_q(37 downto 5);
-- lev3_a0_uid174_prod_uid47_fpMulTest(BITJOIN,173)@2
lev3_a0_uid174_prod_uid47_fpMulTest_q <= lev3_a0high_uid173_prod_uid47_fpMulTest_q & lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_b;
-- osig_uid175_prod_uid47_fpMulTest(BITSELECT,174)@2
osig_uid175_prod_uid47_fpMulTest_in <= lev3_a0_uid174_prod_uid47_fpMulTest_q(35 downto 0);
osig_uid175_prod_uid47_fpMulTest_b <= osig_uid175_prod_uid47_fpMulTest_in(35 downto 9);
-- normalizeBit_uid49_fpMulTest(BITSELECT,48)@2
normalizeBit_uid49_fpMulTest_b <= STD_LOGIC_VECTOR(osig_uid175_prod_uid47_fpMulTest_b(26 downto 26));
-- roundBitAndNormalizationOp_uid57_fpMulTest(BITJOIN,56)@2
roundBitAndNormalizationOp_uid57_fpMulTest_q <= GND_q & normalizeBit_uid49_fpMulTest_b & cstZeroWF_uid11_fpMulTest_q & VCC_q;
-- biasInc_uid45_fpMulTest(CONSTANT,44)
biasInc_uid45_fpMulTest_q <= "0001111111";
-- expSum_uid44_fpMulTest(ADD,43)@0 + 1
expSum_uid44_fpMulTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpMulTest_b);
expSum_uid44_fpMulTest_b <= STD_LOGIC_VECTOR("0" & expY_uid7_fpMulTest_b);
expSum_uid44_fpMulTest_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid44_fpMulTest_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
expSum_uid44_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid44_fpMulTest_a) + UNSIGNED(expSum_uid44_fpMulTest_b));
END IF;
END PROCESS;
expSum_uid44_fpMulTest_q <= expSum_uid44_fpMulTest_o(8 downto 0);
-- redist1_expSum_uid44_fpMulTest_q_2(DELAY,179)
redist1_expSum_uid44_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 9, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expSum_uid44_fpMulTest_q, xout => redist1_expSum_uid44_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- expSumMBias_uid46_fpMulTest(SUB,45)@2
expSumMBias_uid46_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00" & redist1_expSum_uid44_fpMulTest_q_2_q));
expSumMBias_uid46_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid45_fpMulTest_q(9)) & biasInc_uid45_fpMulTest_q));
expSumMBias_uid46_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid46_fpMulTest_a) - SIGNED(expSumMBias_uid46_fpMulTest_b));
expSumMBias_uid46_fpMulTest_q <= expSumMBias_uid46_fpMulTest_o(10 downto 0);
-- fracRPostNormHigh_uid51_fpMulTest(BITSELECT,50)@2
fracRPostNormHigh_uid51_fpMulTest_in <= osig_uid175_prod_uid47_fpMulTest_b(25 downto 0);
fracRPostNormHigh_uid51_fpMulTest_b <= fracRPostNormHigh_uid51_fpMulTest_in(25 downto 2);
-- fracRPostNormLow_uid52_fpMulTest(BITSELECT,51)@2
fracRPostNormLow_uid52_fpMulTest_in <= osig_uid175_prod_uid47_fpMulTest_b(24 downto 0);
fracRPostNormLow_uid52_fpMulTest_b <= fracRPostNormLow_uid52_fpMulTest_in(24 downto 1);
-- fracRPostNorm_uid53_fpMulTest(MUX,52)@2
fracRPostNorm_uid53_fpMulTest_s <= normalizeBit_uid49_fpMulTest_b;
fracRPostNorm_uid53_fpMulTest_combproc: PROCESS (fracRPostNorm_uid53_fpMulTest_s, fracRPostNormLow_uid52_fpMulTest_b, fracRPostNormHigh_uid51_fpMulTest_b)
BEGIN
CASE (fracRPostNorm_uid53_fpMulTest_s) IS
WHEN "0" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormLow_uid52_fpMulTest_b;
WHEN "1" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormHigh_uid51_fpMulTest_b;
WHEN OTHERS => fracRPostNorm_uid53_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- expFracPreRound_uid55_fpMulTest(BITJOIN,54)@2
expFracPreRound_uid55_fpMulTest_q <= expSumMBias_uid46_fpMulTest_q & fracRPostNorm_uid53_fpMulTest_q;
-- expFracRPostRounding_uid58_fpMulTest(ADD,57)@2
expFracRPostRounding_uid58_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((36 downto 35 => expFracPreRound_uid55_fpMulTest_q(34)) & expFracPreRound_uid55_fpMulTest_q));
expFracRPostRounding_uid58_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000000000" & roundBitAndNormalizationOp_uid57_fpMulTest_q));
expFracRPostRounding_uid58_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid58_fpMulTest_a) + SIGNED(expFracRPostRounding_uid58_fpMulTest_b));
expFracRPostRounding_uid58_fpMulTest_q <= expFracRPostRounding_uid58_fpMulTest_o(35 downto 0);
-- expRPreExcExt_uid60_fpMulTest(BITSELECT,59)@2
expRPreExcExt_uid60_fpMulTest_b <= STD_LOGIC_VECTOR(expFracRPostRounding_uid58_fpMulTest_q(35 downto 24));
-- expRPreExc_uid61_fpMulTest(BITSELECT,60)@2
expRPreExc_uid61_fpMulTest_in <= expRPreExcExt_uid60_fpMulTest_b(7 downto 0);
expRPreExc_uid61_fpMulTest_b <= expRPreExc_uid61_fpMulTest_in(7 downto 0);
-- expOvf_uid64_fpMulTest(COMPARE,63)@2
expOvf_uid64_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => expRPreExcExt_uid60_fpMulTest_b(11)) & expRPreExcExt_uid60_fpMulTest_b));
expOvf_uid64_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00000" & cstAllOWE_uid10_fpMulTest_q));
expOvf_uid64_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid64_fpMulTest_a) - SIGNED(expOvf_uid64_fpMulTest_b));
expOvf_uid64_fpMulTest_n(0) <= not (expOvf_uid64_fpMulTest_o(13));
-- invExpXIsMax_uid35_fpMulTest(LOGICAL,34)@2
invExpXIsMax_uid35_fpMulTest_q <= not (redist3_expXIsMax_uid30_fpMulTest_q_2_q);
-- InvExpXIsZero_uid36_fpMulTest(LOGICAL,35)@2
InvExpXIsZero_uid36_fpMulTest_q <= not (redist4_excZ_y_uid29_fpMulTest_q_2_q);
-- excR_y_uid37_fpMulTest(LOGICAL,36)@2
excR_y_uid37_fpMulTest_q <= InvExpXIsZero_uid36_fpMulTest_q and invExpXIsMax_uid35_fpMulTest_q;
-- invExpXIsMax_uid21_fpMulTest(LOGICAL,20)@2
invExpXIsMax_uid21_fpMulTest_q <= not (redist6_expXIsMax_uid16_fpMulTest_q_2_q);
-- InvExpXIsZero_uid22_fpMulTest(LOGICAL,21)@2
InvExpXIsZero_uid22_fpMulTest_q <= not (redist7_excZ_x_uid15_fpMulTest_q_2_q);
-- excR_x_uid23_fpMulTest(LOGICAL,22)@2
excR_x_uid23_fpMulTest_q <= InvExpXIsZero_uid22_fpMulTest_q and invExpXIsMax_uid21_fpMulTest_q;
-- ExcROvfAndInReg_uid73_fpMulTest(LOGICAL,72)@2
ExcROvfAndInReg_uid73_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expOvf_uid64_fpMulTest_n;
-- excYRAndExcXI_uid72_fpMulTest(LOGICAL,71)@2
excYRAndExcXI_uid72_fpMulTest_q <= excR_y_uid37_fpMulTest_q and excI_x_uid19_fpMulTest_q;
-- excXRAndExcYI_uid71_fpMulTest(LOGICAL,70)@2
excXRAndExcYI_uid71_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excI_y_uid33_fpMulTest_q;
-- excXIAndExcYI_uid70_fpMulTest(LOGICAL,69)@2
excXIAndExcYI_uid70_fpMulTest_q <= excI_x_uid19_fpMulTest_q and excI_y_uid33_fpMulTest_q;
-- excRInf_uid74_fpMulTest(LOGICAL,73)@2
excRInf_uid74_fpMulTest_q <= excXIAndExcYI_uid70_fpMulTest_q or excXRAndExcYI_uid71_fpMulTest_q or excYRAndExcXI_uid72_fpMulTest_q or ExcROvfAndInReg_uid73_fpMulTest_q;
-- expUdf_uid62_fpMulTest(COMPARE,61)@2
expUdf_uid62_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "000000000000" & GND_q));
expUdf_uid62_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => expRPreExcExt_uid60_fpMulTest_b(11)) & expRPreExcExt_uid60_fpMulTest_b));
expUdf_uid62_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid62_fpMulTest_a) - SIGNED(expUdf_uid62_fpMulTest_b));
expUdf_uid62_fpMulTest_n(0) <= not (expUdf_uid62_fpMulTest_o(13));
-- excZC3_uid68_fpMulTest(LOGICAL,67)@2
excZC3_uid68_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expUdf_uid62_fpMulTest_n;
-- excYZAndExcXR_uid67_fpMulTest(LOGICAL,66)@2
excYZAndExcXR_uid67_fpMulTest_q <= redist4_excZ_y_uid29_fpMulTest_q_2_q and excR_x_uid23_fpMulTest_q;
-- excXZAndExcYR_uid66_fpMulTest(LOGICAL,65)@2
excXZAndExcYR_uid66_fpMulTest_q <= redist7_excZ_x_uid15_fpMulTest_q_2_q and excR_y_uid37_fpMulTest_q;
-- excXZAndExcYZ_uid65_fpMulTest(LOGICAL,64)@2
excXZAndExcYZ_uid65_fpMulTest_q <= redist7_excZ_x_uid15_fpMulTest_q_2_q and redist4_excZ_y_uid29_fpMulTest_q_2_q;
-- excRZero_uid69_fpMulTest(LOGICAL,68)@2
excRZero_uid69_fpMulTest_q <= excXZAndExcYZ_uid65_fpMulTest_q or excXZAndExcYR_uid66_fpMulTest_q or excYZAndExcXR_uid67_fpMulTest_q or excZC3_uid68_fpMulTest_q;
-- concExc_uid79_fpMulTest(BITJOIN,78)@2
concExc_uid79_fpMulTest_q <= excRNaN_uid78_fpMulTest_q & excRInf_uid74_fpMulTest_q & excRZero_uid69_fpMulTest_q;
-- excREnc_uid80_fpMulTest(LOOKUP,79)@2
excREnc_uid80_fpMulTest_combproc: PROCESS (concExc_uid79_fpMulTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExc_uid79_fpMulTest_q) IS
WHEN "000" => excREnc_uid80_fpMulTest_q <= "01";
WHEN "001" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "010" => excREnc_uid80_fpMulTest_q <= "10";
WHEN "011" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "100" => excREnc_uid80_fpMulTest_q <= "11";
WHEN "101" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "110" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "111" => excREnc_uid80_fpMulTest_q <= "00";
WHEN OTHERS => -- unreachable
excREnc_uid80_fpMulTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExc_uid89_fpMulTest(MUX,88)@2
expRPostExc_uid89_fpMulTest_s <= excREnc_uid80_fpMulTest_q;
expRPostExc_uid89_fpMulTest_combproc: PROCESS (expRPostExc_uid89_fpMulTest_s, cstAllZWE_uid12_fpMulTest_q, expRPreExc_uid61_fpMulTest_b, cstAllOWE_uid10_fpMulTest_q)
BEGIN
CASE (expRPostExc_uid89_fpMulTest_s) IS
WHEN "00" => expRPostExc_uid89_fpMulTest_q <= cstAllZWE_uid12_fpMulTest_q;
WHEN "01" => expRPostExc_uid89_fpMulTest_q <= expRPreExc_uid61_fpMulTest_b;
WHEN "10" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
WHEN "11" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
WHEN OTHERS => expRPostExc_uid89_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- oneFracRPostExc2_uid81_fpMulTest(CONSTANT,80)
oneFracRPostExc2_uid81_fpMulTest_q <= "00000000000000000000001";
-- fracRPreExc_uid59_fpMulTest(BITSELECT,58)@2
fracRPreExc_uid59_fpMulTest_in <= expFracRPostRounding_uid58_fpMulTest_q(23 downto 0);
fracRPreExc_uid59_fpMulTest_b <= fracRPreExc_uid59_fpMulTest_in(23 downto 1);
-- fracRPostExc_uid84_fpMulTest(MUX,83)@2
fracRPostExc_uid84_fpMulTest_s <= excREnc_uid80_fpMulTest_q;
fracRPostExc_uid84_fpMulTest_combproc: PROCESS (fracRPostExc_uid84_fpMulTest_s, cstZeroWF_uid11_fpMulTest_q, fracRPreExc_uid59_fpMulTest_b, oneFracRPostExc2_uid81_fpMulTest_q)
BEGIN
CASE (fracRPostExc_uid84_fpMulTest_s) IS
WHEN "00" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
WHEN "01" => fracRPostExc_uid84_fpMulTest_q <= fracRPreExc_uid59_fpMulTest_b;
WHEN "10" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
WHEN "11" => fracRPostExc_uid84_fpMulTest_q <= oneFracRPostExc2_uid81_fpMulTest_q;
WHEN OTHERS => fracRPostExc_uid84_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- R_uid92_fpMulTest(BITJOIN,91)@2
R_uid92_fpMulTest_q <= signRPostExc_uid91_fpMulTest_q & expRPostExc_uid89_fpMulTest_q & fracRPostExc_uid84_fpMulTest_q;
-- xOut(GPOUT,4)@2
q <= R_uid92_fpMulTest_q;
END normal;
|
mit
|
ba59b74331232564c1e967e73b0d1d4e
| 0.706368 | 3.185815 | false | true | false | false |
lnls-dig/bpm-gw
|
hdl/modules/machine/sirius_sr_250M/dds_sin_lut.vhd
| 1 | 2,440 |
-------------------------------------------------------------------------------
-- Title : Vivadi DDS sin lut for SIRIUS 130M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_sin_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-04-15
-- Last update: 2016-04-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Temporary sine lut for SIRIUS machine with 130M ADC generated
-- through Vivado.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-15 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
-------------------------------------------------------------------------------
entity dds_sin_lut is
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end entity dds_sin_lut;
architecture str of dds_sin_lut is
component generic_rom
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
begin
cmp_sin_lut_sirius_50_191_1 : generic_rom
generic map (
g_data_width => 16,
g_size => 191,
g_init_file => "sin_lut_sirius_50_191.mif",
g_fail_if_file_not_found => true
)
port map (
rst_n_i => '1',
clk_i => clka,
a_i => addra,
q_o => douta
);
end architecture str;
|
lgpl-3.0
|
4799624fe32a50d31852c5620f4f13b9
| 0.391393 | 4.428312 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/Gray_Binarization_GN.vhd
| 2 | 10,796 |
-- Gray_Binarization_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN is
port (
Avalon_ST_Source_valid : out std_logic; -- Avalon_ST_Source_valid.wire
Avalon_ST_Sink_valid : in std_logic := '0'; -- Avalon_ST_Sink_valid.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset_n
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => '0'); -- Avalon_MM_Slave_address.wire
Avalon_ST_Sink_startofpacket : in std_logic := '0'; -- Avalon_ST_Sink_startofpacket.wire
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => '0'); -- Avalon_ST_Sink_data.wire
Avalon_ST_Source_endofpacket : out std_logic; -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Source_ready : in std_logic := '0'; -- Avalon_ST_Source_ready.wire
Avalon_ST_Sink_ready : out std_logic; -- Avalon_ST_Sink_ready.wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- Avalon_ST_Source_data.wire
Avalon_ST_Sink_endofpacket : in std_logic := '0'; -- Avalon_ST_Sink_endofpacket.wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Source_startofpacket : out std_logic; -- Avalon_ST_Source_startofpacket.wire
Avalon_MM_Slave_write : in std_logic := '0' -- Avalon_MM_Slave_write.wire
);
end entity Gray_Binarization_GN;
architecture rtl of Gray_Binarization_GN is
component alt_dspbuilder_clock_GNF343OQUJ is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNF343OQUJ;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_port_GN6TDLHAW6 is
port (
input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_port_GN6TDLHAW6;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is
port (
sop : in std_logic := 'X'; -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
data_out : out std_logic_vector(23 downto 0); -- wire
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
eop : in std_logic := 'X'; -- wire
write : in std_logic := 'X' -- wire
);
end component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module;
signal avalon_st_sink_valid_0_output_wire : std_logic; -- Avalon_ST_Sink_valid_0:output -> Avalon_ST_Source_valid_0:input
signal avalon_st_sink_startofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_startofpacket_0:output -> [Avalon_ST_Source_startofpacket_0:input, Gray_Binarization_Gray_Binarization_Module_0:sop]
signal avalon_st_sink_endofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_endofpacket_0:output -> [Avalon_ST_Source_endofpacket_0:input, Gray_Binarization_Gray_Binarization_Module_0:eop]
signal avalon_st_source_ready_0_output_wire : std_logic; -- Avalon_ST_Source_ready_0:output -> Avalon_ST_Sink_ready_0:input
signal avalon_mm_slave_address_0_output_wire : std_logic_vector(1 downto 0); -- Avalon_MM_Slave_address_0:output -> Gray_Binarization_Gray_Binarization_Module_0:addr
signal avalon_mm_slave_write_0_output_wire : std_logic; -- Avalon_MM_Slave_write_0:output -> Gray_Binarization_Gray_Binarization_Module_0:write
signal avalon_mm_slave_writedata_0_output_wire : std_logic_vector(31 downto 0); -- Avalon_MM_Slave_writedata_0:output -> Gray_Binarization_Gray_Binarization_Module_0:writedata
signal avalon_st_sink_data_0_output_wire : std_logic_vector(23 downto 0); -- Avalon_ST_Sink_data_0:output -> Gray_Binarization_Gray_Binarization_Module_0:data_in
signal gray_binarization_gray_binarization_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Gray_Binarization_Gray_Binarization_Module_0:data_out -> Avalon_ST_Source_data_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> Gray_Binarization_Gray_Binarization_Module_0:aclr
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> Gray_Binarization_Gray_Binarization_Module_0:Clock
begin
clock_0 : component alt_dspbuilder_clock_GNF343OQUJ
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr_n => aclr -- .reset_n
);
avalon_st_sink_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => Avalon_ST_Sink_data, -- input.wire
output => avalon_st_sink_data_0_output_wire -- output.wire
);
avalon_st_sink_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_endofpacket, -- input.wire
output => avalon_st_sink_endofpacket_0_output_wire -- output.wire
);
avalon_mm_slave_address_0 : component alt_dspbuilder_port_GN6TDLHAW6
port map (
input => Avalon_MM_Slave_address, -- input.wire
output => avalon_mm_slave_address_0_output_wire -- output.wire
);
avalon_mm_slave_writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => Avalon_MM_Slave_writedata, -- input.wire
output => avalon_mm_slave_writedata_0_output_wire -- output.wire
);
avalon_st_source_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_valid_0_output_wire, -- input.wire
output => Avalon_ST_Source_valid -- output.wire
);
avalon_st_sink_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_valid, -- input.wire
output => avalon_st_sink_valid_0_output_wire -- output.wire
);
avalon_st_source_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_endofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_endofpacket -- output.wire
);
avalon_st_source_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_startofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_startofpacket -- output.wire
);
gray_binarization_gray_binarization_module_0 : component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module
port map (
sop => avalon_st_sink_startofpacket_0_output_wire, -- sop.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
data_in => avalon_st_sink_data_0_output_wire, -- data_in.wire
data_out => gray_binarization_gray_binarization_module_0_data_out_wire, -- data_out.wire
writedata => avalon_mm_slave_writedata_0_output_wire, -- writedata.wire
addr => avalon_mm_slave_address_0_output_wire, -- addr.wire
eop => avalon_st_sink_endofpacket_0_output_wire, -- eop.wire
write => avalon_mm_slave_write_0_output_wire -- write.wire
);
avalon_st_source_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Source_ready, -- input.wire
output => avalon_st_source_ready_0_output_wire -- output.wire
);
avalon_mm_slave_write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_MM_Slave_write, -- input.wire
output => avalon_mm_slave_write_0_output_wire -- output.wire
);
avalon_st_sink_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_source_ready_0_output_wire, -- input.wire
output => Avalon_ST_Sink_ready -- output.wire
);
avalon_st_sink_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_startofpacket, -- input.wire
output => avalon_st_sink_startofpacket_0_output_wire -- output.wire
);
avalon_st_source_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => gray_binarization_gray_binarization_module_0_data_out_wire, -- input.wire
output => Avalon_ST_Source_data -- output.wire
);
end architecture rtl; -- of Gray_Binarization_GN
|
mit
|
608e2b9f87d4eab07e8555653bb15ba7
| 0.575398 | 3.48708 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd
| 1 | 4,976 |
-------------------------------------------------------------------------------
-- Title : Machine parameters for Sirius with FMCPICO_1M ADC
-- Project :
-------------------------------------------------------------------------------
-- File : machine_pkg.vhd<pbpm_fmcpico1M>
-- Author : Lucas Russo
-- Company :
-- Created : 2017-03-20
-- Last update: 2017-03-20
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Machine parameters for Sirius with FMCPICO_1M ADC
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-03-20 1.0 lerwys Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package machine_pkg is
constant c_pos_calc_with_downconv : boolean := false;
constant c_pos_calc_adc_freq : real := 1.0e6;
constant c_pos_calc_input_width : natural := 32;
constant c_pos_calc_mixed_width : natural := 32;
constant c_pos_calc_adc_ratio : natural := 1;
-- DDS doesn't matter for FMCPICO_1M, as the measurement
-- is already on baseband. The DDS stage is bypassed
constant c_pos_calc_dds_width : natural := 16;
constant c_pos_calc_dds_points : natural := 65;
constant c_pos_calc_sin_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_sin.nif";
constant c_pos_calc_cos_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_cos.nif";
constant c_pos_calc_tbt_cic_delay : natural := 1;
constant c_pos_calc_tbt_cic_stages : natural := 1;
constant c_pos_calc_tbt_ratio : natural := 2;
constant c_pos_calc_tbt_decim_width : natural := 32;
constant c_pos_calc_fofb_cic_delay : natural := 1;
constant c_pos_calc_fofb_cic_stages : natural := 1;
constant c_pos_calc_fofb_ratio : natural := 10;
constant c_pos_calc_fofb_decim_width : natural := 32;
constant c_pos_calc_monit1_cic_delay : natural := 1;
constant c_pos_calc_monit1_cic_stages : natural := 1;
constant c_pos_calc_monit1_ratio : natural := 100; --ratio between fofb and monit 1
constant c_pos_calc_monit1_cic_ratio : natural := 8;
constant c_pos_calc_monit2_cic_delay : natural := 1;
constant c_pos_calc_monit2_cic_stages : natural := 1;
constant c_pos_calc_monit2_ratio : natural := 40; -- ratio between monit 1 and 2
constant c_pos_calc_monit2_cic_ratio : natural := 8;
constant c_pos_calc_monit_decim_width : natural := 32;
-- For now, we use the "cordic_ratio" to avoid changing
-- signal names. All of the other parameters are ignored.
constant c_pos_calc_tbt_cordic_stages : positive := 12;
constant c_pos_calc_tbt_cordic_iter_per_clk : positive := 3;
-- Rates for FMCPICO_1M are already pretty low. No need to CE
-- them, so we gain in latency.
constant c_pos_calc_tbt_cordic_ratio : positive := 1;
-- For now, we use the "cordic_ratio" to avoid changing
-- signal names. All of the other parameters are ignored.
constant c_pos_calc_fofb_cordic_stages : positive := 15;
constant c_pos_calc_fofb_cordic_iter_per_clk : positive := 3;
-- Rates for FMCPICO_1M are already pretty low. No need to CE
-- them, so we gain in latency.
constant c_pos_calc_fofb_cordic_ratio : positive := 1;
constant c_pos_calc_k_width : natural := 25;
constant c_pos_calc_offset_width : natural := 32;
constant c_pos_calc_IQ_width : natural := c_pos_calc_mixed_width;
constant c_pos_calc_k_sum : natural := 85e5;
constant c_pos_calc_k_x : natural := 85e5;
constant c_pos_calc_k_y : natural := 85e5;
end machine_pkg;
|
lgpl-3.0
|
65021b97d142a5e2f75d6180b6dd6ba2
| 0.560892 | 3.899687 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/Gray_Binarization.vhd
| 2 | 2,769 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Gray_Binarization is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end entity Gray_Binarization;
architecture rtl of Gray_Binarization is
component Gray_Binarization_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end component Gray_Binarization_GN;
begin
Gray_Binarization_GN_0: if true generate
inst_Gray_Binarization_GN_0: Gray_Binarization_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
|
mit
|
29da483135a1eeb6ca5ca63ada4e1c1b
| 0.740701 | 3.114736 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/machine/sirius_sr_130M/dds_sin_lut.vhd
| 1 | 2,440 |
-------------------------------------------------------------------------------
-- Title : Vivadi DDS sin lut for SIRIUS 130M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_sin_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-04-15
-- Last update: 2015-04-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Temporary sine lut for SIRIUS machine with 130M ADC generated
-- through Vivado.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-15 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
-------------------------------------------------------------------------------
entity dds_sin_lut is
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end entity dds_sin_lut;
architecture str of dds_sin_lut is
component generic_rom
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
begin
cmp_sin_lut_sirius_52_203_1 : generic_rom
generic map (
g_data_width => 16,
g_size => 203,
g_init_file => "sin_lut_sirius_52_203.mif",
g_fail_if_file_not_found => true
)
port map (
rst_n_i => '1',
clk_i => clka,
a_i => addra,
q_o => douta
);
end architecture str;
|
lgpl-3.0
|
08ea593cdb0181873cd3664c47cc0286
| 0.391393 | 4.428312 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/afc_v3/wb_trigger/sys_pll.vhd
| 1 | 7,822 |
-- MMCM_BASE : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the body of the design code. The instance name
-- declaration : (MMCM_BASE_inst) and/or the port declarations after the
-- code : "=>" declaration maybe changed to properly reference and
-- : connect this function to the design. All inputs and outputs
-- : must be connected.
-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.
-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity sys_pll is
generic(
-- 200 MHz input clock
g_clkin_period : real := 5.000;
g_divclk_divide : integer := 1;
g_clkbout_mult_f : integer := 5;
-- Reference jitter
g_ref_jitter : real := 0.010;
-- 100 MHz output clock
g_clk0_divide_f : integer := 10;
-- 200 MHz output clock
g_clk1_divide : integer := 5;
g_clk2_divide : integer := 6
);
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
clk2_o : out std_logic;
locked_o : out std_logic
);
end sys_pll;
architecture syn of sys_pll is
signal s_mmcm_fbin : std_logic;
signal s_mmcm_fbout : std_logic;
signal s_clk0 : std_logic;
signal s_clk1 : std_logic;
signal s_clk2 : std_logic;
begin
-- Clock PLL
cmp_sys_pll : PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => g_clkbout_mult_f, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => g_clkin_period,
CLKIN2_PERIOD => g_clkin_period,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => g_clk0_divide_f,
CLKOUT1_DIVIDE => g_clk1_divide,
CLKOUT2_DIVIDE => g_clk2_divide,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => g_divclk_divide, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => g_ref_jitter,
REF_JITTER2 => g_ref_jitter,
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => s_clk0, -- 1-bit output: CLKOUT0
CLKOUT1 => s_clk1, -- 1-bit output: CLKOUT1
CLKOUT2 => s_clk2, -- 1-bit output: CLKOUT2
CLKOUT3 => open, -- 1-bit output: CLKOUT3
CLKOUT4 => open, -- 1-bit output: CLKOUT4
CLKOUT5 => open, -- 1-bit output: CLKOUT5
-- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
DO => open, -- 16-bit output: DRP data
DRDY => open, -- 1-bit output: DRP ready
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => s_mmcm_fbout, -- 1-bit output: Feedback clock
LOCKED => locked_o, -- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clk_i, -- 1-bit input: Primary clock
CLKIN2 => '0', -- 1-bit input: Secondary clock
-- Control Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1', -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
PWRDWN => '0', -- 1-bit input: Power-down
RST => rst_i, -- 1-bit input: Reset
-- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
DADDR => (others => '0'), -- 7-bit input: DRP address
DCLK => '0', -- 1-bit input: DRP clock
DEN => '0', -- 1-bit input: DRP enable
DI => (others => '0'), -- 16-bit input: DRP data
DWE => '0', -- 1-bit input: DRP write enable
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => s_mmcm_fbin -- 1-bit input: Feedback clock
);
-- Global clock buffers for "cmp_mmcm" instance
cmp_clkf_bufg : BUFG
port map(
O => s_mmcm_fbin,
I => s_mmcm_fbout
);
cmp_clkout0_buf : BUFG
port map(
O => clk0_o,
I => s_clk0
);
cmp_clkout1_buf : BUFG
port map(
O => clk1_o,
I => s_clk1
);
cmp_clkout2_buf : BUFG
port map(
O => clk2_o,
I => s_clk2
);
end syn;
|
lgpl-3.0
|
996823425eb866c18243453e63136f06
| 0.42585 | 4.582308 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/systimer/systim.vhd
| 1 | 3,467 |
-- System timer for MARK-II
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity systim is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
intrq: out std_logic
);
end entity systim;
architecture systim_arch of systim is
signal counter: unsigned(23 downto 0);
--control register
signal control_reg: unsigned(24 downto 0);
signal top: unsigned(23 downto 0);
signal timeren: std_logic;
signal compare_match: std_logic;
--for bus interface
signal reg_sel: std_logic_vector(1 downto 0);
signal clear_from_write: std_logic; --clear the counter when value is writen to its register
begin
--this is core timer
process (clk, res, compare_match, clear_from_write)
variable cnt: unsigned(23 downto 0) := (others => '0');
begin
if(rising_edge(clk)) then
if (res = '1' or clear_from_write = '1' or compare_match = '1') then
cnt := (others => '0');
elsif(timeren = '1') then
cnt := cnt + 1;
end if;
end if;
counter <= cnt;
end process;
--comparator
process(top, counter) is begin
if(counter = top) then
compare_match <= '1';
else
compare_match <= '0';
end if;
end process;
--for interrupts
intrq <= compare_match;
--control
top <= control_reg(23 downto 0);
timeren <= control_reg(24);
-----------------
--bus interface
--chip select
process(address) is begin
if (unsigned(address) = BASE_ADDRESS) then
reg_sel <= "01"; -- control register
elsif (unsigned(address) = (BASE_ADDRESS + 1)) then
reg_sel <= "10"; -- counter
else
reg_sel <= "00";
end if;
end process;
--registers
process(clk, res, WR, data_mosi, reg_sel) is begin
if rising_edge(clk) then
if res = '1' then
control_reg <= (others => '0');
elsif (reg_sel = "01" and WR = '1') then
control_reg <= unsigned(data_mosi(24 downto 0));
end if;
end if;
end process;
--output from registers
data_miso <= "0000000" & std_logic_vector(control_reg) when (RD = '1' and reg_sel = "01") else
x"00" & std_logic_vector(counter) when (RD = '1' and reg_sel = "10") else (others => 'Z');
--generate signal when there is write acces to counter
process(WR, reg_sel) is begin
if(WR = '1' and reg_sel = "10") then
clear_from_write <= '1';
else
clear_from_write <= '0';
end if;
end process;
ack <= '1' when ((WR = '1' and reg_sel /= "00") or (RD = '1' and reg_sel /= "00")) else '0';
end architecture systim_arch;
|
mit
|
36dccfa9d0d54e968040380ce43fe744
| 0.531737 | 3.792123 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_n_to_1_ddr_s8_diff.vhd
| 1 | 9,467 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_n_to_1_ddr_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic DDR n:1 transmitter module
-- Takes in n bits of data and serialises this to 1 bit
-- data is transmitted LSB first
-- Parallel input word
-- DS, DS-1 ..... 1, 0
-- Serial output words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Data inversion can be accomplished via the TX_SWAP_MASK parameter if required
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_n_to_1_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclkp : in std_logic ; -- IO Clock network
txioclkn : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end serdes_n_to_1_ddr_s8_diff ;
architecture arch_serdes_n_to_1_ddr_s8_diff of serdes_n_to_1_ddr_s8_diff is
signal cascade_di : std_logic_vector(D-1 downto 0) ;
signal cascade_do : std_logic_vector(D-1 downto 0) ;
signal cascade_ti : std_logic_vector(D-1 downto 0) ;
signal cascade_to : std_logic_vector(D-1 downto 0) ;
signal mdataina : std_logic_vector(D*8 downto 0) ;
signal mdatainb : std_logic_vector(D*4 downto 0) ;
signal tx_data_out : std_logic_vector(D downto 0) ;
constant TX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
loop0 : for i in 0 to (D - 1) generate
io_clk_out : obufds port map (
O => dataout_p(i),
OB => dataout_n(i),
I => tx_data_out(i));
loop1 : if (S > 4) generate -- Two oserdes are needed
loop2 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdataina((8*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "DDR", -- <SDR>, DDR
DATA_RATE_OT => "DDR", -- <SDR>, DDR
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclkp,
CLK1 => txioclkn,
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+7),
D3 => mdataina((8*i)+6),
D2 => mdataina((8*i)+5),
D1 => mdataina((8*i)+4),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- Dummy input in Master
SHIFTIN2 => '1', -- Dummy input in Master
SHIFTIN3 => cascade_do(i), -- Cascade output D data from slave
SHIFTIN4 => cascade_to(i), -- Cascade output T data from slave
SHIFTOUT1 => cascade_di(i), -- Cascade input D data to slave
SHIFTOUT2 => cascade_ti(i), -- Cascade input T data to slave
SHIFTOUT3 => open, -- Dummy output in Master
SHIFTOUT4 => open) ; -- Dummy output in Master
oserdes_s : OSERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "DDR", -- <SDR>, DDR
DATA_RATE_OT => "DDR", -- <SDR>, DDR
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => open,
OCE => '1',
CLK0 => txioclkp,
CLK1 => txioclkn,
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdataina((8*i)+3),
D3 => mdataina((8*i)+2),
D2 => mdataina((8*i)+1),
D1 => mdataina((8*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => cascade_di(i), -- Cascade input D from Master
SHIFTIN2 => cascade_ti(i), -- Cascade input T from Master
SHIFTIN3 => '1', -- Dummy input in Slave
SHIFTIN4 => '1', -- Dummy input in Slave
SHIFTOUT1 => open, -- Dummy output in Slave
SHIFTOUT2 => open, -- Dummy output in Slave
SHIFTOUT3 => cascade_do(i), -- Cascade output D data to Master
SHIFTOUT4 => cascade_to(i)) ; -- Cascade output T data to Master
end generate ;
loop3 : if (S < 5) generate -- Only one oserdes needed
loop4 : for j in 0 to (S - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdatainb((4*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "DDR", -- <SDR>, DDR
DATA_RATE_OT => "DDR") -- <SDR>, DDR
-- SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
-- OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclkp,
CLK1 => txioclkn,
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => gclk,
D4 => mdatainb((4*i)+3),
D3 => mdatainb((4*i)+2),
D2 => mdatainb((4*i)+1),
D1 => mdatainb((4*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- No cascades needed
SHIFTIN2 => '1', -- No cascades needed
SHIFTIN3 => '1', -- No cascades needed
SHIFTIN4 => '1', -- No cascades needed
SHIFTOUT1 => open, -- No cascades needed
SHIFTOUT2 => open, -- No cascades needed
SHIFTOUT3 => open, -- No cascades needed
SHIFTOUT4 => open) ; -- No cascades needed
end generate ;
end generate ;
end arch_serdes_n_to_1_ddr_s8_diff ;
|
apache-2.0
|
76d692552fd3238db178c5d2ade362ec
| 0.592585 | 3.126486 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_position_calc/position_calc_core_pkg.vhd
| 1 | 3,384 |
------------------------------------------------------------------------------
-- Title : Wishbone FMC516 ADC Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-12-07
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: General definitions package for position calc core
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-12-07 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
package position_calc_core_pkg is
-------------------------------------------------------------------------------
-- Components Declaration
-------------------------------------------------------------------------------
component trigger2tag
generic (
g_delay_width : natural := 9;
g_tag_size : natural := 1
);
port (
fs_clk_i : in std_logic;
fs_rst_n_i : in std_logic;
-- Pulse programmable delay
pulse_dly_i : in std_logic_vector(g_delay_width-1 downto 0);
-- Pulse input
pulse_i : in std_logic;
-- Output counter
tag_o : out std_logic
);
end component;
--------------------------------------------------------------------
-- SDB Devices Structures
--------------------------------------------------------------------
constant c_xwb_bpm_swap_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"12897592",
version => x"00000001",
date => x"20130703",
name => "LNLS_BPM_SWAP ")));
constant c_xwb_pos_calc_core_regs_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000003FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"1bafbf1e",
version => x"00000001",
date => x"20130703",
name => "LNLS_POS_CALC_REGS ")));
end position_calc_core_pkg;
|
lgpl-3.0
|
00d84367f3ba5752be2089f0379fee1f
| 0.388002 | 4.8 | false | false | false | false |
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