repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
123gmax/Digital-Lab
|
AES128/Architecture1_Pipeline/keyExpansion_tb.vhd
| 1 | 3,241 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/21/2015 09:18:48 PM
-- Design Name:
-- Module Name: keyExpansion_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity keyExpansion_tb is
end keyExpansion_tb;
architecture Behavioral of keyExpansion_tb is
signal CLK : STD_LOGIC := '0';
signal RESET : STD_LOGIC := '0';
signal START : STD_LOGIC := '0';
signal cipherKey : STD_LOGIC_VECTOR (127 downto 0):= (others => '0');
signal DONE : STD_LOGIC := '0';
signal IDLE : STD_LOGIC := '0';
signal MUTATING : STD_LOGIC := '0';
signal expandedKey : STD_LOGIC_VECTOR (1407 downto 0) := (others => '0');
constant clk_period : time := 2ns;
component keyExpansion
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
START : in STD_LOGIC;
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
DONE : out STD_LOGIC;
IDLE : out STD_LOGIC;
MUTATING : out STD_LOGIC;
expandedKey : out STD_LOGIC_VECTOR (1407 downto 0));
end component;
begin
uut: keyExpansion Port Map( CLK => CLK,
RESET => RESET,
START => START,
cipherKey => cipherKey,
DONE => DONE,
IDLE => IDLE,
MUTATING => MUTATING,
expandedKey => expandedKey);
clock_process: process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process;
stim_process: process
begin
--Key expansion samples taken from http://www.samiam.org/key-schedule.html
wait for 5*clk_period;
cipherKey <= x"00000000000000000000000000000000";
START <= '1';
wait for clk_period;
START <= '0';
while DONE = '0' loop
wait for clk_period;
end loop;
wait for clk_period*10;
RESET <= '1';
wait for clk_period;
RESET <= '0';
wait for 5*clk_period;
cipherKey <= x"ffffffffffffffffffffffffffffffff";
START <= '1';
wait for clk_period;
START <= '0';
while DONE = '0' loop
wait for clk_period;
end loop;
wait for clk_period*10;
RESET <= '1';
wait for clk_period;
RESET <= '0';
wait for 5*clk_period;
cipherKey <= x"000102030405060708090a0b0c0d0e0f";
START <= '1';
wait for clk_period;
START <= '0';
while DONE = '0' loop
wait for clk_period;
end loop;
wait for clk_period*10;
RESET <= '1';
wait for clk_period;
RESET <= '0';
end process;
end Behavioral;
|
gpl-2.0
|
f87c5df3c64f17f906c7a99c8aea58e8
| 0.481641 | 4.391599 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc473.vhd
| 4 | 5,454 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc473.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00473ent IS
END c03s02b01x01p19n01i00473ent;
ARCHITECTURE c03s02b01x01p19n01i00473arch OF c03s02b01x01p19n01i00473ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
type array_rec_2cons is array (integer range <>) of record_2cons_array;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C66 : array_rec_2cons(0 to 7) := (others => C52) ;
function complex_scalar(s : array_rec_2cons(0 to 7)) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_2cons is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_2cons(0 to 7);
signal S2 : array_rec_2cons(0 to 7);
signal S3 : array_rec_2cons(0 to 7):= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00473"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00473 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00473arch;
|
gpl-2.0
|
31a090d0bcaa72c2a3731d0387619cb7
| 0.616428 | 3.509653 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_06.vhd
| 4 | 2,295 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_06.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_06 is
end entity ch_07_06;
library bv_utilities;
use bv_utilities.bv_arithmetic;
architecture test of ch_07_06 is
begin
process_07_5_b : process is
-- code from book:
function "+" ( left, right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bv_arithmetic."+"(left, right);
-- end not in book
end function "+";
variable addr_reg : bit_vector(31 downto 0);
-- . . .
-- end of code from book
-- code from book:
function "abs" ( right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
if right(right'left) = '0' then
return right;
else
return bv_arithmetic."-"(right);
end if;
-- end not in book
end function "abs";
variable accumulator : bit_vector(31 downto 0);
-- . . .
-- end of code from book
begin
-- code from book:
addr_reg := addr_reg + X"0000_0004";
-- end of code from book
accumulator := X"000000FF";
-- code from book:
accumulator := abs accumulator;
-- end of code from book
accumulator := X"FFFFFFFE";
accumulator := abs accumulator;
wait;
end process process_07_5_b;
end architecture test;
|
gpl-2.0
|
2c11e14270ce1200fa1664d02debea20
| 0.596078 | 3.984375 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/perf02/fsm_163.vhd
| 3 | 111,073 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_163 is
port (
clock : in std_logic;
reset : in std_logic;
out91 : out std_logic;
out92 : out std_logic;
out93 : out std_logic;
in7 : in std_logic;
out94 : out std_logic;
out95 : out std_logic;
out98 : out std_logic;
out100 : out std_logic;
out101 : out std_logic;
out102 : out std_logic;
out104 : out std_logic;
out105 : out std_logic;
out106 : out std_logic;
out107 : out std_logic;
out108 : out std_logic;
out109 : out std_logic;
out111 : out std_logic;
out114 : out std_logic;
out116 : out std_logic;
out118 : out std_logic;
out119 : out std_logic;
out120 : out std_logic;
out128 : out std_logic;
out130 : out std_logic;
out131 : out std_logic;
out132 : out std_logic;
out137 : out std_logic;
in8 : in std_logic;
out152 : out std_logic;
out155 : out std_logic;
out156 : out std_logic;
out31 : out std_logic;
in2 : in std_logic;
out28 : out std_logic;
out29 : out std_logic;
out30 : out std_logic;
out26 : out std_logic;
out27 : out std_logic;
out24 : out std_logic;
out25 : out std_logic;
out77 : out std_logic;
out79 : out std_logic;
out80 : out std_logic;
out82 : out std_logic;
out34 : out std_logic;
out35 : out std_logic;
out36 : out std_logic;
out32 : out std_logic;
out33 : out std_logic;
out40 : out std_logic;
out41 : out std_logic;
out88 : out std_logic;
out89 : out std_logic;
out21 : out std_logic;
out22 : out std_logic;
out23 : out std_logic;
out73 : out std_logic;
out76 : out std_logic;
in6 : in std_logic;
out70 : out std_logic;
out12 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out17 : out std_logic;
out18 : out std_logic;
out19 : out std_logic;
out20 : out std_logic;
out9 : out std_logic;
out11 : out std_logic;
out8 : out std_logic;
out2 : out std_logic;
out4 : out std_logic;
out5 : out std_logic;
in1 : in std_logic;
out6 : out std_logic;
out7 : out std_logic;
out0 : out std_logic;
out1 : out std_logic;
out37 : out std_logic;
out38 : out std_logic;
out39 : out std_logic;
out1222 : out std_logic;
out1223 : out std_logic;
out1224 : out std_logic;
out1225 : out std_logic;
out1226 : out std_logic;
out1228 : out std_logic;
out1230 : out std_logic;
in0 : in std_logic;
out67 : out std_logic;
out68 : out std_logic;
out65 : out std_logic;
out66 : out std_logic;
in5 : in std_logic;
out62 : out std_logic;
out58 : out std_logic;
out56 : out std_logic;
in4 : in std_logic;
out57 : out std_logic;
out54 : out std_logic;
out55 : out std_logic;
out51 : out std_logic;
out52 : out std_logic;
out53 : out std_logic;
in3 : in std_logic;
out46 : out std_logic;
out47 : out std_logic;
out48 : out std_logic;
out49 : out std_logic;
out50 : out std_logic;
out42 : out std_logic;
out43 : out std_logic;
out44 : out std_logic;
out45 : out std_logic;
in9 : in std_logic;
in10 : in std_logic;
out171 : out std_logic;
in11 : in std_logic;
out191 : out std_logic;
out207 : out std_logic;
out208 : out std_logic;
out209 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
out216 : out std_logic;
out220 : out std_logic;
out221 : out std_logic;
out223 : out std_logic;
out224 : out std_logic;
out226 : out std_logic;
out227 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out230 : out std_logic;
out233 : out std_logic;
out235 : out std_logic;
out236 : out std_logic;
out237 : out std_logic;
out238 : out std_logic;
out239 : out std_logic;
out241 : out std_logic;
out250 : out std_logic;
out258 : out std_logic;
out259 : out std_logic;
out261 : out std_logic;
out270 : out std_logic;
out276 : out std_logic;
out277 : out std_logic;
out283 : out std_logic;
out285 : out std_logic;
out287 : out std_logic;
out290 : out std_logic;
out291 : out std_logic;
out293 : out std_logic;
out301 : out std_logic;
out303 : out std_logic;
out304 : out std_logic;
out315 : out std_logic;
out319 : out std_logic;
out321 : out std_logic;
out330 : out std_logic;
out335 : out std_logic;
out338 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out344 : out std_logic;
out347 : out std_logic;
out351 : out std_logic;
out354 : out std_logic;
out355 : out std_logic;
out356 : out std_logic;
out357 : out std_logic;
out358 : out std_logic;
out360 : out std_logic;
out361 : out std_logic;
out362 : out std_logic;
out365 : out std_logic;
out367 : out std_logic;
out368 : out std_logic;
out370 : out std_logic;
out375 : out std_logic;
out376 : out std_logic;
out378 : out std_logic;
out381 : out std_logic;
out382 : out std_logic;
out386 : out std_logic;
out387 : out std_logic;
out388 : out std_logic;
out390 : out std_logic;
out392 : out std_logic;
out393 : out std_logic;
out394 : out std_logic;
out397 : out std_logic;
out403 : out std_logic;
out404 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
out412 : out std_logic;
out416 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out420 : out std_logic;
out421 : out std_logic;
out424 : out std_logic;
out425 : out std_logic;
out430 : out std_logic;
out431 : out std_logic;
out434 : out std_logic;
out436 : out std_logic;
out438 : out std_logic;
out439 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
out442 : out std_logic;
out443 : out std_logic;
out444 : out std_logic;
out445 : out std_logic;
out446 : out std_logic;
out447 : out std_logic;
out448 : out std_logic;
out450 : out std_logic;
out451 : out std_logic;
out454 : out std_logic;
out457 : out std_logic;
out460 : out std_logic;
out463 : out std_logic;
out465 : out std_logic;
out466 : out std_logic;
out472 : out std_logic;
out473 : out std_logic;
out475 : out std_logic;
out476 : out std_logic;
out479 : out std_logic;
out480 : out std_logic;
out481 : out std_logic;
out482 : out std_logic;
out484 : out std_logic;
out485 : out std_logic;
out489 : out std_logic;
out491 : out std_logic;
out494 : out std_logic;
out497 : out std_logic;
out500 : out std_logic;
out503 : out std_logic;
out504 : out std_logic;
out505 : out std_logic;
out508 : out std_logic;
out509 : out std_logic;
out513 : out std_logic;
out514 : out std_logic;
out516 : out std_logic;
out521 : out std_logic;
out523 : out std_logic;
out524 : out std_logic;
out525 : out std_logic;
out530 : out std_logic;
out532 : out std_logic;
out533 : out std_logic;
out535 : out std_logic;
out536 : out std_logic;
out539 : out std_logic;
out541 : out std_logic;
out543 : out std_logic;
out545 : out std_logic;
out547 : out std_logic;
out549 : out std_logic;
out550 : out std_logic;
out552 : out std_logic;
out558 : out std_logic;
out559 : out std_logic;
out563 : out std_logic;
out566 : out std_logic;
out572 : out std_logic;
out573 : out std_logic;
out576 : out std_logic;
out577 : out std_logic;
out581 : out std_logic;
out582 : out std_logic;
out590 : out std_logic;
out591 : out std_logic;
out592 : out std_logic;
out593 : out std_logic;
out595 : out std_logic;
out611 : out std_logic;
out619 : out std_logic;
out638 : out std_logic;
out643 : out std_logic;
out644 : out std_logic;
out645 : out std_logic;
out646 : out std_logic;
out648 : out std_logic;
out650 : out std_logic;
out652 : out std_logic;
out657 : out std_logic;
out659 : out std_logic;
out662 : out std_logic;
out677 : out std_logic;
out678 : out std_logic;
out679 : out std_logic;
out680 : out std_logic;
out682 : out std_logic;
out686 : out std_logic;
out692 : out std_logic;
out1218 : out std_logic;
out1219 : out std_logic;
out1220 : out std_logic;
out1221 : out std_logic;
out695 : out std_logic;
out697 : out std_logic;
out706 : out std_logic;
out719 : out std_logic;
out729 : out std_logic;
out744 : out std_logic;
out746 : out std_logic;
out748 : out std_logic;
out833 : out std_logic;
out834 : out std_logic;
out836 : out std_logic;
out837 : out std_logic;
out839 : out std_logic;
out840 : out std_logic;
out841 : out std_logic;
out844 : out std_logic;
out845 : out std_logic;
out846 : out std_logic;
out848 : out std_logic;
out850 : out std_logic;
out852 : out std_logic;
out854 : out std_logic;
out856 : out std_logic;
out858 : out std_logic;
out860 : out std_logic;
out863 : out std_logic;
out865 : out std_logic;
out866 : out std_logic;
out873 : out std_logic;
out877 : out std_logic;
out888 : out std_logic;
out891 : out std_logic;
out893 : out std_logic;
out895 : out std_logic;
out898 : out std_logic;
out900 : out std_logic;
out902 : out std_logic;
out903 : out std_logic;
out904 : out std_logic;
out905 : out std_logic;
out906 : out std_logic;
out907 : out std_logic;
out908 : out std_logic;
out909 : out std_logic;
out910 : out std_logic;
out912 : out std_logic;
out913 : out std_logic;
out914 : out std_logic;
out915 : out std_logic;
out917 : out std_logic;
out920 : out std_logic;
out921 : out std_logic;
out924 : out std_logic;
out934 : out std_logic;
out935 : out std_logic;
out937 : out std_logic;
out938 : out std_logic;
out940 : out std_logic;
out943 : out std_logic;
out945 : out std_logic;
out957 : out std_logic;
out958 : out std_logic;
out962 : out std_logic;
out968 : out std_logic;
out972 : out std_logic;
out973 : out std_logic;
out974 : out std_logic;
out975 : out std_logic;
out976 : out std_logic;
out980 : out std_logic;
out986 : out std_logic;
out988 : out std_logic;
out989 : out std_logic;
out990 : out std_logic;
out1004 : out std_logic;
out1008 : out std_logic;
out999 : out std_logic;
out1000 : out std_logic;
out1002 : out std_logic;
out1003 : out std_logic;
out1050 : out std_logic;
out1052 : out std_logic;
out1053 : out std_logic;
out1055 : out std_logic;
out1056 : out std_logic;
out1057 : out std_logic;
out1059 : out std_logic;
out1015 : out std_logic;
out1025 : out std_logic;
out1026 : out std_logic;
out1038 : out std_logic;
out1039 : out std_logic;
out1042 : out std_logic;
out1043 : out std_logic;
out1046 : out std_logic;
out1048 : out std_logic;
out1061 : out std_logic;
out1063 : out std_logic;
out1064 : out std_logic;
out1067 : out std_logic;
out1068 : out std_logic;
out1069 : out std_logic;
out1071 : out std_logic;
out1073 : out std_logic;
out1076 : out std_logic;
out1077 : out std_logic;
out1078 : out std_logic;
out1080 : out std_logic;
out1081 : out std_logic;
out1083 : out std_logic;
out1085 : out std_logic;
out1087 : out std_logic;
out1089 : out std_logic;
out1092 : out std_logic;
out1096 : out std_logic;
out1100 : out std_logic;
out1103 : out std_logic;
out1115 : out std_logic;
out1122 : out std_logic;
out1123 : out std_logic;
out1127 : out std_logic;
out1130 : out std_logic;
out1133 : out std_logic;
out1138 : out std_logic;
out1139 : out std_logic;
out1140 : out std_logic;
out1141 : out std_logic;
out1142 : out std_logic;
out1143 : out std_logic;
out1144 : out std_logic;
out1145 : out std_logic;
out1146 : out std_logic;
out1147 : out std_logic;
out1148 : out std_logic;
out1149 : out std_logic;
out1150 : out std_logic;
out1151 : out std_logic;
out1152 : out std_logic;
out1153 : out std_logic;
out1154 : out std_logic;
out1155 : out std_logic;
out1156 : out std_logic;
out1157 : out std_logic;
out1158 : out std_logic;
out1159 : out std_logic;
out1160 : out std_logic;
out1161 : out std_logic;
out1162 : out std_logic;
out1163 : out std_logic;
out1164 : out std_logic;
out1165 : out std_logic;
out1166 : out std_logic;
out1167 : out std_logic;
out1168 : out std_logic;
out1169 : out std_logic;
out1170 : out std_logic;
out1171 : out std_logic;
out1172 : out std_logic;
out1173 : out std_logic;
out1174 : out std_logic;
out1175 : out std_logic;
out1176 : out std_logic;
out1177 : out std_logic;
out1178 : out std_logic;
out1179 : out std_logic;
out1180 : out std_logic;
out1181 : out std_logic;
out1182 : out std_logic;
out1183 : out std_logic;
out1184 : out std_logic;
out1185 : out std_logic;
out1186 : out std_logic;
out1187 : out std_logic;
out1188 : out std_logic;
out1189 : out std_logic;
out1190 : out std_logic;
out1191 : out std_logic;
out1192 : out std_logic;
out1193 : out std_logic;
out1194 : out std_logic;
out1195 : out std_logic;
out1196 : out std_logic;
out1197 : out std_logic;
out1198 : out std_logic;
out1199 : out std_logic;
out1200 : out std_logic;
out1201 : out std_logic;
out1202 : out std_logic;
out1203 : out std_logic;
out1204 : out std_logic;
out1205 : out std_logic;
out1206 : out std_logic;
out1207 : out std_logic;
out1208 : out std_logic;
out1209 : out std_logic;
out1210 : out std_logic;
out1211 : out std_logic;
out1212 : out std_logic;
out1213 : out std_logic;
out1214 : out std_logic;
out1215 : out std_logic;
out1216 : out std_logic;
out1217 : out std_logic
);
end fsm_163;
architecture augh of fsm_163 is
signal state_cur : std_logic_vector(0 to 523) := (141 => '1', others => '0');
signal state_next : std_logic_vector(0 to 523) := (141 => '1', others => '0');
-- Buffers for outputs
signal out386_buf : std_logic := '0';
signal out386_bufn : std_logic;
signal out404_buf : std_logic := '0';
signal out404_bufn : std_logic;
signal out457_buf : std_logic := '0';
signal out457_bufn : std_logic;
signal out841_buf : std_logic := '0';
signal out841_bufn : std_logic;
signal out276_buf : std_logic := '0';
signal out276_bufn : std_logic;
signal out67_buf : std_logic := '0';
signal out67_bufn : std_logic;
signal out239_buf : std_logic := '0';
signal out239_bufn : std_logic;
signal out259_buf : std_logic := '0';
signal out259_bufn : std_logic;
signal out416_buf : std_logic := '0';
signal out416_bufn : std_logic;
signal out646_buf : std_logic := '0';
signal out646_bufn : std_logic;
signal out485_buf : std_logic := '0';
signal out485_bufn : std_logic;
signal out935_buf : std_logic := '0';
signal out935_bufn : std_logic;
signal out463_buf : std_logic := '0';
signal out463_bufn : std_logic;
signal out120_buf : std_logic := '0';
signal out120_bufn : std_logic;
signal out293_buf : std_logic := '0';
signal out293_bufn : std_logic;
signal out216_buf : std_logic := '0';
signal out216_bufn : std_logic;
signal out319_buf : std_logic := '0';
signal out319_bufn : std_logic;
signal out230_buf : std_logic := '0';
signal out230_bufn : std_logic;
signal out1_buf : std_logic := '0';
signal out1_bufn : std_logic;
signal out93_buf : std_logic := '0';
signal out93_bufn : std_logic;
signal out89_buf : std_logic := '0';
signal out89_bufn : std_logic;
signal out539_buf : std_logic := '0';
signal out539_bufn : std_logic;
signal out62_buf : std_logic := '0';
signal out62_bufn : std_logic;
signal out856_buf : std_logic := '0';
signal out856_bufn : std_logic;
signal out451_buf : std_logic := '0';
signal out451_bufn : std_logic;
signal out287_buf : std_logic := '0';
signal out287_bufn : std_logic;
signal out315_buf : std_logic := '0';
signal out315_bufn : std_logic;
signal out536_buf : std_logic := '0';
signal out536_bufn : std_logic;
signal out209_buf : std_logic := '0';
signal out209_bufn : std_logic;
signal out221_buf : std_logic := '0';
signal out221_bufn : std_logic;
signal out283_buf : std_logic := '0';
signal out283_bufn : std_logic;
signal out368_buf : std_logic := '0';
signal out368_bufn : std_logic;
signal out516_buf : std_logic := '0';
signal out516_bufn : std_logic;
signal out393_buf : std_logic := '0';
signal out393_bufn : std_logic;
signal out1008_buf : std_logic := '0';
signal out1008_bufn : std_logic;
signal out392_buf : std_logic := '0';
signal out392_bufn : std_logic;
signal out261_buf : std_logic := '0';
signal out261_bufn : std_logic;
signal out559_buf : std_logic := '0';
signal out559_bufn : std_logic;
signal out543_buf : std_logic := '0';
signal out543_bufn : std_logic;
signal out895_buf : std_logic := '0';
signal out895_bufn : std_logic;
signal out82_buf : std_logic := '0';
signal out82_bufn : std_logic;
signal out220_buf : std_logic := '0';
signal out220_bufn : std_logic;
signal out95_buf : std_logic := '0';
signal out95_bufn : std_logic;
signal out943_buf : std_logic := '0';
signal out943_bufn : std_logic;
signal out465_buf : std_logic := '0';
signal out465_bufn : std_logic;
signal out238_buf : std_logic := '0';
signal out238_bufn : std_logic;
signal out1025_buf : std_logic := '0';
signal out1025_bufn : std_logic;
signal out132_buf : std_logic := '0';
signal out132_bufn : std_logic;
signal out79_buf : std_logic := '0';
signal out79_bufn : std_logic;
signal out500_buf : std_logic := '0';
signal out500_bufn : std_logic;
signal out65_buf : std_logic := '0';
signal out65_bufn : std_logic;
signal out111_buf : std_logic := '0';
signal out111_bufn : std_logic;
signal out420_buf : std_logic := '0';
signal out420_bufn : std_logic;
signal out1076_buf : std_logic := '0';
signal out1076_bufn : std_logic;
signal out101_buf : std_logic := '0';
signal out101_bufn : std_logic;
signal out106_buf : std_logic := '0';
signal out106_bufn : std_logic;
signal out68_buf : std_logic := '0';
signal out68_bufn : std_logic;
signal out1069_buf : std_logic := '0';
signal out1069_bufn : std_logic;
signal out77_buf : std_logic := '0';
signal out77_bufn : std_logic;
signal out102_buf : std_logic := '0';
signal out102_bufn : std_logic;
signal out394_buf : std_logic := '0';
signal out394_bufn : std_logic;
signal out342_buf : std_logic := '0';
signal out342_bufn : std_logic;
signal out104_buf : std_logic := '0';
signal out104_bufn : std_logic;
signal out361_buf : std_logic := '0';
signal out361_bufn : std_logic;
signal out116_buf : std_logic := '0';
signal out116_bufn : std_logic;
signal out595_buf : std_logic := '0';
signal out595_bufn : std_logic;
signal out1004_buf : std_logic := '0';
signal out1004_bufn : std_logic;
signal out227_buf : std_logic := '0';
signal out227_bufn : std_logic;
signal out109_buf : std_logic := '0';
signal out109_bufn : std_logic;
signal out619_buf : std_logic := '0';
signal out619_bufn : std_logic;
signal out410_buf : std_logic := '0';
signal out410_bufn : std_logic;
signal out989_buf : std_logic := '0';
signal out989_bufn : std_logic;
signal out431_buf : std_logic := '0';
signal out431_bufn : std_logic;
signal out938_buf : std_logic := '0';
signal out938_bufn : std_logic;
signal out525_buf : std_logic := '0';
signal out525_bufn : std_logic;
signal out73_buf : std_logic := '0';
signal out73_bufn : std_logic;
signal out837_buf : std_logic := '0';
signal out837_bufn : std_logic;
signal out860_buf : std_logic := '0';
signal out860_bufn : std_logic;
signal out228_buf : std_logic := '0';
signal out228_bufn : std_logic;
signal out421_buf : std_logic := '0';
signal out421_bufn : std_logic;
signal out409_buf : std_logic := '0';
signal out409_bufn : std_logic;
signal out473_buf : std_logic := '0';
signal out473_bufn : std_logic;
signal out509_buf : std_logic := '0';
signal out509_bufn : std_logic;
signal out94_buf : std_logic := '0';
signal out94_bufn : std_logic;
signal out1048_buf : std_logic := '0';
signal out1048_bufn : std_logic;
signal out98_buf : std_logic := '0';
signal out98_bufn : std_logic;
signal out945_buf : std_logic := '0';
signal out945_bufn : std_logic;
signal out156_buf : std_logic := '0';
signal out156_bufn : std_logic;
signal out152_buf : std_logic := '0';
signal out152_bufn : std_logic;
-- Retiming: counters
signal rtmcounter0 : unsigned(4 downto 0) := (others => '0');
signal rtmcounter0_next : unsigned(4 downto 0);
-- Retiming: Output of comparators
signal rtmcmp92 : std_logic;
signal rtmcmp128 : std_logic;
signal rtmcmp276 : std_logic;
signal rtmcmp290 : std_logic;
-- Don't understand why these two function declarations are needed...
function "/=" (L, R: std_logic) return std_logic is
begin
if L /= R then
return '1';
end if;
return '0';
end function;
function "=" (L, R: std_logic) return std_logic is
begin
if L = R then
return '1';
end if;
return '0';
end function;
begin
-- Sequential process
-- Set the current state
process (clock)
begin
if rising_edge(clock) then
-- Next state
state_cur <= state_next;
-- Buffers for outputs
out386_buf <= out386_bufn;
out404_buf <= out404_bufn;
out457_buf <= out457_bufn;
out841_buf <= out841_bufn;
out276_buf <= out276_bufn;
out67_buf <= out67_bufn;
out239_buf <= out239_bufn;
out259_buf <= out259_bufn;
out416_buf <= out416_bufn;
out646_buf <= out646_bufn;
out485_buf <= out485_bufn;
out935_buf <= out935_bufn;
out463_buf <= out463_bufn;
out120_buf <= out120_bufn;
out293_buf <= out293_bufn;
out216_buf <= out216_bufn;
out319_buf <= out319_bufn;
out230_buf <= out230_bufn;
out1_buf <= out1_bufn;
out93_buf <= out93_bufn;
out89_buf <= out89_bufn;
out539_buf <= out539_bufn;
out62_buf <= out62_bufn;
out856_buf <= out856_bufn;
out451_buf <= out451_bufn;
out287_buf <= out287_bufn;
out315_buf <= out315_bufn;
out536_buf <= out536_bufn;
out209_buf <= out209_bufn;
out221_buf <= out221_bufn;
out283_buf <= out283_bufn;
out368_buf <= out368_bufn;
out516_buf <= out516_bufn;
out393_buf <= out393_bufn;
out1008_buf <= out1008_bufn;
out392_buf <= out392_bufn;
out261_buf <= out261_bufn;
out559_buf <= out559_bufn;
out543_buf <= out543_bufn;
out895_buf <= out895_bufn;
out82_buf <= out82_bufn;
out220_buf <= out220_bufn;
out95_buf <= out95_bufn;
out943_buf <= out943_bufn;
out465_buf <= out465_bufn;
out238_buf <= out238_bufn;
out1025_buf <= out1025_bufn;
out132_buf <= out132_bufn;
out79_buf <= out79_bufn;
out500_buf <= out500_bufn;
out65_buf <= out65_bufn;
out111_buf <= out111_bufn;
out420_buf <= out420_bufn;
out1076_buf <= out1076_bufn;
out101_buf <= out101_bufn;
out106_buf <= out106_bufn;
out68_buf <= out68_bufn;
out1069_buf <= out1069_bufn;
out77_buf <= out77_bufn;
out102_buf <= out102_bufn;
out394_buf <= out394_bufn;
out342_buf <= out342_bufn;
out104_buf <= out104_bufn;
out361_buf <= out361_bufn;
out116_buf <= out116_bufn;
out595_buf <= out595_bufn;
out1004_buf <= out1004_bufn;
out227_buf <= out227_bufn;
out109_buf <= out109_bufn;
out619_buf <= out619_bufn;
out410_buf <= out410_bufn;
out989_buf <= out989_bufn;
out431_buf <= out431_bufn;
out938_buf <= out938_bufn;
out525_buf <= out525_bufn;
out73_buf <= out73_bufn;
out837_buf <= out837_bufn;
out860_buf <= out860_bufn;
out228_buf <= out228_bufn;
out421_buf <= out421_bufn;
out409_buf <= out409_bufn;
out473_buf <= out473_bufn;
out509_buf <= out509_bufn;
out94_buf <= out94_bufn;
out1048_buf <= out1048_bufn;
out98_buf <= out98_bufn;
out945_buf <= out945_bufn;
out156_buf <= out156_bufn;
out152_buf <= out152_bufn;
-- Retiming: counters
rtmcounter0 <= rtmcounter0_next;
end if;
end process;
-- Retiming: the counters
rtmcounter0_next <= rtmcounter0 + 1 when (reset /= '1') and (
(state_cur(290) = '1' and rtmcmp290 = '0') or (state_cur(276) = '1' and rtmcmp276 = '0') or (state_cur(128) = '1' and rtmcmp128 = '0') or (state_cur(92) = '1' and rtmcmp92 = '0')
) else (others => '0');
-- Next state bits
state_next(0) <= (reset /= '1') and ( ( state_cur(90) and not ( (NOT(in0)) = '1' ) ) );
state_next(1) <= (reset /= '1') and ( ( state_cur(86) and not ( (NOT(in1)) = '1' ) ) );
state_next(2) <= (reset /= '1') and ( ( state_cur(44) and not ( (NOT(in0)) = '1' ) ) );
state_next(3) <= (reset /= '1') and ( ( state_cur(201) and not ( (NOT(in0)) = '1' ) ) );
state_next(4) <= (reset /= '1') and ( ( state_cur(48) and not ( (NOT(in0)) = '1' ) ) );
state_next(5) <= (reset /= '1') and ( ( state_cur(6) and not ( (NOT(in0)) = '1' ) ) );
state_next(6) <= (reset /= '1') and ( state_cur(32) or ( state_cur(6) and (NOT(in0)) = '1' ) );
state_next(7) <= (reset /= '1') and ( ( state_cur(207) and not ( (NOT(in0)) = '1' ) ) );
state_next(8) <= (reset /= '1') and ( ( state_cur(17) and not ( (NOT(in0)) = '1' ) ) );
state_next(9) <= (reset /= '1') and ( ( state_cur(13) and not ( (NOT(in0)) = '1' ) ) );
state_next(10) <= (reset /= '1') and ( state_cur(221) or ( state_cur(10) and (NOT(in0)) = '1' ) );
state_next(11) <= (reset /= '1') and ( state_cur(83) or ( state_cur(11) and (NOT(in1)) = '1' ) );
state_next(12) <= (reset /= '1') and ( state_cur(23) or ( state_cur(12) and (NOT(in0)) = '1' ) );
state_next(13) <= (reset /= '1') and ( state_cur(321) or ( state_cur(13) and (NOT(in0)) = '1' ) );
state_next(14) <= (reset /= '1') and ( state_cur(251) or ( state_cur(14) and (NOT(in0)) = '1' ) );
state_next(15) <= (reset /= '1') and ( ( state_cur(263) and not ( (NOT(in0)) = '1' ) ) );
state_next(16) <= (reset /= '1') and ( ( state_cur(188) and not ( (NOT(in0)) = '1' ) ) );
state_next(17) <= (reset /= '1') and ( ( state_cur(17) and (NOT(in0)) = '1' ) or state_cur(9) );
state_next(18) <= (reset /= '1') and ( ( state_cur(239) and not ( (NOT(in0)) = '1' ) ) );
state_next(19) <= (reset /= '1') and ( ( state_cur(14) and not ( (NOT(in0)) = '1' ) ) );
state_next(20) <= (reset /= '1') and ( ( state_cur(27) and not ( (NOT(in0)) = '1' ) ) );
state_next(21) <= (reset /= '1') and ( state_cur(22) or ( state_cur(21) and (NOT(in0)) = '1' ) );
state_next(22) <= (reset /= '1') and ( ( state_cur(26) and not ( (NOT(in0)) = '1' ) ) );
state_next(23) <= (reset /= '1') and ( ( state_cur(117) and not ( (NOT(in0)) = '1' ) ) );
state_next(24) <= (reset /= '1') and ( state_cur(254) or ( state_cur(24) and (NOT(in0)) = '1' ) );
state_next(25) <= (reset /= '1') and ( ( state_cur(320) and not ( (NOT(in0)) = '1' ) ) );
state_next(26) <= (reset /= '1') and ( ( state_cur(26) and (NOT(in0)) = '1' ) or state_cur(25) );
state_next(27) <= (reset /= '1') and ( state_cur(81) or ( state_cur(27) and (NOT(in0)) = '1' ) );
state_next(28) <= (reset /= '1') and ( state_cur(261) or ( state_cur(28) and (NOT(in0)) = '1' ) );
state_next(29) <= (reset /= '1') and ( state_cur(198) or ( state_cur(29) and (NOT(in1)) = '1' ) );
state_next(30) <= (reset /= '1') and ( ( state_cur(324) and not ( (NOT(in0)) = '1' ) ) );
state_next(31) <= (reset /= '1') and ( ( state_cur(33) and not ( (NOT(in0)) = '1' ) ) );
state_next(32) <= (reset /= '1') and ( ( state_cur(259) and not ( (NOT(in0)) = '1' ) ) );
state_next(33) <= (reset /= '1') and ( state_cur(267) or ( state_cur(33) and (NOT(in0)) = '1' ) );
state_next(34) <= (reset /= '1') and ( ( state_cur(34) and (NOT(in0)) = '1' ) or state_cur(31) );
state_next(35) <= (reset /= '1') and ( state_cur(36) or ( state_cur(35) and (NOT(in0)) = '1' ) );
state_next(36) <= (reset /= '1') and ( ( state_cur(34) and not ( (NOT(in0)) = '1' ) ) );
state_next(37) <= (reset /= '1') and ( state_cur(38) or ( state_cur(37) and (NOT(in0)) = '1' ) );
state_next(38) <= (reset /= '1') and ( ( state_cur(35) and not ( (NOT(in0)) = '1' ) ) );
state_next(39) <= (reset /= '1') and ( ( state_cur(323) and not ( (NOT(in0)) = '1' ) ) );
state_next(40) <= (reset /= '1') and ( ( state_cur(285) and not ( (NOT(in0)) = '1' ) ) );
state_next(41) <= (reset /= '1') and ( ( state_cur(41) and (NOT(in0)) = '1' ) or state_cur(8) );
state_next(42) <= (reset /= '1') and ( state_cur(180) or ( state_cur(42) and (NOT(in1)) = '1' ) );
state_next(43) <= (reset /= '1') and ( ( state_cur(41) and not ( (NOT(in0)) = '1' ) ) );
state_next(44) <= (reset /= '1') and ( state_cur(66) or ( state_cur(44) and (NOT(in0)) = '1' ) );
state_next(45) <= (reset /= '1') and ( ( state_cur(37) and not ( (NOT(in0)) = '1' ) ) );
state_next(46) <= (reset /= '1') and ( ( state_cur(46) and (NOT(in0)) = '1' ) or state_cur(43) );
state_next(47) <= (reset /= '1') and ( ( state_cur(46) and not ( (NOT(in0)) = '1' ) ) );
state_next(48) <= (reset /= '1') and ( ( state_cur(48) and (NOT(in0)) = '1' ) or state_cur(40) );
state_next(49) <= (reset /= '1') and ( ( state_cur(49) and (NOT(in0)) = '1' ) or state_cur(18) );
state_next(50) <= (reset /= '1') and ( ( state_cur(50) and (NOT(in0)) = '1' ) or state_cur(47) );
state_next(51) <= (reset /= '1') and ( state_cur(53) or ( state_cur(51) and (NOT(in0)) = '1' ) );
state_next(52) <= (reset /= '1') and ( state_cur(56) or ( state_cur(52) and (NOT(in0)) = '1' ) );
state_next(53) <= (reset /= '1') and ( ( state_cur(52) and not ( (NOT(in0)) = '1' ) ) );
state_next(54) <= (reset /= '1') and ( ( state_cur(51) and not ( (NOT(in0)) = '1' ) ) );
state_next(55) <= (reset /= '1') and ( ( state_cur(55) and (NOT(in0)) = '1' ) or state_cur(54) );
state_next(56) <= (reset /= '1') and ( ( state_cur(21) and not ( (NOT(in0)) = '1' ) ) );
state_next(57) <= (reset /= '1') and ( ( state_cur(104) and not ( (NOT(in0)) = '1' ) ) );
state_next(58) <= (reset /= '1') and ( ( state_cur(12) and not ( (NOT(in0)) = '1' ) ) );
state_next(59) <= (reset /= '1') and ( ( state_cur(61) and not ( (NOT(in0)) = '1' ) ) );
state_next(60) <= (reset /= '1') and ( ( state_cur(246) and not ( (NOT(in0)) = '1' ) ) );
state_next(61) <= (reset /= '1') and ( state_cur(260) or ( state_cur(61) and (NOT(in0)) = '1' ) );
state_next(62) <= (reset /= '1') and ( ( state_cur(65) and not ( (NOT(in0)) = '1' ) ) );
state_next(63) <= (reset /= '1') and ( ( state_cur(24) and not ( (NOT(in0)) = '1' ) ) );
state_next(64) <= (reset /= '1') and ( state_cur(277) or ( state_cur(64) and (NOT(in0)) = '1' ) );
state_next(65) <= (reset /= '1') and ( state_cur(329) or ( state_cur(65) and (NOT(in0)) = '1' ) );
state_next(66) <= (reset /= '1') and ( ( state_cur(256) and not ( (NOT(in0)) = '1' ) ) );
state_next(67) <= (reset /= '1') and ( ( state_cur(67) and (NOT(in0)) = '1' ) or state_cur(62) );
state_next(68) <= (reset /= '1') and ( ( state_cur(68) and (NOT(in0)) = '1' ) or state_cur(60) );
state_next(69) <= (reset /= '1') and ( ( state_cur(258) and not ( (NOT(in0)) = '1' ) ) );
state_next(70) <= (reset /= '1') and ( ( state_cur(278) and not ( (NOT(in0)) = '1' ) ) );
state_next(71) <= (reset /= '1') and ( ( state_cur(255) and not ( (NOT(in1)) = '1' ) ) );
state_next(72) <= (reset /= '1') and ( state_cur(85) or ( state_cur(72) and (NOT(in1)) = '1' ) );
state_next(73) <= (reset /= '1') and ( ( state_cur(106) and not ( (NOT(in1)) = '1' ) ) );
state_next(74) <= (reset /= '1') and ( ( state_cur(297) and not ( (NOT(in0)) = '1' ) ) );
state_next(75) <= (reset /= '1') and ( ( state_cur(75) and (NOT(in0)) = '1' ) or state_cur(57) );
state_next(76) <= (reset /= '1') and ( ( state_cur(272) and not ( (NOT(in0)) = '1' ) ) );
state_next(77) <= (reset /= '1') and ( state_cur(199) or ( state_cur(77) and (NOT(in0)) = '1' ) );
state_next(78) <= (reset /= '1') and ( state_cur(115) or ( state_cur(78) and (NOT(in1)) = '1' ) );
state_next(79) <= (reset /= '1') and ( ( state_cur(42) and not ( (NOT(in1)) = '1' ) ) );
state_next(80) <= (reset /= '1') and ( ( state_cur(80) and (NOT(in0)) = '1' ) or state_cur(7) );
state_next(81) <= (reset /= '1') and ( ( state_cur(80) and not ( (NOT(in0)) = '1' ) ) );
state_next(82) <= (reset /= '1') and ( ( state_cur(217) and not ( (NOT(in0)) = '1' ) ) );
state_next(83) <= (reset /= '1') and ( ( state_cur(72) and not ( (NOT(in1)) = '1' ) ) );
state_next(84) <= (reset /= '1') and ( ( state_cur(84) and (NOT(in0)) = '1' ) or state_cur(82) );
state_next(85) <= (reset /= '1') and ( ( state_cur(29) and not ( (NOT(in1)) = '1' ) ) );
state_next(86) <= (reset /= '1') and ( state_cur(195) or ( state_cur(86) and (NOT(in1)) = '1' ) );
state_next(87) <= (reset /= '1') and ( ( state_cur(87) and (NOT(in0)) = '1' ) or state_cur(20) );
state_next(88) <= (reset /= '1') and ( ( state_cur(288) and not ( (NOT(in0)) = '1' ) ) );
state_next(89) <= (reset /= '1') and ( ( state_cur(140) and not ( (NOT(in0)) = '1' ) ) );
state_next(90) <= (reset /= '1') and ( ( state_cur(90) and (NOT(in0)) = '1' ) or state_cur(89) );
state_next(91) <= (reset /= '1') and ( state_cur(337) );
state_next(92) <= (reset /= '1') and ( (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) );
state_next(93) <= (reset /= '1') and ( state_cur(339) );
state_next(94) <= (reset /= '1') and ( ( state_cur(175) and not ( (in4) = '1' ) ) );
state_next(95) <= (reset /= '1') and ( state_cur(334) );
state_next(96) <= (reset /= '1') and ( state_cur(333) );
state_next(97) <= (reset /= '1') and ( state_cur(244) or ( state_cur(97) and (NOT(in0)) = '1' ) );
state_next(98) <= (reset /= '1') and ( state_cur(228) );
state_next(99) <= (reset /= '1') and ( state_cur(273) or state_cur(105) );
state_next(100) <= (reset /= '1') and ( state_cur(203) );
state_next(101) <= (reset /= '1') and ( ( state_cur(101) and (NOT(in0)) = '1' ) or state_cur(5) );
state_next(102) <= (reset /= '1') and ( state_cur(98) );
state_next(103) <= (reset /= '1') and ( state_cur(200) );
state_next(104) <= (reset /= '1') and ( state_cur(111) or ( state_cur(104) and (NOT(in0)) = '1' ) );
state_next(105) <= (reset /= '1') and ( state_cur(301) );
state_next(106) <= (reset /= '1') and ( state_cur(214) or ( state_cur(106) and (NOT(in1)) = '1' ) );
state_next(107) <= (reset /= '1') and ( rtmcmp276 );
state_next(108) <= (reset /= '1') and ( state_cur(224) );
state_next(109) <= (reset /= '1') and ( ( state_cur(310) and (in9) = '1' ) );
state_next(110) <= (reset /= '1') and ( state_cur(222) or ( state_cur(110) and (NOT(in1)) = '1' ) );
state_next(111) <= (reset /= '1') and ( ( state_cur(112) and not ( (NOT(in0)) = '1' ) ) );
state_next(112) <= (reset /= '1') and ( state_cur(293) or ( state_cur(112) and (NOT(in0)) = '1' ) );
state_next(113) <= (reset /= '1') and ( ( state_cur(304) and not ( (NOT(in0)) = '1' ) ) );
state_next(114) <= (reset /= '1') and ( state_cur(523) or state_cur(129) );
state_next(115) <= (reset /= '1') and ( ( state_cur(110) and not ( (NOT(in1)) = '1' ) ) );
state_next(116) <= (reset /= '1') and ( state_cur(327) or ( state_cur(116) and (NOT(in0)) = '1' ) );
state_next(117) <= (reset /= '1') and ( ( state_cur(117) and (NOT(in0)) = '1' ) or state_cur(2) );
state_next(118) <= (reset /= '1') and ( state_cur(181) or ( state_cur(118) and (NOT(in0)) = '1' ) );
state_next(119) <= (reset /= '1') and ( state_cur(274) );
state_next(120) <= (reset /= '1') and ( ( state_cur(120) and (NOT(in0)) = '1' ) or state_cur(15) );
state_next(121) <= (reset /= '1') and ( state_cur(227) or ( state_cur(121) and (NOT(in0)) = '1' ) );
state_next(122) <= (reset /= '1') and ( ( state_cur(122) and (NOT(in0)) = '1' ) or state_cur(4) );
state_next(123) <= (reset /= '1') and ( state_cur(303) );
state_next(124) <= (reset /= '1') and ( state_cur(133) or ( state_cur(124) and (NOT(in0)) = '1' ) );
state_next(125) <= (reset /= '1') and ( ( state_cur(343) and not ( (NOT(in1)) = '1' ) ) );
state_next(126) <= (reset /= '1') and ( ( state_cur(314) and not ( (NOT(in0)) = '1' ) ) );
state_next(127) <= (reset /= '1') and ( ( state_cur(127) and (NOT(in0)) = '1' ) or state_cur(126) );
state_next(128) <= (reset /= '1') and ( (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296) );
state_next(129) <= (reset /= '1') and ( ( state_cur(208) and (in5) = '1' ) );
state_next(130) <= (reset /= '1') and ( state_cur(137) or ( state_cur(130) and (NOT(in0)) = '1' ) );
state_next(131) <= (reset /= '1') and ( ( state_cur(127) and not ( (NOT(in0)) = '1' ) ) );
state_next(132) <= (reset /= '1') and ( state_cur(191) );
state_next(133) <= (reset /= '1') and ( ( state_cur(118) and not ( (NOT(in0)) = '1' ) ) );
state_next(134) <= (reset /= '1') and ( state_cur(172) );
state_next(135) <= (reset /= '1') and ( state_cur(284) or ( state_cur(135) and (NOT(in0)) = '1' ) );
state_next(136) <= (reset /= '1') and ( state_cur(230) or ( state_cur(136) and (NOT(in0)) = '1' ) );
state_next(137) <= (reset /= '1') and ( ( state_cur(116) and not ( (NOT(in0)) = '1' ) ) );
state_next(138) <= (reset /= '1') and ( ( state_cur(175) and (in4) = '1' ) );
state_next(139) <= (reset /= '1') and ( ( state_cur(101) and not ( (NOT(in0)) = '1' ) ) );
state_next(140) <= (reset /= '1') and ( ( state_cur(140) and (NOT(in0)) = '1' ) or state_cur(139) );
state_next(141) <= (reset = '1') or ( ( state_cur(141) and (NOT(in2)) = '1' ) );
state_next(142) <= (reset /= '1') and ( state_cur(270) );
state_next(143) <= (reset /= '1') and ( state_cur(204) );
state_next(144) <= (reset /= '1') and ( state_cur(173) );
state_next(145) <= (reset /= '1') and ( state_cur(322) );
state_next(146) <= (reset /= '1') and ( state_cur(331) );
state_next(147) <= (reset /= '1') and ( state_cur(197) );
state_next(148) <= (reset /= '1') and ( state_cur(306) );
state_next(149) <= (reset /= '1') and ( state_cur(187) );
state_next(150) <= (reset /= '1') and ( state_cur(294) );
state_next(151) <= (reset /= '1') and ( state_cur(289) );
state_next(152) <= (reset /= '1') and ( ( state_cur(153) and not ( (NOT(in0)) = '1' ) ) );
state_next(153) <= (reset /= '1') and ( state_cur(154) or ( state_cur(153) and (NOT(in0)) = '1' ) );
state_next(154) <= (reset /= '1') and ( ( state_cur(155) and not ( (NOT(in0)) = '1' ) ) );
state_next(155) <= (reset /= '1') and ( state_cur(156) or ( state_cur(155) and (NOT(in0)) = '1' ) );
state_next(156) <= (reset /= '1') and ( ( state_cur(157) and not ( (NOT(in0)) = '1' ) ) );
state_next(157) <= (reset /= '1') and ( state_cur(158) or ( state_cur(157) and (NOT(in0)) = '1' ) );
state_next(158) <= (reset /= '1') and ( ( state_cur(159) and not ( (NOT(in0)) = '1' ) ) );
state_next(159) <= (reset /= '1') and ( state_cur(160) or ( state_cur(159) and (NOT(in0)) = '1' ) );
state_next(160) <= (reset /= '1') and ( ( state_cur(161) and not ( (NOT(in0)) = '1' ) ) );
state_next(161) <= (reset /= '1') and ( state_cur(162) or ( state_cur(161) and (NOT(in0)) = '1' ) );
state_next(162) <= (reset /= '1') and ( ( state_cur(163) and not ( (NOT(in0)) = '1' ) ) );
state_next(163) <= (reset /= '1') and ( state_cur(164) or ( state_cur(163) and (NOT(in0)) = '1' ) );
state_next(164) <= (reset /= '1') and ( ( state_cur(165) and not ( (NOT(in0)) = '1' ) ) );
state_next(165) <= (reset /= '1') and ( state_cur(166) or ( state_cur(165) and (NOT(in0)) = '1' ) );
state_next(166) <= (reset /= '1') and ( ( state_cur(167) and not ( (NOT(in0)) = '1' ) ) );
state_next(167) <= (reset /= '1') and ( state_cur(168) or ( state_cur(167) and (NOT(in0)) = '1' ) );
state_next(168) <= (reset /= '1') and ( ( state_cur(55) and not ( (NOT(in0)) = '1' ) ) );
state_next(169) <= (reset /= '1') and ( state_cur(332) );
state_next(170) <= (reset /= '1') and ( state_cur(169) );
state_next(171) <= (reset /= '1') and ( ( state_cur(171) and (NOT(in0)) = '1' ) or state_cur(16) );
state_next(172) <= (reset /= '1') and ( state_cur(174) );
state_next(173) <= (reset /= '1') and ( ( state_cur(325) and (in10) = '1' ) or ( state_cur(310) and not ( (in9) = '1' ) ) );
state_next(174) <= (reset /= '1') and ( state_cur(319) );
state_next(175) <= (reset /= '1') and ( state_cur(170) );
state_next(176) <= (reset /= '1') and ( ( state_cur(176) and (NOT(in0)) = '1' ) or state_cur(70) );
state_next(177) <= (reset /= '1') and ( ( state_cur(279) and not ( (NOT(in0)) = '1' ) ) );
state_next(178) <= (reset /= '1') and ( ( state_cur(150) and (in3) = '1' ) );
state_next(179) <= (reset /= '1') and ( state_cur(282) );
state_next(180) <= (reset /= '1') and ( ( state_cur(520) and not ( (NOT(in1)) = '1' ) ) );
state_next(181) <= (reset /= '1') and ( ( state_cur(226) and not ( (NOT(in0)) = '1' ) ) );
state_next(182) <= (reset /= '1') and ( state_cur(223) );
state_next(183) <= (reset /= '1') and ( state_cur(280) );
state_next(184) <= (reset /= '1') and ( state_cur(183) );
state_next(185) <= (reset /= '1') and ( ( state_cur(135) and not ( (NOT(in0)) = '1' ) ) );
state_next(186) <= (reset /= '1') and ( rtmcmp290 );
state_next(187) <= (reset /= '1') and ( state_cur(184) );
state_next(188) <= (reset /= '1') and ( state_cur(206) or ( state_cur(188) and (NOT(in0)) = '1' ) );
state_next(189) <= (reset /= '1') and ( state_cur(179) );
state_next(190) <= (reset /= '1') and ( state_cur(186) );
state_next(191) <= (reset /= '1') and ( state_cur(190) );
state_next(192) <= (reset /= '1') and ( ( state_cur(192) and (NOT(in0)) = '1' ) or state_cur(76) );
state_next(193) <= (reset /= '1') and ( state_cur(233) );
state_next(194) <= (reset /= '1') and ( state_cur(252) or ( state_cur(194) and (NOT(in0)) = '1' ) );
state_next(195) <= (reset /= '1') and ( ( state_cur(521) and not ( (NOT(in1)) = '1' ) ) );
state_next(196) <= (reset /= '1') and ( state_cur(231) );
state_next(197) <= (reset /= '1') and ( state_cur(218) );
state_next(198) <= (reset /= '1') and ( ( state_cur(78) and not ( (NOT(in1)) = '1' ) ) );
state_next(199) <= (reset /= '1') and ( ( state_cur(120) and not ( (NOT(in0)) = '1' ) ) );
state_next(200) <= (reset /= '1') and ( state_cur(95) );
state_next(201) <= (reset /= '1') and ( state_cur(307) or ( state_cur(201) and (NOT(in0)) = '1' ) );
state_next(202) <= (reset /= '1') and ( state_cur(266) or ( state_cur(202) and (NOT(in0)) = '1' ) );
state_next(203) <= (reset /= '1') and ( state_cur(91) );
state_next(204) <= (reset /= '1') and ( state_cur(123) );
state_next(205) <= (reset /= '1') and ( ( state_cur(211) and not ( (NOT(in0)) = '1' ) ) );
state_next(206) <= (reset /= '1') and ( ( state_cur(136) and not ( (NOT(in0)) = '1' ) ) );
state_next(207) <= (reset /= '1') and ( ( state_cur(207) and (NOT(in0)) = '1' ) or state_cur(205) );
state_next(208) <= (reset /= '1') and ( state_cur(300) );
state_next(209) <= (reset /= '1') and ( state_cur(312) );
state_next(210) <= (reset /= '1') and ( state_cur(292) );
state_next(211) <= (reset /= '1') and ( ( state_cur(211) and (NOT(in0)) = '1' ) or state_cur(185) );
state_next(212) <= (reset /= '1') and ( state_cur(326) );
state_next(213) <= (reset /= '1') and ( state_cur(340) );
state_next(214) <= (reset /= '1') and ( ( state_cur(11) and not ( (NOT(in1)) = '1' ) ) );
state_next(215) <= (reset /= '1') and ( state_cur(229) or ( state_cur(215) and (NOT(in0)) = '1' ) );
state_next(216) <= (reset /= '1') and ( state_cur(248) or ( state_cur(216) and (NOT(in0)) = '1' ) );
state_next(217) <= (reset /= '1') and ( state_cur(271) or ( state_cur(217) and (NOT(in0)) = '1' ) );
state_next(218) <= (reset /= '1') and ( state_cur(146) or state_cur(138) );
state_next(219) <= (reset /= '1') and ( state_cur(151) );
state_next(220) <= (reset /= '1') and ( state_cur(298) );
state_next(221) <= (reset /= '1') and ( ( state_cur(318) and not ( (NOT(in0)) = '1' ) ) );
state_next(222) <= (reset /= '1') and ( state_cur(152) or ( state_cur(141) and not ( (NOT(in2)) = '1' ) ) );
state_next(223) <= (reset /= '1') and ( state_cur(232) );
state_next(224) <= (reset /= '1') and ( state_cur(342) );
state_next(225) <= (reset /= '1') and ( ( state_cur(202) and not ( (NOT(in0)) = '1' ) ) );
state_next(226) <= (reset /= '1') and ( state_cur(311) or ( state_cur(226) and (NOT(in0)) = '1' ) );
state_next(227) <= (reset /= '1') and ( ( state_cur(250) and not ( (NOT(in0)) = '1' ) ) );
state_next(228) <= (reset /= '1') and ( state_cur(189) );
state_next(229) <= (reset /= '1') and ( ( state_cur(216) and not ( (NOT(in0)) = '1' ) ) );
state_next(230) <= (reset /= '1') and ( ( state_cur(176) and not ( (NOT(in0)) = '1' ) ) );
state_next(231) <= (reset /= '1') and ( state_cur(234) );
state_next(232) <= (reset /= '1') and ( state_cur(145) );
state_next(233) <= (reset /= '1') and ( state_cur(236) );
state_next(234) <= (reset /= '1') and ( state_cur(235) );
state_next(235) <= (reset /= '1') and ( state_cur(102) );
state_next(236) <= (reset /= '1') and ( state_cur(237) );
state_next(237) <= (reset /= '1') and ( state_cur(99) );
state_next(238) <= (reset /= '1') and ( ( state_cur(287) and not ( (NOT(in0)) = '1' ) ) );
state_next(239) <= (reset /= '1') and ( ( state_cur(239) and (NOT(in0)) = '1' ) or state_cur(58) );
state_next(240) <= (reset /= '1') and ( state_cur(241) or state_cur(148) );
state_next(241) <= (reset /= '1') and ( ( state_cur(245) and not ( (in8) = '1' ) ) );
state_next(242) <= (reset /= '1') and ( ( state_cur(97) and not ( (NOT(in0)) = '1' ) ) );
state_next(243) <= (reset /= '1') and ( state_cur(275) or ( state_cur(243) and (NOT(in0)) = '1' ) );
state_next(244) <= (reset /= '1') and ( ( state_cur(245) and (in8) = '1' ) );
state_next(245) <= (reset /= '1') and ( state_cur(247) or state_cur(242) );
state_next(246) <= (reset /= '1') and ( state_cur(253) or ( state_cur(246) and (NOT(in0)) = '1' ) );
state_next(247) <= (reset /= '1') and ( ( state_cur(328) and not ( (in11) = '1' ) ) );
state_next(248) <= (reset /= '1') and ( ( state_cur(302) and not ( (NOT(in0)) = '1' ) ) );
state_next(249) <= (reset /= '1') and ( ( state_cur(77) and not ( (NOT(in0)) = '1' ) ) );
state_next(250) <= (reset /= '1') and ( ( state_cur(250) and (NOT(in0)) = '1' ) or state_cur(88) );
state_next(251) <= (reset /= '1') and ( ( state_cur(130) and not ( (NOT(in0)) = '1' ) ) );
state_next(252) <= (reset /= '1') and ( ( state_cur(171) and not ( (NOT(in0)) = '1' ) ) );
state_next(253) <= (reset /= '1') and ( ( state_cur(49) and not ( (NOT(in0)) = '1' ) ) );
state_next(254) <= (reset /= '1') and ( ( state_cur(68) and not ( (NOT(in0)) = '1' ) ) );
state_next(255) <= (reset /= '1') and ( ( state_cur(255) and (NOT(in1)) = '1' ) or state_cur(79) );
state_next(256) <= (reset /= '1') and ( ( state_cur(256) and (NOT(in0)) = '1' ) or state_cur(69) );
state_next(257) <= (reset /= '1') and ( ( state_cur(64) and not ( (NOT(in0)) = '1' ) ) );
state_next(258) <= (reset /= '1') and ( ( state_cur(258) and (NOT(in0)) = '1' ) or state_cur(249) );
state_next(259) <= (reset /= '1') and ( state_cur(283) or ( state_cur(259) and (NOT(in0)) = '1' ) );
state_next(260) <= (reset /= '1') and ( ( state_cur(50) and not ( (NOT(in0)) = '1' ) ) );
state_next(261) <= (reset /= '1') and ( ( state_cur(269) and not ( (NOT(in0)) = '1' ) ) );
state_next(262) <= (reset /= '1') and ( ( state_cur(240) and not ( (in7) = '1' ) ) );
state_next(263) <= (reset /= '1') and ( ( state_cur(263) and (NOT(in0)) = '1' ) or state_cur(19) );
state_next(264) <= (reset /= '1') and ( state_cur(315) or ( state_cur(264) and (NOT(in0)) = '1' ) );
state_next(265) <= (reset /= '1') and ( ( state_cur(124) and not ( (NOT(in0)) = '1' ) ) );
state_next(266) <= (reset /= '1') and ( ( state_cur(87) and not ( (NOT(in0)) = '1' ) ) );
state_next(267) <= (reset /= '1') and ( ( state_cur(243) and not ( (NOT(in0)) = '1' ) ) );
state_next(268) <= (reset /= '1') and ( state_cur(103) );
state_next(269) <= (reset /= '1') and ( ( state_cur(269) and (NOT(in0)) = '1' ) or state_cur(257) );
state_next(270) <= (reset /= '1') and ( state_cur(144) );
state_next(271) <= (reset /= '1') and ( ( state_cur(28) and not ( (NOT(in0)) = '1' ) ) );
state_next(272) <= (reset /= '1') and ( ( state_cur(272) and (NOT(in0)) = '1' ) or state_cur(225) );
state_next(273) <= (reset /= '1') and ( ( state_cur(220) and (in6) = '1' ) );
state_next(274) <= (reset /= '1') and ( state_cur(134) );
state_next(275) <= (reset /= '1') and ( ( state_cur(75) and not ( (NOT(in0)) = '1' ) ) );
state_next(276) <= (reset /= '1') and ( (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) );
state_next(277) <= (reset /= '1') and ( ( state_cur(67) and not ( (NOT(in0)) = '1' ) ) );
state_next(278) <= (reset /= '1') and ( ( state_cur(278) and (NOT(in0)) = '1' ) or state_cur(265) );
state_next(279) <= (reset /= '1') and ( ( state_cur(279) and (NOT(in0)) = '1' ) or state_cur(3) );
state_next(280) <= (reset /= '1') and ( state_cur(281) );
state_next(281) <= (reset /= '1') and ( ( state_cur(208) and not ( (in5) = '1' ) ) );
state_next(282) <= (reset /= '1') and ( state_cur(100) );
state_next(283) <= (reset /= '1') and ( ( state_cur(10) and not ( (NOT(in0)) = '1' ) ) );
state_next(284) <= (reset /= '1') and ( ( state_cur(264) and not ( (NOT(in0)) = '1' ) ) );
state_next(285) <= (reset /= '1') and ( state_cur(286) or ( state_cur(285) and (NOT(in0)) = '1' ) );
state_next(286) <= (reset /= '1') and ( ( state_cur(313) and not ( (NOT(in0)) = '1' ) ) );
state_next(287) <= (reset /= '1') and ( ( state_cur(287) and (NOT(in0)) = '1' ) or state_cur(177) );
state_next(288) <= (reset /= '1') and ( ( state_cur(288) and (NOT(in0)) = '1' ) or state_cur(45) );
state_next(289) <= (reset /= '1') and ( state_cur(210) );
state_next(290) <= (reset /= '1') and ( (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) );
state_next(291) <= (reset /= '1') and ( ( state_cur(240) and (in7) = '1' ) );
state_next(292) <= (reset /= '1') and ( state_cur(147) );
state_next(293) <= (reset /= '1') and ( ( state_cur(295) and not ( (NOT(in0)) = '1' ) ) );
state_next(294) <= (reset /= '1') and ( state_cur(132) );
state_next(295) <= (reset /= '1') and ( ( state_cur(295) and (NOT(in0)) = '1' ) or state_cur(113) );
state_next(296) <= (reset /= '1') and ( state_cur(268) or state_cur(178) );
state_next(297) <= (reset /= '1') and ( ( state_cur(297) and (NOT(in0)) = '1' ) or state_cur(0) );
state_next(298) <= (reset /= '1') and ( state_cur(143) );
state_next(299) <= (reset /= '1') and ( ( state_cur(194) and not ( (NOT(in0)) = '1' ) ) );
state_next(300) <= (reset /= '1') and ( state_cur(142) );
state_next(301) <= (reset /= '1') and ( state_cur(108) );
state_next(302) <= (reset /= '1') and ( ( state_cur(302) and (NOT(in0)) = '1' ) or state_cur(299) );
state_next(303) <= (reset /= '1') and ( rtmcmp128 );
state_next(304) <= (reset /= '1') and ( ( state_cur(304) and (NOT(in0)) = '1' ) or state_cur(39) );
state_next(305) <= (reset /= '1') and ( ( state_cur(305) and (NOT(in0)) = '1' ) or state_cur(30) );
state_next(306) <= (reset /= '1') and ( state_cur(209) );
state_next(307) <= (reset /= '1') and ( ( state_cur(192) and not ( (NOT(in0)) = '1' ) ) );
state_next(308) <= (reset /= '1') and ( ( state_cur(325) and not ( (in10) = '1' ) ) );
state_next(309) <= (reset /= '1') and ( ( state_cur(122) and not ( (NOT(in0)) = '1' ) ) );
state_next(310) <= (reset /= '1') and ( state_cur(308) or state_cur(196) );
state_next(311) <= (reset /= '1') and ( ( state_cur(84) and not ( (NOT(in0)) = '1' ) ) );
state_next(312) <= (reset /= '1') and ( state_cur(119) );
state_next(313) <= (reset /= '1') and ( state_cur(330) or ( state_cur(313) and (NOT(in0)) = '1' ) );
state_next(314) <= (reset /= '1') and ( ( state_cur(314) and (NOT(in0)) = '1' ) or state_cur(59) );
state_next(315) <= (reset /= '1') and ( ( state_cur(121) and not ( (NOT(in0)) = '1' ) ) );
state_next(316) <= (reset /= '1') and ( ( state_cur(316) and (NOT(in0)) = '1' ) or state_cur(63) );
state_next(317) <= (reset /= '1') and ( ( state_cur(317) and (NOT(in0)) = '1' ) or state_cur(74) );
state_next(318) <= (reset /= '1') and ( ( state_cur(318) and (NOT(in0)) = '1' ) or state_cur(262) );
state_next(319) <= (reset /= '1') and ( state_cur(338) );
state_next(320) <= (reset /= '1') and ( ( state_cur(320) and (NOT(in0)) = '1' ) or state_cur(131) );
state_next(321) <= (reset /= '1') and ( ( state_cur(316) and not ( (NOT(in0)) = '1' ) ) );
state_next(322) <= (reset /= '1') and ( state_cur(212) );
state_next(323) <= (reset /= '1') and ( ( state_cur(323) and (NOT(in0)) = '1' ) or state_cur(309) );
state_next(324) <= (reset /= '1') and ( ( state_cur(324) and (NOT(in0)) = '1' ) or state_cur(238) );
state_next(325) <= (reset /= '1') and ( state_cur(109) );
state_next(326) <= (reset /= '1') and ( state_cur(107) );
state_next(327) <= (reset /= '1') and ( ( state_cur(215) and not ( (NOT(in0)) = '1' ) ) );
state_next(328) <= (reset /= '1') and ( state_cur(219) or state_cur(125) );
state_next(329) <= (reset /= '1') and ( ( state_cur(305) and not ( (NOT(in0)) = '1' ) ) );
state_next(330) <= (reset /= '1') and ( ( state_cur(317) and not ( (NOT(in0)) = '1' ) ) );
state_next(331) <= (reset /= '1') and ( state_cur(213) );
state_next(332) <= (reset /= '1') and ( state_cur(335) );
state_next(333) <= (reset /= '1') and ( ( state_cur(150) and not ( (in3) = '1' ) ) );
state_next(334) <= (reset /= '1') and ( state_cur(96) );
state_next(335) <= (reset /= '1') and ( state_cur(182) );
state_next(336) <= (reset /= '1') and ( ( state_cur(328) and (in11) = '1' ) );
state_next(337) <= (reset /= '1') and ( rtmcmp92 );
state_next(338) <= (reset /= '1') and ( state_cur(193) );
state_next(339) <= (reset /= '1') and ( state_cur(94) );
state_next(340) <= (reset /= '1') and ( state_cur(93) );
state_next(341) <= (reset /= '1') and ( state_cur(522) );
state_next(342) <= (reset /= '1') and ( state_cur(341) );
state_next(343) <= (reset /= '1') and ( state_cur(344) or ( state_cur(343) and (NOT(in1)) = '1' ) );
state_next(344) <= (reset /= '1') and ( ( state_cur(345) and not ( (NOT(in1)) = '1' ) ) );
state_next(345) <= (reset /= '1') and ( state_cur(346) or ( state_cur(345) and (NOT(in1)) = '1' ) );
state_next(346) <= (reset /= '1') and ( ( state_cur(347) and not ( (NOT(in1)) = '1' ) ) );
state_next(347) <= (reset /= '1') and ( state_cur(348) or ( state_cur(347) and (NOT(in1)) = '1' ) );
state_next(348) <= (reset /= '1') and ( ( state_cur(349) and not ( (NOT(in1)) = '1' ) ) );
state_next(349) <= (reset /= '1') and ( state_cur(350) or ( state_cur(349) and (NOT(in1)) = '1' ) );
state_next(350) <= (reset /= '1') and ( ( state_cur(351) and not ( (NOT(in1)) = '1' ) ) );
state_next(351) <= (reset /= '1') and ( state_cur(352) or ( state_cur(351) and (NOT(in1)) = '1' ) );
state_next(352) <= (reset /= '1') and ( ( state_cur(353) and not ( (NOT(in1)) = '1' ) ) );
state_next(353) <= (reset /= '1') and ( state_cur(354) or ( state_cur(353) and (NOT(in1)) = '1' ) );
state_next(354) <= (reset /= '1') and ( ( state_cur(355) and not ( (NOT(in1)) = '1' ) ) );
state_next(355) <= (reset /= '1') and ( state_cur(356) or ( state_cur(355) and (NOT(in1)) = '1' ) );
state_next(356) <= (reset /= '1') and ( ( state_cur(357) and not ( (NOT(in1)) = '1' ) ) );
state_next(357) <= (reset /= '1') and ( state_cur(358) or ( state_cur(357) and (NOT(in1)) = '1' ) );
state_next(358) <= (reset /= '1') and ( ( state_cur(359) and not ( (NOT(in1)) = '1' ) ) );
state_next(359) <= (reset /= '1') and ( state_cur(360) or ( state_cur(359) and (NOT(in1)) = '1' ) );
state_next(360) <= (reset /= '1') and ( ( state_cur(361) and not ( (NOT(in1)) = '1' ) ) );
state_next(361) <= (reset /= '1') and ( state_cur(362) or ( state_cur(361) and (NOT(in1)) = '1' ) );
state_next(362) <= (reset /= '1') and ( ( state_cur(363) and not ( (NOT(in1)) = '1' ) ) );
state_next(363) <= (reset /= '1') and ( state_cur(364) or ( state_cur(363) and (NOT(in1)) = '1' ) );
state_next(364) <= (reset /= '1') and ( ( state_cur(365) and not ( (NOT(in1)) = '1' ) ) );
state_next(365) <= (reset /= '1') and ( state_cur(366) or ( state_cur(365) and (NOT(in1)) = '1' ) );
state_next(366) <= (reset /= '1') and ( ( state_cur(367) and not ( (NOT(in1)) = '1' ) ) );
state_next(367) <= (reset /= '1') and ( state_cur(368) or ( state_cur(367) and (NOT(in1)) = '1' ) );
state_next(368) <= (reset /= '1') and ( ( state_cur(369) and not ( (NOT(in1)) = '1' ) ) );
state_next(369) <= (reset /= '1') and ( state_cur(370) or ( state_cur(369) and (NOT(in1)) = '1' ) );
state_next(370) <= (reset /= '1') and ( ( state_cur(371) and not ( (NOT(in1)) = '1' ) ) );
state_next(371) <= (reset /= '1') and ( state_cur(372) or ( state_cur(371) and (NOT(in1)) = '1' ) );
state_next(372) <= (reset /= '1') and ( ( state_cur(373) and not ( (NOT(in1)) = '1' ) ) );
state_next(373) <= (reset /= '1') and ( state_cur(374) or ( state_cur(373) and (NOT(in1)) = '1' ) );
state_next(374) <= (reset /= '1') and ( ( state_cur(375) and not ( (NOT(in1)) = '1' ) ) );
state_next(375) <= (reset /= '1') and ( state_cur(376) or ( state_cur(375) and (NOT(in1)) = '1' ) );
state_next(376) <= (reset /= '1') and ( ( state_cur(377) and not ( (NOT(in1)) = '1' ) ) );
state_next(377) <= (reset /= '1') and ( state_cur(378) or ( state_cur(377) and (NOT(in1)) = '1' ) );
state_next(378) <= (reset /= '1') and ( ( state_cur(379) and not ( (NOT(in1)) = '1' ) ) );
state_next(379) <= (reset /= '1') and ( state_cur(380) or ( state_cur(379) and (NOT(in1)) = '1' ) );
state_next(380) <= (reset /= '1') and ( ( state_cur(381) and not ( (NOT(in1)) = '1' ) ) );
state_next(381) <= (reset /= '1') and ( state_cur(382) or ( state_cur(381) and (NOT(in1)) = '1' ) );
state_next(382) <= (reset /= '1') and ( ( state_cur(383) and not ( (NOT(in1)) = '1' ) ) );
state_next(383) <= (reset /= '1') and ( state_cur(384) or ( state_cur(383) and (NOT(in1)) = '1' ) );
state_next(384) <= (reset /= '1') and ( ( state_cur(385) and not ( (NOT(in1)) = '1' ) ) );
state_next(385) <= (reset /= '1') and ( state_cur(386) or ( state_cur(385) and (NOT(in1)) = '1' ) );
state_next(386) <= (reset /= '1') and ( ( state_cur(387) and not ( (NOT(in1)) = '1' ) ) );
state_next(387) <= (reset /= '1') and ( state_cur(388) or ( state_cur(387) and (NOT(in1)) = '1' ) );
state_next(388) <= (reset /= '1') and ( ( state_cur(389) and not ( (NOT(in1)) = '1' ) ) );
state_next(389) <= (reset /= '1') and ( state_cur(390) or ( state_cur(389) and (NOT(in1)) = '1' ) );
state_next(390) <= (reset /= '1') and ( ( state_cur(391) and not ( (NOT(in1)) = '1' ) ) );
state_next(391) <= (reset /= '1') and ( state_cur(392) or ( state_cur(391) and (NOT(in1)) = '1' ) );
state_next(392) <= (reset /= '1') and ( ( state_cur(393) and not ( (NOT(in1)) = '1' ) ) );
state_next(393) <= (reset /= '1') and ( state_cur(394) or ( state_cur(393) and (NOT(in1)) = '1' ) );
state_next(394) <= (reset /= '1') and ( ( state_cur(395) and not ( (NOT(in1)) = '1' ) ) );
state_next(395) <= (reset /= '1') and ( state_cur(396) or ( state_cur(395) and (NOT(in1)) = '1' ) );
state_next(396) <= (reset /= '1') and ( ( state_cur(397) and not ( (NOT(in1)) = '1' ) ) );
state_next(397) <= (reset /= '1') and ( state_cur(398) or ( state_cur(397) and (NOT(in1)) = '1' ) );
state_next(398) <= (reset /= '1') and ( ( state_cur(399) and not ( (NOT(in1)) = '1' ) ) );
state_next(399) <= (reset /= '1') and ( state_cur(400) or ( state_cur(399) and (NOT(in1)) = '1' ) );
state_next(400) <= (reset /= '1') and ( ( state_cur(401) and not ( (NOT(in1)) = '1' ) ) );
state_next(401) <= (reset /= '1') and ( state_cur(402) or ( state_cur(401) and (NOT(in1)) = '1' ) );
state_next(402) <= (reset /= '1') and ( ( state_cur(403) and not ( (NOT(in1)) = '1' ) ) );
state_next(403) <= (reset /= '1') and ( state_cur(404) or ( state_cur(403) and (NOT(in1)) = '1' ) );
state_next(404) <= (reset /= '1') and ( ( state_cur(405) and not ( (NOT(in1)) = '1' ) ) );
state_next(405) <= (reset /= '1') and ( state_cur(406) or ( state_cur(405) and (NOT(in1)) = '1' ) );
state_next(406) <= (reset /= '1') and ( ( state_cur(407) and not ( (NOT(in1)) = '1' ) ) );
state_next(407) <= (reset /= '1') and ( state_cur(408) or ( state_cur(407) and (NOT(in1)) = '1' ) );
state_next(408) <= (reset /= '1') and ( ( state_cur(409) and not ( (NOT(in1)) = '1' ) ) );
state_next(409) <= (reset /= '1') and ( state_cur(410) or ( state_cur(409) and (NOT(in1)) = '1' ) );
state_next(410) <= (reset /= '1') and ( ( state_cur(411) and not ( (NOT(in1)) = '1' ) ) );
state_next(411) <= (reset /= '1') and ( state_cur(412) or ( state_cur(411) and (NOT(in1)) = '1' ) );
state_next(412) <= (reset /= '1') and ( ( state_cur(413) and not ( (NOT(in1)) = '1' ) ) );
state_next(413) <= (reset /= '1') and ( state_cur(414) or ( state_cur(413) and (NOT(in1)) = '1' ) );
state_next(414) <= (reset /= '1') and ( ( state_cur(415) and not ( (NOT(in1)) = '1' ) ) );
state_next(415) <= (reset /= '1') and ( state_cur(416) or ( state_cur(415) and (NOT(in1)) = '1' ) );
state_next(416) <= (reset /= '1') and ( ( state_cur(417) and not ( (NOT(in1)) = '1' ) ) );
state_next(417) <= (reset /= '1') and ( state_cur(418) or ( state_cur(417) and (NOT(in1)) = '1' ) );
state_next(418) <= (reset /= '1') and ( ( state_cur(419) and not ( (NOT(in1)) = '1' ) ) );
state_next(419) <= (reset /= '1') and ( state_cur(420) or ( state_cur(419) and (NOT(in1)) = '1' ) );
state_next(420) <= (reset /= '1') and ( ( state_cur(421) and not ( (NOT(in1)) = '1' ) ) );
state_next(421) <= (reset /= '1') and ( state_cur(422) or ( state_cur(421) and (NOT(in1)) = '1' ) );
state_next(422) <= (reset /= '1') and ( ( state_cur(423) and not ( (NOT(in1)) = '1' ) ) );
state_next(423) <= (reset /= '1') and ( state_cur(424) or ( state_cur(423) and (NOT(in1)) = '1' ) );
state_next(424) <= (reset /= '1') and ( ( state_cur(425) and not ( (NOT(in1)) = '1' ) ) );
state_next(425) <= (reset /= '1') and ( state_cur(426) or ( state_cur(425) and (NOT(in1)) = '1' ) );
state_next(426) <= (reset /= '1') and ( ( state_cur(427) and not ( (NOT(in1)) = '1' ) ) );
state_next(427) <= (reset /= '1') and ( state_cur(428) or ( state_cur(427) and (NOT(in1)) = '1' ) );
state_next(428) <= (reset /= '1') and ( ( state_cur(429) and not ( (NOT(in1)) = '1' ) ) );
state_next(429) <= (reset /= '1') and ( state_cur(430) or ( state_cur(429) and (NOT(in1)) = '1' ) );
state_next(430) <= (reset /= '1') and ( ( state_cur(431) and not ( (NOT(in1)) = '1' ) ) );
state_next(431) <= (reset /= '1') and ( state_cur(432) or ( state_cur(431) and (NOT(in1)) = '1' ) );
state_next(432) <= (reset /= '1') and ( ( state_cur(433) and not ( (NOT(in1)) = '1' ) ) );
state_next(433) <= (reset /= '1') and ( state_cur(434) or ( state_cur(433) and (NOT(in1)) = '1' ) );
state_next(434) <= (reset /= '1') and ( ( state_cur(435) and not ( (NOT(in1)) = '1' ) ) );
state_next(435) <= (reset /= '1') and ( state_cur(436) or ( state_cur(435) and (NOT(in1)) = '1' ) );
state_next(436) <= (reset /= '1') and ( ( state_cur(437) and not ( (NOT(in1)) = '1' ) ) );
state_next(437) <= (reset /= '1') and ( state_cur(438) or ( state_cur(437) and (NOT(in1)) = '1' ) );
state_next(438) <= (reset /= '1') and ( ( state_cur(439) and not ( (NOT(in1)) = '1' ) ) );
state_next(439) <= (reset /= '1') and ( state_cur(440) or ( state_cur(439) and (NOT(in1)) = '1' ) );
state_next(440) <= (reset /= '1') and ( ( state_cur(441) and not ( (NOT(in1)) = '1' ) ) );
state_next(441) <= (reset /= '1') and ( state_cur(442) or ( state_cur(441) and (NOT(in1)) = '1' ) );
state_next(442) <= (reset /= '1') and ( ( state_cur(443) and not ( (NOT(in1)) = '1' ) ) );
state_next(443) <= (reset /= '1') and ( state_cur(444) or ( state_cur(443) and (NOT(in1)) = '1' ) );
state_next(444) <= (reset /= '1') and ( ( state_cur(445) and not ( (NOT(in1)) = '1' ) ) );
state_next(445) <= (reset /= '1') and ( state_cur(446) or ( state_cur(445) and (NOT(in1)) = '1' ) );
state_next(446) <= (reset /= '1') and ( ( state_cur(447) and not ( (NOT(in1)) = '1' ) ) );
state_next(447) <= (reset /= '1') and ( state_cur(448) or ( state_cur(447) and (NOT(in1)) = '1' ) );
state_next(448) <= (reset /= '1') and ( ( state_cur(449) and not ( (NOT(in1)) = '1' ) ) );
state_next(449) <= (reset /= '1') and ( state_cur(450) or ( state_cur(449) and (NOT(in1)) = '1' ) );
state_next(450) <= (reset /= '1') and ( ( state_cur(451) and not ( (NOT(in1)) = '1' ) ) );
state_next(451) <= (reset /= '1') and ( state_cur(452) or ( state_cur(451) and (NOT(in1)) = '1' ) );
state_next(452) <= (reset /= '1') and ( ( state_cur(453) and not ( (NOT(in1)) = '1' ) ) );
state_next(453) <= (reset /= '1') and ( state_cur(454) or ( state_cur(453) and (NOT(in1)) = '1' ) );
state_next(454) <= (reset /= '1') and ( ( state_cur(455) and not ( (NOT(in1)) = '1' ) ) );
state_next(455) <= (reset /= '1') and ( state_cur(456) or ( state_cur(455) and (NOT(in1)) = '1' ) );
state_next(456) <= (reset /= '1') and ( ( state_cur(457) and not ( (NOT(in1)) = '1' ) ) );
state_next(457) <= (reset /= '1') and ( state_cur(458) or ( state_cur(457) and (NOT(in1)) = '1' ) );
state_next(458) <= (reset /= '1') and ( ( state_cur(459) and not ( (NOT(in1)) = '1' ) ) );
state_next(459) <= (reset /= '1') and ( state_cur(460) or ( state_cur(459) and (NOT(in1)) = '1' ) );
state_next(460) <= (reset /= '1') and ( ( state_cur(461) and not ( (NOT(in1)) = '1' ) ) );
state_next(461) <= (reset /= '1') and ( state_cur(462) or ( state_cur(461) and (NOT(in1)) = '1' ) );
state_next(462) <= (reset /= '1') and ( ( state_cur(463) and not ( (NOT(in1)) = '1' ) ) );
state_next(463) <= (reset /= '1') and ( state_cur(464) or ( state_cur(463) and (NOT(in1)) = '1' ) );
state_next(464) <= (reset /= '1') and ( ( state_cur(465) and not ( (NOT(in1)) = '1' ) ) );
state_next(465) <= (reset /= '1') and ( state_cur(466) or ( state_cur(465) and (NOT(in1)) = '1' ) );
state_next(466) <= (reset /= '1') and ( ( state_cur(467) and not ( (NOT(in1)) = '1' ) ) );
state_next(467) <= (reset /= '1') and ( state_cur(468) or ( state_cur(467) and (NOT(in1)) = '1' ) );
state_next(468) <= (reset /= '1') and ( ( state_cur(469) and not ( (NOT(in1)) = '1' ) ) );
state_next(469) <= (reset /= '1') and ( state_cur(470) or ( state_cur(469) and (NOT(in1)) = '1' ) );
state_next(470) <= (reset /= '1') and ( ( state_cur(471) and not ( (NOT(in1)) = '1' ) ) );
state_next(471) <= (reset /= '1') and ( state_cur(472) or ( state_cur(471) and (NOT(in1)) = '1' ) );
state_next(472) <= (reset /= '1') and ( ( state_cur(473) and not ( (NOT(in1)) = '1' ) ) );
state_next(473) <= (reset /= '1') and ( state_cur(474) or ( state_cur(473) and (NOT(in1)) = '1' ) );
state_next(474) <= (reset /= '1') and ( ( state_cur(475) and not ( (NOT(in1)) = '1' ) ) );
state_next(475) <= (reset /= '1') and ( state_cur(476) or ( state_cur(475) and (NOT(in1)) = '1' ) );
state_next(476) <= (reset /= '1') and ( ( state_cur(477) and not ( (NOT(in1)) = '1' ) ) );
state_next(477) <= (reset /= '1') and ( state_cur(478) or ( state_cur(477) and (NOT(in1)) = '1' ) );
state_next(478) <= (reset /= '1') and ( ( state_cur(479) and not ( (NOT(in1)) = '1' ) ) );
state_next(479) <= (reset /= '1') and ( state_cur(480) or ( state_cur(479) and (NOT(in1)) = '1' ) );
state_next(480) <= (reset /= '1') and ( ( state_cur(481) and not ( (NOT(in1)) = '1' ) ) );
state_next(481) <= (reset /= '1') and ( state_cur(482) or ( state_cur(481) and (NOT(in1)) = '1' ) );
state_next(482) <= (reset /= '1') and ( ( state_cur(483) and not ( (NOT(in1)) = '1' ) ) );
state_next(483) <= (reset /= '1') and ( state_cur(484) or ( state_cur(483) and (NOT(in1)) = '1' ) );
state_next(484) <= (reset /= '1') and ( ( state_cur(485) and not ( (NOT(in1)) = '1' ) ) );
state_next(485) <= (reset /= '1') and ( state_cur(486) or ( state_cur(485) and (NOT(in1)) = '1' ) );
state_next(486) <= (reset /= '1') and ( ( state_cur(487) and not ( (NOT(in1)) = '1' ) ) );
state_next(487) <= (reset /= '1') and ( state_cur(488) or ( state_cur(487) and (NOT(in1)) = '1' ) );
state_next(488) <= (reset /= '1') and ( ( state_cur(489) and not ( (NOT(in1)) = '1' ) ) );
state_next(489) <= (reset /= '1') and ( state_cur(490) or ( state_cur(489) and (NOT(in1)) = '1' ) );
state_next(490) <= (reset /= '1') and ( ( state_cur(491) and not ( (NOT(in1)) = '1' ) ) );
state_next(491) <= (reset /= '1') and ( state_cur(492) or ( state_cur(491) and (NOT(in1)) = '1' ) );
state_next(492) <= (reset /= '1') and ( ( state_cur(493) and not ( (NOT(in1)) = '1' ) ) );
state_next(493) <= (reset /= '1') and ( state_cur(494) or ( state_cur(493) and (NOT(in1)) = '1' ) );
state_next(494) <= (reset /= '1') and ( ( state_cur(495) and not ( (NOT(in1)) = '1' ) ) );
state_next(495) <= (reset /= '1') and ( state_cur(496) or ( state_cur(495) and (NOT(in1)) = '1' ) );
state_next(496) <= (reset /= '1') and ( ( state_cur(497) and not ( (NOT(in1)) = '1' ) ) );
state_next(497) <= (reset /= '1') and ( state_cur(498) or ( state_cur(497) and (NOT(in1)) = '1' ) );
state_next(498) <= (reset /= '1') and ( ( state_cur(499) and not ( (NOT(in1)) = '1' ) ) );
state_next(499) <= (reset /= '1') and ( state_cur(500) or ( state_cur(499) and (NOT(in1)) = '1' ) );
state_next(500) <= (reset /= '1') and ( ( state_cur(501) and not ( (NOT(in1)) = '1' ) ) );
state_next(501) <= (reset /= '1') and ( state_cur(502) or ( state_cur(501) and (NOT(in1)) = '1' ) );
state_next(502) <= (reset /= '1') and ( ( state_cur(503) and not ( (NOT(in1)) = '1' ) ) );
state_next(503) <= (reset /= '1') and ( state_cur(504) or ( state_cur(503) and (NOT(in1)) = '1' ) );
state_next(504) <= (reset /= '1') and ( ( state_cur(505) and not ( (NOT(in1)) = '1' ) ) );
state_next(505) <= (reset /= '1') and ( state_cur(506) or ( state_cur(505) and (NOT(in1)) = '1' ) );
state_next(506) <= (reset /= '1') and ( ( state_cur(507) and not ( (NOT(in1)) = '1' ) ) );
state_next(507) <= (reset /= '1') and ( state_cur(508) or ( state_cur(507) and (NOT(in1)) = '1' ) );
state_next(508) <= (reset /= '1') and ( ( state_cur(509) and not ( (NOT(in1)) = '1' ) ) );
state_next(509) <= (reset /= '1') and ( state_cur(510) or ( state_cur(509) and (NOT(in1)) = '1' ) );
state_next(510) <= (reset /= '1') and ( ( state_cur(511) and not ( (NOT(in1)) = '1' ) ) );
state_next(511) <= (reset /= '1') and ( state_cur(512) or ( state_cur(511) and (NOT(in1)) = '1' ) );
state_next(512) <= (reset /= '1') and ( ( state_cur(513) and not ( (NOT(in1)) = '1' ) ) );
state_next(513) <= (reset /= '1') and ( state_cur(514) or ( state_cur(513) and (NOT(in1)) = '1' ) );
state_next(514) <= (reset /= '1') and ( ( state_cur(515) and not ( (NOT(in1)) = '1' ) ) );
state_next(515) <= (reset /= '1') and ( state_cur(516) or ( state_cur(515) and (NOT(in1)) = '1' ) );
state_next(516) <= (reset /= '1') and ( ( state_cur(517) and not ( (NOT(in1)) = '1' ) ) );
state_next(517) <= (reset /= '1') and ( state_cur(518) or ( state_cur(517) and (NOT(in1)) = '1' ) );
state_next(518) <= (reset /= '1') and ( ( state_cur(519) and not ( (NOT(in1)) = '1' ) ) );
state_next(519) <= (reset /= '1') and ( ( state_cur(519) and (NOT(in1)) = '1' ) or state_cur(1) );
state_next(520) <= (reset /= '1') and ( ( state_cur(520) and (NOT(in1)) = '1' ) or state_cur(73) );
state_next(521) <= (reset /= '1') and ( ( state_cur(521) and (NOT(in1)) = '1' ) or state_cur(71) );
state_next(522) <= (reset /= '1') and ( ( state_cur(220) and not ( (in6) = '1' ) ) );
state_next(523) <= (reset /= '1') and ( state_cur(149) );
-- Assignment of buffers for buffered outputs
out386_bufn <= state_cur(186) or state_cur(270);
out404_bufn <= (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or state_cur(173);
out457_bufn <= state_cur(142) or state_cur(190) or state_cur(169);
out841_bufn <= rtmcmp92 or state_cur(189);
out276_bufn <= state_cur(233) or state_cur(274);
out67_bufn <= state_cur(189) or state_cur(282) or state_cur(98) or state_cur(203) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out239_bufn <= ( state_cur(240) and (in7) = '1' ) or state_cur(523) or state_cur(129);
out259_bufn <= state_cur(268) or state_cur(178) or ( state_cur(220) and (in6) = '1' ) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(523) or state_cur(129);
out416_bufn <= state_cur(338) or state_cur(143) or state_cur(289) or state_cur(322);
out646_bufn <= state_cur(340) or state_cur(326);
out485_bufn <= ( state_cur(240) and (in7) = '1' ) or ( state_cur(150) and (in3) = '1' );
out935_bufn <= state_cur(193) or state_cur(134);
out463_bufn <= state_cur(338) or state_cur(119) or state_cur(134) or state_cur(233) or state_cur(174);
out120_bufn <= rtmcmp92 or state_cur(100) or state_cur(91) or state_cur(179) or state_cur(228);
out293_bufn <= state_cur(342) or state_cur(303);
out216_bufn <= state_cur(107) or state_cur(212) or rtmcmp128 or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(326) or state_cur(123) or state_cur(190) or state_cur(186) or rtmcmp290 or state_cur(204) or state_cur(191) or state_cur(303) or rtmcmp276;
out319_bufn <= (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(99) or state_cur(218) or (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296);
out230_bufn <= ( state_cur(220) and (in6) = '1' ) or state_cur(224);
out1_bufn <= ( state_cur(317) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(305) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(215) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(316) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(121) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(84) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(122) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(192) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(194) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(295) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(313) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(264) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(10) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(67) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(75) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(28) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(243) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(87) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(124) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(240) and not ( (in7) = '1' ) ) or ( state_cur(269) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(50) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(64) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(68) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(49) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(171) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(130) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(77) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(302) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(287) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(176) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(216) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(250) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(202) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(318) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(136) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(211) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(120) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(135) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(226) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(279) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(55) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(167) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(165) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(163) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(161) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(159) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(157) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(155) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(101) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(116) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(118) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(127) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(314) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(304) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(112) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(140) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(288) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(217) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(80) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(272) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(297) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(278) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(258) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(256) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(24) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(65) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(246) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(61) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(12) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(104) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(21) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(51) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(52) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(46) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(37) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(41) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(285) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(323) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(35) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(34) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(259) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(33) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(324) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(320) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(117) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(26) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(27) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(14) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(239) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(188) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(263) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(13) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(17) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(207) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(6) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(48) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(201) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(44) and not ( (NOT(in0)) = '1' ) ) or ( state_cur(90) and not ( (NOT(in0)) = '1' ) );
out93_bufn <= state_cur(522) or state_cur(93) or state_cur(96) or state_cur(108) or ( state_cur(220) and (in6) = '1' ) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or ( state_cur(150) and (in3) = '1' ) or state_cur(187) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(334) or state_cur(339);
out89_bufn <= state_cur(149) or state_cur(341) or state_cur(522) or state_cur(93) or state_cur(94) or state_cur(96) or state_cur(213) or state_cur(108) or state_cur(281) or state_cur(103) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or state_cur(183) or state_cur(280) or state_cur(187) or state_cur(331) or state_cur(224) or state_cur(301) or state_cur(200) or state_cur(333) or state_cur(334) or state_cur(339);
out539_bufn <= state_cur(142) or state_cur(190);
out62_bufn <= state_cur(193) or rtmcmp92 or state_cur(107) or state_cur(212) or state_cur(338) or state_cur(119) or rtmcmp128 or state_cur(100) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114) or state_cur(134) or state_cur(236) or state_cur(189) or state_cur(326) or state_cur(312) or state_cur(123) or state_cur(91) or state_cur(233) or state_cur(190) or state_cur(186) or state_cur(179) or rtmcmp290 or state_cur(282) or state_cur(319) or state_cur(174) or state_cur(204) or state_cur(172) or state_cur(191) or state_cur(303) or state_cur(274) or rtmcmp276 or state_cur(98) or state_cur(203) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out856_bufn <= state_cur(107) or state_cur(147) or state_cur(236);
out451_bufn <= state_cur(123) or state_cur(169);
out287_bufn <= state_cur(332) or state_cur(303);
out315_bufn <= state_cur(268) or state_cur(178) or (state_cur(128) = '1' and rtmcmp128 = '0') or state_cur(296);
out536_bufn <= state_cur(95) or state_cur(190);
out209_bufn <= state_cur(191) or state_cur(200);
out221_bufn <= rtmcmp128 or state_cur(237) or state_cur(197) or rtmcmp276;
out283_bufn <= state_cur(193) or state_cur(236) or state_cur(312) or state_cur(319) or state_cur(172) or state_cur(274);
out368_bufn <= state_cur(213) or ( state_cur(175) and (in4) = '1' );
out516_bufn <= ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or state_cur(183) or state_cur(280);
out393_bufn <= state_cur(193) or state_cur(212) or state_cur(338) or state_cur(143) or state_cur(210) or state_cur(289) or state_cur(322) or state_cur(204);
out1008_bufn <= state_cur(182) or state_cur(268) or state_cur(178);
out392_bufn <= state_cur(108) or state_cur(204);
out261_bufn <= state_cur(268) or state_cur(178) or state_cur(523) or state_cur(129);
out559_bufn <= state_cur(99) or state_cur(218);
out543_bufn <= state_cur(326) or state_cur(292) or state_cur(123) or state_cur(233);
out895_bufn <= state_cur(219) or state_cur(125) or state_cur(247) or state_cur(242) or state_cur(241) or state_cur(148);
out82_bufn <= ( state_cur(208) and (in5) = '1' ) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out220_bufn <= state_cur(107) or rtmcmp128 or state_cur(147) or state_cur(237) or state_cur(236) or state_cur(197) or rtmcmp276;
out95_bufn <= state_cur(522) or state_cur(93) or state_cur(96) or state_cur(108) or state_cur(342) or state_cur(340) or state_cur(95) or state_cur(184) or state_cur(187) or state_cur(334) or state_cur(339);
out943_bufn <= (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out465_bufn <= state_cur(319) or state_cur(174);
out238_bufn <= ( state_cur(175) and (in4) = '1' ) or state_cur(523) or state_cur(129);
out1025_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(268) or state_cur(178);
out132_bufn <= state_cur(146) or state_cur(138) or state_cur(273) or state_cur(105);
out79_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(98) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out500_bufn <= state_cur(91) or state_cur(282);
out65_bufn <= state_cur(179) or state_cur(337);
out111_bufn <= state_cur(96) or state_cur(95) or state_cur(334);
out420_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(306);
out1076_bufn <= state_cur(93) or state_cur(107);
out101_bufn <= state_cur(523) or state_cur(129) or ( state_cur(175) and not ( (in4) = '1' ) );
out106_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(94) or ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(213) or ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or state_cur(183) or state_cur(280) or state_cur(224) or state_cur(200) or state_cur(333) or ( state_cur(175) and not ( (in4) = '1' ) );
out68_bufn <= state_cur(193) or rtmcmp92 or state_cur(338) or state_cur(119) or state_cur(100) or state_cur(134) or state_cur(236) or state_cur(189) or state_cur(312) or state_cur(91) or state_cur(233) or state_cur(179) or state_cur(282) or state_cur(319) or state_cur(174) or state_cur(172) or state_cur(274) or state_cur(98) or state_cur(203) or state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out1069_bufn <= state_cur(213) or state_cur(212);
out77_bufn <= state_cur(228) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336);
out102_bufn <= state_cur(94) or state_cur(213) or ( state_cur(175) and not ( (in4) = '1' ) );
out394_bufn <= state_cur(193) or state_cur(212) or state_cur(210) or state_cur(204);
out342_bufn <= ( state_cur(220) and (in6) = '1' ) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' );
out104_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(94) or ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(213) or ( state_cur(208) and not ( (in5) = '1' ) ) or state_cur(281) or ( state_cur(220) and (in6) = '1' ) or state_cur(146) or state_cur(138) or state_cur(183) or state_cur(280) or ( state_cur(150) and (in3) = '1' ) or ( state_cur(175) and (in4) = '1' ) or ( state_cur(208) and (in5) = '1' ) or state_cur(224) or state_cur(200) or state_cur(273) or state_cur(105) or state_cur(333) or ( state_cur(175) and not ( (in4) = '1' ) );
out361_bufn <= state_cur(338) or state_cur(172);
out116_bufn <= ( state_cur(150) and not ( (in3) = '1' ) ) or state_cur(200) or state_cur(333);
out595_bufn <= state_cur(119) or state_cur(237) or state_cur(236) or state_cur(312);
out1004_bufn <= state_cur(143) or state_cur(132);
out227_bufn <= state_cur(123) or state_cur(224);
out109_bufn <= state_cur(186) or state_cur(334);
out619_bufn <= state_cur(237) or state_cur(312);
out410_bufn <= state_cur(335) or state_cur(143) or state_cur(132) or state_cur(322);
out989_bufn <= ( state_cur(150) and not ( (in3) = '1' ) ) or ( state_cur(240) and (in7) = '1' );
out431_bufn <= state_cur(184) or state_cur(187);
out938_bufn <= state_cur(94) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out525_bufn <= state_cur(96) or rtmcmp290;
out73_bufn <= rtmcmp92 or (state_cur(290) = '1' and rtmcmp290 = '0') or state_cur(291) or state_cur(91) or state_cur(203) or (state_cur(92) = '1' and rtmcmp92 = '0') or state_cur(336) or state_cur(337);
out837_bufn <= state_cur(522) or state_cur(108) or state_cur(342);
out860_bufn <= state_cur(119) or state_cur(236);
out228_bufn <= ( state_cur(220) and not ( (in6) = '1' ) ) or state_cur(341) or state_cur(224);
out421_bufn <= ( state_cur(328) and (in11) = '1' ) or ( state_cur(325) and not ( (in10) = '1' ) ) or ( state_cur(97) and not ( (NOT(in0)) = '1' ) ) or state_cur(306);
out409_bufn <= state_cur(132) or state_cur(322);
out473_bufn <= state_cur(99) or state_cur(218) or ( state_cur(325) and (in10) = '1' ) or ( state_cur(310) and not ( (in9) = '1' ) );
out509_bufn <= state_cur(123) or state_cur(223);
out94_bufn <= rtmcmp276 or state_cur(339);
out1048_bufn <= state_cur(341) or rtmcmp128;
out98_bufn <= state_cur(93) or state_cur(340) or state_cur(339);
out945_bufn <= ( state_cur(240) and (in7) = '1' ) or (state_cur(276) = '1' and rtmcmp276 = '0') or state_cur(114);
out156_bufn <= ( state_cur(328) and (in11) = '1' ) or state_cur(98);
out152_bufn <= state_cur(100) or state_cur(203);
-- Assignment of non-buffered outputs
out80 <=
state_cur(92);
out576 <=
state_cur(200);
out1103 <=
state_cur(336);
out438 <=
state_cur(151);
out171 <=
state_cur(222) or state_cur(102);
out378 <=
state_cur(340) or state_cur(222) or state_cur(138);
out940 <=
state_cur(276);
out131 <=
state_cur(99);
out376 <=
state_cur(138);
out891 <=
state_cur(237);
out611 <=
state_cur(209);
out638 <=
state_cur(222) or state_cur(209);
out354 <=
state_cur(129);
out7 <=
state_cur(3);
out1127 <=
state_cur(339);
out888 <=
state_cur(237);
out1141 <=
state_cur(348);
out6 <=
state_cur(2);
out1200 <=
state_cur(466);
out1148 <=
state_cur(362);
out250 <=
state_cur(114);
out1100 <=
state_cur(335);
out1168 <=
state_cur(402);
out1158 <=
state_cur(382);
out581 <=
state_cur(204);
out549 <=
state_cur(222) or state_cur(193);
out412 <=
state_cur(145);
out381 <=
state_cur(222) or state_cur(213) or state_cur(138);
out38 <=
state_cur(56);
out100 <=
state_cur(522) or state_cur(342) or state_cur(341) or state_cur(340) or state_cur(339) or state_cur(334) or state_cur(333) or state_cur(331) or
state_cur(301) or state_cur(281) or state_cur(280) or state_cur(224) or state_cur(213) or state_cur(200) or state_cur(187) or state_cur(184) or
state_cur(183) or state_cur(149) or state_cur(108) or state_cur(103) or state_cur(96) or state_cur(95) or state_cur(94) or state_cur(93);
out1181 <=
state_cur(428);
out22 <=
state_cur(20);
out56 <=
state_cur(85);
out224 <=
state_cur(326) or state_cur(303) or state_cur(292) or rtmcmp276 or state_cur(237) or state_cur(236) or state_cur(233) or state_cur(197) or
state_cur(147) or rtmcmp128 or state_cur(123) or state_cur(107);
out1115 <=
state_cur(336);
out191 <=
state_cur(102);
out290 <=
state_cur(123);
out1226 <=
state_cur(518);
out921 <=
state_cur(271);
out535 <=
state_cur(191);
out489 <=
state_cur(178);
out13 <=
state_cur(8);
out1161 <=
state_cur(388);
out408 <=
state_cur(144);
out1197 <=
state_cur(460);
out521 <=
state_cur(184);
out128 <=
state_cur(296) or state_cur(218) or state_cur(114) or state_cur(99);
out440 <=
state_cur(154);
out330 <=
state_cur(128);
out1003 <=
state_cur(294);
out1145 <=
state_cur(356);
out1156 <=
state_cur(378);
out497 <=
state_cur(268) or state_cur(222) or state_cur(178);
out52 <=
state_cur(79);
out659 <=
state_cur(218);
out566 <=
state_cur(197);
out850 <=
state_cur(231);
out1123 <=
state_cur(338);
out558 <=
state_cur(197);
out902 <=
state_cur(248);
out1217 <=
state_cur(500);
out357 <=
state_cur(132);
out229 <=
state_cur(108);
out1096 <=
state_cur(335);
out1188 <=
state_cur(442);
out39 <=
state_cur(57);
out118 <=
state_cur(96);
out387 <=
state_cur(142);
out514 <=
state_cur(183);
out425 <=
state_cur(148);
out508 <=
state_cur(182);
out1155 <=
state_cur(376);
out877 <=
state_cur(236);
out844 <=
state_cur(228);
out237 <=
state_cur(113);
out1133 <=
state_cur(341);
out1046 <=
state_cur(301);
out365 <=
state_cur(137);
out858 <=
state_cur(233);
out873 <=
state_cur(235);
out909 <=
state_cur(260);
out846 <=
state_cur(230);
out484 <=
state_cur(177);
out836 <=
state_cur(224);
out898 <=
state_cur(242);
out1196 <=
state_cur(458);
out26 <=
state_cur(30);
out1147 <=
state_cur(360);
out744 <=
state_cur(342) or state_cur(273) or state_cur(222);
out1026 <=
state_cur(296);
out430 <=
state_cur(149);
out962 <=
state_cur(281);
out45 <=
state_cur(66);
out9 <=
state_cur(5);
out1002 <=
state_cur(294);
out1139 <=
state_cur(344);
out1143 <=
state_cur(352);
out1173 <=
state_cur(412);
out28 <=
state_cur(32);
out1092 <=
state_cur(334);
out1140 <=
state_cur(346);
out40 <=
state_cur(58);
out119 <=
state_cur(98);
out382 <=
state_cur(139);
out241 <=
state_cur(114);
out91 <=
state_cur(93);
out920 <=
state_cur(270);
out986 <=
state_cur(290);
out657 <=
state_cur(222) or state_cur(218);
out375 <=
state_cur(331) or state_cur(222) or state_cur(138);
out866 <=
state_cur(235);
out577 <=
state_cur(203);
out1159 <=
state_cur(384);
out236 <=
state_cur(111);
out367 <=
state_cur(339) or state_cur(222) or state_cur(138);
out1130 <=
state_cur(340);
out25 <=
state_cur(25);
out258 <=
state_cur(222) or state_cur(114);
out990 <=
state_cur(291);
out900 <=
state_cur(244);
out748 <=
state_cur(273) or state_cur(224) or state_cur(222);
out1219 <=
state_cur(504);
out552 <=
state_cur(196);
out852 <=
state_cur(232);
out644 <=
state_cur(222) or state_cur(210);
out4 <=
state_cur(1);
out1142 <=
state_cur(350);
out1089 <=
state_cur(333);
out937 <=
state_cur(275);
out291 <=
state_cur(335) or state_cur(332) or state_cur(303) or state_cur(169) or rtmcmp128 or state_cur(123);
out482 <=
state_cur(222) or state_cur(175);
out924 <=
state_cur(273);
out1218 <=
state_cur(502);
out590 <=
state_cur(205);
out20 <=
state_cur(18);
out114 <=
state_cur(222) or state_cur(178) or state_cur(96);
out30 <=
state_cur(38);
out1224 <=
state_cur(514);
out107 <=
state_cur(95);
out915 <=
state_cur(268);
out34 <=
state_cur(45);
out1213 <=
state_cur(492);
out33 <=
state_cur(43);
out530 <=
state_cur(187);
out1191 <=
state_cur(448);
out223 <=
state_cur(107);
out834 <=
state_cur(231) or state_cur(223);
out1038 <=
state_cur(298);
out454 <=
state_cur(170);
out1087 <=
state_cur(332);
out233 <=
state_cur(109);
out66 <=
state_cur(91);
out347 <=
state_cur(222) or state_cur(149) or state_cur(129);
out848 <=
state_cur(231);
out746 <=
state_cur(301) or state_cur(273) or state_cur(222);
out695 <=
state_cur(232) or state_cur(222);
out1203 <=
state_cur(472);
out1085 <=
state_cur(332);
out1157 <=
state_cur(380);
out1039 <=
state_cur(298);
out532 <=
state_cur(189);
out1138 <=
state_cur(342);
out441 <=
state_cur(156);
out845 <=
state_cur(229);
out48 <=
state_cur(71);
out593 <=
state_cur(222) or state_cur(208);
out1182 <=
state_cur(430);
out57 <=
state_cur(88);
out44 <=
state_cur(63);
out1183 <=
state_cur(432);
out29 <=
state_cur(36);
out1015 <=
state_cur(296);
out910 <=
state_cur(261);
out524 <=
state_cur(186);
out958 <=
state_cur(280);
out460 <=
state_cur(300) or state_cur(204) or state_cur(191) or state_cur(170);
out50 <=
state_cur(74);
out304 <=
state_cur(126);
out130 <=
state_cur(222) or state_cur(99);
out833 <=
state_cur(223);
out513 <=
rtmcmp290 or state_cur(223) or state_cur(182);
out1210 <=
state_cur(486);
out370 <=
state_cur(222) or state_cur(146) or state_cur(138);
out481 <=
state_cur(175);
out207 <=
state_cur(103);
out445 <=
state_cur(164);
out362 <=
state_cur(134);
out908 <=
state_cur(257);
out1186 <=
state_cur(438);
out466 <=
state_cur(172);
out1083 <=
state_cur(331);
out475 <=
state_cur(173);
out19 <=
state_cur(16);
out645 <=
state_cur(212);
out582 <=
state_cur(222) or state_cur(204);
out547 <=
state_cur(193);
out1154 <=
state_cur(374);
out854 <=
state_cur(232);
out208 <=
state_cur(222) or state_cur(178) or state_cur(103);
out975 <=
state_cur(286);
out1150 <=
state_cur(366);
out503 <=
state_cur(179);
out650 <=
state_cur(213);
out863 <=
state_cur(234);
out1211 <=
state_cur(488);
out1228 <=
state_cur(522);
out5 <=
state_cur(518) or state_cur(516) or state_cur(514) or state_cur(512) or state_cur(510) or state_cur(508) or state_cur(506) or state_cur(504) or
state_cur(502) or state_cur(500) or state_cur(498) or state_cur(496) or state_cur(494) or state_cur(492) or state_cur(490) or state_cur(488) or
state_cur(486) or state_cur(484) or state_cur(482) or state_cur(480) or state_cur(478) or state_cur(476) or state_cur(474) or state_cur(472) or
state_cur(470) or state_cur(468) or state_cur(466) or state_cur(464) or state_cur(462) or state_cur(460) or state_cur(458) or state_cur(456) or
state_cur(454) or state_cur(452) or state_cur(450) or state_cur(448) or state_cur(446) or state_cur(444) or state_cur(442) or state_cur(440) or
state_cur(438) or state_cur(436) or state_cur(434) or state_cur(432) or state_cur(430) or state_cur(428) or state_cur(426) or state_cur(424) or
state_cur(422) or state_cur(420) or state_cur(418) or state_cur(416) or state_cur(414) or state_cur(412) or state_cur(410) or state_cur(408) or
state_cur(406) or state_cur(404) or state_cur(402) or state_cur(400) or state_cur(398) or state_cur(396) or state_cur(394) or state_cur(392) or
state_cur(390) or state_cur(388) or state_cur(386) or state_cur(384) or state_cur(382) or state_cur(380) or state_cur(378) or state_cur(376) or
state_cur(374) or state_cur(372) or state_cur(370) or state_cur(368) or state_cur(366) or state_cur(364) or state_cur(362) or state_cur(360) or
state_cur(358) or state_cur(356) or state_cur(354) or state_cur(352) or state_cur(350) or state_cur(348) or state_cur(346) or state_cur(344) or
state_cur(214) or state_cur(198) or state_cur(195) or state_cur(180) or state_cur(125) or state_cur(115) or state_cur(85) or state_cur(83) or
state_cur(79) or state_cur(73) or state_cur(71) or state_cur(1);
out1081 <=
state_cur(330);
out980 <=
rtmcmp290;
out533 <=
state_cur(190);
out338 <=
state_cur(280) or state_cur(222) or state_cur(129);
out32 <=
state_cur(40);
out1080 <=
state_cur(329);
out27 <=
state_cur(31);
out893 <=
state_cur(238);
out397 <=
state_cur(143);
out1000 <=
state_cur(293);
out55 <=
state_cur(83);
out235 <=
state_cur(109);
out1198 <=
state_cur(462);
out12 <=
state_cur(7);
out1221 <=
state_cur(508);
out277 <=
state_cur(119);
out1205 <=
state_cur(476);
out321 <=
state_cur(338) or state_cur(322) or state_cur(319) or state_cur(298) or state_cur(289) or rtmcmp276 or state_cur(237) or state_cur(197) or
state_cur(151) or state_cur(145) or state_cur(143) or rtmcmp128;
out1216 <=
state_cur(498);
out999 <=
state_cur(292);
out1190 <=
state_cur(446);
out1078 <=
state_cur(327);
out17 <=
state_cur(521) or state_cur(520) or state_cur(519) or state_cur(517) or state_cur(515) or state_cur(513) or state_cur(511) or state_cur(509) or
state_cur(507) or state_cur(505) or state_cur(503) or state_cur(501) or state_cur(499) or state_cur(497) or state_cur(495) or state_cur(493) or
state_cur(491) or state_cur(489) or state_cur(487) or state_cur(485) or state_cur(483) or state_cur(481) or state_cur(479) or state_cur(477) or
state_cur(475) or state_cur(473) or state_cur(471) or state_cur(469) or state_cur(467) or state_cur(465) or state_cur(463) or state_cur(461) or
state_cur(459) or state_cur(457) or state_cur(455) or state_cur(453) or state_cur(451) or state_cur(449) or state_cur(447) or state_cur(445) or
state_cur(443) or state_cur(441) or state_cur(439) or state_cur(437) or state_cur(435) or state_cur(433) or state_cur(431) or state_cur(429) or
state_cur(427) or state_cur(425) or state_cur(423) or state_cur(421) or state_cur(419) or state_cur(417) or state_cur(415) or state_cur(413) or
state_cur(411) or state_cur(409) or state_cur(407) or state_cur(405) or state_cur(403) or state_cur(401) or state_cur(399) or state_cur(397) or
state_cur(395) or state_cur(393) or state_cur(391) or state_cur(389) or state_cur(387) or state_cur(385) or state_cur(383) or state_cur(381) or
state_cur(379) or state_cur(377) or state_cur(375) or state_cur(373) or state_cur(371) or state_cur(369) or state_cur(367) or state_cur(365) or
state_cur(363) or state_cur(361) or state_cur(359) or state_cur(357) or state_cur(355) or state_cur(353) or state_cur(351) or state_cur(349) or
state_cur(347) or state_cur(345) or state_cur(343) or state_cur(255) or state_cur(110) or state_cur(106) or state_cur(86) or state_cur(78) or
state_cur(72) or state_cur(42) or state_cur(29) or state_cur(11);
out1209 <=
state_cur(484);
out70 <=
state_cur(337) or state_cur(336) or state_cur(282) or state_cur(228) or state_cur(203) or state_cur(189) or state_cur(179) or state_cur(102) or
state_cur(100) or state_cur(98) or rtmcmp92 or state_cur(91);
out1077 <=
state_cur(326);
out1215 <=
state_cur(496);
out285 <=
state_cur(338) or state_cur(319) or state_cur(312) or state_cur(274) or state_cur(236) or state_cur(233) or state_cur(209) or state_cur(193) or
state_cur(174) or state_cur(172) or state_cur(134) or state_cur(119);
out1206 <=
state_cur(478);
out1175 <=
state_cur(416);
out1222 <=
state_cur(510);
out443 <=
state_cur(160);
out212 <=
state_cur(105);
out270 <=
state_cur(296) or state_cur(114);
out865 <=
state_cur(234);
out648 <=
state_cur(222) or state_cur(212);
out1176 <=
state_cur(418);
out1174 <=
state_cur(414);
out54 <=
state_cur(82);
out706 <=
state_cur(296) or state_cur(222);
out913 <=
state_cur(266);
out24 <=
state_cur(23);
out1164 <=
state_cur(394);
out729 <=
state_cur(341) or state_cur(273) or state_cur(222);
out1204 <=
state_cur(474);
out573 <=
state_cur(199);
out480 <=
state_cur(222) or state_cur(174);
out14 <=
state_cur(9);
out1073 <=
state_cur(325);
out974 <=
state_cur(284);
out358 <=
state_cur(222) or state_cur(132);
out504 <=
state_cur(180);
out21 <=
state_cur(19);
out37 <=
state_cur(54);
out541 <=
state_cur(222) or state_cur(191);
out1071 <=
state_cur(322);
out23 <=
state_cur(22);
out1122 <=
state_cur(337);
out8 <=
state_cur(4);
out839 <=
state_cur(225);
out35 <=
state_cur(47);
out988 <=
state_cur(291);
out419 <=
state_cur(147);
out976 <=
state_cur(289);
out973 <=
state_cur(283);
out58 <=
state_cur(89);
out424 <=
state_cur(306) or state_cur(148);
out450 <=
state_cur(222) or state_cur(170);
out1068 <=
state_cur(321);
out1170 <=
state_cur(406);
out1067 <=
state_cur(319);
out1225 <=
state_cur(516);
out1187 <=
state_cur(440);
out563 <=
state_cur(222) or state_cur(197);
out1178 <=
state_cur(422);
out31 <=
state_cur(39);
out51 <=
state_cur(76);
out1171 <=
state_cur(408);
out41 <=
state_cur(59);
out360 <=
state_cur(133);
out1162 <=
state_cur(390);
out403 <=
state_cur(144);
out1179 <=
state_cur(424);
out1212 <=
state_cur(490);
out1189 <=
state_cur(444);
out1166 <=
state_cur(398);
out42 <=
state_cur(60);
out1220 <=
state_cur(506);
out137 <=
state_cur(99);
out643 <=
state_cur(210);
out692 <=
rtmcmp276 or state_cur(222);
out43 <=
state_cur(62);
out972 <=
state_cur(282);
out472 <=
state_cur(173);
out505 <=
state_cur(181);
out934 <=
state_cur(274);
out1165 <=
state_cur(396);
out494 <=
state_cur(334) or state_cur(222) or state_cur(178);
out1208 <=
state_cur(482);
out1172 <=
state_cur(410);
out550 <=
state_cur(195);
out439 <=
state_cur(152);
out388 <=
rtmcmp290 or state_cur(270) or state_cur(190) or state_cur(186) or state_cur(144) or state_cur(142);
out1195 <=
state_cur(456);
out479 <=
state_cur(174);
out1193 <=
state_cur(452);
out105 <=
state_cur(94);
out903 <=
state_cur(249);
out697 <=
state_cur(300) or state_cur(222);
out1149 <=
state_cur(364);
out49 <=
state_cur(73);
out448 <=
state_cur(169);
out436 <=
state_cur(150);
out917 <=
state_cur(270);
out1064 <=
state_cur(315);
out912 <=
state_cur(265);
out592 <=
state_cur(208);
out1167 <=
state_cur(400);
out719 <=
state_cur(237) or state_cur(222);
out301 <=
state_cur(125);
out1152 <=
state_cur(370);
out1063 <=
state_cur(312);
out1230 <=
state_cur(523);
out46 <=
state_cur(69);
out47 <=
state_cur(70);
out351 <=
state_cur(222) or state_cur(184) or state_cur(129);
out1169 <=
state_cur(404);
out491 <=
state_cur(222) or state_cur(200) or state_cur(178);
out1061 <=
state_cur(311);
out434 <=
state_cur(150);
out76 <=
state_cur(337) or state_cur(336) or state_cur(326) or state_cur(322) or state_cur(303) or state_cur(296) or state_cur(291) or rtmcmp290 or
rtmcmp276 or state_cur(212) or state_cur(204) or state_cur(203) or state_cur(191) or state_cur(190) or state_cur(186) or state_cur(143) or
state_cur(132) or rtmcmp128 or state_cur(123) or state_cur(114) or state_cur(107) or state_cur(100) or rtmcmp92 or state_cur(91);
out840 <=
state_cur(227);
out88 <=
state_cur(336) or state_cur(296) or state_cur(291) or rtmcmp290 or rtmcmp276 or rtmcmp128 or state_cur(114) or rtmcmp92;
out356 <=
state_cur(131);
out442 <=
state_cur(158);
out1199 <=
state_cur(464);
out1043 <=
state_cur(300);
out11 <=
state_cur(324) or state_cur(323) or state_cur(320) or state_cur(318) or state_cur(317) or state_cur(316) or state_cur(314) or state_cur(313) or
state_cur(305) or state_cur(304) or state_cur(302) or state_cur(297) or state_cur(295) or state_cur(288) or state_cur(287) or state_cur(285) or
state_cur(279) or state_cur(278) or state_cur(272) or state_cur(269) or state_cur(264) or state_cur(263) or state_cur(259) or state_cur(258) or
state_cur(256) or state_cur(250) or state_cur(246) or state_cur(243) or state_cur(239) or state_cur(226) or state_cur(217) or state_cur(216) or
state_cur(215) or state_cur(211) or state_cur(207) or state_cur(202) or state_cur(201) or state_cur(194) or state_cur(192) or state_cur(188) or
state_cur(176) or state_cur(171) or state_cur(167) or state_cur(165) or state_cur(163) or state_cur(161) or state_cur(159) or state_cur(157) or
state_cur(155) or state_cur(153) or state_cur(140) or state_cur(136) or state_cur(135) or state_cur(130) or state_cur(127) or state_cur(124) or
state_cur(122) or state_cur(121) or state_cur(120) or state_cur(118) or state_cur(117) or state_cur(116) or state_cur(112) or state_cur(104) or
state_cur(101) or state_cur(97) or state_cur(90) or state_cur(87) or state_cur(84) or state_cur(80) or state_cur(77) or state_cur(75) or
state_cur(68) or state_cur(67) or state_cur(65) or state_cur(64) or state_cur(61) or state_cur(55) or state_cur(52) or state_cur(51) or
state_cur(50) or state_cur(49) or state_cur(48) or state_cur(46) or state_cur(44) or state_cur(41) or state_cur(37) or state_cur(35) or
state_cur(34) or state_cur(33) or state_cur(28) or state_cur(27) or state_cur(26) or state_cur(24) or state_cur(21) or state_cur(17) or
state_cur(14) or state_cur(13) or state_cur(12) or state_cur(10) or state_cur(6);
out591 <=
state_cur(206);
out1180 <=
state_cur(426);
out476 <=
state_cur(291) or state_cur(173);
out1059 <=
state_cur(310);
out92 <=
state_cur(222) or state_cur(138) or state_cur(93);
out418 <=
state_cur(146);
out1042 <=
state_cur(299);
out1057 <=
state_cur(309);
out213 <=
state_cur(273) or state_cur(222) or state_cur(105);
out444 <=
state_cur(162);
out1153 <=
state_cur(372);
out1056 <=
state_cur(336) or state_cur(308);
out957 <=
state_cur(277);
out344 <=
state_cur(222) or state_cur(183) or state_cur(129);
out545 <=
state_cur(212) or state_cur(210) or state_cur(204) or state_cur(193);
out1055 <=
state_cur(308);
out968 <=
state_cur(282);
out335 <=
state_cur(222) or rtmcmp128;
out226 <=
state_cur(273) or state_cur(222) or state_cur(108);
out905 <=
state_cur(252);
out1177 <=
state_cur(420);
out904 <=
state_cur(251);
out1053 <=
state_cur(307);
out1052 <=
state_cur(306);
out417 <=
state_cur(145);
out1201 <=
state_cur(468);
out1163 <=
state_cur(392);
out2 <=
state_cur(330) or state_cur(329) or state_cur(327) or state_cur(321) or state_cur(315) or state_cur(311) or state_cur(309) or state_cur(307) or
state_cur(299) or state_cur(293) or state_cur(286) or state_cur(284) or state_cur(283) or state_cur(277) or state_cur(275) or state_cur(271) or
state_cur(267) or state_cur(266) or state_cur(265) or state_cur(262) or state_cur(261) or state_cur(260) or state_cur(257) or state_cur(254) or
state_cur(253) or state_cur(252) or state_cur(251) or state_cur(249) or state_cur(248) or state_cur(244) or state_cur(238) or state_cur(230) or
state_cur(229) or state_cur(227) or state_cur(225) or state_cur(221) or state_cur(206) or state_cur(205) or state_cur(199) or state_cur(185) or
state_cur(181) or state_cur(177) or state_cur(168) or state_cur(166) or state_cur(164) or state_cur(162) or state_cur(160) or state_cur(158) or
state_cur(156) or state_cur(154) or state_cur(139) or state_cur(137) or state_cur(133) or state_cur(131) or state_cur(126) or state_cur(113) or
state_cur(111) or state_cur(89) or state_cur(88) or state_cur(82) or state_cur(81) or state_cur(76) or state_cur(74) or state_cur(70) or
state_cur(69) or state_cur(66) or state_cur(63) or state_cur(62) or state_cur(60) or state_cur(59) or state_cur(58) or state_cur(57) or
state_cur(56) or state_cur(54) or state_cur(53) or state_cur(47) or state_cur(45) or state_cur(43) or state_cur(40) or state_cur(39) or
state_cur(38) or state_cur(36) or state_cur(32) or state_cur(31) or state_cur(30) or state_cur(25) or state_cur(23) or state_cur(22) or
state_cur(20) or state_cur(19) or state_cur(18) or state_cur(16) or state_cur(15) or state_cur(9) or state_cur(8) or state_cur(7) or
state_cur(5) or state_cur(4) or state_cur(3) or state_cur(2) or state_cur(0);
out447 <=
state_cur(168);
out1202 <=
state_cur(470);
out1192 <=
state_cur(450);
out1050 <=
state_cur(303);
out1144 <=
state_cur(354);
out0 <=
state_cur(0);
out446 <=
state_cur(166);
out914 <=
state_cur(267);
out1194 <=
state_cur(454);
out906 <=
state_cur(253);
out1146 <=
state_cur(358);
out572 <=
state_cur(198);
out1223 <=
state_cur(512);
out53 <=
state_cur(81);
out36 <=
state_cur(53);
out355 <=
state_cur(222) or state_cur(187) or state_cur(129);
out1184 <=
state_cur(434);
out907 <=
state_cur(254);
out1207 <=
state_cur(480);
out18 <=
state_cur(15);
out108 <=
state_cur(222) or state_cur(178) or state_cur(95);
out1160 <=
state_cur(386);
out662 <=
state_cur(218);
out303 <=
state_cur(247) or state_cur(242) or state_cur(241) or state_cur(197) or state_cur(152) or state_cur(148) or state_cur(125);
out1214 <=
state_cur(494);
out1185 <=
state_cur(436);
out341 <=
state_cur(523) or state_cur(222) or state_cur(129);
out1151 <=
state_cur(368);
out652 <=
state_cur(214);
out390 <=
state_cur(222) or state_cur(143);
out523 <=
state_cur(185);
out686 <=
state_cur(222);
out155 <=
state_cur(100);
out682 <=
state_cur(221);
out680 <=
state_cur(222) or state_cur(220);
out679 <=
state_cur(220);
out678 <=
state_cur(222) or state_cur(219);
out677 <=
state_cur(219);
-- Assignment of buffered outputs
out386 <= out386_buf;
out404 <= out404_buf;
out457 <= out457_buf;
out841 <= out841_buf;
out276 <= out276_buf;
out67 <= out67_buf;
out239 <= out239_buf;
out259 <= out259_buf;
out416 <= out416_buf;
out646 <= out646_buf;
out485 <= out485_buf;
out935 <= out935_buf;
out463 <= out463_buf;
out120 <= out120_buf;
out293 <= out293_buf;
out216 <= out216_buf;
out319 <= out319_buf;
out230 <= out230_buf;
out1 <= out1_buf;
out93 <= out93_buf;
out89 <= out89_buf;
out539 <= out539_buf;
out62 <= out62_buf;
out856 <= out856_buf;
out451 <= out451_buf;
out287 <= out287_buf;
out315 <= out315_buf;
out536 <= out536_buf;
out209 <= out209_buf;
out221 <= out221_buf;
out283 <= out283_buf;
out368 <= out368_buf;
out516 <= out516_buf;
out393 <= out393_buf;
out1008 <= out1008_buf;
out392 <= out392_buf;
out261 <= out261_buf;
out559 <= out559_buf;
out543 <= out543_buf;
out895 <= out895_buf;
out82 <= out82_buf;
out220 <= out220_buf;
out95 <= out95_buf;
out943 <= out943_buf;
out465 <= out465_buf;
out238 <= out238_buf;
out1025 <= out1025_buf;
out132 <= out132_buf;
out79 <= out79_buf;
out500 <= out500_buf;
out65 <= out65_buf;
out111 <= out111_buf;
out420 <= out420_buf;
out1076 <= out1076_buf;
out101 <= out101_buf;
out106 <= out106_buf;
out68 <= out68_buf;
out1069 <= out1069_buf;
out77 <= out77_buf;
out102 <= out102_buf;
out394 <= out394_buf;
out342 <= out342_buf;
out104 <= out104_buf;
out361 <= out361_buf;
out116 <= out116_buf;
out595 <= out595_buf;
out1004 <= out1004_buf;
out227 <= out227_buf;
out109 <= out109_buf;
out619 <= out619_buf;
out410 <= out410_buf;
out989 <= out989_buf;
out431 <= out431_buf;
out938 <= out938_buf;
out525 <= out525_buf;
out73 <= out73_buf;
out837 <= out837_buf;
out860 <= out860_buf;
out228 <= out228_buf;
out421 <= out421_buf;
out409 <= out409_buf;
out473 <= out473_buf;
out509 <= out509_buf;
out94 <= out94_buf;
out1048 <= out1048_buf;
out98 <= out98_buf;
out945 <= out945_buf;
out156 <= out156_buf;
out152 <= out152_buf;
-- Retiming: the comparators
rtmcmp92 <= '1' when state_cur(92) = '1' and rtmcounter0 = 1 else '0';
rtmcmp128 <= '1' when state_cur(128) = '1' and rtmcounter0 = 1 else '0';
rtmcmp276 <= '1' when state_cur(276) = '1' and rtmcounter0 = 1 else '0';
rtmcmp290 <= '1' when state_cur(290) = '1' and rtmcounter0 = 1 else '0';
end architecture;
|
gpl-2.0
|
9720793fef65f918b396d88d96630d83
| 0.587704 | 2.391959 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_01.vhd
| 4 | 1,801 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_ch_17_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_17_01 is
end entity ch_17_01;
----------------------------------------------------------------
architecture test of ch_17_01 is
begin
process is
-- code from book:
type natural_ptr is access natural;
variable count : natural_ptr;
-- end of code from book
begin
-- code from book:
count := new natural;
count.all := 10;
if count.all = 0 then
-- . . .
-- not in book
report "count.all = 0";
-- end not in book
end if;
-- end of code from book
if count.all /= 0 then
report "count.all /= 0";
end if;
-- code from book:
count := new natural'(10);
-- end of code from book
wait;
end process;
end architecture test;
|
gpl-2.0
|
7a9485e4995ec36569cd9c9e4329da4f
| 0.565242 | 4.217799 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.g-Div.vhd
| 1 | 6,697 |
--------------------------------------------------------------------------------
-- FILE: Div
-- DESC: Divider
--
-- Author:
-- Create: 2015-09-09
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Div is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
DIV_STAGE : integer := C_DIV_STAGE;
SQRT_STAGE : integer := C_SQRT_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
en: in std_logic:='0';
lock: in std_logic:='0';
sign: in std_logic:='0'; -- 0 UNSIGNED, 1 SIGNED
func: in std_logic:='0'; -- 0 DIV, 1 SQRT
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0') -- Data Out
);
end Div;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture div_arch of Div is
component AddSub is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
as: in std_logic; -- Add(Active High)/Sub(Active Low)
a, b: in std_logic_vector(DATA_SIZE-1 downto 0); -- Operands
re: out std_logic_vector(DATA_SIZE-1 downto 0); -- Return value
cout: out std_logic -- Carry
);
end component;
component Sipo is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
rst: in std_logic;
en : in std_logic;
clk: in std_logic;
din: in std_logic;
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Reg is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
rst: in std_logic;
en : in std_logic;
clk: in std_logic;
din: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Mux is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
sel: in std_logic;
din0: in std_logic_vector(DATA_SIZE-1 downto 0);
din1: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
signal a_adj, b_adj: std_logic_vector(DATA_SIZE-1 downto 0);
signal a_mod_dir, b_mod_dir, b_mod, a_mod: std_logic_vector(DATA_SIZE*2-1 downto 0);
signal a_mux, b_mux: std_logic_vector(DATA_SIZE*2-1 downto 0);
signal a_shf_div, a_shf_sqrt, a_shf : std_logic_vector(DATA_SIZE*2-1 downto 0);
signal b_shf_div, b_shf_sqrt, b_shf : std_logic_vector(DATA_SIZE*2-1 downto 0);
signal r_es : std_logic_vector(DATA_SIZE*2-1 downto 0);
signal r: std_logic_vector(DATA_SIZE*2-1 downto 0);
signal q : std_logic_vector(DATA_SIZE-1 downto 0);
signal not_r_es_sign, not_r_sign: std_logic;
signal en_input, sel_r, en_r, en_q : std_logic:='0';
signal c_state, n_state : integer:=0;
signal inv_a_flag, inv_b_flag, inv_q_flag, inv_q_flag_mod : std_logic:='0';
-- signal o_div, o_sqrt: std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal local_rst, reg_rst : std_logic:='1';
signal zeros32: std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
begin
-- Datapath
-- INPUT ADJUST
P0: process(clk, en_input)
begin
if rising_edge(clk) and en_input='1' then
a_mod <= a_mod_dir;
b_mod <= b_mod_dir;
inv_q_flag_mod <= inv_q_flag;
end if;
end process;
inv_a_flag <= sign and a(DATA_SIZE-1) and (not func);
inv_b_flag <= sign and b(DATA_SIZE-1) and (not func);
inv_q_flag <= sign and (a(DATA_SIZE-1) xor b(DATA_SIZE-1)) and (not func);
ADJUST0a: AddSub
generic map(DATA_SIZE)
port map(inv_a_flag, zeros32 , a, a_adj, open);
ADJUST0b: AddSub
generic map(DATA_SIZE)
port map(inv_b_flag, zeros32 , b, b_adj, open);
a_mod_dir(DATA_SIZE-1 downto 0) <= a_adj;
a_mod_dir(DATA_SIZE*2-1 downto DATA_SIZE) <= (others=>'0');
b_mod_dir(DATA_SIZE-1 downto 0) <= (others=>'0');
b_mod_dir(DATA_SIZE*2-1 downto DATA_SIZE) <= b_adj;
-- DIV & SQRT CALCULATION
MUXa: Mux
generic map(DATA_SIZE*2)
port map(sel_r, a_mod, r, a_mux);
b_mux <= b_mod;
not_r_sign <= not a_mux(DATA_SIZE*2-1);
a_shf_div(DATA_SIZE*2-1 downto 1) <= a_mux(DATA_SIZE*2-2 downto 0);
a_shf_div(0) <= '0';
a_shf_sqrt(DATA_SIZE*2-1 downto 2) <= a_mux(DATA_SIZE*2-3 downto 0);
a_shf_sqrt(1 downto 0) <= "00";
a_shf <= a_shf_sqrt when func='1' else a_shf_div;
b_shf_div <= b_mux;
b_shf_sqrt(DATA_SIZE*2-1 downto DATA_SIZE+2) <= q(DATA_SIZE-3 downto 0);
b_shf_sqrt(DATA_SIZE+1 downto DATA_SIZE) <= "01" when not_r_sign='1' else "11";
b_shf_sqrt(DATA_SIZE-1 downto 0) <= (others=>'0');
b_shf <= b_shf_sqrt when func='1' else b_shf_div;
ADD0: AddSub
generic map(DATA_SIZE*2)
port map(not_r_sign, a_shf, b_shf, r_es, open);
reg_rst <= rst and local_rst;
REG_R: Reg
generic map(DATA_SIZE*2)
port map(reg_rst, en_r, clk, r_es, r);
not_r_es_sign <= not r_es(DATA_SIZE*2-1);
REG_Q: Sipo
generic map(DATA_SIZE)
port map(reg_rst, en_q, clk, not_r_es_sign, q);
-- OUTPUT ADJUST
-- NEG q IF NEEDED (FOR DIV)
ADJUST: AddSub
generic map(DATA_SIZE)
port map(inv_q_flag_mod, zeros32, q, o, open);
-- MASK HIGH 16 bits to '0' (FOR SQRT)
-- o_sqrt <= q and x"0000ffff";
-- CHOOSE OUTPUT BASED ON func
-- o <= o_sqrt when func='1' else o_div;
-- Control Logic (FSM)
-- NEXT STATE GENERATOR
P_NSG1: process(en, c_state, lock)
begin
if en='1' and lock='1' then
n_state<=SG_ST0;
else
if en='1' and c_state = SG_ST0 and lock='0' then
n_state<=SG_ST1;
else
if c_state = SG_ST0 or (c_state>=DIV_STAGE-1 and func='0') or (c_state>=SQRT_STAGE-1 and func='1') then
n_state <= SG_ST0;
else
n_state <= c_state + 1;
end if;
end if;
end if;
end process;
-- OUTPUT GENERATOR
P_OUT1: process(c_state)
begin
if c_state=SG_ST1 then
en_input <= '0';
sel_r <= '0';
en_r <= '1';
en_q <= '1';
local_rst <= '1';
elsif c_state>SG_ST1 and ((c_state<DIV_STAGE and func='0') or (c_state<SQRT_STAGE and func='1'))then
en_input <= '0';
sel_r <= '1';
en_r <= '1';
en_q <= '1';
local_rst <= '1';
else
en_input <= '1';
sel_r <= '0';
en_r <= '0';
en_q <= '0';
local_rst <= '0';
end if;
end process;
-- NEXT STATE REGISTER
P_REG1: process(rst, clk)
begin
if rst='0' then
c_state <= SG_ST0;
else
if rising_edge(clk) then
c_state <= n_state;
end if;
end if;
end process;
end div_arch;
|
mit
|
9f4fc157adbe330452d25ed225a615a6
| 0.57354 | 2.60381 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/plasma.vhd
| 2 | 8,165 |
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mlite_pack;
use mlite_pack.mlite_pack.all;
entity plasma is
generic(memory_type : string := "DUAL_PORT_"; --"DUAL_PORT_" "ALTERA_LPM" "XILINX_16X";
log_file : string := "UNUSED";
ethernet : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
opcode_test_check : out std_logic_vector(31 downto 0);
pc_future_test_check : out std_logic_vector(31 downto 2);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal mem_address : std_logic_vector(31 downto 2);
signal mem_byte_we : std_logic_vector(3 downto 0);
signal data_r : std_logic_vector(31 downto 0);
signal data_w : std_logic_vector(31 downto 0);
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal mem_pause : std_logic;
signal eth_pause : std_logic;
signal enable_internal_ram : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
begin --architecture
write_enable <= '1' when mem_byte_we /= "0000" else '0';
mem_pause <= ((mem_pause_in or eth_pause) and not enable_misc) or
(uart_write_busy and enable_uart and write_enable);
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_internal_ram <= '1' when address_next(30 downto 28) = "000" else '0';
enable_misc <= '1' when mem_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and mem_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and mem_address(7 downto 4) = "0111" else '0';
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
address_next => address_next,
byte_we_next => byte_we_next,
opcode_test_out => opcode_test_check,
pc_future_test_out => pc_future_test_check,
address => mem_address,
byte_we => mem_byte_we,
data_w => data_w,
data_r => data_r,
mem_pause => mem_pause);
misc_proc: process(clk, reset, address_next, mem_address, enable_misc,
data_read_ram, data_read, data_read_uart, mem_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
gpioA_in, counter_reg, data_w)
begin
case mem_address(30 downto 28) is
when "000" => --internal RAM
data_r <= data_read_ram;
when "001" => --external RAM
data_r <= data_read;
when "010" => --misc
case mem_address(6 downto 4) is
when "000" => --uart
data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
data_r <= gpio0_reg;
when "101" => --gpioA
data_r <= gpioA_in;
when "110" => --counter
data_r <= counter_reg;
when others =>
data_r <= gpioA_in;
end case;
when "011" => --flash
data_r <= data_read;
when others =>
data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
if mem_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if mem_address(6 downto 4) = "001" then
irq_mask_reg <= data_w(7 downto 0);
elsif mem_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or data_w;
elsif mem_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not data_w;
end if;
end if;
end if;
counter_reg <= bv_inc(counter_reg);
end if;
end process;
u2_ram: ram
generic map (memory_type => memory_type)
port map (
clk => clk,
enable => enable_internal_ram,
write_byte_enable => byte_we_next,
address => address_next,
data_write => data_w,
data_read => data_read_ram);
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail);
dma_gen: if ethernet = '0' generate
address <= mem_address;
byte_we <= mem_byte_we;
data_write <= data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
end; --architecture logic
|
mit
|
8216d7d5e6ec93e97629d02191246f09
| 0.54305 | 3.467091 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3046.vhd
| 4 | 2,035 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3046.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b03x00p01n02i03046ent IS
type c_r is
record
i1 : integer;
r1 : real;
b1 : bit;
end record;
type c_a is array(1 to 3) of bit;
END c12s02b03x00p01n02i03046ent;
ARCHITECTURE c12s02b03x00p01n02i03046arch OF c12s02b03x00p01n02i03046ent IS
signal sr : c_r := (14,1.4,'1');
signal sa : c_a := "101";
BEGIN
b1: block
port(r:c_r; a:c_a);
port map (r=>sr, a=>sa);
begin
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( r=(14,1.4,'1') and a="101")
report "***PASSED TEST: c12s02b03x00p01n02i03046"
severity NOTE;
assert ( r=(14,1.4,'1') and a="101")
report "***FAILED TEST: c12s02b03x00p01n02i03046 - Ports should conform to their subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b03x00p01n02i03046arch;
|
gpl-2.0
|
65e11d113b98e971a42e6e0a1afa72e9
| 0.636855 | 3.431703 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd
| 4 | 1,915 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
package synchronize is
procedure init_synchronize ( signal synch : out std_logic );
procedure begin_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs );
procedure end_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs );
end package synchronize;
package body synchronize is
-- code from book
procedure init_synchronize ( signal synch : out std_logic ) is
begin
synch <= '0';
end procedure init_synchronize;
procedure begin_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs ) is
begin
synch <= 'Z' after Tdelay;
wait until synch = 'H';
end procedure begin_synchronize;
procedure end_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs ) is
begin
synch <= '0' after Tdelay;
wait until synch = '0';
end procedure end_synchronize;
-- end code from book
end package body synchronize;
|
gpl-2.0
|
ca5e8df0e1245cbb42ecd6f0cb058232
| 0.671018 | 4.402299 | false | false | false | false |
mmoraless/ecc_vhdl
|
ecc_add/Lut_3in_113.vhd
| 1 | 4,867 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------------------------
entity lut_3in is
generic(
NUM_BITS: positive := 113
);
port (
A: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
s0: in STD_LOGIC;
B: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
D: out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end;
---------------------------------------------------------------------------------------------
architecture behave of lut_3in is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
begin
D(0) <= (A(0) and s0) xor B(0);
D(1) <= (A(1) and s0) xor B(1);
D(2) <= (A(2) and s0) xor B(2);
D(3) <= (A(3) and s0) xor B(3);
D(4) <= (A(4) and s0) xor B(4);
D(5) <= (A(5) and s0) xor B(5);
D(6) <= (A(6) and s0) xor B(6);
D(7) <= (A(7) and s0) xor B(7);
D(8) <= (A(8) and s0) xor B(8);
D(9) <= (A(9) and s0) xor B(9);
D(10) <= (A(10) and s0) xor B(10);
D(11) <= (A(11) and s0) xor B(11);
D(12) <= (A(12) and s0) xor B(12);
D(13) <= (A(13) and s0) xor B(13);
D(14) <= (A(14) and s0) xor B(14);
D(15) <= (A(15) and s0) xor B(15);
D(16) <= (A(16) and s0) xor B(16);
D(17) <= (A(17) and s0) xor B(17);
D(18) <= (A(18) and s0) xor B(18);
D(19) <= (A(19) and s0) xor B(19);
D(20) <= (A(20) and s0) xor B(20);
D(21) <= (A(21) and s0) xor B(21);
D(22) <= (A(22) and s0) xor B(22);
D(23) <= (A(23) and s0) xor B(23);
D(24) <= (A(24) and s0) xor B(24);
D(25) <= (A(25) and s0) xor B(25);
D(26) <= (A(26) and s0) xor B(26);
D(27) <= (A(27) and s0) xor B(27);
D(28) <= (A(28) and s0) xor B(28);
D(29) <= (A(29) and s0) xor B(29);
D(30) <= (A(30) and s0) xor B(30);
D(31) <= (A(31) and s0) xor B(31);
D(32) <= (A(32) and s0) xor B(32);
D(33) <= (A(33) and s0) xor B(33);
D(34) <= (A(34) and s0) xor B(34);
D(35) <= (A(35) and s0) xor B(35);
D(36) <= (A(36) and s0) xor B(36);
D(37) <= (A(37) and s0) xor B(37);
D(38) <= (A(38) and s0) xor B(38);
D(39) <= (A(39) and s0) xor B(39);
D(40) <= (A(40) and s0) xor B(40);
D(41) <= (A(41) and s0) xor B(41);
D(42) <= (A(42) and s0) xor B(42);
D(43) <= (A(43) and s0) xor B(43);
D(44) <= (A(44) and s0) xor B(44);
D(45) <= (A(45) and s0) xor B(45);
D(46) <= (A(46) and s0) xor B(46);
D(47) <= (A(47) and s0) xor B(47);
D(48) <= (A(48) and s0) xor B(48);
D(49) <= (A(49) and s0) xor B(49);
D(50) <= (A(50) and s0) xor B(50);
D(51) <= (A(51) and s0) xor B(51);
D(52) <= (A(52) and s0) xor B(52);
D(53) <= (A(53) and s0) xor B(53);
D(54) <= (A(54) and s0) xor B(54);
D(55) <= (A(55) and s0) xor B(55);
D(56) <= (A(56) and s0) xor B(56);
D(57) <= (A(57) and s0) xor B(57);
D(58) <= (A(58) and s0) xor B(58);
D(59) <= (A(59) and s0) xor B(59);
D(60) <= (A(60) and s0) xor B(60);
D(61) <= (A(61) and s0) xor B(61);
D(62) <= (A(62) and s0) xor B(62);
D(63) <= (A(63) and s0) xor B(63);
D(64) <= (A(64) and s0) xor B(64);
D(65) <= (A(65) and s0) xor B(65);
D(66) <= (A(66) and s0) xor B(66);
D(67) <= (A(67) and s0) xor B(67);
D(68) <= (A(68) and s0) xor B(68);
D(69) <= (A(69) and s0) xor B(69);
D(70) <= (A(70) and s0) xor B(70);
D(71) <= (A(71) and s0) xor B(71);
D(72) <= (A(72) and s0) xor B(72);
D(73) <= (A(73) and s0) xor B(73);
D(74) <= (A(74) and s0) xor B(74);
D(75) <= (A(75) and s0) xor B(75);
D(76) <= (A(76) and s0) xor B(76);
D(77) <= (A(77) and s0) xor B(77);
D(78) <= (A(78) and s0) xor B(78);
D(79) <= (A(79) and s0) xor B(79);
D(80) <= (A(80) and s0) xor B(80);
D(81) <= (A(81) and s0) xor B(81);
D(82) <= (A(82) and s0) xor B(82);
D(83) <= (A(83) and s0) xor B(83);
D(84) <= (A(84) and s0) xor B(84);
D(85) <= (A(85) and s0) xor B(85);
D(86) <= (A(86) and s0) xor B(86);
D(87) <= (A(87) and s0) xor B(87);
D(88) <= (A(88) and s0) xor B(88);
D(89) <= (A(89) and s0) xor B(89);
D(90) <= (A(90) and s0) xor B(90);
D(91) <= (A(91) and s0) xor B(91);
D(92) <= (A(92) and s0) xor B(92);
D(93) <= (A(93) and s0) xor B(93);
D(94) <= (A(94) and s0) xor B(94);
D(95) <= (A(95) and s0) xor B(95);
D(96) <= (A(96) and s0) xor B(96);
D(97) <= (A(97) and s0) xor B(97);
D(98) <= (A(98) and s0) xor B(98);
D(99) <= (A(99) and s0) xor B(99);
D(100) <= (A(100) and s0) xor B(100);
D(101) <= (A(101) and s0) xor B(101);
D(102) <= (A(102) and s0) xor B(102);
D(103) <= (A(103) and s0) xor B(103);
D(104) <= (A(104) and s0) xor B(104);
D(105) <= (A(105) and s0) xor B(105);
D(106) <= (A(106) and s0) xor B(106);
D(107) <= (A(107) and s0) xor B(107);
D(108) <= (A(108) and s0) xor B(108);
D(109) <= (A(109) and s0) xor B(109);
D(110) <= (A(110) and s0) xor B(110);
D(111) <= (A(111) and s0) xor B(111);
D(112) <= (A(112) and s0) xor B(112);
end;
|
gpl-3.0
|
ec3eeb8d2d3ccb34056f878ae8d0d1f9
| 0.45264 | 1.909376 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.0-Mux4.vhd
| 1 | 1,258 |
--------------------------------------------------------------------------------
-- FILE: Mux4
-- DESC: 4 inputs 1 output multiplexer
--
-- Author:
-- Create: 2015-05-28
-- Update: 2015-05-30
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Mux4 is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
sel: in std_logic_vector(1 downto 0);
din0: in std_logic_vector(DATA_SIZE-1 downto 0);
din1: in std_logic_vector(DATA_SIZE-1 downto 0);
din2: in std_logic_vector(DATA_SIZE-1 downto 0);
din3: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end Mux4;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture mux4_arch of Mux4 is
begin
dout <= din0 when sel="00" else
din1 when sel="01" else
din2 when sel="10" else
din3 when sel="11";
end mux4_arch;
|
mit
|
5e55d951a5ca4c2e34aea56a9cd4cf1f
| 0.418919 | 4.165563 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_06.vhd
| 4 | 1,622 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_06 is
end entity tb_05_06;
architecture test of tb_05_06 is
signal s, r : bit := '0';
signal q, q_n : bit;
begin
dut : entity work.S_R_flipflop(functional)
port map ( s => s, r => r, q => q, q_n => q_n );
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
8b31e85e5da1b84887ebd579961089f3
| 0.588779 | 3.518438 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd
| 4 | 1,652 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_coeff_ram is
end entity tb_coeff_ram;
----------------------------------------------------------------
architecture test_abstract of tb_coeff_ram is
use work.coeff_ram_types.all;
signal rd, wr : bit := '0';
signal addr : coeff_ram_address := 0;
signal d_in, d_out : real := 0.0;
begin
dut : entity work.coeff_ram(abstract)
port map ( rd => rd, wr => wr,
addr => addr,
d_in => d_in, d_out => d_out );
stumulus : process is
begin
wait for 100 ns;
addr <= 10; d_in <= 10.0; wait for 10 ns;
wr <= '1'; wait for 10 ns;
d_in <= 20.0; wait for 10 ns;
wr <= '0'; wait for 70 ns;
addr <= 20; wait for 10 ns;
rd <= '1'; wait for 10 ns;
addr <= 10; wait for 10 ns;
rd <= '0'; wait for 10 ns;
wait;
end process stumulus;
end architecture test_abstract;
|
gpl-2.0
|
329eadbfeb8d8932090e891911f7984b
| 0.624697 | 3.583514 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/SingleFile/f2m_divider_571.vhd
| 1 | 8,920 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_571 is
generic(
NUM_BITS : positive := 571
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
Ux : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_571 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
--constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par, u_mas_v_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, INIT, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & y;
B <= F;
U <= '0' & x;
v <= (others => '0');
Ux <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
Ux <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
68c5d756e7ae4fb2d75c5f6bdc40ed7c
| 0.499103 | 4.772606 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-b.vhd
| 4 | 3,145 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxtst-b.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench of dlx_test is
use work.dlx_types.all;
component clock_gen is
port ( phi1, phi2 : out std_logic;
reset : out std_logic );
end component clock_gen;
component memory is
port ( phi1, phi2 : in std_logic;
a : in dlx_address;
d : inout dlx_word;
width : in dlx_mem_width;
write_enable : in std_logic;
burst : in std_logic := '0';
mem_enable : in std_logic;
ready : out std_logic );
end component memory;
component dlx is
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
a : out dlx_address;
d : inout dlx_word;
width : out dlx_mem_width;
write_enable : out std_logic;
ifetch : out std_logic;
mem_enable : out std_logic;
ready : in std_logic );
end component dlx;
signal phi1, phi2, reset : std_logic;
signal a : dlx_address;
signal d : dlx_word;
signal halt : std_logic;
signal width : dlx_mem_width;
signal write_enable, mem_enable, ifetch, ready : std_logic;
begin
cg : component clock_gen
port map ( phi1 => phi1, phi2 => phi2, reset => reset );
mem : component memory
port map ( phi1 => phi1, phi2 => phi2,
a => a, d => d,
width => width, write_enable => write_enable, burst => open,
mem_enable => mem_enable, ready => ready );
proc : component dlx
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt,
a => a, d => d,
width => width, write_enable => write_enable, ifetch => ifetch,
mem_enable => mem_enable, ready => ready );
end architecture bench;
|
gpl-2.0
|
9934010a7923ac46006f803dfb8b2726
| 0.520827 | 4.314129 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd
| 4 | 1,457 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity and2 is
port ( a, b : in std_ulogic; y : out std_ulogic );
end entity and2;
--------------------------------------------------
architecture detailed_delay of and2 is
signal result : std_ulogic;
begin
gate : process (a, b) is
begin
result <= a and b;
end process gate;
delay : process (result) is
begin
if result = '1' then
y <= reject 400 ps inertial '1' after 1.5 ns;
elsif result = '0' then
y <= reject 300 ps inertial '0' after 1.2 ns;
else
y <= reject 300 ps inertial 'X' after 500 ps;
end if;
end process delay;
end architecture detailed_delay;
|
gpl-2.0
|
d22a3935e1324e51f3cc570f2dfec0f1
| 0.672615 | 3.906166 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc426.vhd
| 4 | 3,263 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc426.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00426ent IS
END c03s02b01x01p19n01i00426ent;
ARCHITECTURE c03s02b01x01p19n01i00426arch OF c03s02b01x01p19n01i00426ent IS
type time_cons_vector is array (15 downto 0) of time;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
constant C1 : time_cons_vectorofvector := (others => (others => 3 ns));
function complex_scalar(s : time_cons_vectorofvector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return time_cons_vectorofvector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : time_cons_vectorofvector;
signal S2 : time_cons_vectorofvector;
signal S3 : time_cons_vectorofvector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00426"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00426 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00426arch;
|
gpl-2.0
|
0956a44e043509604038b0e013aea298
| 0.657677 | 3.699546 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1027.vhd
| 4 | 3,139 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1027.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p01n01i01027ent IS
END c06s04b00x00p01n01i01027ent;
ARCHITECTURE c06s04b00x00p01n01i01027arch OF c06s04b00x00p01n01i01027ent IS
BEGIN
TESTING: PROCESS
variable V1 : BIT_VECTOR(1 to 2);
variable V2 : BIT_VECTOR(3 to 4);
variable pass : integer := 0;
BEGIN
v1(1) := '1';
v1(2) := '0';
v2(3) := '0';
v2(4) := '1';
assert v1(1) = '1' report "v1(1) initial value is wrong.";
assert v1(2) = '0' report "v1(2) initial value is wrong.";
assert v2(3) = '0' report "v2(3) initial value is wrong.";
assert v2(4) = '1' report "v2(4) initial value is wrong.";
if ( V1(1) /= '1' or V1(2) /= '0' or
V2(3) /= '0' or V2(4) /= '1' ) then
pass := 1;
end if;
v1 := v2; -- composite variable assignment
assert v1(1) = '0' report "v1(1) final value is wrong.";
assert v1(2) = '1' report "v1(2) final value is wrong.";
assert v2(3) = '0' report "v2(3) final value is wrong.";
assert v2(4) = '1' report "v2(4) final value is wrong.";
if ( V1(1) /= '0' or V1(2) /= '1' or
V2(3) /= '0' or V2(4) /= '1' ) then
pass := 1;
end if;
v1 := ('1', '1'); -- composite variable assignment
-- aggregate value
assert v1(1) = '1' report "v1(1) final value is wrong.";
assert v1(2) = '1' report "v1(2) final value is wrong.";
assert v2(3) = '0' report "v2(3) final value is wrong.";
assert v2(4) = '1' report "v2(4) final value is wrong.";
if ( V1(1) /= '1' or V1(2) /= '1' or
V2(3) /= '0' or V2(4) /= '1' ) then
pass := 1;
end if;
wait for 5 ns;
assert NOT( pass = 0 )
report "***PASSED TEST: c06s04b00x00p01n01i01027"
severity NOTE;
assert ( pass = 0 )
report "***FAILED TEST: c06s04b00x00p01n01i01027 - Indexed reference test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p01n01i01027arch;
|
gpl-2.0
|
5d78f39f18f7199e2a005b5ac9eacd78
| 0.586174 | 3.107921 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc752.vhd
| 4 | 22,506 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc752.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00752ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00752ent;
ARCHITECTURE c01s01b01x01p05n02i00752arch OF c01s01b01x01p05n02i00752ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record:= (C85,C86,C88);
BEGIN
TESTING: PROCESS
variable V1 : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
variable V2 : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
variable V3 : integer_vector(zero to fifteen) := (zero to fifteen => C5);
variable V4 : real_vector(zero to fifteen) := (zero to fifteen => C6);
variable V5 : time_vector (zero to fifteen) := (zero to fifteen => C7);
variable V6 : natural_vector(zero to fifteen):= (zero to fifteen => C8);
variable V7 : positive_vector(zero to fifteen):= (zero to fifteen => C9);
variable V8 : boolean_cons_vector:= C19;
variable V9 : severity_level_cons_vector := C20;
variable V10 : integer_cons_vector:= C21;
variable V11 : real_cons_vector:= C22;
variable V12 : time_cons_vector := C23;
variable V13 : natural_cons_vector := C24;
variable V14 : positive_cons_vector := C25;
variable V15 : boolean_cons_vectorofvector := C26;
variable V16 : severity_level_cons_vectorofvector:= C27;
variable V17 : integer_cons_vectorofvector:= C28;
variable V18 : real_cons_vectorofvector:= C29;
variable V19 : time_cons_vectorofvector:= C30;
variable V20 : natural_cons_vectorofvector:= C31;
variable V21 : positive_cons_vectorofvector:= C32;
variable V22 : record_std_package:= C50;
variable V23 : record_cons_array := C51;
variable V24 : record_cons_arrayofarray := C53 ;
variable V25 : boolean_vector_st:= C70 ;
variable V26 : severity_level_vector_st := C71;
variable V27 : integer_vector_st:= C72;
variable V28 : real_vector_st := C73;
variable V29 : time_vector_st := C74;
variable V30 : natural_vector_st:= C75;
variable V31 : positive_vector_st := C76;
variable V32 : record_array_st := C54a;
variable V33 : record_array_st := C54a;
variable V34 : record_array_new:= C54b;
variable V35 : record_of_records := C55;
variable V36 : byte := C60;
variable V37 : word := C61;
variable V41 : boolean_vector_range := C78;
variable V42 : severity_level_vector_range := C79;
variable V43 : integer_vector_range := C80;
variable V44 : real_vector_range:= C81 ;
variable V45 : time_vector_range := C82;
variable V46 : natural_vector_range := C83;
variable V47 : positive_vector_range := C84;
variable V48 : array_rec_std(zero to seven) := C85;
variable V49 : array_rec_cons(zero to seven) := C86;
variable V50 : array_rec_rec(zero to seven) := C88;
variable V51 : record_of_arr_of_record := C102;
BEGIN
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34 = C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00752"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00752 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00752arch;
|
gpl-2.0
|
f859fa7788b161b6cd8655621ece88f1
| 0.557985 | 3.814576 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1476.vhd
| 4 | 1,818 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1476.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n01i01476ent IS
END c08s08b00x00p04n01i01476ent;
ARCHITECTURE c08s08b00x00p04n01i01476arch OF c08s08b00x00p04n01i01476ent IS
type t_int1 is range 0 to 100;
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable i : integer := 50;
BEGIN
case i is
when t_int1'low to 60 => k := 5;
when 61 to 88 => NULL;
when others => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p04n01i01476 - all of the choices must have the same type as the expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n01i01476arch;
|
gpl-2.0
|
70a29d4524cc3f96d3dd6511c7e1d05e
| 0.655666 | 3.710204 | false | true | false | false |
peteut/ghdl
|
libraries/ieee2008/float_pkg.vhdl
| 4 | 2,608 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Floating-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library ieee;
package float_pkg is new IEEE.float_generic_pkg
generic map (
float_exponent_width => 8, -- float32'high
float_fraction_width => 23, -- -float32'low
float_round_style => IEEE.fixed_float_types.round_nearest, -- round nearest algorithm
float_denormalize => true, -- Use IEEE extended floating
float_check_error => true, -- Turn on NAN and overflow processing
float_guard_bits => 3, -- number of guard bits
no_warning => false, -- show warnings
fixed_pkg => IEEE.fixed_pkg
);
|
gpl-2.0
|
3cb297412467e6f860817d0a8c44e355
| 0.595859 | 4.591549 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/numeric_std-body.vhdl
| 4 | 139,912 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number
-- : in vector form
-- : -- > UNRESOLVED_SIGNED: represents a SIGNED number
-- : in vector form
-- : The base element type is type STD_ULOGIC.
-- : Aliases U_UNSIGNED and U_SIGNED are defined for the types
-- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively.
-- : Two numeric subtypes are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The element subtypes are the same subtype as STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body NUMERIC_STD is
-- null range array constants
constant NAU : UNRESOLVED_UNSIGNED (0 downto 1) := (others => '0');
constant NAS : UNRESOLVED_SIGNED (0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING : BOOLEAN := false; -- default to emit warnings
-- =========================Local Subprograms =================================
function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function UNSIGNED_NUM_BITS;
------------------------------------------------------------------------
-- this internal function computes the addition of two UNRESOLVED_UNSIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R : UNRESOLVED_UNSIGNED; C : STD_LOGIC)
return UNRESOLVED_UNSIGNED
is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is R;
variable RESULT : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable CBIT : STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_UNSIGNED;
-- this internal function computes the addition of two UNRESOLVED_SIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_SIGNED (L, R : UNRESOLVED_SIGNED; C : STD_LOGIC)
return UNRESOLVED_SIGNED
is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(L_LEFT downto 0) is R;
variable RESULT : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable CBIT : STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_SIGNED;
-----------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM : UNRESOLVED_UNSIGNED;
XQUOT, XREMAIN : out UNRESOLVED_UNSIGNED) is
variable TEMP : UNRESOLVED_UNSIGNED(NUM'length downto 0);
variable QUOT : UNRESOLVED_UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1
downto 0);
alias DENOM : UNRESOLVED_UNSIGNED(XDENOM'length-1 downto 0) is XDENOM;
variable TOPBIT : INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'range loop
if DENOM(J) = '1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "NUMERIC_STD.DIVMOD: DIV, MOD, or REM by zero"
severity error;
for J in NUM'length-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1) = '0'
report "NUMERIC_STD.DIVMOD: internal error in the division algorithm"
severity error;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'length);
XREMAIN := RESIZE(TEMP, XREMAIN'length);
end procedure DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end function XSLL;
function XSRL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end function XSRL;
function XSRA (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0);
variable XCOUNT : NATURAL := COUNT;
begin
if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end function XSRA;
function XROL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end function XROL;
function XROR (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end function XROR;
-----------------Local Subprograms - Relational ops---------------------------
--
-- General "=" for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R);
end function UNSIGNED_EQUAL;
--
-- General "=" for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R);
end function SIGNED_EQUAL;
--
-- General "<" for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) < STD_ULOGIC_VECTOR(R);
end function UNSIGNED_LESS;
--
-- General "<" function for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_LESS (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1);
variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_ULOGIC_VECTOR(INTERN_L) < STD_ULOGIC_VECTOR(INTERN_R);
end function SIGNED_LESS;
--
-- General "<=" function for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_UNSIGNED)
return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) <= STD_ULOGIC_VECTOR(R);
end function UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1);
variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_ULOGIC_VECTOR(INTERN_L) <= STD_ULOGIC_VECTOR(INTERN_R);
end function SIGNED_LESS_OR_EQUAL;
-- =========================Exported Functions ==========================
-- Id: A.1
function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNRESOLVED_SIGNED(ARG_LEFT downto 0);
begin
if ARG'length < 1 then return NAS;
end if;
RESULT := TO_01(XARG, 'X');
if (RESULT(RESULT'left) = 'X') then return RESULT;
end if;
if RESULT(RESULT'left) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end function "abs";
-- Id: A.2
function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT, XARG01 : UNRESOLVED_SIGNED(ARG_LEFT downto 0);
variable CBIT : STD_LOGIC := '1';
begin
if ARG'length < 1 then return NAS;
end if;
XARG01 := TO_01(ARG, 'X');
if (XARG01(XARG01'left) = 'X') then return XARG01;
end if;
for I in 0 to RESULT'left loop
RESULT(I) := not(XARG01(I)) xor CBIT;
CBIT := CBIT and not(XARG01(I));
end loop;
return RESULT;
end function "-";
-- ============================================================================
-- Id: A.3
function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_UNSIGNED(L01, R01, '0');
end function "+";
-- Id: A.3R
function "+" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED
is
variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4
function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_SIGNED(L01, R01, '0');
end function "+";
-- Id: A.4R
function "+" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED
is
variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.5
function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'length);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) + R;
end function "+";
-- Id: A.7
function "+" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return L + TO_SIGNED(R, L'length);
end function "+";
-- Id: A.8
function "+" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) + R;
end function "+";
-- ============================================================================
-- Id: A.9
function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_UNSIGNED(L01, not(R01), '1');
end function "-";
-- Id: A.9R
function "-" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED
is
variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10
function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_SIGNED(L01, not(R01), '1');
end function "-";
-- Id: A.10R
function "-" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED
is
variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.11
function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'length);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) - R;
end function "-";
-- Id: A.13
function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is
begin
return L - TO_SIGNED(R, L'length);
end function "-";
-- Id: A.14
function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) - R;
end function "-";
-- ============================================================================
-- Id: A.15
function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable RESULT : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0) :=
(others => '0');
variable ADVAL : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end function "*";
-- Id: A.16
function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable RESULT : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0) :=
(others => '0');
variable ADVAL : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := TO_01(L, 'X');
XR := TO_01(R, 'X');
if ((XL(L_LEFT) = 'X') or (XR(R_LEFT) = 'X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT-1 loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT) = '1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end function "*";
-- Id: A.17
function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'length);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) * R;
end function "*";
-- Id: A.19
function "*" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return L * TO_SIGNED(R, L'length);
end function "*";
-- Id: A.20
function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) * R;
end function "*";
-- ============================================================================
-- Id: A.21
function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FQUOT := (others => 'X');
return FQUOT;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FQUOT;
end function "/";
-- Id: A.22
function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable QNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FQUOT := (others => 'X');
return UNRESOLVED_SIGNED(FQUOT);
end if;
if XL(XL'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-XL);
QNEG := true;
else
XNUM := UNRESOLVED_UNSIGNED(XL);
end if;
if XR(XR'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-XR);
QNEG := not QNEG;
else
XDENOM := UNRESOLVED_UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return UNRESOLVED_SIGNED(FQUOT);
end function "/";
-- Id: A.23
function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, QUOT : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(0) /= 'X'
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- Id: A.25
function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, QUOT : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.26
function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(0) /= 'X'
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => QUOT(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- ============================================================================
-- Id: A.27
function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end function "rem";
-- Id: A.28
function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XNUM := UNRESOLVED_UNSIGNED(TO_01(XXL, 'X'));
XDENOM := UNRESOLVED_UNSIGNED(TO_01(XXR, 'X'));
if ((XNUM(XNUM'left) = 'X') or (XDENOM(XDENOM'left) = 'X')) then
FREMAIN := (others => 'X');
return UNRESOLVED_SIGNED(FREMAIN);
end if;
if XNUM(XNUM'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XNUM));
RNEG := true;
else
XNUM := UNRESOLVED_UNSIGNED(XNUM);
end if;
if XDENOM(XDENOM'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XDENOM));
else
XDENOM := UNRESOLVED_UNSIGNED(XDENOM);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return UNRESOLVED_SIGNED(FREMAIN);
end function "rem";
-- Id: A.29
function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := L rem XR;
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := XL rem R;
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- Id: A.31
function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.32
function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- ============================================================================
-- Id: A.33
function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end function "mod";
-- Id: A.34
function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return UNRESOLVED_SIGNED(FREMAIN);
end if;
if XL(XL'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-XL);
else
XNUM := UNRESOLVED_UNSIGNED(XL);
end if;
if XR(XR'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-XR);
RNEG := true;
else
XDENOM := UNRESOLVED_UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'left) = '1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN /= "0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'left) = '1' and FREMAIN /= "0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return UNRESOLVED_SIGNED(FREMAIN);
end function "mod";
-- Id: A.35
function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- Id: A.37
function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.38
function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- ============================================================================
-- Id: A.39
function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.40
function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- Id: A.42
function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- ============================================================================
-- Id: C.1
function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">";
-- Id: C.2
function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function ">";
-- Id: C.4
function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01);
end function ">";
-- Id: C.5
function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function ">";
-- Id: C.6
function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length));
end function ">";
-- ============================================================================
-- Id: C.7
function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<";
-- Id: C.8
function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01);
end function "<";
-- Id: C.10
function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R01'length), R01);
end function "<";
-- Id: C.11
function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length));
end function "<";
-- Id: C.12
function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS(L01, TO_SIGNED(R, L01'length));
end function "<";
-- ============================================================================
-- Id: C.13
function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<=";
-- Id: C.14
function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function "<=";
-- Id: C.16
function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01);
end function "<=";
-- Id: C.17
function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function "<=";
-- Id: C.18
function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length));
end function "<=";
-- ============================================================================
-- Id: C.19
function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">=";
-- Id: C.20
function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01);
end function ">=";
-- Id: C.22
function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R01'length), R01);
end function ">=";
-- Id: C.23
function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length));
end function ">=";
-- Id: C.24
function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS(L01, TO_SIGNED(R, L01'length));
end function ">=";
-- ============================================================================
-- Id: C.25
function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "=";
-- Id: C.26
function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return false;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function "=";
-- Id: C.28
function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return false;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01);
end function "=";
-- Id: C.29
function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function "=";
-- Id: C.30
function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return false;
end if;
return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length));
end function "=";
-- ============================================================================
-- Id: C.31
function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end function "/=";
-- Id: C.32
function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01));
end function "/=";
-- Id: C.34
function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01));
end function "/=";
-- Id: C.35
function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length)));
end function "/=";
-- Id: C.36
function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length)));
end function "/=";
-- ============================================================================
-- Id: C.37
function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if UNSIGNED_LESS(L01, R01) then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.38
function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if SIGNED_LESS(L01, R01) then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- ============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if UNSIGNED_LESS(L01, R01) then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- Id: C.44
function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if SIGNED_LESS(L01, R01) then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
-- ============================================================================
-- Id: C.49
function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if Is_X(L) or Is_X(R) then
return 'X';
elsif L > R then
return '1';
else
return '0';
end if;
end if;
end function "?>";
-- Id: C.50
function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if Is_X(L) or Is_X(R) then
return 'X';
elsif L > R then
return '1';
else
return '0';
end if;
end if;
end function "?>";
-- Id: C.51
function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?> R;
end function "?>";
-- Id: C.52
function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?> R;
end function "?>";
-- Id: C.53
function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?> TO_UNSIGNED(R, L'length);
end function "?>";
-- Id: C.54
function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?> TO_SIGNED(R, L'length);
end function "?>";
-- ============================================================================
-- Id: C.55
function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if Is_X(L) or Is_X(R) then
return 'X';
elsif L < R then
return '1';
else
return '0';
end if;
end if;
end function "?<";
-- Id: C.56
function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if Is_X(L) or Is_X(R) then
return 'X';
elsif L < R then
return '1';
else
return '0';
end if;
end if;
end function "?<";
-- Id: C.57
function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?< R;
end function "?<";
-- Id: C.58
function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?< R;
end function "?<";
-- Id: C.59
function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?< TO_UNSIGNED(R, L'length);
end function "?<";
-- Id: C.60
function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?< TO_SIGNED(R, L'length);
end function "?<";
-- ============================================================================
-- Id: C.61
function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if Is_X(L) or Is_X(R) then
return 'X';
elsif L <= R then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
-- Id: C.62
function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if Is_X(L) or Is_X(R) then
return 'X';
elsif L <= R then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
-- Id: C.63
function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?<= R;
end function "?<=";
-- Id: C.64
function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?<= R;
end function "?<=";
-- Id: C.65
function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?<= TO_UNSIGNED(R, L'length);
end function "?<=";
-- Id: C.66
function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?<= TO_SIGNED(R, L'length);
end function "?<=";
-- ============================================================================
-- Id: C.67
function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if Is_X(L) or Is_X(R) then
return 'X';
elsif L >= R then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
-- Id: C.68
function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if Is_X(L) or Is_X(R) then
return 'X';
elsif L >= R then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
-- Id: C.69
function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?>= R;
end function "?>=";
-- Id: C.70
function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?>= R;
end function "?>=";
-- Id: C.71
function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?>= TO_UNSIGNED(R, L'length);
end function "?>=";
-- Id: C.72
function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?>= TO_SIGNED(R, L'length);
end function "?>=";
-- ============================================================================
-- Id: C.73
function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := LX(i) ?= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function "?=";
-- Id: C.74
function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := LX(i) ?= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function "?=";
-- Id: C.75
function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?= R;
end function "?=";
-- Id: C.76
function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?= R;
end function "?=";
-- Id: C.77
function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?= TO_UNSIGNED(R, L'length);
end function "?=";
-- Id: C.78
function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?= TO_SIGNED(R, L'length);
end function "?=";
-- ============================================================================
-- Id: C.79
function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := LX(i) ?/= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function "?/=";
-- Id: C.80
function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := LX(i) ?/= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function "?/=";
-- Id: C.81
function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?/= R;
end function "?/=";
-- Id: C.82
function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?/= R;
end function "?/=";
-- Id: C.83
function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?/= TO_UNSIGNED(R, L'length);
end function "?/=";
-- Id: C.84
function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?/= TO_SIGNED(R, L'length);
end function "?/=";
-- ============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XSRL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XSRA(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- ============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- ============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- ============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XXARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
variable XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0);
variable RESULT : NATURAL := 0;
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
XARG := TO_01(XXARG, 'X');
if (XARG(XARG'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
for I in XARG'range loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end function TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER is
variable XARG : UNRESOLVED_SIGNED(ARG'length-1 downto 0);
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
XARG := TO_01(ARG, 'X');
if (XARG(XARG'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if XARG(XARG'left) = '0' then
return TO_INTEGER(UNRESOLVED_UNSIGNED(XARG));
else
return (- (TO_INTEGER(UNRESOLVED_UNSIGNED(- (XARG + 1)))) -1);
end if;
end function TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable B_VAL : STD_LOGIC := '0';
variable I_VAL : INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then
assert NO_WARNING
report "NUMERIC_STD.TO_SIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_SIGNED;
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
-- ============================================================================
-- Id: R.1
function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL)
return UNRESOLVED_SIGNED
is
alias INVEC : UNRESOLVED_SIGNED(ARG'length-1 downto 0) is ARG;
variable RESULT : UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0) :=
(others => '0');
constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'length = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'left));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end function RESIZE;
-- Id: R.2
function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0) :=
(others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'length = 0 then return RESULT;
end if;
if (RESULT'length < ARG'length) then
RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0);
else
RESULT(RESULT'left downto XARG'left+1) := (others => '0');
RESULT(XARG'left downto 0) := XARG;
end if;
return RESULT;
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- ============================================================================
-- Id: L.1
function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(not(STD_ULOGIC_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.2
function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) and
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.3
function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) or
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.4
function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nand
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.5
function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.6
function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xnor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.8
function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(not(STD_ULOGIC_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.9
function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.10
function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.11
function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nand
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.12
function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.13
function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xnor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.15
function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L and STD_ULOGIC_VECTOR(R));
end function "and";
-- Id: L.16
function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) and R);
end function "and";
-- Id: L.17
function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L or STD_ULOGIC_VECTOR(R));
end function "or";
-- Id: L.18
function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) or R);
end function "or";
-- Id: L.19
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L nand STD_ULOGIC_VECTOR(R));
end function "nand";
-- Id: L.20
function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nand R);
end function "nand";
-- Id: L.21
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L nor STD_ULOGIC_VECTOR(R));
end function "nor";
-- Id: L.22
function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nor R);
end function "nor";
-- Id: L.23
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L xor STD_ULOGIC_VECTOR(R));
end function "xor";
-- Id: L.24
function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L xnor STD_ULOGIC_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xnor R);
end function "xnor";
-- Id: L.27
function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L and STD_ULOGIC_VECTOR(R));
end function "and";
-- Id: L.28
function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) and R);
end function "and";
-- Id: L.29
function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L or STD_ULOGIC_VECTOR(R));
end function "or";
-- Id: L.30
function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) or R);
end function "or";
-- Id: L.31
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L nand STD_ULOGIC_VECTOR(R));
end function "nand";
-- Id: L.32
function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nand R);
end function "nand";
-- Id: L.33
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L nor STD_ULOGIC_VECTOR(R));
end function "nor";
-- Id: L.34
function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nor R);
end function "nor";
-- Id: L.35
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L xor STD_ULOGIC_VECTOR(R));
end function "xor";
-- Id: L.36
function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L xnor STD_ULOGIC_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xnor R);
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return and (STD_ULOGIC_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return and (STD_ULOGIC_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return nand (STD_ULOGIC_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return nand (STD_ULOGIC_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return or (STD_ULOGIC_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return or (STD_ULOGIC_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return nor (STD_ULOGIC_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return nor (STD_ULOGIC_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return xor (STD_ULOGIC_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return xor (STD_ULOGIC_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return xnor (STD_ULOGIC_VECTOR (L));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return xnor (STD_ULOGIC_VECTOR (L));
end function "xnor";
-- ============================================================================
-- support constants for STD_MATCH:
type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN;
constant MATCH_TABLE : BOOLEAN_TABLE := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(false, false, false, false, false, false, false, false, true), -- | U |
(false, false, false, false, false, false, false, false, true), -- | X |
(false, false, true, false, false, false, true, false, true), -- | 0 |
(false, false, false, true, false, false, false, true, true), -- | 1 |
(false, false, false, false, false, false, false, false, true), -- | Z |
(false, false, false, false, false, false, false, false, true), -- | W |
(false, false, true, false, false, false, true, false, true), -- | L |
(false, false, false, true, false, false, false, true, true), -- | H |
(true, true, true, true, true, true, true, true, true) -- | - |
);
-- Id: M.1
function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN is
variable VALUE : STD_ULOGIC;
begin
return MATCH_TABLE(L, R);
end function STD_MATCH;
-- Id: M.2
function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
alias LV : UNRESOLVED_UNSIGNED(1 to L'length) is L;
alias RV : UNRESOLVED_UNSIGNED(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- Id: M.3
function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
alias LV : UNRESOLVED_SIGNED(1 to L'length) is L;
alias RV : UNRESOLVED_SIGNED(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- Id: M.5
function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
alias LV : STD_ULOGIC_VECTOR(1 to L'length) is L;
alias RV : STD_ULOGIC_VECTOR(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- ============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0')
return UNRESOLVED_UNSIGNED is
begin
if (S'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAU"
severity warning;
return NAU;
end if;
return UNRESOLVED_UNSIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP));
end function TO_01;
-- Id: T.2
function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0')
return UNRESOLVED_SIGNED is
begin
if (S'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAS"
severity warning;
return NAS;
end if;
return UNRESOLVED_SIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP));
end function TO_01;
-- Id: T.3
function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_X01(STD_ULOGIC_VECTOR(S)));
end function TO_X01;
-- Id: T.4
function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_X01(STD_ULOGIC_VECTOR(S)));
end function TO_X01;
-- Id: T.5
function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S)));
end function TO_X01Z;
-- Id: T.6
function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S)));
end function TO_X01Z;
-- Id: T.7
function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_UX01(STD_ULOGIC_VECTOR(S)));
end function TO_UX01;
-- Id: T.8
function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_UX01(STD_ULOGIC_VECTOR(S)));
end function TO_UX01;
-- Id: T.9
function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return IS_X(STD_ULOGIC_VECTOR(S));
end function IS_X;
-- Id: T.10
function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN is
begin
return IS_X(STD_ULOGIC_VECTOR(S));
end function IS_X;
-- ============================================================================
-- string conversion and write operations
-- ============================================================================
function to_ostring (value : UNRESOLVED_UNSIGNED) return STRING is
begin
return to_ostring(STD_ULOGIC_VECTOR (value));
end function to_ostring;
function to_ostring (value : UNRESOLVED_SIGNED) return STRING is
constant result_length : INTEGER := (value'length+2)/3;
constant pad : STD_ULOGIC_VECTOR(1 to (result_length*3 -
value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return to_ostring(pad & STD_ULOGIC_VECTOR (value));
end function to_ostring;
function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING is
begin
return to_hstring(STD_ULOGIC_VECTOR (value));
end function to_hstring;
function to_hstring (value : UNRESOLVED_SIGNED) return STRING is
constant result_length : INTEGER := (value'length+3)/4;
constant pad : STD_ULOGIC_VECTOR(1 to (result_length*4 -
value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return to_hstring(pad & STD_ULOGIC_VECTOR (value));
end function to_hstring;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.OREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.HREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
OWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : STD_ULOGIC_VECTOR(0 to (ne*3 - VALUE'length) - 1)
:= (others => VALUE (VALUE'left));
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
OWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
HWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
constant ne : INTEGER := (value'length+3)/4;
constant pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1)
:= (others => VALUE(VALUE'left));
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
HWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
end package body NUMERIC_STD;
|
gpl-2.0
|
1dbcd0c1f9217f8b26f8b8cb74c10083
| 0.569265 | 3.856025 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/control/ps2_rx_tb.vhd
| 1 | 4,386 |
-- ps2_rx_tb.vhd - TB modulu pro prijem signalu z portu PS2
-- Autori: Jakub Cabal
-- Posledni zmena: 04.10.2014 21:24
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY TB_PS2_RX IS
END TB_PS2_RX;
ARCHITECTURE behavior OF TB_PS2_RX IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PS2_RX
PORT(
CLK : IN std_logic;
RST : IN std_logic;
PS2C : IN std_logic;
PS2D : IN std_logic;
PS2RX_DATA : OUT std_logic_vector(7 downto 0);
PS2RX_VALID : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal ps2c : std_logic := '0';
signal ps2d : std_logic := '0';
--Outputs
signal PS2RX_DATA : std_logic_vector(7 downto 0);
signal PS2RX_VALID : std_logic;
-- Clock period definitions
constant CLK2_period : time := 10 ns;
constant clk_period : time := 90 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PS2_RX PORT MAP (
CLK => CLK,
RST => RST,
PS2C => ps2c,
PS2D => ps2d,
PS2RX_DATA => PS2RX_DATA,
PS2RX_VALID => PS2RX_VALID
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK2_period/2;
CLK <= '1';
wait for CLK2_period/2;
end process;
-- Stimulus process - generate scan codes
p_keyboard: process
variable data : std_logic_vector(7 downto 0);
variable parity : std_logic;
begin
ps2d <= '1';
ps2c <= '1';
RST <= '1';
wait for 100 ns;
RST <= '0';
wait for clk_period*10;
----------------------------------------------------------------------------------
-- key A - make code
data := X"1C";
parity := data(7) xor data(6) xor data(5) xor data(4) xor data(3) xor data(2) xor data(1) xor data(0) xor '1';
ps2d <= '0'; -- start bit
wait for clk_period*0.1;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
for i in 0 to 7 loop
ps2d <= data(0); -- LSB first
data := '0' & data(7 downto 1); -- shift right
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
end loop;
ps2d <= parity; -- parity bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
ps2d <= '1'; -- stop bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
wait for clk_period*50;
----------------------------------------------------------------------------------
-- break code
data := X"F0";
parity := data(7) xor data(6) xor data(5) xor data(4) xor data(3) xor data(2) xor data(1) xor data(0) xor '1';
ps2d <= '0'; -- start bit
wait for clk_period*0.1;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
for i in 0 to 7 loop
ps2d <= data(0); -- LSB first
data := '0' & data(7 downto 1); -- shift right
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
end loop;
ps2d <= parity; -- parity bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
ps2d <= '1'; -- stop bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
wait for clk_period*50;
----------------------------------------------------------------------------------
-- break code of key A
data := X"1C";
parity := data(7) xor data(6) xor data(5) xor data(4) xor data(3) xor data(2) xor data(1) xor data(0) xor '1';
ps2d <= '0'; -- start bit
wait for clk_period*0.1;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
for i in 0 to 7 loop
ps2d <= data(0); -- LSB first
data := '0' & data(7 downto 1); -- shift right
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
end loop;
ps2d <= parity; -- parity bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
ps2d <= '1'; -- stop bit
wait for clk_period/2;
ps2c <= '0';
wait for clk_period/2;
ps2c <= '1';
wait for clk_period*50;
----------------------------------------------------------------------------------
-- end of simulation
wait;
end process p_keyboard;
END;
|
mit
|
4cea7dad064f29e3176c6f617738b4d0
| 0.505928 | 2.855469 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc408.vhd
| 4 | 2,987 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc408.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00408ent IS
END c03s02b01x01p19n01i00408ent;
ARCHITECTURE c03s02b01x01p19n01i00408arch OF c03s02b01x01p19n01i00408ent IS
constant C1 : character := 's';
function complex_scalar(s : character) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return character is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : character;
signal S2 : character;
signal S3 : character := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00408"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00408 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00408arch;
|
gpl-2.0
|
257eeaf29b3afbfa42ac1b66383ab7ae
| 0.656177 | 3.701363 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc486.vhd
| 4 | 11,524 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc486.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00486ent IS
END c03s02b01x01p19n01i00486ent;
ARCHITECTURE c03s02b01x01p19n01i00486arch OF c03s02b01x01p19n01i00486ent IS
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
e: record_2cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
end record;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C52,C53,C77);
type array_rec_rec is array (integer range <>) of record_of_records;
function resolution13(i:in array_rec_rec) return record_of_records is
variable temp : record_of_records :=C55 ;
begin
return temp;
end resolution13;
subtype array_rec_rec_state is resolution13 record_of_records;
constant C66 : array_rec_rec_state := C55;
function complex_scalar(s : array_rec_rec_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_rec_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_rec_state;
signal S2 : array_rec_rec_state;
signal S3 : array_rec_rec_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00486"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00486 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00486arch;
|
gpl-2.0
|
c2685aaf97a80bb982553d7bd6f27d16
| 0.583218 | 3.78084 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd
| 4 | 1,761 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book (in text)
entity nand3 is
port ( a, b, c : in bit; y : out bit );
end entity nand3;
-- end code from book
architecture behavioral of nand3 is
begin
y <= not (a and b and c);
end architecture behavioral;
entity logic_block is
end entity logic_block;
-- code from book
library gate_lib;
architecture ideal of logic_block is
component nand2 is
port ( in1, in2 : in bit; result : out bit );
end component nand2;
for all : nand2
use entity gate_lib.nand3(behavioral)
port map ( a => in1, b => in2, c => '1', y => result );
-- . . . -- other declarations
-- not in book
signal s1, s2, s3 : bit := '0';
begin
gate1 : component nand2
port map ( in1 => s1, in2 => s2, result => s3 );
-- . . . -- other concurrent statements
-- not in book
s1 <= '1' after 20 ns;
s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
-- end not in book
end architecture ideal;
-- end code from book
|
gpl-2.0
|
3641b3af84f865efcddce31694e01a3b
| 0.670074 | 3.557576 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket89/project/src93/bfm_common_pkg.vhd
| 3 | 18,983 |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : bfm_common_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.methods_pkg.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.std_logic_1164_additions.all;
use ieee_proposed.standard_textio_additions.all;
package bfm_common_pkg is
-- General declarations related to BFMs
type t_normalization_mode is (ALLOW_WIDER, ALLOW_NARROWER, ALLOW_WIDER_NARROWER, ALLOW_EXACT_ONLY);
-- Functions/procedures
impure function normalise(
constant value : in std_logic_vector;
constant target : in std_logic_vector;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "slv"
) return std_logic_vector;
impure function normalise(
constant value : in unsigned;
constant target : in unsigned;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "unsigned"
) return unsigned;
impure function normalise(
constant value : in signed;
constant target : in signed;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "signed"
) return signed;
-- Functions/procedures
impure function normalize_and_check(
constant value : in std_logic_vector;
constant target : in std_logic_vector;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "slv"
) return std_logic_vector;
impure function normalize_and_check(
constant value : in unsigned;
constant target : in unsigned;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "unsigned"
) return unsigned;
impure function normalize_and_check(
constant value : in signed;
constant target : in signed;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "signed"
) return signed;
procedure wait_until_given_time_after_rising_edge (
signal clk : in std_logic;
constant wait_time : in time
);
end package bfm_common_pkg;
--=================================================================================================
package body bfm_common_pkg is
constant C_SCOPE : string := "bfm_common";
-- Normalize 'value' to the width given by 'target' and perform sanity check.
impure function normalize_and_check(
constant value : in std_logic_vector;
constant target : in std_logic_vector;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "slv"
) return std_logic_vector is
constant name : string := "normalize_and_check(" & val_type & ": " &
value_name & "=" & to_string(value, HEX, AS_IS) & ", " &
target_name & "=" & to_string(target, HEX, AS_IS) & ")";
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_target : std_logic_vector(target'length - 1 downto 0) is target;
variable v_normalized_value : std_logic_vector(target'length - 1 downto 0);
begin
-- Verify that value and target are not zero-length vectors
if value'length = 0 then
tb_error(name & " => Value length is zero! " & msg, C_SCOPE);
return v_normalized_value;
elsif target'length = 0 then
tb_error(name & " => Target length is zero! " & msg, C_SCOPE);
return v_normalized_value;
end if;
-- If value'length > target'length, remove leading zeros from value
if (a_value'length > a_target'length) then
v_normalized_value := a_value(a_target'length - 1 downto 0);
-- Sanity checks
if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE);
end if;
if not matching_widths(a_value, a_target) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE);
end if;
-- If value'length = target'length
elsif (a_value'length = a_target'length) then
v_normalized_value := a_value;
-- If value'length < target'length, add padding (leading zeros) to value
elsif (a_value'length < a_target'length) then
v_normalized_value := (others => '0');
v_normalized_value(a_value'length - 1 downto 0) := a_value;
-- Sanity check
if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE);
end if;
end if;
return v_normalized_value;
end;
impure function normalize_and_check(
constant value : in unsigned;
constant target : in unsigned;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "unsigned"
) return unsigned is
begin
return unsigned( normalize_and_check(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type) );
end;
impure function normalize_and_check(
constant value : in signed;
constant target : in signed;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "signed"
) return signed is
constant name : string := "normalize_and_check(" & val_type & ": " &
value_name & "=" & to_string(std_logic_vector(value)) & ", " &
target_name & "=" & to_string(std_logic_vector(target)) & ")";
alias a_value : signed(value'length - 1 downto 0) is value;
alias a_target : signed(target'length - 1 downto 0) is target;
variable v_normalized_value : signed(target'length - 1 downto 0);
begin
-- Verify that value and target are not zero-length vectors
if value'length = 0 then
tb_error(name & " => Value length is zero! " & msg, C_SCOPE);
return v_normalized_value;
elsif target'length = 0 then
tb_error(name & " => Target length is zero! " & msg, C_SCOPE);
return v_normalized_value;
end if;
-- If value'length > target'length, remove leading zeros/ones from value
if a_value'length > a_target'length then
v_normalized_value := a_value(a_target'length - 1 downto 0);
-- Sanity checks
if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE);
end if;
if a_value(a_value'high) = '0' then -- positive value
if not matching_widths(a_value, a_target) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE);
end if;
elsif a_value(a_value'high) = '1' then -- negative value
for i in a_value'high downto a_target'length loop
if a_value(i) = '0' then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & msg, C_SCOPE);
end if;
end loop;
end if;
-- If value'length = target'length
elsif a_value'length = a_target'length then
v_normalized_value := a_value;
-- If value'length < target'length, add padding (leading zeros/ones) to value
elsif a_value'length < a_target'length then
if a_value(a_value'high) = '0' then -- positive value
v_normalized_value := (others => '0');
elsif a_value(a_value'high) = '1' then -- negative value
v_normalized_value := (others => '1');
end if;
v_normalized_value(a_value'length - 1 downto 0) := a_value;
-- Sanity check
if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE);
end if;
end if;
return v_normalized_value;
end;
-- Normalise 'value' to the width given by 'target'.
impure function normalise(
constant value : in std_logic_vector;
constant target : in std_logic_vector;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "slv"
) return std_logic_vector is
constant name : string := "normalise(" & val_type & ": " &
value_name & "=" & to_string(value, HEX, AS_IS) & ", " &
target_name & "=" & to_string(target, HEX, AS_IS) & ")";
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_target : std_logic_vector(target'length - 1 downto 0) is target;
variable v_normalised_value : std_logic_vector(target'length - 1 downto 0);
begin
deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check().");
-- Verify that value and target are not zero-length vectors
if value'length = 0 then
tb_error(name & " => Value length is zero! " & msg, C_SCOPE);
return v_normalised_value;
elsif target'length = 0 then
tb_error(name & " => Target length is zero! " & msg, C_SCOPE);
return v_normalised_value;
end if;
-- If value'length > target'length, remove leading zeros from value
if (a_value'length > a_target'length) then
v_normalised_value := a_value(a_target'length - 1 downto 0);
-- Sanity checks
if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE);
end if;
if not matching_widths(a_value, a_target) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE);
end if;
-- If value'length = target'length
elsif (a_value'length = a_target'length) then
v_normalised_value := a_value;
-- If value'length < target'length, add padding (leading zeros) to value
elsif (a_value'length < a_target'length) then
v_normalised_value := (others => '0');
v_normalised_value(a_value'length - 1 downto 0) := a_value;
-- Sanity check
if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE);
end if;
end if;
return v_normalised_value;
end;
impure function normalise(
constant value : in unsigned;
constant target : in unsigned;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "unsigned"
) return unsigned is
begin
return unsigned( normalise(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type) );
end;
impure function normalise(
constant value : in signed;
constant target : in signed;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "signed"
) return signed is
constant name : string := "normalise(" & val_type & ": " &
value_name & "=" & to_string(std_logic_vector(value)) & ", " &
target_name & "=" & to_string(std_logic_vector(target)) & ")";
alias a_value : signed(value'length - 1 downto 0) is value;
alias a_target : signed(target'length - 1 downto 0) is target;
variable v_normalised_value : signed(target'length - 1 downto 0);
begin
deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check().");
-- Verify that value and target are not zero-length vectors
if value'length = 0 then
tb_error(name & " => Value length is zero! " & msg, C_SCOPE);
return v_normalised_value;
elsif target'length = 0 then
tb_error(name & " => Target length is zero! " & msg, C_SCOPE);
return v_normalised_value;
end if;
-- If value'length > target'length, remove leading zeros/ones from value
if a_value'length > a_target'length then
v_normalised_value := a_value(a_target'length - 1 downto 0);
-- Sanity checks
if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE);
end if;
if a_value(a_value'high) = '0' then -- positive value
if not matching_widths(a_value, a_target) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE);
end if;
elsif a_value(a_value'high) = '1' then -- negative value
for i in a_value'high downto a_target'length loop
if a_value(i) = '0' then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & msg, C_SCOPE);
end if;
end loop;
end if;
-- If value'length = target'length
elsif a_value'length = a_target'length then
v_normalised_value := a_value;
-- If value'length < target'length, add padding (leading zeros/ones) to value
elsif a_value'length < a_target'length then
if a_value(a_value'high) = '0' then -- positive value
v_normalised_value := (others => '0');
elsif a_value(a_value'high) = '1' then -- negative value
v_normalised_value := (others => '1');
end if;
v_normalised_value(a_value'length - 1 downto 0) := a_value;
-- Sanity check
if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE);
end if;
end if;
return v_normalised_value;
end;
-- Wait until wait_time after rising_edge(clk)
procedure wait_until_given_time_after_rising_edge (
signal clk : in std_logic;
constant wait_time : in time
) is
variable v_remaining_wait_time : time;
begin
-- If the time since the previous rising_edge is less than wait_time,
-- we don't have to wait until the next rising_edge,
-- only wait_time minus the time already passed since rising_edge
if (clk'last_event <= wait_time and -- less than wait_time has passed since last event
clk'last_value = '0' and clk = '1' -- last event was a rising_edge
) then
v_remaining_wait_time := wait_time - clk'last_event; -- Wait until wait_time after rising_edge
else
wait until rising_edge(clk);
v_remaining_wait_time := wait_time; -- Wait until wait_time after rising_edge
end if;
wait for v_remaining_wait_time;
end;
end package body bfm_common_pkg;
|
gpl-2.0
|
78522230caea66fde1cc0efdbed9fd39
| 0.58447 | 3.982169 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1947.vhd
| 4 | 16,579 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1947.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01947pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- -----------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01947pkg.all;
ENTITY c07s02b01x00p01n02i01947ent IS
END c07s02b01x00p01n02i01947ent;
ARCHITECTURE c07s02b01x00p01n02i01947arch OF c07s02b01x00p01n02i01947ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT NAND_C_csa1_1 : t_csa1_1 := ( '0', '1', '1', '1' );
CONSTANT NAND_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT NAND_C_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, TRUE );
CONSTANT NAND_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, TRUE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT NAND_C_csa1_3 : t_csa1_3 := ( '0', '1', '1', '1' );
CONSTANT NAND_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT NAND_C_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, TRUE );
CONSTANT NAND_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, TRUE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL NAND_S_csa1_1 : t_csa1_1 := ( '0', '1', '1', '1' );
SIGNAL NAND_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL NAND_S_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, TRUE );
SIGNAL NAND_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, TRUE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL NAND_S_csa1_3 : t_csa1_3 := ( '0', '1', '1', '1' );
SIGNAL NAND_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL NAND_S_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, TRUE );
SIGNAL NAND_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, TRUE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE NAND_V_csa1_1 : t_csa1_1 := ( '0', '1', '1', '1' );
VARIABLE NAND_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE NAND_V_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, TRUE );
VARIABLE NAND_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, TRUE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE NAND_V_csa1_3 : t_csa1_3 := ( '0', '1', '1', '1' );
VARIABLE NAND_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE NAND_V_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, TRUE );
VARIABLE NAND_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, TRUE );
BEGIN
--
-- Test NANDoperator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4
REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4
REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test NANDoperator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4
REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4
REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test NANDoperator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4
REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4
REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1 and
( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2 and
( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3 and
( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4 and
( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1 and
( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2 and
( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3 and
( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4 and
( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1 and
( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2 and
( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3 and
( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4 and
( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1 and
( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2 and
( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3 and
( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4 and
( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1 and
( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2 and
( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3 and
( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4 and
( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1 and
( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2 and
( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3 and
( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01947"
severity NOTE;
assert ( ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1 and
( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2 and
( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3 and
( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4 and
( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1 and
( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2 and
( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3 and
( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4 and
( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1 and
( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2 and
( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3 and
( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4 and
( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1 and
( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2 and
( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3 and
( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4 and
( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1 and
( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2 and
( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3 and
( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4 and
( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1 and
( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2 and
( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3 and
( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01947 - Logical operator NAND for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01947arch;
|
gpl-2.0
|
ff65fb221a51a315e4fb36a2d6156cf5
| 0.555643 | 2.689213 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_131_2.vhd
| 1 | 4,118 |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
-- FSM are not used.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_131 is
generic (
NUM_BITS : positive := 131 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_131;
-----------------------------------------------------------
architecture behave of serial_multiplier_131 is
-----------------------------------------------------------
-- m = 131 x131 + x8 + x3 + x2 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001101";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
done <= done_int;
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10000010"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done_int <= '0';
else
if done_int = '0' then
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
bx_int <= bx_shift;
if counter = "00000000" then -- The done signal is asserted at the same time that the result is computed.
Done_int <= '1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
12fa1b00f853f750f46246e9f6900cbf
| 0.491744 | 4.06917 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_01.vhd
| 4 | 2,289 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_ch_11_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_11_01 is
end entity ch_11_01;
----------------------------------------------------------------
architecture test of ch_11_01 is
type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type
-- code from book:
type small_int is range 1 to 4;
type small_array is array (small_int range <>) of -- . . . ;
-- not in book
MVL4_ulogic;
-- end not in book
-- end of code from book
type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
constant resolution_table : table :=
-- 'X' '0' '1' 'Z'
-- ------------------
( ( 'X', 'X', 'X', 'X' ), -- 'X'
( 'X', '0', 'X', '0' ), -- '0'
( 'X', 'X', '1', '1' ), -- '1'
( 'X', '0', '1', 'Z' ) ); -- 'Z'
function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is
variable result : MVL4_ulogic := 'Z';
begin
for index in contribution'range loop
result := resolution_table(result, contribution(index));
end loop;
return result;
end function resolve_MVL4;
subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
signal s : MVL4_logic;
begin
driver_1 : s <= 'Z';
driver_2 : s <= 'Z';
driver_3 : s <= 'Z';
driver_4 : s <= 'Z';
driver_5 : s <= 'Z';
end architecture test;
|
gpl-2.0
|
d6d3433855da60ce5ac7accee5f8fb81
| 0.559633 | 3.554348 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/memory/bram_sync_tdp.vhd
| 1 | 2,169 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: BRAM_SYNC_TDP
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
-- BRAM_SYNC_TDP is optimized for Altera Cyclone IV BRAM!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity BRAM_SYNC_TDP is
Generic (
DATA_WIDTH : integer := 32; -- Sirka datoveho vstupu a vystupu
ADDR_WIDTH : integer := 9 -- Sirka adresove sbernice, urcuje take pocet polozek v pameti (2^ADDR_WIDTH)
);
Port (
CLK : in std_logic;
-- Port A
WE_A : in std_logic;
ADDR_A : in std_logic_vector(ADDR_WIDTH-1 downto 0);
DATAIN_A : in std_logic_vector(DATA_WIDTH-1 downto 0);
DATAOUT_A : out std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port B
WE_B : in std_logic;
ADDR_B : in std_logic_vector(ADDR_WIDTH-1 downto 0);
DATAIN_B : in std_logic_vector(DATA_WIDTH-1 downto 0);
DATAOUT_B : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end BRAM_SYNC_TDP;
architecture FULL of BRAM_SYNC_TDP is
type ram_t is array((2**ADDR_WIDTH)-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
shared variable ram : ram_t := (others => (others => '0'));
begin
process (CLK)
begin
if (rising_edge(CLK)) then
if (WE_A = '1') then
ram(to_integer(unsigned(ADDR_A))) := DATAIN_A;
end if;
DATAOUT_A <= ram(to_integer(unsigned(ADDR_A)));
end if;
end process;
process (CLK)
begin
if (rising_edge(CLK)) then
if (WE_B = '1') then
ram(to_integer(unsigned(ADDR_B))) := DATAIN_B;
end if;
DATAOUT_B <= ram(to_integer(unsigned(ADDR_B)));
end if;
end process;
end FULL;
|
mit
|
f60d05bae8d2515a5eae823687ed99cd
| 0.518211 | 3.682513 | false | false | false | false |
tristanseifert/68komputer
|
sdr_data_path.vhd
| 1 | 2,595 |
--######################################################################
--
-- LOGIC CORE: SDR Data Path Module
-- MODULE NAME: sdr_data_path()
-- COMPANY: Altera Corporation
-- www.altera.com
--
-- REVISION HISTORY:
--
-- Revision 1.1 06/06/2000 Description: Initial Release.
--
-- FUNCTIONAL DESCRIPTION:
--
-- This module is the data path module for the SDR SDRAM controller.
--
--
-- Copyright (C) 1991-2000 Altera Corporation
--
--#######################################################################
library ieee;
use ieee.std_logic_1164.all;
entity sdr_data_path is
generic (DSIZE : integer := 32);
port (
CLK : in std_logic; -- System Clock
RESET_N : in std_logic; -- System Reset
OE : in std_logic; -- Data output(to the SDRAM) enable
DATAIN : in std_logic_vector(DSIZE-1 downto 0); -- Data input from the host
DM : in std_logic_vector(DSIZE/8-1 downto 0); -- byte data masks
DATAOUT : out std_logic_vector(DSIZE-1 downto 0); -- Read data output to host
DQIN : in std_logic_vector(DSIZE-1 downto 0); -- SDRAM data bus
DQOUT : out std_logic_vector(DSIZE-1 downto 0);
DQM : out std_logic_vector(DSIZE/8-1 downto 0) -- SDRAM data mask ouputs
);
end sdr_data_path;
architecture RTL of sdr_data_path is
-- signal declarations
signal DIN1 : std_logic_vector(DSIZE-1 downto 0);
signal DIN2 : std_logic_vector(DSIZE-1 downto 0);
signal DM1 : std_logic_vector(DSIZE/8-1 downto 0);
begin
-- This always block is a two stage pipe line delay that keeps the
-- data aligned with the command sequence in the other modules.
-- The pipeline is in both directions.
process(CLK, RESET_N)
begin
if (RESET_N = '0') then
DIN1 <= (others => '0');
DIN2 <= (others => '0');
DM1 <= (others => '0');
elsif rising_edge(CLK) then
DIN1 <= DATAIN;
DIN2 <= DIN1;
DM1 <= DM;
DQM <= DM1;
end if;
end process;
DATAOUT <= DQIN;
DQOUT <= DIN2;
end RTL;
|
bsd-2-clause
|
1596717f6aa2ea4657275e8802c85187
| 0.451638 | 4.145367 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc278.vhd
| 4 | 1,984 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc278.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p07n01i00278ent IS
END c03s01b03x00p07n01i00278ent;
ARCHITECTURE c03s01b03x00p07n01i00278arch OF c03s01b03x00p07n01i00278ent IS
type twos_complement_integer is range -32768 to 32767;
type J is
range twos_complement_integer'low to twos_complement_integer'high
units -- Success_here
A;
B = 10 A;
C = 10 B;
D = 10 C;
end units;
BEGIN
TESTING: PROCESS
variable k : J := 31000 A;
BEGIN
k := 5 A;
assert NOT(k=5 A)
report "***PASSED TEST: c03s01b03x00p07n01i00278"
severity NOTE;
assert (k=5 A)
report "***FAILED TEST: c03s01b03x00p07n01i00278 - The bounds in the range constraint are not locally static expressions."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p07n01i00278arch;
|
gpl-2.0
|
a358217351f1b58468e65e6d8f171d9c
| 0.659778 | 3.653775 | false | true | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/game/random.vhd
| 1 | 3,074 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: RANDOM_GENERATOR
-- AUTHORS: Vojtěch Jeřábek <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RANDOM_GENERATOR is
generic (
NUMBER_OF_OPTIONS : natural := 12; -- z kolika nahodnych moznosti chete vybirat.
FLIP_FLOPS : natural := 4 -- FLIP_FLOPS = (log(Number_of_options)/log(2)) zaokrouhlujte nahoru
);
Port (
CLK : in std_logic;
RST : in std_logic;
RANDOM_PULSE : in std_logic; -- pro provedeni nahodne generace sem privedte enable signal
RANDOM_OUT : out std_logic_vector(FLIP_FLOPS-1 downto 0); -- vygenerovana nahodna hodnota
ENABLE_OUT : out std_logic
);
end RANDOM_GENERATOR;
architecture Behavioral of RANDOM_GENERATOR is
signal counter : unsigned(FLIP_FLOPS-1 downto 0); -- citac pro vyber nahodneho cisla
signal divider2 : std_logic; -- zde je clk/2
begin
--------------------------------------------------------------------------------
-- vydeleni CLK dvema
divider2_p : process (CLK, RST)
begin
if (RST = '1') then
divider2 <= '0';
elsif (falling_edge(CLK)) then
divider2 <= NOT divider2;
end if;
end process;
--------------------------------------------------------------------------------
-- na counteru se pocita od nuly do (FLIP_FLOPS-1)
counter_p : process (CLK, RST)
begin
if (RST='1') then
counter <= (others=>'0');
elsif (rising_edge(CLK)) then
if (divider2 = '1') then
if (counter = (NUMBER_OF_OPTIONS-1)) then
counter <= (others=>'0');
else
counter <= counter + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- pokud je na RANDOM_PULSE log. 1, objevi se na RANDOM_OUT aktualni
-- hodnota counteru
random_out_reg : process (CLK, RST)
begin
if (RST='1') then
RANDOM_OUT <= (others=>'0');
elsif (rising_edge(CLK)) then
if (RANDOM_PULSE = '1') then
RANDOM_OUT <= std_logic_vector(counter);
end if;
end if;
end process;
enable_out_reg : process (CLK, RST)
begin
if (RST='1') then
ENABLE_OUT <='0';
elsif (rising_edge(CLK)) then
if (RANDOM_PULSE = '1') then
ENABLE_OUT <='1';
else
ENABLE_OUT <='0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
4474cb8f2be441d6bf4e45b9f24d2c26
| 0.464669 | 4.265278 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/packages/bit_vector_signed_arithmetic.vhd
| 4 | 2,350 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
function "-" ( bv : bit_vector ) return bit_vector;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector;
-- . . .
end package bit_vector_signed_arithmetic;
--------------------------------------------------
-- not in book
library ieee; use ieee.numeric_bit.all;
-- end not in book
package body bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bit_vector( "+"(signed(bv1), signed(bv2)) );
end function "+";
-- end not in book
function "-" ( bv : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bit_vector( "-"(signed(bv)) );
end function "-";
-- end not in book
function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is
-- . . .
begin
-- not in book
-- . . .
return bit_vector( "*"(unsigned(bv1), unsigned(bv2)) );
-- end not in book
end function mult_unsigned;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector is
begin
if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then
return mult_unsigned(bv1, bv2);
elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then
return -mult_unsigned(bv1, -bv2);
elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then
return -mult_unsigned(-bv1, bv2);
else
return mult_unsigned(-bv1, -bv2);
end if;
end function "*";
-- . . .
end package body bit_vector_signed_arithmetic;
|
gpl-2.0
|
3fec005efe764e03a2a3cb1f0c9ce250
| 0.639574 | 3.523238 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd
| 4 | 1,900 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity sensor_interface is
end entity sensor_interface;
-- end not in book
architecture structural of sensor_interface is
component adc is
generic ( width : positive );
port ( terminal analog_in : electrical;
signal clock : in std_logic;
signal start : in std_logic;
signal eoc : out std_logic;
signal data_out : out std_logic_vector(0 to width - 1) );
end component adc;
-- ...
-- not in book
terminal sensor_input : electrical;
signal clk, start_conversion, end_conversion : std_logic;
signal sensor_data : std_logic_vector(0 to 7);
-- end not in book
begin
sensor_adc : component adc
generic map ( width => sensor_data'length )
port map ( analog_in => sensor_input,
clock => clk,
start => start_conversion,
eoc => end_conversion,
data_out => sensor_data );
-- ...
end architecture structural;
|
gpl-2.0
|
f52764372a0e190c8c501d86fea09b85
| 0.665789 | 4.175824 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk.vhd
| 4 | 2,137 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity bfsk is
generic ( fc : real := 1.0e6; -- mean carrier frequency
delta_f : real := 5.0e3; -- difference between low and high
-- carrier frequencies
amp : voltage := 1.0; -- amplitude of modulated signal
offset : voltage := 0.0 ); -- output offset voltage
port ( signal d_in : in std_logic; -- digital input
terminal a_out : electrical ); -- output terminal
end entity bfsk;
----------------------------------------------------------------
architecture behavioral of bfsk is
quantity vout across iout through a_out; -- output branch
quantity phi : real; -- free quantity angle in radians
constant wc : real := math_2_pi * fc; -- convert fc to rad/s
constant delta_w : real := math_2_pi * delta_f; -- convert delta_f to rad/s
begin
if To_X01(d_in) = '0' use
phi'dot == wc; -- set to carrier frequency
elsif To_X01(d_in) = '1' use
phi'dot == wc + delta_w; -- set to carrier frequency + delta
else
phi'dot == 0.0;
end use;
break on d_in;
vout == offset + amp * sin(phi); -- create sinusoidal output using phi
end architecture behavioral;
|
gpl-2.0
|
56b42602294b4629d9a08aa19b1884a3
| 0.638278 | 3.935543 | false | false | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/device.vhd
| 1 | 1,405 |
library ieee;
use ieee.std_logic_1164.all;
entity device is
port (a,b: in std_logic_vector(31 downto 0);
clk,en,rst: in std_logic;
c: out std_logic_vector(31 downto 0);
done: out std_logic
);
end device;
architecture arch_device_1 of device is
component datapath is
port (a,b: in std_logic_vector(31 downto 0);
clk,rst: in std_logic;
en: in std_logic_vector(1 downto 0);
c: out std_logic_vector(31 downto 0);
done,m47: out std_logic
);
end component;
component exceptions
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
int_mul: in std_logic_vector(31 downto 0);
enable: in std_logic;
m_in47:in std_logic;
exp_out: out std_logic_vector(31 downto 0)
);
end component;
component control
port (clk,rst,en: in std_logic;
done_m: in std_logic;
done:out std_logic;
en_mul: out std_logic_vector(1 downto 0)
);
end component;
signal done_s : std_logic ;
signal res: std_logic_vector(31 downto 0);
signal m47: std_logic;
signal en_m:std_logic_vector(1 downto 0);
signal d: std_logic;
begin
done<=d;
dp: datapath port map(a=>a,b=>b,clk=>clk,rst=>rst,en=>en_m,c=>res,done=>done_s,m47=>m47);
ex:exceptions port map(in1=>a,in2=>b,int_mul=>res,enable=>d,m_in47=>m47,exp_out=>c);
ctrl: control port map(clk=>clk,rst=>rst,en=>en,done_m=>done_s,done=>d,en_mul=>en_m);
end arch_device_1;
|
mit
|
26f0d1f96b456db9d3f1cdd25eb066f9
| 0.664769 | 2.616387 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/Modular/celda_U.vhd
| 1 | 2,256 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_U is
generic(
NUM_BITS : positive := 163
);
port(
U : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
V : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
P : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c0 : in STD_LOGIC;
c1 : in STD_LOGIC;
c2 : in STD_LOGIC;
c3 : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
toU : out STD_LOGIC_VECTOR(NUM_BITS downto 0);
RegU : out STD_LOGIC_VECTOR(NUM_BITS downto 0)
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_U is
----------------------------------------------------------------------------------------------------
signal U1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal V1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal P1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal R1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal xr1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal xr2 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal divx : STD_LOGIC_VECTOR(NUM_BITS downto 0);
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
U1 <= U when c0 = '1' else
(others => '0');
V1 <= V when c1 = '1' else
(others => '0');
P1 <= P when c2 = '1' else
(others => '0');
xr1 <= (U1 xor V1);
xr2 <= xr1 xor P1;
R1 <= xr1 when c2 = '0' else
xr1 when xr1(0) = '0' and c2 = '1' else
xr2;
divx <= '0'&R1(NUM_BITS downto 1);
toU <= divx;
celda_U_process: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
RegU <= (others => '0');
else
if c3 = '1' then
RegU <= divx;
end if;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
77ead27e274f10f72e1d3e7243b12291
| 0.427305 | 3.615385 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1371.vhd
| 4 | 6,575 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1371.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01371ent IS
END c08s05b00x00p03n01i01371ent;
ARCHITECTURE c08s05b00x00p03n01i01371arch OF c08s05b00x00p03n01i01371ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_rec3 : st_rec3 :=c_st_rec3_1 ;
--
BEGIN
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01371"
severity NOTE;
assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01371 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01371arch;
|
gpl-2.0
|
d4d337479f9baf1daa672a193761daf5
| 0.583878 | 2.922222 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket40/generic_when.vhdl
| 3 | 901 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity GENERIC_WHEN is
generic( FOO : std_logic_vector(1 downto 0) );
port( IN1 : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(1 downto 0) );
end GENERIC_WHEN;
architecture BEHAVIOUR of GENERIC_WHEN is
begin
PR1:
process( IN1 )
variable l : line;
begin
case IN1 is
when FOO => OUT1 <= FOO; write(l, string'("FOO")); writeline(output, l);
--when "00" => write(l, string'("00")); writeline(output, l);
when "01" => write(l, string'("01")); writeline(output, l);
when others => write(l, string'("other")); writeline(output, l);
end case;
end process PR1;
end BEHAVIOUR;
|
gpl-2.0
|
470ccaa7f05e5fcee55dcef002c40975
| 0.517203 | 3.850427 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd
| 4 | 2,059 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_18.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity XYZ3000_cpu is
port ( clock : in bit; addr_data : inout bit_vector(31 downto 0);
other_port : in bit := '0' );
end entity XYZ3000_cpu;
architecture full_function of XYZ3000_cpu is
begin
end architecture full_function;
entity memory_array is
port ( addr : in bit_vector(25 downto 0); other_port : in bit := '0' );
end entity memory_array;
architecture behavioral of memory_array is
begin
end architecture behavioral;
-- code from book
library chips;
configuration intermediate of single_board_computer is
for structural
for cpu : processor
use entity chips.XYZ3000_cpu(full_function)
port map ( clock => clk, addr_data => a_d, -- . . . );
-- not in book
other_port => open );
-- end not in book
end for;
for main_memory : memory
use entity work.memory_array(behavioral);
end for;
for all : serial_interface
use open;
end for;
-- . . .
end for;
end configuration intermediate;
-- end code from book
|
gpl-2.0
|
44595ceaff54863246015c576f082ca4
| 0.630403 | 4.021484 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_02.vhd
| 4 | 2,513 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_12_fg_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
entity D_flipflop is
generic ( Tpd_clk_q, Tsu_d_clk, Th_d_clk : delay_length );
port ( clk, d : in bit; q : out bit );
end entity D_flipflop;
--------------------------------------------------
architecture basic of D_flipflop is
begin
behavior : q <= d after Tpd_clk_q when clk = '1' and clk'event;
check_setup : process is
begin
wait until clk = '1';
assert d'last_event >= Tsu_d_clk
report "setup violation";
end process check_setup;
check_hold : process is
begin
wait until clk'delayed(Th_d_clk) = '1';
assert d'delayed'last_event >= Th_d_clk
report "hold violation";
end process check_hold;
end architecture basic;
-- end code from book
entity fg_12_02 is
end entity fg_12_02;
architecture test of fg_12_02 is
signal system_clock, request, request_pending : bit := '0';
begin
-- code from book (in text)
request_flipflop : entity work.D_flipflop(basic)
generic map ( Tpd_clk_q => 4 ns,
Tsu_d_clk => 3 ns, Th_d_clk => 1 ns )
port map ( clk => system_clock,
d => request, q => request_pending );
-- end code from book
clock_gen : system_clock <= '1' after 10 ns,
'0' after 20 ns when system_clock = '0';
stimulus : request <= '1' after 25 ns, '0' after 35 ns,
'1' after 67 ns, '0' after 71 ns,
'1' after 108 ns, '0' after 110.5 ns;
end architecture test;
|
gpl-2.0
|
60006b8d360b5ed9be5579791d0616cc
| 0.588938 | 3.745156 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1781.vhd
| 4 | 4,938 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1781.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
Package c09s06b00x00p04n05i01781pkg is
type info is record
field_1 : integer;
field_2 : real;
end record;
type stuff is array (Integer range 1 to 2) of info;
end c09s06b00x00p04n05i01781pkg;
use work.c09s06b00x00p04n05i01781pkg.all;
entity c09s06b00x00p04n05i01781ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end c09s06b00x00p04n05i01781ent_a;
use work.c09s06b00x00p04n05i01781pkg.all;
architecture c09s06b00x00p04n05i01781arch_a of c09s06b00x00p04n05i01781ent_a is
-- Check that the data was passed...
begin
TESTING: PROCESS
BEGIN
assert NOT( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***PASSED TEST: c09s06b00x00p04n05i01781"
severity NOTE;
assert ( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***FAILED TEST: c09s06b00x00p04n05i01781 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
end c09s06b00x00p04n05i01781arch_a;
-------------------------------------------------------------------------
ENTITY c09s06b00x00p04n05i01781ent IS
END c09s06b00x00p04n05i01781ent;
use work.c09s06b00x00p04n05i01781pkg.all;
ARCHITECTURE c09s06b00x00p04n05i01781arch OF c09s06b00x00p04n05i01781ent IS
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01781ent_a(c09s06b00x00p04n05i01781arch_a);
BEGIN
u1 : MultiType
generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100",
gB(2) => ( 890, 135.7 ),
gB(1) => ( 123, 456.7 )
);
END c09s06b00x00p04n05i01781arch;
|
gpl-2.0
|
40dd280556e040166af66ae365285343
| 0.508505 | 3.755133 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2012.vhd
| 4 | 11,577 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2012.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02012ent IS
END c07s02b02x00p10n01i02012ent;
ARCHITECTURE c07s02b02x00p10n01i02012arch OF c07s02b02x00p10n01i02012ent IS
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_scl1 IS CHARACTER ;
SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH;
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
CONSTANT C2_scl1 : st_scl1 := 'Z' ;
CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
CONSTANT C2_scl3 : st_scl3 := 8 ;
CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
OTHERS =>C0_scl1);
CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
OTHERS =>C0_scl3);
BEGIN
TESTING: PROCESS
--
-- Constant declarations - for unconstrained types
-- other composite type declarations are in package "COMPOSITE"
--
CONSTANT C0_usa1_1 : t_usa1_1 (st_ind1 ) := C0_csa1_1;
CONSTANT C0_usa1_3 : t_usa1_3 (st_ind3 ) := C0_csa1_3;
CONSTANT C2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
CONSTANT C2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
--
-- Composite VARIABLE declarations
--
VARIABLE V0_usa1_1 : t_usa1_1 (st_ind1 ) ;
VARIABLE V0_usa1_3 : t_usa1_3 (st_ind3 ) ;
VARIABLE V0_csa1_1 : t_csa1_1 ;
VARIABLE V0_csa1_3 : t_csa1_3 ;
VARIABLE V2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
VARIABLE V2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
VARIABLE V2_csa1_1 : t_csa1_1 := C2_csa1_1;
VARIABLE V2_csa1_3 : t_csa1_3 := C2_csa1_3;
--
-- Arrays of the same type, element values, different length
--
VARIABLE V3_usa1_1 : t_usa1_1 ( 1 TO 7 ) ;
VARIABLE V3_usa1_3 : t_usa1_3 ('a' TO 'c' ) ;
--
CONSTANT msg1 : STRING := "ERROR: less than operator failure: ";
CONSTANT msg2 : STRING := "ERROR: less than or equal operator failure: ";
BEGIN
--
-- Check less than operator - CONSTANTS (from package 'composite')
--
ASSERT C0_usa1_1 < C2_usa1_1 REPORT msg1 & "C0<C2_usa1_1" SEVERITY FAILURE;
ASSERT C0_usa1_3 < C2_usa1_3 REPORT msg1 & "C0<C2_usa1_3" SEVERITY FAILURE;
ASSERT C0_csa1_1 < C2_csa1_1 REPORT msg1 & "C0<C2_csa1_1" SEVERITY FAILURE;
ASSERT C0_csa1_3 < C2_csa1_3 REPORT msg1 & "C0<C2_csa1_3" SEVERITY FAILURE;
--
-- Check less than operator - VARIABLES
--
ASSERT V0_usa1_1 < V2_usa1_1 REPORT msg1 & "V0<V2_usa1_1" SEVERITY FAILURE;
ASSERT V0_usa1_3 < V2_usa1_3 REPORT msg1 & "V0<V2_usa1_3" SEVERITY FAILURE;
ASSERT V0_csa1_1 < V2_csa1_1 REPORT msg1 & "V0<V2_csa1_1" SEVERITY FAILURE;
ASSERT V0_csa1_3 < V2_csa1_3 REPORT msg1 & "V0<V2_csa1_3" SEVERITY FAILURE;
--
-- Check less than operator - VARIABLES and CONSTANTS
--
ASSERT V0_usa1_1 < C2_usa1_1 REPORT msg1 & "V0<C2_usa1_1" SEVERITY FAILURE;
ASSERT V0_usa1_3 < C2_usa1_3 REPORT msg1 & "V0<C2_usa1_3" SEVERITY FAILURE;
ASSERT V0_csa1_1 < C2_csa1_1 REPORT msg1 & "V0<C2_csa1_1" SEVERITY FAILURE;
ASSERT V0_csa1_3 < C2_csa1_3 REPORT msg1 & "V0<C2_csa1_3" SEVERITY FAILURE;
--
-- Check less than operator - same type, element values : diff array length
--
ASSERT V3_usa1_1 < V2_usa1_1 REPORT msg1 & "V3<V2_usa1_1" SEVERITY FAILURE;
ASSERT V3_usa1_3 < V2_usa1_3 REPORT msg1 & "V3<V2_usa1_3" SEVERITY FAILURE;
--
-- Check less than or equal operator - CONSTANTS (from package 'composite')
--
ASSERT C0_usa1_1 <= C2_usa1_1 REPORT msg2 & "C0<=C2_usa1_1" SEVERITY FAILURE;
ASSERT C0_usa1_3 <= C2_usa1_3 REPORT msg2 & "C0<=C2_usa1_3" SEVERITY FAILURE;
ASSERT C0_csa1_1 <= C2_csa1_1 REPORT msg2 & "C0<=C2_csa1_1" SEVERITY FAILURE;
ASSERT C0_csa1_3 <= C2_csa1_3 REPORT msg2 & "C0<=C2_csa1_3" SEVERITY FAILURE;
--
-- Check less than or equal operator - VARIABLES
--
ASSERT V0_usa1_1 <= V2_usa1_1 REPORT msg2 & "V0<=V2_usa1_1" SEVERITY FAILURE;
ASSERT V0_usa1_3 <= V2_usa1_3 REPORT msg2 & "V0<=V2_usa1_3" SEVERITY FAILURE;
ASSERT V0_csa1_1 <= V2_csa1_1 REPORT msg2 & "V0<=V2_csa1_1" SEVERITY FAILURE;
ASSERT V0_csa1_3 <= V2_csa1_3 REPORT msg2 & "V0<=V2_csa1_3" SEVERITY FAILURE;
--
-- Check less than or equal operator - VARIABLES and CONSTANTS
--
ASSERT V0_usa1_1 <= C2_usa1_1 REPORT msg2 & "V0<=C2_usa1_1" SEVERITY FAILURE;
ASSERT V0_usa1_3 <= C2_usa1_3 REPORT msg2 & "V0<=C2_usa1_3" SEVERITY FAILURE;
ASSERT V0_csa1_1 <= C2_csa1_1 REPORT msg2 & "V0<=C2_csa1_1" SEVERITY FAILURE;
ASSERT V0_csa1_3 <= C2_csa1_3 REPORT msg2 & "V0<=C2_csa1_3" SEVERITY FAILURE;
--
-- Check less than or equal operator - same type, element values : diff array length
--
ASSERT V3_usa1_1 <= V2_usa1_1 REPORT msg2 & "V3<=V2_usa1_1" SEVERITY FAILURE;
ASSERT V3_usa1_3 <= V2_usa1_3 REPORT msg2 & "V3<=V2_usa1_3" SEVERITY FAILURE;
--
-- Check less than or equal operator - CONSTANTS (from package 'composite')
--
ASSERT C2_usa1_1 <= C2_usa1_1 REPORT msg2 & "C2<=C2_usa1_1" SEVERITY FAILURE;
ASSERT C2_usa1_3 <= C2_usa1_3 REPORT msg2 & "C2<=C2_usa1_3" SEVERITY FAILURE;
ASSERT C2_csa1_1 <= C2_csa1_1 REPORT msg2 & "C2<=C2_csa1_1" SEVERITY FAILURE;
ASSERT C2_csa1_3 <= C2_csa1_3 REPORT msg2 & "C2<=C2_csa1_3" SEVERITY FAILURE;
--
-- Check less than or equal operator - VARIABLES
--
ASSERT V2_usa1_1 <= V2_usa1_1 REPORT msg2 & "V2<=V2_usa1_1" SEVERITY FAILURE;
ASSERT V2_usa1_3 <= V2_usa1_3 REPORT msg2 & "V2<=V2_usa1_3" SEVERITY FAILURE;
ASSERT V2_csa1_1 <= V2_csa1_1 REPORT msg2 & "V2<=V2_csa1_1" SEVERITY FAILURE;
ASSERT V2_csa1_3 <= V2_csa1_3 REPORT msg2 & "V2<=V2_csa1_3" SEVERITY FAILURE;
--
-- Check less than or equal operator - VARIABLES and CONSTANTS
--
ASSERT V2_usa1_1 <= C2_usa1_1 REPORT msg2 & "V2<=C2_usa1_1" SEVERITY FAILURE;
ASSERT V2_usa1_3 <= C2_usa1_3 REPORT msg2 & "V2<=C2_usa1_3" SEVERITY FAILURE;
ASSERT V2_csa1_1 <= C2_csa1_1 REPORT msg2 & "V2<=C2_csa1_1" SEVERITY FAILURE;
ASSERT V2_csa1_3 <= C2_csa1_3 REPORT msg2 & "V2<=C2_csa1_3" SEVERITY FAILURE;
assert NOT( C0_usa1_1 < C2_usa1_1 and
C0_usa1_3 < C2_usa1_3 and
C0_csa1_1 < C2_csa1_1 and
C0_csa1_3 < C2_csa1_3 and
V0_usa1_1 < V2_usa1_1 and
V0_usa1_3 < V2_usa1_3 and
V0_csa1_1 < V2_csa1_1 and
V0_csa1_3 < V2_csa1_3 and
V0_usa1_1 < C2_usa1_1 and
V0_usa1_3 < C2_usa1_3 and
V0_csa1_1 < C2_csa1_1 and
V0_csa1_3 < C2_csa1_3 and
V3_usa1_1 < V2_usa1_1 and
V3_usa1_3 < V2_usa1_3 and
C0_usa1_1 <= C2_usa1_1 and
C0_usa1_3 <= C2_usa1_3 and
C0_csa1_1 <= C2_csa1_1 and
C0_csa1_3 <= C2_csa1_3 and
V0_usa1_1 <= V2_usa1_1 and
V0_usa1_3 <= V2_usa1_3 and
V0_csa1_1 <= V2_csa1_1 and
V0_csa1_3 <= V2_csa1_3 and
V0_usa1_1 <= C2_usa1_1 and
V0_usa1_3 <= C2_usa1_3 and
V0_csa1_1 <= C2_csa1_1 and
V0_csa1_3 <= C2_csa1_3 and
V3_usa1_1 <= V2_usa1_1 and
V3_usa1_3 <= V2_usa1_3 and
C2_usa1_1 <= C2_usa1_1 and
C2_usa1_3 <= C2_usa1_3 and
C2_csa1_1 <= C2_csa1_1 and
C2_csa1_3 <= C2_csa1_3 and
V2_usa1_1 <= V2_usa1_1 and
V2_usa1_3 <= V2_usa1_3 and
V2_csa1_1 <= V2_csa1_1 and
V2_csa1_3 <= V2_csa1_3 and
V2_usa1_1 <= C2_usa1_1 and
V2_usa1_3 <= C2_usa1_3 and
V2_csa1_1 <= C2_csa1_1 and
V2_csa1_3 <= C2_csa1_3 )
report "***PASSED TEST: c07s02b02x00p10n01i02012"
severity NOTE;
assert ( C0_usa1_1 < C2_usa1_1 and
C0_usa1_3 < C2_usa1_3 and
C0_csa1_1 < C2_csa1_1 and
C0_csa1_3 < C2_csa1_3 and
V0_usa1_1 < V2_usa1_1 and
V0_usa1_3 < V2_usa1_3 and
V0_csa1_1 < V2_csa1_1 and
V0_csa1_3 < V2_csa1_3 and
V0_usa1_1 < C2_usa1_1 and
V0_usa1_3 < C2_usa1_3 and
V0_csa1_1 < C2_csa1_1 and
V0_csa1_3 < C2_csa1_3 and
V3_usa1_1 < V2_usa1_1 and
V3_usa1_3 < V2_usa1_3 and
C0_usa1_1 <= C2_usa1_1 and
C0_usa1_3 <= C2_usa1_3 and
C0_csa1_1 <= C2_csa1_1 and
C0_csa1_3 <= C2_csa1_3 and
V0_usa1_1 <= V2_usa1_1 and
V0_usa1_3 <= V2_usa1_3 and
V0_csa1_1 <= V2_csa1_1 and
V0_csa1_3 <= V2_csa1_3 and
V0_usa1_1 <= C2_usa1_1 and
V0_usa1_3 <= C2_usa1_3 and
V0_csa1_1 <= C2_csa1_1 and
V0_csa1_3 <= C2_csa1_3 and
V3_usa1_1 <= V2_usa1_1 and
V3_usa1_3 <= V2_usa1_3 and
C2_usa1_1 <= C2_usa1_1 and
C2_usa1_3 <= C2_usa1_3 and
C2_csa1_1 <= C2_csa1_1 and
C2_csa1_3 <= C2_csa1_3 and
V2_usa1_1 <= V2_usa1_1 and
V2_usa1_3 <= V2_usa1_3 and
V2_csa1_1 <= V2_csa1_1 and
V2_csa1_3 <= V2_csa1_3 and
V2_usa1_1 <= C2_usa1_1 and
V2_usa1_3 <= C2_usa1_3 and
V2_csa1_1 <= C2_csa1_1 and
V2_csa1_3 <= C2_csa1_3 )
report "***FAILED TEST: c07s02b02x00p10n01i02012 - Ordering operators <, <= for composite type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02012arch;
|
gpl-2.0
|
db7afc786e21b4650561ece8997c58ff
| 0.554289 | 2.647987 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc381.vhd
| 4 | 2,006 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc381.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p04n01i00381ent IS
END c03s02b01x01p04n01i00381ent;
ARCHITECTURE c03s02b01x01p04n01i00381arch OF c03s02b01x01p04n01i00381ent IS
type bit_vctor is array (bit range '0' to '1') of integer;
BEGIN
TESTING: PROCESS
variable k : bit_vctor;
BEGIN
k('0') := 1;
k('1') := 0;
assert NOT (k('0') = 1 and
k('1') = 0 )
report "***PASSED TEST: c03s02b01x01p04n01i00381"
severity NOTE;
assert (k('0') = 1 and
k('1') = 0 )
report "***FAILED TEST: c03s02b01x01p04n01i00381 - An index constraint is compatible with the type denoted by the type mark if and only if the constraint defined by each discrete range is compatible with the corresponding subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p04n01i00381arch;
|
gpl-2.0
|
0c37aa2f00979780f9b9c7197016ddfd
| 0.653539 | 3.735568 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_07.vhd
| 4 | 2,052 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_ch_17_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_17_07 is
end entity ch_17_07;
----------------------------------------------------------------
architecture test of ch_17_07 is
begin
process is
-- code from book:
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : bit_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list : value_ptr;
-- end of code from book
begin
-- code from book:
if value_list /= null then
-- . . . -- do something with the list
-- not in book
report "value_list /= null";
-- end not in book
end if;
value_list := new value_cell'( B"1000", value_list );
value_list := new value_cell'( B"0010", value_list );
value_list := new value_cell'( B"0000", value_list );
-- end of code from book
wait;
end process;
end architecture test;
|
gpl-2.0
|
0d014c073fd133f62c89bf0b5f2888c7
| 0.553119 | 4.301887 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc616.vhd
| 4 | 3,979 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc616.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:44 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00616ent IS
END c03s04b01x00p01n01i00616ent;
ARCHITECTURE c03s04b01x00p01n01i00616arch OF c03s04b01x00p01n01i00616ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_array_st_file is file of record_array_st;
constant C1 : boolean := true;
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
constant C28 : boolean_vector_st :=(others => C1);
constant C29 : severity_level_vector_st :=(others => C4);
constant C30 : integer_vector_st :=(others => C5);
constant C31 : real_vector_st :=(others => C6);
constant C32 : time_vector_st :=(others => C7);
constant C33 : natural_vector_st :=(others => C8);
constant C34 : positive_vector_st :=(others => C9);
constant C35 : record_array_st := (C28,C29,C30,C31,C32,C33,C34);
BEGIN
TESTING: PROCESS
file filein : record_array_st_file open write_mode is "iofile.34";
BEGIN
for i in 1 to 100 loop
write(filein, C35);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00616 - The output file will be verified by test s010270.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00616arch;
|
gpl-2.0
|
5f0625d5698c6a995e54a90c8d5a30d8
| 0.607439 | 3.74318 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2163.vhd
| 4 | 2,056 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2163.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02163ent IS
END c07s02b04x00p22n01i02163ent;
ARCHITECTURE c07s02b04x00p22n01i02163arch OF c07s02b04x00p22n01i02163ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_2 is positive_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : positive_2;
variable l_operand : positive := 1 ;
variable r_operand : positive := 89 ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result = ( 1, 89 ))
report "***PASSED TEST: c07s02b04x00p22n01i02163"
severity NOTE;
assert (result = ( 1, 89 ))
report "***FAILED TEST: c07s02b04x00p22n01i02163 - Concatenation of element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02163arch;
|
gpl-2.0
|
7afdd2a4a274bda48f2197074dff058e
| 0.664397 | 3.751825 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc668.vhd
| 4 | 6,912 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc668.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:57 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00668ent IS
END c03s04b01x00p01n01i00668ent;
ARCHITECTURE c03s04b01x00p01n01i00668arch OF c03s04b01x00p01n01i00668ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
i: record_array_st;
end record;
type array_rec_rec is array (integer range <>) of record_of_records;
type array_rec_rec_file is file of array_rec_rec;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C28 : boolean_vector_st := (others => C1);
constant C29 : severity_level_vector_st := (others => C4);
constant C30 : integer_vector_st := (others => C5);
constant C31 : real_vector_st := (others => C6);
constant C32 : time_vector_st := (others => C7);
constant C33 : natural_vector_st := (others => C8);
constant C34 : positive_vector_st := (others => C9);
constant C35 : record_array_st := (C28,C29,C30,C31,C32,C33,C34);
constant C37 : record_of_records := (C26,C27,C35);
constant C59: array_rec_rec(0 to 7) :=(others => C37);
BEGIN
TESTING: PROCESS
file filein : array_rec_rec_file open write_mode is "iofile.15";
BEGIN
for i in 1 to 100 loop
write(filein,C59);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00668 - The output file will be verified by test s010118.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00668arch;
|
gpl-2.0
|
769c39297f33cea86a59a8ba79414107
| 0.558015 | 3.774986 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc466.vhd
| 4 | 3,392 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc466.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00466ent IS
END c03s02b01x01p19n01i00466ent;
ARCHITECTURE c03s02b01x01p19n01i00466arch OF c03s02b01x01p19n01i00466ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type integer_vector is array (natural range <>) of integer;
subtype integer_vector_range is integer_vector(hi_to_low_range);
constant C66: integer_vector_range := (others => 3);
function complex_scalar(s : integer_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_vector_range;
signal S2 : integer_vector_range;
signal S3 : integer_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00466"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00466 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00466arch;
|
gpl-2.0
|
b8b2139d0adaa1a10e8f79ea8724f4c9
| 0.655955 | 3.682953 | false | true | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.f-Mul.core/a.b.f.a-BoothMul.vhd
| 1 | 6,588 |
--------------------------------------------------------------------------------
-- FILE: BoothMul
-- DESC: Booth's Multiplier
--
-- Author:
-- Create: 2015-08-14
-- Update: 2015-09-28
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity BoothMul is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE/2;
STAGE : integer := C_MUL_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
en: in std_logic;
lock: in std_logic;
sign: in std_logic;
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE*2-1 downto 0):=(others=>'0') -- Data Out
);
end BoothMul;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture booth_mul_arch of BoothMul is
component BoothEncoder is
port(
din: in std_logic_vector(2 downto 0);
sel: out std_logic_vector(2 downto 0)
);
end component;
component BoothGenerator is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE/2;
STAGE : integer := C_MUL_STAGE
);
port(
a: in std_logic_vector(DATA_SIZE*2-1 downto 0);
ya, y2a: out std_logic_vector(DATA_SIZE*2-1 downto 0)
);
end component;
component Mux is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE/2
);
port(
sel: in std_logic;
din0: in std_logic_vector(DATA_SIZE-1 downto 0);
din1: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Adder is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
cin: in std_logic;
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
s : out std_logic_vector(DATA_SIZE-1 downto 0);
cout: out std_logic
);
end component;
component AddSub is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE/2
);
port(
as: in std_logic; -- Add(Active High)/Sub(Active Low)
a, b: in std_logic_vector(DATA_SIZE-1 downto 0); -- Operands
re: out std_logic_vector(DATA_SIZE-1 downto 0); -- Return value
cout: out std_logic -- Carry
);
end component;
component Reg is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
rst: in std_logic;
en : in std_logic;
clk: in std_logic;
din: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
signal sel:std_logic_vector(2 downto 0);
signal ya, y2a : std_logic_vector(DATA_SIZE*2-1 downto 0);
signal e_a, e_a_dir, a_mux: std_logic_vector(DATA_SIZE*2-1 downto 0);
signal e_b, e_b_dir, b_mux: std_logic_vector(DATA_SIZE downto 0);
signal mux_out, zero_out, add_out, add_out_reg:std_logic_vector(DATA_SIZE*2-1 downto 0);
signal c_state, n_state : integer:=0;
signal en_input, sel_ab, local_rst, en_o, reg_rst : std_logic;
signal adj_sum : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal adj_cout : std_logic:='0';
signal adj_final, adj_final_mod : std_logic_vector(DATA_SIZE*2-1 downto 0):=(others=>'0');
signal adj_mid_h : std_logic_vector(1 downto 0):=(others=>'0');
signal adj_mid_l : std_logic_vector(DATA_SIZE*2-3 downto 0):=(others=>'0');
signal a_m, b_m: std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Operands
begin
P0: process(clk, en, en_input, lock)
begin
if rising_edge(clk) then
if en='1' and en_input='1' then
e_a <= e_a_dir;
e_b <= e_b_dir;
adj_final_mod <= adj_final;
else
e_b(DATA_SIZE-2 downto 0)<=e_b(DATA_SIZE downto 2);
e_b(DATA_SIZE downto DATA_SIZE-1)<=(others=>'0');
e_a(DATA_SIZE*2-1 downto 2)<=e_a(DATA_SIZE*2-3 downto 0);
e_a(1 downto 0)<=(others=>'0');
end if;
end if;
end process;
e_a_dir(DATA_SIZE-1) <= a(DATA_SIZE-1) and sign;
e_a_dir(DATA_SIZE-2 downto 0)<=a(DATA_SIZE-2 downto 0);
e_a_dir(DATA_SIZE*2-1 downto DATA_SIZE)<=(others=>(a(DATA_SIZE-1) and sign));
e_b_dir(DATA_SIZE) <= b(DATA_SIZE-1) and sign;
e_b_dir(DATA_SIZE-1 downto 1)<=b(DATA_SIZE-2 downto 0);
e_b_dir(0) <= '0';
a_m <= a when b(DATA_SIZE-1)='1' else (others=>'0');
b_m <= b when a(DATA_SIZE-1)='1' else (others=>'0');
ADJUST0: Adder
generic map(DATA_SIZE)
port map('0', a_m, b_m, adj_sum, adj_cout);
adj_mid_h <= adj_cout & adj_sum(DATA_SIZE-1) when (a(DATA_SIZE-1) and b(DATA_SIZE-1))='0' else (adj_cout and adj_sum(DATA_SIZE-1)) & (not adj_sum(DATA_SIZE-1));
adj_mid_l(DATA_SIZE*2-3 downto DATA_SIZE-1) <= adj_sum(DATA_SIZE-2 downto 0);
adj_mid_l(DATA_SIZE-2 downto 0) <= (others=>'0');
adj_final <= adj_mid_h & adj_mid_l when sign='0' else (others=>'0');
a_mux <= e_a;
b_mux <= e_b;
BEC0: BoothEncoder
port map(e_b(2 downto 0), sel);
ya <= a_mux;
y2a(DATA_SIZE*2-1 downto 1) <= a_mux(DATA_SIZE*2-2 downto 0);
y2a(0) <= '0';
MUX0: Mux
generic map(DATA_SIZE*2)
port map(sel(0), ya, y2a, mux_out);
zero_out <= mux_out when sel(2)='1' else (others=>'0');
ADDSUBn: AddSub
generic map(DATA_SIZE*2)
port map(sel(1), add_out_reg, zero_out, add_out, open);
reg_rst <= rst and local_rst;
REG0: Reg
generic map(DATA_SIZE*2)
port map(reg_rst, en_o, clk, add_out, add_out_reg);
ADJUST1: Adder
generic map(DATA_SIZE*2)
port map('0', add_out_reg, adj_final_mod, o, open);
-- FSM
-- NEXT STATE GENERATOR
P_NSG1: process(en, c_state, lock)
begin
if en='1' and lock='1' then
n_state<=SG_ST0;
else
if en='1' and c_state = SG_ST0 and lock='0' then
n_state<=SG_ST1;
else
if c_state = SG_ST0 or c_state >= STAGE-1 then
n_state <= SG_ST0;
else
n_state <= c_state + 1;
end if;
end if;
end if;
end process;
-- OUTPUT GENERATOR
P_OUT1: process(c_state)
begin
if c_state=SG_ST1 then
en_input <= '0';
sel_ab <= '0';
en_o <= '1';
local_rst <= '1';
elsif c_state>SG_ST1 and c_state<STAGE then
en_input <= '0';
sel_ab <= '1';
en_o <= '1';
local_rst <= '1';
else
en_input <= '1';
sel_ab <= '1';
en_o <= '0';
local_rst <= '0';
end if;
end process;
-- NEXT STATE REGISTER
P_REG1: process(rst, clk)
begin
if rst='0' then
c_state <= SG_ST0;
else
if rising_edge(clk) then
c_state <= n_state;
end if;
end if;
end process;
end booth_mul_arch;
|
mit
|
df9fdbb47431b15fb44e65db5fe13401
| 0.575896 | 2.64154 | false | false | false | false |
tristanseifert/68komputer
|
BusRouter.vhd
| 1 | 7,686 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BusRouter is
PORT(
SW: IN std_logic_vector(9 downto 0);
KEY: IN std_logic_vector(3 downto 0);
LEDR: OUT std_logic_vector(9 downto 0) := (others => '0');
LEDG: OUT std_logic_vector(7 downto 0) := (others => '0');
CLOCK_24: IN std_logic_vector(1 downto 0);
CLOCK_27: IN std_logic_vector(1 downto 0);
CLOCK_50: IN std_logic;
-- video
VGA_R: OUT std_logic_vector(3 downto 0);
VGA_G: OUT std_logic_vector(3 downto 0);
VGA_B: OUT std_logic_vector(3 downto 0);
VGA_VS: OUT std_logic := '0';
VGA_HS: OUT std_logic := '0';
-- SRAM
SRAM_ADDR: OUT std_logic_vector(17 downto 0);
SRAM_DQ: INOUT std_logic_vector(15 downto 0);
SRAM_CE_N: OUT std_logic;
SRAM_OE_N: OUT std_logic;
SRAM_WE_N: OUT std_logic;
SRAM_LB_N: OUT std_logic;
SRAM_UB_N: OUT std_logic;
-- SDRAM
DRAM_CS_N: OUT std_logic;
DRAM_WE_N: OUT std_logic;
DRAM_CAS_N: OUT std_logic;
DRAM_RAS_N: OUT std_logic;
DRAM_ADDR: OUT std_logic_vector(11 downto 0);
DRAM_BA_0: OUT std_logic;
DRAM_BA_1: OUT std_logic;
DRAM_CKE: OUT std_logic;
DRAM_CLK: OUT std_logic;
DRAM_DQ: INOUT std_logic_vector(15 downto 0);
DRAM_LDQM: OUT std_logic;
DRAM_UDQM: OUT std_logic;
-- Flash memory
FL_ADDR: OUT std_logic_vector(21 downto 0);
FL_DQ: INOUT std_logic_vector(7 downto 0);
FL_OE_N: OUT std_logic := '1';
FL_RST_N: OUT std_logic := '1';
FL_WE_N: OUT std_logic := '1';
-- PS2
PS2_CLK: INOUT std_logic;
PS2_DAT: INOUT std_logic;
-- SD card
SD_MISO: IN std_logic;
SD_MOSI: OUT std_logic;
SD_SCLK: OUT std_logic;
SD_CS: OUT std_logic;
-- UART
UART_RXD: IN std_logic;
UART_TXD: OUT std_logic;
-- audio codec
I2C_SCLK: INOUT std_logic;
I2C_SDAT: INOUT std_logic;
AUD_ADCDAT: IN std_logic;
AUD_ADCLRCK: OUT std_logic;
AUD_BCLK: OUT std_logic;
AUD_XCK: OUT std_logic;
AUD_DACDAT: OUT std_logic;
AUD_DACLRCK: OUT std_logic;
-- seven segment displays
HEX0: OUT std_logic_vector(6 downto 0);
HEX1: OUT std_logic_vector(6 downto 0);
HEX2: OUT std_logic_vector(6 downto 0);
HEX3: OUT std_logic_vector(6 downto 0)
);
end BusRouter;
architecture behavioral of BusRouter is
signal clk_cpu: std_logic;
signal clk_sdram: std_logic;
signal sys_reset: std_logic := '1';
-- 68k bus: system control
signal bus_reset: std_logic := '1';
signal bus_clk: std_logic; -- CPU clock
signal bus_halt: std_logic := '1';
signal bus_error: std_logic := '1';
-- 68k bus: data
signal bus_data: std_logic_vector(15 downto 0) := (others => 'Z');
signal bus_addr: std_logic_vector(23 downto 0) := (others => '0');
-- 68k bus: bus control
signal bus_as: std_logic := '1';
signal bus_rw: std_logic := '1'; -- read = 1, write = 0
signal bus_uds: std_logic := '1'; -- upper and lower byte strobes
signal bus_lds: std_logic := '1';
signal bus_dtack: std_logic := '1'; -- data acknowledge, driven by peripheral
-- 68k bus: bus arbitration
signal bus_br: std_logic := '1'; -- assert to request bus
signal bus_bg: std_logic := '1'; -- asserted when bus is free
signal bus_bgack: std_logic := '1'; -- assert to acknowledge bus request
-- 68k bus: interrupt control
signal bus_irq: std_logic_vector(2 downto 0) := (others => '1');
-- 68k bus: processor status
signal bus_fc: std_logic_vector(3 downto 0);
-- 5Hz blink clock generator
signal blink_clk: std_logic;
-- chip selects for various HW (low active)
signal cs_rom: std_logic := '1';
signal cs_ram: std_logic := '1';
signal cs_video: std_logic := '1';
begin
-- VDP
u_VideoController: entity work.VideoController(behavioral)
port map(
reset => sys_reset,
In_Clk_24 => CLOCK_24(0),
Out_R => VGA_R,
Out_G => VGA_G,
Out_B => VGA_B,
Out_HSync => VGA_HS,
Out_VSync => VGA_VS,
SRAM_Addr => SRAM_ADDR,
SRAM_Data => SRAM_DQ,
SRAM_CE => SRAM_CE_N,
SRAM_OE => SRAM_OE_N,
SRAM_WE => SRAM_WE_N,
SRAM_LB => SRAM_LB_N,
SRAM_UB => SRAM_UB_N,
-- bus interface
bus_clk => bus_clk,
bus_data => bus_data,
bus_address => bus_addr(18 downto 0),
bus_rw => bus_rw,
bus_as => bus_as,
bus_dtack => bus_dtack,
bus_uds => bus_uds,
bus_lds => bus_lds,
bus_cs => cs_video
);
-- SDRAM controller
u_sdram: entity work.BusSDRAM(behavioral)
port map(
reset => sys_reset,
reset_n => bus_reset,
sdram_clk => clk_sdram,
bus_cs => cs_ram,
bus_clk => clk_cpu,
bus_address => bus_addr (22 downto 0),
bus_data => bus_data,
bus_rw => bus_rw,
bus_as => bus_as,
bus_dtack => bus_dtack,
bus_uds => bus_uds,
bus_lds => bus_lds,
DRAM_CS_N => DRAM_CS_N,
DRAM_WE_N => DRAM_WE_N,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA_0 => DRAM_BA_0,
DRAM_BA_1 => DRAM_BA_1,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_DQ => DRAM_DQ,
DRAM_LDQM => DRAM_LDQM,
DRAM_UDQM => DRAM_UDQM
);
-- bus PLL
u_buspll: entity work.BusPLL(SYN)
port map(
areset => sys_reset,
inclk0 => CLOCK_50,
c0 => clk_cpu,
c1 => clk_sdram
);
-- debug monitor
u_monitor: entity work.BusMonitor(behavioral)
port map(
clk_cpu => clk_cpu,
blink_clk => blink_clk,
sys_reset => sys_reset,
bus_reset => bus_reset,
bus_clk => bus_clk,
bus_halt => bus_halt,
bus_error => bus_error,
bus_data => bus_data,
bus_addr => bus_addr,
bus_as => bus_as,
bus_rw => bus_rw,
bus_uds => bus_uds,
bus_lds => bus_lds,
bus_dtack => bus_dtack,
bus_br => bus_br,
bus_bg => bus_bg,
bus_bgack => bus_bgack,
bus_irq => bus_irq,
HEX0 => HEX0,
HEX1 => HEX1,
HEX2 => HEX2,
HEX3 => HEX3,
SW => SW,
KEY => KEY,
LEDR => LEDR,
LEDG => LEDG
);
-- Address decoder: tied to the FALLING edge of bus_clk
process (bus_clk, sys_reset, bus_as)
begin
-- if reset, make sure everything is deselected
if sys_reset='1' then
-- decode address
elsif falling_edge(bus_clk) then
-- is the address on the bus valid?
if bus_as='0' then
-- decode high nybble
case bus_addr(23 downto 20) is
when x"0" =>
cs_rom <= '0';
when x"1" =>
cs_ram <= '0';
when x"2" =>
cs_ram <= '0';
when x"3" =>
cs_ram <= '0';
when x"4" =>
cs_ram <= '0';
when x"5" =>
cs_ram <= '0';
when x"6" =>
cs_ram <= '0';
when x"7" =>
cs_ram <= '0';
when x"8" =>
cs_ram <= '0';
when x"9" => -- video controller
cs_video <= '0';
when x"A" =>
when x"B" =>
when x"C" =>
when x"D" =>
when x"E" =>
when x"F" =>
end case;
else
-- address invalid
cs_rom <= '1';
cs_ram <= '1';
cs_video <= '1';
end if;
end if;
end process;
-- LED blink clock generator
process (clk_cpu, sys_reset)
variable cnt: integer := 0;
begin
if sys_reset='1'
then
cnt := 0;
elsif rising_edge(clk_cpu) then
if cnt = 741337
then
blink_clk <= NOT blink_clk;
cnt := 0;
else
cnt := cnt + 1;
end if;
end if;
end process;
-- reset logic
bus_reset <= NOT sys_reset;
end behavioral;
|
bsd-2-clause
|
b9657e8bcb6e7edded58d48b6e486144
| 0.550221 | 2.636707 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_07.vhd
| 4 | 1,648 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_07 is
end entity test_bench_03_07;
architecture test_cos_fixed_length_series of test_bench_03_07 is
signal theta, result : real := 0.0;
begin
dut : entity work.cos(fixed_length_series)
port map ( theta => theta, result => result );
stimulus : process is
constant pi : real := 3.1415927;
begin
wait for 10 ns;
theta <= pi / 6.0; wait for 10 ns;
theta <= pi / 4.0; wait for 10 ns;
theta <= pi / 3.0; wait for 10 ns;
theta <= pi / 2.0; wait for 10 ns;
wait;
end process stimulus;
end architecture test_cos_fixed_length_series;
|
gpl-2.0
|
d62772010995a788fa0d5ed3d838368f
| 0.619539 | 3.806005 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc696.vhd
| 4 | 3,157 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc696.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:05 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:39 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:44 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00696ent IS
END c03s04b01x00p23n01i00696ent;
ARCHITECTURE c03s04b01x00p23n01i00696arch OF c03s04b01x00p23n01i00696ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of SEVERITY_LEVEL;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.55";
-- Declare a variable into which we will read.
constant CON : SEVERITY_LEVEL := WARNING;
variable VAR : SEVERITY_LEVEL;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00696"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00696 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00696arch;
|
gpl-2.0
|
cb9a56ee4108e322c7682b4cf886217f
| 0.547989 | 4.037084 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd
| 4 | 1,725 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity triangle_waveform_wa is
port ( terminal pos, neg : electrical );
end entity triangle_waveform_wa;
----------------------------------------------------------------
architecture ideal of triangle_waveform_wa is
constant freq : real := 10_000.0; -- in Hz
constant period : real := 1.0 / freq;
constant amplitude : voltage := 5.0;
constant offset : voltage := 0.0;
signal square_wave : real := 0.0;
quantity v across i through pos to neg;
-- limit v : voltage with period / 10.0;
begin
process is
variable state : bit := '0';
begin
if state = '1' then
square_wave <= 1.0;
else
square_wave <= 0.0;
end if;
state := not state;
wait for period / 2.0;
end process;
v == offset + amplitude * square_wave'ramp(period / 2.0);
end architecture ideal;
|
gpl-2.0
|
d52f269d6114754044318259350b2513
| 0.649275 | 4.078014 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.a-ControlUnit.vhd
| 1 | 4,588 |
--------------------------------------------------------------------------------
-- FILE: ControlUnit
-- DESC: Control unit of DLX
--
-- Author:
-- Create: 2015-06-01
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity ControlUnit is
generic(
ISTR_SIZE : integer := C_SYS_ISTR_SIZE; -- Instruction Register Size
DATA_SIZE : integer := C_SYS_DATA_SIZE; -- Data Size
OPCD_SIZE : integer := C_SYS_OPCD_SIZE; -- Op Code Size
FUNC_SIZE : integer := C_SYS_FUNC_SIZE; -- Func Field Size for R-Type Ops
CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Control Word Size
CALU_SIZE : integer := C_CTR_CALU_SIZE; -- ALU Op Code Word Size
ADDR_SIZE : integer := C_SYS_ADDR_SIZE -- Address size
);
port(
clk : in std_logic;
rst : in std_logic;
ir : in std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
pc : in std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
reg_a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
ld_a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
sig_bal : in std_logic:='0';
sig_bpw : out std_logic:='0';
sig_jral: in std_logic:='0';
sig_ral : in std_logic;
sig_mul : in std_logic;
sig_div : in std_logic;
sig_sqrt: in std_logic;
cw : out std_logic_vector(CWRD_SIZE-1 downto 0);
calu : out std_logic_vector(CALU_SIZE-1 downto 0)
);
end ControlUnit;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture control_unit_arch of ControlUnit is
component CwGenerator is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE; -- Data Size
OPCD_SIZE : integer := C_SYS_OPCD_SIZE; -- Op Code Size
FUNC_SIZE : integer := C_SYS_FUNC_SIZE; -- Func Field Size for R-Type Ops
CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Control Word Size
CALU_SIZE : integer := C_CTR_CALU_SIZE -- ALU Op Code Word Size
);
port (
clk : in std_logic;
rst : in std_logic;
opcd : in std_logic_vector(OPCD_SIZE-1 downto 0);
func : in std_logic_vector(FUNC_SIZE-1 downto 0);
stall_flag : in std_logic_vector(4 downto 0);
taken : in std_logic;
cw : out std_logic_vector(CWRD_SIZE-1 downto 0);
calu : out std_logic_vector(CALU_SIZE-1 downto 0)
);
end component;
component StallGenerator is
generic(
CWRD_SIZE : integer := C_SYS_CWRD_SIZE
);
port(
rst : in std_logic;
clk : in std_logic;
sig_ral : in std_logic := '0'; -- from DataPath
sig_bpw : in std_logic := '0'; -- from Branch
sig_jral : in std_logic := '0'; -- from DataPath
sig_mul : in std_logic := '0'; -- from DataPath
sig_div : in std_logic := '0'; -- from DataPath
sig_sqrt : in std_logic := '0'; -- from DataPath
stall_flag : out std_logic_vector(4 downto 0):=(others=>'0')
);
end component;
component Branch is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
OPCD_SIZE : integer := C_SYS_OPCD_SIZE;
ADDR_SIZE : integer := C_SYS_ADDR_SIZE
);
port (
rst : in std_logic;
clk : in std_logic;
reg_a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
ld_a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
opcd : in std_logic_vector(OPCD_SIZE-1 downto 0):=(others=>'0');
addr : in std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
sig_bal : in std_logic:='0';
sig_bpw : out std_logic :='0';
sig_brt : out std_logic :='0'
);
end component;
signal stall_flag : std_logic_vector(4 downto 0);
signal sig_brt : std_logic;
signal en_branch : std_logic;
signal sig_bpw_tmp: std_logic;
begin
CW_GEN: CwGenerator
generic map(DATA_SIZE, OPCD_SIZE, FUNC_SIZE, CWRD_SIZE, CALU_SIZE)
port map(clk, rst, ir(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE), ir(FUNC_SIZE-1 downto 0), stall_flag, sig_brt, cw, calu);
S_GEN: StallGenerator
generic map(CWRD_SIZE)
port map(rst, clk, sig_ral, sig_bpw_tmp, sig_jral, sig_mul, sig_div, sig_sqrt, stall_flag);
BR : Branch
generic map(DATA_SIZE, OPCD_SIZE, ADDR_SIZE)
port map(rst, clk, reg_a, ld_a, ir(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE), pc, sig_bal, sig_bpw_tmp, sig_brt);
sig_bpw <= sig_bpw_tmp;
end control_unit_arch;
|
mit
|
4aea4d15e934c53188525978d554b2d3
| 0.569093 | 2.933504 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc750.vhd
| 4 | 22,323 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc750.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00750ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive :=1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00750ent;
ARCHITECTURE c01s01b01x01p05n02i00750arch OF c01s01b01x01p05n02i00750ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record:= (C85,C86,C88);
signal V1 : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
signal V2 : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
signal V3 : integer_vector(zero to fifteen) := (zero to fifteen => C5);
signal V4 : real_vector(zero to fifteen) := (zero to fifteen => C6);
signal V5 : time_vector (zero to fifteen) := (zero to fifteen => C7);
signal V6 : natural_vector(zero to fifteen):= (zero to fifteen => C8);
signal V7 : positive_vector(zero to fifteen):= (zero to fifteen => C9);
signal V8 : boolean_cons_vector:= C19;
signal V9 : severity_level_cons_vector:= C20;
signal V10 : integer_cons_vector:= C21;
signal V11 : real_cons_vector:= C22;
signal V12 : time_cons_vector:= C23;
signal V13 : natural_cons_vector := C24;
signal V14 : positive_cons_vector := C25;
signal V15 : boolean_cons_vectorofvector := C26;
signal V16 : severity_level_cons_vectorofvector:= C27;
signal V17 : integer_cons_vectorofvector:= C28;
signal V18 : real_cons_vectorofvector:= C29;
signal V19 : time_cons_vectorofvector:= C30;
signal V20 : natural_cons_vectorofvector:= C31;
signal V21 : positive_cons_vectorofvector:= C32;
signal V22 : record_std_package:= C50;
signal V23 : record_cons_array := C51;
signal V24 : record_cons_arrayofarray := C53 ;
signal V25 : boolean_vector_st := C70 ;
signal V26 : severity_level_vector_st:= C71;
signal V27 : integer_vector_st := C72;
signal V28 : real_vector_st := C73;
signal V29 : time_vector_st := C74;
signal V30 : natural_vector_st := C75;
signal V31 : positive_vector_st := C76;
signal V32 : record_array_st := C54a;
signal V33 : record_array_st := C54a;
signal V34 : record_array_new:= C54b;
signal V35 : record_of_records := C55;
signal V36 : byte := C60;
signal V37 : word := C61;
signal V41 : boolean_vector_range := C78;
signal V42 : severity_level_vector_range := C79;
signal V43 : integer_vector_range := C80;
signal V44 : real_vector_range:= C81 ;
signal V45 : time_vector_range := C82;
signal V46 : natural_vector_range := C83;
signal V47 : positive_vector_range := C84;
signal V48 : array_rec_std(zero to seven) := C85;
signal V49 : array_rec_cons(zero to seven) := C86;
signal V50 : array_rec_rec(zero to seven) := C88;
signal V51 : record_of_arr_of_record := C102;
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00750"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00750 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00750arch;
|
gpl-2.0
|
af33072d74c935a3a0340dd0e986ec51
| 0.558706 | 3.787411 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_06.vhd
| 4 | 2,879 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_06 is
end entity ch_04_06;
----------------------------------------------------------------
--library ieee; use ieee.std_logic_1164.std_ulogic;
library ieee; use ieee.std_logic_1164.all;
architecture test of ch_04_06 is
-- code from book:
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
--
subtype std_ulogic_word is std_ulogic_vector(0 to 31);
--
signal csr_offset : std_ulogic_vector(2 downto 1);
-- end of code from book
begin
process_04_2_b : process is
-- code from book:
type string is array (positive range <>) of character;
--
constant LCD_display_len : positive := 20;
subtype LCD_display_string is string(1 to LCD_display_len);
variable LCD_display : LCD_display_string := (others => ' ');
--
type bit_vector is array (natural range <>) of bit;
--
subtype byte is bit_vector(7 downto 0);
--
variable channel_busy_register : bit_vector(1 to 4);
--
constant ready_message : string := "Ready ";
--
variable current_test : std_ulogic_vector(0 to 13) := "ZZZZZZZZZZ----";
--
constant all_ones : std_ulogic_vector(15 downto 0) := X"FFFF";
-- end of code from book
begin
-- code from book:
channel_busy_register := b"0000";
-- end of code from book
wait;
end process process_04_2_b;
end architecture test;
|
gpl-2.0
|
21a0c911f1942e1749cb86e9a3bcdcc0
| 0.510594 | 4.636071 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd
| 4 | 66,048 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo;
architecture rudder_servo of rudder_servo is
-- Component declarations
-- Signal declarations
terminal error : electrical;
terminal ll_in : electrical;
terminal ll_out : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
servo_limiter : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => ll_out,
output => servo_out
);
lead_lag : entity work.lead_lag_e(simple)
generic map(
k => 400.0,
f1 => 5.0,
f2 => 2000.0
)
port map(
input => ll_in,
output => ll_out
);
end rudder_servo;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
-- w2 == w1*ratio;
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang'above(ang_max) use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang'above(ang_min) use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity switch_dig_log is
generic
(
trans_time : real := 1.0e-9;
r_closed : resistance := 1.0e-3;
r_open : resistance := 1.0e6
);
port
(
terminal p1 : electrical ;
sw_state : in std_logic ;
terminal p2 : electrical
);
begin
end switch_dig_log ;
-----------------------------------------------------------------------------------------
architecture linear of switch_dig_log is
signal r_sig : resistance := r_open; -- create internal signal for CreateState process
quantity v across i through p1 to p2;
quantity r : resistance;
begin
-- purpose: Detect Switch state and assign resistance value to r_sig
-- type : combinational
-- inputs : sw_state
-- outputs: r_sig
DetectState: process (sw_state)
begin -- process DetectState
if (sw_state'event and sw_state = '0') then
r_sig <= r_open;
elsif (sw_state'event and sw_state = '1') then
r_sig <= r_closed;
end if;
end process DetectState;
-- Characteristic equations
r == r_sig'ramp(trans_time, trans_time);
v == r*i;
end architecture linear;
-------------------------------------------------------------------------------------------
architecture log of switch_dig_log is
constant log10_r_open : real := log10(r_open);
constant log10_r_closed : real := log10(r_closed);
signal log10_r_sig : resistance := log10_r_open; -- create internal signal for CreateState process
quantity v across i through p1 to p2;
quantity r : resistance;
quantity log10_r : real;
begin
-- purpose: Detect Switch state and assign resistance value to r_sig
-- type : combinational
-- inputs : sw_state
-- outputs: r_sig
DetectState: process (sw_state)
begin -- process DetectState
if (sw_state'event and sw_state = '0') then
log10_r_sig <= log10_r_open;
elsif (sw_state'event and sw_state = '1') then
log10_r_sig <= log10_r_closed;
end if;
end process DetectState;
-- Characteristic equations
log10_r == log10_r_sig'ramp(trans_time, trans_time);
r == 10**log10_r;
v == r*i;
end architecture log;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : buff.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Simple Buffer with delay time
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity buff is
generic (
delay : time := 0 ns); -- Delay time
port (
input : in std_logic;
output : out std_logic);
end entity buff;
architecture ideal of buff is
begin
output <= input after delay;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Inverter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY inverter IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
input : IN std_logic;
output : OUT std_logic);
END ENTITY inverter;
ARCHITECTURE ideal OF inverter IS
BEGIN
output <= NOT input AFTER delay;
END ARCHITECTURE ideal;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : opamp.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: 3-pin OpAmp model with behavioral architecture
-- Uses Q'LTF function to define open-loop response
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity opamp is
-- Initialize parameters
generic (rin : resistance := 1.0e6; -- Input resistance [Ohms]
rout : resistance := 100.0; -- Output resistance (Ohms]
avol : real := 100.0e3; -- Open loop gain
f_0dB : real := 1.0e6 -- Unity Gain Frequency [Hz]
);
-- Define ports as electrical terminals
port (
terminal in_pos, in_neg, output : electrical);
end entity opamp;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Characteristics modeled:
-- 1. Open loop gain
-- 2. Frequency characteristics (single pole response)
-- 3. Input and output resistance
-- Uses Q'Ltf function to create open loop gain and roll off
-------------------------------------------------------------------------------
architecture basic of opamp is
-- Declare constants
constant f_3db : real := f_0db / avol; -- -3dB frequency
constant w_3dB : real := math_2_pi*f_3dB; -- -3dB freq in radians
-- Numerator and denominator for Q'LTF function
constant num : real_vector := (0 => avol);
constant den : real_vector := (1.0, 1.0/w_3dB);
-- Declare input and output quantities
quantity v_in across i_in through in_pos to in_neg;
quantity v_out across i_out through output;
begin -- ARCHITECTURE basic
i_in == v_in / rin; -- input current
v_out == v_in'ltf(num, den) + i_out*rout; -- output voltage
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical Resistor Model
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY resistor IS
-- Initialize parameters
GENERIC (
res : RESISTANCE); -- resistance (no initial value)
-- Define ports as electrical terminals
PORT (
TERMINAL p1, p2 : ELECTRICAL);
END ENTITY resistor;
-- Ideal Architecture (V = I*R)
ARCHITECTURE ideal OF resistor IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH p1 TO p2;
BEGIN
-- Characteristic equations
v == i*res;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Constant Voltage Source (Includes Frequency Domain settings)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY v_constant IS
-- Initialize parameters
GENERIC (
level : VOLTAGE; -- Constant voltage value (V)
ac_mag : VOLTAGE := 1.0; -- AC magnitude (V)
ac_phase : real := 0.0); -- AC phase (degrees)
-- Define ports as electrical terminals
PORT (
TERMINAL pos, neg : ELECTRICAL);
END ENTITY v_constant;
-- Ideal Architecture (I = constant)
ARCHITECTURE ideal OF v_constant IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH pos TO neg;
-- Declare quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
v == level;
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : comparator_d.vhd
-- Author : Mentor Graphics
-- Created : 2001/08/03
-- Last update: 2001/08/03
-------------------------------------------------------------------------------
-- Description: Voltage comparator with digital output
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/08/03 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use IEEE natures and packages
library IEEE;
use ieee.std_logic_1164.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
use IEEE_proposed.ENERGY_SYSTEMS.all;
entity comparator_d is
port (
terminal in_pos : electrical;
terminal in_neg : electrical;
signal output : out std_logic := '1' -- Digital output
);
end comparator_d;
-------------------------------------------------------------------------------
-- Behavioral architecture
-------------------------------------------------------------------------------
architecture behavioral of comparator_d is
quantity Vin across in_pos;
quantity Vref across in_neg;
begin -- behavioral
-- purpose: Detect threshold crossing and assign event on output
-- type : combinational
-- inputs : vin'above(thres)
-- outputs: pulse_signal
process (Vin'above(Vref)) is
begin -- PROCESS
if Vin'above(Vref) then
output <= '1' after 1us;
else
output <= '0' after 1us;
end if;
end process;
end behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity pwm_mac is
port(
terminal inp : electrical;
terminal inm : electrical;
dig_out : out std_logic
);
end pwm_mac;
architecture pwm_mac of pwm_mac is
-- Component declarations
-- Signal declarations
terminal cmp_in : electrical;
terminal plse_in : electrical;
terminal XSIG010002 : electrical;
terminal XSIG010003 : electrical;
begin
-- Signal assignments
-- Component instances
U1 : entity work.opamp(basic)
port map(
in_neg => XSIG010002,
in_pos => inm,
output => cmp_in
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => XSIG010002,
p2 => cmp_in
);
v2 : entity work.v_constant(ideal)
generic map(
level => 0.0
)
port map(
pos => XSIG010003,
neg => ELECTRICAL_REF
);
R2 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => plse_in,
p2 => XSIG010002
);
R3 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => inp,
p2 => XSIG010002
);
XCMP4 : entity work.comparator_d(behavioral)
port map(
output => dig_out,
in_pos => XSIG010003,
in_neg => cmp_in
);
v9 : entity work.v_pulse(ideal)
generic map(
initial => -4.7,
pulse => 4.7,
ti2p => 200 us,
tp2i => 200 us,
delay => 1 us,
width => 1 us,
period => 405 us
)
port map(
pos => plse_in,
neg => ELECTRICAL_REF
);
end pwm_mac;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : diode_pwl.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Diode model with ideal architecture
-- Currently no Generics due to bug in DV
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
-- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin)
use IEEE_proposed.energy_systems.all;
ENTITY diode_pwl IS
GENERIC (
ron : real; -- equivalent series resistance
roff : real); -- leakage resistance
PORT (
TERMINAL p, -- positive pin
m : electrical); -- minus pin
END ENTITY diode_pwl;
ARCHITECTURE simple OF diode_pwl IS
QUANTITY v across i through p TO m;
BEGIN -- simple ARCHITECTURE
if v'Above(0.0) use
i == v/ron;
elsif not v'Above(0.0) use
i == v/roff;
else
i == 0.0;
end use;
break on v'Above(0.0);
END ARCHITECTURE simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity pwm_H_bridge is
port(
terminal mot_ccw : electrical;
terminal pwr_in : electrical;
terminal mot_cw : electrical;
terminal src_in : electrical
);
end pwm_H_bridge;
architecture pwm_H_bridge of pwm_H_bridge is
-- Component declarations
-- Signal declarations
signal pwm_out : std_logic;
signal sw_ccw : std_logic;
signal sw_cw : std_logic;
begin
-- Signal assignments
-- Component instances
sw2 : entity work.switch_dig_log(linear)
generic map(
trans_time => 1.0e-5,
r_closed => 0.1
)
port map(
sw_state => sw_cw,
p2 => pwr_in,
p1 => mot_cw
);
sw3 : entity work.switch_dig_log(linear)
generic map(
trans_time => 1.0e-5,
r_closed => 0.1
)
port map(
sw_state => sw_ccw,
p2 => mot_cw,
p1 => ELECTRICAL_REF
);
U1 : entity work.buff(ideal)
port map(
input => pwm_out,
output => sw_cw
);
U2 : entity work.inverter(ideal)
port map(
input => pwm_out,
output => sw_ccw
);
sw5 : entity work.switch_dig_log(linear)
generic map(
trans_time => 1.0e-5,
r_closed => 0.1
)
port map(
sw_state => sw_ccw,
p2 => pwr_in,
p1 => mot_ccw
);
sw6 : entity work.switch_dig_log(linear)
generic map(
trans_time => 1.0e-5,
r_closed => 0.1
)
port map(
sw_state => sw_cw,
p2 => mot_ccw,
p1 => ELECTRICAL_REF
);
pwm : entity work.pwm_mac
port map(
inp => src_in,
dig_out => pwm_out,
inm => ELECTRICAL_REF
);
D7 : entity work.diode_pwl(simple)
generic map(
roff => 100.0e3,
ron => 0.001
)
port map(
p => mot_cw,
m => pwr_in
);
D8 : entity work.diode_pwl(simple)
generic map(
ron => 0.001,
roff => 100.0e3
)
port map(
p => mot_ccw,
m => pwr_in
);
D9 : entity work.diode_pwl(simple)
generic map(
ron => 0.001,
roff => 100.0e3
)
port map(
p => ELECTRICAL_REF,
m => mot_cw
);
D10 : entity work.diode_pwl(simple)
generic map(
ron => 0.001,
roff => 100.0e3
)
port map(
p => ELECTRICAL_REF,
m => mot_ccw
);
end pwm_H_bridge;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical sinusoidal voltage source (stick.vhd)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY stick IS
-- Initialize parameters
GENERIC (
freq : real; -- frequency, [Hertz]
amplitude : real; -- amplitude, [Volt]
phase : real := 0.0; -- initial phase, [Degree]
offset : real := 0.0; -- DC value, [Volt]
df : real := 0.0; -- damping factor, [1/second]
ac_mag : real := 1.0; -- AC magnitude, [Volt]
ac_phase : real := 0.0); -- AC phase, [Degree]
-- Define ports as electrical terminals
PORT (
TERMINAL v_out : ELECTRICAL);
END ENTITY stick;
-- Ideal Architecture
ARCHITECTURE ideal OF stick IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
-- Declare Quantity for Phase in radians (calculated below)
QUANTITY phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : inductor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Inductor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity inductor is
generic (
ind : inductance; -- Nominal inductance
i_ic : real := real'low); -- Initial current (use IF statement below
-- to activate)
port (
terminal p1, p2 : electrical);
end entity inductor;
-------------------------------------------------------------------------------
-- Ideal Architecture (V = L * di/dt)
-- Includes initial condition
-------------------------------------------------------------------------------
architecture ideal of inductor is
-- Declare Branch Quantities
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and i_ic /= real'low use
i == i_ic;
else
v == ind * i'dot; -- characteristic equation
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : capacitor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Capacitor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity capacitor is
generic (
cap : capacitance; -- Capacitance [F]
v_ic : real := real'low; -- Initial voltage (activated by
-- IF statement below)
r_esr : resistance := 0.0); -- Equivalent Series Capicitance
-- (used only in ESR architecture)
port (
terminal p1, p2 : electrical);
end entity capacitor;
-------------------------------------------------------------------------------
-- Ideal Architecture (I = C * dV/dt)
-- Includes initial condition
-------------------------------------------------------------------------------
architecture ideal of capacitor is
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and v_ic /= real'low use
v == v_ic;
else
i == cap * v'dot; -- characteristic equation
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Architecture includes effects of Equivalent Series Capacitance
-------------------------------------------------------------------------------
architecture ESR of capacitor is
quantity v across i through p1 to p2;
quantity vc : voltage; -- Internal voltage across capacitor
begin
if domain = quiescent_domain and v_ic /= real'low use
vc == v_ic;
i == 0.0;
else
vc == v - (i * r_esr);
i == cap * vc'dot;
end use;
end architecture ESR;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity buck_sw is
generic (
Vd : voltage := 0.7; -- Diode Voltage
Vramp : voltage := 2.5); -- P-P amplitude of ramp voltage
port (
terminal input, output, ref, ctrl: electrical);
end entity buck_sw;
architecture average of buck_sw is
quantity Vout across Iout through output to ref;
quantity Vin across input to ref;
quantity Vctrl across ctrl to ref;
begin -- bhv
Vout + Vd == Vctrl * Vin / Vramp;
end average;
--
-- Loop control switch
library IEEE;
use IEEE.std_logic_1164.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity sw_LoopCtrl is
generic (r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
sw_state : integer := 1);
port (terminal c, p1, p2 : electrical);
end entity sw_LoopCtrl;
architecture ideal of sw_LoopCtrl is
quantity v1 across i1 through c to p1;
quantity v2 across i2 through c to p2;
quantity r1, r2 : resistance;
begin
if (sw_state = 1) use
r1 == r_closed;
r2 == r_open;
elsif (sw_state = 2) use
r1 == r_open;
r2 == r_closed;
else
r1 == r_closed;
r2 == r_open;
end use;
v1 == r1*i1;
v2 == r2*i2;
end architecture ideal;
--
library ieee, ieee_proposed;
use ieee.math_real.all;
use IEEE_proposed.electrical_systems.all;
entity comp_2p2z is
generic (
gain : real := 100.0; -- High DC gain for good load regulation
fp1 : real := 7.5e3; -- Pole location to achieve crossover frequency
fp2 : real := 531.0e3; -- Pole location to cancel effect of ESR
fz1 : real := 806.0; -- Zero locations to cancel LC filter poles
fz2 : real := 806.0);
port (
terminal input, output, ref : electrical);
end entity comp_2p2z;
architecture ltf of comp_2p2z is
quantity vin across input to ref;
quantity vout across iout through output to ref;
constant wp1 : real := math_2_pi*fp1; -- Pole freq (in radians)
constant wp2 : real := math_2_pi*fp2;
constant wz1 : real := math_2_pi*fz1; -- Zero freq (in radians)
constant wz2 : real := math_2_pi*fz2;
constant num : real_vector := (1.0, 1.0/wz1 + 1.0/wz2, 1.0/(wz1*wz2));
constant den : real_vector := (1.0e-9,1.0,1.0/wp1+1.0/wp2,1.0/(wp1*wp2));
begin
vout == -1.0*gain*vin'ltf(num, den);
end architecture ltf;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity ex_buck is
port(
terminal pwr_out : electrical
);
end ex_buck;
architecture ex_buck of ex_buck is
-- Component declarations
-- Signal declarations
terminal vcomp_out : electrical;
terminal vctrl : electrical;
terminal vctrl_init : electrical;
terminal vin : electrical;
terminal vmid : electrical;
terminal XSIG010004 : electrical;
begin
-- Signal assignments
-- Component instances
l1 : entity work.inductor(ideal)
generic map(
ind => 6.5e-3
)
port map(
p1 => vmid,
p2 => pwr_out
);
c1 : entity work.capacitor(ideal)
generic map(
cap => 6.0e-6,
r_esr => 50.0e-3
)
port map(
p1 => pwr_out,
p2 => ELECTRICAL_REF
);
buck_sw1 : entity work.buck_sw(average)
port map(
output => vmid,
ref => ELECTRICAL_REF,
ctrl => vctrl,
input => vin
);
sw1 : entity work.sw_LoopCtrl(ideal)
generic map(
sw_state => 1
)
port map(
p2 => vctrl_init,
c => vctrl,
p1 => vcomp_out
);
comp_2p2z1 : entity work.comp_2p2z(ltf)
port map(
ref => XSIG010004,
output => vcomp_out,
input => pwr_out
);
v1 : entity work.v_pulse(ideal)
generic map(
initial => 42.0,
pulse => 42.0,
delay => 10ms,
width => 100ms,
period => 1000ms
)
port map(
pos => vin,
neg => ELECTRICAL_REF
);
v2 : entity work.v_constant(ideal)
generic map(
level => 0.327
)
port map(
pos => vctrl_init,
neg => ELECTRICAL_REF
);
v3 : entity work.v_constant(ideal)
generic map(
level => 4.8
)
port map(
pos => XSIG010004,
neg => ELECTRICAL_REF
);
end ex_buck;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CS5_Rudder_Power is
end tb_CS5_Rudder_Power ;
architecture TB_CS5_Rudder_Power of tb_CS5_Rudder_Power is
-- Component declarations
-- Signal declarations
terminal buck_out : electrical;
terminal gear_out : rotational;
terminal link_in : translational;
terminal link_out : translational;
terminal mot_ccw : electrical;
terminal mot_cw : electrical;
terminal mot_out : rotational_v;
terminal pos_fb_v : electrical;
terminal pwm_in : electrical;
terminal rudder : rotational;
terminal src_in : electrical;
begin
-- Signal assignments
-- Component instances
rudder_servo1 : entity work.rudder_servo
port map(
servo_out => pwm_in,
servo_in => src_in,
pos_fb => pos_fb_v
);
gear3 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => mot_out,
rot2 => gear_out
);
r2v : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => pos_fb_v,
input => gear_out
);
r2t : entity work.horn_r2t(bhv)
port map(
theta => gear_out,
pos => link_in
);
t2r : entity work.horn_t2r(bhv)
port map(
theta => rudder,
pos => link_out
);
motor1 : entity work.DC_Motor(basic)
generic map(
r_wind => 2.2,
kt => 3.43e-3,
l => 2.03e-3,
d => 5.63e-6,
j => 168.0e-9
)
port map(
p1 => mot_cw,
p2 => mot_ccw,
shaft_rotv => mot_out
);
stop1 : entity work.stop_r(ideal)
generic map(
damp_stop => 1.0e2,
k_stop => 1.0e6,
ang_max => 1.05,
ang_min => -1.05
)
port map(
ang1 => gear_out,
ang2 => ROTATIONAL_REF
);
\linkage\ : entity work.tran_linkage(a1)
port map(
p2 => link_out,
p1 => link_in
);
rudder_1 : entity work.rudder(bhv)
generic map(
k => 0.02
)
port map(
rot => rudder
);
pwm_H_bridge1 : entity work.pwm_H_bridge
port map(
src_in => pwm_in,
mot_cw => mot_cw,
pwr_in => buck_out,
mot_ccw => mot_ccw
);
XCMP65 : entity work.stick(ideal)
generic map(
freq => 1.0,
amplitude => 4.7,
phase => 0.0,
offset => 0.0
)
port map(
v_out => src_in
);
ex_buck4 : entity work.ex_buck
port map(
pwr_out => buck_out
);
end TB_CS5_Rudder_Power;
--
|
gpl-2.0
|
85febe36a843debce2e614adf969f6ee
| 0.570328 | 4.372592 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1874.vhd
| 4 | 2,100 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1874.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01874ent IS
END c07s01b00x00p08n01i01874ent;
ARCHITECTURE c07s01b00x00p08n01i01874arch OF c07s01b00x00p08n01i01874ent IS
type small_int is range 0 to 7;
signal s_int : small_int;
signal bool : boolean;
BEGIN
sig : bool <= true after 5 ns;
b : block (s_int = 0)
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 => tmp := 0;
when others => tmp := 1;
end case;
return sig; -- signal assignment labels illegal here
end value;
begin
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01874 - Signal assignment labels are not permitted as primaries in a function return expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01874arch;
|
gpl-2.0
|
f2ec28af291679f952c4b31dd36dabd6
| 0.645714 | 3.818182 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/ticket89/x_ieee_proposed/src/standard_textio_additions_c.vhdl
| 3 | 16,873 |
------------------------------------------------------------------------------
-- "standard_textio_additions" package contains the additions to the built in
-- "standard.textio" package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee_proposed.standard_textio_additions.all;
-- Last Modified: $Date: 2007/03/13 18:25:58 $
-- RCS ID: $Id: standard_textio_additions_c.vhdl,v 1.5 2007/03/13 18:25:58 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
use std.textio.all;
package standard_textio_additions is
-- procedure DEALLOCATE (P : inout LINE);
-- procedure FLUSH (file F : TEXT);
--
-- function MINIMUM (L, R : SIDE) return SIDE;
-- function MAXIMUM (L, R : SIDE) return SIDE;
--
-- function TO_STRING (VALUE : SIDE) return STRING;
--
-- function JUSTIFY (VALUE : STRING; JUSTIFIED : SIDE := right; FIELD : WIDTH := 0) return STRING;
--
-- procedure SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL);
-- alias STRING_READ is SREAD [LINE, STRING, NATURAL];
-- alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
-- alias BREAD is READ [LINE, BIT_VECTOR];
-- alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
-- alias BINARY_READ is READ [LINE, BIT_VECTOR];
-- procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
-- procedure OREAD (L : inout LINE; VALUE : out BIT_VECTOR);
-- alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
-- alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
-- procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR; GOOD : out BOOLEAN);
-- procedure HREAD (L : inout LINE; VALUE : out BIT_VECTOR);
-- alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
-- alias HEX_READ is HREAD [LINE, BIT_VECTOR];
-- procedure TEE (file F : TEXT; L : inout LINE);
-- procedure WRITE (L : inout LINE; VALUE : in REAL;
-- FORMAT : in STRING);
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
end package standard_textio_additions;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body standard_textio_additions is
--pragma synthesis_off
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- Writes L to a file without modifying the contents of the line
procedure TEE (file F : TEXT; L : inout LINE) is
begin
write (OUTPUT, L.all & LF);
writeline(F, L);
end procedure TEE;
procedure FLUSH (file F: TEXT) is -- Implicit
begin
file_close (F);
end procedure FLUSH;
-- Read and Write procedure for strings
procedure SREAD (L : inout LINE;
VALUE : out STRING;
STRLEN : out natural) is
variable ok : BOOLEAN;
variable c : CHARACTER;
-- Result is padded with space characters
variable result : STRING (1 to VALUE'length) := (others => ' ');
begin
VALUE := result;
loop -- skip white space
read(L, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
STRLEN := 0;
return;
end if;
result (1) := c;
STRLEN := 1;
for i in 2 to VALUE'length loop
read(L, c, ok);
if (ok = false) or ((c = ' ') or (c = NBSP) or (c = HT)) then
exit;
else
result (i) := c;
end if;
STRLEN := i;
end loop;
VALUE := result;
end procedure SREAD;
-- Hex Read and Write procedures for bit_vector.
-- Procedure only visible internally.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out BIT_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when others =>
assert not ISSUE_ERROR report
"TEXTIO.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)." severity error;
GOOD := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR (0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*4 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.HREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.HREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.HREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
-- Procedure only visible internally.
procedure Char2TriBits (C : CHARACTER;
RESULT : out BIT_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when others =>
assert not ISSUE_ERROR
report
"TEXTIO.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
GOOD := false;
end case;
end procedure Char2TriBits;
-- Read and Write procedures for Octal values
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, false);
if not ok then
GOOD := false;
return;
end if;
read(L, s, ok);
if not ok then
GOOD := false;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, false);
if not ok then
GOOD := false;
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE;
VALUE : out BIT_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : BIT_VECTOR(0 to ne*3 - 1) := (others => '0');
variable s : STRING(1 to ne-1);
begin
VALUE := (VALUE'range => '0');
loop -- skip white space
read(l, c, ok);
exit when (ok = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
report "TEXTIO.OREAD Error: Failed skipping white space"
severity error;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, true);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
report "TEXTIO.OREAD Error: Failed to read the STRING"
severity error;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then
report "TEXTIO.OREAD Error: Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE;
VALUE : in BIT_VECTOR;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
write (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
-- read and write for vector versions
-- These versions produce "value1, value2, value3 ...."
procedure read (L : inout LINE;
VALUE : out boolean_vector;
GOOD : out BOOLEAN) is
variable dummy : CHARACTER;
variable igood : BOOLEAN := true;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
GOOD => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
good := false;
return;
end if;
end loop;
good := true;
end procedure read;
procedure read (L : inout LINE;
VALUE : out boolean_vector) is
variable dummy : CHARACTER;
variable igood : BOOLEAN;
begin
for i in VALUE'range loop
read (L => L,
VALUE => VALUE(i),
good => igood);
if (igood) and (i /= value'right) then
read (L => L,
VALUE => dummy, -- Toss the comma or seperator
good => igood);
end if;
if (not igood) then
report "STANDARD.STD_TEXTIO(BOOLEAN_VECTOR) "
& "Read error ecounted during vector read" severity error;
return;
end if;
end loop;
end procedure read;
procedure write (L : inout LINE;
VALUE : in boolean_vector;
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin
for i in VALUE'range loop
write (L => L,
VALUE => VALUE(i),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
if (i /= value'right) then
swrite (L, ", ");
end if;
end loop;
end procedure write;
procedure WRITE (L: inout LINE; VALUE: in REAL;
FORMAT: in STRING) is
begin
--ET: Below modification is required to avoid the following error in iSim
-- "FATAL_ERROR:Simulator:CompilerAssert.h:40:1.67 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 7524 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support."
-- swrite ( L => L, VALUE => to_string (VALUE, FORMAT));
swrite ( L, to_string (VALUE, FORMAT));
end procedure WRITE;
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_string (
VALUE : SIDE) return STRING is
begin
return SIDE'image(VALUE);
end function to_string;
-- pragma synthesis_on
-- Will be implicit
function minimum (L, R : SIDE) return SIDE is
begin
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : SIDE) return SIDE is
begin
if L > R then return L;
else return R;
end if;
end function maximum;
end package body standard_textio_additions;
|
gpl-2.0
|
210ca5c34dfdbcc6e60b378466338f67
| 0.511409 | 3.87173 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Guerric/Modular/celda_r.vhd
| 1 | 1,729 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_r is
generic(
NUM_BITS : positive := 163
);
port(
R_div_2 : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
P_div_2 : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
S_div_2 : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
c_3 : in STD_LOGIC;
c_0 : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
R : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_r is
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
Celda_r_process: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
R <= (others => '0');
else
if c_3 = '1' and C_0 = '1' then
R <= R_div_2 xor P_div_2 xor S_div_2;
elsif c_3 = '1' and C_0 = '0' then
R <= R_div_2 xor P_div_2;
elsif c_3 = '0' and C_0 = '1' then
R <= R_div_2 xor S_div_2;
else
R <= R_div_2;
end if;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
1626684f3c630d0d5644c2d00128b3b9
| 0.352227 | 3.825221 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd
| 4 | 1,240 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity SR_flipflop is
port ( s_n, r_n : in bit; q, q_n : inout bit );
begin
postponed process (q, q_n) is
begin
assert now = 0 fs or q = not q_n
report "implementation error: q /= not q_n";
end postponed process;
end entity SR_flipflop;
--------------------------------------------------
architecture dataflow of SR_flipflop is
begin
gate_1 : q <= s_n nand q_n;
gate_2 : q_n <= r_n nand q;
end architecture dataflow;
|
gpl-2.0
|
e94f2592195d2c901c0295ddb35dc37d
| 0.679839 | 3.862928 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc688.vhd
| 4 | 3,124 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc688.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:35 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:42 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00688ent IS
END c03s04b01x00p23n01i00688ent;
ARCHITECTURE c03s04b01x00p23n01i00688arch OF c03s04b01x00p23n01i00688ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of TIME;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.52";
-- Declare a variable into which we will read.
constant CON : TIME := 1 ns;
variable VAR : TIME;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00688"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00688 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00688arch;
|
gpl-2.0
|
f5b62381ada6a48d597f3862baedad72
| 0.543854 | 3.984694 | false | true | false | false |
stnolting/neo430
|
sim/neo430_tb.vhd
| 1 | 12,139 |
-- #################################################################################################
-- # << NEO430 - Simple testbench >> #
-- # ********************************************************************************************* #
-- # This simple testbench instantiates the top entity of the NEO430 processors, generates clock #
-- # and reset signals and outputs data send via the processor's UART to the simulator console. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library neo430;
use neo430.neo430_package.all;
use std.textio.all;
entity neo430_tb is
end neo430_tb;
architecture neo430_tb_rtl of neo430_tb is
-- User Configuration ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant t_clock_c : time := 10 ns; -- main clock period
constant f_clock_c : real := 100000000.0; -- main clock in Hz
constant baud_rate_c : real := 19200.0; -- standard UART baudrate
-- -------------------------------------------------------------------------------------------
-- textio --
file file_uart_tx_out : text open write_mode is "neo430.uart_tx.txt";
-- internal configuration --
constant baud_val_c : real := f_clock_c / baud_rate_c;
constant f_clk_c : natural := natural(f_clock_c);
-- reduced ASCII table --
type ascii_t is array (0 to 94) of character;
constant ascii_lut : ascii_t := (' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-',
'.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', 'A',
'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U',
'V', 'W', 'X', 'Y', 'Z', '[', '\', ']', '^', '_', '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '{', '|', '}', '~');
-- generators --
signal clk_gen, rst_gen : std_ulogic := '0';
signal irq, irq_ack : std_ulogic_vector(7 downto 0);
-- local signals --
signal uart_txd : std_ulogic;
signal spi_data : std_ulogic;
-- simulation uart receiver --
signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
signal uart_rx_busy : std_ulogic := '0';
signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
signal uart_rx_baud_cnt : real;
signal uart_rx_bitcnt : natural;
-- twi --
signal twi_sda : std_logic;
signal twi_scl : std_logic;
begin
-- Clock/Reset Generator ----------------------------------------------------
-- -----------------------------------------------------------------------------
clk_gen <= not clk_gen after (t_clock_c/2);
rst_gen <= '0', '1' after 60*(t_clock_c/2);
-- CPU Core -----------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_top_inst: neo430_top
generic map (
-- general configuration --
CLOCK_SPEED => f_clk_c, -- main clock in Hz
IMEM_SIZE => 4*1024, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => 2*1024, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => x"4788", -- custom user code
-- module configuration --
MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
WB32_USE => true, -- implement WB32 unit? (default=true)
WDT_USE => true, -- implement WBT? (default=true)
GPIO_USE => true, -- implement GPIO unit? (default=true)
TIMER_USE => true, -- implement timer? (default=true)
UART_USE => true, -- implement UART? (default=true)
CRC_USE => true, -- implement CRC unit? (default=true)
CFU_USE => false, -- implement custom functions unit? (default=false)
PWM_USE => true, -- implement PWM controller? (default=true)
TWI_USE => true, -- implement two wire serial interface? (default=true)
SPI_USE => true, -- implement SPI? (default=true)
TRNG_USE => false, -- implement TRNG? (default=false) - CANNOT BE SIMULATED!
EXIRQ_USE => true, -- implement EXIRQ? (default=true)
FREQ_GEN_USE => true, -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE => false, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => clk_gen, -- global clock, rising edge
rst_i => rst_gen, -- global reset, async, low-active
-- gpio --
gpio_o => open, -- parallel output
gpio_i => x"0000", -- parallel input
-- pwm channels --
pwm_o => open, -- pwm channels
-- arbitrary frequency generator --
freq_gen_o => open, -- programmable frequency output
-- serial com --
uart_txd_o => uart_txd, -- UART send data
uart_rxd_i => uart_txd, -- UART receive data
spi_sclk_o => open, -- serial clock line
spi_mosi_o => spi_data, -- serial data line out
spi_miso_i => spi_data, -- serial data line in
spi_cs_o => open, -- SPI CS 0..5
twi_sda_io => twi_sda, -- twi serial data line
twi_scl_io => twi_scl, -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o => open, -- address
wb_dat_i => x"00000000", -- read data
wb_dat_o => open, -- write data
wb_we_o => open, -- read/write
wb_sel_o => open, -- byte enable
wb_stb_o => open, -- strobe
wb_cyc_o => open, -- valid cycle
wb_ack_i => '0', -- transfer acknowledge
-- external interrupts --
ext_irq_i => irq, -- external interrupt request lines
ext_ack_o => irq_ack -- external interrupt request acknowledges
);
-- twi pull-ups --
twi_sda <= 'H';
twi_scl <= 'H';
-- Interrupt Generator ------------------------------------------------------
-- -----------------------------------------------------------------------------
interrupt_gen: process
begin
irq <= (others => '0');
wait for 20 ms;
wait until rising_edge(clk_gen);
irq <= "00000111";
wait for t_clock_c;
wait;
end process interrupt_gen;
-- Console UART Receiver ----------------------------------------------------
-- -----------------------------------------------------------------------------
uart_rx_unit: process(clk_gen)
variable i, j : integer;
variable line_tmp : line;
begin
-- "UART" --
if rising_edge(clk_gen) then
-- synchronizer --
uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
-- arbiter --
if (uart_rx_busy = '0') then -- idle
uart_rx_busy <= '0';
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
uart_rx_bitcnt <= 9;
if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
uart_rx_busy <= '1';
end if;
else
if (uart_rx_baud_cnt = 0.0) then
-- adapt to the inter-frame pause - which is not implemented in the neo430 uart ;)
if (uart_rx_bitcnt = 1) then
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
else
uart_rx_baud_cnt <= round(baud_val_c);
end if;
if (uart_rx_bitcnt = 0) then
uart_rx_busy <= '0'; -- done
i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
j := i - 32;
if (j < 0) or (j > 95) then
j := 0; -- undefined = SPACE
end if;
if (i < 32) or (j > 32+95) then
report "UART TX: (" & integer'image(i) & ")"; -- print code
else
report "UART TX: " & ascii_lut(j); -- print ASCII
end if;
if (i = 10) then -- Linux line break
writeline(file_uart_tx_out, line_tmp);
elsif (i /= 13) then -- Remove additional carriage return
write(line_tmp, ascii_lut(j));
end if;
else
uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
uart_rx_bitcnt <= uart_rx_bitcnt - 1;
end if;
else
uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
end if;
end if;
end if;
end process uart_rx_unit;
end neo430_tb_rtl;
|
bsd-3-clause
|
c14eda1a608e2b52e521509650be6fef
| 0.439081 | 4.377569 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd
| 4 | 2,927 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
package stimulus_generators is
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length );
procedure all_possible_values ( signal bv : out std_ulogic_vector;
delay_between_values : in delay_length );
procedure all_possible_values ( signal bv : out std_logic_vector;
delay_between_values : in delay_length );
end package stimulus_generators;
package body stimulus_generators is
type digit_table is array ( natural range 0 to 1 ) of bit;
constant digit : digit_table := ( '0', '1' );
function natural_to_bv ( nat : in natural;
length : in natural ) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(0 to length - 1);
begin
for index in result'reverse_range loop
result(index) := digit( temp rem 2 );
temp := temp / 2;
end loop;
return result;
end function natural_to_bv;
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length ) is
begin
bv <= natural_to_bv(0, bv'length);
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= natural_to_bv(value, bv'length);
end loop;
end procedure all_possible_values;
procedure all_possible_values ( signal bv : out std_ulogic_vector;
delay_between_values : in delay_length ) is
begin
bv <= To_StdULogicVector(natural_to_bv(0, bv'length));
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= To_StdULogicVector(natural_to_bv(value, bv'length));
end loop;
end procedure all_possible_values;
procedure all_possible_values ( signal bv : out std_logic_vector;
delay_between_values : in delay_length ) is
begin
bv <= To_StdLogicVector(natural_to_bv(0, bv'length));
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= To_StdLogicVector(natural_to_bv(value, bv'length));
end loop;
end procedure all_possible_values;
end package body stimulus_generators;
|
gpl-2.0
|
c2df4e1485b8f0d99390a67a1636e4ae
| 0.689101 | 3.841207 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_04.vhd
| 4 | 3,446 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_04.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity DRAM is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end entity DRAM;
architecture empty of DRAM is
begin
d <= (others => 'Z');
end architecture empty;
library ieee; use ieee.std_logic_1164.all;
entity memory_board is
end entity memory_board;
-- end not in book
architecture chip_level of memory_board is
component DRAM is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end component DRAM;
signal buffered_address : std_logic_vector(0 to 10);
signal DRAM_data : std_logic_vector(0 to 31);
signal bank_select : std_logic_vector(0 to 3);
signal buffered_we, buffered_ras, buffered_cas : std_logic;
-- . . . -- other declarations
begin
bank_array : for bank_index in 0 to 3 generate
begin
nibble_array : for nibble_index in 0 to 7 generate
constant data_lo : natural := nibble_index * 4;
constant data_hi : natural := nibble_index * 4 + 3;
begin
a_DRAM : component DRAM
port map ( a => buffered_address,
d => DRAM_data(data_lo to data_hi),
cs => bank_select(bank_index),
we => buffered_we,
ras => buffered_ras,
cas => buffered_cas );
end generate nibble_array;
end generate bank_array;
-- . . . -- other component instances, etc
-- not in book
buffered_address <= "01010101010";
DRAM_data <= X"01234567";
-- end not in book
end architecture chip_level;
|
gpl-2.0
|
387411365d4123454a44354db67de91a
| 0.482298 | 4.894886 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.f-Mul.core/a.b.f.0-BoothGenerator.vhd
| 1 | 1,329 |
--------------------------------------------------------------------------------
-- FILE: BoothGenerator
-- DESC: Generator of Booth's Multiplier
--
-- Author:
-- Create: 2015-08-14
-- Update: 2015-08-14
-- Status: TESED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity BoothGenerator is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE/2;
STAGE : integer := C_MUL_STAGE
);
port(
a: in std_logic_vector(DATA_SIZE*2-1 downto 0);
ya, y2a: out std_logic_vector(DATA_SIZE*2-1 downto 0)
);
end BoothGenerator;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture booth_generator_arch of BoothGenerator is
begin
-- a
ya(DATA_SIZE*2-1 downto STAGE*2) <= a(DATA_SIZE*2-STAGE*2-1 downto 0);
ya(STAGE*2-1 downto 0) <= (others=>'0');
-- 2a
y2a(DATA_SIZE*2-1 downto STAGE*2+1) <= a(DATA_SIZE*2-STAGE*2-2 downto 0);
y2a(STAGE*2 downto 0) <= (others=>'0');
end booth_generator_arch;
|
mit
|
90100edbf74c09a8e8f41b32f2a65b29
| 0.431904 | 3.955357 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/MAIA/inverter_maia.vhd
| 1 | 9,692 |
----------------------------------------------------------------------------------------------------
-- inverter_maia_2.vhd ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the Modified Almost Inverse Algorithm.
-- Diferent to the first implementation, here the test g(U) < g(V) is
-- performed directly by a m+1 bit comparer.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
--------------------------------------------------------
entity inverter_maia is
generic(
NUM_BITS : positive := 163 -- The order of the finite field
);
port(
ax : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- input polynomial of grade m-1
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
z : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end inverter_maia;
---------------------------------------------------------
architecture behave of inverter_maia is
---------------------------------------------------------
signal B,C,U,V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal processing registers, one bit more
signal Bx_Op1 : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Multiplexer which depends on if B is ever or odd
signal Ux_div_x : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- U and B divided by x
signal Bx_div_x : STD_LOGIC_VECTOR(NUM_BITS downto 0);
--163
constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--233
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--277
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--283
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--409
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--571
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--
-- m = 163 x163 + x7 + x6 + x3 + 1
constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F_x: std_logic_vector(NUM_BITS1 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------
-- States fot the FSM controlling the execution of the algorithm
----------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, LOOP_U0, NEXT_STEP);
signal State: CurrentState_type;
----------------------------------------------------------------------------------
begin
------------------------------------------------------
Ux_div_x <= '0' & U(NUM_BITS downto 1); -- Dividing U and B by x
Bx_div_x <= '0' & Bx_Op1(NUM_BITS downto 1);
------------------------------------------------------
Bx_Op1 <= B xor Fx when B(0) = '1' else -- Multiplexer for operand B
B;
-------------------------------------------------------
-- The Modified ALmost Inverse Algorithm implementation
-------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then -- initialize internal registers
State <= LOOP_U0;
B <= UNO;
U <= '0'&Ax;
V <= Fx;
C <= (others => '0');
z <= (others => '0'); -- set to zero the output register
Done <= '0';
else
case State is
-----------------------------------------------------------------------------------
when LOOP_U0 => -- Stay here while U be even
if U(0) = '1' then
if U = UNO then -- The algorithm finishes when U = 1
Z <= B(NUM_BITS-1 downto 0);
Done <= '1';
State <= END_STATE;
else
if U < V then -- Interchange the registers U <-> V and B <-> C
U <= V;
V <= U;
B <= C;
C <= B;
end if;
State <= NEXT_STEP;
end if;
else -- Divide U and B and repeat the process
U <= Ux_div_x;
B <= Bx_div_x;
end if;
-----------------------------------------------------------------------------------
when NEXT_STEP => -- update U and B with the values previously assigned
U <= U xor V;
B <= B xor C;
State <= LOOP_U0;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
State <= END_STATE;
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
01f547b0eba531d25f9deec8c9fc19e2
| 0.640838 | 6.688751 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.c-tbInstructionRam.vhd
| 1 | 1,137 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
entity tbInstructionRam is
end tbInstructionRam;
architecture tb_instruction_ram_arch of tbInstructionRam is
constant ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
constant ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
component InstructionRam
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE
);
port (
rst : in std_logic;
addr : in std_logic_vector(ADDR_SIZE-1 downto 0);
iout : out std_logic_vector(ISTR_SIZE-1 downto 0)
);
end component;
signal rst : std_logic;
signal addr : std_logic_vector(ADDR_SIZE-1 downto 0);
signal iout : std_logic_vector(ISTR_SIZE-1 downto 0);
begin
IRAM: InstructionRam
port map(rst, addr, iout);
rst <= '0', '1' after 1 ns;
addr <= x"00000000", x"00000001" after 2 ns, x"00000002" after 3 ns, x"00000003" after 4 ns, x"00000004" after 5 ns;
end tb_instruction_ram_arch;
configuration tb_instruction_ram_cfg of tbInstructionRam is
for tb_instruction_ram_arch
end for;
end tb_instruction_ram_cfg;
|
mit
|
793aadf8685e878a77a0c5eea5534154
| 0.710642 | 2.915385 | false | false | false | false |
tristanseifert/68komputer
|
VideoSyncGenerator.vhd
| 1 | 2,582 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- This is responsible for outputting the proper video sync signals for VGA at
-- 640x480 with a 60 Hz refresh rate.
--
-- The actual video dimensions are 800x525:
-- HORIZONTAL:
-- 640 clocks: Displayable (000)
-- 016 clocks: Front porch (640)
-- 096 clocks: Sync pulse (656)
-- 048 clocks: Back porch (752)
--
-- VERTICAL:
-- 480 lines: Displayable (000)
-- 010 lines: Front porch (480)
-- 002 lines: Sync pulse (490)
-- 033 lines: Back porch (492)
--
-- In our case, the sync pulse will pulse the proper sync signal low: it is
-- usually high during displayed frames.
entity VideoSyncGenerator is
PORT(
reset: IN std_logic;
PixelClock: IN std_logic;
HSync: OUT std_logic;
VSync: OUT std_logic;
VideoOn: OUT std_logic; -- indicates whether colourshall be outputted
CurCol: OUT std_logic_vector(9 downto 0);
CurRow: OUT std_logic_vector(9 downto 0)
);
end VideoSyncGenerator;
architecture behavioral of VideoSyncGenerator is
signal vcount: std_logic_vector(9 downto 0); -- count scanlines
signal hcount: std_logic_vector(9 downto 0); -- count pixels
signal hblank, vblank: std_logic;
begin
-- Horizontal line counter
hcounter: process(PixelClock, reset)
begin
-- if reset is asserted
if reset = '1'
then hcount <= (others => '0');
elsif rising_edge(PixelClock)
then
if hcount=799
then hcount <= (others => '0');
else hcount <= hcount + 1;
end if;
end if;
end process;
-- HSync generator
process(hcount)
begin
hblank <= '1';
CurCol <= hcount;
if hcount>=640
then
hblank <= '0';
CurCol <= (others => '0');
end if;
if (hcount<=755 and hcount>=659)
then HSync <= '0';
else HSync <= '1';
end if;
end process;
-- Vertical line counter
vcounter: process(PixelClock, reset)
begin
if reset = '1'
then vcount <= (others => '0');
elsif rising_edge(PixelClock)
then
if hcount=799
then
if vcount=524
then vcount <= (others => '0');
else vcount <= vcount + 1;
end if;
end if;
end if;
end process;
-- VSync generator
process(vcount)
begin
vblank <= '1';
CurRow <= vcount;
if vcount>=480
then
vblank <= '0';
CurRow <= (others => '0');
end if;
if (vcount<=494 and vcount>=493)
then VSync <= '0';
else VSync <= '1';
end if;
end process;
VideoOn <= VBlank and HBlank;
end behavioral;
|
bsd-2-clause
|
e8f033770c11c6dcc5bbbf74c1f281a5
| 0.62897 | 3.030516 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_10.vhd
| 4 | 2,678 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity computer_system is
end entity computer_system;
-- code from book
architecture abstract of computer_system is
-- not in book
subtype word is bit_vector(31 downto 0);
type word_vector is array (natural range <>) of word;
function resolve_word ( drivers : word_vector ) return word is
begin
if drivers'length > 0 then
return drivers(drivers'left);
else
return X"00000000";
end if;
end function resolve_word;
-- end not in book
-- . . .
signal address_bus : resolve_word word bus;
signal hold_req : bit;
-- . . .
-- not in book
signal clk : bit := '0';
-- end not in book
begin
cpu : block is
signal guard : boolean := false;
signal cpu_internal_address : word;
-- . . .
begin
cpu_address_driver:
address_bus <= guarded cpu_internal_address;
-- . . . -- other bus drivers
controller : process is
-- . . .
begin
-- . . .
-- . . . -- determine when to disable cpu bus drivers
guard <= false;
wait on clk until hold_req = '0' and clk = '1';
guard <= true; -- re-enable cpu bus drivers
-- . . .
-- not in book
wait until clk = '1';
-- end not in book
end process controller;
-- . . . -- cpu datapath processes
-- not in book
cpu_internal_address <= X"11111111";
-- end not in book
end block cpu;
-- . . . -- blocks for DMA and other modules
-- not in book
clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
-- end not in book
end architecture abstract;
-- end code from book
|
gpl-2.0
|
fee0a4c02471311f01a64fb9bdc06436
| 0.585138 | 4.051437 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc492.vhd
| 4 | 5,711 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc492.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p01n01i00492ent IS
END c03s02b02x00p01n01i00492ent;
ARCHITECTURE c03s02b02x00p01n01i00492arch OF c03s02b02x00p01n01i00492ent IS
type etype is (one,two,three,four,five,six,seven);
type TR is record
i : integer;
b : bit;
bo : boolean;
bv : bit_vector (0 to 3);
r : real;
t : time;
e : etype;
c : character;
end record;
type T1 is record
t : time;
b : bit;
i : integer;
bo : boolean;
r : real;
bv : bit_vector (0 to 3);
e : etype;
c : character;
end record;
function FUNC1(signal recd1: TR) return T1 is
variable recd2:T1;
begin
recd2.bv := recd1.bv;
recd2.b := recd1.b;
recd2.bo := recd1.bo;
recd2.i := recd1.i;
recd2.r := recd1.r;
recd2.t := recd1.t;
recd2.e := recd1.e;
recd2.c := recd1.c;
return recd2;
end FUNC1;
function FUNC2(signal recd1: TR) return integer is
begin
return recd1.i;
end;
function FUNC3(signal recd1: TR) return bit is
begin
return recd1.b;
end;
function FUNC4(signal recd1: TR) return boolean is
begin
return recd1.bo;
end;
function FUNC5(signal recd1: TR) return bit_vector is
begin
return recd1.bv;
end;
function FUNC6(signal recd1: TR) return real is
begin
return recd1.r;
end;
function FUNC7(signal recd1: TR) return time is
begin
return recd1.t;
end;
function FUNC8(signal recd1: TR) return etype is
begin
return recd1.e;
end;
function FUNC9(signal recd1: TR) return character is
begin
return recd1.c;
end;
signal var1: TR;
signal var2: T1;
BEGIN
TESTING: PROCESS
variable OkayCount : integer := 0;
BEGIN
wait for 1 ns;
var2 <= (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
var1 <= (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%');
wait for 1 ns;
var2 <= FUNC1(var1);
wait for 1 ns;
assert var2.bv = "0001" report "var2.bv /= 0001" severity note;
assert var2.b = '1' report "var2.b /= 1" severity note;
assert var2.bo = true report "var2.bo /= true" severity note;
assert var2.i = 777 report "var2.i /= 777" severity note;
assert var2.r = 333.767 report "var2.r /= 333.767" severity note;
assert var2.t = 44 ms report "var2.t /= 44 ms" severity note;
assert var2.e = seven report "var2.e /= seven" severity note;
assert var2.c = '%' report "var2.c /= c" severity note;
if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
OkayCount := OkayCount + 1;
else
assert false report "bad return on FUNC1" severity note;
end if;
var2 <= (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
wait for 1 ns;
if var2 = (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a') then
OkayCount := OkayCount + 1;
end if;
var2.i <= FUNC2(var1);
var2.b <= FUNC3(var1);
var2.bo <= FUNC4(var1);
var2.bv <= FUNC5(var1);
var2.r <= FUNC6(var1);
var2.t <= FUNC7(var1);
var2.e <= FUNC8(var1);
var2.c <= FUNC9(var1);
wait for 1 ns;
assert var2.bv = "0001" report "var2.bv /= 0001" severity note;
assert var2.b = '1' report "var2.b /= 1" severity note;
assert var2.bo = true report "var2.bo /= true" severity note;
assert var2.i = 777 report "var2.i /= 777" severity note;
assert var2.r = 333.767 report "var2.r /= 333.767" severity note;
assert var2.t = 44 ms report "var2.t /= 44 ms" severity note;
assert var2.e = seven report "var2.e /= seven" severity note;
assert var2.c = '%' report "var2.c /= c" severity note;
if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
OkayCount := OkayCount + 1;
else
assert false report "bad return on FUNC2-8" severity note;
end if;
wait for 1 ns;
assert NOT( OkayCount = 3 )
report "***PASSED TEST: c03s02b02x00p01n01i00492"
severity NOTE;
assert ( OkayCount = 3 )
report "***FAILED TEST: c03s02b02x00p01n01i00492 - Problem assigning record subelements in function."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p01n01i00492arch;
|
gpl-2.0
|
59d35be53ad82a7a2c4921288208f410
| 0.581509 | 3.204826 | false | false | false | false |
nczempin/NICNAC16
|
ipcore_dir/ROM01/example_design/ROM01_exdes.vhd
| 1 | 4,429 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM01_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ROM01_exdes IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END ROM01_exdes;
ARCHITECTURE xilinx OF ROM01_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT ROM01 IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : ROM01
PORT MAP (
--Port A
ENA => ENA,
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
mit
|
eed784f6ae228179490631317e2d0aa5
| 0.569429 | 4.767492 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket89/project/tb/partial_test_tb.vhd
| 3 | 6,340 |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : partial_test_tb
--
-- Description : Parts of the testbench used for testing the Bitvis Utility Library
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use std.textio.all;
library work;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.bfm_common_pkg.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all; -- Used for to_string(real)
use ieee_proposed.std_logic_1164_additions.all; -- Used for to_string(std_logic)
entity partial_test_tb is
end entity;
architecture func of partial_test_tb is
signal sl : std_logic := '0';
signal clk100M : std_logic;
signal clk100M_ena : boolean := true;
signal clk200M : std_logic;
signal clk200M_ena : boolean := true;
signal clk50M : std_logic;
constant C_CLK100M_PERIOD : time := 10 ns;
begin
------------------------------------------------
-- Process: clock generator
------------------------------------------------
-- Overloaded version with enable signal as argument
clock_generator(clk100M, clk100M_ena, C_CLK100M_PERIOD, "Clk100M");
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
constant C_SCOPE : string := "TB seq";
-- Log overloads for simplification
procedure log(
msg : string) is
begin
log(ID_SEQUENCER, msg, C_SCOPE);
end;
begin
set_alert_file_name("alertlog.txt");
set_log_file_name("testlog.txt");
set_alert_stop_limit(WARNING, 0);
set_alert_stop_limit(ERROR, 0); -- 0 = Never stop
wait for 1 ns;
-- ####################### BLOCK 1 - Causes "internal error: delayed" ##########################
-- FROM_NOW, FROM_NOW
await_stable(sl, 50 ns, FROM_NOW, 100 ns, FROM_NOW, ERROR, "sl: Stable FROM_NOW, FROM_NOW, OK after 50 ns", C_SCOPE);
sl <= transport not sl after 30 ns;
await_stable(sl, 50 ns, FROM_NOW, 100 ns, FROM_NOW, ERROR, "sl: Stable FROM_NOW, FROM_NOW, OK after 80 ns", C_SCOPE);
sl <= transport not sl after 30 ns;
await_stable(sl, 50 ns, FROM_NOW, 60 ns, FROM_NOW, ERROR, "sl: Not stable FROM_NOW, FROM_NOW, Fail after 30 ns", C_SCOPE);
increment_expected_alerts(ERROR, 1);
await_stable(sl, 50 ns, FROM_NOW, 1 ns, FROM_NOW, ERROR, "sl: Timeout before stable_req, FROM_NOW, FROM_NOW, Fail immediately", C_SCOPE);
increment_expected_alerts(ERROR, 1);
await_stable(sl, 0 ns, FROM_NOW, 0 ns, FROM_NOW, ERROR, "sl: stable for 0 ns, FROM_NOW, FROM_NOW, OK after 0 ns", C_SCOPE);
-- FROM_LAST_EVENT, FROM_NOW
sl <= not sl;
log("NOTE: ERROR HAPPENS AFTER HERE");
wait for 10 ns;
log("NOTE: ERROR HAPPENS BEFORE HERE");
-- ####################### END OF BLOCK 1 ##########################
-- ####################### BLOCK 2 - Code works if this is removed ##########################
-- Pulse a certain number of clock periods
clk100M_ena <= true; -- Clock must be running
sl <= '0';
wait for 0 ns; -- Wait for signal to update
gen_pulse(sl, clk100M, 10, "Test pulse 10 clk periods");
check_value(sl'delayed(0 ns)'last_event, 10*C_CLK100M_PERIOD, ERROR, "Check start of pulse");
wait for 0 ns; -- Wait for signal to be updated
check_value(sl, '0', ERROR, "pulse for 10 clk periods, pulse done", C_SCOPE);
check_value(sl'last_event, 0 ns, ERROR, "pulse for 10 clk periods. Check that it actually pulsed for a delta cycle", C_SCOPE);
check_value(sl'last_value, '1', ERROR, "pulse for 10 clk periods, check that it actually pulsed for a delta cycle", C_SCOPE);
wait for 100 ns;
-- ####################### END OF BLOCK 2 ##########################
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(INTERMEDIATE);
report_alert_counters(FINAL);
log(ID_LOG_HDR,"SIMULATION COMPLETED", C_SCOPE);
assert false
report "End of simulation. (***Ignore this failure. Was provoked to stop the simulation.)"
severity failure;
wait; -- to stop completely
end process p_main;
end func;
|
gpl-2.0
|
e6c8abbc4f8c19d6b8952a75e35f1ed7
| 0.551735 | 4.243641 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc749.vhd
| 4 | 23,150 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc749.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00749ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00749ent;
ARCHITECTURE c01s01b01x01p05n02i00749arch OF c01s01b01x01p05n02i00749ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st := (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a :record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new := (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records:= (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record := (C85,C86,C88);
signal V1 : boolean_vector(zero to fifteen) ;
signal V2 : severity_level_vector(zero to fifteen);
signal V3 : integer_vector(zero to fifteen) ;
signal V4 : real_vector(zero to fifteen) ;
signal V5 : time_vector (zero to fifteen);
signal V6 : natural_vector(zero to fifteen);
signal V7 : positive_vector(zero to fifteen);
signal V8 : boolean_cons_vector;
signal V9 : severity_level_cons_vector ;
signal V10 : integer_cons_vector;
signal V11 : real_cons_vector;
signal V12 : time_cons_vector ;
signal V13 : natural_cons_vector ;
signal V14 : positive_cons_vector ;
signal V15 : boolean_cons_vectorofvector ;
signal V16 : severity_level_cons_vectorofvector;
signal V17 : integer_cons_vectorofvector;
signal V18 : real_cons_vectorofvector;
signal V19 : time_cons_vectorofvector;
signal V20 : natural_cons_vectorofvector;
signal V21 : positive_cons_vectorofvector;
signal V22 : record_std_package;
signal V23 : record_cons_array ;
signal V24 : record_cons_arrayofarray ;
signal V25 : boolean_vector_st ;
signal V26 : severity_level_vector_st ;
signal V27 : integer_vector_st ;
signal V28 : real_vector_st ;
signal V29 : time_vector_st ;
signal V30 : natural_vector_st ;
signal V31 : positive_vector_st ;
signal V32 : record_array_st ;
signal V33 : record_array_st ;
signal V34 : record_array_new ;
signal V35 : record_of_records ;
signal V36 : byte ;
signal V37 : word ;
signal V41 : boolean_vector_range ;
signal V42 : severity_level_vector_range ;
signal V43 : integer_vector_range ;
signal V44 : real_vector_range ;
signal V45 : time_vector_range ;
signal V46 : natural_vector_range ;
signal V47 : positive_vector_range ;
signal V48 : array_rec_std(zero to seven) ;
signal V49 : array_rec_cons(zero to seven) ;
signal V50 : array_rec_rec(zero to seven) ;
signal V51 : record_of_arr_of_record ;
BEGIN
V1 <= (zero to fifteen => C1);
V2 <= (zero to fifteen => C4);
V3 <= (zero to fifteen => C5);
V4 <= (zero to fifteen => C6);
V5 <= (zero to fifteen => C7);
V6 <= (zero to fifteen => C8);
V7 <= (zero to fifteen => C9);
V8 <= C19;
V9 <= C20;
V10 <= C21;
V11 <= C22;
V12 <= C23;
V13 <= C24;
V14 <= C25;
V15 <= C26;
V16 <= C27;
V17 <= C28;
V18 <= C29;
V19 <= C30;
V20 <= C31;
V21 <= C32;
V22 <= C50;
V23 <= C51;
V24 <= C53;
V25 <= C70;
V26 <= C71;
V27 <= C72;
V28 <= C73;
V29 <= C74;
V30 <= C75;
V31 <= C76;
V32 <= C54a;
V33 <= C54a;
V34 <= C54b;
V35 <= C55;
V36 <= C60;
V37 <= C61;
V41 <= C78;
V42 <= C79;
V43 <= C80;
V44 <= C81;
V45 <= C82;
V46 <= C83;
V47 <= C84;
V48 <= C85;
V49 <= C86;
V50 <= C88;
V51 <= C102;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00749"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00749 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00749arch;
|
gpl-2.0
|
96f1a17428417b2f59dd29a70fc73545
| 0.544579 | 3.721267 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/top.vhd
| 1 | 15,124 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: TOP
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TOP is
Generic (
SOUND_ENABLE : boolean := false -- Enable / disable sound
);
Port (
CLK : in std_logic; -- Clock - 50 MHz
ASYNC_RST : in std_logic; -- High active asynchronous reset
-- PS2 INTERFACE
PS2_CLK : in std_logic; -- PS2 CLK
PS2_DATA : in std_logic; -- PS2 DATA
-- VGA INTERFACE
VGA_RED : out std_logic_vector(2 downto 0); -- VGA RED
VGA_GREEN : out std_logic_vector(2 downto 0); -- VGA GREEN
VGA_BLUE : out std_logic_vector(1 downto 0); -- VGA BLUE
VGA_H_SYNC : out std_logic; -- VGA H-SYNC
VGA_V_SYNC : out std_logic; -- VGA V-SYNC
-- SOUND OUTPUT
SOUND : out std_logic; -- Sound output
-- CTRL LEDS
LED_GWIN : out std_logic; -- LED GAME WIN
LED_GOVER : out std_logic -- LED GAME OVER
);
end TOP;
architecture FULL of TOP is
-- reset signals
signal async_rst_deb : std_logic;
signal reset : std_logic;
-- keys signals
signal sig_key_w : std_logic;
signal sig_key_s : std_logic;
signal sig_key_a : std_logic;
signal sig_key_d : std_logic;
signal sig_key_space : std_logic;
-- pixels signals
signal pix_x : std_logic_vector(9 downto 0);
signal pix_y : std_logic_vector(9 downto 0);
signal pix_x1 : std_logic_vector(9 downto 0);
signal pix_y1 : std_logic_vector(9 downto 0);
signal pix_x2 : std_logic_vector(9 downto 0);
signal pix_y2 : std_logic_vector(9 downto 0);
-- cell ctrl signals
signal sig_pix_set_x : std_logic;
signal sig_pix_set_y : std_logic;
signal sig_komp_set_x : std_logic;
signal sig_komp_set_y : std_logic;
signal sig_komp_on : std_logic;
signal sig_komp4_is : std_logic;
signal sig_komp_out : std_logic_vector(5 downto 0);
-- video signals
signal sig_hsync : std_logic;
signal sig_vsync : std_logic;
signal sig_hsync1 : std_logic;
signal sig_vsync1 : std_logic;
signal sig_hsync2 : std_logic;
signal sig_vsync2 : std_logic;
signal sig_hsync3 : std_logic;
signal sig_vsync3 : std_logic;
signal sig_hsync4 : std_logic;
signal sig_vsync4 : std_logic;
signal sig_rgb : std_logic_vector(2 downto 0);
-- memory signals
signal sig_addr_cell_ctrl : std_logic_vector(7 downto 0);
signal sig_addr_cell_ctrl_2 : std_logic_vector(8 downto 0);
signal sig_dout_cell_gen : std_logic_vector(31 downto 0);
signal sig_we_hub : std_logic;
signal sig_addr_hub : std_logic_vector(7 downto 0);
signal sig_addr_hub_2 : std_logic_vector(8 downto 0);
signal sig_dout_hub : std_logic_vector(31 downto 0);
signal sig_din_hub : std_logic_vector(31 downto 0);
-- memory hub signals
signal hub_we_a : std_logic;
signal hub_en_a : std_logic;
signal hub_addr_a : std_logic_vector(7 downto 0);
signal hub_din_a : std_logic_vector(31 downto 0);
signal hub_dout_a : std_logic_vector(31 downto 0);
signal hub_ack_a : std_logic;
signal hub_we_b : std_logic;
signal hub_en_b : std_logic;
signal hub_addr_b : std_logic_vector(7 downto 0);
signal hub_din_b : std_logic_vector(31 downto 0);
signal hub_dout_b : std_logic_vector(31 downto 0);
signal hub_ack_b : std_logic;
-- kurzor signals
signal sig_kurzor : std_logic;
signal sig_kurzor_addr : std_logic_vector(7 downto 0);
-- roura generator signals
signal sig_komp0 : std_logic_vector(5 downto 0);
signal sig_komp1 : std_logic_vector(5 downto 0);
signal sig_komp2 : std_logic_vector(5 downto 0);
signal sig_komp3 : std_logic_vector(5 downto 0);
signal sig_komp4 : std_logic_vector(5 downto 0);
signal sig_gen_new : std_logic;
signal sig_gen_five : std_logic;
-- sounds signals
signal sound_place_pipe : std_logic;
signal sound_cant_place : std_logic;
signal sound_win : std_logic;
signal sound_lose : std_logic;
-- game ctrl
signal sig_lvl1 : std_logic;
signal sig_lvl2 : std_logic;
signal sig_lvl3 : std_logic;
signal sig_lvl4 : std_logic;
signal sig_screen_code : std_logic_vector(2 downto 0);
signal sig_game_on : std_logic;
signal sig_win : std_logic;
signal sig_lose : std_logic;
signal sig_load_water : std_logic_vector(7 downto 0);
signal rst_wtr_ctrl : std_logic;
signal wtr_ctrl_start : std_logic;
begin
LED_GWIN <= sig_win;
LED_GOVER <= sig_lose;
VGA_RED <= sig_rgb(2) & sig_rgb(2) & sig_rgb(2);
VGA_GREEN <= sig_rgb(1) & sig_rgb(1) & sig_rgb(1);
VGA_BLUE <= sig_rgb(0) & sig_rgb(0);
VGA_V_SYNC <= sig_vsync4;
VGA_H_SYNC <= sig_hsync4;
----------------------------------------------------------------------------
-- RESET DEBOUNCER AND SYNCHRONIZER
----------------------------------------------------------------------------
async_rst_debouncer_i: entity work.DEBOUNCER
port map(
CLK => CLK,
RST => '0',
DIN => ASYNC_RST,
DOUT => async_rst_deb -- Debounced Asynchronous Reset
);
reset_sync_i: entity work.RESET_SYNC
port map(
CLK => CLK,
ASYNC_RST => async_rst_deb,
OUT_RST => reset -- Synchronized Asynchronous Reset
);
----------------------------------------------------------------------------
-- PS2 DRIVER
----------------------------------------------------------------------------
ps2_i: entity work.PS2
port map(
CLK => CLK,
RST => reset,
PS2C => PS2_CLK,
PS2D => PS2_DATA,
KEY_W => sig_key_w,
KEY_S => sig_key_s,
KEY_A => sig_key_a,
KEY_D => sig_key_d,
KEY_SPACE => sig_key_space
);
----------------------------------------------------------------------------
-- VIDEO GENERATOR
----------------------------------------------------------------------------
-- VGA driver
vga_sync_i: entity work.VGA_SYNC
port map(
CLK => CLK,
RST => reset,
PIXEL_X => pix_x,
PIXEL_Y => pix_y,
HSYNC => sig_hsync,
VSYNC => sig_vsync
);
cell_ctrl_i: entity work.CELL_CTRL
port map(
CLK => CLK,
PIXEL_X => pix_x,
PIXEL_Y => pix_y,
KURZOR_ADDR => sig_kurzor_addr,
KURZOR => sig_kurzor,
PIXEL_SET_X => sig_pix_set_x,
PIXEL_SET_Y => sig_pix_set_y,
KOMP_SET_X => sig_komp_set_x,
KOMP_SET_Y => sig_komp_set_y,
KOMP_ON => sig_komp_on,
KOMP4_IS => sig_komp4_is,
ADDR => sig_addr_cell_ctrl,
KOMP0 => sig_komp0,
KOMP1 => sig_komp1,
KOMP2 => sig_komp2,
KOMP3 => sig_komp3,
KOMP4 => sig_komp4,
KOMP_OUT => sig_komp_out,
SCREEN_CODE => sig_screen_code
);
sig_addr_cell_ctrl_2 <= '0' & sig_addr_cell_ctrl;
cell_generator_i: entity work.CELL_GENERATOR
port map(
CLK => CLK,
RST => reset,
TYP_ROURY => sig_dout_cell_gen(3 downto 0),
NATOCENI_ROURY => sig_dout_cell_gen(5 downto 4),
ROURA_VODA1 => sig_dout_cell_gen(15 downto 10),
ROURA_VODA2 => sig_dout_cell_gen(21 downto 16),
ZDROJ_VODY1 => sig_dout_cell_gen(25 downto 22),
ZDROJ_VODY2 => sig_dout_cell_gen(29 downto 26),
KURZOR => sig_kurzor,
PIXEL_X2 => pix_x2,
PIXEL_Y2 => pix_y2,
PIXEL_SET_X => sig_pix_set_x,
PIXEL_SET_Y => sig_pix_set_y,
KOMP_SET_X => sig_komp_set_x,
KOMP_SET_Y => sig_komp_set_y,
KOMP_ON => sig_komp_on,
KOMP4_IS => sig_komp4_is,
KOMP_IN => sig_komp_out,
GAME_ON => sig_game_on,
LOAD_WATER => sig_load_water,
RGB => sig_rgb
);
-- pixels and sync shift registers
vga_shreg_p: process (CLK)
begin
if (rising_edge(CLK)) then
sig_hsync1 <= sig_hsync;
sig_hsync2 <= sig_hsync1;
sig_hsync3 <= sig_hsync2;
sig_hsync4 <= sig_hsync3;
sig_vsync1 <= sig_vsync;
sig_vsync2 <= sig_vsync1;
sig_vsync3 <= sig_vsync2;
sig_vsync4 <= sig_vsync3;
pix_x1 <= pix_x;
pix_x2 <= pix_x1;
pix_y1 <= pix_y;
pix_y2 <= pix_y1;
end if;
end process;
----------------------------------------------------------------------------
-- OBVODY RIDICI KURZOR A V KLADANI ROUR
----------------------------------------------------------------------------
kurzor_ctrl_i: entity work.KURZOR_CTRL
port map(
CLK => CLK,
RST => reset,
KEY_W => sig_key_w,
KEY_S => sig_key_s,
KEY_A => sig_key_a,
KEY_D => sig_key_d,
KEY_SPACE => sig_key_space,
KOMP_GEN => sig_gen_new,
KURZOR_ADDR => sig_kurzor_addr,
DATAIN => hub_dout_a,
DATAOUT => hub_din_a,
ADDR => hub_addr_a,
EN => hub_en_a,
WE => hub_we_a,
ACK => hub_ack_a,
KOMP4 => sig_komp4,
CANT_PLACE => sound_cant_place,
CAN_PLACE => sound_place_pipe,
SCREEN_CODE => sig_screen_code,
GAME_ON => sig_game_on
);
random_decoder_fifo_i: entity work.RANDOM_DECODER_FIFO
port map(
CLK => CLK,
RST => reset,
GENERATE_NEW => sig_gen_new, -- po poslani enable signalu se obevi nova komponenta
GENERATE_FIVE => sig_gen_five, -- po poslani enable signalu se obevi 5 novych komponent
KOMP0 => sig_komp0,
KOMP1 => sig_komp1,
KOMP2 => sig_komp2,
KOMP3 => sig_komp3,
KOMP4 => sig_komp4
);
----------------------------------------------------------------------------
-- PAMETI
----------------------------------------------------------------------------
-- BRAM pamet pro stavy policek
bram_i: entity work.BRAM_SYNC_TDP
generic map(
DATA_WIDTH => 32, -- Sirka datoveho vstupu a vystupu
ADDR_WIDTH => 9 -- Sirka adresove sbernice, urcuje take pocet polozek v pameti (2^ADDR_WIDTH)
)
port map(
CLK => CLK,
-- Port A
WE_A => sig_we_hub,
ADDR_A => sig_addr_hub_2,
DATAIN_A => sig_din_hub,
DATAOUT_A => sig_dout_hub,
-- Port B - Pouziva ho pouze VGA radic a to pouze ke cteni
WE_B => '0',
ADDR_B => sig_addr_cell_ctrl_2,
DATAIN_B => (others => '0'),
DATAOUT_B => sig_dout_cell_gen
);
-- Rozdvojka pameti
mem_hub_i: entity work.MEM_HUB
port map(
CLK => CLK,
RST => reset,
-- Port A
EN_A => hub_en_a,
WE_A => hub_we_a,
ADDR_A => hub_addr_a,
DIN_A => hub_din_a,
DOUT_A => hub_dout_a,
ACK_A => hub_ack_a,
-- Port B
EN_B => hub_en_b,
WE_B => hub_we_b,
ADDR_B => hub_addr_b,
DIN_B => hub_din_b,
DOUT_B => hub_dout_b,
ACK_B => hub_ack_b,
-- Port to memory
WE => sig_we_hub,
ADDR => sig_addr_hub,
DIN => sig_din_hub,
DOUT => sig_dout_hub
);
sig_addr_hub_2 <= '0' & sig_addr_hub;
wtr_ctrl_i: entity work.WTR_CTRL
port map(
CLK => CLK,
RST => rst_wtr_ctrl,
ADR => hub_addr_b,
CELL_IN => hub_dout_b,
CELL_OUT => hub_din_b,
WE_OUT => hub_we_b,
RE_OUT => hub_en_b,
WIN_BIT => sig_win,
KNLG_next => hub_ack_b,
START => wtr_ctrl_start,
fail_out => sig_lose
);
----------------------------------------------------------------------------
-- SOUND
----------------------------------------------------------------------------
enable_sound_g: if (SOUND_ENABLE = true) generate
sound_i: entity work.MUZIKA
port map(
CLK => CLK,
RST => reset,
PLACE_PIPE => sound_place_pipe,
CANT_PLACE => sound_cant_place,
WIN_LEVEL => sound_win,
GAME_OVER => sound_lose,
MUSIC => SOUND
);
rised_sound_1_i: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_win,
VYSTUP => sound_win
);
rised_sound_2_i: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_lose,
VYSTUP => sound_lose
);
end generate;
disable_sound_g: if (SOUND_ENABLE = false) generate
SOUND <= '0';
end generate;
----------------------------------------------------------------------------
-- GAME CTRL
----------------------------------------------------------------------------
game_ctrl_i: entity work.GAME_CTRL
port map(
CLK => CLK,
RST => reset,
WIN => sig_win,
LOSE => sig_lose,
KEY_W => sig_key_w,
KEY_S => sig_key_s,
KEY_A => sig_key_a,
KEY_D => sig_key_d,
GEN5_EN => sig_gen_five,
SCREEN_CODE => sig_screen_code,
GAME_ON => sig_game_on,
WATER => sig_load_water
);
rst_wtr_ctrl <= reset or not sig_game_on;
wtr_ctrl_start <= '1' when (sig_load_water = "11111111") else '0';
end FULL;
|
mit
|
cd85b03fdd73f22ac37c096e356ec4d0
| 0.447368 | 3.695992 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd
| 4 | 2,259 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity resolve_tri_state_logic is
end entity resolve_tri_state_logic;
architecture test of resolve_tri_state_logic is
-- code from book (in text)
type tri_state_logic is ('0', '1', 'Z');
type tri_state_logic_array is array (integer range <>) of tri_state_logic;
-- end code from book
-- code from book
function resolve_tri_state_logic ( values : in tri_state_logic_array )
return tri_state_logic is
variable result : tri_state_logic := 'Z';
begin
for index in values'range loop
if values(index) /= 'Z' then
result := values(index);
end if;
end loop;
return result;
end function resolve_tri_state_logic;
-- end code from book
-- code from book (in text)
signal s1 : resolve_tri_state_logic tri_state_logic;
subtype resolved_logic is resolve_tri_state_logic tri_state_logic;
signal s2, s3 : resolved_logic;
-- end code from book
begin
source_1 : s1 <= 'Z',
'0' after 10 ns,
'Z' after 20 ns,
'1' after 30 ns,
'Z' after 40 ns,
'1' after 200 ns,
'Z' after 220 ns;
source_2 : s1 <= 'Z',
'0' after 110 ns,
'Z' after 120 ns,
'1' after 130 ns,
'Z' after 140 ns,
'1' after 200 ns,
'0' after 210 ns,
'Z' after 220 ns;
end architecture test;
|
gpl-2.0
|
e3a5051cf98fcb94db7a4504e0f72e8d
| 0.61266 | 3.915078 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/non_compliant/ch_04_ch_04_09.vhd
| 4 | 2,329 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_09.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_09 is
end entity ch_04_09;
----------------------------------------------------------------
architecture test of ch_04_09 is
begin
process_04_3_c : process is
-- code from book:
subtype name is string(1 to 20);
type display_string is array (integer range 0 to 19) of character;
variable item_name : name;
variable display : display_string;
--
subtype big_endian_upper_halfword is bit_vector(0 to 15);
subtype little_endian_upper_halfword is bit_vector(31 downto 16);
variable big : big_endian_upper_halfword;
variable little : little_endian_upper_halfword;
-- end of code from book
begin
-- error: Incompatible types for assignment
-- display := item_name; -- ilegal
item_name := (others => 'A');
little := x"AAAA";
-- code from book:
display := display_string(item_name);
--
big := little;
little := big;
-- end of code from book
wait;
end process process_04_3_c;
----------------
end architecture test;
|
gpl-2.0
|
4c40f57b7371ff31969eda437901e16d
| 0.535852 | 4.648703 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd
| 4 | 1,811 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_v_source is
end tb_v_source ;
architecture TB_v_source of tb_v_source is
terminal sin_out1, sin_out2 : electrical;
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
v1 : entity work.v_source(behavior)
port map(
pos => sin_out1,
neg => ELECTRICAL_REF
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => sin_out1,
p2 => electrical_ref
);
v2 : entity work.v_constant(ideal)
generic map(
level => 1.0
)
port map(
pos => sin_out2,
neg => ELECTRICAL_REF
);
R2 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => sin_out2,
p2 => electrical_ref
);
end TB_v_source ;
|
gpl-2.0
|
400f960893f3e9f594eac1ed5c97680e
| 0.615682 | 4.024444 | false | false | false | false |
tristanseifert/68komputer
|
VideoCRAM.vhd
| 1 | 9,640 |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: VideoCRAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.0 Build 156 04/24/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY VideoCRAM IS
PORT
(
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclock : IN STD_LOGIC ;
wraddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wrclock : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END VideoCRAM;
ARCHITECTURE SYN OF videocram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock1 : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(23 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
init_file => "default_palette.mif",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 256,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => 8,
widthad_b => 8,
width_a => 24,
width_b => 24,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => wrclock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
clock1 => rdclock,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "1"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "6144"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "default_palette.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "24"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "24"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "24"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "24"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "default_palette.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "24"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
-- Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
-- Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 24 0 data 0 0 24 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 24 0 @q_b 0 0 24 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoCRAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoCRAM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoCRAM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoCRAM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoCRAM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
bsd-2-clause
|
f4acf05967c339d42e0294db96d5aa3f
| 0.665664 | 3.397956 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2395.vhd
| 4 | 2,080 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2395.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n02i02395ent IS
END c07s03b02x00p07n02i02395ent;
ARCHITECTURE c07s03b02x00p07n02i02395arch OF c07s03b02x00p07n02i02395ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype ONE is BIT_VECTOR( 0 to 0);
-- Declare array variables of these types.
variable ONEV1 : ONE;
variable ONEV2 : ONE;
BEGIN
ONEV1 := ONE'( 0 => '0' );
assert( ONEV1( 0 ) = '0' );
ONEV2 := ONE'( 0 => '1' );
assert( ONEV2( 0 ) = '1' );
assert NOT(( ONEV1( 0 ) = '0' ) and ( ONEV2( 0 ) = '1' ))
report "***PASSED TEST: c07s03b02x00p07n02i02395"
severity NOTE;
assert (( ONEV1( 0 ) = '0' ) and ( ONEV2( 0 ) = '1' ))
report "***FAILED TEST: c07s03b02x00p07n02i02395 - Aggregate specification should be using named association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n02i02395arch;
|
gpl-2.0
|
405f89b88db1b9f65c1015934bbd70dd
| 0.643269 | 3.549488 | false | true | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/sound/muzika.vhd
| 1 | 11,954 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: MUZIKA
-- AUTHORS: Vojtěch Jeřábek <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
--po privedeni enagle signalu na jednotlive vstupy je odehrana prislusna melodie
entity MUZIKA is
Port ( PLACE_PIPE : in STD_LOGIC;
CANT_PLACE : in STD_LOGIC;
WIN_LEVEL : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
GAME_OVER : in STD_LOGIC;
MUSIC : out STD_LOGIC);
end MUZIKA;
architecture Behavioral of MUZIKA is
type state is (silent, A, H, G, C, step_down, step_down_tone_state, cant_place_tone_state, step_down_tone_state_prepare);
type state0 is (no_sound, place_pipe_state, win_level_state, cant_place_state, game_over_state);
signal present_st : state;
signal next_st : state;
signal present_st0 : state0;
signal next_st0 : state0;
signal G_TONE1 : STD_LOGIC;
signal A_TONE1 : STD_LOGIC;
signal H_TONE1 : STD_LOGIC;
signal C_TONE1 : STD_LOGIC;
signal G_TONE2 : STD_LOGIC;
signal A_TONE2 : STD_LOGIC;
signal H_TONE2 : STD_LOGIC;
signal C_TONE2 : STD_LOGIC;
signal G_TONE : STD_LOGIC;
signal A_TONE : STD_LOGIC;
signal H_TONE : STD_LOGIC;
signal C_TONE : STD_LOGIC;
signal cant_place_tone : STD_LOGIC;
signal music_signal : std_logic;
signal music_out_enable : std_logic;
signal play_place_pipe : std_logic;
signal play_cant_place : std_logic;
signal playing : std_logic;
signal play_win_level : std_logic;
signal play_game_over : std_logic;
signal period_counter : std_logic_vector(18 downto 0);
signal lenght_signal : std_logic_vector(18 downto 0);
signal melody_counter : std_logic_vector(27 downto 0);
begin
----melodie
----Pametova cast stavoveho automatu
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
present_st0 <= no_sound;
else
present_st0 <= next_st0;
end if;
end if;
end process;
process (CANT_PLACE, PLACE_PIPE, WIN_LEVEL, playing, present_st0, GAME_OVER)
begin
case present_st0 is
when no_sound =>
if (PLACE_PIPE = '1') then
next_st0 <= place_pipe_state;
elsif (WIN_LEVEL = '1') then
next_st0 <= win_level_state;
elsif (CANT_PLACE = '1') then
next_st0 <= cant_place_state;
elsif (GAME_OVER = '1') then
next_st0 <= game_over_state;
else
next_st0 <= no_sound;
end if;
play_place_pipe <= '0';
play_win_level <= '0';
play_cant_place <= '0';
play_game_over <= '0';
when place_pipe_state =>
if (playing = '1' AND WIN_LEVEL = '0' AND CANT_PLACE = '0' AND GAME_OVER = '0') then
next_st0 <= place_pipe_state;
else
next_st0 <= no_sound;
end if;
play_win_level <= '0';
play_place_pipe <= '1';
play_cant_place <= '0';
play_game_over <= '0';
when win_level_state =>
if (playing = '1' AND CANT_PLACE = '0' AND PLACE_PIPE = '0' AND GAME_OVER = '0') then
next_st0 <= win_level_state;
else
next_st0 <= no_sound;
end if;
play_place_pipe <= '0';
play_win_level <= '1';
play_cant_place <= '0';
play_game_over <= '0';
when cant_place_state =>
if (playing = '1' AND WIN_LEVEL = '0' AND PLACE_PIPE = '0' AND GAME_OVER = '0') then
next_st0 <= cant_place_state;
else
next_st0 <= no_sound;
end if;
play_place_pipe <= '0';
play_win_level <= '0';
play_cant_place <= '1';
play_game_over <= '0';
when game_over_state =>
if (playing = '1' AND WIN_LEVEL = '0' AND PLACE_PIPE = '0' AND CANT_PLACE = '0') then
next_st0 <= game_over_state;
else
next_st0 <= no_sound;
end if;
play_game_over <= '1';
play_place_pipe <= '0';
play_win_level <= '0';
play_cant_place <= '0';
when others =>
next_st0 <= no_sound;
play_win_level <= '0';
play_place_pipe <= '0';
play_cant_place <= '0';
play_game_over <= '0';
end case;
end process;
--Melodie p�i polo�en� trubky
process(clk) begin
if (rising_edge(CLK)) then
if (play_place_pipe = '1') then
if (melody_counter > 0 AND melody_counter<1562501) then
G_TONE1 <= '1';
A_TONE1 <= '0';
H_TONE1 <= '0';
C_TONE1 <= '0';
melody_counter <= melody_counter + 1;
playing <= '1';
elsif (melody_counter>1562500 AND melody_counter<3125000) then
G_TONE1 <= '0';
A_TONE1 <= '1';
H_TONE1 <= '0';
C_TONE1 <= '0';
melody_counter <= melody_counter + 1;
playing <= '1';
elsif (melody_counter=3125000) then
melody_counter <= (others=>'0');
playing <= '0';
elsif (melody_counter=0) then
G_TONE1 <= '0';
A_TONE1 <= '0';
H_TONE1 <= '0';
C_TONE1 <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
end if;
--vyherni melodie
elsif (play_win_level = '1') then
if (melody_counter>0 AND melody_counter<18000000) then
G_TONE2 <= '0';
A_TONE2 <= '1';
H_TONE2 <= '0';
C_TONE2 <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
elsif (melody_counter>18750000 AND melody_counter<24250001) then
G_TONE2 <= '0';
A_TONE2 <= '1';
H_TONE2 <= '0';
C_TONE2 <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
elsif (melody_counter>25000000 AND melody_counter<37500001) then
melody_counter <= (others=>'0');
G_TONE2 <= '0';
A_TONE2 <= '1';
H_TONE2 <= '0';
C_TONE2 <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
elsif (melody_counter>37500000 AND melody_counter<50000001) then
G_TONE2 <= '1';
A_TONE2 <= '0';
H_TONE2 <= '0';
C_TONE2 <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
elsif (melody_counter>50000000 AND melody_counter<62500001) then
G_TONE2 <= '0';
A_TONE2 <= '1';
H_TONE2 <= '0';
C_TONE2 <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
elsif (melody_counter>62500000 AND melody_counter<68750001) then
G_TONE2 <= '0';
A_TONE2 <= '0';
H_TONE2 <= '1';
C_TONE2 <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
elsif (melody_counter>68750000 AND melody_counter<75000001) then
G_TONE2 <= '0';
A_TONE2 <= '0';
H_TONE2 <= '0';
C_TONE2 <= '1';
playing <= '1';
melody_counter <= melody_counter + 1;
elsif (melody_counter>75000000 AND melody_counter<100000000) then
G_TONE2 <= '0';
A_TONE2 <= '0';
H_TONE2 <= '1';
C_TONE2 <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
elsif (melody_counter=100000000) then
playing <= '0';
melody_counter <= (others=>'0');
elsif (melody_counter=0) then
G_TONE2 <= '0';
A_TONE2 <= '0';
H_TONE2 <= '0';
C_TONE2 <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
else
G_TONE2 <= '0';
A_TONE2 <= '0';
H_TONE2 <= '0';
C_TONE2 <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
end if;
-- kdyz nelze polozit trubku
elsif (play_cant_place='1') then
if (melody_counter>0 AND melody_counter<12500000) then
playing <= '1';
cant_place_tone <= '1';
melody_counter <= melody_counter + 1;
elsif (melody_counter=12500000) then
playing <= '0';
melody_counter <= (others=>'0');
elsif (melody_counter=0) then
cant_place_tone <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
else
playing <= '1';
melody_counter <= melody_counter + 1;
end if;
--pri prohrani hry
elsif (play_game_over='1') then
if (melody_counter>0 AND melody_counter<70000000) then
playing <= '1';
cant_place_tone <= '1';
melody_counter <= melody_counter + 1;
elsif (melody_counter=70000000) then
playing <= '0';
melody_counter <= (others=>'0');
elsif (melody_counter=0) then
cant_place_tone <= '0';
playing <= '1';
melody_counter <= melody_counter + 1;
else
playing <= '1';
melody_counter <= melody_counter + 1;
end if;
else
G_TONE2 <= '0';
A_TONE2 <= '0';
H_TONE2 <= '0';
C_TONE2 <= '0';
cant_place_tone <= '0';
melody_counter <= (others=>'0');
end if;
end if;
end process;
----------------------------------------------------------------
-- STAVOVY AUTOMAT pro generovani tonu
----------------------------------------------------------------
-- Pametova cast stavoveho automatu
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
present_st <= silent;
else
present_st <= next_st;
end if;
end if;
end process;
-- Rozhodovaci cast stavoveho automatu
process (C_TONE, A_TONE, H_TONE, G_TONE, present_st, cant_place_tone)
begin
case present_st is
when silent =>
if (C_TONE = '1') then
next_st <= C;
elsif (cant_place_tone = '1') then
next_st <= cant_place_tone_state;
elsif (G_TONE = '1') then
next_st <= G;
elsif (A_TONE = '1') then
next_st <= A;
elsif (H_TONE = '1') then
next_st <= H;
else
next_st <= silent;
end if;
music_out_enable <= '0';
lenght_signal <= (others=>'0');
when cant_place_tone_state =>
if (cant_place_tone = '1') then
next_st <= cant_place_tone_state;
else
next_st <= silent;
end if;
lenght_signal <= std_logic_vector(to_unsigned(262113,19));
music_out_enable <= '1';
when G =>
if (G_TONE = '1') then
next_st <= G;
else
next_st <= silent;
end if;
lenght_signal <= std_logic_vector(to_unsigned(63777,19));
music_out_enable <= '1';
when A =>
if (A_TONE = '1') then
next_st <= A;
else
next_st <= silent;
end if;
lenght_signal <= std_logic_vector(to_unsigned(56819,19));
music_out_enable <= '1';
when H =>
if (H_TONE = '1') then
next_st <= H;
else
next_st <= silent;
end if;
lenght_signal <= std_logic_vector(to_unsigned(50620,19));
music_out_enable <= '1';
when C =>
if (C_TONE = '1') then
next_st <= C;
else
next_st <= silent;
end if;
lenght_signal <= std_logic_vector(to_unsigned(47779,19));
music_out_enable <= '1';
when others =>
next_st <= silent;
music_out_enable <= '0';
lenght_signal <= std_logic_vector(to_unsigned(0,19));
end case;
end process;
--citac pro generovani jednotlivych tonu
process(clk) begin
if (rising_edge(CLK)) then
if (music_out_enable = '1') then
if (period_counter = lenght_signal) then
period_counter <= (others=>'0');
music_signal <= music_signal xor '1';
else
period_counter <= period_counter + 1;
end if;
else
music_signal <= '0';
end if;
end if;
end process;
MUSIC <= music_signal AND music_out_enable;
G_TONE <= G_TONE1 OR G_TONE2;
A_TONE <= A_TONE1 OR A_TONE2;
H_TONE <= H_TONE1 OR H_TONE2;
C_TONE <= C_TONE1 OR C_TONE2;
end Behavioral;
|
mit
|
d28a62e300fd0ea2c8669cf84bc7bf15
| 0.530347 | 2.989239 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/a2d_nbit.vhd
| 4 | 3,596 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity a2d_nbit is
port ( signal start : in std_ulogic; -- Start signal
signal clk : in std_ulogic; -- Strobe clock
terminal ain : electrical; -- Analog input terminal
signal eoc : out std_ulogic := '0'; -- End of conversion pin
signal dout : out std_ulogic_vector(9 downto 0) ); -- Digital output signal
end entity a2d_nbit;
----------------------------------------------------------------
architecture sar of a2d_nbit is
constant Vmax : real := 5.0; -- ADC's maximum range
constant delay : time := 10 us; -- ADC's conversion time
type states is (input, convert); -- Two states of A2D Conversion
constant bit_range : integer := 9; -- Bit range for dtmp and dout
quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
begin
sa_adc: process is
variable thresh : real := Vmax; -- Threshold to test input voltage against
variable Vtmp : real := Vin; -- Snapshot of input voltage
-- when conversion starts
variable dtmp : std_ulogic_vector(bit_range downto 0); -- Temp. output data
variable status : states := input; -- Begin with "input" case
variable bit_cnt : integer := bit_range;
begin
case status is
when input => -- Read input voltages when start goes high
wait on start until start = '1' or start = 'H';
bit_cnt := bit_range; -- Reset bit_cnt for conversion
thresh := Vmax;
Vtmp := Vin; -- Variable to hold input comparison voltage
eoc <= '0'; -- Reset end of conversion
status := convert; -- Go to convert state
when convert => -- Begin successive approximation conversion
wait on clk until clk = '1' or clk = 'H';
thresh := thresh / 2.0; -- Get value of MSB
if Vtmp > thresh then
dtmp(bit_cnt) := '1'; -- Store '1' in dtmp variable vector
Vtmp := Vtmp - thresh; -- Prepare for next comparison
else
dtmp(bit_cnt) := '0'; -- Store '0' in dtmp variable vector
end if;
if bit_cnt > 0 then
bit_cnt := bit_cnt - 1; -- Decrement the bit count
else
dout <= dtmp; -- Put contents of dtmp on output pins
eoc <= '1' after delay; -- Signal end of conversion
status := input; -- Go to input state
end if;
end case;
end process sa_adc;
Iin == 0.0; -- Ideal input draws no current
end architecture sar;
|
gpl-2.0
|
0324e462c5e2e2813dd898179e396c5a
| 0.589822 | 4.358788 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2386.vhd
| 4 | 1,809 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2386.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n01i02386ent IS
END c07s03b02x00p07n01i02386ent;
ARCHITECTURE c07s03b02x00p07n01i02386arch OF c07s03b02x00p07n01i02386ent IS
BEGIN
TESTING: PROCESS
type array_three is array (1 to 6) of integer;
variable x : array_three := (1 =>10, 3 => 30,
others => 20, 2 => 25); -- Failure_here
-- no association can
-- follow an others association.
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x00p07n01i02386 - No association can follow an others association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n01i02386arch;
|
gpl-2.0
|
a54804eb5f8f3b10ce428302251cc9c4
| 0.657269 | 3.816456 | false | true | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/exceptions.vhd
| 1 | 2,173 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity exceptions is
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
int_mul: in std_logic_vector(31 downto 0);
enable: in std_logic;
m_in47:in std_logic;
exp_out: out std_logic_vector(31 downto 0)
);
end exceptions;
architecture arch_exceptions of exceptions is
signal expa :std_logic_vector (8 downto 0);
signal expb :std_logic_vector (8 downto 0);
signal summ :std_logic_vector (8 downto 0);
signal m :std_logic_vector (8 downto 0) ;
begin
expa<='0' & in1(30 downto 23);
expb<='0' & in2(30 downto 23);
m<="00000000" & m_in47;
summ<=std_logic_vector(unsigned(expa)+unsigned(expb)+unsigned(m));
process (enable,in1,in2,int_mul,summ)
begin
if(enable='1')then
-- not anumber
if (in1(30 downto 23)="11111111" and in1(22 downto 0 )/= "00000000000000000000000") then
exp_out<="11111111111111111111111111111111"; -- NaN
elsif (in2(30 downto 23)="11111111" and in2(22 downto 0 )/="00000000000000000000000") then
exp_out<="11111111111111111111111111111111"; -- NaN
elsif(in1=x"00000000")then
-- zero by infinity or negative infinity = NaN
if(in2(30 downto 0)="1111111100000000000000000000000")then
exp_out<="11111111111111111111111111111111"; --NaN
-- zero by any number = 0
else
exp_out<=(others=>'0');
end if;
elsif(in2=x"00000000")then
if(in1(30 downto 0)="1111111100000000000000000000000")then
exp_out<="11111111111111111111111111111111"; -- NaN
else
exp_out<=(others=>'0');
end if;
elsif(in1(30 downto 0)="1111111100000000000000000000000") then
exp_out<=int_mul(31)&in1(30 downto 0 );
elsif(in2(30 downto 0)="1111111100000000000000000000000") then
exp_out<=int_mul(31)&in2(30 downto 0 );
---overflow detector \\\ ----
elsif (summ>="111111100") then
exp_out<=int_mul(31)&"1111111100000000000000000000000";
-- underflow detector
elsif (summ<="001111111") then
exp_out<="00000000000000000000000000000000";
else
exp_out<=int_mul;
end if ;
end if;
end process;
end arch_exceptions;
|
mit
|
ef3867098f9f1acb87132ef589c68f19
| 0.675104 | 3.368992 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork-b.vhd
| 4 | 4,783 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_fork-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavior of fork is
begin
forker : process
variable cumulative_probabilities : probability_vector(1 to probabilities'length);
variable destination : positive range out_arc'range;
variable probabilities_index : positive range probabilities'range;
variable number_of_tokens_forked : natural := 0;
type counter_array is array (positive range out_arc'range) of natural;
variable number_forked_to_destination : counter_array := (others => 0);
variable random_info : random_info_record;
variable random_number : real;
type transaction_vector is array (positive range <>) of boolean;
variable out_arc_transaction_driving_value : transaction_vector(out_arc'range)
:= (others => false);
use std.textio.all;
file info_file : text;
variable L : line;
procedure write_summary is
begin
write(L, string'("Summary information for fork "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens forked = "));
write(L, natural(number_of_tokens_forked));
writeline(info_file, L);
for destination in out_arc'range loop
write(L, string'(" Number to output("));
write(L, destination);
write(L, string'(") = "));
write(L, number_forked_to_destination(destination));
write(L, string'(" ("));
write(L, real(number_forked_to_destination(destination))
/ real(number_of_tokens_forked),
digits => 4);
write(L, ')');
writeline(info_file, L);
end loop;
writeline(info_file, L);
end write_summary;
procedure write_trace is
begin
write(L, string'("Fork "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" forked to output "));
write(L, destination);
write(L, ' ');
write(L, in_arc.token, time_unit);
writeline(info_file, L);
end write_trace;
begin
assert probabilities'length = out_arc'length - 1
report "incorrent number of probabilities - should be "
& integer'image(out_arc'length - 1) severity failure;
cumulative_probabilities := probabilities;
for index in 2 to cumulative_probabilities'length loop
cumulative_probabilities(index) := cumulative_probabilities(index - 1)
+ cumulative_probabilities(index);
end loop;
init_uniform( random_info,
lower_bound => 0.0, upper_bound => 1.0, seed => seed );
file_open(info_file, info_file_name, write_mode);
loop
wait on info_detail'transaction, in_arc;
if info_detail'active and info_detail = summary then
write_summary;
end if;
if in_arc'event then
generate_random(random_info, random_number);
destination := out_arc'left;
for index in 1 to cumulative_probabilities'length loop
exit when random_number < cumulative_probabilities(index);
if out_arc'ascending then
destination := destination + 1;
else
destination := destination - 1;
end if;
end loop;
out_arc(destination) <= arc_type'( transaction => not out_arc_transaction_driving_value(destination),
token => in_arc.token );
out_arc_transaction_driving_value(destination) := not out_arc_transaction_driving_value(destination);
number_of_tokens_forked := number_of_tokens_forked + 1;
number_forked_to_destination(destination)
:= number_forked_to_destination(destination) + 1;
if info_detail = trace then
write_trace;
end if;
end if;
end loop;
end process forker;
end behavior;
|
gpl-2.0
|
b9d2f057e3fbe98eab234d98028e9f60
| 0.630567 | 4.074106 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/Modular/shantz_modular_113.vhd
| 1 | 5,072 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_113 is
generic(
NUM_BITS : positive := 113
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_113 is
----------------------------------------------------------------------------------------------------
-- m = 113, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000001";
-- control signals
signal CASO: std_logic_vector(1 downto 0);
signal c0, c1, c2, c3, c4, c5, c6, enA, enB, a_greater_b,a_eq_b: std_logic;
signal A, B, U, V, X2, Y2, toB, toV: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
X2 <= x & '0';
Y2 <= y & '0';
caso <= "00" when A(0) = '0' and currentState = CYCLE else
"01" when B(0) = '0' and currentState = CYCLE else
"10" when a_greater_b = '1' and currentState = CYCLE else
"11";
c0 <= '0' when caso = "01" else
'1';
c1 <= '0' when caso = "00" else
'1';
c2 <= '0' when caso = "01" else
'1';
c3 <= '0' when caso = "00" else
'1';
c4 <= '0' when CurrentState = Load1 else
'1';
c5 <= '0' when rst = '1' or currentState = LOAD1 else
'1';
c6 <= '0' when rst = '1' else
'1';
enA <= '1' when currentState = LOAD1 or caso = "00" or caso = "10" else
'0';
enB <= '1' when caso = "01" or caso = "11" or rst = '1' or currentstate = LOAD1 else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
celda_reg_A: entity celda_a(behave)
generic map(NUM_BITS)
port map( A, B, c0, c1, enA, rst, clk, toB, A);
celda_reg_U: entity celda_U(behave)
generic map(NUM_BITS)
port map(U, V, P, c2, c3, c4, enA, rst, clk, toV, U);
celda_reg_B: entity celda_B(behave)
generic map(NUM_BITS)
port map(toB, P , Y2, c5, c6, enB, clk, B);
celda_reg_V: entity celda_v(behave)
generic map(NUM_BITS)
port map(toV, X2, c5, c6, enB, clk, V);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if rst = '1' then
x_div_y <= (others => '0');
done <= '0';
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
currentState <= Cycle;
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
--done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
9ec0cd28c3798be5478014b4edba4c5d
| 0.411672 | 3.993701 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/memory/bram_rom_cell.vhd
| 1 | 24,460 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: BRAM_ROM_CELL
-- AUTHORS: Tomáš Bannert <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity BRAM_ROM_CELL is
Port (
CLK : in std_logic;
ROM_ADDR : in std_logic_vector(8 downto 0);
ROM_DOUT : out std_logic_vector(31 downto 0)
);
end BRAM_ROM_CELL;
architecture FULL of BRAM_ROM_CELL is
type rom_t is array (0 to 511) of std_logic_vector(0 to 31);
constant ROM : rom_t :=
(
"11111111111111111111111111111111",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"11111111111111111111111111111111",
-- Dalsi obrazek (rovna 1=modra) -- 0001
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- Dalsi obrazek (zahnuta 1=modra) 0010
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11100000000000000000000000000000",
"11100000000000000000000000000000",
"11100000000000000000000000000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"00000000000000001111111110000000",
"00000000000000001111111110000000",
"00000000000000000011111110000000",
"00000000000000000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11100001111111000011111110000000",
"11100001111111000011111110000000",
"11100001111111000011111110000000",
"00000001111111000011111110000000",
"00001111111111000011111111110000",
"00001111111111000011111111110000",
"00001111111111000011111111110000",
-- Dalsi obrazek (T 1=modra) - 0011
"00001111111111000011111111110000",
"00001111111111000011111111110000",
"00001111111111000011111111110000",
"00000001111111000011111110000000",
"11100001111111000011111110000111",
"11100001111111000011111110000111",
"11100001111111000011111110000111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11100001111111000011111110000111",
"11100001111111000011111110000111",
"11100001111111000011111110000111",
"00000001111111000011111110000000",
"00001111111111000011111111110000",
"00001111111111000011111111110000",
"00001111111111000011111111110000",
-- Dalsi obrazek (spodni cast bocni trubky 1=modra) - 0100
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111001110011100111001110011111",
"11111001110011100111001110011111",
"01111111111111111111111111111110",
"01111111111111111111111111111110",
"01111111111111111111111111111110",
"00111111111111111111111111111100",
"00111111111111111111111111111100",
"00011111111111111111111111111000",
"00001111111111111111111111110000",
"00000111111111111111111111100000",
"00000011111111111111111111000000",
"00000001111111111111111110000000",
"00000000011111111111111000000000",
"00000000000011111111000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
-- Dalsi obrazek (telo trubky 1=bila 8x) - 0101
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
-- Dalsi obrazek (vrchni cast bocni trubky 1=modra) - 0110
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
-- Dalsi obrazek (propojka bocni trubky s hernim polem 1=modra) - 0111
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- Dalsi obrazek (koncova trubka 1=modra) - 1000
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111000011111111111111",
"11111111111100111100111111111111",
"11111111111001111110011111111111",
"11111111111010111101011111111111",
"11111111110111011011101111111111",
"11111111110111100111101111111111",
"11111111110111100111101111111111",
"11111111110111011011101111111111",
"11111111111010111101011111111111",
"11111111111001111110011111111111",
"11111111111100111100111111111111",
"11111111111111000011111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- text1 (bila) - 1001
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00011110000111100001111110000111",
"00011110000111100001111110000111",
"00011001100110011001100000011000",
"00011001100110011001100000011000",
"00011110000111100001111000000110",
"00011110000111100001111000000110",
"00011000000110011001100000000001",
"00011000000110011001100000000001",
"00011000000110011001111110011110",
"00011000000110011001111110011110",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000001100001",
"00000000000000000000000001100001",
"00000000000000000000000110011001",
"00000000000000000000000110011001",
"00000000000000000000000110011001",
"00000000000000000000000110011001",
"00000000000000000000000110011001",
"00000000000000000000000110011001",
"00000000000000000000000001100001",
"00000000000000000000000001100001",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- Dalsi obrazek (tenka trubka ke startovni ohnuta 1=modra) - 1010
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000001111100000000000000",
"00000000000011111100000000000000",
"11111111111111111000000000000000",
"11111111111111111000000000000000",
"11111111111111110000000000000000",
"11111111111111000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- Dalsi obrazek (tenka trubka ke startovni rovna 1=modra) - 1011
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- Dalsi obrazek (cihla 1=cervena) - 1100
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"00000000000000000000000000000000",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"00000000000000000000000000000000",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"00000000000000000000000000000000",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"00000000000000000000000000000000",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"00000000000000000000000000000000",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"00000000000000000000000000000000",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"00000000000000000000000000000000",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"00000000000000000000000000000000",
-- text2 (bila) - 1101
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000011000000000011000",
"00000000000000011000000000011000",
"10000111100000011000011110011000",
"10000111100000011000011110011000",
"00011000000000000001100000000000",
"00011000000000000001100000000000",
"00000110000000000000011000000000",
"00000110000000000000011000000000",
"10000001100000000000000110000000",
"10000001100000000000000110000000",
"00011110000000000001111000000000",
"00011110000000000001111000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11100001100110011000011000011001",
"11100001100110011000011000011001",
"10011001100110011001100110011001",
"10011001100110011001100110011001",
"11100001100110011001100110011001",
"11100001100110011001100110011001",
"10011000011000011001100110011001",
"10011000011000011001100110011001",
"11100000011000011000011000000110",
"11100000011000011000011000000110",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- text3 (bila) - 1110
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00011111100001100000000001111001",
"00011111100001100000000001111001",
"00000110000110011000000110000000",
"00000110000110011000000110000000",
"00000110000110011000000001100000",
"00000110000110011000000001100000",
"00000110000110011000000000011000",
"00000110000110011000000000011000",
"00000110000001100000000111100000",
"00000110000001100000000111100000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000111100110000001100110000000",
"00000111100110000001100110000000",
"00011000000110000001100110000000",
"00011000000110000001100110000000",
"00000110000110000000011000000000",
"00000110000110000000011000000000",
"00000001100110000000011000000000",
"00000001100110000000011000000000",
"00011110000111111000011000011000",
"00011110000111111000011000011000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- text4 (bila) - 1111
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11111000011000011110000111111000",
"11111000011000011110000111111000",
"01100001100110011001100001100000",
"01100001100110011001100001100000",
"01100001100110011110000001100000",
"01100001100110011110000001100000",
"01100001111110011001100001100000",
"01100001111110011001100001100000",
"01100001100110011001100001100000",
"01100001100110011001100001100000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00011000000000000000000000000000",
"00011000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
others => (others => '0')
);
begin
process (CLK)
begin
if (rising_edge(CLK)) then
ROM_DOUT <= ROM(to_integer(unsigned(ROM_ADDR)));
end if;
end process;
end FULL;
|
mit
|
06957152190d12fccf7bcd2fbf27987c
| 0.710851 | 8.657699 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2495.vhd
| 4 | 2,070 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2495.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n02i02495ent IS
END c07s03b03x00p04n02i02495ent;
ARCHITECTURE c07s03b03x00p04n02i02495arch OF c07s03b03x00p04n02i02495ent IS
BEGIN
TESTING: PROCESS
function check (x:integer; y:boolean; z1:real; z2:real:= 1.3)
return boolean is
begin
if y then
return true;
end if;
return false;
end;
variable p: integer := 3;
variable q: boolean := true;
variable s: boolean;
variable r: real;
BEGIN
s := check (p, q, r); -- No_failure_here
assert NOT( s=true )
report "***PASSED TEST: c07s03b03x00p04n02i02495"
severity NOTE;
assert ( s=true )
report "***FAILED TEST: c07s03b03x00p04n02i02495 - The actual parameter can be specified explicitly by an association element in the association list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n02i02495arch;
|
gpl-2.0
|
5d2da763fea8eb6f75034e36bbf35aec
| 0.658454 | 3.696429 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/bug20549/tb.vhdl
| 3 | 1,323 |
-- This testbench fails with GHDL 0.29 and with GHDL svn_2013-02-13.
library ieee;
use ieee.std_logic_1164.all;
entity clkgen is
-- NOTE: Removing the default value makes the testbench work as expected.
port ( b: out std_ulogic := '0' );
end entity;
architecture arch of clkgen is
signal a: std_ulogic;
begin
a <= '0', '1' after 10 ns, '0' after 20 ns;
b <= a;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity tb is
end entity;
architecture arch of tb is
-- NOTE: Declaring C as std_ulogic makes the testbench work as expected.
signal c: std_logic;
begin
u0: entity work.clkgen port map ( b => c );
process
begin
wait for 1 ns;
if c = '0' then
report "good: C is '0' as expected";
else
-- This fails with GHDL 0.29.
report "BAD: C is not '0'" severity failure;
end if;
wait until c = '1' for 50 ns;
-- This is ok with GHDL 0.29.
assert c = '1' severity failure;
wait until c = '0' for 50 ns;
if c = '0' then
report "good: C is '0' as expected";
else
-- This fails with GHDL 0.29.
report "BAD: C is not '0'" severity failure;
end if;
wait;
end process;
end architecture;
|
gpl-2.0
|
0309c3d004c481e2c62e17f28666f2b9
| 0.573696 | 3.585366 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/math_complex-body.vhdl
| 4 | 52,743 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_COMPLEX package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common COMPLEX
-- : constants and common COMPLEX mathematical functions and
-- : operators.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use WORK.MATH_REAL.all;
package body MATH_COMPLEX is
--
-- Equality and Inequality Operators for COMPLEX_POLAR
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return TRUE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return TRUE;
end if;
return FALSE;
end function "=";
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return FALSE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return FALSE;
end if;
return TRUE;
end function "/=";
--
-- Other Functions Start Here
--
function CMPLX(X: in REAL; Y: in REAL := 0.0 ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(X, Y);
end function CMPLX;
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Check if already a principal value
if ( X > -MATH_PI and X <= MATH_PI ) then
return PRINCIPAL_VALUE'(X);
end if;
-- Get principal value
TEMP := X;
while ( TEMP <= -MATH_PI ) loop
TEMP := TEMP + MATH_2_PI;
end loop;
while (TEMP > MATH_PI ) loop
TEMP := TEMP - MATH_2_PI;
end loop;
return PRINCIPAL_VALUE'(TEMP);
end function GET_PRINCIPAL_VALUE;
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.IM > 0.0 ) then
return COMPLEX_POLAR'(Z.IM, MATH_PI_OVER_2);
else
return COMPLEX_POLAR'(-Z.IM, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.RE > 0.0 ) then
return COMPLEX_POLAR'(Z.RE, 0.0);
else
return COMPLEX_POLAR'(-Z.RE, MATH_PI);
end if;
end if;
-- Get principal value for general case
TEMP := ARCTAN(Z.IM, Z.RE);
return COMPLEX_POLAR'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM),
GET_PRINCIPAL_VALUE(TEMP));
end function COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns MATH_CZERO on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in POLAR_TO_COMPLEX(Z)"
severity ERROR;
return MATH_CZERO;
end if;
-- Get value for general case
return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
end function POLAR_TO_COMPLEX;
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
begin
-- Get value for general case
return POSITIVE_REAL'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM));
end function "ABS";
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = Z.MAG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ABS(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.MAG;
end function "ABS";
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = ARCTAN(Z.IM, Z.RE)
variable ZTEMP : COMPLEX_POLAR;
begin
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
return ZTEMP.ARG;
end function ARG;
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = Z.ARG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ARG(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.ARG;
end function ARG;
function "-" (Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns -x -jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(-Z.RE, -Z.IM);
end function "-";
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (Z.MAG, Z.ARG + MATH_PI)
-- b) Returns Z on error
variable TEMP: REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in -(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
TEMP := REAL'(Z.ARG) + MATH_PI;
return COMPLEX_POLAR'(Z.MAG, GET_PRINCIPAL_VALUE(TEMP));
end function "-";
function CONJ (Z: in COMPLEX) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns x - jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(Z.RE, -Z.IM);
end function CONJ;
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX conjugate (Z.MAG, -Z.ARG)
-- b) Returns Z on error
--
variable TEMP: PRINCIPAL_VALUE;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in CONJ(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
if ( Z.ARG = MATH_PI or Z.ARG = 0.0 ) then
TEMP := Z.ARG;
else
TEMP := -Z.ARG;
end if;
return COMPLEX_POLAR'(Z.MAG, TEMP);
end function CONJ;
function SQRT(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable ZTEMP : COMPLEX_POLAR;
variable ZOUT : COMPLEX;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CZERO;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TMAG := SQRT(ZTEMP.MAG);
TARG := 0.5*ZTEMP.ARG;
if ( COS(TARG) > 0.0 ) then
ZOUT.RE := TMAG*COS(TARG);
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
if ( COS(TARG) < 0.0 ) then
ZOUT.RE := TMAG*COS(TARG + MATH_PI);
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end if;
if ( SIN(TARG) > 0.0 ) then
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end function SQRT;
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZOUT : COMPLEX_POLAR;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SQRT(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return Z;
end if;
-- Get principal value for general case
TMAG := SQRT(Z.MAG);
TARG := 0.5*Z.ARG;
ZOUT.MAG := POSITIVE_REAL'(TMAG);
if ( COS(TARG) < 0.0 ) then
TARG := TARG + MATH_PI;
end if;
if ( (COS(TARG) = 0.0) and (SIN(TARG) < 0.0) ) then
TARG := TARG + MATH_PI;
end if;
ZOUT.ARG := GET_PRINCIPAL_VALUE(TARG);
return ZOUT;
end function SQRT;
function EXP(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 0.0 ) then
if ( Z.IM = MATH_PI or Z.IM = -MATH_PI ) then
return COMPLEX'(-1.0, 0.0);
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return COMPLEX'(0.0, -1.0);
end if;
end if;
-- Get value for general case
TEMP := EXP(Z.RE);
return COMPLEX'(TEMP*COS(Z.IM), TEMP*SIN(Z.IM));
end function EXP;
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZTEMP : COMPLEX;
variable temp: REAL;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in EXP(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and (Z.ARG = MATH_PI_OVER_2 or
Z.ARG = -MATH_PI_OVER_2 )) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 ) then
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get principal value for general case
ZTEMP := POLAR_TO_COMPLEX(Z);
ZOUT.MAG := POSITIVE_REAL'(EXP(ZTEMP.RE));
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZTEMP.IM);
return ZOUT;
end function EXP;
function LOG(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = -1.0 ) then
return COMPLEX'(0.0, MATH_PI);
end if;
if ( Z.RE = MATH_E ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
if ( Z.RE = 0.0 ) then
if (Z.IM = 1.0) then
return COMPLEX'(0.0, MATH_PI_OVER_2);
end if;
if (Z.IM = -1.0) then
return COMPLEX'(0.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, ZTEMP.ARG);
end function LOG;
function LOG2(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 2.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG2_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG2_OF_E*ZTEMP.ARG);
end function LOG2;
function LOG10(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 10.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG10_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG10_OF_E*ZTEMP.ARG);
end function LOG10;
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 ) then
if ( Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2);
end if;
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.MAG = MATH_E and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG);
ZTEMP.IM := Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG;
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 2.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG2_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG2_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG2;
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 10.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG10_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG10_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG10;
function LOG(Z: in COMPLEX; BASE: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMPRE : REAL;
variable TEMPIM : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = BASE ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMPRE := LOG(ZTEMP.MAG, BASE);
TEMPIM := ZTEMP.ARG/LOG(BASE);
return COMPLEX'(TEMPRE, TEMPIM);
end function LOG;
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = BASE and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG, BASE);
ZTEMP.IM := Z.ARG/LOG(BASE);
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG;
function SIN(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 or Z.RE = MATH_PI) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(SIN(Z.RE)*COSH(Z.IM), COS(Z.RE)*SINH(Z.IM));
end function SIN;
function SIN(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SIN(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SIN(Z1.RE)*COSH(Z1.IM), COS(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function SIN;
function COS(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = MATH_PI_OVER_2 or Z.RE = -MATH_PI_OVER_2) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COS(Z.RE)*COSH(Z.IM), -SIN(Z.RE)*SINH(Z.IM));
end function COS;
function COS(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COS(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COS(Z1.RE)*COSH(Z1.IM), -SIN(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function COS;
function SINH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 or Z.IM = MATH_PI ) then
return MATH_CZERO;
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return -MATH_CBASE_J;
end if;
end if;
-- Get value for general case
return COMPLEX'(SINH(Z.RE)*COS(Z.IM), COSH(Z.RE)*SIN(Z.IM));
end function SINH;
function SINH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SINH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SINH(Z1.RE)*COS(Z1.IM), COSH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function SINH;
function COSH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI ) then
return -MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI_OVER_2 or Z.IM = -MATH_PI_OVER_2 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COSH(Z.RE)*COS(Z.IM), SINH(Z.RE)*SIN(Z.IM));
end function COSH;
function COSH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COSH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COSH(Z1.RE)*COS(Z1.IM), SINH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function COSH;
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R.RE, L.IM + R.IM);
end function "+";
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L + R.RE, R.IM);
end function "+";
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R, L.IM);
end function "+";
function "+" (L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + ZR.RE, ZL.IM +ZR.IM));
return ZOUT;
end function "+";
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L + ZR.RE, ZR.IM));
return ZOUT;
end function "+";
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + R, ZL.IM));
return ZOUT;
end function "+";
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R.RE, L.IM - R.IM);
end function "-";
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L - R.RE, -1.0 * R.IM);
end function "-";
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R, L.IM);
end function "-";
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - ZR.RE, ZL.IM -ZR.IM));
return ZOUT;
end function "-";
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L - ZR.RE, -1.0*ZR.IM));
return ZOUT;
end function "-";
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - R, ZL.IM));
return ZOUT;
end function "-";
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R.RE - L.IM * R.IM, L.RE * R.IM + L.IM * R.RE);
end function "*";
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L * R.RE, L * R.IM);
end function "*";
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R, L.IM * R);
end function "*";
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + R.ARG);
return ZOUT;
end function "*";
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if ( L < 0.0 ) then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG + R.ARG);
return ZOUT;
end function "*";
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if ( R < 0.0 ) then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG * ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + ZR.ARG);
return ZOUT;
end function "*";
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'( (L.RE * R.RE + L.IM * R.IM) / TEMP,
(L.IM * R.RE - L.RE * R.IM) / TEMP);
end function "/";
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
TEMP := L / TEMP;
return COMPLEX'( TEMP * R.RE, -TEMP * R.IM );
end function "/";
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by 0.0"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'(L.RE / R, L.IM / R);
end function "/";
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - R.ARG);
return ZOUT;
end function "/";
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by 0.0"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if R < 0.0 then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG/ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - ZR.ARG);
return ZOUT;
end function "/";
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_P in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if L < 0.0 then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG - R.ARG);
return ZOUT;
end function "/";
end package body MATH_COMPLEX;
|
gpl-2.0
|
207a7c9028cb9abb916c2b417708b95a
| 0.475949 | 4.14744 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.d-tbDataRam.vhd
| 1 | 2,364 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
entity tbDataRam is
end tbDataRam;
architecture tb_data_ram_arch of tbDataRam is
constant DRCW_SIZE : integer := C_CTR_DRCW_SIZE;
constant ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
constant DATA_SIZE : integer := C_SYS_DATA_SIZE;
component DataRam is
generic (
DRCW_SIZE : integer := C_CTR_DRCW_SIZE; -- Data RAM Control Word: R/W
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
rst : in std_logic;
en : in std_logic;
addr : in std_logic_vector(ADDR_SIZE-1 downto 0);
din : in std_logic_vector(DATA_SIZE-1 downto 0);
dout : out std_logic_vector(DATA_SIZE-1 downto 0);
dr_cw : in std_logic_vector(DRCW_SIZE-1 downto 0)
);
end component;
signal rst : std_logic;
signal addr : std_logic_vector(ADDR_SIZE-1 downto 0):=x"00000000";
signal din : std_logic_vector(DATA_SIZE-1 downto 0);
signal dout0 : std_logic_vector(DATA_SIZE-1 downto 0);
signal dout1 : std_logic_vector(DATA_SIZE-1 downto 0);
signal dout2 : std_logic_vector(DATA_SIZE-1 downto 0);
signal ctrl0 : std_logic_vector(DRCW_SIZE-1 downto 0);
signal ctrl1 : std_logic_vector(DRCW_SIZE-1 downto 0);
signal ctrl2 : std_logic_vector(DRCW_SIZE-1 downto 0);
begin
DRAM0: DataRam
port map(rst, '1', addr, din, dout0, ctrl0);
DRAM1: DataRam
port map(rst, '1', addr, din, dout1, ctrl1);
DRAM2: DataRam
port map(rst, '1', addr, din, dout2, ctrl2);
rst <= '0', '1' after 1 ns;
ctrl0(3) <= '1', '0' after 6 ns;
ctrl1(3) <= '1', '0' after 6 ns;
ctrl2(3) <= '1', '0' after 6 ns;
ctrl0(2 downto 0) <= "000";
ctrl1(2 downto 0) <= "001";
ctrl2(2 downto 0) <= "010";
addr <= x"00000000", x"00000001" after 2 ns, x"00000002" after 3 ns, x"00000003" after 4 ns, x"00000004" after 5 ns, x"00000006" after 7 ns, x"00000007" after 8 ns, x"00000008" after 9 ns, x"00000009" after 10 ns;
din <= x"00805060", x"08010001" after 2 ns, x"12f67002" after 3 ns, x"02028003" after 4 ns, x"08900204" after 5 ns, x"34502005" after 6 ns, x"030b2003" after 7 ns, x"01034602" after 8 ns, x"0f0a4601" after 9 ns, x"04660040" after 10 ns, x"0000000a" after 11 ns;
end tb_data_ram_arch;
configuration tb_data_ram_cfg of tbDataRam is
for tb_data_ram_arch
end for;
end tb_data_ram_cfg;
|
mit
|
1c0d66668fbf8b1de68bf64d07b82da8
| 0.673435 | 2.572361 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd
| 4 | 1,664 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book:
package coeff_ram_types is
subtype coeff_ram_address is integer range 0 to 63;
end package coeff_ram_types;
use work.coeff_ram_types.all;
-- end not in book
entity coeff_ram is
port ( rd, wr : in bit; addr : in coeff_ram_address;
d_in : in real; d_out : out real );
end entity coeff_ram;
--------------------------------------------------
architecture abstract of coeff_ram is
begin
memory : process is
type coeff_array is array (coeff_ram_address) of real;
variable coeff : coeff_array;
begin
for index in coeff_ram_address loop
coeff(index) := 0.0;
end loop;
loop
wait on rd, wr, addr, d_in;
if rd = '1' then
d_out <= coeff(addr);
end if;
if wr = '1' then
coeff(addr) := d_in;
end if;
end loop;
end process memory;
end architecture abstract;
|
gpl-2.0
|
c8c1999f38fe87e5da7d95fe42b76098
| 0.659856 | 3.799087 | false | false | false | false |
mmoraless/ecc_vhdl
|
scalar_mul_serial/binaryMethod_serial_163.vhd
| 1 | 11,939 |
----------------------------------------------------------------------------|
-- Author : Miguel Morales-Sandoval Copyrights (R) |
-- Project : " Reconfigurable ECC" |
-- Organization : INAOE, Computer Science Department |
-- Date : Originally created March, 2007. |
----------------------------------------------------------------------------|
-- / o o \ This the binary method to compute |
-- / - o o - \ scalar multiplication in affine |
-- / --- o o --- \ coordinates. It uses a module that |
-- / ---- o o ---- \ implements the ECC-ADD and ECC-DOUBLE |
-- /------ o o ----- \ at the same time. The operations are |
-- / ----- o o ----- \ performed serially. This is a 163 bit |
-- / o o o o o o \ implementation. |
-- x x x |
-- x ----- x |
-- x ------- x |
-- x --------- x |
-- x --------- x |
-- ------------- |
-- _ _ _ _ ___ ___ |
-- | || \ | | / _ \ | _ || __| |
-- | || \| || |_| ||| ||||__ |
-- | || \ | || _ |||_||||__ |
-- |_||_|\__||_| |_||___||___| |
----------------------------------------------------------------------------|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity binaryMethod is
generic(
--------------------------------------------------------------
-- para la entrada y salida
CW : positive := 29; -- 29, 23, 11, 5, 7, 5 :- bits que "faltan" para ser multiplo de 32
WORD : positive := 32; -- 32, 32, 32, 32, 32, 32 :- Numero de palabra de entrada
ITR : positive := 6; -- 6, 8, 9, 9, 13, 18 :- No. de iteraciones en la máquina de estados
--------------------------------------------------------------
-- 163, 233, 277, 283, 409, 571
-- para el squarer
--------------------------------------------------------------
D : positive := 9; -- 9, 76, 14, 14, 89, 12 -- el "grado mas grande" para el polinomio en el campo m + 2
NUM2_BITS: positive := 325; -- 325, 465, 553, 565, 817, 1141 -- 2*NUMBITS -1
--------------------------------------------------------------
-- 163, 233, 277, 283, 409, 571
-- El nivel de seguridad
NUM_BITS: positive := 163
);
port(
valid_data_in :in std_logic;
valid_data_out :out std_logic;
ack_master :in std_logic;
ack_slave :out std_logic;
data_in : in std_logic_vector(WORD-1 downto 0);
data_out : out std_logic_vector(WORD-1 downto 0);
op : in std_logic; -- 0 -> Scalar multiplication, 1 -> SUM of points
clk : in std_logic;
rst : in std_logic
);
end;
------------------------------------------------------------------
architecture behave of BinaryMethod is
------------------------------------------------------------------
-- se agregaron mas estados para controlar la carga de los
-- operadores de la multiplicación escalar o de la suma
type CurrentState_type is (END_STATE, WAIT_DATA, WAIT_MORE, SEND_MORE, SEND_DATA, MODE0, WAIT_FINISH);
signal CurrentState: CurrentState_type;
------------------------------------------------------------------
signal R_X: std_logic_vector(NUM_BITS-1 downto 0); -- Registros para manterner las operaciones ADD y Double
signal R_Y: std_logic_vector(NUM_BITS-1 downto 0);
signal P_X: std_logic_vector(NUM_BITS-1 downto 0);
signal P_Y: std_logic_vector(NUM_BITS-1 downto 0);
signal counter: std_logic_vector(7 downto 0); -- Counter, indicates the number of iterations (m)
------------------------------------------------------------------
signal RstADD : std_logic; -- Interface signals for the ADD-Double module
signal ADD_X : std_logic_vector(NUM_BITS-1 downto 0);
signal ADD_Y : std_logic_vector(NUM_BITS-1 downto 0);
signal DoneADD: std_logic;
signal op_ADD: std_logic;
------------------------------------------------------------------
signal internal_regk : std_logic_vector(NUM_BITS-1 downto 0); -- Register to keep the shifth value of the scalar
signal K_SHIFT : std_logic_vector(NUM_BITS-1 downto 0); -- The combinatorial shifter for the scalar
------------------------------------------------------------------
-- Estas señales se agregaron para controlar y carga y salida de
-- valores desde/hacia el modulo KP
signal B_x_in : std_logic_vector((NUM_BITS+CW)-1 downto 0); -- 1 Registros de NUM_BITS bits para el siguiente corrimiento
signal B_X_shift : std_logic_vector((NUM_BITS+CW)-1 downto 0); -- Corrimiento combinacional
signal counter_word : std_logic_vector(4 downto 0); -- Contador para la carga del dato
signal mux_input : std_logic_vector(WORD-1 downto 0); -- Contador para la carga del dato
------------------------------------------------------------------
begin
------------------------------------------------------------------
-- The ADD module
ECC_ADD: entity ECC_add_serial_163(behave)
--Generic Map (D, NUM2_BITS, NUM_BITS)
Generic Map (NUM_BITS)
Port Map(R_X, R_Y, P_X, P_Y, clk, RstADD, op_ADD, ADD_X, ADD_Y, DoneADD);
k_shift <= internal_regk(NUM_BITS-2 downto 0) & '0'; -- Shift the scalar every time
mux_input <= data_in when currentState = WAIT_DATA else
(others => '0');
B_x_shift <= B_x_in((NUM_BITS+CW)-WORD-1 downto 0) & mux_input;
data_out <= B_x_in(NUM_BITS+CW-1 downto NUM_BITS+CW-WORD);
------------------------------------------------------------------
-- Finite state machine that implements the LEFT-TO-RIGTH
-- binary method, ADD and DOUBLING are performed serially
------------------------------------------------------------------
SCALAR_MUL_FSM: process (CLK)
Begin -- Inferencias de 6 registros de m y m+CW bits
if CLK'event and CLK = '1' then
if Rst = '1' then -- synchronous reset
R_X <= (others => '0'); -- registros internos
R_Y <= (others => '0'); -- para suma y double
P_X <= (others => '0');
P_Y <= (others => '0');
B_x_in <= (others => '0');
internal_regk <= (others => '0'); -- registro de corrimiento del escalar k
RstADD <= '0'; -- Señales de control para los bloques ADD y DOUBLE
counter_word <= (others => '0'); -- contador para capturar las palabras de entrada
counter <= (others => '0'); -- contador para la multiplicación escalar
CurrentState <= WAIT_DATA; -- El estado para esperar la primera secuencia de WORDS
ack_slave <= '0';
valid_data_out <= '0'; -- Señal de salida que habilida WORDs validos a la salida
else
case CurrentState is
----------------------------------------------------
when WAIT_DATA =>
if valid_data_in = '1' then
B_X_in <= B_x_shift;
ack_slave <= '1';
if counter_word = "00110" then -- ITR
P_X <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
elsif counter_word = "01100" then -- 2*ITR
P_Y <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
elsif counter_word = "10010" then -- 3*ITR
if op = '0' then -- multiplicación escalar
internal_regk <= B_x_in(NUM_BITS-1 downto 0); -- Lo que se leyo es el escalar, comenzar a ejecutar kP
op_ADD <= '0'; --Double
RstADD <= '1';
CurrentState <= MODE0;
else
R_X <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
end if;
elsif counter_word = "11000" then --4*ITR
R_Y <= B_X_in(NUM_BITS-1 downto 0); -- Ya tenemos los dos puntos, hacemos la suma
op_ADD <= '1'; --ADD
RstADD <= '1';
CurrentState <= MODE0;
else
CurrentState <= WAIT_MORE;
end if;
end if;
----------------------------------------------------
when WAIT_MORE => -- Espera a que el host regrese subtype señal de dato valido a cero
if valid_data_in = '0' then
ack_slave <= '0';
CurrentState <= WAIT_DATA;
Counter_word <= Counter_word + "0001";
end if;
----------------------------------------------------
when MODE0 =>
RstADD <= '0'; -- Emite el pulso al Modulo de suma y espera a que termine la operacion
CurrentState <= WAIT_FINISH;
----------------------------------------------------
when WAIT_FINISH =>
if DoneADD = '1' then -- Espera hasta que la operacion ADD termina
if op = '1' then -- solo esta suma, terminar
B_x_in <= "00000000000000000000000000000" & ADD_X;
counter_word <= (others => '0');
CurrentState <= SEND_DATA;
valid_data_out <= '1';
else
R_X <= ADD_X; -- Almacenar el resultado actual
R_Y <= ADD_Y;
if internal_regk(NUM_BITS-1) = '1' and op_ADD = '0' then-- se comienza una nueva operacion si es qu es necesario realizar una suma
op_ADD <= '1'; -- venia de una operacion doble, realiza una operacion suma
RSTADD <= '1';
CurrentState <= MODE0;
else
counter <= counter + 1; -- incrementa el counter para indicar que ya se consumio un bit del escalar
if counter = "10100010" then --162 = NUM_BITS-1, if all iterations has been performed, then the operation is compleated
B_x_in <= "00000000000000000000000000000" & ADD_X;
counter_word <= (others => '0');
valid_data_out <= '1';
CurrentState <= SEND_DATA;
else -- if not all iterations have been performed, do the following
internal_regk <= k_shift; -- update the scalar shifted
op_ADD <= '0'; -- operacion double
RstADD <= '1';
CurrentState <= MODE0;
end if;
end if;
end if;
end if;
----------------------------------------------------
when SEND_DATA => -- ya hay una palabra valida a la salida, esperar a que el host la lea
--espera el ack del receptor
if ack_master = '1' then
Counter_word <= Counter_word + "0001";
valid_data_out <= '0';
CurrentState <= SEND_MORE;
end if;
----------------------------------------------------
when SEND_MORE => -- pone una palabra valida mas
if ack_master = '0' then
if counter_word = "0110" then -- ITR = 6
B_x_in <= "00000000000000000000000000000" & ADD_Y;
valid_data_out <= '1';
CurrentState <= SEND_DATA;
elsif counter_word = "1100" then -- 2*ITR = 12
CurrentState <= END_STATE;
else
B_x_in <= B_x_shift;
valid_data_out <= '1';
CurrentState <= SEND_DATA;
end if;
end if;
when END_STATE => -- do nothing, wait until the reset signal goes to '1'
valid_data_out <= '0';
----------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
1e3c9f8c51dbb8cd3b065c647558c3fe
| 0.449116 | 3.791362 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_113.vhd
| 1 | 15,616 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- x ^113 + x ^9 + 1
entity serial_multiplier_113 is
generic (
NUM_BITS : positive := 113 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_113;
-----------------------------------------------------------
architecture behave of serial_multiplier_113 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
-- Result of the multiplication
xor_1 <= Cx_int(8) xor Cx_int(NUM_BITS-1);
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
CELL_0: ENTITY work.basic_cell(behave)
PORT MAP(Ax(0),Bx_int(NUM_BITS-1),Cx_int(NUM_BITS-1),clk,reset,Cx_int(0));
CELL_1: ENTITY work.basic_cell(behave)
PORT MAP(Ax(1),Bx_int(NUM_BITS-1),Cx_int(0),clk,reset,Cx_int(1));
CELL_2: ENTITY work.basic_cell(behave)
PORT MAP(Ax(2),Bx_int(NUM_BITS-1),Cx_int(1),clk,reset,Cx_int(2));
CELL_3: ENTITY work.basic_cell(behave)
PORT MAP(Ax(3),Bx_int(NUM_BITS-1),Cx_int(2),clk,reset,Cx_int(3));
CELL_4: ENTITY work.basic_cell(behave)
PORT MAP(Ax(4),Bx_int(NUM_BITS-1),Cx_int(3),clk,reset,Cx_int(4));
CELL_5: ENTITY work.basic_cell(behave)
PORT MAP(Ax(5),Bx_int(NUM_BITS-1),Cx_int(4),clk,reset,Cx_int(5));
CELL_6: ENTITY work.basic_cell(behave)
PORT MAP(Ax(6),Bx_int(NUM_BITS-1),Cx_int(5),clk,reset,Cx_int(6));
CELL_7: ENTITY work.basic_cell(behave)
PORT MAP(Ax(7),Bx_int(NUM_BITS-1),Cx_int(6),clk,reset,Cx_int(7));
CELL_8: ENTITY work.basic_cell(behave)
PORT MAP(Ax(8),Bx_int(NUM_BITS-1),Cx_int(7),clk,reset,Cx_int(8));
CELL_9: ENTITY work.basic_cell(behave)
PORT MAP(Ax(9),Bx_int(NUM_BITS-1),xor_1,clk,reset,Cx_int(9));
CELL_10: ENTITY work.basic_cell(behave)
PORT MAP(Ax(10),Bx_int(NUM_BITS-1),Cx_int(9),clk,reset,Cx_int(10));
CELL_11: ENTITY work.basic_cell(behave)
PORT MAP(Ax(11),Bx_int(NUM_BITS-1),Cx_int(10),clk,reset,Cx_int(11));
CELL_12: ENTITY work.basic_cell(behave)
PORT MAP(Ax(12),Bx_int(NUM_BITS-1),Cx_int(11),clk,reset,Cx_int(12));
CELL_13: ENTITY work.basic_cell(behave)
PORT MAP(Ax(13),Bx_int(NUM_BITS-1),Cx_int(12),clk,reset,Cx_int(13));
CELL_14: ENTITY work.basic_cell(behave)
PORT MAP(Ax(14),Bx_int(NUM_BITS-1),Cx_int(13),clk,reset,Cx_int(14));
CELL_15: ENTITY work.basic_cell(behave)
PORT MAP(Ax(15),Bx_int(NUM_BITS-1),Cx_int(14),clk,reset,Cx_int(15));
CELL_16: ENTITY work.basic_cell(behave)
PORT MAP(Ax(16),Bx_int(NUM_BITS-1),Cx_int(15),clk,reset,Cx_int(16));
CELL_17: ENTITY work.basic_cell(behave)
PORT MAP(Ax(17),Bx_int(NUM_BITS-1),Cx_int(16),clk,reset,Cx_int(17));
CELL_18: ENTITY work.basic_cell(behave)
PORT MAP(Ax(18),Bx_int(NUM_BITS-1),Cx_int(17),clk,reset,Cx_int(18));
CELL_19: ENTITY work.basic_cell(behave)
PORT MAP(Ax(19),Bx_int(NUM_BITS-1),Cx_int(18),clk,reset,Cx_int(19));
CELL_20: ENTITY work.basic_cell(behave)
PORT MAP(Ax(20),Bx_int(NUM_BITS-1),Cx_int(19),clk,reset,Cx_int(20));
CELL_21: ENTITY work.basic_cell(behave)
PORT MAP(Ax(21),Bx_int(NUM_BITS-1),Cx_int(20),clk,reset,Cx_int(21));
CELL_22: ENTITY work.basic_cell(behave)
PORT MAP(Ax(22),Bx_int(NUM_BITS-1),Cx_int(21),clk,reset,Cx_int(22));
CELL_23: ENTITY work.basic_cell(behave)
PORT MAP(Ax(23),Bx_int(NUM_BITS-1),Cx_int(22),clk,reset,Cx_int(23));
CELL_24: ENTITY work.basic_cell(behave)
PORT MAP(Ax(24),Bx_int(NUM_BITS-1),Cx_int(23),clk,reset,Cx_int(24));
CELL_25: ENTITY work.basic_cell(behave)
PORT MAP(Ax(25),Bx_int(NUM_BITS-1),Cx_int(24),clk,reset,Cx_int(25));
CELL_26: ENTITY work.basic_cell(behave)
PORT MAP(Ax(26),Bx_int(NUM_BITS-1),Cx_int(25),clk,reset,Cx_int(26));
CELL_27: ENTITY work.basic_cell(behave)
PORT MAP(Ax(27),Bx_int(NUM_BITS-1),Cx_int(26),clk,reset,Cx_int(27));
CELL_28: ENTITY work.basic_cell(behave)
PORT MAP(Ax(28),Bx_int(NUM_BITS-1),Cx_int(27),clk,reset,Cx_int(28));
CELL_29: ENTITY work.basic_cell(behave)
PORT MAP(Ax(29),Bx_int(NUM_BITS-1),Cx_int(28),clk,reset,Cx_int(29));
CELL_30: ENTITY work.basic_cell(behave)
PORT MAP(Ax(30),Bx_int(NUM_BITS-1),Cx_int(29),clk,reset,Cx_int(30));
CELL_31: ENTITY work.basic_cell(behave)
PORT MAP(Ax(31),Bx_int(NUM_BITS-1),Cx_int(30),clk,reset,Cx_int(31));
CELL_32: ENTITY work.basic_cell(behave)
PORT MAP(Ax(32),Bx_int(NUM_BITS-1),Cx_int(31),clk,reset,Cx_int(32));
CELL_33: ENTITY work.basic_cell(behave)
PORT MAP(Ax(33),Bx_int(NUM_BITS-1),Cx_int(32),clk,reset,Cx_int(33));
CELL_34: ENTITY work.basic_cell(behave)
PORT MAP(Ax(34),Bx_int(NUM_BITS-1),Cx_int(33),clk,reset,Cx_int(34));
CELL_35: ENTITY work.basic_cell(behave)
PORT MAP(Ax(35),Bx_int(NUM_BITS-1),Cx_int(34),clk,reset,Cx_int(35));
CELL_36: ENTITY work.basic_cell(behave)
PORT MAP(Ax(36),Bx_int(NUM_BITS-1),Cx_int(35),clk,reset,Cx_int(36));
CELL_37: ENTITY work.basic_cell(behave)
PORT MAP(Ax(37),Bx_int(NUM_BITS-1),Cx_int(36),clk,reset,Cx_int(37));
CELL_38: ENTITY work.basic_cell(behave)
PORT MAP(Ax(38),Bx_int(NUM_BITS-1),Cx_int(37),clk,reset,Cx_int(38));
CELL_39: ENTITY work.basic_cell(behave)
PORT MAP(Ax(39),Bx_int(NUM_BITS-1),Cx_int(38),clk,reset,Cx_int(39));
CELL_40: ENTITY work.basic_cell(behave)
PORT MAP(Ax(40),Bx_int(NUM_BITS-1),Cx_int(39),clk,reset,Cx_int(40));
CELL_41: ENTITY work.basic_cell(behave)
PORT MAP(Ax(41),Bx_int(NUM_BITS-1),Cx_int(40),clk,reset,Cx_int(41));
CELL_42: ENTITY work.basic_cell(behave)
PORT MAP(Ax(42),Bx_int(NUM_BITS-1),Cx_int(41),clk,reset,Cx_int(42));
CELL_43: ENTITY work.basic_cell(behave)
PORT MAP(Ax(43),Bx_int(NUM_BITS-1),Cx_int(42),clk,reset,Cx_int(43));
CELL_44: ENTITY work.basic_cell(behave)
PORT MAP(Ax(44),Bx_int(NUM_BITS-1),Cx_int(43),clk,reset,Cx_int(44));
CELL_45: ENTITY work.basic_cell(behave)
PORT MAP(Ax(45),Bx_int(NUM_BITS-1),Cx_int(44),clk,reset,Cx_int(45));
CELL_46: ENTITY work.basic_cell(behave)
PORT MAP(Ax(46),Bx_int(NUM_BITS-1),Cx_int(45),clk,reset,Cx_int(46));
CELL_47: ENTITY work.basic_cell(behave)
PORT MAP(Ax(47),Bx_int(NUM_BITS-1),Cx_int(46),clk,reset,Cx_int(47));
CELL_48: ENTITY work.basic_cell(behave)
PORT MAP(Ax(48),Bx_int(NUM_BITS-1),Cx_int(47),clk,reset,Cx_int(48));
CELL_49: ENTITY work.basic_cell(behave)
PORT MAP(Ax(49),Bx_int(NUM_BITS-1),Cx_int(48),clk,reset,Cx_int(49));
CELL_50: ENTITY work.basic_cell(behave)
PORT MAP(Ax(50),Bx_int(NUM_BITS-1),Cx_int(49),clk,reset,Cx_int(50));
CELL_51: ENTITY work.basic_cell(behave)
PORT MAP(Ax(51),Bx_int(NUM_BITS-1),Cx_int(50),clk,reset,Cx_int(51));
CELL_52: ENTITY work.basic_cell(behave)
PORT MAP(Ax(52),Bx_int(NUM_BITS-1),Cx_int(51),clk,reset,Cx_int(52));
CELL_53: ENTITY work.basic_cell(behave)
PORT MAP(Ax(53),Bx_int(NUM_BITS-1),Cx_int(52),clk,reset,Cx_int(53));
CELL_54: ENTITY work.basic_cell(behave)
PORT MAP(Ax(54),Bx_int(NUM_BITS-1),Cx_int(53),clk,reset,Cx_int(54));
CELL_55: ENTITY work.basic_cell(behave)
PORT MAP(Ax(55),Bx_int(NUM_BITS-1),Cx_int(54),clk,reset,Cx_int(55));
CELL_56: ENTITY work.basic_cell(behave)
PORT MAP(Ax(56),Bx_int(NUM_BITS-1),Cx_int(55),clk,reset,Cx_int(56));
CELL_57: ENTITY work.basic_cell(behave)
PORT MAP(Ax(57),Bx_int(NUM_BITS-1),Cx_int(56),clk,reset,Cx_int(57));
CELL_58: ENTITY work.basic_cell(behave)
PORT MAP(Ax(58),Bx_int(NUM_BITS-1),Cx_int(57),clk,reset,Cx_int(58));
CELL_59: ENTITY work.basic_cell(behave)
PORT MAP(Ax(59),Bx_int(NUM_BITS-1),Cx_int(58),clk,reset,Cx_int(59));
CELL_60: ENTITY work.basic_cell(behave)
PORT MAP(Ax(60),Bx_int(NUM_BITS-1),Cx_int(59),clk,reset,Cx_int(60));
CELL_61: ENTITY work.basic_cell(behave)
PORT MAP(Ax(61),Bx_int(NUM_BITS-1),Cx_int(60),clk,reset,Cx_int(61));
CELL_62: ENTITY work.basic_cell(behave)
PORT MAP(Ax(62),Bx_int(NUM_BITS-1),Cx_int(61),clk,reset,Cx_int(62));
CELL_63: ENTITY work.basic_cell(behave)
PORT MAP(Ax(63),Bx_int(NUM_BITS-1),Cx_int(62),clk,reset,Cx_int(63));
CELL_64: ENTITY work.basic_cell(behave)
PORT MAP(Ax(64),Bx_int(NUM_BITS-1),Cx_int(63),clk,reset,Cx_int(64));
CELL_65: ENTITY work.basic_cell(behave)
PORT MAP(Ax(65),Bx_int(NUM_BITS-1),Cx_int(64),clk,reset,Cx_int(65));
CELL_66: ENTITY work.basic_cell(behave)
PORT MAP(Ax(66),Bx_int(NUM_BITS-1),Cx_int(65),clk,reset,Cx_int(66));
CELL_67: ENTITY work.basic_cell(behave)
PORT MAP(Ax(67),Bx_int(NUM_BITS-1),Cx_int(66),clk,reset,Cx_int(67));
CELL_68: ENTITY work.basic_cell(behave)
PORT MAP(Ax(68),Bx_int(NUM_BITS-1),Cx_int(67),clk,reset,Cx_int(68));
CELL_69: ENTITY work.basic_cell(behave)
PORT MAP(Ax(69),Bx_int(NUM_BITS-1),Cx_int(68),clk,reset,Cx_int(69));
CELL_70: ENTITY work.basic_cell(behave)
PORT MAP(Ax(70),Bx_int(NUM_BITS-1),Cx_int(69),clk,reset,Cx_int(70));
CELL_71: ENTITY work.basic_cell(behave)
PORT MAP(Ax(71),Bx_int(NUM_BITS-1),Cx_int(70),clk,reset,Cx_int(71));
CELL_72: ENTITY work.basic_cell(behave)
PORT MAP(Ax(72),Bx_int(NUM_BITS-1),Cx_int(71),clk,reset,Cx_int(72));
CELL_73: ENTITY work.basic_cell(behave)
PORT MAP(Ax(73),Bx_int(NUM_BITS-1),Cx_int(72),clk,reset,Cx_int(73));
CELL_74: ENTITY work.basic_cell(behave)
PORT MAP(Ax(74),Bx_int(NUM_BITS-1),Cx_int(73),clk,reset,Cx_int(74));
CELL_75: ENTITY work.basic_cell(behave)
PORT MAP(Ax(75),Bx_int(NUM_BITS-1),Cx_int(74),clk,reset,Cx_int(75));
CELL_76: ENTITY work.basic_cell(behave)
PORT MAP(Ax(76),Bx_int(NUM_BITS-1),Cx_int(75),clk,reset,Cx_int(76));
CELL_77: ENTITY work.basic_cell(behave)
PORT MAP(Ax(77),Bx_int(NUM_BITS-1),Cx_int(76),clk,reset,Cx_int(77));
CELL_78: ENTITY work.basic_cell(behave)
PORT MAP(Ax(78),Bx_int(NUM_BITS-1),Cx_int(77),clk,reset,Cx_int(78));
CELL_79: ENTITY work.basic_cell(behave)
PORT MAP(Ax(79),Bx_int(NUM_BITS-1),Cx_int(78),clk,reset,Cx_int(79));
CELL_80: ENTITY work.basic_cell(behave)
PORT MAP(Ax(80),Bx_int(NUM_BITS-1),Cx_int(79),clk,reset,Cx_int(80));
CELL_81: ENTITY work.basic_cell(behave)
PORT MAP(Ax(81),Bx_int(NUM_BITS-1),Cx_int(80),clk,reset,Cx_int(81));
CELL_82: ENTITY work.basic_cell(behave)
PORT MAP(Ax(82),Bx_int(NUM_BITS-1),Cx_int(81),clk,reset,Cx_int(82));
CELL_83: ENTITY work.basic_cell(behave)
PORT MAP(Ax(83),Bx_int(NUM_BITS-1),Cx_int(82),clk,reset,Cx_int(83));
CELL_84: ENTITY work.basic_cell(behave)
PORT MAP(Ax(84),Bx_int(NUM_BITS-1),Cx_int(83),clk,reset,Cx_int(84));
CELL_85: ENTITY work.basic_cell(behave)
PORT MAP(Ax(85),Bx_int(NUM_BITS-1),Cx_int(84),clk,reset,Cx_int(85));
CELL_86: ENTITY work.basic_cell(behave)
PORT MAP(Ax(86),Bx_int(NUM_BITS-1),Cx_int(85),clk,reset,Cx_int(86));
CELL_87: ENTITY work.basic_cell(behave)
PORT MAP(Ax(87),Bx_int(NUM_BITS-1),Cx_int(86),clk,reset,Cx_int(87));
CELL_88: ENTITY work.basic_cell(behave)
PORT MAP(Ax(88),Bx_int(NUM_BITS-1),Cx_int(87),clk,reset,Cx_int(88));
CELL_89: ENTITY work.basic_cell(behave)
PORT MAP(Ax(89),Bx_int(NUM_BITS-1),Cx_int(88),clk,reset,Cx_int(89));
CELL_90: ENTITY work.basic_cell(behave)
PORT MAP(Ax(90),Bx_int(NUM_BITS-1),Cx_int(89),clk,reset,Cx_int(90));
CELL_91: ENTITY work.basic_cell(behave)
PORT MAP(Ax(91),Bx_int(NUM_BITS-1),Cx_int(90),clk,reset,Cx_int(91));
CELL_92: ENTITY work.basic_cell(behave)
PORT MAP(Ax(92),Bx_int(NUM_BITS-1),Cx_int(91),clk,reset,Cx_int(92));
CELL_93: ENTITY work.basic_cell(behave)
PORT MAP(Ax(93),Bx_int(NUM_BITS-1),Cx_int(92),clk,reset,Cx_int(93));
CELL_94: ENTITY work.basic_cell(behave)
PORT MAP(Ax(94),Bx_int(NUM_BITS-1),Cx_int(93),clk,reset,Cx_int(94));
CELL_95: ENTITY work.basic_cell(behave)
PORT MAP(Ax(95),Bx_int(NUM_BITS-1),Cx_int(94),clk,reset,Cx_int(95));
CELL_96: ENTITY work.basic_cell(behave)
PORT MAP(Ax(96),Bx_int(NUM_BITS-1),Cx_int(95),clk,reset,Cx_int(96));
CELL_97: ENTITY work.basic_cell(behave)
PORT MAP(Ax(97),Bx_int(NUM_BITS-1),Cx_int(96),clk,reset,Cx_int(97));
CELL_98: ENTITY work.basic_cell(behave)
PORT MAP(Ax(98),Bx_int(NUM_BITS-1),Cx_int(97),clk,reset,Cx_int(98));
CELL_99: ENTITY work.basic_cell(behave)
PORT MAP(Ax(99),Bx_int(NUM_BITS-1),Cx_int(98),clk,reset,Cx_int(99));
CELL_100: ENTITY work.basic_cell(behave)
PORT MAP(Ax(100),Bx_int(NUM_BITS-1),Cx_int(99),clk,reset,Cx_int(100));
CELL_101: ENTITY work.basic_cell(behave)
PORT MAP(Ax(101),Bx_int(NUM_BITS-1),Cx_int(100),clk,reset,Cx_int(101));
CELL_102: ENTITY work.basic_cell(behave)
PORT MAP(Ax(102),Bx_int(NUM_BITS-1),Cx_int(101),clk,reset,Cx_int(102));
CELL_103: ENTITY work.basic_cell(behave)
PORT MAP(Ax(103),Bx_int(NUM_BITS-1),Cx_int(102),clk,reset,Cx_int(103));
CELL_104: ENTITY work.basic_cell(behave)
PORT MAP(Ax(104),Bx_int(NUM_BITS-1),Cx_int(103),clk,reset,Cx_int(104));
CELL_105: ENTITY work.basic_cell(behave)
PORT MAP(Ax(105),Bx_int(NUM_BITS-1),Cx_int(104),clk,reset,Cx_int(105));
CELL_106: ENTITY work.basic_cell(behave)
PORT MAP(Ax(106),Bx_int(NUM_BITS-1),Cx_int(105),clk,reset,Cx_int(106));
CELL_107: ENTITY work.basic_cell(behave)
PORT MAP(Ax(107),Bx_int(NUM_BITS-1),Cx_int(106),clk,reset,Cx_int(107));
CELL_108: ENTITY work.basic_cell(behave)
PORT MAP(Ax(108),Bx_int(NUM_BITS-1),Cx_int(107),clk,reset,Cx_int(108));
CELL_109: ENTITY work.basic_cell(behave)
PORT MAP(Ax(109),Bx_int(NUM_BITS-1),Cx_int(108),clk,reset,Cx_int(109));
CELL_110: ENTITY work.basic_cell(behave)
PORT MAP(Ax(110),Bx_int(NUM_BITS-1),Cx_int(109),clk,reset,Cx_int(110));
CELL_111: ENTITY work.basic_cell(behave)
PORT MAP(Ax(111),Bx_int(NUM_BITS-1),Cx_int(110),clk,reset,Cx_int(111));
CELL_112: ENTITY work.basic_cell(behave)
PORT MAP(Ax(112),Bx_int(NUM_BITS-1),Cx_int(111),clk,reset,Cx_int(112));
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "11100000"; -- m-1 value, in this case, it is 112, be sure to set the correct value
bx_int <= bx;
cx <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
counter <= counter - 1;
if counter = "00000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
else
bx_int <= bx_shift;
end if;
when END_STATE =>
Cx <= Cx_int;
Done <= '1';
CurrentState <= NOTHING;
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
d0b71568f5daebcaaed5017b2df72395
| 0.650871 | 2.438095 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_15.vhd
| 4 | 1,913 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_15.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_15 is
end entity fg_07_15;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_07_15 is
-- code from book
procedure generate_clock ( signal clk : out std_ulogic;
constant Tperiod, Tpulse, Tphase : in time ) is
begin
wait for Tphase;
loop
clk <= '1', '0' after Tpulse;
wait for Tperiod;
end loop;
end procedure generate_clock;
-- end code from book
-- code from book (in text)
signal phi1, phi2 : std_ulogic := '0';
-- . . .
-- end code from book
begin
-- code from book (in text)
gen_phi1 : generate_clock ( phi1, Tperiod => 50 ns, Tpulse => 20 ns,
Tphase => 0 ns );
gen_phi2 : generate_clock ( phi2, Tperiod => 50 ns, Tpulse => 20 ns,
Tphase => 25 ns );
-- end code from book
end architecture test;
|
gpl-2.0
|
d6395a3a836f3dc08a4fc6fbbdc58c7b
| 0.5954 | 4.018908 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd
| 4 | 3,040 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity NMOS_transistor is
generic ( Cgs : real := 1.0e-6; -- gate to source capacitance
Cgd : real := 1.0e-6; -- gate to drain capacitance
gm : real := 5.0e-4; -- transconductance
temp : real := 1.0; -- termperature
Ro : real := 500.0e3; -- ro resistance
af : real := 1.0; -- flicker noise exponent constant
k_flicker : real := 1.0 ); -- flicker noise constant
port ( terminal gate, drain, source : electrical );
end entity NMOS_transistor;
----------------------------------------------------------------
architecture noisy of NMOS_transistor is
quantity vgs across igs through gate to source;
quantity vds across ids through drain to source;
quantity vsd across source to drain;
quantity vgd across igd through gate to drain;
constant threshold_voltage : voltage := 1.0;
constant k : real := 1.0e-5;
-- declare quantity in frequency domain for AC analysis
quantity MOS_noise_source : real noise
4.0*K*temp/Ro + -- thermal noise
k_flicker*ids**af/frequency; -- flicker noise
begin
if domain = quiescent_domain or domain = time_domain use
if vds >= 0.0 use -- transistor is forward biased
if vgs < threshold_voltage use -- cutoff region
ids == 0.0;
elsif vds > vgs - threshold_voltage use -- saturation region
ids == 0.5 * k * (vgs - threshold_voltage)**2;
else -- linear/triode region
ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
end use;
else -- transistor is reverse biased
if vgd < threshold_voltage use -- cutoff region
ids == 0.0;
elsif vsd > vgd - threshold_voltage use -- saturation region
ids == -0.5 * k * (vgd - threshold_voltage)**2;
else -- linear/triode region
ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
end use;
end use;
igs == 0.0;
igd == 0.0;
else -- noise and frequency model
igs == Cgs*vgs'dot;
igd == Cgd*vgd'dot;
ids == gm*vgs + vds/Ro + MOS_noise_source;
end use;
end architecture noisy;
|
gpl-2.0
|
65ea75f7cb14138d67031d58f7ce59ed
| 0.628618 | 3.877551 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CalcBuckParams.vhd
| 4 | 1,970 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CalcBuckParams is
end tb_CalcBuckParams;
architecture tb_CalcBuckParams of tb_CalcBuckParams is
-- Component declarations
-- Signal declarations
quantity Cmin : capacitance;
quantity freq_in : real;
quantity Lmin : inductance;
begin
-- Signal assignments
-- Component instances
src1 : entity work.src_pulse(ideal)
generic map(
initial => 25.0e3,
pulse => 200.0e3,
ti2p => 1ms,
tp2i => 1ms,
delay => 1ms,
width => 100ms,
period => 1000ms
)
port map(
output => freq_in
);
CalcBuckParams1 : entity work.CalcBuckParams_wa(ideal)
generic map(
Vripple => 100.0e-3,
Vin => 42.0,
Vout => 4.8,
Vd => 0.7,
Imin => 15.0e-3,
Resr => 50.0e-3
)
port map(
Fsw => freq_in,
Lmin => Lmin,
Cmin => Cmin
);
end tb_CalcBuckParams;
|
gpl-2.0
|
eb137212bc6148d16e36652020b67b2e
| 0.620812 | 4.01222 | false | false | false | false |
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