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nkkav/bstest-s3esk
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std_logic_textio.vhd
| 1 | 24,062 |
-- --------------------------------------------------------------------
--
-- Title : std_logic_textio
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Adapted by IEEE P1164 Working Group from
-- : source donated by Synopsys, Inc.
-- :
-- Purpose : This packages defines procedures for reading and writing
-- : standard-logic scalars and vectors in binary, hexadecimal
-- : and octal format.
-- :
-- Limitation: None.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the procedures of std_logic_textio.
-- : The std_logic_textio package body shall be
-- : considered the formal definition of the semantics of
-- : this package, except that where a procedure issues an
-- : assertion violation, the standard does not specify the
-- : required behavior in response to the erroneous condition.
-- : Tool developers may choose to implement the package body
-- : in the most efficient manner available to them.
-- :
-- --------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- --------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC);
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR);
procedure WRITE (L: inout LINE; VALUE: in STD_ULOGIC;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out STD_LOGIC_VECTOR);
procedure WRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
-- Read and Write procedures for Hex values
procedure HREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR);
procedure HWRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR);
procedure HWRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
-- Read and Write procedures for Octal values
procedure OREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR);
procedure OWRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR);
procedure OWRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
constant NBSP : character := character'val(160);
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC; GOOD: out BOOLEAN) is
variable c: character;
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l, c, readOk); -- but also exit on a bad read
exit when (readOk = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if not readOk then
good := FALSE;
else
if char_to_MVL9plus(c) = ERROR then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end if;
end READ;
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l, c, readOk);
exit when (readOk = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not readOk then
good := FALSE;
return;
end if;
if char_to_MVL9plus(c) = ERROR then
value := allU;
good := FALSE;
return;
end if;
read(l, s, readOk);
-- Bail out if there was a bad read
if not readOk then
good := FALSE;
return;
end if;
for i in 1 to value'length-1 loop
if char_to_MVL9plus(s(i)) = ERROR then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l, c);
exit when (c /= ' ') and (c /= NBSP) and (c /= HT);
end loop;
if char_to_MVL9plus(c) = ERROR then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l, c);
exit when (c /= ' ') and (c /= NBSP) and (c /= HT);
end loop;
if char_to_MVL9plus(c) = ERROR then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if char_to_MVL9plus(s(i)) = ERROR then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE (L: inout LINE; VALUE: in STD_ULOGIC;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ (L: inout LINE; VALUE: out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
procedure Char2QuadBits (C: Character;
RESULT: out std_ulogic_vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' | 'a' => result := x"A"; good := TRUE;
when 'B' | 'b' => result := x"B"; good := TRUE;
when 'C' | 'c' => result := x"C"; good := TRUE;
when 'D' | 'd' => result := x"D"; good := TRUE;
when 'E' | 'e' => result := x"E"; good := TRUE;
when 'F' | 'f' => result := x"F"; good := TRUE;
when 'Z' => result := "ZZZZ"; good := TRUE;
when 'X' => result := "XXXX"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable sv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l, c, ok);
exit when (ok = FALSE) or (c = LF) or (c = CR) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
-- exit when (ok = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
good := FALSE;
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := sv;
end HREAD;
procedure HREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable sv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l, c, ok);
exit when (ok = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
assert FALSE
report "HREAD Error: Failed skipping white space";
return;
end if;
Char2QuadBits(c, sv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), sv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := sv;
end HREAD;
procedure HWRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
variable quad: std_ulogic_vector(0 to 3);
constant ne: integer := value'length/4;
variable sv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := To_X01Z(sv(4*i to 4*i+3));
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
when others =>
if (quad = "ZZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
procedure Char2TriBits (C: Character;
RESULT: out std_ulogic_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when 'Z' => result := "ZZZ"; good := TRUE;
when 'X' => result := "XXX"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable sv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l, c, ok);
exit when (ok = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
good := FALSE;
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := sv;
end OREAD;
procedure OREAD (L: inout LINE; VALUE: out STD_ULOGIC_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable sv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l, c, ok);
exit when (ok = FALSE) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
-- Bail out if there was a bad read
if not ok then
assert FALSE
report "OREAD Error: Failed skipping white space";
return;
end if;
Char2TriBits(c, sv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), sv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := sv;
end OREAD;
procedure OWRITE (L: inout LINE; VALUE: in STD_ULOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
variable tri: std_ulogic_vector(0 to 2);
constant ne: integer := value'length/3;
variable sv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := To_X01Z(sv(3*i to 3*i+2));
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
when others =>
if (tri = "ZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
begin
HWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD (L: inout LINE; VALUE: out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE (L: inout LINE; VALUE: in STD_LOGIC_VECTOR;
JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
end STD_LOGIC_TEXTIO;
|
bsd-3-clause
|
d37aa8b62d3b94e7d80efcd8cc252550
| 0.473236 | 3.975219 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/Mibench/firmware/outputs/ram_image.vhd
| 1 | 181,522 |
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafaf2708000c4034241400ac373c343c343c373c00100010",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f000cafafafafafafafafafafafafafafafaf",
INIT_02 => X"afafafaf03af270003278f0303af2740034034278f8f8f8f8f8f8f8f8f8f8f8f",
INIT_03 => X"8faf0030008faf008c343caf0014248faf00008faf008c343c0014248c3cac3c",
INIT_04 => X"afafaf00008f8faf00008faf00008faf008c343caf30008faf008c343c001000",
INIT_05 => X"af240014008f0000008faf00008c0024003c8faf30008c0024003c8fafaf0008",
INIT_06 => X"0014008f001428008faf24008f0008ac008f3caf00008f8faf008c3caf00008f",
INIT_07 => X"008f0000008faf00343c8faf008c343caf24008fac008f3caf003c8faf008c3c",
INIT_08 => X"3caf24008f0008af24008f001400348faf00008faf008c343cac008f343caf00",
INIT_09 => X"0000000000000008ac243cac008f343caf00008f0000008faf30008faf008c34",
INIT_0A => X"0801010101010101010000000000000000000000000000000000000000000000",
INIT_0B => X"3a3938080706050403022a29280d0c0b0a0908071a19180302010f0e0d0c0ac0",
INIT_0C => X"0d0c6a6968080706050403025a59580d0c0b0a0908074a49480302010f0e0d0c",
INIT_0D => X"000000000b0a09080706050403028a89880d0c0b0a0908077a79780302010f0e",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"aaa9a8a7a6a5a4a3a2a1bd000000880884608580bd1da50584049c1c00000000",
INIT_01 => X"aeadacabaaa9a8a7a6a5a4a3a2a10000bfb9b8b7b6b5b4b3b2b1b0afaeadacab",
INIT_02 => X"c0c0c5c4a0bebd00e0bdbec0a0bebd9a601b1abdbfb9b8b7b6b5b4b3b2b1b0af",
INIT_03 => X"c2c2024200828200424202c0006202c3c2020082820042420200620243024002",
INIT_04 => X"c0c0c26200c2c3c20200c2c20200828200424202c24200828200424202004000",
INIT_05 => X"c202006200c2400200c2c202004282620203c2c242004282620203c2c0c00000",
INIT_06 => X"004000c200404200c2c24200c200006200c203c24300c2c3c2004202c20200c2",
INIT_07 => X"0082400200c282624202838200424202c24200c26200c203c26202c3c2004202",
INIT_08 => X"02c24200c20000c24200c200406202c3c2020082820042420262008243028262",
INIT_09 => X"0000000000000000620203620082430282620082400200c28242008282004242",
INIT_0A => X"0101010101010101010000000000000000000000000000000000000000000000",
INIT_0B => X"010101282726252423220101011d1c1b1a1918170101011312110f0e0d0c01a8",
INIT_0C => X"4d4c010101484746454443420101013d3c3b3a3938370101013332312f2e2d2c",
INIT_0D => X"000000006b6a69686766656463620101015d5c5b5a5958570101015352514f4e",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000ff000000600000ff18001f0018001800180000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"00000000f000ff00000000e8f000ff6000700000000000000000000000000000",
INIT_03 => X"000012ff00000000000010000000080000140000000000001000ff00001f0018",
INIT_04 => X"000000100000000014000000140000000000001000ff00000000000010000000",
INIT_05 => X"0000000000001812000000120000100520000000000000100520000000000000",
INIT_06 => X"0000000000ff0000000000000000000000001000100000000000001000140000",
INIT_07 => X"000018120000001000ff00000000001000ff0000000000100010000000000010",
INIT_08 => X"1000010000000100010000000010fe0000140000000000001000000000100010",
INIT_09 => X"00000000000000000000180000000010001000001814000000ff000000000000",
INIT_0A => X"0101010101010101010000000000000000000000000000000000000000000000",
INIT_0B => X"010101282726252423220101011d1c1b1a1918170101011312110f0e0d0c0101",
INIT_0C => X"4d4c010101484746454443420101013d3c3b3a3938370101013332312f2e2d2c",
INIT_0D => X"000000006b6a69686766656463620101015d5c5b5a5958570101015352514f4e",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"2c2824201c181410040090140059000104fd2a00f80004000000000000120003",
INIT_01 => X"3c3a34302c2824201c181410040000516c6864605c5854504c4844403c3a3430",
INIT_02 => X"04103c382134c800080804212104f800080001706c6864605c5854504c484440",
INIT_03 => X"0000020000000000001c000000c2001414020000000000140000fc0100000000",
INIT_04 => X"10241821001c202000002c1c02000000000028002cff0000000000240000b300",
INIT_05 => X"24010016000c210200180c020000215c80001008ff0000215c800010080c00d7",
INIT_06 => X"000d002400c76500101001001000dc0000280028250028082800000008000008",
INIT_07 => X"0000210000000024ffff000000001c0000ff0000000028002825042828000000",
INIT_08 => X"0004000004001f0401000400072aff040402000000000020000000001c000025",
INIT_09 => X"00000000000000600001000000002000002500002100000400ff000000000020",
INIT_0A => X"1004040404040404040000000000000000000000000000000000000000000000",
INIT_0B => X"0401100110040110040104011010040110040104040110100401100401100401",
INIT_0C => X"0401040110041004011004010401101004011004011004011004011004011004",
INIT_0D => X"0000000010040110040110040110040110040110040110040401100110040110",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
mit
|
2aefc126446bd96a36f8a9225b1fb2a5
| 0.842906 | 6.72852 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_28.vhd
| 4 | 1,930 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_28.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity reg is
port ( d : in bit_vector(7 downto 0);
q : out bit_vector(7 downto 0);
clk : in bit );
end entity reg;
--------------------------------------------------
-- not in book
entity microprocessor is
end entity microprocessor;
-- end not in book
architecture RTL of microprocessor is
signal interrupt_req : bit;
signal interrupt_level : bit_vector(2 downto 0);
signal carry_flag, negative_flag, overflow_flag, zero_flag : bit;
signal program_status : bit_vector(7 downto 0);
signal clk_PSR : bit;
-- . . .
begin
PSR : entity work.reg
port map ( d(7) => interrupt_req,
d(6 downto 4) => interrupt_level,
d(3) => carry_flag, d(2) => negative_flag,
d(1) => overflow_flag, d(0) => zero_flag,
q => program_status,
clk => clk_PSR );
-- . . .
end architecture RTL;
|
gpl-2.0
|
d9c3d706ab268971f70d2257dd0112ff
| 0.586528 | 3.930754 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/MAIA/poly_grade.vhd
| 1 | 3,706 |
----------------------------------------------------------------------------------------------------
-- poly_grade.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: It calculates the grade of the input polynomial
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
----------------------------------------------------------------------------------------------------
entity grade is
port(
rst : in std_logic;
clk : in std_logic;
a : in std_logic_vector(163 downto 0);
done : out std_logic;
c : out std_logic_vector(7 downto 0)
);
end grade;
----------------------------------------------------------------------------------------------------
architecture grade of grade is
----------------------------------------------------------------------------------------------------
signal counter : std_logic_vector (7 downto 0); -- keeps the track of the grade
signal a_int : std_logic_vector(163 downto 0); -- register and shifter for the input a
signal a_shift : std_logic_vector(163 downto 0);
----------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, E0); -- the finite stte machine
signal State: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
c <= counter; -- Output
a_shift <= a_int(162 downto 0) & '0'; -- shift to lefts of the internal register for the input
----------------------------------------------------------------------------------------------------
-- Finite state machine for computing the grade of the input polynomial
----------------------------------------------------------------------------------------------------
GRADE_FST : process(clk)
begin
if CLK'event and CLK = '1' then
if (rst = '1')then -- synchronous resert signal, the input needs to be valid at the moment
a_int <= a;
counter <= "10100011"; -- NUM_BITS , in this case it is 163
Done <= '0';
State <= E0;
else
case State is
------------------------------------------------------------------------------
when E0 => -- The operation concludes when it founds the most significant bit of the input
if a_int(163) = '1' or counter = "00000000" then
done <= '1';
State <= END_STATE;
else
counter <= counter - 1;
a_int <= a_shift; -- Check out if the next bit of the input is '1'
end if;
------------------------------------------------------------------------------
when END_STATE => -- Do nothing, just wait the reset signal again
State <= END_STATE;
------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end;
|
gpl-3.0
|
5d89e8895c2dde2b2890c991bcdbff8c
| 0.348354 | 5.286733 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2149.vhd
| 4 | 2,231 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2149.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02149ent IS
END c07s02b04x00p21n01i02149ent;
ARCHITECTURE c07s02b04x00p21n01i02149arch OF c07s02b04x00p21n01i02149ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_5 is real_v (1 to 5);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : real_5;
variable l_operand : real := 12.345;
variable r_operand : real_4 := (12.345, -67.890, 12.345, -67.890);
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (12.345, 12.345, -67.890, 12.345, -67.890)) and (result(1) = 12.345))
report "***PASSED TEST: c07s02b04x00p21n01i02149"
severity NOTE;
assert ((result = (12.345, 12.345, -67.890, 12.345, -67.890)) and (result(1) = 12.345))
report "***FAILED TEST: c07s02b04x00p21n01i02149 - Concatenation of element and REAL array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02149arch;
|
gpl-2.0
|
aaf97803bc56c34c9f611f25fa19130d
| 0.654415 | 3.432308 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/bug03/wor_std.vhdl
| 3 | 3,481 |
library ieee;
use ieee.std_logic_1164.all;
package wor_std is
subtype rddata_o_range is integer range 3 downto 0;
type rddata_o_array is array (natural range <>) of std_logic_vector(rddata_o_range);
function rddata_o_resolv (s: rddata_o_array) return std_logic_vector;
function wor_trior (s: std_logic_vector) return std_logic;
function slv_image(inp: std_logic_vector) return string;
end package;
package body wor_std is
type wor_table is array (X01Z, X01Z) of std_ulogic;
constant resolution_table : wor_table := (
-- --------------------------------
-- | X 0 1 Z | |
-- --------------------------------
('X', 'X', '1', 'X'), -- | X |
('X', '0', '1', '0'), -- | 0 |
('1', '1', '1', '1'), -- | 1 |
('X', '0', '1', 'Z') -- | Z |
);
function wor_trior ( s: std_logic_vector ) return std_logic is
variable result: std_logic := 'Z';
begin
if (s'length = 1) then return (To_X01Z(s(s'low)));
else
for i in s'range loop
result := resolution_table(result, To_X01Z(s(i)));
end loop;
end if;
return result;
end wor_trior;
function rddata_o_resolv (s: rddata_o_array) return std_logic_vector is
variable wor: std_logic_vector (s'range);
variable result: std_logic_vector (rddata_o_range);
begin
for i in result'range loop
for j in s'range loop
wor(j) := s(j)(i);
end loop;
-- report "wor = " & slv_image(wor);
result(i) := wor_trior(wor);
end loop;
return result;
end function;
function slv_image(inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use work.wor_std.all;
entity cpu_reg_dummy is
generic ( value: std_logic_vector(3 downto 0) := (others => 'Z') );
port ( rddata_o: out std_logic_vector(3 downto 0) );
end entity;
architecture foo of cpu_reg_dummy is
begin
rddata_o <= value after 0.5 ns;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use work.wor_std.all;
entity foe is
end entity;
architecture fum of foe is
component cpu_reg_dummy
generic ( value: std_logic_vector(rddata_o_range) := (others => 'Z') );
port ( rddata_o: out std_logic_vector(rddata_o_range) );
end component;
signal rddata_o: rddata_o_resolv std_logic_vector (rddata_o_range);
begin
CPU_REG1:
cpu_reg_dummy
generic map (value => "0000")
port map (rddata_o => rddata_o);
CPU_REG2:
cpu_reg_dummy
generic map (value => "1001")
port map (rddata_o => rddata_o);
CPU_REG3:
cpu_reg_dummy
generic map (value => "ZZZZ")
port map (rddata_o => rddata_o);
CPU_REG4:
cpu_reg_dummy
generic map (value => "ZZZX")
port map (rddata_o => rddata_o);
WHAT:
process
begin
wait for 0.6 ns;
report "rddata_o = " & slv_image(rddata_o);
wait;
end process;
end architecture;
|
gpl-2.0
|
457a0ff18bd10af23d8b7ff97d1baae3
| 0.548118 | 3.360039 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd
| 4 | 2,480 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_05a is
end entity inline_05a;
architecture test of inline_05a is
begin
block_1 : block is
constant cap : real := 1.0e-9;
constant rleak : real := 1.0E6;
-- code from book
terminal p1, p2 : electrical;
quantity vcap across icap, ileak through p1 to p2;
-- end code from book
begin
-- code from book
icap == cap * vcap'dot;
ileak == vcap / rleak;
-- end code from book
end block block_1;
block_2 : block is
-- code from book
nature electrical_vector is array (natural range <>) of electrical;
terminal a_bus : electrical_vector(1 to 8);
terminal signal_ground : electrical;
--
quantity bus_drops across bus_currents through a_bus to signal_ground;
--
terminal p1 : electrical_vector(0 to 3);
terminal p2 : electrical;
quantity v across i through p1 to p2;
--
constant tc1 : real := 1.0e-3; -- Linear temperature coefficient
constant tc2 : real := 1.0e-6; -- Second-order temperature coefficient
constant temp : real := 27.0; -- Ambient temperature
constant tnom : real := 50.0; -- Nominal temperature
constant res : real_vector := (1.0e3, 2.0e3, 4.0e3, 8.0e3); -- Nominal resistances
--
constant res_factor : real := (1.0 + tc1*(temp-tnom) + tc2*(temp-tnom)**2);
-- end code from book
begin
-- code from book
v(0) == i(0) * res(0) * res_factor;
v(1) == i(1) * res(1) * res_factor;
v(2) == i(2) * res(2) * res_factor;
v(3) == i(3) * res(3) * res_factor;
-- end code from book
end block block_2;
end architecture test;
|
gpl-2.0
|
7ac5ef40a71e67e15892b77625432e1d
| 0.656855 | 3.537803 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1461.vhd
| 4 | 1,884 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1461.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01461ent IS
END c08s07b00x00p04n01i01461ent;
ARCHITECTURE c08s07b00x00p04n01i01461arch OF c08s07b00x00p04n01i01461ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
variable n : integer := 0;
begin
if delay = 1 then
k := 1;
end if;
assert NOT(k = 1)
report "***PASSED TEST: c08s07b00x00p04n01i01461"
severity NOTE;
assert (k = 1)
report "***FAILED TEST: c08s07b00x00p04n01i01461 - the condition after the IF statement is TRUE in 'if-end if' format"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01461arch;
|
gpl-2.0
|
9a8cbceb4485c1ad8adc233f9fec84f7
| 0.653397 | 3.658252 | false | true | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.e-FwdMux2.vhd
| 1 | 2,252 |
--------------------------------------------------------------------------------
-- FILE: FwdMux2
-- DESC: Forward Multiplexer with 2 stage forward.
--
-- Author:
-- Create: 2015-06-01
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity FwdMux2 is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_ADDR_SIZE : integer := MyLog2Ceil(C_REG_NUM)
);
port(
reg_c : in std_logic_vector(DATA_SIZE-1 downto 0);
reg_f : in std_logic_vector(DATA_SIZE-1 downto 0);
reg_ff : in std_logic_vector(DATA_SIZE-1 downto 0);
addr_c : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
addr_f : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
addr_ff : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
valid_f : in std_logic;
valid_ff: in std_logic;
dirty_f : in std_logic;
dirty_ff: in std_logic;
en : in std_logic:='1';
output : out std_logic_vector(DATA_SIZE-1 downto 0);
match_dirty_f : out std_logic;
match_dirty_ff : out std_logic
);
end FwdMux2;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture fwd_mux_2_arch of FwdMux2 is
begin
P0: process(en, reg_c, reg_f, reg_ff, addr_c, addr_f, addr_ff, valid_f, valid_ff, dirty_f, dirty_ff)
variable dmatchf: std_logic:='0';
variable dmatchff: std_logic:='0';
begin
dmatchf:='0';
dmatchff:='0';
if en='1' then
if addr_c=(addr_c'range=>'0') then
output <= reg_c;
else
if (addr_c=addr_f) and (valid_f='1') then
if dirty_f='1' then
dmatchf := '1';
end if;
output <= reg_f;
elsif (addr_c=addr_ff) and (valid_ff='1') then
if dirty_ff='1' then
dmatchff := '1';
end if;
output <= reg_ff;
else
output <= reg_c;
end if;
end if;
match_dirty_f <= dmatchf;
match_dirty_ff <= dmatchff;
end if;
end process;
end fwd_mux_2_arch;
|
mit
|
f4a013fe8a8b7cc11929801b9378c574
| 0.494227 | 3.154062 | false | false | false | false |
123gmax/Digital-Lab
|
Lab3/Alex/Assignment3A/customip.vhd
| 1 | 8,639 |
------------------------------------------------------------------------------
-- hw_acc - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: hw_acc
-- Version: 1.00.a
-- Description: Example Axi Streaming core (VHDL).
-- Date: Mon Sep 15 15:41:21 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- ACLK : Synchronous clock
-- ARESETN : System reset, active low
-- S_AXIS_TREADY : Ready to accept data in
-- S_AXIS_TDATA : Data in
-- S_AXIS_TLAST : Optional data in qualifier
-- S_AXIS_TVALID : Data in is valid
-- M_AXIS_TVALID : Data out is valid
-- M_AXIS_TDATA : Data Out
-- M_AXIS_TLAST : Optional data out qualifier
-- M_AXIS_TREADY : Connected slave device is ready to accept data out
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity myip_v1_0 is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ACLK : in std_logic;
ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of ACLK : signal is "Clk";
end myip_v1_0;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
-- In this section, we povide an example implementation of ENTITY hw_acc
-- that does the following:
--
-- 1. Read all inputs
-- 2. Add each input to the contents of register 'sum' which
-- acts as an accumulator
-- 3. After all the inputs have been read, write out the
-- content of 'sum' into the output stream NUMBER_OF_OUTPUT_WORDS times
--
-- You will need to modify this example or implement a new architecture for
-- ENTITY hw_acc to implement your coprocessor
architecture EXAMPLE of myip_v1_0 is
-- Total number of input data.
constant NUMBER_OF_INPUT_WORDS : natural := 2;
-- Total number of output data
constant NUMBER_OF_OUTPUT_WORDS : natural := 2;
type STATE_TYPE is (Idle, Read_Input1, Read_Input2, Write_Outputs);
signal state : STATE_TYPE;
-- Accumulator to hold product of inputs read at any point in time
signal product : unsigned(63 downto 0);
signal product_vector : std_logic_vector(63 downto 0);
-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1;
signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1;
begin
-- CAUTION:
-- The sequence in which data are read in and written out should be
-- consistent with the sequence they are written and read in the
-- driver's hw_acc.c file
S_AXIS_TREADY <= '1' when (state = Read_Input1 or state = Read_Input2) else '0';
M_AXIS_TVALID <= '1' when state = Write_Outputs else '0';
M_AXIS_TLAST <= '1' when (state = Write_Outputs and nr_of_writes = 0) else '0';
--Output MSB first
product_vector <= std_logic_vector(product);
M_AXIS_TDATA <= product_vector(63 downto 32);
The_SW_accelerator : process (ACLK) is
begin -- process The_SW_accelerator
if ACLK'event and ACLK = '1' then -- Rising clock edge
if ARESETN = '0' then -- Synchronous reset (active low)
-- CAUTION: make sure your reset polarity is consistent with the
-- system reset polarity
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
product <= (others => '0');
else
case state is
when Idle =>
if (S_AXIS_TVALID = '1') then
state <= Read_Input1;
--Subtract 2 because the first input word is always directly copied to the product.
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
product <= (others => '0');
end if;
when Read_Input1 =>
if (S_AXIS_TVALID = '1') then
--The first number is always stored in the product.
product <= resize(unsigned(S_AXIS_TDATA), product'length);
state <= Read_Input2;
nr_of_reads <= nr_of_reads - 1;
end if;
when Read_Input2 =>
if(S_AXIS_TVALID = '1') then
--Subsequent numbers multiply the existing product.
product <= resize(product*unsigned(S_AXIS_TDATA), product'length);
if (nr_of_reads = 0) then
state <= Write_Outputs;
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
else
nr_of_reads <= nr_of_reads - 1;
end if;
end if;
when Write_Outputs =>
if (M_AXIS_TREADY = '1') then
if (nr_of_writes = 0) then
state <= Idle;
else
nr_of_writes <= nr_of_writes - 1;
--Shift the product one whole word to the left.
product <= shift_left(product, 32);
end if;
end if;
end case;
end if;
end if;
end process The_SW_accelerator;
end architecture EXAMPLE;
|
gpl-2.0
|
5defef51b47b40c930cc06a8dc6d6efc
| 0.485589 | 4.551633 | false | false | false | false |
dicearr/neuron-vhdl
|
src/adder_tree.vhd
| 1 | 4,835 |
-- ----------------------------------------------------------------
-- adder_tree.vhd
--
-- 4/28/2011 D. W. Hawkins ([email protected])
--
-- Adder tree.
--
-- This component calculates the pipelined sum of parallel input
-- arguments and generates a single output. The sums are
-- implemented in pairs. The width of the sums increases 1-bit
-- per layer. The number of sum layers is ceil(log2(NINPUTS)),
-- where NINPUTS is the number of inputs.
--
-- The sum pipeline pads the number of sums at the input to the
-- next power of two; synthesis removes unused logic. The sum
-- indexing for an 8 input example is;
--
-- sum(0) --|\ sum(8)
-- |+|--------|\
-- sum(1) --|/ | | sum(12)
-- |+|---------|\
-- sum(2) --|\ sum(9) | | | |
-- |+|--------|/ | |
-- sum(3) --|/ | | sum(14)
-- |+|---------
-- sum(4) --|\ sum(10) | |
-- |+|--------|\ | |
-- sum(5) --|/ | | sum(13) | |
-- |+|---------|/
-- sum(6) --|\ sum(11)| |
-- |+|--------|/
-- sum(7) --|/
--
-- The width of the full-precision output can be reduce by
-- rounding using the unbiased 'convergent' rounding component.
--
-- The parallel inputs are signed values packed into a wide
-- std_logic_vector.
--
-- ----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- ----------------------------------------------------------------
entity adder_tree is
generic (
-- Number of inputs
NINPUTS : integer;
-- Input data width
IWIDTH : integer;
-- Output data width
-- * full-precision requires that
-- OWIDTH = IWIDTH + ceil(log2(NINPUTS))
OWIDTH : integer
);
port (
-- Reset and clock
rstN : in std_logic;
clk : in std_logic;
-- Input data
-- * NINPUTS x signed(IWIDTH-1 downto 0)
d : in std_logic_vector(NINPUTS*IWIDTH-1 downto 0);
-- Output data
q : out signed(OWIDTH-1 downto 0)
);
end entity;
-- ----------------------------------------------------------------
architecture mixed of adder_tree is
-- ------------------------------------------------------------
-- Local functions
-- ------------------------------------------------------------
--
-- Input lookup and signed conversion
impure function din(i : integer) return signed is
begin
return signed(d((i+1)*IWIDTH-1 downto i*IWIDTH));
end function;
-- ------------------------------------------------------------
-- Constants
-- ------------------------------------------------------------
--
-- Number of stages required to sum the inputs
constant NSTAGES : integer :=
integer(ceil(log2(real(NINPUTS))));
-- Number of inputs padded to next power-of-2
-- * the width of the first stage of sums
constant PWIDTH : integer := 2**NSTAGES;
-- The total number of sums in the pipeline
constant NSUMS : integer := PWIDTH-1;
-- The width of the last sum (used for all sums)
constant SWIDTH : integer :=
IWIDTH + NSTAGES;
-- ------------------------------------------------------------
-- Signals
-- ------------------------------------------------------------
--
-- Sum pipeline
type sum_t is array (0 to NSUMS-1) of
signed(SWIDTH-1 downto 0);
signal sum : sum_t;
begin
-- ------------------------------------------------------------
-- Pipelined adders
-- ------------------------------------------------------------
--
process(clk,rstN)
variable prev_index : integer;
variable curr_index : integer;
variable num_sums : integer;
begin
if (rstN = '0') then
sum <= (others => (others => '0'));
elsif rising_edge(clk) then
-- First stage; pairs of input sums
-- * unused power-of-2 padding is left at the
-- reset value of zero.
num_sums := PWIDTH/2;
for j in 0 to num_sums-1 loop
if (2*j+1 < NINPUTS) then
-- Resize and then sum (to avoid overflow)
sum(j) <=
resize(din(2*j), SWIDTH) +
resize(din(2*j+1), SWIDTH);
elsif (2*j < NINPUTS) then
sum(j) <= resize(din(2*j), SWIDTH);
end if;
end loop;
-- Subsequent stages; sums of previous sums
prev_index := 0;
curr_index := num_sums;
num_sums := num_sums/2;
for i in 1 to NSTAGES-1 loop
for j in 0 to num_sums-1 loop
sum(curr_index + j) <=
sum(prev_index + 2*j) +
sum(prev_index + 2*j + 1);
end loop;
prev_index := curr_index;
curr_index := curr_index + num_sums;
num_sums := num_sums/2;
end loop;
end if;
end process;
-- ------------------------------------------------------------
-- Full-precision output sum
-- ------------------------------------------------------------
--
q <= sum(NSUMS-1)(OWIDTH-1 downto 0);
end architecture;
|
mit
|
26d384b56ce1835294bb49e8b1522355
| 0.470941 | 3.59747 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1986.vhd
| 4 | 5,430 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1986.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01986ent IS
type omega is range (-100) to 100
units
o1;
o2 = 5 o1;
o3 = 10 o1;
end units;
END c07s02b02x00p02n01i01986ent;
ARCHITECTURE c07s02b02x00p02n01i01986arch OF c07s02b02x00p02n01i01986ent IS
BEGIN
TESTING: PROCESS
variable om1, om2, om3 : omega;
--alias in A of variable in A of E physical type
alias al1 : omega is om1;
alias al2 : omega is om2;
alias al3 : omega is om3;
BEGIN
om1 := 4 o1;
om2 := 5 o1;
om3 := 6 o1;
assert NOT( 5 o1 = 5 o1 and
5 o1 = abs(5 o1) and
5 o1 = abs(-5 o1) and
4 o1 /= 5 o1 and
4 o1 /= abs(5 o1) and
4 o1 /= abs(-5 o1) and
4 o1 <= 5 o1 and
4 o1 <= abs(5 o1) and
4 o1 <= abs(-5 o1) and
5 o1 <= abs(-5 o1) and
4 o1 < 5 o1 and
4 o1 < abs(5 o1) and
4 o1 < abs(-5 o1) and
6 o1 >= 5 o1 and
6 o1 >= abs(5 o1) and
6 o1 >= abs(-5 o1) and
5 o1 >= abs(-5 o1) and
6 o1 > 5 o1 and
6 o1 > abs(5 o1) and
6 o1 > abs(-5 o1) and
--relation operators with variables
om1 = om1 and
om2 = abs(om2) and
om2 = abs(-om2) and
om1 /= om2 and
om1 /= abs(om2) and
om1 /= abs(-om2) and
om1 <= om2 and
om1 <= abs(om2) and
om1 <= abs(-om2) and
om2 <= abs(-om2) and
om1 < om2 and
om1 < abs(om2) and
om1 < abs(-om2) and
om2 >= om1 and
om2 >= abs(om1) and
om2 >= abs(-om1) and
om2 >= abs(-om1) and
om2 > om1 and
om2 > abs(om1) and
om2 > abs(-om1) )
report "***PASSED TEST: c07s02b02x00p02n01i01986"
severity NOTE;
assert ( 5 o1 = 5 o1 and
5 o1 = abs(5 o1) and
5 o1 = abs(-5 o1) and
4 o1 /= 5 o1 and
4 o1 /= abs(5 o1) and
4 o1 /= abs(-5 o1) and
4 o1 <= 5 o1 and
4 o1 <= abs(5 o1) and
4 o1 <= abs(-5 o1) and
5 o1 <= abs(-5 o1) and
4 o1 < 5 o1 and
4 o1 < abs(5 o1) and
4 o1 < abs(-5 o1) and
6 o1 >= 5 o1 and
6 o1 >= abs(5 o1) and
6 o1 >= abs(-5 o1) and
5 o1 >= abs(-5 o1) and
6 o1 > 5 o1 and
6 o1 > abs(5 o1) and
6 o1 > abs(-5 o1) and
--relation operators with variables
om1 = om1 and
om2 = abs(om2) and
om2 = abs(-om2) and
om1 /= om2 and
om1 /= abs(om2) and
om1 /= abs(-om2) and
om1 <= om2 and
om1 <= abs(om2) and
om1 <= abs(-om2) and
om2 <= abs(-om2) and
om1 < om2 and
om1 < abs(om2) and
om1 < abs(-om2) and
om2 >= om1 and
om2 >= abs(om1) and
om2 >= abs(-om1) and
om2 >= abs(-om1) and
om2 > om1 and
om2 > abs(om1) and
om2 > abs(-om1) )
report "***FAILED TEST: c07s02b02x00p02n01i01986 - Relational operators truth table test for data type of Physical failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01986arch;
|
gpl-2.0
|
a3be045f6a3eebbbc162b130e42e7734
| 0.416943 | 3.673884 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_05.vhd
| 4 | 1,908 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
architecture test of inline_05 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
-- code from book:
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
disconnect all : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
d88eda5562451b6aeb74e2393c0cdd69
| 0.682914 | 3.854545 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/SingleFile/f2m_divider_2_163.vhd
| 1 | 5,627 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m . Based on the work of Meurice Guerric
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_y: out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
signal R,S : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
signal V_shift,S_shift,U_shift,R_shift,P_shift : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal D, counter :std_logic_vector(8 downto 0);
signal IsPos: std_logic;
type CurrentState_type is (END_STATE, INIT, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
V_shift <= '0' & V(NUM_BITS downto 1);
S_shift <= '0' & S(NUM_BITS downto 1);
U_shift <= '0' & U(NUM_BITS downto 1);
R_shift <= '0' & R(NUM_BITS downto 1);
P_shift <= F(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
U <= '0' & y;
V <= F;
R <= '0' & x;
S <= (others => '0');
done <= '0';
x_y <= (others => '0');
counter <= "101000101"; -- 325 2m-1
D <= "000000001";
IsPos <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if counter = "000000000" then
currentState <= END_STATE;
Done <= '1';
x_y <= S(NUM_BITS-1 downto 0);
else
counter <= counter - 1;
if U(0) = '0' then
U <= U_shift;
if R(0) = '1' then
R <= (R_shift xor P_shift);
else
R <= R_shift;
end if;
if IsPos = '0' then
D <= D + 1;
elsif D = "000000000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
elsif IsPos = '1' then
U <= U_shift xor V_shift;
if R(0) = '1' then
R <= R_shift xor S_shift xor P_shift;
else
R <= R_shift xor S_shift;
end if;
if D = "000000000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
else
D <= D - 1;
IsPos <= '1';
U <= U_shift xor V_shift;
V <= U;
S <= R;
if R(0) = '1' then
R <= R_shift xor S_shift xor P_shift;
else
R <= R_shift xor S_shift;
end if;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
-- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
7e1c9fab215da7353622f4f3b1586d6b
| 0.362538 | 4.635091 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/capacitor.vhd
| 4 | 1,453 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
generic ( cap : capacitance;
r_esr : resistance := 0.0;
v_ic : voltage := real'low );
port ( terminal p1, p2 : electrical );
end entity capacitor;
----------------------------------------------------------------
architecture esr of capacitor is
quantity v across i through p1 to p2;
quantity vc : voltage; -- Internal voltage across capacitor
begin
if domain = quiescent_domain and v_ic /= real'low use
vc == v_ic;
i == 0.0;
else
vc == v - (i * r_esr);
i == cap * vc'dot;
end use;
end architecture esr;
|
gpl-2.0
|
ee78de29eed55199a582d47a7408b8c2
| 0.66139 | 4.070028 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc439.vhd
| 4 | 4,724 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc439.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00439ent IS
END c03s02b01x01p19n01i00439ent;
ARCHITECTURE c03s02b01x01p19n01i00439arch OF c03s02b01x01p19n01i00439ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
function complex_scalar(s : record_cons_array) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_cons_array is
begin
return C51;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_cons_array;
signal S2 : record_cons_array;
signal S3 : record_cons_array := C51;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C51) and (S2 = C51))
report "***PASSED TEST: c03s02b01x01p19n01i00439"
severity NOTE;
assert ((S1 = C51) and (S2 = C51))
report "***FAILED TEST: c03s02b01x01p19n01i00439 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00439arch;
|
gpl-2.0
|
2dba2a40eda11a17822d80ec2cd331a1
| 0.620872 | 3.656347 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3202.vhd
| 4 | 3,801 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3202.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.textio.all;
ENTITY c14s03b00x00p56n01i03202ent IS
END c14s03b00x00p56n01i03202ent;
ARCHITECTURE c14s03b00x00p56n01i03202arch OF c14s03b00x00p56n01i03202ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open read_mode is "iofile.61";
variable L : LINE;
variable Bi : BIT;
variable Bo : BOOLEAN;
variable BV : Bit_Vector(1 to 60);
variable BV2 : Bit_Vector(1 to 60);
-- Define the ScanForStars subprogram
procedure ScanForStars(L: inout Line) is
variable Index : Natural := 1;
variable C1, C2: Character := ' ';
begin
while C1 = ' ' loop
Read(L, C1);
end loop;
Read(L, C2);
assert C1 = '*' and C2 = '*'
report "Could not find two stars";
end;
BEGIN
-- Read the entire line..
READLINE(F, L);
assert L.all = "hello world"
report "Could not find opening banner...";
-- Read the blank line...
READLINE(F, L);
assert L.all = ""
report "Could not find blank line...";
-- Read some BITS...
for width in 1 to 10 loop
READLINE(F, L);
READ(L, Bi);
assert Bi = '0'
report "Failed in Read(BIT). (Should be '0')";
ScanForStars(L);
READ(L, Bi);
assert Bi = '1'
report "Failed in Read(BIT). (Should be '1')";
ScanForStars(L);
end loop;
READLINE(F, L);
-- Read some Bit vectors...
for i in BV'Range loop
BV(i) := Bit'Val(Boolean'Pos(BV'Right mod i = 0));
end loop;
for width in 15 downto 1 loop
READLINE(F, L);
READ(L, BV2(1 to 2*width));
assert BV2(1 to 2*width) = BV((15-width)*2+1 to 30)
report "Failed in Read(BIT_VECTOR). (Left side)";
ScanForStars(L);
READ(L, BV2(1 to 2*width));
assert BV2(1 to 2*width) = BV(1 to 2*width)
report "Failed in Read(BIT_VECTOR). (Right side)";
end loop;
READLINE(F, L);
-- Read some BOOLEANs...
for i in 10 downto 1 loop
READLINE(F, L);
READ(L, Bo);
assert Bo = FALSE
report "Failed in Read(BOOLEAN). (Left side)";
ScanForStars(L);
READ(L, Bo);
assert Bo = TRUE
report "Failed in Read(BOOLEAN). (Right side)";
end loop;
READLINE(F, L);
assert FALSE
report "***PASSED TEST: c14s03b00x00p56n01i03202 - This test file will read in an TEXT file with predefined data type BIT, BITVECOTR, BOOLEAN and STRING, and needs manual check to make sure that there is no ERROR assertion note."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p56n01i03202arch;
|
gpl-2.0
|
7d02d3bfaa68769dac6340703bbba48e
| 0.605367 | 3.562324 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd
| 4 | 2,550 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_07 is
end entity inline_07;
----------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture test of inline_07 is
signal clk, d : std_ulogic;
constant Tpw_clk : delay_length := 10 ns;
constant Tsu : delay_length := 4 ns;
begin
process_3_c : process (clk, d) is
begin
-- code from book:
if clk'event and (clk = '1' or clk = 'H')
and (clk'last_value = '0' or clk'last_value = 'L')
then
assert d'last_event >= Tsu
report "Timing error: d changed within setup time of clk";
end if;
-- end of code from book
end process process_3_c;
----------------
process_3_d : process (clk, d) is
begin
-- code from book:
assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
report "Clock frequency too high";
-- end of code from book
end process process_3_d;
----------------
process_3_e : process is
begin
-- code from book:
wait until clk = '1';
-- end of code from book
report "clk changed to '1'";
end process process_3_e;
----------------
stimulus_3_c_d : process is
begin
clk <= '1' after 15 ns,
'0' after 30 ns,
'1' after 40 ns,
'0' after 50 ns,
'H' after 60 ns,
'0' after 70 ns,
'1' after 80 ns,
'L' after 90 ns,
'H' after 100 ns,
'L' after 120 ns,
'1' after 125 ns, -- should cause error
'0' after 130 ns; -- should cause error
d <= '1' after 35 ns,
'0' after 77 ns, -- should cause error
'1' after 102 ns;
wait;
end process stimulus_3_c_d;
end architecture test;
|
gpl-2.0
|
698ad42aaeb5e9d258118d36dd5b40c7
| 0.584314 | 3.783383 | false | false | false | false |
siavooshpayandehazad/high_level_test_pattern_gen
|
Test/lib.vhd
| 1 | 6,666 |
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
--------------------------------------------------------------------------------
--!@file: tp_lib.vhd
--!@brief: library of tp
--
--!@author: Tobias Koal(TK)
--!@date: 13-10-02
--------------------------------------------------------------------------------
--! library description of the test processor!
package lib is
constant WIDTH : natural := 16;
constant PRG_WIDTH : natural := 104; -- Bits im Instruktionswort
constant OPC_WIDTH : natural := 8; -- Bits zur Speicherung des Opcodes
constant OPR_WIDTH : natural := 6; -- Bits zur Speicherung einer Registernummer
constant OFU_WIDTH : natural := OPC_WIDTH + 3*OPR_WIDTH;
constant SOPC1 : natural := PRG_WIDTH-1;
constant EOPC1 : natural := PRG_WIDTH-OPC_WIDTH;
constant SSRC1_1: natural := EOPC1-1;
constant ESRC1_1: natural := EOPC1-OPR_WIDTH;
constant SSRC1_2: natural := ESRC1_1-1;
constant ESRC1_2: natural := ESRC1_1-OPR_WIDTH;
constant SDST1 : natural := ESRC1_2-1;
constant EDST1 : natural := ESRC1_2-OPR_WIDTH;
constant SOPC2 : natural := SOPC1 -OFU_WIDTH;
constant EOPC2 : natural := EOPC1 -OFU_WIDTH;
constant SSRC2_1: natural := SSRC1_1-OFU_WIDTH;
constant ESRC2_1: natural := ESRC1_1-OFU_WIDTH;
constant SSRC2_2: natural := SSRC1_2-OFU_WIDTH;
constant ESRC2_2: natural := ESRC1_2-OFU_WIDTH;
constant SDST2 : natural := SDST1 -OFU_WIDTH;
constant EDST2 : natural := EDST1 -OFU_WIDTH;
constant SOPC3 : natural := SOPC1 -2*OFU_WIDTH;
constant EOPC3 : natural := EOPC1 -2*OFU_WIDTH;
constant SSRC3_1: natural := SSRC1_1-2*OFU_WIDTH;
constant ESRC3_1: natural := ESRC1_1-2*OFU_WIDTH;
constant SSRC3_2: natural := SSRC1_2-2*OFU_WIDTH;
constant ESRC3_2: natural := ESRC1_2-2*OFU_WIDTH;
constant SDST3 : natural := SDST1 -2*OFU_WIDTH;
constant EDST3 : natural := EDST1 -2*OFU_WIDTH;
constant SOPC4 : natural := SOPC1 -3*OFU_WIDTH;
constant EOPC4 : natural := EOPC1 -3*OFU_WIDTH;
constant SSRC4_1: natural := SSRC1_1-3*OFU_WIDTH;
constant ESRC4_1: natural := ESRC1_1-3*OFU_WIDTH;
constant SSRC4_2: natural := SSRC1_2-3*OFU_WIDTH;
constant ESRC4_2: natural := ESRC1_2-3*OFU_WIDTH;
constant SDST4 : natural := SDST1 -3*OFU_WIDTH;
constant EDST4 : natural := EDST1 -3*OFU_WIDTH;
subtype data_width is std_logic_vector(WIDTH - 1 downto 0);
subtype prog_addr_width is std_logic_vector(15 downto 0);
subtype dmem_addr_width is std_logic_vector(15 downto 0);
subtype instruction_width is std_logic_vector(PRG_WIDTH - 1 downto 0);
subtype opcode_width is std_logic_vector(OPC_WIDTH - 1 downto 0);
subtype reg_select is std_logic_vector(OPR_WIDTH - 1 downto 0);
constant ZERO_VECTOR : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
constant ONE_VECTOR : std_logic_vector(WIDTH - 1 downto 0) := (others => '1');
constant NOP_VECTOR : instruction_width := (others => '0');
constant C_ALU : std_logic_vector(3 downto 0) := "1100";
-- C_ALU & "0000" noch frei
constant I_CML : opcode_width := C_ALU & "0001";
constant I_INC : opcode_width := C_ALU & "0010";
constant I_DEC : opcode_width := C_ALU & "0011";
constant I_ADD : opcode_width := C_ALU & "0100";
constant I_ADC : opcode_width := C_ALU & "0101";
constant I_SUB : opcode_width := C_ALU & "0110";
constant I_SBB : opcode_width := C_ALU & "0111";
constant I_AND : opcode_width := C_ALU & "1000";
constant I_OR : opcode_width := C_ALU & "1001";
constant I_XOR : opcode_width := C_ALU & "1010";
constant I_CMP : opcode_width := C_ALU & "1011";
constant I_SHR : opcode_width := C_ALU & "1100";
constant I_SHL : opcode_width := C_ALU & "1101";
constant I_RRC : opcode_width := C_ALU & "1110";
constant I_RLC : opcode_width := C_ALU & "1111";
constant C_JMP_R : std_logic_vector(3 downto 0) := "0001";
-- C_JMP_R & "0000" noch frei
constant I_JZ : opcode_width := C_JMP_R & "0001";
constant I_JNZ : opcode_width := C_JMP_R & "0010";
constant I_CALL : opcode_width := C_JMP_R & "0011";
constant I_JMP : opcode_width := C_JMP_R & "0100";
constant I_JMPT : opcode_width := C_JMP_R & "0101";
constant I_JMPF : opcode_width := C_JMP_R & "0110";
constant I_JS : opcode_width := C_JMP_R & "0111";
constant I_JNS : opcode_width := C_JMP_R & "1000";
constant I_JC : opcode_width := C_JMP_R & "1001";
-- C_JMP_R & "1010" noch frei
constant I_JNC : opcode_width := C_JMP_R & "1011";
constant I_JO : opcode_width := C_JMP_R & "1100";
constant I_JNO : opcode_width := C_JMP_R & "1101";
constant I_JZ_C : std_logic_vector(3 downto 0) := "0010";
constant I_JNZ_C : std_logic_vector(3 downto 0) := "0011";
constant I_JS_C : std_logic_vector(3 downto 0) := "0100";
constant I_JNS_C : std_logic_vector(3 downto 0) := "0101";
constant I_JC_C : std_logic_vector(3 downto 0) := "0110";
constant I_JNC_C : std_logic_vector(3 downto 0) := "0111";
constant I_JO_C : std_logic_vector(3 downto 0) := "1000";
constant I_JNO_C : std_logic_vector(3 downto 0) := "1001";
constant I_JMPT_C : std_logic_vector(3 downto 0) := "1010";
constant I_JMPF_C : std_logic_vector(3 downto 0) := "1011";
constant C_MEM : std_logic_vector(3 downto 0) := "0000";
constant I_NOP : opcode_width := C_MEM & "0000";
constant I_LD0 : opcode_width := C_MEM & "0001";
constant I_LD1 : opcode_width := C_MEM & "0010";
constant I_ST0 : opcode_width := C_MEM & "0011";
constant I_ST1 : opcode_width := C_MEM & "0100";
constant I_CHK_L_0 : opcode_width := C_MEM & "0101";
constant I_CHK_R_0 : opcode_width := C_MEM & "0110";
constant I_CHK_R_1 : opcode_width := C_MEM & "1001";
constant I_CHK_L_1 : opcode_width := C_MEM & "1010";
constant I_HALT : opcode_width := C_MEM & "0111";
constant I_LD_FS : opcode_width := C_MEM & "1000";
-- "1101" noch frei
constant I_JMP_C : std_logic_vector(3 downto 0) := "1110";
constant I_LDC : std_logic_vector(3 downto 0) := "1111";
type faulty_rps_register is array (9 downto 0) of std_logic_vector(63 downto 0);
type fs_regs_select is array(3 downto 0) of std_logic_vector(3 downto 0);
type fs_bits_select is array(3 downto 0) of std_logic_vector(5 downto 0);
-- AP --
constant AP_WIDTH : natural := 8;
constant AP_ADDR_WIDTH : natural := 11;
subtype AP_data_width is std_logic_vector(AP_WIDTH-1 downto 0);
subtype AP_mem_addr_width is std_logic_vector(AP_ADDR_WIDTH-1 downto 0);
subtype AP_instruction_width is std_logic_vector(7 downto 0);
subtype AP_reg_select is std_logic_vector(1 downto 0);
end package lib;
--! package body of lib
package body lib is
end package body;
|
gpl-3.0
|
b13ca1b0d3425e318effe68cd52e04e1
| 0.636214 | 2.840222 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/mlite_pack/mlite_pack.vhd
| 2 | 21,630 |
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
GENERIC (
lpm_width : NATURAL;
lpm_widthad : NATURAL;
rden_used : STRING;
intended_device_family : STRING;
lpm_indata : STRING;
lpm_wraddress_control : STRING;
lpm_rdaddress_control : STRING;
lpm_outdata : STRING;
use_eab : STRING;
lpm_type : STRING);
PORT (
wren : IN STD_LOGIC ;
wrclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"16");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "ALTERA_LPM");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "ALTERA_LPM"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
opcode_test_out : out std_logic_vector(31 downto 0);
pc_future_test_out : out std_logic_vector(31 downto 2);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component ram
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
mit
|
418756fdb4463ac824cbb60e76f795a3
| 0.547203 | 3.620084 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd
| 4 | 1,333 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity fm_radio is
end entity fm_radio;
-- end not in book
architecture top_level of fm_radio is
terminal left_decoded, left_filtered : electrical;
terminal right_decoded, right_filtered : electrical;
-- ...
begin
left_pilot_filter : configuration work.notch_filter_down_to_device_level
port map ( input => left_decoded, output => left_filtered,
vdd => vdd, vss => vss, gnd => gnd );
-- ...
end architecture top_level;
|
gpl-2.0
|
c90789999a5e1131ac7970a3ea553b18
| 0.71943 | 3.95549 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_08.vhd
| 4 | 3,907 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_08.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity buf is
port ( a : in std_logic; y : out std_logic );
end entity buf;
architecture basic of buf is
begin
y <= a;
end architecture basic;
-- code from book
library ieee; use ieee.std_logic_1164.all;
entity fanout_tree is
generic ( height : natural );
port ( input : in std_logic;
output : out std_logic_vector (0 to 2**height - 1) );
end entity fanout_tree;
--------------------------------------------------
architecture recursive of fanout_tree is
begin
degenerate_tree : if height = 0 generate
begin
output(0) <= input;
end generate degenerate_tree;
compound_tree : if height > 0 generate
signal buffered_input_0, buffered_input_1 : std_logic;
begin
buf_0 : entity work.buf(basic)
port map ( a => input, y => buffered_input_0 );
subtree_0 : entity work.fanout_tree(recursive)
generic map ( height => height - 1 )
port map ( input => buffered_input_0,
output => output(0 to 2**(height - 1) - 1) );
buf_1 : entity work.buf(basic)
port map ( a => input, y => buffered_input_1 );
subtree_1 : entity work.fanout_tree(recursive)
generic map ( height => height - 1 )
port map ( input => buffered_input_1,
output => output(2**(height - 1) to 2**height - 1) );
end generate compound_tree;
end architecture recursive;
-- end code from book
library ieee; use ieee.std_logic_1164.all;
entity fg_14_08 is
end entity fg_14_08;
architecture test of fg_14_08 is
signal unbuffered_clock : std_logic;
signal buffered_clock_array : std_logic_vector(0 to 7);
begin
-- code from book (in text)
clock_buffer_tree : entity work.fanout_tree(recursive)
generic map ( height => 3 )
port map ( input => unbuffered_clock,
output => buffered_clock_array );
-- end code from book
clock_gen : process is
begin
unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
end process clock_gen;
end architecture test;
|
gpl-2.0
|
8bee984beeca4d6636cdb6725ff9c411
| 0.490914 | 4.847395 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_sequencer.vhd
| 4 | 2,107 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity control_sequencer is
end entity control_sequencer;
architecture test of control_sequencer is
signal phase1, phase2, reg_file_write_en,
A_reg_out_en, B_reg_out_en, C_reg_load_en : bit := '0';
begin
-- code from book
control_sequencer : process is
procedure control_write_back is
begin
wait until phase1 = '1';
reg_file_write_en <= '1';
wait until phase2 = '0';
reg_file_write_en <= '0';
end procedure control_write_back;
procedure control_arith_op is
begin
wait until phase1 = '1';
A_reg_out_en <= '1';
B_reg_out_en <= '1';
wait until phase1 = '0';
A_reg_out_en <= '0';
B_reg_out_en <= '0';
wait until phase2 = '1';
C_reg_load_en <= '1';
wait until phase2 = '0';
C_reg_load_en <= '0';
control_write_back; -- call procedure
end procedure control_arith_op;
-- . . .
begin
-- . . .
control_arith_op; -- call procedure
-- . . .
-- not in book
wait;
-- end not in book
end process control_sequencer;
-- end code from book
clock_gen : process is
begin
phase1 <= '1' after 10 ns, '0' after 20 ns;
phase2 <= '1' after 30 ns, '0' after 40 ns;
wait for 40 ns;
end process clock_gen;
end architecture test;
|
gpl-2.0
|
efa911f22ddb54f2c1044ba5a7bb2739
| 0.633602 | 3.589438 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_05.vhd
| 4 | 1,896 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_05.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_05 is
end entity ch_04_05;
----------------------------------------------------------------
architecture test of ch_04_05 is
begin
process_04_2_a : process is
-- code from book:
type sample is array (natural range <>) of integer;
variable short_sample_buf : sample(0 to 63);
subtype long_sample is sample(0 to 255);
variable new_sample_buf, old_sample_buf : long_sample;
constant lookup_table : sample := ( 1 => 23, 3 => -16, 2 => 100, 4 => 11);
constant beep_sample : sample := ( 127, 63, 0, -63, -127, -63, 0, 63 );
-- end of code from book
begin
wait;
end process process_04_2_a;
end architecture test;
|
gpl-2.0
|
5e2cdb9adce4c930268359fd4bbb60ae
| 0.537447 | 4.399072 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/math_real.vhd
| 4 | 7,959 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: math_real.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: Based on work by IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.4 JAT 4/15/93
-------------------------------------------------------------
Library IEEE;
Package MATH_REAL is
--synopsys synthesis_off
constant MATH_E : real := 2.71828_18284_59045_23536;
-- value of e
constant MATH_1_E: real := 0.36787_94411_71442_32160;
-- value of 1/e
constant MATH_PI : real := 3.14159_26535_89793_23846;
-- value of pi
constant MATH_1_PI : real := 0.31830_98861_83790_67154;
-- value of 1/pi
constant MATH_LOG_OF_2: real := 0.69314_71805_59945_30942;
-- natural log of 2
constant MATH_LOG_OF_10: real := 2.30258_50929_94045_68402;
-- natural log of10
constant MATH_LOG2_OF_E: real := 1.44269_50408_88963_4074;
-- log base 2 of e
constant MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765;
-- log base 10 of e
constant MATH_SQRT2: real := 1.41421_35623_73095_04880;
-- sqrt of 2
constant MATH_SQRT1_2: real := 0.70710_67811_86547_52440;
-- sqrt of 1/2
constant MATH_SQRT_PI: real := 1.77245_38509_05516_02730;
-- sqrt of pi
constant MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577;
-- conversion factor from degree to radian
constant MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685;
-- conversion factor from radian to degree
--
-- attribute for functions whose implementation is foreign (C native)
--
-- attribute FOREIGN: string; -- predefined attribute in VHDL-1992
--
function SIGN (X: real ) return real;
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
function CEIL (X : real ) return real;
-- returns smallest integer value (as real) not less than X
function FLOOR (X : real ) return real;
-- returns largest integer value (as real) not greater than X
function ROUND (X : real ) return real;
-- returns FLOOR(X + 0.5) if X > 0.0;
-- return CEIL(X - 0.5) if X < 0.0
function FMAX (X, Y : real ) return real;
-- returns the algebraically larger of X and Y
function FMIN (X, Y : real ) return real;
-- returns the algebraically smaller of X and Y
function SRAND (seed: in integer ) return integer;
-- attribute FOREIGN of SRAND: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- sets value of seed for sequence of pseudo-random numbers.
-- returns the value of the seed.
-- It uses the native C function srand().
function RAND return integer;
-- attribute FOREIGN of RAND: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- returns an integer pseudo-random number with uniform distribution.
-- It uses the native C function rand().
-- Seed for the sequence is initialized with the
-- SRAND() function and value of the seed is changed every
-- time SRAND() is called, but it is not visible.
-- The range of generated values is platform dependent.
function GET_RAND_MAX return integer;
-- attribute FOREIGN of GET_RAND_MAX: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- returns the upper bound of the range of the
-- pseudo-random numbers generated by RAND().
-- The support for this function is platform dependent.
-- It may not be available in some platforms.
-- Note: the value of (RAND() / GET_RAND_MAX()) is a
-- pseudo-random number distributed between 0 & 1.
function SQRT (X : real ) return real;
-- returns square root of X; X >= 0.0
function CBRT (X : real ) return real;
-- returns cube root of X
function "**" (X : integer; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integral value
function "**" (X : real; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integral value
function EXP (X : real ) return real;
-- returns e**X; where e = MATH_E
function LOG (X : real ) return real;
-- returns natural logarithm of X; X > 0
function LOG (BASE: positive; X : real) return real;
-- returns logarithm base BASE of X; X > 0
function SIN (X : real ) return real;
-- returns sin X; X in radians
function COS ( X : real ) return real;
-- returns cos X; X in radians
function TAN (X : real ) return real;
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
function ASIN (X : real ) return real;
-- returns -PI/2 < asin X < PI/2; | X | <= 1.0
function ACOS (X : real ) return real;
-- returns 0 < acos X < PI; | X | <= 1.0
function ATAN (X : real) return real;
-- returns -PI/2 < atan X < PI/2
function ATAN2 (X : real; Y : real) return real;
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
function SINH (X : real) return real;
-- hyperbolic sine; returns (e**X - e**(-X))/2
function COSH (X : real) return real;
-- hyperbolic cosine; returns (e**X + e**(-X))/2
function TANH (X : real) return real;
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
function ASINH (X : real) return real;
-- returns ln( X + sqrt( X**2 + 1))
function ACOSH (X : real) return real;
-- returns ln( X + sqrt( X**2 - 1)); X >= 1.0
function ATANH (X : real) return real;
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1.0
--synopsys synthesis_on
end MATH_REAL;
|
gpl-2.0
|
14802b5a39767412771fba57b458babf
| 0.570423 | 3.839363 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd
| 4 | 1,359 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity bit_to_analog is
port ( d : in bit;
terminal a : electrical );
end entity bit_to_analog;
----------------------------------------------------------------
architecture ideal of bit_to_analog is
constant v_low : real := 0.0;
constant v_high : real := 5.0;
signal v_in : real := 0.0;
quantity v_out across i_out through a to electrical_ref;
begin
v_in <= v_high when d = '1' else v_low;
v_out == v_in'ramp(1.0e-9);
end architecture ideal;
|
gpl-2.0
|
9ea0cc272ddca692d5eb3bdddf731c7e
| 0.665195 | 3.905172 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_283.vhd
| 1 | 4,799 |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_283 is
generic (
NUM_BITS : positive := 283 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_283;
-----------------------------------------------------------
architecture behave of serial_multiplier_283 is
-----------------------------------------------------------
-- m = 283 x283 + x12 + x7 + x5 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(8 downto 0); -- 8-bit counter, controling the number of iterations: m
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "100011010"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
if counter = "000000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
Done <= '1';
else
bx_int <= bx_shift;
end if;
when END_STATE =>
CurrentState <= END_STATE;
Done <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
39f4c05ded021a2e2bbde72accfb1f14
| 0.491977 | 4.423041 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd
| 4 | 1,702 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inverting_integrator is
port ( terminal input, output : electrical;
signal rst : in std_ulogic );
end entity inverting_integrator;
----------------------------------------------------------------
architecture structural of inverting_integrator is
terminal internal : electrical;
begin
r1 : entity work.resistor(ideal)
port map ( node1 => input, node2 => internal);
c1 : entity work.capacitor(leakage)
port map ( node1 => internal, node2 => output );
amp : entity work.opamp(slew_limited)
port map ( plus_in => electrical_ref, minus_in => internal,
output => output);
switch : entity work.analog_switch(ideal)
port map ( n1 => internal, n2 => output, control => rst );
end architecture structural;
|
gpl-2.0
|
eebf8720d973fde937945092fa00ce61
| 0.676263 | 4.308861 | false | false | false | false |
tristanseifert/68komputer
|
BusSDRAM.vhd
| 1 | 3,050 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- SDRAM controller. This uses the Altera sdr_sdram component to interface with
-- the SDRAM, and couple it to the 68k bus.
--
entity BusSDRAM is
PORT(
-- system signals
reset: IN std_logic;
reset_n: IN std_logic;
sdram_clk: IN std_logic; -- 100 MHz
-- CPU bus
bus_cs: IN std_logic; -- when high, outs is Z
bus_clk: IN std_logic; -- clock for bus
bus_address: IN std_logic_vector(22 downto 0);
bus_data: INOUT std_logic_vector(15 downto 0);
bus_rw: IN std_logic;
bus_as: IN std_logic;
bus_dtack: OUT std_logic;
bus_uds: IN std_logic;
bus_lds: IN std_logic;
-- connect to SDRAM
DRAM_CS_N: OUT std_logic;
DRAM_WE_N: OUT std_logic;
DRAM_CAS_N: OUT std_logic;
DRAM_RAS_N: OUT std_logic;
DRAM_ADDR: OUT std_logic_vector(11 downto 0);
DRAM_BA_0: OUT std_logic;
DRAM_BA_1: OUT std_logic;
DRAM_CKE: OUT std_logic;
DRAM_CLK: OUT std_logic;
DRAM_DQ: INOUT std_logic_vector(15 downto 0);
DRAM_LDQM: OUT std_logic;
DRAM_UDQM: OUT std_logic
);
end BusSDRAM;
architecture behavioral of BusSDRAM is
signal sdr_addr: std_logic_vector(22 downto 0);
signal sdr_cmd: std_logic_vector(2 downto 0);
signal sdr_cmdack: std_logic;
signal sdr_din: std_logic_vector(15 downto 0);
signal sdr_dout: std_logic_vector(15 downto 0);
signal sdr_data_mask: std_logic_vector(1 downto 0);
signal dram_bank: std_logic_vector(1 downto 0);
signal dram_cs: std_logic_vector(1 downto 0);
signal dram_dqm: std_logic_vector(1 downto 0);
begin
-- contat separate bank signals into one
DRAM_BA_0 <= dram_bank(0);
DRAM_BA_1 <= dram_bank(1);
DRAM_CS_N <= dram_cs(0);
DRAM_LDQM <= dram_dqm(0);
DRAM_UDQM <= dram_dqm(1);
-- SDRAM controller
u_sdram_controller: entity work.sdr_sdram(RTL)
port map(
CLK => sdram_clk,
RESET_N => reset_N,
-- interfacing with controller
ADDR => sdr_addr,
DATAIN => sdr_din,
DATAOUT => sdr_dout,
DM => sdr_data_mask, -- data masks
CMD => sdr_cmd,
CMDACK => sdr_cmdack,
-- to SDRAM
SA => DRAM_ADDR,
BA => dram_bank,
CS_N => dram_cs,
CKE => DRAM_CKE,
RAS_N => DRAM_RAS_N,
CAS_N => DRAM_CAS_N,
WE_N => DRAM_WE_N,
DQ => DRAM_DQ,
DQM => dram_dqm
);
-- 68k bus interface
process(bus_clk, reset, bus_cs, bus_rw)
begin
-- in reset state, don't drive the bus
if reset='0' then
bus_data <= (others => 'Z');
bus_dtack <= 'Z';
elsif rising_edge(bus_clk) then
-- is chip select asserted?
if bus_cs='0' then
-- write cycle
if bus_rw='0' then
bus_dtack <= '1';
-- read cycle
else
bus_dtack <= '1';
end if;
-- not selected: don't drive bus
else
bus_data <= (others => 'Z');
bus_dtack <= 'Z';
end if;
end if;
end process;
end behavioral;
|
bsd-2-clause
|
ed1833a9bde9461565dd8eb17696b811
| 0.599344 | 2.723214 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_10.vhd
| 4 | 2,124 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
-- not in book
entity signal_generator is
generic ( period : delay_length := 20 ns;
pulse_count : natural := 5 );
end entity signal_generator;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
architecture top_level of signal_generator is
signal raw_signal : std_ulogic;
-- . . .
procedure generate_pulse_train ( width, separation : in delay_length;
number : in natural;
signal s : out std_ulogic ) is
begin
for count in 1 to number loop
s <= '1', '0' after width;
wait for width + separation;
end loop;
end procedure generate_pulse_train;
begin
raw_signal_generator : process is
begin
-- . . .
generate_pulse_train ( width => period / 2,
separation => period - period / 2,
number => pulse_count,
s => raw_signal );
-- . . .
-- not in book
wait;
-- end not in book
end process raw_signal_generator;
-- . . .
end architecture top_level;
|
gpl-2.0
|
bf06b888770344f8a9edfc939204c7a4
| 0.581921 | 4.172888 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket11/tb2.vhdl
| 3 | 442 |
entity tb2 is
end entity;
architecture arch of tb2 is
signal s: integer := 0;
signal s2: integer := 0;
begin
process is
begin
wait for 1 us;
s2 <= 3;
s <= 1;
s <= 2 after 1 us;
assert s = 0;
wait on s;
report "s = " & integer'image(s);
assert s = 2 severity failure;
assert now = 2 us severity failure;
wait;
end process;
end architecture;
|
gpl-2.0
|
271bd3338eb16dbad430a3615fbfda4a
| 0.524887 | 3.714286 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2962.vhd
| 4 | 2,249 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2962.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b00x00p02n01i02962ent IS
port (f,h,i : out integer);
type tripe is (alpha,beta,gamma,delta,epsilon);
subtype subt is tripe range beta to epsilon;
END c02s03b00x00p02n01i02962ent;
ARCHITECTURE c02s03b00x00p02n01i02962arch OF c02s03b00x00p02n01i02962ent IS
function funk (signal fa,fb : tripe) return integer is
begin
return (1);
end;
function funk (signal fa,fb : bit) return integer is
begin
return (2);
end;
signal bv1 : bit_vector (1 to 40);
signal a,b,c : subt;
signal d,e,g : integer;
BEGIN
d <= funk(a,b);
TESTING: PROCESS
variable x : integer;
BEGIN
WAIT FOR 1 ns;
e <= funk(c,a);
x := funk(c,b);
g <= funk(bv1(2),bv1(6));
wait for 5 ns;
assert NOT(e=1 and x=1 and g=2)
report "***PASSED TEST: c02s03b00x00p02n01i02962"
severity NOTE;
assert (e=1 and x=1 and g=2)
report "***FAILED TEST: c02s03b00x00p02n01i02962 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02962arch;
|
gpl-2.0
|
e120fa5473ab1a60207f02f0df7005c8
| 0.648733 | 3.407576 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd
| 4 | 2,324 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity bus_module is
port ( synch : inout std_ulogic; -- . . . );
-- not in book
other_port : in std_ulogic := 'U' );
-- end not in book
end entity bus_module;
--------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity bus_based_system is
end entity bus_based_system;
-- end not in book
architecture top_level of bus_based_system is
signal synch_control : std_logic;
-- . . .
begin
synch_control_pull_up : synch_control <= 'H';
bus_module_1 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
-- not in book
other_port => open );
-- end not in book
bus_module_2 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture top_level;
architecture behavioral of bus_module is
begin
behavior : process is
-- . . .
-- not in book
constant Tdelay_synch : delay_length := 10 ns;
constant wait_delay : delay_length := 100 ns;
-- end not in book
begin
synch <= '0' after Tdelay_synch;
-- . . .
-- not in book
wait for wait_delay;
-- end not in book
-- ready to start operation
synch <= 'Z' after Tdelay_synch;
wait until synch = 'H';
-- proceed with operation
-- . . .
end process behavior;
end architecture behavioral;
|
gpl-2.0
|
2bda0e6801f4b448b9a2ab0363e05777
| 0.63253 | 3.828666 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/mb_lite/fetch.vhd
| 3 | 2,196 |
----------------------------------------------------------------------------------------------
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
-- uses a single port Random Access Memory component which holds
-- the instructions. The next instruction is computed in the decode
-- stage.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.core_Pkg.ALL;
USE work.std_Pkg.ALL;
ENTITY fetch IS PORT
(
fetch_o : OUT fetch_out_type;
imem_adr_o : OUT std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
imem_ena_o : OUT std_ulogic;
fetch_i : IN fetch_in_type;
rst_i : IN std_ulogic;
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END fetch;
ARCHITECTURE arch OF fetch IS
SIGNAL r, rin : fetch_out_type;
BEGIN
fetch_o.program_counter <= r.program_counter;
imem_adr_o <= rin.program_counter;
imem_ena_o <= ena_i;
fetch_comb: PROCESS(fetch_i, r, rst_i)
VARIABLE v : fetch_out_type;
BEGIN
v := r;
IF fetch_i.hazard = '1' THEN
v.program_counter := r.program_counter;
ELSIF fetch_i.branch = '1' THEN
v.program_counter := fetch_i.branch_target;
ELSE
v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 DOWNTO 2)) & "00";
END IF;
rin <= v;
END PROCESS;
fetch_seq: PROCESS(clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
r.program_counter <= (OTHERS => '0');
ELSIF ena_i = '1' THEN
r <= rin;
END IF;
END IF;
END PROCESS;
END arch;
|
mit
|
4b8c268f4b98cdf0df3fa98b8abc3060
| 0.500455 | 3.971067 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_131.vhd
| 1 | 17,856 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- x^131 + x^8 + x^3 + x^2 + 1
entity serial_multiplier_131 is
generic (
NUM_BITS : positive := 131 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_131;
-----------------------------------------------------------
architecture behave of serial_multiplier_131 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
signal xor_2 : std_logic;
signal xor_3 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
-- Result of the multiplication
xor_1 <= Cx_int(1) xor Cx_int(NUM_BITS-1);
xor_2 <= Cx_int(2) xor Cx_int(NUM_BITS-1);
xor_3 <= Cx_int(7) xor Cx_int(NUM_BITS-1);
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
CELL_0: ENTITY work.basic_cell(behave)
PORT MAP(Ax(0),Bx_int(NUM_BITS-1),Cx_int(NUM_BITS-1),clk,reset,Cx_int(0));
CELL_1: ENTITY work.basic_cell(behave)
PORT MAP(Ax(1),Bx_int(NUM_BITS-1),Cx_int(0),clk,reset,Cx_int(1));
CELL_2: ENTITY work.basic_cell(behave)
PORT MAP(Ax(2),Bx_int(NUM_BITS-1),xor_1,clk,reset,Cx_int(2));
CELL_3: ENTITY work.basic_cell(behave)
PORT MAP(Ax(3),Bx_int(NUM_BITS-1),xor_2,clk,reset,Cx_int(3));
CELL_4: ENTITY work.basic_cell(behave)
PORT MAP(Ax(4),Bx_int(NUM_BITS-1),Cx_int(3),clk,reset,Cx_int(4));
CELL_5: ENTITY work.basic_cell(behave)
PORT MAP(Ax(5),Bx_int(NUM_BITS-1),Cx_int(4),clk,reset,Cx_int(5));
CELL_6: ENTITY work.basic_cell(behave)
PORT MAP(Ax(6),Bx_int(NUM_BITS-1),Cx_int(5),clk,reset,Cx_int(6));
CELL_7: ENTITY work.basic_cell(behave)
PORT MAP(Ax(7),Bx_int(NUM_BITS-1),Cx_int(6),clk,reset,Cx_int(7));
CELL_8: ENTITY work.basic_cell(behave)
PORT MAP(Ax(8),Bx_int(NUM_BITS-1),xor_3,clk,reset,Cx_int(8));
CELL_9: ENTITY work.basic_cell(behave)
PORT MAP(Ax(9),Bx_int(NUM_BITS-1),Cx_int(8),clk,reset,Cx_int(9));
CELL_10: ENTITY work.basic_cell(behave)
PORT MAP(Ax(10),Bx_int(NUM_BITS-1),Cx_int(9),clk,reset,Cx_int(10));
CELL_11: ENTITY work.basic_cell(behave)
PORT MAP(Ax(11),Bx_int(NUM_BITS-1),Cx_int(10),clk,reset,Cx_int(11));
CELL_12: ENTITY work.basic_cell(behave)
PORT MAP(Ax(12),Bx_int(NUM_BITS-1),Cx_int(11),clk,reset,Cx_int(12));
CELL_13: ENTITY work.basic_cell(behave)
PORT MAP(Ax(13),Bx_int(NUM_BITS-1),Cx_int(12),clk,reset,Cx_int(13));
CELL_14: ENTITY work.basic_cell(behave)
PORT MAP(Ax(14),Bx_int(NUM_BITS-1),Cx_int(13),clk,reset,Cx_int(14));
CELL_15: ENTITY work.basic_cell(behave)
PORT MAP(Ax(15),Bx_int(NUM_BITS-1),Cx_int(14),clk,reset,Cx_int(15));
CELL_16: ENTITY work.basic_cell(behave)
PORT MAP(Ax(16),Bx_int(NUM_BITS-1),Cx_int(15),clk,reset,Cx_int(16));
CELL_17: ENTITY work.basic_cell(behave)
PORT MAP(Ax(17),Bx_int(NUM_BITS-1),Cx_int(16),clk,reset,Cx_int(17));
CELL_18: ENTITY work.basic_cell(behave)
PORT MAP(Ax(18),Bx_int(NUM_BITS-1),Cx_int(17),clk,reset,Cx_int(18));
CELL_19: ENTITY work.basic_cell(behave)
PORT MAP(Ax(19),Bx_int(NUM_BITS-1),Cx_int(18),clk,reset,Cx_int(19));
CELL_20: ENTITY work.basic_cell(behave)
PORT MAP(Ax(20),Bx_int(NUM_BITS-1),Cx_int(19),clk,reset,Cx_int(20));
CELL_21: ENTITY work.basic_cell(behave)
PORT MAP(Ax(21),Bx_int(NUM_BITS-1),Cx_int(20),clk,reset,Cx_int(21));
CELL_22: ENTITY work.basic_cell(behave)
PORT MAP(Ax(22),Bx_int(NUM_BITS-1),Cx_int(21),clk,reset,Cx_int(22));
CELL_23: ENTITY work.basic_cell(behave)
PORT MAP(Ax(23),Bx_int(NUM_BITS-1),Cx_int(22),clk,reset,Cx_int(23));
CELL_24: ENTITY work.basic_cell(behave)
PORT MAP(Ax(24),Bx_int(NUM_BITS-1),Cx_int(23),clk,reset,Cx_int(24));
CELL_25: ENTITY work.basic_cell(behave)
PORT MAP(Ax(25),Bx_int(NUM_BITS-1),Cx_int(24),clk,reset,Cx_int(25));
CELL_26: ENTITY work.basic_cell(behave)
PORT MAP(Ax(26),Bx_int(NUM_BITS-1),Cx_int(25),clk,reset,Cx_int(26));
CELL_27: ENTITY work.basic_cell(behave)
PORT MAP(Ax(27),Bx_int(NUM_BITS-1),Cx_int(26),clk,reset,Cx_int(27));
CELL_28: ENTITY work.basic_cell(behave)
PORT MAP(Ax(28),Bx_int(NUM_BITS-1),Cx_int(27),clk,reset,Cx_int(28));
CELL_29: ENTITY work.basic_cell(behave)
PORT MAP(Ax(29),Bx_int(NUM_BITS-1),Cx_int(28),clk,reset,Cx_int(29));
CELL_30: ENTITY work.basic_cell(behave)
PORT MAP(Ax(30),Bx_int(NUM_BITS-1),Cx_int(29),clk,reset,Cx_int(30));
CELL_31: ENTITY work.basic_cell(behave)
PORT MAP(Ax(31),Bx_int(NUM_BITS-1),Cx_int(30),clk,reset,Cx_int(31));
CELL_32: ENTITY work.basic_cell(behave)
PORT MAP(Ax(32),Bx_int(NUM_BITS-1),Cx_int(31),clk,reset,Cx_int(32));
CELL_33: ENTITY work.basic_cell(behave)
PORT MAP(Ax(33),Bx_int(NUM_BITS-1),Cx_int(32),clk,reset,Cx_int(33));
CELL_34: ENTITY work.basic_cell(behave)
PORT MAP(Ax(34),Bx_int(NUM_BITS-1),Cx_int(33),clk,reset,Cx_int(34));
CELL_35: ENTITY work.basic_cell(behave)
PORT MAP(Ax(35),Bx_int(NUM_BITS-1),Cx_int(34),clk,reset,Cx_int(35));
CELL_36: ENTITY work.basic_cell(behave)
PORT MAP(Ax(36),Bx_int(NUM_BITS-1),Cx_int(35),clk,reset,Cx_int(36));
CELL_37: ENTITY work.basic_cell(behave)
PORT MAP(Ax(37),Bx_int(NUM_BITS-1),Cx_int(36),clk,reset,Cx_int(37));
CELL_38: ENTITY work.basic_cell(behave)
PORT MAP(Ax(38),Bx_int(NUM_BITS-1),Cx_int(37),clk,reset,Cx_int(38));
CELL_39: ENTITY work.basic_cell(behave)
PORT MAP(Ax(39),Bx_int(NUM_BITS-1),Cx_int(38),clk,reset,Cx_int(39));
CELL_40: ENTITY work.basic_cell(behave)
PORT MAP(Ax(40),Bx_int(NUM_BITS-1),Cx_int(39),clk,reset,Cx_int(40));
CELL_41: ENTITY work.basic_cell(behave)
PORT MAP(Ax(41),Bx_int(NUM_BITS-1),Cx_int(40),clk,reset,Cx_int(41));
CELL_42: ENTITY work.basic_cell(behave)
PORT MAP(Ax(42),Bx_int(NUM_BITS-1),Cx_int(41),clk,reset,Cx_int(42));
CELL_43: ENTITY work.basic_cell(behave)
PORT MAP(Ax(43),Bx_int(NUM_BITS-1),Cx_int(42),clk,reset,Cx_int(43));
CELL_44: ENTITY work.basic_cell(behave)
PORT MAP(Ax(44),Bx_int(NUM_BITS-1),Cx_int(43),clk,reset,Cx_int(44));
CELL_45: ENTITY work.basic_cell(behave)
PORT MAP(Ax(45),Bx_int(NUM_BITS-1),Cx_int(44),clk,reset,Cx_int(45));
CELL_46: ENTITY work.basic_cell(behave)
PORT MAP(Ax(46),Bx_int(NUM_BITS-1),Cx_int(45),clk,reset,Cx_int(46));
CELL_47: ENTITY work.basic_cell(behave)
PORT MAP(Ax(47),Bx_int(NUM_BITS-1),Cx_int(46),clk,reset,Cx_int(47));
CELL_48: ENTITY work.basic_cell(behave)
PORT MAP(Ax(48),Bx_int(NUM_BITS-1),Cx_int(47),clk,reset,Cx_int(48));
CELL_49: ENTITY work.basic_cell(behave)
PORT MAP(Ax(49),Bx_int(NUM_BITS-1),Cx_int(48),clk,reset,Cx_int(49));
CELL_50: ENTITY work.basic_cell(behave)
PORT MAP(Ax(50),Bx_int(NUM_BITS-1),Cx_int(49),clk,reset,Cx_int(50));
CELL_51: ENTITY work.basic_cell(behave)
PORT MAP(Ax(51),Bx_int(NUM_BITS-1),Cx_int(50),clk,reset,Cx_int(51));
CELL_52: ENTITY work.basic_cell(behave)
PORT MAP(Ax(52),Bx_int(NUM_BITS-1),Cx_int(51),clk,reset,Cx_int(52));
CELL_53: ENTITY work.basic_cell(behave)
PORT MAP(Ax(53),Bx_int(NUM_BITS-1),Cx_int(52),clk,reset,Cx_int(53));
CELL_54: ENTITY work.basic_cell(behave)
PORT MAP(Ax(54),Bx_int(NUM_BITS-1),Cx_int(53),clk,reset,Cx_int(54));
CELL_55: ENTITY work.basic_cell(behave)
PORT MAP(Ax(55),Bx_int(NUM_BITS-1),Cx_int(54),clk,reset,Cx_int(55));
CELL_56: ENTITY work.basic_cell(behave)
PORT MAP(Ax(56),Bx_int(NUM_BITS-1),Cx_int(55),clk,reset,Cx_int(56));
CELL_57: ENTITY work.basic_cell(behave)
PORT MAP(Ax(57),Bx_int(NUM_BITS-1),Cx_int(56),clk,reset,Cx_int(57));
CELL_58: ENTITY work.basic_cell(behave)
PORT MAP(Ax(58),Bx_int(NUM_BITS-1),Cx_int(57),clk,reset,Cx_int(58));
CELL_59: ENTITY work.basic_cell(behave)
PORT MAP(Ax(59),Bx_int(NUM_BITS-1),Cx_int(58),clk,reset,Cx_int(59));
CELL_60: ENTITY work.basic_cell(behave)
PORT MAP(Ax(60),Bx_int(NUM_BITS-1),Cx_int(59),clk,reset,Cx_int(60));
CELL_61: ENTITY work.basic_cell(behave)
PORT MAP(Ax(61),Bx_int(NUM_BITS-1),Cx_int(60),clk,reset,Cx_int(61));
CELL_62: ENTITY work.basic_cell(behave)
PORT MAP(Ax(62),Bx_int(NUM_BITS-1),Cx_int(61),clk,reset,Cx_int(62));
CELL_63: ENTITY work.basic_cell(behave)
PORT MAP(Ax(63),Bx_int(NUM_BITS-1),Cx_int(62),clk,reset,Cx_int(63));
CELL_64: ENTITY work.basic_cell(behave)
PORT MAP(Ax(64),Bx_int(NUM_BITS-1),Cx_int(63),clk,reset,Cx_int(64));
CELL_65: ENTITY work.basic_cell(behave)
PORT MAP(Ax(65),Bx_int(NUM_BITS-1),Cx_int(64),clk,reset,Cx_int(65));
CELL_66: ENTITY work.basic_cell(behave)
PORT MAP(Ax(66),Bx_int(NUM_BITS-1),Cx_int(65),clk,reset,Cx_int(66));
CELL_67: ENTITY work.basic_cell(behave)
PORT MAP(Ax(67),Bx_int(NUM_BITS-1),Cx_int(66),clk,reset,Cx_int(67));
CELL_68: ENTITY work.basic_cell(behave)
PORT MAP(Ax(68),Bx_int(NUM_BITS-1),Cx_int(67),clk,reset,Cx_int(68));
CELL_69: ENTITY work.basic_cell(behave)
PORT MAP(Ax(69),Bx_int(NUM_BITS-1),Cx_int(68),clk,reset,Cx_int(69));
CELL_70: ENTITY work.basic_cell(behave)
PORT MAP(Ax(70),Bx_int(NUM_BITS-1),Cx_int(69),clk,reset,Cx_int(70));
CELL_71: ENTITY work.basic_cell(behave)
PORT MAP(Ax(71),Bx_int(NUM_BITS-1),Cx_int(70),clk,reset,Cx_int(71));
CELL_72: ENTITY work.basic_cell(behave)
PORT MAP(Ax(72),Bx_int(NUM_BITS-1),Cx_int(71),clk,reset,Cx_int(72));
CELL_73: ENTITY work.basic_cell(behave)
PORT MAP(Ax(73),Bx_int(NUM_BITS-1),Cx_int(72),clk,reset,Cx_int(73));
CELL_74: ENTITY work.basic_cell(behave)
PORT MAP(Ax(74),Bx_int(NUM_BITS-1),Cx_int(73),clk,reset,Cx_int(74));
CELL_75: ENTITY work.basic_cell(behave)
PORT MAP(Ax(75),Bx_int(NUM_BITS-1),Cx_int(74),clk,reset,Cx_int(75));
CELL_76: ENTITY work.basic_cell(behave)
PORT MAP(Ax(76),Bx_int(NUM_BITS-1),Cx_int(75),clk,reset,Cx_int(76));
CELL_77: ENTITY work.basic_cell(behave)
PORT MAP(Ax(77),Bx_int(NUM_BITS-1),Cx_int(76),clk,reset,Cx_int(77));
CELL_78: ENTITY work.basic_cell(behave)
PORT MAP(Ax(78),Bx_int(NUM_BITS-1),Cx_int(77),clk,reset,Cx_int(78));
CELL_79: ENTITY work.basic_cell(behave)
PORT MAP(Ax(79),Bx_int(NUM_BITS-1),Cx_int(78),clk,reset,Cx_int(79));
CELL_80: ENTITY work.basic_cell(behave)
PORT MAP(Ax(80),Bx_int(NUM_BITS-1),Cx_int(79),clk,reset,Cx_int(80));
CELL_81: ENTITY work.basic_cell(behave)
PORT MAP(Ax(81),Bx_int(NUM_BITS-1),Cx_int(80),clk,reset,Cx_int(81));
CELL_82: ENTITY work.basic_cell(behave)
PORT MAP(Ax(82),Bx_int(NUM_BITS-1),Cx_int(81),clk,reset,Cx_int(82));
CELL_83: ENTITY work.basic_cell(behave)
PORT MAP(Ax(83),Bx_int(NUM_BITS-1),Cx_int(82),clk,reset,Cx_int(83));
CELL_84: ENTITY work.basic_cell(behave)
PORT MAP(Ax(84),Bx_int(NUM_BITS-1),Cx_int(83),clk,reset,Cx_int(84));
CELL_85: ENTITY work.basic_cell(behave)
PORT MAP(Ax(85),Bx_int(NUM_BITS-1),Cx_int(84),clk,reset,Cx_int(85));
CELL_86: ENTITY work.basic_cell(behave)
PORT MAP(Ax(86),Bx_int(NUM_BITS-1),Cx_int(85),clk,reset,Cx_int(86));
CELL_87: ENTITY work.basic_cell(behave)
PORT MAP(Ax(87),Bx_int(NUM_BITS-1),Cx_int(86),clk,reset,Cx_int(87));
CELL_88: ENTITY work.basic_cell(behave)
PORT MAP(Ax(88),Bx_int(NUM_BITS-1),Cx_int(87),clk,reset,Cx_int(88));
CELL_89: ENTITY work.basic_cell(behave)
PORT MAP(Ax(89),Bx_int(NUM_BITS-1),Cx_int(88),clk,reset,Cx_int(89));
CELL_90: ENTITY work.basic_cell(behave)
PORT MAP(Ax(90),Bx_int(NUM_BITS-1),Cx_int(89),clk,reset,Cx_int(90));
CELL_91: ENTITY work.basic_cell(behave)
PORT MAP(Ax(91),Bx_int(NUM_BITS-1),Cx_int(90),clk,reset,Cx_int(91));
CELL_92: ENTITY work.basic_cell(behave)
PORT MAP(Ax(92),Bx_int(NUM_BITS-1),Cx_int(91),clk,reset,Cx_int(92));
CELL_93: ENTITY work.basic_cell(behave)
PORT MAP(Ax(93),Bx_int(NUM_BITS-1),Cx_int(92),clk,reset,Cx_int(93));
CELL_94: ENTITY work.basic_cell(behave)
PORT MAP(Ax(94),Bx_int(NUM_BITS-1),Cx_int(93),clk,reset,Cx_int(94));
CELL_95: ENTITY work.basic_cell(behave)
PORT MAP(Ax(95),Bx_int(NUM_BITS-1),Cx_int(94),clk,reset,Cx_int(95));
CELL_96: ENTITY work.basic_cell(behave)
PORT MAP(Ax(96),Bx_int(NUM_BITS-1),Cx_int(95),clk,reset,Cx_int(96));
CELL_97: ENTITY work.basic_cell(behave)
PORT MAP(Ax(97),Bx_int(NUM_BITS-1),Cx_int(96),clk,reset,Cx_int(97));
CELL_98: ENTITY work.basic_cell(behave)
PORT MAP(Ax(98),Bx_int(NUM_BITS-1),Cx_int(97),clk,reset,Cx_int(98));
CELL_99: ENTITY work.basic_cell(behave)
PORT MAP(Ax(99),Bx_int(NUM_BITS-1),Cx_int(98),clk,reset,Cx_int(99));
CELL_100: ENTITY work.basic_cell(behave)
PORT MAP(Ax(100),Bx_int(NUM_BITS-1),Cx_int(99),clk,reset,Cx_int(100));
CELL_101: ENTITY work.basic_cell(behave)
PORT MAP(Ax(101),Bx_int(NUM_BITS-1),Cx_int(100),clk,reset,Cx_int(101));
CELL_102: ENTITY work.basic_cell(behave)
PORT MAP(Ax(102),Bx_int(NUM_BITS-1),Cx_int(101),clk,reset,Cx_int(102));
CELL_103: ENTITY work.basic_cell(behave)
PORT MAP(Ax(103),Bx_int(NUM_BITS-1),Cx_int(102),clk,reset,Cx_int(103));
CELL_104: ENTITY work.basic_cell(behave)
PORT MAP(Ax(104),Bx_int(NUM_BITS-1),Cx_int(103),clk,reset,Cx_int(104));
CELL_105: ENTITY work.basic_cell(behave)
PORT MAP(Ax(105),Bx_int(NUM_BITS-1),Cx_int(104),clk,reset,Cx_int(105));
CELL_106: ENTITY work.basic_cell(behave)
PORT MAP(Ax(106),Bx_int(NUM_BITS-1),Cx_int(105),clk,reset,Cx_int(106));
CELL_107: ENTITY work.basic_cell(behave)
PORT MAP(Ax(107),Bx_int(NUM_BITS-1),Cx_int(106),clk,reset,Cx_int(107));
CELL_108: ENTITY work.basic_cell(behave)
PORT MAP(Ax(108),Bx_int(NUM_BITS-1),Cx_int(107),clk,reset,Cx_int(108));
CELL_109: ENTITY work.basic_cell(behave)
PORT MAP(Ax(109),Bx_int(NUM_BITS-1),Cx_int(108),clk,reset,Cx_int(109));
CELL_110: ENTITY work.basic_cell(behave)
PORT MAP(Ax(110),Bx_int(NUM_BITS-1),Cx_int(109),clk,reset,Cx_int(110));
CELL_111: ENTITY work.basic_cell(behave)
PORT MAP(Ax(111),Bx_int(NUM_BITS-1),Cx_int(110),clk,reset,Cx_int(111));
CELL_112: ENTITY work.basic_cell(behave)
PORT MAP(Ax(112),Bx_int(NUM_BITS-1),Cx_int(111),clk,reset,Cx_int(112));
CELL_113: ENTITY work.basic_cell(behave)
PORT MAP(Ax(113),Bx_int(NUM_BITS-1),Cx_int(112),clk,reset,Cx_int(113));
CELL_114: ENTITY work.basic_cell(behave)
PORT MAP(Ax(114),Bx_int(NUM_BITS-1),Cx_int(113),clk,reset,Cx_int(114));
CELL_115: ENTITY work.basic_cell(behave)
PORT MAP(Ax(115),Bx_int(NUM_BITS-1),Cx_int(114),clk,reset,Cx_int(115));
CELL_116: ENTITY work.basic_cell(behave)
PORT MAP(Ax(116),Bx_int(NUM_BITS-1),Cx_int(115),clk,reset,Cx_int(116));
CELL_117: ENTITY work.basic_cell(behave)
PORT MAP(Ax(117),Bx_int(NUM_BITS-1),Cx_int(116),clk,reset,Cx_int(117));
CELL_118: ENTITY work.basic_cell(behave)
PORT MAP(Ax(118),Bx_int(NUM_BITS-1),Cx_int(117),clk,reset,Cx_int(118));
CELL_119: ENTITY work.basic_cell(behave)
PORT MAP(Ax(119),Bx_int(NUM_BITS-1),Cx_int(118),clk,reset,Cx_int(119));
CELL_120: ENTITY work.basic_cell(behave)
PORT MAP(Ax(120),Bx_int(NUM_BITS-1),Cx_int(119),clk,reset,Cx_int(120));
CELL_121: ENTITY work.basic_cell(behave)
PORT MAP(Ax(121),Bx_int(NUM_BITS-1),Cx_int(120),clk,reset,Cx_int(121));
CELL_122: ENTITY work.basic_cell(behave)
PORT MAP(Ax(122),Bx_int(NUM_BITS-1),Cx_int(121),clk,reset,Cx_int(122));
CELL_123: ENTITY work.basic_cell(behave)
PORT MAP(Ax(123),Bx_int(NUM_BITS-1),Cx_int(122),clk,reset,Cx_int(123));
CELL_124: ENTITY work.basic_cell(behave)
PORT MAP(Ax(124),Bx_int(NUM_BITS-1),Cx_int(123),clk,reset,Cx_int(124));
CELL_125: ENTITY work.basic_cell(behave)
PORT MAP(Ax(125),Bx_int(NUM_BITS-1),Cx_int(124),clk,reset,Cx_int(125));
CELL_126: ENTITY work.basic_cell(behave)
PORT MAP(Ax(126),Bx_int(NUM_BITS-1),Cx_int(125),clk,reset,Cx_int(126));
CELL_127: ENTITY work.basic_cell(behave)
PORT MAP(Ax(127),Bx_int(NUM_BITS-1),Cx_int(126),clk,reset,Cx_int(127));
CELL_128: ENTITY work.basic_cell(behave)
PORT MAP(Ax(128),Bx_int(NUM_BITS-1),Cx_int(127),clk,reset,Cx_int(128));
CELL_129: ENTITY work.basic_cell(behave)
PORT MAP(Ax(129),Bx_int(NUM_BITS-1),Cx_int(128),clk,reset,Cx_int(129));
CELL_130: ENTITY work.basic_cell(behave)
PORT MAP(Ax(130),Bx_int(NUM_BITS-1),Cx_int(129),clk,reset,Cx_int(130));
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10000010"; -- m-1 value, in this case, it is 112, be sure to set the correct value
bx_int <= bx;
cx <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
counter <= counter - 1;
if counter = "0000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
else
bx_int <= bx_shift;
end if;
when END_STATE =>
Cx <= Cx_int;
Done <= '1';
CurrentState <= NOTHING;
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
03a93cc85981990affe42deecd8dce8f
| 0.655746 | 2.420168 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug7751/7751_extra_tests.vhd
| 3 | 7,504 |
entity tb is
end tb;
architecture sim of tb is
-- Extra tests for 'image and 'value on enumeration types (other than boolean)
-- Type with less than 256 values
type e8 is (one, two, three, four);
-- Type with more than 256 values
type e32 is (T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
T20, T21, T22, T23, T24, T25, T26, T27, T28, T29,
T30, T31, T32, T33, T34, T35, T36, T37, T38, T39,
T40, T41, T42, T43, T44, T45, T46, T47, T48, T49,
T50, T51, T52, T53, T54, T55, T56, T57, T58, T59,
T60, T61, T62, T63, T64, T65, T66, T67, T68, T69,
T70, T71, T72, T73, T74, T75, T76, T77, T78, T79,
T80, T81, T82, T83, T84, T85, T86, T87, T88, T89,
T90, T91, T92, T93, T94, T95, T96, T97, T98, T99,
T100, T101, T102, T103, T104, T105, T106, T107, T108, T109,
T110, T111, T112, T113, T114, T115, T116, T117, T118, T119,
T120, T121, T122, T123, T124, T125, T126, T127, T128, T129,
T130, T131, T132, T133, T134, T135, T136, T137, T138, T139,
T140, T141, T142, T143, T144, T145, T146, T147, T148, T149,
T150, T151, T152, T153, T154, T155, T156, T157, T158, T159,
T160, T161, T162, T163, T164, T165, T166, T167, T168, T169,
T170, T171, T172, T173, T174, T175, T176, T177, T178, T179,
T180, T181, T182, T183, T184, T185, T186, T187, T188, T189,
T190, T191, T192, T193, T194, T195, T196, T197, T198, T199,
T200, T201, T202, T203, T204, T205, T206, T207, T208, T209,
T210, T211, T212, T213, T214, T215, T216, T217, T218, T219,
T220, T221, T222, T223, T224, T225, T226, T227, T228, T229,
T230, T231, T232, T233, T234, T235, T236, T237, T238, T239,
T240, T241, T242, T243, T244, T245, T246, T247, T248, T249,
T250, T251, T252, T253, T254, T255, T256, T257, T258, T259,
T260, T261, T262, T263, T264, T265, T266, T267, T268, T269,
T270, T271, T272, T273, T274, T275, T276, T277, T278, T279,
T280, T281, T282, T283, T284, T285, T286, T287, T288, T289,
T290, T291, T292, T293, T294, T295, T296, T297, T298, T299 );
-------------- static value ----------------------
-- static value : enumeration
constant e8str : string := "three";
constant e8val : e8 := e8'value("TWO");
constant e32str_1 : string := "T254";
constant e32str_2 : string := "T257";
constant e32val_1 : e32 := e32'value("T250");
constant e32val_2 : e32 := e32'value("T260");
-------------- static image ----------------------
-- static image : enumeration
constant e8_img1 : string := e8'image(One);
constant e8_img2 : string := e8'image(Two);
constant e32_img1 : string := e32'image(T1);
constant e32_img2 : string := e32'image(T299);
-------------- runtime value ----------------------
-- runtime enumeration
signal my_e8 : e8 := One;
signal my_e8_str : string(1 to 3) := "Two";
signal my_e32 : e32 := T298;
signal my_e32_str : string(1 to 3) := "T22";
function e_val (s : string) return e8 is
begin
return e8'value(s);
end e_val;
function e_val (s : string) return e32 is
begin
return e32'value(s);
end e_val;
-------------- runtime image ----------------------
-- runtime enumeration
signal sig_e8 : e8 := e8'value("Three");
signal sig_e32 : e32 := e32'value("T123");
function e_img (e : e8) return string is
begin
return e8'image(e);
end e_img;
function e_img (e : e32) return string is
begin
return e32'image(e);
end e_img;
function t_val (t : string) return time is
begin
return time'value (t);
end t_val;
begin
-- At least one test for each constant, signal or function
-- Value tests : static enumeration expressions.
Assert e8'value("One") = Two report "Assertion 1 triggered ... correctly" severity NOTE;
Assert e8'value("One") = One report "Assertion 2 triggered ... wrongly" severity FAILURE;
Assert e8'value(e8str) = Two report "Assertion 3 triggered ... correctly" severity NOTE;
Assert e8'value(e8str) = Three report "Assertion 4 triggered ... wrongly" severity FAILURE;
Assert e8val = Four report "Assertion 5 triggered ... correctly" severity NOTE;
Assert e8val = Two report "Assertion 6 triggered ... wrongly" severity FAILURE;
Assert e32'value("T1") = T2 report "Assertion 7 triggered ... correctly" severity NOTE;
Assert e32'value("T2") = T2 report "Assertion 8 triggered ... wrongly" severity FAILURE;
Assert e32'value(e32str_1) = T257 report "Assertion 9 triggered ... correctly" severity NOTE;
Assert e32'value(e32str_2) = T257 report "Assertion 10 triggered ... wrongly" severity FAILURE;
Assert e32val_1 = T260 report "Assertion 11 triggered ... correctly" severity NOTE;
Assert e32val_2 = T260 report "Assertion 12 triggered ... wrongly" severity FAILURE;
-- static image : enumeration
Assert e8_img1 = "One" report "Assertion 13 triggered ... correctly" severity NOTE;
Assert e8_img2 = "two" report "Assertion 14 triggered ... wrongly" severity FAILURE;
Assert e32_img1 = "T1" report "Assertion 15 triggered ... correctly" severity NOTE;
Assert e32_img2 = "t299" report "Assertion 16 triggered ... wrongly" severity FAILURE;
-------------- runtime value ----------------------
my_e8 <= Two after 10 ns;
my_e8_str <= "One" after 20 ns;
Assert my_e8 = One report "Assertion 17 triggered ... correctly" severity NOTE;
Assert my_e8 = Two report "Assertion 18 triggered ... correctly" severity NOTE;
Assert e_val(my_e8_str) = Three report "Assertion 19 triggered ... correctly" severity NOTE;
Assert e_val(my_e8_str) = Two report "Assertion 20 triggered ... wrongly except at 20ns" severity NOTE;
my_e32 <= T297 after 30 ns;
Assert my_e32 = T296 report "Assertion 21 triggered ... correctly" severity NOTE;
my_e32_str <= "T24" after 40 ns;
Assert e_val(my_e32_str) = T23 report "Assertion 22 triggered ... correctly" severity NOTE;
Assert e_val(my_e32_str) = T22 report "Assertion 23 triggered ... wrongly except at 40ns" severity NOTE;
-- Check white spaces and case.
assert e_val(" one") = one report "assertion 31" severity failure;
assert e_val(" one ") = one report "assertion 32" severity failure;
assert e_val("one ") = one report "assertion 33" severity failure;
assert e_val("oNe") = one report "assertion 34" severity failure;
assert e_val(" T1") = t1 report "assertion 35" severity failure;
assert e_val(" t2 ") = t2 report "assertion 36" severity failure;
assert e_val("t3 ") = t3 report "assertion 37" severity failure;
assert e_val("t39") = t39 report "assertion 38" severity failure;
assert t_val("1 ns") = 1 ns report "assertion 40" severity failure;
assert t_val(" 1 nS") = 1 ns report "assertion 41" severity failure;
assert t_val(" 1 Ns ") = 1 ns report "assertion 42" severity failure;
assert t_val(" -1.5 ns ") = -1500 ps report "assertion 44" severity failure;
-------------- runtime image ----------------------
-- runtime enumeration
sig_e8 <= Two after 50 ns, Four after 60 ns;
Assert sig_e8 = One report "Sig_e8 = " & e8'image(sig_e8) & " fn returns " & e_img(sig_e8) severity Note;
sig_e32 <= T124 after 70 ns, T125 after 80 ns;
Assert sig_e32 = T122 report "Sig_e32 = " & e32'image(sig_e32) & " fn returns " & e_img(sig_e32) severity Note;
end sim;
|
gpl-2.0
|
8d15cf8fbdf5fe9a9cee3f58d60a670c
| 0.615139 | 3.071633 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/numeric_bit.vhdl
| 4 | 63,654 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
package NUMERIC_BIT is
constant CopyRightNotice : STRING
:= "Copyright © 2008 IEEE. All rights reserved.";
--============================================================================
-- Numeric Array Type Definitions
--============================================================================
type UNSIGNED is array (NATURAL range <>) of BIT;
type SIGNED is array (NATURAL range <>) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG : SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG : SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit UNSIGNED
-- Id: A.3L
function "+"(L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.4
function "+" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.4R
function "+"(L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.4 where R is bit 0 of a non-negative.
-- Id: A.4L
function "+"(L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.4 where L is bit 0 of a non-negative.
-- Id: A.5
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Adds an UNSIGNED vector, L, with a nonnegative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Adds a nonnegative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.10
function "-" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.10R
function "-"(L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.10 where R is bit 0 of a non-negative.
-- Id: A.10L
function "-"(L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.10 where R is bit 0 of a non-negative.
-- Id: A.11
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Subtracts a nonnegative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Subtracts an UNSIGNED vector, R, from a nonnegative INTEGER, L.
-- Id: A.13
function "-" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies an UNSIGNED vector, L, with a nonnegative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies an UNSIGNED vector, R, with a nonnegative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a nonnegative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a nonnegative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- nonnegative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- nonnegative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a nonnegative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a nonnegative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : UNSIGNED; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.40
function find_leftmost (ARG : SIGNED; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : UNSIGNED; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.42
function find_rightmost (ARG : SIGNED; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.6
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.12
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.18
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.24
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.30
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.36
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.38
function MINIMUM (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the lesser of two SIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.40
function MINIMUM (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the lesser of an INTEGER, L, and a SIGNED
-- vector, R.
-- Id: C.41
function MINIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
-- Id: C.42
function MINIMUM (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the lesser of a SIGNED vector, L, and
-- an INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.44
function MAXIMUM (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the greater of two SIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.46
function MAXIMUM (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the greater of an INTEGER, L, and a SIGNED
-- vector, R.
-- Id: C.47
function MAXIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
-- Id: C.48
function MAXIMUM (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the greater of a SIGNED vector, L, and
-- an INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.50
function "?>" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.52
function "?>" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.53
function "?>" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.54
function "?>" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.56
function "?<" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.58
function "?<" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.59
function "?<" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.60
function "?<" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.62
function "?<=" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.64
function "?<=" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.65
function "?<=" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.66
function "?<=" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.68
function "?>=" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.70
function "?>=" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.71
function "?>=" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.72
function "?>=" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.74
function "?=" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.76
function "?=" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an INTEGER and
-- R is an SIGNED vector.
-- Id: C.77
function "?=" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.78
function "?=" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.80
function "?/=" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.82
function "?/=" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is an SIGNED vector.
-- Id: C.83
function "?/=" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.84
function "?/=" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG : SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0)
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0)
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.15
function "and" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector AND operation
-- Id: L.16
function "and" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar AND operation
-- Id: L.17
function "or" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector OR operation
-- Id: L.18
function "or" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar OR operation
-- Id: L.19
function "nand" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NAND operation
-- Id: L.20
function "nand" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NAND operation
-- Id: L.21
function "nor" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NOR operation
-- Id: L.22
function "nor" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NOR operation
-- Id: L.23
function "xor" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XOR operation
-- Id: L.24
function "xor" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XOR operation
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XNOR operation
-- Id: L.27
function "and" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector AND operation
-- Id: L.28
function "and" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar AND operation
-- Id: L.29
function "or" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector OR operation
-- Id: L.30
function "or" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar OR operation
-- Id: L.31
function "nand" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NAND operation
-- Id: L.32
function "nand" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NAND operation
-- Id: L.33
function "nor" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NOR operation
-- Id: L.34
function "nor" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NOR operation
-- Id: L.35
function "xor" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XOR operation
-- Id: L.36
function "xor" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XOR operation
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of and'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "nand" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of nand'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "or" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of or'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nor" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of nor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "xor" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of xor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "xnor" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of xnor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "and" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of and'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nand" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of nand'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "or" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of or'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "nor" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of nor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xor" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of xor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of xnor'ing all of the bits of the vector.
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
alias RISING_EDGE is STD.STANDARD.RISING_EDGE
[STD.STANDARD.BIT return STD.STANDARD.BOOLEAN];
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
alias FALLING_EDGE is STD.STANDARD.FALLING_EDGE
[STD.STANDARD.BIT return STD.STANDARD.BOOLEAN];
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
--============================================================================
-- string conversion and write operations
--============================================================================
-- the following operations are predefined
-- FUNCTION to_string ( value : UNSIGNED ) RETURN string;
-- FUNCTION to_string ( value : SIGNED ) RETURN string;
-- explicitly defined operations
alias to_bstring is to_string [UNSIGNED return STRING];
alias to_bstring is to_string [SIGNED return STRING];
alias to_binary_string is to_string [UNSIGNED return STRING];
alias to_binary_string is to_string [SIGNED return STRING];
function to_ostring (value : UNSIGNED) return STRING;
function to_ostring (value : SIGNED) return STRING;
alias to_octal_string is to_ostring [UNSIGNED return STRING];
alias to_octal_string is to_ostring [SIGNED return STRING];
function to_hstring (value : UNSIGNED) return STRING;
function to_hstring (value : SIGNED) return STRING;
alias to_hex_string is to_hstring [UNSIGNED return STRING];
alias to_hex_string is to_hstring [SIGNED return STRING];
procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNSIGNED);
procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out SIGNED);
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, UNSIGNED, BOOLEAN];
alias BREAD is READ [LINE, SIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNSIGNED];
alias BREAD is READ [LINE, SIGNED];
alias BINARY_READ is READ [LINE, UNSIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, SIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNSIGNED];
alias BINARY_READ is READ [LINE, SIGNED];
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure OREAD (L : inout LINE; VALUE : out SIGNED);
alias OCTAL_READ is OREAD [LINE, UNSIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, SIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNSIGNED];
alias OCTAL_READ is OREAD [LINE, SIGNED];
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure HREAD (L : inout LINE; VALUE : out SIGNED);
alias HEX_READ is HREAD [LINE, UNSIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, SIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNSIGNED];
alias HEX_READ is HREAD [LINE, SIGNED];
alias BWRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, SIGNED, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, SIGNED, SIDE, WIDTH];
end package NUMERIC_BIT;
|
gpl-2.0
|
abb901c2ba1b300dc104a6c7e65b6df3
| 0.562274 | 4.280124 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd
| 4 | 1,997 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity decoder_3_to_8 is
generic ( Tpd_01, Tpd_10 : delay_length );
port ( s0, s1, s2 : in bit;
enable : in bit;
y0, y1, y2, y3, y4, y5, y6, y7 : out bit );
end entity decoder_3_to_8;
-- not in book
architecture basic of decoder_3_to_8 is
begin
process (enable, s2, s1, s0) is
begin
if enable = '0' then
(y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000000");
else
case bit_vector'(s2, s1, s0) is
when "000" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000001");
when "001" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000010");
when "010" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000100");
when "011" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00001000");
when "100" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00010000");
when "101" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00100000");
when "110" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("01000000");
when "111" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("10000000");
end case;
end if;
end process;
end architecture basic;
-- end not in book
|
gpl-2.0
|
664dc36abb91c7bc8403b392d0f69d0c
| 0.612419 | 2.865136 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.a-ControlUnit.core/a.a.a-CwGenerator.vhd
| 1 | 10,864 |
--------------------------------------------------------------------------------
-- FILE: CwGenerator
-- DESC: Generate Control Word
--
-- Author:
-- Create: 2015-05-30
-- Update: 2015-09-02
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity CwGenerator is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE; -- Data Size
OPCD_SIZE : integer := C_SYS_OPCD_SIZE; -- Op Code Size
FUNC_SIZE : integer := C_SYS_FUNC_SIZE; -- Func Field Size for R-Type Ops
CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Control Word Size
CALU_SIZE : integer := C_CTR_CALU_SIZE -- ALU Op Code Word Size
);
port (
clk : in std_logic;
rst : in std_logic;
opcd : in std_logic_vector(OPCD_SIZE-1 downto 0):=(others=>'0');
func : in std_logic_vector(FUNC_SIZE-1 downto 0):=(others=>'0');
stall_flag : in std_logic_vector(4 downto 0):=(others=>'0');
taken : in std_logic;
cw : out std_logic_vector(CWRD_SIZE-1 downto 0):=(others=>'0');
calu : out std_logic_vector(CALU_SIZE-1 downto 0):=(others=>'0')
);
end CwGenerator;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture cw_generator_arch of CwGenerator is
constant PIPELINE_STAGE: integer := 5;
--constant UCODE_MEM_SIZE : integer := 2**OPCD_SIZE;
constant UCODE_MEM_SIZE : integer := 69;
constant RELOC_MEM_SIZE : integer := 64;
type ucode_mem_t is array (0 to UCODE_MEM_SIZE-1) of std_logic_vector(CWRD_SIZE-1 downto 0);
type reloc_mem_t is array (0 to RELOC_MEM_SIZE-1) of std_logic_vector(OPCD_SIZE+1 downto 0); -- Mul by 4, since each instruction need 4 stages, IF stage do not count.
signal stall1 : std_logic;
signal stall2 : std_logic;
signal stall3 : std_logic;
signal stall4 : std_logic;
signal stall5 : std_logic;
signal reloc_mem : reloc_mem_t := (
x"01", -- 0x00 R
x"01", -- 0x01 F
x"05", -- 0x02 J
x"09", -- 0x03 JAL
x"0d", -- 0x04 BEQZ
x"0d", -- 0x05 BNEZ
x"00", -- 0x06 UNUSED
x"00", -- 0x07 UNUSED
x"11", -- 0x08 ADDI
x"41", -- 0x09 ADDUI
x"11", -- 0x0a SUBI
x"41", -- 0x0b SUBUI
x"41", -- 0x0c ANDI
x"41", -- 0x0d ORI
x"41", -- 0x0e XORI
x"11", -- 0x0f LHI
x"00", -- 0x10 UNUSED
x"00", -- 0x11 UNUSED
x"15", -- 0x12 JR
x"19", -- 0x13 JALR
x"41", -- 0x14 SLLI
x"1d", -- 0x15 NOP
x"41", -- 0x16 SRLI
x"41", -- 0x17 SRAI
x"11", -- 0x18 SEQI
x"11", -- 0x19 SNEI
x"11", -- 0x1a SLTI
x"11", -- 0x1b SGTI
x"11", -- 0x1c SLEI
x"11", -- 0x1d SGEI
x"00", -- 0x1e UNUSED
x"00", -- 0x1f UNUSED
x"21", -- 0x20 LB
x"25", -- 0x21 LH
x"00", -- 0x22 UNUSED
x"29", -- 0x23 LW
x"2d", -- 0x24 LBU
x"31", -- 0x25 LHU
x"00", -- 0x26 UNUSED
x"00", -- 0x27 UNUSED
x"35", -- 0x28 SB
x"39", -- 0x29 SH
x"00", -- 0x2a UNUSED
x"3d", -- 0x2b SW
x"00", -- 0x2c UNUSED
x"00", -- 0x2d UNUSED
x"00", -- 0x2e UNUSED
x"00", -- 0x2f UNUSED
x"00", -- 0x30 UNUSED
x"00", -- 0x31 UNUSED
x"00", -- 0x32 UNUSED
x"00", -- 0x33 UNUSED
x"00", -- 0x34 UNUSED
x"00", -- 0x35 UNUSED
x"00", -- 0x36 UNUSED
x"00", -- 0x37 UNUSED
x"00", -- 0x38 UNUSED
x"00", -- 0x39 UNUSED
x"41", -- 0x3a SLTUI
x"41", -- 0x3b SGTUI
x"41", -- 0x3c SLEUI
x"41", -- 0x3d SGEUI
x"00", -- 0x3e UNUSED
x"00" -- 0x3f UNUSED
);
signal ucode_mem : ucode_mem_t := (
"00000000000000000000", -- 0x00 RESET
"00000000000001000000", -- 0x01 R [ID]
"00000000011000000000", -- R [EXE]
"01100000000000000000", -- R [MEM]
"10000000000000000000", -- R [WB]
"00000000000001000110", -- 0x05 J
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000001010110", -- 0x09 JAL
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000001100000", -- 0x0d BEQZ/BENZ
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000001100000", -- 0x11 ADDI/...
"00000000011010000000",
"01100000000000000000",
"10000000000000000000",
"00000000000001001010", -- 0x15 JR
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000001001010", -- 0x19 JALR
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000", -- 0x1d NOP
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000001000000", -- 0x21 LB
"00000000011110000000",
"01111010100000000000",
"10000000000000000000",
"00000000000001000000", -- 0x25 LH
"00000000011110000000",
"01111001100000000000",
"10000000000000000000",
"00000000000001000000", -- 0x29 LW
"00000000011110000000",
"01111000000000000000",
"10000000000000000000",
"00000000000001000000", -- 0x2d LBU
"00000000011110000000",
"01111010000000000000",
"10000000000000000000",
"00000000000001000000", -- 0x31 LHU
"00000000011110000000",
"01111001000000000000",
"10000000000000000000",
"00000000000001000000", -- 0x35 SB
"00000000010010000000",
"01000110000000000000",
"00000000000000000000",
"00000000000001000000", -- 0x39 SH
"00000000010010000000",
"01000101000000000000",
"00000000000000000000",
"00000000000001000000", -- 0x3d SW
"00000000010010000000",
"01000100000000000000",
"00000000000000000000",
"00000000000001000000", -- 0x41 ADDUI/...
"00000000011010000000",
"01100000000000000000",
"10000000000000000000"
);
signal cw1 : std_logic_vector(CWRD_SIZE-1 downto 0):=(CW_S1_LATCH=>'1', others=>'0');
signal cw2 : std_logic_vector(CWRD_SIZE-1 downto 0);
signal cw3 : std_logic_vector(CWRD_SIZE-1 downto 0);
signal cw4 : std_logic_vector(CWRD_SIZE-1 downto 0);
signal cw5 : std_logic_vector(CWRD_SIZE-1 downto 0);
signal cw_temp : std_logic_vector(CWRD_SIZE-1 downto 0);
signal cw_mask : std_logic_vector(CWRD_SIZE-1 downto 0);
signal upc2 : integer range 0 to 131072:=0;
signal upc3 : integer range 0 to 131072:=0;
signal upc4 : integer range 0 to 131072:=0;
signal upc5 : integer range 0 to 131072:=0;
signal i_count : integer range 0 to PIPELINE_STAGE;
signal relc : std_logic_vector(OPCD_SIZE+1 downto 0);
signal calu2 : std_logic_vector(CALU_SIZE-1 downto 0);
signal taken_flag: std_logic_vector(CWRD_SIZE-1 downto 0);
begin
cw1 <= (CW_S1_LATCH=>'1', others=>'0');
cw2 <= ucode_mem(upc2);
cw3 <= ucode_mem(upc3);
cw4 <= ucode_mem(upc4);
cw5 <= ucode_mem(upc5);
stall1 <= stall_flag(4);
stall2 <= stall_flag(3);
stall3 <= stall_flag(2);
stall4 <= stall_flag(1);
stall5 <= stall_flag(0);
cw_mask(CW_S1_LATCH downto 0) <= (others=> (not stall1));
cw_mask(CW_S2_LATCH downto CW_S1_LATCH+1) <= (others=> (not stall2));
cw_mask(CW_S3_LATCH downto CW_S2_LATCH+1) <= (others=> (not stall3));
cw_mask(CW_S4_LATCH downto CW_S3_LATCH+1) <= (others=> (not stall4));
cw_mask(CWRD_SIZE-1 downto CW_S4_LATCH+1) <= (others=> (not stall5));
taken_flag <= (CW_S2_JUMP => taken, others=>'0');
cw_temp <= (cw1 or cw2 or cw3 or cw4 or cw5 or taken_flag);
cw <= cw_temp and cw_mask;
relc <= reloc_mem(to_integer(unsigned(opcd)));
P_CALU: process (opcd, func)
begin
calu2 <= (others => '0');
if (opcd = OPCD_R) then
if (func=FUNC_ADD) or (func=FUNC_ADDU) then -- ADD
calu2 <= OP_ADD;
elsif (func=FUNC_AND) then -- AND
calu2 <= OP_AND;
elsif (func=FUNC_OR) then -- OR
calu2 <= OP_OR;
elsif (func=FUNC_XOR) then -- AND
calu2 <= OP_XOR;
elsif (func=FUNC_SLL) then -- SLL
calu2 <= OP_SLL;
elsif (func=FUNC_SRL) then -- SRL
calu2 <= OP_SRL;
elsif (func=FUNC_SRA) then -- SRA
calu2 <= OP_SRA;
elsif (func=FUNC_SUB) or (func=FUNC_SUBU) then -- SUB
calu2 <= OP_SUB;
elsif (func = FUNC_SGT) then -- SGT
calu2 <= OP_SGT;
elsif (func = FUNC_SGE) then -- SGE
calu2 <= OP_SGE;
elsif (func = FUNC_SLT) then -- SLT
calu2 <= OP_SLT;
elsif (func = FUNC_SLE) then -- SLE
calu2 <= OP_SLE;
elsif (func = FUNC_SGTU) then -- SGTU
calu2 <= OP_SGTU;
elsif (func = FUNC_SGEU) then -- SGEU
calu2 <= OP_SGEU;
elsif (func = FUNC_SLTU) then -- SLTU
calu2 <= OP_SLTU;
elsif (func = FUNC_SLEU) then -- SLEU
calu2 <= OP_SLEU;
elsif (func = FUNC_SEQ) then -- SEQ
calu2 <= OP_SEQ;
elsif (func = FUNC_SNE) then -- SNE
calu2 <= OP_SNE;
else
calu2 <= OP_ADD;
end if;
elsif (opcd=OPCD_F) then
if (func=FUNC_MULTU) then -- MULTU
calu2 <= OP_MULTU;
elsif (func=FUNC_MULT) then -- MULT
calu2 <= OP_MULT;
elsif (func=FUNC_DIVU) then -- DIVU
calu2 <= OP_DIVU;
elsif (func=FUNC_DIV) then -- DIV
calu2 <= OP_DIV;
elsif (func=FUNC_SQRT) then -- SQRT
calu2 <= OP_SQRT;
end if;
elsif (opcd=OPCD_ADDI) or (opcd=OPCD_ADDUI) then -- ADD
calu2 <= OP_ADD;
elsif (opcd=OPCD_SUBI) or (opcd=OPCD_SUBUI) then -- SUB
calu2 <= OP_SUB;
elsif opcd=OPCD_ANDI then -- AND
calu2 <= OP_AND;
elsif opcd=OPCD_ORI then -- OR
calu2 <= OP_OR;
elsif opcd=OPCD_XORI then -- XOR
calu2 <= OP_XOR;
elsif opcd=OPCD_SLLI then -- SLL
calu2 <= OP_SLL;
elsif opcd=OPCD_SRLI then -- SRL
calu2 <= OP_SRL;
elsif opcd=OPCD_SRAI then -- SRA
calu2 <= OP_SRA;
elsif opcd=OPCD_SEQI then -- SEQ
calu2 <= OP_SEQ;
elsif opcd=OPCD_SNEI then -- SNE
calu2 <= OP_SNE;
elsif opcd=OPCD_SLTI then -- SLT
calu2 <= OP_SLT;
elsif opcd=OPCD_SGTI then -- SGT
calu2 <= OP_SGT;
elsif opcd=OPCD_SLEI then -- SLE
calu2 <= OP_SLE;
elsif opcd=OPCD_SGEI then -- SGE
calu2 <= OP_SGE;
elsif opcd=OPCD_SLTUI then -- SLTU
calu2 <= OP_SLTU;
elsif opcd=OPCD_SGTUI then -- SGTU
calu2 <= OP_SGTU;
elsif opcd=OPCD_SLEUI then -- SLEU
calu2 <= OP_SLEU;
elsif opcd=OPCD_SGEUI then -- SGEU
calu2 <= OP_SGEU;
else
calu2 <= OP_ADD;
end if;
end process;
upc2 <= to_integer(unsigned(relc)) when (stall2='0') else 0 when (rst='0');
P_CW: process (clk, rst)
begin
if rst = '0' then
-- upc2 <= 0;
upc3 <= 0;
upc4 <= 0;
upc5 <= 0;
elsif clk'event and clk = '1' then
-- if stall2='0' then
-- upc2 <= to_integer(unsigned(relc));
-- end if;
if (upc2 /= 0) and (stall3='0') then
upc3 <= upc2+1;
calu <= calu2;
end if;
if (upc3 /= 0) and (stall4='0') then
upc4 <= upc3+1;
end if;
if (upc4 /= 0) and (stall5='0') then
upc5 <= upc4+1;
end if;
end if;
end process;
end cw_generator_arch;
|
mit
|
4235186b6c299e964e5d60316e1875bb
| 0.592139 | 2.711932 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/std_logic_1164-body.vhdl
| 4 | 57,352 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body std_logic_1164 is
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
type stdlogic_1d is array (STD_ULOGIC) of STD_ULOGIC;
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
constant resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'), -- | 0 |
('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'), -- | Z |
('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'), -- | W |
('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'), -- | L |
('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := 'Z'; -- weakest state default
begin
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
if (s'length = 1) then return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end function resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
constant and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U'), -- | U |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | X |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 1 |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | Z |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | W |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | H |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X') -- | - |
);
-- truth table for "or" function
constant or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U'), -- | U |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | Z |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | H |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X') -- | - |
);
-- truth table for "xor" function
constant xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
-- truth table for "not" function
constant not_table : stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X');
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (and_table(l, r));
end function "and";
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (and_table(l, r)));
end function "nand";
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (or_table(l, r));
end function "or";
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (or_table(l, r)));
end function "nor";
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (xor_table(l, r));
end function "xor";
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return ux01 is
begin
return not_table(xor_table(l, r));
end function "xnor";
function "not" (l : STD_ULOGIC) return UX01 is
begin
return (not_table(l));
end function "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := and_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(and_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := or_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(or_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := xor_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(xor_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "xnor";
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => 'X');
begin
for i in result'range loop
result(i) := not_table(lv(i));
end loop;
return result;
end function "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := and_table (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := and_table (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(and_table (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(and_table (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := or_table (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := or_table (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(or_table (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(or_table (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := xor_table (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := xor_table (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(xor_table (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(xor_table (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := and_table (l(i), result);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := and_table (l(i), result);
end loop;
return not_table(result);
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := or_table (l(i), result);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := or_table (l(i), result);
end loop;
return not_table(result);
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := xor_table (l(i), result);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := xor_table (l(i), result);
end loop;
return not_table(result);
end function "xnor";
-------------------------------------------------------------------
-- shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
type logic_x01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01;
type logic_x01z_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01Z;
type logic_ux01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT is
begin
case s is
when '0' | 'L' => return ('0');
when '1' | 'H' => return ('1');
when others => return xmap;
end case;
end function To_bit;
--------------------------------------------------------------------
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0')
return BIT_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : BIT_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
case sv(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := xmap;
end case;
end loop;
return result;
end function To_bitvector;
--------------------------------------------------------------------
function To_StdULogic (b : BIT) return STD_ULOGIC is
begin
case b is
when '0' => return '0';
when '1' => return '1';
end case;
end function To_StdULogic;
--------------------------------------------------------------------
function To_StdLogicVector (b : BIT_VECTOR)
return STD_LOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_LOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_StdLogicVector;
--------------------------------------------------------------------
function To_StdLogicVector (s : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_LOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end function To_StdLogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (b : BIT_VECTOR)
return STD_ULOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_ULOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_StdULogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (s : STD_LOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_ULOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end function To_StdULogicVector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR
is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0') return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR
is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0') return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01 (sv(i));
end loop;
return result;
end function To_X01;
--------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC) return X01 is
begin
return (cvt_to_x01(s));
end function To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT) return X01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_X01;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01z (sv(i));
end loop;
return result;
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (s : STD_ULOGIC) return X01Z is
begin
return (cvt_to_x01z(s));
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT) return X01Z is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_X01Z;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_ux01 (sv(i));
end loop;
return result;
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (s : STD_ULOGIC) return UX01 is
begin
return (cvt_to_ux01(s));
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT) return UX01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_UX01;
function "??" (l : STD_ULOGIC) return BOOLEAN is
begin
return l = '1' or l = 'H';
end function "??";
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '1') and
(To_X01(s'last_value) = '0'));
end function rising_edge;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '0') and
(To_X01(s'last_value) = '1'));
end function falling_edge;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
for i in s'range loop
case s(i) is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
end loop;
return false;
end function Is_X;
--------------------------------------------------------------------
function Is_X (s : STD_ULOGIC) return BOOLEAN is
begin
case s is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
return false;
end function Is_X;
-------------------------------------------------------------------
-- string conversion and write operations
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant result_length : NATURAL := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(1 to result_length*3 - value'length);
variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*3);
variable result : STRING(1 to result_length);
variable tri : STD_ULOGIC_VECTOR(1 to 3);
begin
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
padded_value := pad & value;
for i in 1 to result_length loop
tri := To_X01Z(padded_value(3*i-2 to 3*i));
case tri is
when o"0" => result(i) := '0';
when o"1" => result(i) := '1';
when o"2" => result(i) := '2';
when o"3" => result(i) := '3';
when o"4" => result(i) := '4';
when o"5" => result(i) := '5';
when o"6" => result(i) := '6';
when o"7" => result(i) := '7';
when "ZZZ" => result(i) := 'Z';
when others => result(i) := 'X';
end case;
end loop;
return result;
end function to_ostring;
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant result_length : NATURAL := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(1 to result_length*4 - value'length);
variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*4);
variable result : STRING(1 to result_length);
variable quad : STD_ULOGIC_VECTOR(1 to 4);
begin
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
padded_value := pad & value;
for i in 1 to result_length loop
quad := To_X01Z(padded_value(4*i-3 to 4*i));
case quad is
when x"0" => result(i) := '0';
when x"1" => result(i) := '1';
when x"2" => result(i) := '2';
when x"3" => result(i) := '3';
when x"4" => result(i) := '4';
when x"5" => result(i) := '5';
when x"6" => result(i) := '6';
when x"7" => result(i) := '7';
when x"8" => result(i) := '8';
when x"9" => result(i) := '9';
when x"A" => result(i) := 'A';
when x"B" => result(i) := 'B';
when x"C" => result(i) := 'C';
when x"D" => result(i) := 'D';
when x"E" => result(i) := 'E';
when x"F" => result(i) := 'F';
when "ZZZZ" => result(i) := 'Z';
when others => result(i) := 'X';
end case;
end loop;
return result;
end function to_hstring;
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
c := l (l'left);
if c = ' ' or c = NBSP or c = HT then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := true;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then
good := false; -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
alias m : STD_ULOGIC_VECTOR(1 to VALUE'length) is VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
procedure Char2TriBits (C : in CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
end package body std_logic_1164;
|
gpl-2.0
|
885adc1fcdee1a74bcad1d8345799005
| 0.438276 | 3.976702 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_163_2.vhd
| 1 | 21,010 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- Con celda y configuration maquina de estados
--------------------------------------------------------
-- x^163 + x^7 + x^6 + x^3 + 1
entity serial_multiplier is
generic (
NUM_BITS : positive := 163 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier;
-----------------------------------------------------------
architecture behave of serial_multiplier is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
signal xor_2 : std_logic;
signal xor_3 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
-- Result of the multiplication
xor_1 <= Cx_int(2) xor Cx_int(NUM_BITS-1);
xor_2 <= Cx_int(5) xor Cx_int(NUM_BITS-1);
xor_3 <= Cx_int(6) xor Cx_int(NUM_BITS-1);
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
CELL_0: ENTITY basic_cell(behave)
PORT MAP(Ax(0),Bx_int(NUM_BITS-1),Cx_int(NUM_BITS-1),clk,reset,Cx_int(0));
CELL_1: ENTITY basic_cell(behave)
PORT MAP(Ax(1),Bx_int(NUM_BITS-1),Cx_int(0),clk,reset,Cx_int(1));
CELL_2: ENTITY basic_cell(behave)
PORT MAP(Ax(2),Bx_int(NUM_BITS-1),Cx_int(1),clk,reset,Cx_int(2));
CELL_3: ENTITY basic_cell(behave)
PORT MAP(Ax(3),Bx_int(NUM_BITS-1),xor_1,clk,reset,Cx_int(3));
CELL_4: ENTITY basic_cell(behave)
PORT MAP(Ax(4),Bx_int(NUM_BITS-1),Cx_int(3),clk,reset,Cx_int(4));
CELL_5: ENTITY basic_cell(behave)
PORT MAP(Ax(5),Bx_int(NUM_BITS-1),Cx_int(4),clk,reset,Cx_int(5));
CELL_6: ENTITY basic_cell(behave)
PORT MAP(Ax(6),Bx_int(NUM_BITS-1),xor_2,clk,reset,Cx_int(6));
CELL_7: ENTITY basic_cell(behave)
PORT MAP(Ax(7),Bx_int(NUM_BITS-1),xor_3,clk,reset,Cx_int(7));
CELL_8: ENTITY basic_cell(behave)
PORT MAP(Ax(8),Bx_int(NUM_BITS-1),Cx_int(7),clk,reset,Cx_int(8));
CELL_9: ENTITY basic_cell(behave)
PORT MAP(Ax(9),Bx_int(NUM_BITS-1),Cx_int(8),clk,reset,Cx_int(9));
CELL_10: ENTITY basic_cell(behave)
PORT MAP(Ax(10),Bx_int(NUM_BITS-1),Cx_int(9),clk,reset,Cx_int(10));
CELL_11: ENTITY basic_cell(behave)
PORT MAP(Ax(11),Bx_int(NUM_BITS-1),Cx_int(10),clk,reset,Cx_int(11));
CELL_12: ENTITY basic_cell(behave)
PORT MAP(Ax(12),Bx_int(NUM_BITS-1),Cx_int(11),clk,reset,Cx_int(12));
CELL_13: ENTITY basic_cell(behave)
PORT MAP(Ax(13),Bx_int(NUM_BITS-1),Cx_int(12),clk,reset,Cx_int(13));
CELL_14: ENTITY basic_cell(behave)
PORT MAP(Ax(14),Bx_int(NUM_BITS-1),Cx_int(13),clk,reset,Cx_int(14));
CELL_15: ENTITY basic_cell(behave)
PORT MAP(Ax(15),Bx_int(NUM_BITS-1),Cx_int(14),clk,reset,Cx_int(15));
CELL_16: ENTITY basic_cell(behave)
PORT MAP(Ax(16),Bx_int(NUM_BITS-1),Cx_int(15),clk,reset,Cx_int(16));
CELL_17: ENTITY basic_cell(behave)
PORT MAP(Ax(17),Bx_int(NUM_BITS-1),Cx_int(16),clk,reset,Cx_int(17));
CELL_18: ENTITY basic_cell(behave)
PORT MAP(Ax(18),Bx_int(NUM_BITS-1),Cx_int(17),clk,reset,Cx_int(18));
CELL_19: ENTITY basic_cell(behave)
PORT MAP(Ax(19),Bx_int(NUM_BITS-1),Cx_int(18),clk,reset,Cx_int(19));
CELL_20: ENTITY basic_cell(behave)
PORT MAP(Ax(20),Bx_int(NUM_BITS-1),Cx_int(19),clk,reset,Cx_int(20));
CELL_21: ENTITY basic_cell(behave)
PORT MAP(Ax(21),Bx_int(NUM_BITS-1),Cx_int(20),clk,reset,Cx_int(21));
CELL_22: ENTITY basic_cell(behave)
PORT MAP(Ax(22),Bx_int(NUM_BITS-1),Cx_int(21),clk,reset,Cx_int(22));
CELL_23: ENTITY basic_cell(behave)
PORT MAP(Ax(23),Bx_int(NUM_BITS-1),Cx_int(22),clk,reset,Cx_int(23));
CELL_24: ENTITY basic_cell(behave)
PORT MAP(Ax(24),Bx_int(NUM_BITS-1),Cx_int(23),clk,reset,Cx_int(24));
CELL_25: ENTITY basic_cell(behave)
PORT MAP(Ax(25),Bx_int(NUM_BITS-1),Cx_int(24),clk,reset,Cx_int(25));
CELL_26: ENTITY basic_cell(behave)
PORT MAP(Ax(26),Bx_int(NUM_BITS-1),Cx_int(25),clk,reset,Cx_int(26));
CELL_27: ENTITY basic_cell(behave)
PORT MAP(Ax(27),Bx_int(NUM_BITS-1),Cx_int(26),clk,reset,Cx_int(27));
CELL_28: ENTITY basic_cell(behave)
PORT MAP(Ax(28),Bx_int(NUM_BITS-1),Cx_int(27),clk,reset,Cx_int(28));
CELL_29: ENTITY basic_cell(behave)
PORT MAP(Ax(29),Bx_int(NUM_BITS-1),Cx_int(28),clk,reset,Cx_int(29));
CELL_30: ENTITY basic_cell(behave)
PORT MAP(Ax(30),Bx_int(NUM_BITS-1),Cx_int(29),clk,reset,Cx_int(30));
CELL_31: ENTITY basic_cell(behave)
PORT MAP(Ax(31),Bx_int(NUM_BITS-1),Cx_int(30),clk,reset,Cx_int(31));
CELL_32: ENTITY basic_cell(behave)
PORT MAP(Ax(32),Bx_int(NUM_BITS-1),Cx_int(31),clk,reset,Cx_int(32));
CELL_33: ENTITY basic_cell(behave)
PORT MAP(Ax(33),Bx_int(NUM_BITS-1),Cx_int(32),clk,reset,Cx_int(33));
CELL_34: ENTITY basic_cell(behave)
PORT MAP(Ax(34),Bx_int(NUM_BITS-1),Cx_int(33),clk,reset,Cx_int(34));
CELL_35: ENTITY basic_cell(behave)
PORT MAP(Ax(35),Bx_int(NUM_BITS-1),Cx_int(34),clk,reset,Cx_int(35));
CELL_36: ENTITY basic_cell(behave)
PORT MAP(Ax(36),Bx_int(NUM_BITS-1),Cx_int(35),clk,reset,Cx_int(36));
CELL_37: ENTITY basic_cell(behave)
PORT MAP(Ax(37),Bx_int(NUM_BITS-1),Cx_int(36),clk,reset,Cx_int(37));
CELL_38: ENTITY basic_cell(behave)
PORT MAP(Ax(38),Bx_int(NUM_BITS-1),Cx_int(37),clk,reset,Cx_int(38));
CELL_39: ENTITY basic_cell(behave)
PORT MAP(Ax(39),Bx_int(NUM_BITS-1),Cx_int(38),clk,reset,Cx_int(39));
CELL_40: ENTITY basic_cell(behave)
PORT MAP(Ax(40),Bx_int(NUM_BITS-1),Cx_int(39),clk,reset,Cx_int(40));
CELL_41: ENTITY basic_cell(behave)
PORT MAP(Ax(41),Bx_int(NUM_BITS-1),Cx_int(40),clk,reset,Cx_int(41));
CELL_42: ENTITY basic_cell(behave)
PORT MAP(Ax(42),Bx_int(NUM_BITS-1),Cx_int(41),clk,reset,Cx_int(42));
CELL_43: ENTITY basic_cell(behave)
PORT MAP(Ax(43),Bx_int(NUM_BITS-1),Cx_int(42),clk,reset,Cx_int(43));
CELL_44: ENTITY basic_cell(behave)
PORT MAP(Ax(44),Bx_int(NUM_BITS-1),Cx_int(43),clk,reset,Cx_int(44));
CELL_45: ENTITY basic_cell(behave)
PORT MAP(Ax(45),Bx_int(NUM_BITS-1),Cx_int(44),clk,reset,Cx_int(45));
CELL_46: ENTITY basic_cell(behave)
PORT MAP(Ax(46),Bx_int(NUM_BITS-1),Cx_int(45),clk,reset,Cx_int(46));
CELL_47: ENTITY basic_cell(behave)
PORT MAP(Ax(47),Bx_int(NUM_BITS-1),Cx_int(46),clk,reset,Cx_int(47));
CELL_48: ENTITY basic_cell(behave)
PORT MAP(Ax(48),Bx_int(NUM_BITS-1),Cx_int(47),clk,reset,Cx_int(48));
CELL_49: ENTITY basic_cell(behave)
PORT MAP(Ax(49),Bx_int(NUM_BITS-1),Cx_int(48),clk,reset,Cx_int(49));
CELL_50: ENTITY basic_cell(behave)
PORT MAP(Ax(50),Bx_int(NUM_BITS-1),Cx_int(49),clk,reset,Cx_int(50));
CELL_51: ENTITY basic_cell(behave)
PORT MAP(Ax(51),Bx_int(NUM_BITS-1),Cx_int(50),clk,reset,Cx_int(51));
CELL_52: ENTITY basic_cell(behave)
PORT MAP(Ax(52),Bx_int(NUM_BITS-1),Cx_int(51),clk,reset,Cx_int(52));
CELL_53: ENTITY basic_cell(behave)
PORT MAP(Ax(53),Bx_int(NUM_BITS-1),Cx_int(52),clk,reset,Cx_int(53));
CELL_54: ENTITY basic_cell(behave)
PORT MAP(Ax(54),Bx_int(NUM_BITS-1),Cx_int(53),clk,reset,Cx_int(54));
CELL_55: ENTITY basic_cell(behave)
PORT MAP(Ax(55),Bx_int(NUM_BITS-1),Cx_int(54),clk,reset,Cx_int(55));
CELL_56: ENTITY basic_cell(behave)
PORT MAP(Ax(56),Bx_int(NUM_BITS-1),Cx_int(55),clk,reset,Cx_int(56));
CELL_57: ENTITY basic_cell(behave)
PORT MAP(Ax(57),Bx_int(NUM_BITS-1),Cx_int(56),clk,reset,Cx_int(57));
CELL_58: ENTITY basic_cell(behave)
PORT MAP(Ax(58),Bx_int(NUM_BITS-1),Cx_int(57),clk,reset,Cx_int(58));
CELL_59: ENTITY basic_cell(behave)
PORT MAP(Ax(59),Bx_int(NUM_BITS-1),Cx_int(58),clk,reset,Cx_int(59));
CELL_60: ENTITY basic_cell(behave)
PORT MAP(Ax(60),Bx_int(NUM_BITS-1),Cx_int(59),clk,reset,Cx_int(60));
CELL_61: ENTITY basic_cell(behave)
PORT MAP(Ax(61),Bx_int(NUM_BITS-1),Cx_int(60),clk,reset,Cx_int(61));
CELL_62: ENTITY basic_cell(behave)
PORT MAP(Ax(62),Bx_int(NUM_BITS-1),Cx_int(61),clk,reset,Cx_int(62));
CELL_63: ENTITY basic_cell(behave)
PORT MAP(Ax(63),Bx_int(NUM_BITS-1),Cx_int(62),clk,reset,Cx_int(63));
CELL_64: ENTITY basic_cell(behave)
PORT MAP(Ax(64),Bx_int(NUM_BITS-1),Cx_int(63),clk,reset,Cx_int(64));
CELL_65: ENTITY basic_cell(behave)
PORT MAP(Ax(65),Bx_int(NUM_BITS-1),Cx_int(64),clk,reset,Cx_int(65));
CELL_66: ENTITY basic_cell(behave)
PORT MAP(Ax(66),Bx_int(NUM_BITS-1),Cx_int(65),clk,reset,Cx_int(66));
CELL_67: ENTITY basic_cell(behave)
PORT MAP(Ax(67),Bx_int(NUM_BITS-1),Cx_int(66),clk,reset,Cx_int(67));
CELL_68: ENTITY basic_cell(behave)
PORT MAP(Ax(68),Bx_int(NUM_BITS-1),Cx_int(67),clk,reset,Cx_int(68));
CELL_69: ENTITY basic_cell(behave)
PORT MAP(Ax(69),Bx_int(NUM_BITS-1),Cx_int(68),clk,reset,Cx_int(69));
CELL_70: ENTITY basic_cell(behave)
PORT MAP(Ax(70),Bx_int(NUM_BITS-1),Cx_int(69),clk,reset,Cx_int(70));
CELL_71: ENTITY basic_cell(behave)
PORT MAP(Ax(71),Bx_int(NUM_BITS-1),Cx_int(70),clk,reset,Cx_int(71));
CELL_72: ENTITY basic_cell(behave)
PORT MAP(Ax(72),Bx_int(NUM_BITS-1),Cx_int(71),clk,reset,Cx_int(72));
CELL_73: ENTITY basic_cell(behave)
PORT MAP(Ax(73),Bx_int(NUM_BITS-1),Cx_int(72),clk,reset,Cx_int(73));
CELL_74: ENTITY basic_cell(behave)
PORT MAP(Ax(74),Bx_int(NUM_BITS-1),Cx_int(73),clk,reset,Cx_int(74));
CELL_75: ENTITY basic_cell(behave)
PORT MAP(Ax(75),Bx_int(NUM_BITS-1),Cx_int(74),clk,reset,Cx_int(75));
CELL_76: ENTITY basic_cell(behave)
PORT MAP(Ax(76),Bx_int(NUM_BITS-1),Cx_int(75),clk,reset,Cx_int(76));
CELL_77: ENTITY basic_cell(behave)
PORT MAP(Ax(77),Bx_int(NUM_BITS-1),Cx_int(76),clk,reset,Cx_int(77));
CELL_78: ENTITY basic_cell(behave)
PORT MAP(Ax(78),Bx_int(NUM_BITS-1),Cx_int(77),clk,reset,Cx_int(78));
CELL_79: ENTITY basic_cell(behave)
PORT MAP(Ax(79),Bx_int(NUM_BITS-1),Cx_int(78),clk,reset,Cx_int(79));
CELL_80: ENTITY basic_cell(behave)
PORT MAP(Ax(80),Bx_int(NUM_BITS-1),Cx_int(79),clk,reset,Cx_int(80));
CELL_81: ENTITY basic_cell(behave)
PORT MAP(Ax(81),Bx_int(NUM_BITS-1),Cx_int(80),clk,reset,Cx_int(81));
CELL_82: ENTITY basic_cell(behave)
PORT MAP(Ax(82),Bx_int(NUM_BITS-1),Cx_int(81),clk,reset,Cx_int(82));
CELL_83: ENTITY basic_cell(behave)
PORT MAP(Ax(83),Bx_int(NUM_BITS-1),Cx_int(82),clk,reset,Cx_int(83));
CELL_84: ENTITY basic_cell(behave)
PORT MAP(Ax(84),Bx_int(NUM_BITS-1),Cx_int(83),clk,reset,Cx_int(84));
CELL_85: ENTITY basic_cell(behave)
PORT MAP(Ax(85),Bx_int(NUM_BITS-1),Cx_int(84),clk,reset,Cx_int(85));
CELL_86: ENTITY basic_cell(behave)
PORT MAP(Ax(86),Bx_int(NUM_BITS-1),Cx_int(85),clk,reset,Cx_int(86));
CELL_87: ENTITY basic_cell(behave)
PORT MAP(Ax(87),Bx_int(NUM_BITS-1),Cx_int(86),clk,reset,Cx_int(87));
CELL_88: ENTITY basic_cell(behave)
PORT MAP(Ax(88),Bx_int(NUM_BITS-1),Cx_int(87),clk,reset,Cx_int(88));
CELL_89: ENTITY basic_cell(behave)
PORT MAP(Ax(89),Bx_int(NUM_BITS-1),Cx_int(88),clk,reset,Cx_int(89));
CELL_90: ENTITY basic_cell(behave)
PORT MAP(Ax(90),Bx_int(NUM_BITS-1),Cx_int(89),clk,reset,Cx_int(90));
CELL_91: ENTITY basic_cell(behave)
PORT MAP(Ax(91),Bx_int(NUM_BITS-1),Cx_int(90),clk,reset,Cx_int(91));
CELL_92: ENTITY basic_cell(behave)
PORT MAP(Ax(92),Bx_int(NUM_BITS-1),Cx_int(91),clk,reset,Cx_int(92));
CELL_93: ENTITY basic_cell(behave)
PORT MAP(Ax(93),Bx_int(NUM_BITS-1),Cx_int(92),clk,reset,Cx_int(93));
CELL_94: ENTITY basic_cell(behave)
PORT MAP(Ax(94),Bx_int(NUM_BITS-1),Cx_int(93),clk,reset,Cx_int(94));
CELL_95: ENTITY basic_cell(behave)
PORT MAP(Ax(95),Bx_int(NUM_BITS-1),Cx_int(94),clk,reset,Cx_int(95));
CELL_96: ENTITY basic_cell(behave)
PORT MAP(Ax(96),Bx_int(NUM_BITS-1),Cx_int(95),clk,reset,Cx_int(96));
CELL_97: ENTITY basic_cell(behave)
PORT MAP(Ax(97),Bx_int(NUM_BITS-1),Cx_int(96),clk,reset,Cx_int(97));
CELL_98: ENTITY basic_cell(behave)
PORT MAP(Ax(98),Bx_int(NUM_BITS-1),Cx_int(97),clk,reset,Cx_int(98));
CELL_99: ENTITY basic_cell(behave)
PORT MAP(Ax(99),Bx_int(NUM_BITS-1),Cx_int(98),clk,reset,Cx_int(99));
CELL_100: ENTITY basic_cell(behave)
PORT MAP(Ax(100),Bx_int(NUM_BITS-1),Cx_int(99),clk,reset,Cx_int(100));
CELL_101: ENTITY basic_cell(behave)
PORT MAP(Ax(101),Bx_int(NUM_BITS-1),Cx_int(100),clk,reset,Cx_int(101));
CELL_102: ENTITY basic_cell(behave)
PORT MAP(Ax(102),Bx_int(NUM_BITS-1),Cx_int(101),clk,reset,Cx_int(102));
CELL_103: ENTITY basic_cell(behave)
PORT MAP(Ax(103),Bx_int(NUM_BITS-1),Cx_int(102),clk,reset,Cx_int(103));
CELL_104: ENTITY basic_cell(behave)
PORT MAP(Ax(104),Bx_int(NUM_BITS-1),Cx_int(103),clk,reset,Cx_int(104));
CELL_105: ENTITY basic_cell(behave)
PORT MAP(Ax(105),Bx_int(NUM_BITS-1),Cx_int(104),clk,reset,Cx_int(105));
CELL_106: ENTITY basic_cell(behave)
PORT MAP(Ax(106),Bx_int(NUM_BITS-1),Cx_int(105),clk,reset,Cx_int(106));
CELL_107: ENTITY basic_cell(behave)
PORT MAP(Ax(107),Bx_int(NUM_BITS-1),Cx_int(106),clk,reset,Cx_int(107));
CELL_108: ENTITY basic_cell(behave)
PORT MAP(Ax(108),Bx_int(NUM_BITS-1),Cx_int(107),clk,reset,Cx_int(108));
CELL_109: ENTITY basic_cell(behave)
PORT MAP(Ax(109),Bx_int(NUM_BITS-1),Cx_int(108),clk,reset,Cx_int(109));
CELL_110: ENTITY basic_cell(behave)
PORT MAP(Ax(110),Bx_int(NUM_BITS-1),Cx_int(109),clk,reset,Cx_int(110));
CELL_111: ENTITY basic_cell(behave)
PORT MAP(Ax(111),Bx_int(NUM_BITS-1),Cx_int(110),clk,reset,Cx_int(111));
CELL_112: ENTITY basic_cell(behave)
PORT MAP(Ax(112),Bx_int(NUM_BITS-1),Cx_int(111),clk,reset,Cx_int(112));
CELL_113: ENTITY basic_cell(behave)
PORT MAP(Ax(113),Bx_int(NUM_BITS-1),Cx_int(112),clk,reset,Cx_int(113));
CELL_114: ENTITY basic_cell(behave)
PORT MAP(Ax(114),Bx_int(NUM_BITS-1),Cx_int(113),clk,reset,Cx_int(114));
CELL_115: ENTITY basic_cell(behave)
PORT MAP(Ax(115),Bx_int(NUM_BITS-1),Cx_int(114),clk,reset,Cx_int(115));
CELL_116: ENTITY basic_cell(behave)
PORT MAP(Ax(116),Bx_int(NUM_BITS-1),Cx_int(115),clk,reset,Cx_int(116));
CELL_117: ENTITY basic_cell(behave)
PORT MAP(Ax(117),Bx_int(NUM_BITS-1),Cx_int(116),clk,reset,Cx_int(117));
CELL_118: ENTITY basic_cell(behave)
PORT MAP(Ax(118),Bx_int(NUM_BITS-1),Cx_int(117),clk,reset,Cx_int(118));
CELL_119: ENTITY basic_cell(behave)
PORT MAP(Ax(119),Bx_int(NUM_BITS-1),Cx_int(118),clk,reset,Cx_int(119));
CELL_120: ENTITY basic_cell(behave)
PORT MAP(Ax(120),Bx_int(NUM_BITS-1),Cx_int(119),clk,reset,Cx_int(120));
CELL_121: ENTITY basic_cell(behave)
PORT MAP(Ax(121),Bx_int(NUM_BITS-1),Cx_int(120),clk,reset,Cx_int(121));
CELL_122: ENTITY basic_cell(behave)
PORT MAP(Ax(122),Bx_int(NUM_BITS-1),Cx_int(121),clk,reset,Cx_int(122));
CELL_123: ENTITY basic_cell(behave)
PORT MAP(Ax(123),Bx_int(NUM_BITS-1),Cx_int(122),clk,reset,Cx_int(123));
CELL_124: ENTITY basic_cell(behave)
PORT MAP(Ax(124),Bx_int(NUM_BITS-1),Cx_int(123),clk,reset,Cx_int(124));
CELL_125: ENTITY basic_cell(behave)
PORT MAP(Ax(125),Bx_int(NUM_BITS-1),Cx_int(124),clk,reset,Cx_int(125));
CELL_126: ENTITY basic_cell(behave)
PORT MAP(Ax(126),Bx_int(NUM_BITS-1),Cx_int(125),clk,reset,Cx_int(126));
CELL_127: ENTITY basic_cell(behave)
PORT MAP(Ax(127),Bx_int(NUM_BITS-1),Cx_int(126),clk,reset,Cx_int(127));
CELL_128: ENTITY basic_cell(behave)
PORT MAP(Ax(128),Bx_int(NUM_BITS-1),Cx_int(127),clk,reset,Cx_int(128));
CELL_129: ENTITY basic_cell(behave)
PORT MAP(Ax(129),Bx_int(NUM_BITS-1),Cx_int(128),clk,reset,Cx_int(129));
CELL_130: ENTITY basic_cell(behave)
PORT MAP(Ax(130),Bx_int(NUM_BITS-1),Cx_int(129),clk,reset,Cx_int(130));
CELL_131: ENTITY basic_cell(behave)
PORT MAP(Ax(131),Bx_int(NUM_BITS-1),Cx_int(130),clk,reset,Cx_int(131));
CELL_132: ENTITY basic_cell(behave)
PORT MAP(Ax(132),Bx_int(NUM_BITS-1),Cx_int(131),clk,reset,Cx_int(132));
CELL_133: ENTITY basic_cell(behave)
PORT MAP(Ax(133),Bx_int(NUM_BITS-1),Cx_int(132),clk,reset,Cx_int(133));
CELL_134: ENTITY basic_cell(behave)
PORT MAP(Ax(134),Bx_int(NUM_BITS-1),Cx_int(133),clk,reset,Cx_int(134));
CELL_135: ENTITY basic_cell(behave)
PORT MAP(Ax(135),Bx_int(NUM_BITS-1),Cx_int(134),clk,reset,Cx_int(135));
CELL_136: ENTITY basic_cell(behave)
PORT MAP(Ax(136),Bx_int(NUM_BITS-1),Cx_int(135),clk,reset,Cx_int(136));
CELL_137: ENTITY basic_cell(behave)
PORT MAP(Ax(137),Bx_int(NUM_BITS-1),Cx_int(136),clk,reset,Cx_int(137));
CELL_138: ENTITY basic_cell(behave)
PORT MAP(Ax(138),Bx_int(NUM_BITS-1),Cx_int(137),clk,reset,Cx_int(138));
CELL_139: ENTITY basic_cell(behave)
PORT MAP(Ax(139),Bx_int(NUM_BITS-1),Cx_int(138),clk,reset,Cx_int(139));
CELL_140: ENTITY basic_cell(behave)
PORT MAP(Ax(140),Bx_int(NUM_BITS-1),Cx_int(139),clk,reset,Cx_int(140));
CELL_141: ENTITY basic_cell(behave)
PORT MAP(Ax(141),Bx_int(NUM_BITS-1),Cx_int(140),clk,reset,Cx_int(141));
CELL_142: ENTITY basic_cell(behave)
PORT MAP(Ax(142),Bx_int(NUM_BITS-1),Cx_int(141),clk,reset,Cx_int(142));
CELL_143: ENTITY basic_cell(behave)
PORT MAP(Ax(143),Bx_int(NUM_BITS-1),Cx_int(142),clk,reset,Cx_int(143));
CELL_144: ENTITY basic_cell(behave)
PORT MAP(Ax(144),Bx_int(NUM_BITS-1),Cx_int(143),clk,reset,Cx_int(144));
CELL_145: ENTITY basic_cell(behave)
PORT MAP(Ax(145),Bx_int(NUM_BITS-1),Cx_int(144),clk,reset,Cx_int(145));
CELL_146: ENTITY basic_cell(behave)
PORT MAP(Ax(146),Bx_int(NUM_BITS-1),Cx_int(145),clk,reset,Cx_int(146));
CELL_147: ENTITY basic_cell(behave)
PORT MAP(Ax(147),Bx_int(NUM_BITS-1),Cx_int(146),clk,reset,Cx_int(147));
CELL_148: ENTITY basic_cell(behave)
PORT MAP(Ax(148),Bx_int(NUM_BITS-1),Cx_int(147),clk,reset,Cx_int(148));
CELL_149: ENTITY basic_cell(behave)
PORT MAP(Ax(149),Bx_int(NUM_BITS-1),Cx_int(148),clk,reset,Cx_int(149));
CELL_150: ENTITY basic_cell(behave)
PORT MAP(Ax(150),Bx_int(NUM_BITS-1),Cx_int(149),clk,reset,Cx_int(150));
CELL_151: ENTITY basic_cell(behave)
PORT MAP(Ax(151),Bx_int(NUM_BITS-1),Cx_int(150),clk,reset,Cx_int(151));
CELL_152: ENTITY basic_cell(behave)
PORT MAP(Ax(152),Bx_int(NUM_BITS-1),Cx_int(151),clk,reset,Cx_int(152));
CELL_153: ENTITY basic_cell(behave)
PORT MAP(Ax(153),Bx_int(NUM_BITS-1),Cx_int(152),clk,reset,Cx_int(153));
CELL_154: ENTITY basic_cell(behave)
PORT MAP(Ax(154),Bx_int(NUM_BITS-1),Cx_int(153),clk,reset,Cx_int(154));
CELL_155: ENTITY basic_cell(behave)
PORT MAP(Ax(155),Bx_int(NUM_BITS-1),Cx_int(154),clk,reset,Cx_int(155));
CELL_156: ENTITY basic_cell(behave)
PORT MAP(Ax(156),Bx_int(NUM_BITS-1),Cx_int(155),clk,reset,Cx_int(156));
CELL_157: ENTITY basic_cell(behave)
PORT MAP(Ax(157),Bx_int(NUM_BITS-1),Cx_int(156),clk,reset,Cx_int(157));
CELL_158: ENTITY basic_cell(behave)
PORT MAP(Ax(158),Bx_int(NUM_BITS-1),Cx_int(157),clk,reset,Cx_int(158));
CELL_159: ENTITY basic_cell(behave)
PORT MAP(Ax(159),Bx_int(NUM_BITS-1),Cx_int(158),clk,reset,Cx_int(159));
CELL_160: ENTITY basic_cell(behave)
PORT MAP(Ax(160),Bx_int(NUM_BITS-1),Cx_int(159),clk,reset,Cx_int(160));
CELL_161: ENTITY basic_cell(behave)
PORT MAP(Ax(161),Bx_int(NUM_BITS-1),Cx_int(160),clk,reset,Cx_int(161));
CELL_162: ENTITY basic_cell(behave)
PORT MAP(Ax(162),Bx_int(NUM_BITS-1),Cx_int(161),clk,reset,Cx_int(162));
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10100010"; -- m-1 value, in this case, it is 112, be sure to set the correct value
bx_int <= bx;
cx <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
counter <= counter - 1;
if counter = "00000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
else
bx_int <= bx_shift;
end if;
when END_STATE =>
Cx <= Cx_int;
Done <= '1';
CurrentState <= NOTHING;
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
8ce49c31e4f8f0fb01b5108286c2e787
| 0.651071 | 2.381816 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1147.vhd
| 5 | 2,139 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1147.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n03i01147ent IS
END c06s05b00x00p05n03i01147ent;
ARCHITECTURE c06s05b00x00p05n03i01147arch OF c06s05b00x00p05n03i01147ent IS
SUBTYPE thirteen is INTEGER range 0 to 12;
BEGIN
TESTING: PROCESS
VARIABLE null_array : bit_vector ( 1 to 0 ); -- OK, a nice clean null array
VARIABLE slice : bit_vector ( thirteen );
BEGIN
assert NOT( null_array = slice (11 to 10) and
null_array = slice (-1 to -5) and
null_array = slice (15 to 14) )
report "***PASSED TEST: c06s05b00x00p05n03i01147"
severity NOTE;
assert ( null_array = slice (11 to 10) and
null_array = slice (-1 to -5) and
null_array = slice (15 to 14) )
report "***FAILED TEST: c06s05b00x00p05n03i01147 - The bounds of a null slice need not belong to the subtype of the index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n03i01147arch;
|
gpl-2.0
|
8957df049212b902dbb436305b620185
| 0.645629 | 3.707106 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc15.vhd
| 4 | 3,261 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc15.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p06n01i00015ent IS
END c04s02b00x00p06n01i00015ent;
ARCHITECTURE c04s02b00x00p06n01i00015arch OF c04s02b00x00p06n01i00015ent IS
BEGIN
TESTING: PROCESS
subtype tboolean is boolean range FALSE to TRUE;
subtype tbit is bit range '0' to '1';
subtype tcharacter is character range 'A' to 'Z';
subtype tseverity_level is severity_level range NOTE to ERROR;
subtype tinteger is integer range 1111 to 2222;
subtype treal is real range 1.11 to 2.22;
subtype ttime is time range 1 ns to 1 hr;
subtype tnatural is natural range 100 to 200;
subtype tpositive is positive range 1000 to 2000;
variable k1 : tboolean;
variable k2 : tbit;
variable k3 : tcharacter;
variable k4 : tseverity_level;
variable k5 : tinteger;
variable k6 : treal;
variable k7 : ttime;
variable k8 : tnatural;
variable k9 : tpositive;
BEGIN
assert NOT( k1 = tboolean'left and
k2 = tbit'left and
k3 = tcharacter'left and
k4 = tseverity_level'left and
k5 = tinteger'left and
k6 = treal'left and
k7 = ttime'left and
k8 = tnatural'left and
k9 = tpositive'left )
report "***PASSED TEST: c04s02b00x00p06n01i00015"
severity NOTE;
assert ( k1 = tboolean'left and
k2 = tbit'left and
k3 = tcharacter'left and
k4 = tseverity_level'left and
k5 = tinteger'left and
k6 = treal'left and
k7 = ttime'left and
k8 = tnatural'left and
k9 = tpositive'left )
report "***FAILED TEST: c04s02b00x00p06n01i00015 - A type mark denotes a type or a subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p06n01i00015arch;
|
gpl-2.0
|
d6e2be8e0f5909517f04a021d76b04e0
| 0.583563 | 3.765589 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_08.vhd
| 4 | 2,125 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
library star_lib;
--use star_lib.edge_triggered_dff;
use star_lib.all;
configuration full of counter is
for registered -- architecture of counter
for all : digit_register
use entity work.reg4(struct);
for struct -- architecture of reg4
for bit0 : flipflop
use entity edge_triggered_Dff(hi_fanout);
end for;
for others : flipflop
use entity edge_triggered_Dff(basic);
end for;
end for; -- end of architecture struct
end for;
-- . . . -- bindings for other component instances
end for; -- end of architecture registered
end configuration full;
-- not in book
entity fg_13_08 is
end entity fg_13_08;
use work.counter_types.all;
architecture test of fg_13_08 is
signal clk, clr : bit := '0';
signal q0, q1 : digit;
begin
dut : configuration work.full
port map ( clk => clk, clr => clr,
q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 20 ns;
clr_gen : clr <= '1' after 95 ns,
'0' after 135 ns;
end architecture test;
-- end not in book
|
gpl-2.0
|
1ff1929a9ccf352a3753c1c512c10300
| 0.618353 | 3.849638 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2734.vhd
| 4 | 8,790 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2734.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
ENTITY c13s05b00x00p01n01i02734ent IS
END c13s05b00x00p01n01i02734ent;
ARCHITECTURE c13s05b00x00p01n01i02734arch OF c13s05b00x00p01n01i02734ent IS
BEGIN
TESTING: PROCESS
type grph is array (1 to 95) of character;
variable k : grph;
BEGIN
k(1) := 'A';
k(2) := 'B';
k(3) := 'C';
k(4) := 'D';
k(5) := 'E';
k(6) := 'F';
k(7) := 'G';
k(8) := 'H';
k(9) := 'I';
k(10) := 'J';
k(11) := 'K';
k(12) := 'L';
k(13) := 'M';
k(14) := 'N';
k(15) := 'O';
k(16) := 'P';
k(17) := 'Q';
k(18) := 'R';
k(19) := 'S';
k(20) := 'T';
k(21) := 'U';
k(22) := 'V';
k(23) := 'W';
k(24) := 'X';
k(25) := 'Y';
k(26) := 'Z';
k(27) := '0';
k(28) := '1';
k(29) := '2';
k(30) := '3';
k(31) := '4';
k(32) := '5';
k(33) := '6';
k(34) := '7';
k(35) := '8';
k(36) := '9';
k(37) := '"';
k(38) := '#';
k(39) := '&';
k(40) := ''';
k(41) := '(';
k(42) := ')';
k(43) := '*';
k(44) := '+';
k(45) := ',';
k(46) := '-';
k(47) := '.';
k(48) := '/';
k(49) := ':';
k(50) := ';';
k(51) := '<';
k(52) := '=';
k(53) := '>';
k(54) := '_';
k(55) := '|';
k(56) := ' ';
k(57) := 'a';
k(58) := 'b';
k(59) := 'c';
k(60) := 'd';
k(61) := 'e';
k(62) := 'f';
k(63) := 'g';
k(64) := 'h';
k(65) := 'i';
k(66) := 'j';
k(67) := 'k';
k(68) := 'l';
k(69) := 'm';
k(70) := 'n';
k(71) := 'o';
k(72) := 'p';
k(73) := 'q';
k(74) := 'r';
k(75) := 's';
k(76) := 't';
k(77) := 'u';
k(78) := 'v';
k(79) := 'w';
k(80) := 'x';
k(81) := 'y';
k(82) := 'z';
k(83) := '!';
k(84) := '$';
k(85) := '%';
k(86) := '@';
k(87) := '?';
k(88) := '[';
k(89) := '\';
k(90) := ']';
k(91) := '^';
k(92) := '`';
k(93) := '{';
k(94) := '}';
k(95) := '~';
assert NOT( k(1) = 'A' and
k(2) = 'B' and
k(3) = 'C' and
k(4) = 'D' and
k(5) = 'E' and
k(6) = 'F' and
k(7) = 'G' and
k(8) = 'H' and
k(9) = 'I' and
k(10) = 'J' and
k(11) = 'K' and
k(12) = 'L' and
k(13) = 'M' and
k(14) = 'N' and
k(15) = 'O' and
k(16) = 'P' and
k(17) = 'Q' and
k(18) = 'R' and
k(19) = 'S' and
k(20) = 'T' and
k(21) = 'U' and
k(22) = 'V' and
k(23) = 'W' and
k(24) = 'X' and
k(25) = 'Y' and
k(26) = 'Z' and
k(27) = '0' and
k(28) = '1' and
k(29) = '2' and
k(30) = '3' and
k(31) = '4' and
k(32) = '5' and
k(33) = '6' and
k(34) = '7' and
k(35) = '8' and
k(36) = '9' and
k(37) = '"' and
k(38) = '#' and
k(39) = '&' and
k(40) = ''' and
k(41) = '(' and
k(42) = ')' and
k(43) = '*' and
k(44) = '+' and
k(45) = ',' and
k(46) = '-' and
k(47) = '.' and
k(48) = '/' and
k(49) = ':' and
k(50) = ';' and
k(51) = '<' and
k(52) = '=' and
k(53) = '>' and
k(54) = '_' and
k(55) = '|' and
k(56) = ' ' and
k(57) = 'a' and
k(58) = 'b' and
k(59) = 'c' and
k(60) = 'd' and
k(61) = 'e' and
k(62) = 'f' and
k(63) = 'g' and
k(64) = 'h' and
k(65) = 'i' and
k(66) = 'j' and
k(67) = 'k' and
k(68) = 'l' and
k(69) = 'm' and
k(70) = 'n' and
k(71) = 'o' and
k(72) = 'p' and
k(73) = 'q' and
k(74) = 'r' and
k(75) = 's' and
k(76) = 't' and
k(77) = 'u' and
k(78) = 'v' and
k(79) = 'w' and
k(80) = 'x' and
k(81) = 'y' and
k(82) = 'z' and
k(83) = '!' and
k(84) = '$' and
k(85) = '%' and
k(86) = '@' and
k(87) = '?' and
k(88) = '[' and
k(89) = '\' and
k(90) = ']' and
k(91) = '^' and
k(92) = '`' and
k(93) = '{' and
k(94) = '}' and
k(95) = '~' )
report "***PASSED TEST: /src/ch13/sc05/p001-002/s010107.vhd"
severity NOTE;
assert ( k(1) = 'A' and
k(2) = 'B' and
k(3) = 'C' and
k(4) = 'D' and
k(5) = 'E' and
k(6) = 'F' and
k(7) = 'G' and
k(8) = 'H' and
k(9) = 'I' and
k(10) = 'J' and
k(11) = 'K' and
k(12) = 'L' and
k(13) = 'M' and
k(14) = 'N' and
k(15) = 'O' and
k(16) = 'P' and
k(17) = 'Q' and
k(18) = 'R' and
k(19) = 'S' and
k(20) = 'T' and
k(21) = 'U' and
k(22) = 'V' and
k(23) = 'W' and
k(24) = 'X' and
k(25) = 'Y' and
k(26) = 'Z' and
k(27) = '0' and
k(28) = '1' and
k(29) = '2' and
k(30) = '3' and
k(31) = '4' and
k(32) = '5' and
k(33) = '6' and
k(34) = '7' and
k(35) = '8' and
k(36) = '9' and
k(37) = '"' and
k(38) = '#' and
k(39) = '&' and
k(40) = ''' and
k(41) = '(' and
k(42) = ')' and
k(43) = '*' and
k(44) = '+' and
k(45) = ',' and
k(46) = '-' and
k(47) = '.' and
k(48) = '/' and
k(49) = ':' and
k(50) = ';' and
k(51) = '<' and
k(52) = '=' and
k(53) = '>' and
k(54) = '_' and
k(55) = '|' and
k(56) = ' ' and
k(57) = 'a' and
k(58) = 'b' and
k(59) = 'c' and
k(60) = 'd' and
k(61) = 'e' and
k(62) = 'f' and
k(63) = 'g' and
k(64) = 'h' and
k(65) = 'i' and
k(66) = 'j' and
k(67) = 'k' and
k(68) = 'l' and
k(69) = 'm' and
k(70) = 'n' and
k(71) = 'o' and
k(72) = 'p' and
k(73) = 'q' and
k(74) = 'r' and
k(75) = 's' and
k(76) = 't' and
k(77) = 'u' and
k(78) = 'v' and
k(79) = 'w' and
k(80) = 'x' and
k(81) = 'y' and
k(82) = 'z' and
k(83) = '!' and
k(84) = '$' and
k(85) = '%' and
k(86) = '@' and
k(87) = '?' and
k(88) = '[' and
k(89) = '\' and
k(90) = ']' and
k(91) = '^' and
k(92) = '`' and
k(93) = '{' and
k(94) = '}' and
k(95) = '~' )
report "***FAILED TEST: c13s05b00x00p01n01i02734 - Any one of the 95 graphic characters should be a character literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s05b00x00p01n01i02734arch;
|
gpl-2.0
|
a04a27e4504f7e8ed7ba6719811bb69c
| 0.31479 | 2.656392 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_10.vhd
| 4 | 3,361 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_10.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_10 is
end entity ch_04_10;
----------------------------------------------------------------
architecture test of ch_04_10 is
-- code from book:
type time_stamp is record
seconds : integer range 0 to 59;
minutes : integer range 0 to 59;
hours : integer range 0 to 23;
end record time_stamp;
-- end of code from book
begin
process_04_4_a : process is
-- code from book:
variable sample_time, current_time : time_stamp;
--
constant midday : time_stamp := (0, 0, 12);
-- end of code from book
constant clock : integer := 79;
variable sample_hour : integer;
begin
current_time := (30, 15, 2);
-- code from book:
sample_time := current_time;
sample_hour := sample_time.hours;
current_time.seconds := clock mod 60;
-- end of code from book
wait;
end process process_04_4_a;
process_04_4_b : process is
type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, nop);
type reg_number is range 0 to 31;
type instruction is record
opcode : opcodes;
source_reg1, source_reg2, dest_reg : reg_number;
displacement : integer;
end record instruction;
-- code from book:
constant midday : time_stamp := (hours => 12, minutes => 0, seconds => 0);
--
constant nop_instr : instruction :=
( opcode => addu,
source_reg1 | source_reg2 | dest_reg => 0,
displacement => 0 );
variable latest_event : time_stamp := (others => 0); -- initially midnight
-- end of code from book
begin
wait;
end process process_04_4_b;
end architecture test;
|
gpl-2.0
|
d09cf205c2cc1cece4758c5f686c3186
| 0.476644 | 4.979259 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd
| 4 | 2,347 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity single_board_computer is
end entity single_board_computer;
-- end not in book
architecture structural of single_board_computer is
-- . . . -- type and signal declarations
-- not in book
subtype word is bit_vector(31 downto 0);
signal sys_clk : bit;
signal cpu_a_d, latched_addr : word;
-- end not in book
component processor is
port ( clk : in bit; a_d : inout word; -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component processor;
component memory is
port ( addr : in bit_vector(25 downto 0); -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component memory;
component serial_interface is
port ( clk : in bit; address : in bit_vector(3 downto 0); -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component serial_interface;
begin
cpu : component processor
port map ( clk => sys_clk, a_d => cpu_a_d, -- . . . );
-- not in book
other_port => open );
-- end not in book
main_memory : component memory
port map ( addr => latched_addr(25 downto 0), -- . . . );
-- not in book
other_port => open );
-- end not in book
serial_interface_a : component serial_interface
port map ( clk => sys_clk, address => latched_addr(3 downto 0), -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture structural;
|
gpl-2.0
|
8572bb66e07dd20ddbe5568f76ca1726
| 0.626331 | 3.872937 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_08.vhd
| 4 | 3,434 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity entname is
end entity entname;
-- end not in book
architecture rtl of entname is
type state_type is (s0, s1, s2, s3);
signal state, next_state : state_type;
signal con1, con2, con3 : std_ulogic;
signal out1, out2 : std_ulogic;
signal clk, reset : std_ulogic;
-- . . .
begin
state_logic : process (state, con1, con2, con3) is
begin
case state is
when s0 =>
out1 <= '0';
out2 <= '0';
next_state <= s1;
when s1 =>
out1 <= '1';
if con1 = '1' then
next_state <= s2;
else
next_state <= s1;
end if;
when s2 =>
out2 <= '1';
next_state <= s3;
when s3 =>
if con2 = '0' then
next_state <= s3;
elsif con3 = '0' then
out1 <= '0';
next_state <= s2;
else
next_state <= s1;
end if;
end case;
end process state_logic;
state_register : process (clk, reset) is
begin
if reset = '0' then
state <= s0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process state_register;
-- . . .
-- not in book
clk_gen : process is
begin
clk <= '0', '1' after 10 ns;
wait for 20 ns;
end process clk_gen;
reset <= '0', '1' after 40 ns;
con1 <= '0', '1' after 100 ns, '0' after 120 ns;
con2 <= '0', '1' after 160 ns;
con3 <= '0', '1' after 220 ns;
-- end not in book
end architecture rtl;
|
gpl-2.0
|
5f9d730514d60137630be29de305e502
| 0.416424 | 4.762829 | false | false | false | false |
nczempin/NICNAC16
|
ipcore_dir/blk_mem_gen_v7_3/simulation/blk_mem_gen_v7_3_synth.vhd
| 1 | 7,117 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
ENA => ENA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
ENA => ENA_R,
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
mit
|
ce9dad13ee4acba00ee04811e2fde173
| 0.57454 | 3.72228 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc753.vhd
| 4 | 17,354 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc753.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00753pkg is
subtype hi_to_low_range is integer range 0 to 7;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(1 to 7);
k:bit_vector(0 to 3);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(0 to 15);
b:severity_level_vector(0 to 15);
c:integer_vector(0 to 15);
d:real_vector(0 to 15);
e:time_vector(0 to 15);
f:natural_vector(0 to 15);
g:positive_vector(0 to 15);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(0 to 7);
b: array_rec_cons(0 to 7);
c: array_rec_rec(0 to 7);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(0 to 7) of bit;
subtype word is bit_vector(0 to 15); --constrained array
constant size :integer := 7;
type primary_memory is array(0 to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range 1 to 10;
end c01s01b01x01p05n02i00753pkg;
use work.c01s01b01x01p05n02i00753pkg.all;
ENTITY c01s01b01x01p05n02i00753ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
port(
S1 : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
S2 : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
S3 : integer_vector(zero to fifteen):= (zero to fifteen => C5);
S4 : real_vector(zero to fifteen):= (zero to fifteen => C6);
S5 : time_vector (zero to fifteen):= (zero to fifteen => C7);
S6 : natural_vector(zero to fifteen):= (zero to fifteen => C8);
S7 : positive_vector(zero to fifteen):= (zero to fifteen => C9);
S8 : boolean_cons_vector:= (zero to fifteen => C1);
S9 : severity_level_cons_vector := (zero to fifteen => C4);
S10 : integer_cons_vector:= (zero to fifteen => C5);
S11 : real_cons_vector:= (zero to fifteen => C6);
S12 : time_cons_vector := (zero to fifteen => C7);
S13 : natural_cons_vector := (zero to fifteen => C8);
S14 : positive_cons_vector := (zero to fifteen => C9);
S15 : boolean_cons_vectorofvector:= (zero to fifteen =>(others=> C1));
S16 : severity_level_cons_vectorofvector := (zero to fifteen =>(others=> C4));
S17 : integer_cons_vectorofvector := (zero to fifteen =>(others=> C5));
S18 : real_cons_vectorofvector := (zero to fifteen =>(others=> C6));
S19 : time_cons_vectorofvector := (zero to fifteen =>(others=> C7));
S20 : natural_cons_vectorofvector := (zero to fifteen =>(others=> C8));
S21 : positive_cons_vectorofvector := (zero to fifteen =>(others=> C9));
S22 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
S25 : boolean_vector_st := (zero to fifteen => C1);
S26 : severity_level_vector_st:= (zero to fifteen => C4);
S27 : integer_vector_st:= (zero to fifteen => C5);
S28 : real_vector_st:= (zero to fifteen => C6);
S29 : time_vector_st:= (zero to fifteen => C7);
S30 : natural_vector_st:= (zero to fifteen => C8);
S31 : positive_vector_st:= (zero to fifteen => C9)
);
END c01s01b01x01p05n02i00753ent;
ARCHITECTURE c01s01b01x01p05n02i00753arch OF c01s01b01x01p05n02i00753ent IS
BEGIN
assert (S1(0) = C1) report " error in initializing S1" severity error;
assert (S2(0) = C4) report " error in initializing S2" severity error;
assert (S3(0) = C5) report " error in initializing S3" severity error;
assert (S4(0) = C6) report " error in initializing S4" severity error;
assert (S5(0) = C7) report " error in initializing S5" severity error;
assert (S6(0) = C8) report " error in initializing S6" severity error;
assert (S7(0) = C9) report " error in initializing S7" severity error;
assert (S8(0) = C1) report " error in initializing S8" severity error;
assert (S9(0) = C4) report " error in initializing S9" severity error;
assert (S10(0) = C5) report " error in initializing S10" severity error;
assert (S11(0) = C6) report " error in initializing S11" severity error;
assert (S12(0) = C7) report " error in initializing S12" severity error;
assert (S13(0) = C8) report " error in initializing S13" severity error;
assert (S14(0) = C9) report " error in initializing S14" severity error;
assert (S15(0)(0) = C1) report " error in initializing S15" severity error;
assert (S16(0)(0) = C4) report " error in initializing S16" severity error;
assert (S17(0)(0) = C5) report " error in initializing S17" severity error;
assert (S18(0)(0) = C6) report " error in initializing S18" severity error;
assert (S19(0)(0) = C7) report " error in initializing S19" severity error;
assert (S20(0)(0) = C8) report " error in initializing S20" severity error;
assert (S21(0)(0) = C9) report " error in initializing S21" severity error;
assert (S22.a = C1) report " error in initializing S21" severity error;
assert (S22.b = C2) report " error in initializing S21" severity error;
assert (S22.c = C3) report " error in initializing S21" severity error;
assert (S22.d = C4) report " error in initializing S21" severity error;
assert (S22.e = C5) report " error in initializing S21" severity error;
assert (S22.f = C6) report " error in initializing S21" severity error;
assert (S22.g = C7) report " error in initializing S21" severity error;
assert (S22.h = C8) report " error in initializing S21" severity error;
assert (S22.i = C9) report " error in initializing S21" severity error;
assert (S22.j = C10) report " error in initializing S21" severity error;
assert (S22.k = C11) report " error in initializing S21" severity error;
assert (S25(0) = C1) report " error in initializing S25" severity error;
assert (S26(0) = C4) report " error in initializing S26" severity error;
assert (S27(0) = C5) report " error in initializing S27" severity error;
assert (S28(0) = C6) report " error in initializing S28" severity error;
assert (S29(0) = C7) report " error in initializing S29" severity error;
assert (S30(0) = C8) report " error in initializing S30" severity error;
assert (S31(0) = C9) report " error in initializing S31" severity error;
TESTING: PROCESS
BEGIN
assert NOT( (S1(0) = C1) and
(S2(0) = C4) and
(S3(0) = C5) and
(S4(0) = C6) and
(S5(0) = C7) and
(S6(0) = C8) and
(S7(0) = C9) and
(S8(0) = C1) and
(S9(0) = C4) and
(S10(0) = C5) and
(S11(0) = C6) and
(S12(0) = C7) and
(S13(0) = C8) and
(S14(0) = C9) and
(S15(0)(0) = C1) and
(S16(0)(0) = C4) and
(S17(0)(0) = C5) and
(S18(0)(0) = C6) and
(S19(0)(0) = C7) and
(S20(0)(0) = C8) and
(S21(0)(0) = C9) and
(S22.a = C1) and
(S22.b = C2) and
(S22.c = C3) and
(S22.d = C4) and
(S22.e = C5) and
(S22.f = C6) and
(S22.g = C7) and
(S22.h = C8) and
(S22.i = C9) and
(S22.j = C10) and
(S22.k = C11) and
(S25(0) = C1) and
(S26(0) = C4) and
(S27(0) = C5) and
(S28(0) = C6) and
(S29(0) = C7) and
(S30(0) = C8) and
(S31(0) = C9) )
report "***PASSED TEST: c01s01b01x01p05n02i00753"
severity NOTE;
assert ( (S1(0) = C1) and
(S2(0) = C4) and
(S3(0) = C5) and
(S4(0) = C6) and
(S5(0) = C7) and
(S6(0) = C8) and
(S7(0) = C9) and
(S8(0) = C1) and
(S9(0) = C4) and
(S10(0) = C5) and
(S11(0) = C6) and
(S12(0) = C7) and
(S13(0) = C8) and
(S14(0) = C9) and
(S15(0)(0) = C1) and
(S16(0)(0) = C4) and
(S17(0)(0) = C5) and
(S18(0)(0) = C6) and
(S19(0)(0) = C7) and
(S20(0)(0) = C8) and
(S21(0)(0) = C9) and
(S22.a = C1) and
(S22.b = C2) and
(S22.c = C3) and
(S22.d = C4) and
(S22.e = C5) and
(S22.f = C6) and
(S22.g = C7) and
(S22.h = C8) and
(S22.i = C9) and
(S22.j = C10) and
(S22.k = C11) and
(S25(0) = C1) and
(S26(0) = C4) and
(S27(0) = C5) and
(S28(0) = C6) and
(S29(0) = C7) and
(S30(0) = C8) and
(S31(0) = C9) )
report "***FAILED TEST: c01s01b01x01p05n02i00753 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00753arch;
|
gpl-2.0
|
89c2936c07bca1ff5115f1fe8a2d16df
| 0.532327 | 3.619942 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_409.vhd
| 1 | 4,897 |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_409 is
generic (
NUM_BITS : positive := 409 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_409;
-----------------------------------------------------------
architecture behave of serial_multiplier_409 is
-----------------------------------------------------------
-- m = 409 x409 + x87 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(8 downto 0); -- 8-bit counter, controling the number of iterations: m
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "110011000"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
if counter = "000000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
Done <= '1';
else
bx_int <= bx_shift;
end if;
when END_STATE =>
CurrentState <= END_STATE;
Done <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
845c0a7f8a693ba71689c7c08100e4c1
| 0.507045 | 4.542672 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_03.vhd
| 4 | 3,373 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_fg_04_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_04_03 is
end entity fg_04_03;
----------------------------------------------------------------
architecture test of fg_04_03 is
begin
-- code from book:
modem_controller : process is
type symbol is ('a', 't', 'd', 'h', digit, cr, other);
type symbol_string is array (1 to 20) of symbol;
type state is range 0 to 6;
type transition_matrix is array (state, symbol) of state;
constant next_state : transition_matrix :=
( 0 => ('a' => 1, others => 6),
1 => ('t' => 2, others => 6),
2 => ('d' => 3, 'h' => 5, others => 6),
3 => (digit => 4, others => 6),
4 => (digit => 4, cr => 0, others => 6),
5 => (cr => 0, others => 6),
6 => (cr => 0, others => 6) );
variable command : symbol_string;
variable current_state : state := 0;
-- not in book:
type sample_array is array (positive range <>) of symbol_string;
constant sample_command : sample_array :=
( 1 => ( 'a', 't', 'd', digit, digit, cr, others => other ),
2 => ( 'a', 't', 'h', cr, others => other ),
3 => ( 'a', 't', other, other, cr, others => other ) );
-- end not in book
begin
-- . . .
-- not in book:
for command_index in sample_command'range loop
command := sample_command(command_index);
-- end not in book
for index in 1 to 20 loop
current_state := next_state( current_state, command(index) );
case current_state is
-- . . .
-- not in book:
when 0 => exit;
when others => null;
-- end not in book
end case;
end loop;
-- . . .
-- not in book:
end loop;
wait;
-- end not in book
end process modem_controller;
-- end of code from book
end architecture test;
|
gpl-2.0
|
b89036d0abcbc17b4a49432aec8bdb32
| 0.455677 | 4.607923 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_06.vhd
| 4 | 1,869 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_06 is
end entity ch_05_06;
----------------------------------------------------------------
architecture test of ch_05_06 is
signal y : bit := '0';
signal or_a_b : bit := '0';
signal clk : bit := '0';
begin
process_05_3_a : process is
begin
-- code from book:
y <= not or_a_b after 5 ns;
-- end of code from book
wait on or_a_b;
end process process_05_3_a;
stimulus_05_3_a : process is
begin
or_a_b <= '1' after 20 ns,
'0' after 40 ns;
wait;
end process stimulus_05_3_a;
process_05_3_b : process is
constant T_pw : delay_length := 10 ns;
begin
-- code from book:
clk <= '1' after T_pw, '0' after 2*T_pw;
-- end of code from book
wait for 2*T_pw;
end process process_05_3_b;
end architecture test;
|
gpl-2.0
|
55772926809b08f70088209440ea2010
| 0.570894 | 3.738 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd
| 4 | 1,833 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_15 is
end entity inline_15;
----------------------------------------------------------------
architecture test of inline_15 is
begin
process_3_c : process is
-- code from book:
subtype name is string(1 to 20);
type display_string is array (integer range 0 to 19) of character;
variable item_name : name;
variable display : display_string;
--
subtype big_endian_upper_halfword is bit_vector(0 to 15);
subtype little_endian_upper_halfword is bit_vector(31 downto 16);
variable big : big_endian_upper_halfword;
variable little : little_endian_upper_halfword;
-- end of code from book
begin
-- error: Incompatible types for assignment
-- display := item_name; -- ilegal
item_name := (others => 'A');
little := x"AAAA";
-- code from book:
display := display_string(item_name);
--
big := little;
little := big;
-- end of code from book
wait;
end process process_3_c;
----------------
end architecture test;
|
gpl-2.0
|
b0c6997b27ad6cc944a7f7dd0347df78
| 0.655756 | 4.194508 | false | false | false | false |
dicearr/neuron-vhdl
|
src/Neuron.vhd
| 1 | 3,135 |
----------------------------------------------------------------------------------
-- Engineer: Diego Ceresuela, Oscar Clemente.
--
-- Create Date: 13.04.2016 09:27:04
-- Module Name: Neuron - Behavioral
-- Description: Implements a neuron prepared to be connected into a network using an aproximation of the sigmoid
-- function based on a ROM and using Q15.16 signed codification.
--
-- Dependencies: sigmoid.vhd data_types.vhd adder_tree.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- Worst negative slack is not always in the correct range.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work;
use work.data_types.all;
entity Neuron is
generic ( n : integer := 0 );
Port ( slv_Xin, slv_Win : in STD_LOGIC_VECTOR ((n*32)+31 downto 0); --Values
clk : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (31 downto 0) );
end Neuron;
architecture Behavioral of Neuron is
component sigmoid
port ( Y : in STD_LOGIC_VECTOR (31 downto 0);
O : out STD_LOGIC_VECTOR (31 downto 0);
clk: in STD_LOGIC );
end component;
component adder_tree
generic (
NINPUTS : integer;
IWIDTH : integer;
OWIDTH : integer
);
port (
rstN : in std_logic;
clk : in std_logic;
d : in std_logic_vector(NINPUTS*IWIDTH-1 downto 0);
q : out signed(OWIDTH-1 downto 0)
);
end component;
signal sum : signed(31 downto 0) := x"00000000";
signal Y : STD_LOGIC_VECTOR (31 downto 0);
signal Xin, Win, Prod : vector (0 to n) := (others => x"00000000");
signal d : STD_LOGIC_VECTOR ((n*32)+31 downto 0);
begin
SIG : sigmoid port map (Y => Y, O => O, clk => clk);
G1: if n>0 generate
ADDER : adder_tree
generic map ( NINPUTS => n+1, IWIDTH => 32, OWIDTH => 32)
port map ( rstN => '1', clk => clk, d => d, q => sum);
end generate G1;
Xin <= to_vec(slv_Xin);
Win <= to_vec(slv_Win);
d <= to_slv(Prod);
process (Xin, Win,sum)
begin
if (n>0) then
L1: for I in 0 to n loop
Prod(I) <= to_stdlogicvector(to_bitvector(std_logic_vector(signed(Xin(I)) * signed(Win(I)))) sra 16)(31 downto 0);
end loop L1;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if (n<1) then
Y <= to_stdlogicvector(to_bitvector(std_logic_vector(signed(Xin(0)) * signed(Win(0)))) sra 16)(31 downto 0);
else
Y <= std_logic_vector(sum);
end if;
end if;
end process;
end Behavioral;
|
mit
|
02d3d69bcc3d105c6dc86be466f0d953
| 0.554067 | 3.74105 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2262.vhd
| 4 | 1,768 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2262.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p11n01i02262ent IS
END c07s02b06x00p11n01i02262ent;
ARCHITECTURE c07s02b06x00p11n01i02262arch OF c07s02b06x00p11n01i02262ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
k := 10 rem (-3);
assert NOT(k=1)
report "***PASSED TEST: c07s02b06x00p11n01i02262"
severity NOTE;
assert ( k=1 )
report "***FAILED TEST: c07s02b06x00p11n01i02262 - Integer division and remainder are deined by the following relation : A = (A/B)*B + (A rem B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p11n01i02262arch;
|
gpl-2.0
|
c0df9519026fe2192c942ddeb390c8e9
| 0.665724 | 3.615542 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_277.vhd
| 1 | 4,776 |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_277 is
generic (
NUM_BITS : positive := 277 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_277;
-----------------------------------------------------------
architecture behave of serial_multiplier_277 is
-----------------------------------------------------------
-- m = 277 x277 + x74 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(8 downto 0); -- 8-bit counter, controling the number of iterations: m
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "100010100"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
if counter = "000000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
Done <= '1';
else
bx_int <= bx_shift;
end if;
when END_STATE =>
CurrentState <= END_STATE;
Done <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
af4343f1a5c8a9d73dedb24b228def25
| 0.493719 | 4.414048 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/mlite_cpu.vhd
| 2 | 13,252 |
---------------------------------------------------------------------
-- TITLE: Plasma CPU core
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_cpu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS
-- Technologies. MIPS Technologies does not endorse and is not
-- associated with this project.
-- DESCRIPTION:
-- Top level VHDL document that ties the nine other entities together.
--
-- Executes all MIPS I(tm) opcodes but exceptions and non-aligned
-- memory accesses. Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
--
-- The CPU is implemented as a two or three stage pipeline.
-- An add instruction would take the following steps (see cpu.gif):
-- Stage #0:
-- 1. The "pc_next" entity passes the program counter (PC) to the
-- "mem_ctrl" entity which fetches the opcode from memory.
-- Stage #1:
-- 2. The memory returns the opcode.
-- Stage #2:
-- 3. "Mem_ctrl" passes the opcode to the "control" entity.
-- 4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
-- and sends control signals to the other entities.
-- 5. Based on the rs_index and rt_index control signals, "reg_bank"
-- sends the 32-bit reg_source and reg_target to "bus_mux".
-- 6. Based on the a_source and b_source control signals, "bus_mux"
-- multiplexes reg_source onto a_bus and reg_target onto b_bus.
-- Stage #3 (part of stage #2 if using two stage pipeline):
-- 7. Based on the alu_func control signals, "alu" adds the values
-- from a_bus and b_bus and places the result on c_bus.
-- 8. Based on the c_source control signals, "bus_bux" multiplexes
-- c_bus onto reg_dest.
-- 9. Based on the rd_index control signal, "reg_bank" saves
-- reg_dest into the correct register.
-- Stage #3b:
-- 10. Read or write memory if needed.
--
-- All signals are active high.
-- Here are the signals for writing a character to address 0xffff
-- when using a two stage pipeline:
--
-- Program:
-- addr value opcode
-- =============================
-- 3c: 00000000 nop
-- 40: 34040041 li $a0,0x41
-- 44: 3405ffff li $a1,0xffff
-- 48: a0a40000 sb $a0,0($a1)
-- 4c: 00000000 nop
-- 50: 00000000 nop
--
-- intr_in mem_pause
-- reset_in byte_we Stages
-- ns address data_w data_r 40 44 48 4c 50
-- 3600 0 0 00000040 00000000 34040041 0 0 1
-- 3700 0 0 00000044 00000000 3405FFFF 0 0 2 1
-- 3800 0 0 00000048 00000000 A0A40000 0 0 2 1
-- 3900 0 0 0000004C 41414141 00000000 0 0 2 1
-- 4000 0 0 0000FFFC 41414141 XXXXXX41 1 0 3 2
-- 4100 0 0 00000050 00000000 00000000 0 0 1
---------------------------------------------------------------------
library ieee;
use work.mlite_pack.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mlite_cpu is
generic(memory_type : string := "DUAL_PORT_"; --ALTERA_LPM, or DUAL_PORT_ "XILINX_16X"
mult_type : string := "DEFAULT"; --AREA_OPTIMIZED
shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED
alu_type : string := "DEFAULT"; --AREA_OPTIMIZED
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
opcode_test_out : out std_logic_vector(31 downto 0);
pc_future_test_out : out std_logic_vector(31 downto 2);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end; --entity mlite_cpu
architecture logic of mlite_cpu is
--When using a two stage pipeline "sigD <= sig".
--When using a three stage pipeline "sigD <= sig when rising_edge(clk)",
-- so sigD is delayed by one clock cycle.
signal opcode : std_logic_vector(31 downto 0);
signal rs_index : std_logic_vector(5 downto 0);
signal rt_index : std_logic_vector(5 downto 0);
signal rd_index : std_logic_vector(5 downto 0);
signal rd_indexD : std_logic_vector(5 downto 0);
signal reg_source : std_logic_vector(31 downto 0);
signal reg_target : std_logic_vector(31 downto 0);
signal reg_dest : std_logic_vector(31 downto 0);
signal reg_destD : std_logic_vector(31 downto 0);
signal a_bus : std_logic_vector(31 downto 0);
signal a_busD : std_logic_vector(31 downto 0);
signal b_bus : std_logic_vector(31 downto 0);
signal b_busD : std_logic_vector(31 downto 0);
signal c_bus : std_logic_vector(31 downto 0);
signal c_alu : std_logic_vector(31 downto 0);
signal c_shift : std_logic_vector(31 downto 0);
signal c_mult : std_logic_vector(31 downto 0);
signal c_memory : std_logic_vector(31 downto 0);
signal imm : std_logic_vector(15 downto 0);
signal pc_future : std_logic_vector(31 downto 2);
signal pc_current : std_logic_vector(31 downto 2);
signal pc_plus4 : std_logic_vector(31 downto 2);
signal alu_func : alu_function_type;
signal alu_funcD : alu_function_type;
signal shift_func : shift_function_type;
signal shift_funcD : shift_function_type;
signal mult_func : mult_function_type;
signal mult_funcD : mult_function_type;
signal branch_func : branch_function_type;
signal take_branch : std_logic;
signal a_source : a_source_type;
signal b_source : b_source_type;
signal c_source : c_source_type;
signal pc_source : pc_source_type;
signal mem_source : mem_source_type;
signal pause_mult : std_logic;
signal pause_ctrl : std_logic;
signal pause_pipeline : std_logic;
signal pause_any : std_logic;
signal pause_non_ctrl : std_logic;
signal pause_bank : std_logic;
signal nullify_op : std_logic;
signal intr_enable : std_logic;
signal intr_signal : std_logic;
signal exception_sig : std_logic;
signal reset_reg : std_logic_vector(3 downto 0);
signal reset : std_logic;
begin --architecture
pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
or intr_signal = '1' or exception_sig = '1'
else '0';
c_bus <= c_alu or c_shift or c_mult;
reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
--synchronize reset and interrupt pins
intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
pc_source, pc_current, pause_any)
begin
if reset_in = '1' then
reset_reg <= "0000";
intr_signal <= '0';
elsif rising_edge(clk) then
if reset_reg /= "1111" then
reset_reg <= reset_reg + 1;
end if;
--don't try to interrupt a multi-cycle instruction
if pause_any = '0' then
if intr_in = '1' and intr_enable = '1' and
pc_source = FROM_INC4 then
--the epc will contain pc+4
intr_signal <= '1';
else
intr_signal <= '0';
end if;
end if;
end if;
end process;
u1_pc_next: pc_next PORT MAP (
clk => clk,
reset_in => reset,
take_branch => take_branch,
pause_in => pause_any,
pc_new => c_bus(31 downto 2),
opcode25_0 => opcode(25 downto 0),
pc_source => pc_source,
pc_future => pc_future,
-- pc_future_test => pc_future_test_out,
pc_current => pc_current,
pc_plus4 => pc_plus4);
u2_mem_ctrl: mem_ctrl
PORT MAP (
clk => clk,
reset_in => reset,
pause_in => pause_non_ctrl,
nullify_op => nullify_op,
address_pc => pc_future,
opcode_out => opcode,
-- opcode_test => opcode_test_out,
address_in => c_bus,
mem_source => mem_source,
data_write => reg_target,
data_read => c_memory,
pause_out => pause_ctrl,
address_next => address_next,
byte_we_next => byte_we_next,
address => address,
byte_we => byte_we,
data_w => data_w,
data_r => data_r);
u3_control: control PORT MAP (
opcode => opcode,
intr_signal => intr_signal,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_index,
imm_out => imm,
alu_func => alu_func,
shift_func => shift_func,
mult_func => mult_func,
branch_func => branch_func,
a_source_out => a_source,
b_source_out => b_source,
c_source_out => c_source,
pc_source_out=> pc_source,
mem_source_out=> mem_source,
exception_out=> exception_sig);
u4_reg_bank: reg_bank
generic map(memory_type => memory_type)
port map (
clk => clk,
reset_in => reset,
pause => pause_bank,
rs_index => rs_index,
rt_index => rt_index,
rd_index => rd_indexD,
reg_source_out => reg_source,
reg_target_out => reg_target,
reg_dest_new => reg_destD,
intr_enable => intr_enable);
u5_bus_mux: bus_mux port map (
imm_in => imm,
reg_source => reg_source,
a_mux => a_source,
a_out => a_bus,
reg_target => reg_target,
b_mux => b_source,
b_out => b_bus,
c_bus => c_bus,
c_memory => c_memory,
c_pc => pc_current,
c_pc_plus4 => pc_plus4,
c_mux => c_source,
reg_dest_out => reg_dest,
branch_func => branch_func,
take_branch => take_branch);
u6_alu: alu
generic map (alu_type => alu_type)
port map (
a_in => a_busD,
b_in => b_busD,
alu_function => alu_funcD,
c_alu => c_alu);
u7_shifter: shifter
generic map (shifter_type => shifter_type)
port map (
value => b_busD,
shift_amount => a_busD(4 downto 0),
shift_func => shift_funcD,
c_shift => c_shift);
u8_mult: mult
generic map (mult_type => mult_type)
port map (
clk => clk,
reset_in => reset,
a => a_busD,
b => b_busD,
mult_func => mult_funcD,
c_mult => c_mult,
pause_out => pause_mult);
pipeline2: if pipeline_stages <= 2 generate
a_busD <= a_bus;
b_busD <= b_bus;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
rd_indexD <= rd_index;
reg_destD <= reg_dest;
pause_pipeline <= '0';
end generate; --pipeline2
pipeline3: if pipeline_stages > 2 generate
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
u9_pipeline: pipeline port map (
clk => clk,
reset => reset,
a_bus => a_bus,
a_busD => a_busD,
b_bus => b_bus,
b_busD => b_busD,
alu_func => alu_func,
alu_funcD => alu_funcD,
shift_func => shift_func,
shift_funcD => shift_funcD,
mult_func => mult_func,
mult_funcD => mult_funcD,
reg_dest => reg_dest,
reg_destD => reg_destD,
rd_index => rd_index,
rd_indexD => rd_indexD,
rs_index => rs_index,
rt_index => rt_index,
pc_source => pc_source,
mem_source => mem_source,
a_source => a_source,
b_source => b_source,
c_source => c_source,
c_bus => c_bus,
pause_any => pause_any,
pause_pipeline => pause_pipeline);
end generate; --pipeline3
opcode_test_out <= opcode;
pc_future_test_out <= pc_current;
end; --architecture logic
|
mit
|
4eda6a24f28c4f0c61fe21c4888af522
| 0.541503 | 3.50582 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_25.vhd
| 4 | 2,618 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_25.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- VHDL-87
entity mux4 is
port ( i0, i1, i2, i3, sel0, sel1 : in bit;
z : out bit );
end mux4;
----------------------------------------------------------------
architecture functional of mux4 is
begin
out_select : process (sel0, sel1, i0, i1, i2, i3)
subtype bits_2 is bit_vector(1 downto 0);
begin
case bits_2'(sel1, sel0) is
when "00" => z <= i0;
when "01" => z <= i1;
when "10" => z <= i2;
when "11" => z <= i3;
end case;
end process out_select;
end functional;
----------------------------------------------------------------
entity ch_05_25 is
end ch_05_25;
----------------------------------------------------------------
architecture test of ch_05_25 is
signal select_line, line0, line1, result_line : bit;
-- code from book:
signal tied_0 : bit := '0';
signal tied_1 : bit := '1';
-- end of code from book
component mux4
port ( i0, i1, i2, i3, sel0, sel1 : in bit;
z : out bit );
end component;
for all : mux4
use entity work.mux4;
begin
a_mux : mux4
-- code from book:
port map ( sel0 => select_line, i0 => line0, i1 => line1,
z => result_line,
sel1 => tied_0, i2 => tied_1, i3 => tied_1 );
-- end of code from book
----------------
stimulus : process
begin
wait for 5 ns;
line0 <= '1'; wait for 5 ns;
line1 <= '1'; wait for 5 ns;
select_line <= '1'; wait for 5 ns;
line1 <= '0'; wait for 5 ns;
line0 <= '0'; wait for 5 ns;
wait;
end process stimulus;
end test;
|
gpl-2.0
|
d714f196d14521687ac8601663af40d4
| 0.526738 | 3.591221 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_wdt.vhd
| 1 | 10,368 |
-- #################################################################################################
-- # << NEO430 - Watchdog Timer >> #
-- # ********************************************************************************************* #
-- # The internal counter is 16 bit wide and triggers a HW reset when overflowing. The clock is #
-- # selected via the clk_sel bits of the control register. The WDT can only operate when the #
-- # enable bit is set. A write access to the WDT can only be performed, if the higher byte of the #
-- # written data contains the specific WDT password (0x47). I a write access occurs with a wrong #
-- # password, a HW reset is triggered, but only if the WDT is enabled. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_wdt is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- external reset, low-active, use as async
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- system reset --
rst_o : out std_ulogic -- timeout reset, low_active, use it as async!
);
end neo430_wdt;
architecture neo430_wdt_rtl of neo430_wdt is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(wdt_size_c); -- low address boundary bit
-- Watchdog access password - do not change! --
constant wdt_password_c : std_ulogic_vector(07 downto 0) := x"47";
-- Control register bits --
constant ctrl_clksel0_c : natural := 0; -- r/w: prescaler select bit 0
constant ctrl_clksel1_c : natural := 1; -- r/w: prescaler select bit 1
constant ctrl_clksel2_c : natural := 2; -- r/w: prescaler select bit 2
constant ctrl_enable_c : natural := 3; -- r/w: WDT enable
constant ctrl_rcause_c : natural := 4; -- r/-: reset cause (0: external, 1: watchdog timeout)
constant ctrl_rpwfail_c : natural := 5; -- r/-: watchdog reset caused by wrong password access when '1'
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal pwd_ok : std_ulogic; -- password correct
signal fail, fail_ff : std_ulogic; -- unauthorized access
signal wren : std_ulogic;
-- accessible regs --
signal rst_source : std_ulogic; -- source of the system reset: '0' = external, '1' = watchdog timeout
signal pw_fail : std_ulogic; -- watchdog reset caused by wrong password access
signal enable : std_ulogic;
signal clk_sel : std_ulogic_vector(02 downto 0);
-- reset counter --
signal cnt : std_ulogic_vector(16 downto 0);
signal rst_gen : std_ulogic_vector(03 downto 0);
signal rst_sync : std_ulogic_vector(01 downto 0);
-- prescaler clock generator --
signal prsc_tick : std_ulogic;
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0';
pwd_ok <= '1' when (data_i(15 downto 8) = wdt_password_c) else '0'; -- password check
wren <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '1')) else '0'; -- write access ok
fail <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '0')) else '0'; -- write access fail!
-- Write Access, Reset Generator --------------------------------------------
-- -----------------------------------------------------------------------------
wdt_core: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '0') or (rst_sync(1) = '0') then -- external or internal reset
enable <= '0'; -- disable WDT
clk_sel <= (others => '1'); -- slowest clock rst_source
rst_gen <= (others => '1'); -- do NOT fire on reset!
else
-- control register write access --
if (wren = '1') then -- allow write if password is correct
enable <= data_i(ctrl_enable_c);
clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
end if;
-- reset generator - enabled and (overflow or unauthorized access)? --
if (enable = '1') and ((cnt(cnt'left) = '1') or (fail_ff = '1')) then
rst_gen <= (others => '0');
else
rst_gen <= rst_gen(rst_gen'left-1 downto 0) & '1';
end if;
end if;
end if;
end process wdt_core;
-- enable external clock generator --
clkgen_en_o <= enable;
-- Counter Update -----------------------------------------------------------
-- -----------------------------------------------------------------------------
cnt_sync: process(clk_i)
begin
if rising_edge(clk_i) then
-- clock_en buffer --
prsc_tick <= clkgen_i(to_integer(unsigned(clk_sel)));
-- unauthorized access buffer --
fail_ff <= fail;
-- reset synchronizer --
rst_sync <= rst_sync(0) & rst_gen(rst_gen'left);
-- counter update --
if (wren = '1') then -- clear counter on write access (manual watchdog reset)
cnt <= (others => '0');
elsif (enable = '1') and (prsc_tick = '1') then
cnt <= std_ulogic_vector(unsigned('0' & cnt(cnt'left-1 downto 0)) + 1);
end if;
end if;
end process cnt_sync;
-- system reset --
rst_o <= rst_sync(1);
-- Reset Cause Indicator ----------------------------------------------------
-- -----------------------------------------------------------------------------
rst_cause: process(rst_i, clk_i)
begin
if (rst_i = '0') then
rst_source <= '0';
pw_fail <= '0';
elsif rising_edge(clk_i) then
rst_source <= rst_source or (cnt(cnt'left) and enable) or (fail_ff and enable); -- set on WDT timeout or access error
pw_fail <= (pw_fail or (fail_ff and enable)) and (not (cnt(cnt'left) and enable)); -- set on failed access, clear on WDT timeout
--pw_fail <= (pw_fail and (not (cnt(cnt'left) and enable))) or (fail_ff and enable); -- clear on WDT timeout, set on failed access
end if;
end process rst_cause;
-- Read Access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
read_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (acc_en = '1') and (rden_i = '1') then
data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= clk_sel;
data_o(ctrl_enable_c) <= enable;
data_o(ctrl_rcause_c) <= rst_source;
data_o(ctrl_rpwfail_c) <= pw_fail;
end if;
end if;
end process read_access;
end neo430_wdt_rtl;
|
bsd-3-clause
|
86d2c764db7a7dec6d1a2ae4eefc2d7c
| 0.490162 | 4.408163 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1497.vhd
| 4 | 1,871 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1497.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n01i01497ent IS
END c08s08b00x00p14n01i01497ent;
ARCHITECTURE c08s08b00x00p14n01i01497arch OF c08s08b00x00p14n01i01497ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable p : integer := 20;
BEGIN
case p>=20 and p<30 is
when TRUE => k := 5;
when FALSE => NULL;
when others => NULL;
end case;
assert NOT( k=5 )
report "***PASSED TEST: c08s08b00x00p14n01i01497"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s08b00x00p14n01i01497 - Case expression may be a complex static expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n01i01497arch;
|
gpl-2.0
|
4adb4e818500091092116fceea4596e8
| 0.653661 | 3.654297 | false | true | false | false |
123gmax/Digital-Lab
|
AES128/building_blocks/invMixColumn.vhd
| 2 | 50,061 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/15/2015 04:30:29 PM
-- Design Name:
-- Module Name: invMixColumn - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- x9, x11, x13, x14 are the Gallois Multiplication Lookup Tables
-- Source: https://en.wikipedia.org/wiki/Rijndael_mix_columns#Galois_Multiplication_lookup_tables
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity x9 is
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end x9;
architecture Behavioral of x9 is
begin
process(byteIn)
begin
case byteIn is
when x"00" => byteOut <= x"00";
when x"01" => byteOut <= x"09";
when x"02" => byteOut <= x"12";
when x"03" => byteOut <= x"1B";
when x"04" => byteOut <= x"24";
when x"05" => byteOut <= x"2D";
when x"06" => byteOut <= x"36";
when x"07" => byteOut <= x"3F";
when x"08" => byteOut <= x"48";
when x"09" => byteOut <= x"41";
when x"0A" => byteOut <= x"5A";
when x"0B" => byteOut <= x"53";
when x"0C" => byteOut <= x"6C";
when x"0D" => byteOut <= x"65";
when x"0E" => byteOut <= x"7E";
when x"0F" => byteOut <= x"77";
when x"10" => byteOut <= x"90";
when x"11" => byteOut <= x"99";
when x"12" => byteOut <= x"82";
when x"13" => byteOut <= x"8B";
when x"14" => byteOut <= x"B4";
when x"15" => byteOut <= x"BD";
when x"16" => byteOut <= x"A6";
when x"17" => byteOut <= x"AF";
when x"18" => byteOut <= x"D8";
when x"19" => byteOut <= x"D1";
when x"1A" => byteOut <= x"CA";
when x"1B" => byteOut <= x"C3";
when x"1C" => byteOut <= x"FC";
when x"1D" => byteOut <= x"F5";
when x"1E" => byteOut <= x"EE";
when x"1F" => byteOut <= x"E7";
when x"20" => byteOut <= x"3B";
when x"21" => byteOut <= x"32";
when x"22" => byteOut <= x"29";
when x"23" => byteOut <= x"20";
when x"24" => byteOut <= x"1F";
when x"25" => byteOut <= x"16";
when x"26" => byteOut <= x"0D";
when x"27" => byteOut <= x"04";
when x"28" => byteOut <= x"73";
when x"29" => byteOut <= x"7A";
when x"2A" => byteOut <= x"61";
when x"2B" => byteOut <= x"68";
when x"2C" => byteOut <= x"57";
when x"2D" => byteOut <= x"5E";
when x"2E" => byteOut <= x"45";
when x"2F" => byteOut <= x"4C";
when x"30" => byteOut <= x"AB";
when x"31" => byteOut <= x"A2";
when x"32" => byteOut <= x"B9";
when x"33" => byteOut <= x"B0";
when x"34" => byteOut <= x"8F";
when x"35" => byteOut <= x"86";
when x"36" => byteOut <= x"9D";
when x"37" => byteOut <= x"94";
when x"38" => byteOut <= x"E3";
when x"39" => byteOut <= x"EA";
when x"3A" => byteOut <= x"F1";
when x"3B" => byteOut <= x"F8";
when x"3C" => byteOut <= x"C7";
when x"3D" => byteOut <= x"CE";
when x"3E" => byteOut <= x"D5";
when x"3F" => byteOut <= x"DC";
when x"40" => byteOut <= x"76";
when x"41" => byteOut <= x"7F";
when x"42" => byteOut <= x"64";
when x"43" => byteOut <= x"6D";
when x"44" => byteOut <= x"52";
when x"45" => byteOut <= x"5B";
when x"46" => byteOut <= x"40";
when x"47" => byteOut <= x"49";
when x"48" => byteOut <= x"3E";
when x"49" => byteOut <= x"37";
when x"4A" => byteOut <= x"2C";
when x"4B" => byteOut <= x"25";
when x"4C" => byteOut <= x"1A";
when x"4D" => byteOut <= x"13";
when x"4E" => byteOut <= x"08";
when x"4F" => byteOut <= x"01";
when x"50" => byteOut <= x"E6";
when x"51" => byteOut <= x"EF";
when x"52" => byteOut <= x"F4";
when x"53" => byteOut <= x"FD";
when x"54" => byteOut <= x"C2";
when x"55" => byteOut <= x"CB";
when x"56" => byteOut <= x"D0";
when x"57" => byteOut <= x"D9";
when x"58" => byteOut <= x"AE";
when x"59" => byteOut <= x"A7";
when x"5A" => byteOut <= x"BC";
when x"5B" => byteOut <= x"B5";
when x"5C" => byteOut <= x"8A";
when x"5D" => byteOut <= x"83";
when x"5E" => byteOut <= x"98";
when x"5F" => byteOut <= x"91";
when x"60" => byteOut <= x"4D";
when x"61" => byteOut <= x"44";
when x"62" => byteOut <= x"5F";
when x"63" => byteOut <= x"56";
when x"64" => byteOut <= x"69";
when x"65" => byteOut <= x"60";
when x"66" => byteOut <= x"7B";
when x"67" => byteOut <= x"72";
when x"68" => byteOut <= x"05";
when x"69" => byteOut <= x"0C";
when x"6A" => byteOut <= x"17";
when x"6B" => byteOut <= x"1E";
when x"6C" => byteOut <= x"21";
when x"6D" => byteOut <= x"28";
when x"6E" => byteOut <= x"33";
when x"6F" => byteOut <= x"3A";
when x"70" => byteOut <= x"DD";
when x"71" => byteOut <= x"D4";
when x"72" => byteOut <= x"CF";
when x"73" => byteOut <= x"C6";
when x"74" => byteOut <= x"F9";
when x"75" => byteOut <= x"F0";
when x"76" => byteOut <= x"EB";
when x"77" => byteOut <= x"E2";
when x"78" => byteOut <= x"95";
when x"79" => byteOut <= x"9C";
when x"7A" => byteOut <= x"87";
when x"7B" => byteOut <= x"8E";
when x"7C" => byteOut <= x"B1";
when x"7D" => byteOut <= x"B8";
when x"7E" => byteOut <= x"A3";
when x"7F" => byteOut <= x"AA";
when x"80" => byteOut <= x"EC";
when x"81" => byteOut <= x"E5";
when x"82" => byteOut <= x"FE";
when x"83" => byteOut <= x"F7";
when x"84" => byteOut <= x"C8";
when x"85" => byteOut <= x"C1";
when x"86" => byteOut <= x"DA";
when x"87" => byteOut <= x"D3";
when x"88" => byteOut <= x"A4";
when x"89" => byteOut <= x"AD";
when x"8A" => byteOut <= x"B6";
when x"8B" => byteOut <= x"BF";
when x"8C" => byteOut <= x"80";
when x"8D" => byteOut <= x"89";
when x"8E" => byteOut <= x"92";
when x"8F" => byteOut <= x"9B";
when x"90" => byteOut <= x"7C";
when x"91" => byteOut <= x"75";
when x"92" => byteOut <= x"6E";
when x"93" => byteOut <= x"67";
when x"94" => byteOut <= x"58";
when x"95" => byteOut <= x"51";
when x"96" => byteOut <= x"4A";
when x"97" => byteOut <= x"43";
when x"98" => byteOut <= x"34";
when x"99" => byteOut <= x"3D";
when x"9A" => byteOut <= x"26";
when x"9B" => byteOut <= x"2F";
when x"9C" => byteOut <= x"10";
when x"9D" => byteOut <= x"19";
when x"9E" => byteOut <= x"02";
when x"9F" => byteOut <= x"0B";
when x"A0" => byteOut <= x"D7";
when x"A1" => byteOut <= x"DE";
when x"A2" => byteOut <= x"C5";
when x"A3" => byteOut <= x"CC";
when x"A4" => byteOut <= x"F3";
when x"A5" => byteOut <= x"FA";
when x"A6" => byteOut <= x"E1";
when x"A7" => byteOut <= x"E8";
when x"A8" => byteOut <= x"9F";
when x"A9" => byteOut <= x"96";
when x"AA" => byteOut <= x"8D";
when x"AB" => byteOut <= x"84";
when x"AC" => byteOut <= x"BB";
when x"AD" => byteOut <= x"B2";
when x"AE" => byteOut <= x"A9";
when x"AF" => byteOut <= x"A0";
when x"B0" => byteOut <= x"47";
when x"B1" => byteOut <= x"4E";
when x"B2" => byteOut <= x"55";
when x"B3" => byteOut <= x"5C";
when x"B4" => byteOut <= x"63";
when x"B5" => byteOut <= x"6A";
when x"B6" => byteOut <= x"71";
when x"B7" => byteOut <= x"78";
when x"B8" => byteOut <= x"0F";
when x"B9" => byteOut <= x"06";
when x"BA" => byteOut <= x"1D";
when x"BB" => byteOut <= x"14";
when x"BC" => byteOut <= x"2B";
when x"BD" => byteOut <= x"22";
when x"BE" => byteOut <= x"39";
when x"BF" => byteOut <= x"30";
when x"C0" => byteOut <= x"9A";
when x"C1" => byteOut <= x"93";
when x"C2" => byteOut <= x"88";
when x"C3" => byteOut <= x"81";
when x"C4" => byteOut <= x"BE";
when x"C5" => byteOut <= x"B7";
when x"C6" => byteOut <= x"AC";
when x"C7" => byteOut <= x"A5";
when x"C8" => byteOut <= x"D2";
when x"C9" => byteOut <= x"DB";
when x"CA" => byteOut <= x"C0";
when x"CB" => byteOut <= x"C9";
when x"CC" => byteOut <= x"F6";
when x"CD" => byteOut <= x"FF";
when x"CE" => byteOut <= x"E4";
when x"CF" => byteOut <= x"ED";
when x"D0" => byteOut <= x"0A";
when x"D1" => byteOut <= x"03";
when x"D2" => byteOut <= x"18";
when x"D3" => byteOut <= x"11";
when x"D4" => byteOut <= x"2E";
when x"D5" => byteOut <= x"27";
when x"D6" => byteOut <= x"3C";
when x"D7" => byteOut <= x"35";
when x"D8" => byteOut <= x"42";
when x"D9" => byteOut <= x"4B";
when x"DA" => byteOut <= x"50";
when x"DB" => byteOut <= x"59";
when x"DC" => byteOut <= x"66";
when x"DD" => byteOut <= x"6F";
when x"DE" => byteOut <= x"74";
when x"DF" => byteOut <= x"7D";
when x"E0" => byteOut <= x"A1";
when x"E1" => byteOut <= x"A8";
when x"E2" => byteOut <= x"B3";
when x"E3" => byteOut <= x"BA";
when x"E4" => byteOut <= x"85";
when x"E5" => byteOut <= x"8C";
when x"E6" => byteOut <= x"97";
when x"E7" => byteOut <= x"9E";
when x"E8" => byteOut <= x"E9";
when x"E9" => byteOut <= x"E0";
when x"EA" => byteOut <= x"FB";
when x"EB" => byteOut <= x"F2";
when x"EC" => byteOut <= x"CD";
when x"ED" => byteOut <= x"C4";
when x"EE" => byteOut <= x"DF";
when x"EF" => byteOut <= x"D6";
when x"F0" => byteOut <= x"31";
when x"F1" => byteOut <= x"38";
when x"F2" => byteOut <= x"23";
when x"F3" => byteOut <= x"2A";
when x"F4" => byteOut <= x"15";
when x"F5" => byteOut <= x"1C";
when x"F6" => byteOut <= x"07";
when x"F7" => byteOut <= x"0E";
when x"F8" => byteOut <= x"79";
when x"F9" => byteOut <= x"70";
when x"FA" => byteOut <= x"6B";
when x"FB" => byteOut <= x"62";
when x"FC" => byteOut <= x"5D";
when x"FD" => byteOut <= x"54";
when x"FE" => byteOut <= x"4F";
when x"FF" => byteOut <= x"46";
when others => byteOut <= x"00";
end case;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity x11 is
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end x11;
architecture Behavioral of x11 is
begin
process(byteIn)
begin
case byteIn is
when x"00" => byteOut <= x"00";
when x"01" => byteOut <= x"0B";
when x"02" => byteOut <= x"16";
when x"03" => byteOut <= x"1D";
when x"04" => byteOut <= x"2C";
when x"05" => byteOut <= x"27";
when x"06" => byteOut <= x"3A";
when x"07" => byteOut <= x"31";
when x"08" => byteOut <= x"58";
when x"09" => byteOut <= x"53";
when x"0A" => byteOut <= x"4E";
when x"0B" => byteOut <= x"45";
when x"0C" => byteOut <= x"74";
when x"0D" => byteOut <= x"7F";
when x"0E" => byteOut <= x"62";
when x"0F" => byteOut <= x"69";
when x"10" => byteOut <= x"B0";
when x"11" => byteOut <= x"BB";
when x"12" => byteOut <= x"A6";
when x"13" => byteOut <= x"AD";
when x"14" => byteOut <= x"9C";
when x"15" => byteOut <= x"97";
when x"16" => byteOut <= x"8A";
when x"17" => byteOut <= x"81";
when x"18" => byteOut <= x"E8";
when x"19" => byteOut <= x"E3";
when x"1A" => byteOut <= x"FE";
when x"1B" => byteOut <= x"F5";
when x"1C" => byteOut <= x"C4";
when x"1D" => byteOut <= x"CF";
when x"1E" => byteOut <= x"D2";
when x"1F" => byteOut <= x"D9";
when x"20" => byteOut <= x"7B";
when x"21" => byteOut <= x"70";
when x"22" => byteOut <= x"6D";
when x"23" => byteOut <= x"66";
when x"24" => byteOut <= x"57";
when x"25" => byteOut <= x"5C";
when x"26" => byteOut <= x"41";
when x"27" => byteOut <= x"4A";
when x"28" => byteOut <= x"23";
when x"29" => byteOut <= x"28";
when x"2A" => byteOut <= x"35";
when x"2B" => byteOut <= x"3E";
when x"2C" => byteOut <= x"0F";
when x"2D" => byteOut <= x"04";
when x"2E" => byteOut <= x"19";
when x"2F" => byteOut <= x"12";
when x"30" => byteOut <= x"CB";
when x"31" => byteOut <= x"C0";
when x"32" => byteOut <= x"DD";
when x"33" => byteOut <= x"D6";
when x"34" => byteOut <= x"E7";
when x"35" => byteOut <= x"EC";
when x"36" => byteOut <= x"F1";
when x"37" => byteOut <= x"FA";
when x"38" => byteOut <= x"93";
when x"39" => byteOut <= x"98";
when x"3A" => byteOut <= x"85";
when x"3B" => byteOut <= x"8E";
when x"3C" => byteOut <= x"BF";
when x"3D" => byteOut <= x"B4";
when x"3E" => byteOut <= x"A9";
when x"3F" => byteOut <= x"A2";
when x"40" => byteOut <= x"F6";
when x"41" => byteOut <= x"FD";
when x"42" => byteOut <= x"E0";
when x"43" => byteOut <= x"EB";
when x"44" => byteOut <= x"DA";
when x"45" => byteOut <= x"D1";
when x"46" => byteOut <= x"CC";
when x"47" => byteOut <= x"C7";
when x"48" => byteOut <= x"AE";
when x"49" => byteOut <= x"A5";
when x"4A" => byteOut <= x"B8";
when x"4B" => byteOut <= x"B3";
when x"4C" => byteOut <= x"82";
when x"4D" => byteOut <= x"89";
when x"4E" => byteOut <= x"94";
when x"4F" => byteOut <= x"9F";
when x"50" => byteOut <= x"46";
when x"51" => byteOut <= x"4D";
when x"52" => byteOut <= x"50";
when x"53" => byteOut <= x"5B";
when x"54" => byteOut <= x"6A";
when x"55" => byteOut <= x"61";
when x"56" => byteOut <= x"7C";
when x"57" => byteOut <= x"77";
when x"58" => byteOut <= x"1E";
when x"59" => byteOut <= x"15";
when x"5A" => byteOut <= x"08";
when x"5B" => byteOut <= x"03";
when x"5C" => byteOut <= x"32";
when x"5D" => byteOut <= x"39";
when x"5E" => byteOut <= x"24";
when x"5F" => byteOut <= x"2F";
when x"60" => byteOut <= x"8D";
when x"61" => byteOut <= x"86";
when x"62" => byteOut <= x"9B";
when x"63" => byteOut <= x"90";
when x"64" => byteOut <= x"A1";
when x"65" => byteOut <= x"AA";
when x"66" => byteOut <= x"B7";
when x"67" => byteOut <= x"BC";
when x"68" => byteOut <= x"D5";
when x"69" => byteOut <= x"DE";
when x"6A" => byteOut <= x"C3";
when x"6B" => byteOut <= x"C8";
when x"6C" => byteOut <= x"F9";
when x"6D" => byteOut <= x"F2";
when x"6E" => byteOut <= x"EF";
when x"6F" => byteOut <= x"E4";
when x"70" => byteOut <= x"3D";
when x"71" => byteOut <= x"36";
when x"72" => byteOut <= x"2B";
when x"73" => byteOut <= x"20";
when x"74" => byteOut <= x"11";
when x"75" => byteOut <= x"1A";
when x"76" => byteOut <= x"07";
when x"77" => byteOut <= x"0C";
when x"78" => byteOut <= x"65";
when x"79" => byteOut <= x"6E";
when x"7A" => byteOut <= x"73";
when x"7B" => byteOut <= x"78";
when x"7C" => byteOut <= x"49";
when x"7D" => byteOut <= x"42";
when x"7E" => byteOut <= x"5F";
when x"7F" => byteOut <= x"54";
when x"80" => byteOut <= x"F7";
when x"81" => byteOut <= x"FC";
when x"82" => byteOut <= x"E1";
when x"83" => byteOut <= x"EA";
when x"84" => byteOut <= x"DB";
when x"85" => byteOut <= x"D0";
when x"86" => byteOut <= x"CD";
when x"87" => byteOut <= x"C6";
when x"88" => byteOut <= x"AF";
when x"89" => byteOut <= x"A4";
when x"8A" => byteOut <= x"B9";
when x"8B" => byteOut <= x"B2";
when x"8C" => byteOut <= x"83";
when x"8D" => byteOut <= x"88";
when x"8E" => byteOut <= x"95";
when x"8F" => byteOut <= x"9E";
when x"90" => byteOut <= x"47";
when x"91" => byteOut <= x"4C";
when x"92" => byteOut <= x"51";
when x"93" => byteOut <= x"5A";
when x"94" => byteOut <= x"6B";
when x"95" => byteOut <= x"60";
when x"96" => byteOut <= x"7D";
when x"97" => byteOut <= x"76";
when x"98" => byteOut <= x"1F";
when x"99" => byteOut <= x"14";
when x"9A" => byteOut <= x"09";
when x"9B" => byteOut <= x"02";
when x"9C" => byteOut <= x"33";
when x"9D" => byteOut <= x"38";
when x"9E" => byteOut <= x"25";
when x"9F" => byteOut <= x"2E";
when x"A0" => byteOut <= x"8C";
when x"A1" => byteOut <= x"87";
when x"A2" => byteOut <= x"9A";
when x"A3" => byteOut <= x"91";
when x"A4" => byteOut <= x"A0";
when x"A5" => byteOut <= x"AB";
when x"A6" => byteOut <= x"B6";
when x"A7" => byteOut <= x"BD";
when x"A8" => byteOut <= x"D4";
when x"A9" => byteOut <= x"DF";
when x"AA" => byteOut <= x"C2";
when x"AB" => byteOut <= x"C9";
when x"AC" => byteOut <= x"F8";
when x"AD" => byteOut <= x"F3";
when x"AE" => byteOut <= x"EE";
when x"AF" => byteOut <= x"E5";
when x"B0" => byteOut <= x"3C";
when x"B1" => byteOut <= x"37";
when x"B2" => byteOut <= x"2A";
when x"B3" => byteOut <= x"21";
when x"B4" => byteOut <= x"10";
when x"B5" => byteOut <= x"1B";
when x"B6" => byteOut <= x"06";
when x"B7" => byteOut <= x"0D";
when x"B8" => byteOut <= x"64";
when x"B9" => byteOut <= x"6F";
when x"BA" => byteOut <= x"72";
when x"BB" => byteOut <= x"79";
when x"BC" => byteOut <= x"48";
when x"BD" => byteOut <= x"43";
when x"BE" => byteOut <= x"5E";
when x"BF" => byteOut <= x"55";
when x"C0" => byteOut <= x"01";
when x"C1" => byteOut <= x"0A";
when x"C2" => byteOut <= x"17";
when x"C3" => byteOut <= x"1C";
when x"C4" => byteOut <= x"2D";
when x"C5" => byteOut <= x"26";
when x"C6" => byteOut <= x"3B";
when x"C7" => byteOut <= x"30";
when x"C8" => byteOut <= x"59";
when x"C9" => byteOut <= x"52";
when x"CA" => byteOut <= x"4F";
when x"CB" => byteOut <= x"44";
when x"CC" => byteOut <= x"75";
when x"CD" => byteOut <= x"7E";
when x"CE" => byteOut <= x"63";
when x"CF" => byteOut <= x"68";
when x"D0" => byteOut <= x"B1";
when x"D1" => byteOut <= x"BA";
when x"D2" => byteOut <= x"A7";
when x"D3" => byteOut <= x"AC";
when x"D4" => byteOut <= x"9D";
when x"D5" => byteOut <= x"96";
when x"D6" => byteOut <= x"8B";
when x"D7" => byteOut <= x"80";
when x"D8" => byteOut <= x"E9";
when x"D9" => byteOut <= x"E2";
when x"DA" => byteOut <= x"FF";
when x"DB" => byteOut <= x"F4";
when x"DC" => byteOut <= x"C5";
when x"DD" => byteOut <= x"CE";
when x"DE" => byteOut <= x"D3";
when x"DF" => byteOut <= x"D8";
when x"E0" => byteOut <= x"7A";
when x"E1" => byteOut <= x"71";
when x"E2" => byteOut <= x"6C";
when x"E3" => byteOut <= x"67";
when x"E4" => byteOut <= x"56";
when x"E5" => byteOut <= x"5D";
when x"E6" => byteOut <= x"40";
when x"E7" => byteOut <= x"4B";
when x"E8" => byteOut <= x"22";
when x"E9" => byteOut <= x"29";
when x"EA" => byteOut <= x"34";
when x"EB" => byteOut <= x"3F";
when x"EC" => byteOut <= x"0E";
when x"ED" => byteOut <= x"05";
when x"EE" => byteOut <= x"18";
when x"EF" => byteOut <= x"13";
when x"F0" => byteOut <= x"CA";
when x"F1" => byteOut <= x"C1";
when x"F2" => byteOut <= x"DC";
when x"F3" => byteOut <= x"D7";
when x"F4" => byteOut <= x"E6";
when x"F5" => byteOut <= x"ED";
when x"F6" => byteOut <= x"F0";
when x"F7" => byteOut <= x"FB";
when x"F8" => byteOut <= x"92";
when x"F9" => byteOut <= x"99";
when x"FA" => byteOut <= x"84";
when x"FB" => byteOut <= x"8F";
when x"FC" => byteOut <= x"BE";
when x"FD" => byteOut <= x"B5";
when x"FE" => byteOut <= x"A8";
when x"FF" => byteOut <= x"A3";
when others => byteOut <= x"00";
end case;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity x13 is
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end x13;
architecture Behavioral of x13 is
begin
process(byteIn)
begin
case byteIn is
when x"00" => byteOut <= x"00";
when x"01" => byteOut <= x"0D";
when x"02" => byteOut <= x"1A";
when x"03" => byteOut <= x"17";
when x"04" => byteOut <= x"34";
when x"05" => byteOut <= x"39";
when x"06" => byteOut <= x"2E";
when x"07" => byteOut <= x"23";
when x"08" => byteOut <= x"68";
when x"09" => byteOut <= x"65";
when x"0A" => byteOut <= x"72";
when x"0B" => byteOut <= x"7F";
when x"0C" => byteOut <= x"5C";
when x"0D" => byteOut <= x"51";
when x"0E" => byteOut <= x"46";
when x"0F" => byteOut <= x"4B";
when x"10" => byteOut <= x"D0";
when x"11" => byteOut <= x"DD";
when x"12" => byteOut <= x"CA";
when x"13" => byteOut <= x"C7";
when x"14" => byteOut <= x"E4";
when x"15" => byteOut <= x"E9";
when x"16" => byteOut <= x"FE";
when x"17" => byteOut <= x"F3";
when x"18" => byteOut <= x"B8";
when x"19" => byteOut <= x"B5";
when x"1A" => byteOut <= x"A2";
when x"1B" => byteOut <= x"AF";
when x"1C" => byteOut <= x"8C";
when x"1D" => byteOut <= x"81";
when x"1E" => byteOut <= x"96";
when x"1F" => byteOut <= x"9B";
when x"20" => byteOut <= x"BB";
when x"21" => byteOut <= x"B6";
when x"22" => byteOut <= x"A1";
when x"23" => byteOut <= x"AC";
when x"24" => byteOut <= x"8F";
when x"25" => byteOut <= x"82";
when x"26" => byteOut <= x"95";
when x"27" => byteOut <= x"98";
when x"28" => byteOut <= x"D3";
when x"29" => byteOut <= x"DE";
when x"2A" => byteOut <= x"C9";
when x"2B" => byteOut <= x"C4";
when x"2C" => byteOut <= x"E7";
when x"2D" => byteOut <= x"EA";
when x"2E" => byteOut <= x"FD";
when x"2F" => byteOut <= x"F0";
when x"30" => byteOut <= x"6B";
when x"31" => byteOut <= x"66";
when x"32" => byteOut <= x"71";
when x"33" => byteOut <= x"7C";
when x"34" => byteOut <= x"5F";
when x"35" => byteOut <= x"52";
when x"36" => byteOut <= x"45";
when x"37" => byteOut <= x"48";
when x"38" => byteOut <= x"03";
when x"39" => byteOut <= x"0E";
when x"3A" => byteOut <= x"19";
when x"3B" => byteOut <= x"14";
when x"3C" => byteOut <= x"37";
when x"3D" => byteOut <= x"3A";
when x"3E" => byteOut <= x"2D";
when x"3F" => byteOut <= x"20";
when x"40" => byteOut <= x"6D";
when x"41" => byteOut <= x"60";
when x"42" => byteOut <= x"77";
when x"43" => byteOut <= x"7A";
when x"44" => byteOut <= x"59";
when x"45" => byteOut <= x"54";
when x"46" => byteOut <= x"43";
when x"47" => byteOut <= x"4E";
when x"48" => byteOut <= x"05";
when x"49" => byteOut <= x"08";
when x"4A" => byteOut <= x"1F";
when x"4B" => byteOut <= x"12";
when x"4C" => byteOut <= x"31";
when x"4D" => byteOut <= x"3C";
when x"4E" => byteOut <= x"2B";
when x"4F" => byteOut <= x"26";
when x"50" => byteOut <= x"BD";
when x"51" => byteOut <= x"B0";
when x"52" => byteOut <= x"A7";
when x"53" => byteOut <= x"AA";
when x"54" => byteOut <= x"89";
when x"55" => byteOut <= x"84";
when x"56" => byteOut <= x"93";
when x"57" => byteOut <= x"9E";
when x"58" => byteOut <= x"D5";
when x"59" => byteOut <= x"D8";
when x"5A" => byteOut <= x"CF";
when x"5B" => byteOut <= x"C2";
when x"5C" => byteOut <= x"E1";
when x"5D" => byteOut <= x"EC";
when x"5E" => byteOut <= x"FB";
when x"5F" => byteOut <= x"F6";
when x"60" => byteOut <= x"D6";
when x"61" => byteOut <= x"DB";
when x"62" => byteOut <= x"CC";
when x"63" => byteOut <= x"C1";
when x"64" => byteOut <= x"E2";
when x"65" => byteOut <= x"EF";
when x"66" => byteOut <= x"F8";
when x"67" => byteOut <= x"F5";
when x"68" => byteOut <= x"BE";
when x"69" => byteOut <= x"B3";
when x"6A" => byteOut <= x"A4";
when x"6B" => byteOut <= x"A9";
when x"6C" => byteOut <= x"8A";
when x"6D" => byteOut <= x"87";
when x"6E" => byteOut <= x"90";
when x"6F" => byteOut <= x"9D";
when x"70" => byteOut <= x"06";
when x"71" => byteOut <= x"0B";
when x"72" => byteOut <= x"1C";
when x"73" => byteOut <= x"11";
when x"74" => byteOut <= x"32";
when x"75" => byteOut <= x"3F";
when x"76" => byteOut <= x"28";
when x"77" => byteOut <= x"25";
when x"78" => byteOut <= x"6E";
when x"79" => byteOut <= x"63";
when x"7A" => byteOut <= x"74";
when x"7B" => byteOut <= x"79";
when x"7C" => byteOut <= x"5A";
when x"7D" => byteOut <= x"57";
when x"7E" => byteOut <= x"40";
when x"7F" => byteOut <= x"4D";
when x"80" => byteOut <= x"DA";
when x"81" => byteOut <= x"D7";
when x"82" => byteOut <= x"C0";
when x"83" => byteOut <= x"CD";
when x"84" => byteOut <= x"EE";
when x"85" => byteOut <= x"E3";
when x"86" => byteOut <= x"F4";
when x"87" => byteOut <= x"F9";
when x"88" => byteOut <= x"B2";
when x"89" => byteOut <= x"BF";
when x"8A" => byteOut <= x"A8";
when x"8B" => byteOut <= x"A5";
when x"8C" => byteOut <= x"86";
when x"8D" => byteOut <= x"8B";
when x"8E" => byteOut <= x"9C";
when x"8F" => byteOut <= x"91";
when x"90" => byteOut <= x"0A";
when x"91" => byteOut <= x"07";
when x"92" => byteOut <= x"10";
when x"93" => byteOut <= x"1D";
when x"94" => byteOut <= x"3E";
when x"95" => byteOut <= x"33";
when x"96" => byteOut <= x"24";
when x"97" => byteOut <= x"29";
when x"98" => byteOut <= x"62";
when x"99" => byteOut <= x"6F";
when x"9A" => byteOut <= x"78";
when x"9B" => byteOut <= x"75";
when x"9C" => byteOut <= x"56";
when x"9D" => byteOut <= x"5B";
when x"9E" => byteOut <= x"4C";
when x"9F" => byteOut <= x"41";
when x"A0" => byteOut <= x"61";
when x"A1" => byteOut <= x"6C";
when x"A2" => byteOut <= x"7B";
when x"A3" => byteOut <= x"76";
when x"A4" => byteOut <= x"55";
when x"A5" => byteOut <= x"58";
when x"A6" => byteOut <= x"4F";
when x"A7" => byteOut <= x"42";
when x"A8" => byteOut <= x"09";
when x"A9" => byteOut <= x"04";
when x"AA" => byteOut <= x"13";
when x"AB" => byteOut <= x"1E";
when x"AC" => byteOut <= x"3D";
when x"AD" => byteOut <= x"30";
when x"AE" => byteOut <= x"27";
when x"AF" => byteOut <= x"2A";
when x"B0" => byteOut <= x"B1";
when x"B1" => byteOut <= x"BC";
when x"B2" => byteOut <= x"AB";
when x"B3" => byteOut <= x"A6";
when x"B4" => byteOut <= x"85";
when x"B5" => byteOut <= x"88";
when x"B6" => byteOut <= x"9F";
when x"B7" => byteOut <= x"92";
when x"B8" => byteOut <= x"D9";
when x"B9" => byteOut <= x"D4";
when x"BA" => byteOut <= x"C3";
when x"BB" => byteOut <= x"CE";
when x"BC" => byteOut <= x"ED";
when x"BD" => byteOut <= x"E0";
when x"BE" => byteOut <= x"F7";
when x"BF" => byteOut <= x"FA";
when x"C0" => byteOut <= x"B7";
when x"C1" => byteOut <= x"BA";
when x"C2" => byteOut <= x"AD";
when x"C3" => byteOut <= x"A0";
when x"C4" => byteOut <= x"83";
when x"C5" => byteOut <= x"8E";
when x"C6" => byteOut <= x"99";
when x"C7" => byteOut <= x"94";
when x"C8" => byteOut <= x"DF";
when x"C9" => byteOut <= x"D2";
when x"CA" => byteOut <= x"C5";
when x"CB" => byteOut <= x"C8";
when x"CC" => byteOut <= x"EB";
when x"CD" => byteOut <= x"E6";
when x"CE" => byteOut <= x"F1";
when x"CF" => byteOut <= x"FC";
when x"D0" => byteOut <= x"67";
when x"D1" => byteOut <= x"6A";
when x"D2" => byteOut <= x"7D";
when x"D3" => byteOut <= x"70";
when x"D4" => byteOut <= x"53";
when x"D5" => byteOut <= x"5E";
when x"D6" => byteOut <= x"49";
when x"D7" => byteOut <= x"44";
when x"D8" => byteOut <= x"0F";
when x"D9" => byteOut <= x"02";
when x"DA" => byteOut <= x"15";
when x"DB" => byteOut <= x"18";
when x"DC" => byteOut <= x"3B";
when x"DD" => byteOut <= x"36";
when x"DE" => byteOut <= x"21";
when x"DF" => byteOut <= x"2C";
when x"E0" => byteOut <= x"0C";
when x"E1" => byteOut <= x"01";
when x"E2" => byteOut <= x"16";
when x"E3" => byteOut <= x"1B";
when x"E4" => byteOut <= x"38";
when x"E5" => byteOut <= x"35";
when x"E6" => byteOut <= x"22";
when x"E7" => byteOut <= x"2F";
when x"E8" => byteOut <= x"64";
when x"E9" => byteOut <= x"69";
when x"EA" => byteOut <= x"7E";
when x"EB" => byteOut <= x"73";
when x"EC" => byteOut <= x"50";
when x"ED" => byteOut <= x"5D";
when x"EE" => byteOut <= x"4A";
when x"EF" => byteOut <= x"47";
when x"F0" => byteOut <= x"DC";
when x"F1" => byteOut <= x"D1";
when x"F2" => byteOut <= x"C6";
when x"F3" => byteOut <= x"CB";
when x"F4" => byteOut <= x"E8";
when x"F5" => byteOut <= x"E5";
when x"F6" => byteOut <= x"F2";
when x"F7" => byteOut <= x"FF";
when x"F8" => byteOut <= x"B4";
when x"F9" => byteOut <= x"B9";
when x"FA" => byteOut <= x"AE";
when x"FB" => byteOut <= x"A3";
when x"FC" => byteOut <= x"80";
when x"FD" => byteOut <= x"8D";
when x"FE" => byteOut <= x"9A";
when x"FF" => byteOut <= x"97";
when others => byteOut <= x"00";
end case;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity x14 is
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end x14;
architecture Behavioral of x14 is
begin
process(byteIn)
begin
case byteIn is
when x"00" => byteOut <= x"00";
when x"01" => byteOut <= x"0E";
when x"02" => byteOut <= x"1C";
when x"03" => byteOut <= x"12";
when x"04" => byteOut <= x"38";
when x"05" => byteOut <= x"36";
when x"06" => byteOut <= x"24";
when x"07" => byteOut <= x"2A";
when x"08" => byteOut <= x"70";
when x"09" => byteOut <= x"7E";
when x"0A" => byteOut <= x"6C";
when x"0B" => byteOut <= x"62";
when x"0C" => byteOut <= x"48";
when x"0D" => byteOut <= x"46";
when x"0E" => byteOut <= x"54";
when x"0F" => byteOut <= x"5A";
when x"10" => byteOut <= x"E0";
when x"11" => byteOut <= x"EE";
when x"12" => byteOut <= x"FC";
when x"13" => byteOut <= x"F2";
when x"14" => byteOut <= x"D8";
when x"15" => byteOut <= x"D6";
when x"16" => byteOut <= x"C4";
when x"17" => byteOut <= x"CA";
when x"18" => byteOut <= x"90";
when x"19" => byteOut <= x"9E";
when x"1A" => byteOut <= x"8C";
when x"1B" => byteOut <= x"82";
when x"1C" => byteOut <= x"A8";
when x"1D" => byteOut <= x"A6";
when x"1E" => byteOut <= x"B4";
when x"1F" => byteOut <= x"BA";
when x"20" => byteOut <= x"DB";
when x"21" => byteOut <= x"D5";
when x"22" => byteOut <= x"C7";
when x"23" => byteOut <= x"C9";
when x"24" => byteOut <= x"E3";
when x"25" => byteOut <= x"ED";
when x"26" => byteOut <= x"FF";
when x"27" => byteOut <= x"F1";
when x"28" => byteOut <= x"AB";
when x"29" => byteOut <= x"A5";
when x"2A" => byteOut <= x"B7";
when x"2B" => byteOut <= x"B9";
when x"2C" => byteOut <= x"93";
when x"2D" => byteOut <= x"9D";
when x"2E" => byteOut <= x"8F";
when x"2F" => byteOut <= x"81";
when x"30" => byteOut <= x"3B";
when x"31" => byteOut <= x"35";
when x"32" => byteOut <= x"27";
when x"33" => byteOut <= x"29";
when x"34" => byteOut <= x"03";
when x"35" => byteOut <= x"0D";
when x"36" => byteOut <= x"1F";
when x"37" => byteOut <= x"11";
when x"38" => byteOut <= x"4B";
when x"39" => byteOut <= x"45";
when x"3A" => byteOut <= x"57";
when x"3B" => byteOut <= x"59";
when x"3C" => byteOut <= x"73";
when x"3D" => byteOut <= x"7D";
when x"3E" => byteOut <= x"6F";
when x"3F" => byteOut <= x"61";
when x"40" => byteOut <= x"AD";
when x"41" => byteOut <= x"A3";
when x"42" => byteOut <= x"B1";
when x"43" => byteOut <= x"BF";
when x"44" => byteOut <= x"95";
when x"45" => byteOut <= x"9B";
when x"46" => byteOut <= x"89";
when x"47" => byteOut <= x"87";
when x"48" => byteOut <= x"DD";
when x"49" => byteOut <= x"D3";
when x"4A" => byteOut <= x"C1";
when x"4B" => byteOut <= x"CF";
when x"4C" => byteOut <= x"E5";
when x"4D" => byteOut <= x"EB";
when x"4E" => byteOut <= x"F9";
when x"4F" => byteOut <= x"F7";
when x"50" => byteOut <= x"4D";
when x"51" => byteOut <= x"43";
when x"52" => byteOut <= x"51";
when x"53" => byteOut <= x"5F";
when x"54" => byteOut <= x"75";
when x"55" => byteOut <= x"7B";
when x"56" => byteOut <= x"69";
when x"57" => byteOut <= x"67";
when x"58" => byteOut <= x"3D";
when x"59" => byteOut <= x"33";
when x"5A" => byteOut <= x"21";
when x"5B" => byteOut <= x"2F";
when x"5C" => byteOut <= x"05";
when x"5D" => byteOut <= x"0B";
when x"5E" => byteOut <= x"19";
when x"5F" => byteOut <= x"17";
when x"60" => byteOut <= x"76";
when x"61" => byteOut <= x"78";
when x"62" => byteOut <= x"6A";
when x"63" => byteOut <= x"64";
when x"64" => byteOut <= x"4E";
when x"65" => byteOut <= x"40";
when x"66" => byteOut <= x"52";
when x"67" => byteOut <= x"5C";
when x"68" => byteOut <= x"06";
when x"69" => byteOut <= x"08";
when x"6A" => byteOut <= x"1A";
when x"6B" => byteOut <= x"14";
when x"6C" => byteOut <= x"3E";
when x"6D" => byteOut <= x"30";
when x"6E" => byteOut <= x"22";
when x"6F" => byteOut <= x"2C";
when x"70" => byteOut <= x"96";
when x"71" => byteOut <= x"98";
when x"72" => byteOut <= x"8A";
when x"73" => byteOut <= x"84";
when x"74" => byteOut <= x"AE";
when x"75" => byteOut <= x"A0";
when x"76" => byteOut <= x"B2";
when x"77" => byteOut <= x"BC";
when x"78" => byteOut <= x"E6";
when x"79" => byteOut <= x"E8";
when x"7A" => byteOut <= x"FA";
when x"7B" => byteOut <= x"F4";
when x"7C" => byteOut <= x"DE";
when x"7D" => byteOut <= x"D0";
when x"7E" => byteOut <= x"C2";
when x"7F" => byteOut <= x"CC";
when x"80" => byteOut <= x"41";
when x"81" => byteOut <= x"4F";
when x"82" => byteOut <= x"5D";
when x"83" => byteOut <= x"53";
when x"84" => byteOut <= x"79";
when x"85" => byteOut <= x"77";
when x"86" => byteOut <= x"65";
when x"87" => byteOut <= x"6B";
when x"88" => byteOut <= x"31";
when x"89" => byteOut <= x"3F";
when x"8A" => byteOut <= x"2D";
when x"8B" => byteOut <= x"23";
when x"8C" => byteOut <= x"09";
when x"8D" => byteOut <= x"07";
when x"8E" => byteOut <= x"15";
when x"8F" => byteOut <= x"1B";
when x"90" => byteOut <= x"A1";
when x"91" => byteOut <= x"AF";
when x"92" => byteOut <= x"BD";
when x"93" => byteOut <= x"B3";
when x"94" => byteOut <= x"99";
when x"95" => byteOut <= x"97";
when x"96" => byteOut <= x"85";
when x"97" => byteOut <= x"8B";
when x"98" => byteOut <= x"D1";
when x"99" => byteOut <= x"DF";
when x"9A" => byteOut <= x"CD";
when x"9B" => byteOut <= x"C3";
when x"9C" => byteOut <= x"E9";
when x"9D" => byteOut <= x"E7";
when x"9E" => byteOut <= x"F5";
when x"9F" => byteOut <= x"FB";
when x"A0" => byteOut <= x"9A";
when x"A1" => byteOut <= x"94";
when x"A2" => byteOut <= x"86";
when x"A3" => byteOut <= x"88";
when x"A4" => byteOut <= x"A2";
when x"A5" => byteOut <= x"AC";
when x"A6" => byteOut <= x"BE";
when x"A7" => byteOut <= x"B0";
when x"A8" => byteOut <= x"EA";
when x"A9" => byteOut <= x"E4";
when x"AA" => byteOut <= x"F6";
when x"AB" => byteOut <= x"F8";
when x"AC" => byteOut <= x"D2";
when x"AD" => byteOut <= x"DC";
when x"AE" => byteOut <= x"CE";
when x"AF" => byteOut <= x"C0";
when x"B0" => byteOut <= x"7A";
when x"B1" => byteOut <= x"74";
when x"B2" => byteOut <= x"66";
when x"B3" => byteOut <= x"68";
when x"B4" => byteOut <= x"42";
when x"B5" => byteOut <= x"4C";
when x"B6" => byteOut <= x"5E";
when x"B7" => byteOut <= x"50";
when x"B8" => byteOut <= x"0A";
when x"B9" => byteOut <= x"04";
when x"BA" => byteOut <= x"16";
when x"BB" => byteOut <= x"18";
when x"BC" => byteOut <= x"32";
when x"BD" => byteOut <= x"3C";
when x"BE" => byteOut <= x"2E";
when x"BF" => byteOut <= x"20";
when x"C0" => byteOut <= x"EC";
when x"C1" => byteOut <= x"E2";
when x"C2" => byteOut <= x"F0";
when x"C3" => byteOut <= x"FE";
when x"C4" => byteOut <= x"D4";
when x"C5" => byteOut <= x"DA";
when x"C6" => byteOut <= x"C8";
when x"C7" => byteOut <= x"C6";
when x"C8" => byteOut <= x"9C";
when x"C9" => byteOut <= x"92";
when x"CA" => byteOut <= x"80";
when x"CB" => byteOut <= x"8E";
when x"CC" => byteOut <= x"A4";
when x"CD" => byteOut <= x"AA";
when x"CE" => byteOut <= x"B8";
when x"CF" => byteOut <= x"B6";
when x"D0" => byteOut <= x"0C";
when x"D1" => byteOut <= x"02";
when x"D2" => byteOut <= x"10";
when x"D3" => byteOut <= x"1E";
when x"D4" => byteOut <= x"34";
when x"D5" => byteOut <= x"3A";
when x"D6" => byteOut <= x"28";
when x"D7" => byteOut <= x"26";
when x"D8" => byteOut <= x"7C";
when x"D9" => byteOut <= x"72";
when x"DA" => byteOut <= x"60";
when x"DB" => byteOut <= x"6E";
when x"DC" => byteOut <= x"44";
when x"DD" => byteOut <= x"4A";
when x"DE" => byteOut <= x"58";
when x"DF" => byteOut <= x"56";
when x"E0" => byteOut <= x"37";
when x"E1" => byteOut <= x"39";
when x"E2" => byteOut <= x"2B";
when x"E3" => byteOut <= x"25";
when x"E4" => byteOut <= x"0F";
when x"E5" => byteOut <= x"01";
when x"E6" => byteOut <= x"13";
when x"E7" => byteOut <= x"1D";
when x"E8" => byteOut <= x"47";
when x"E9" => byteOut <= x"49";
when x"EA" => byteOut <= x"5B";
when x"EB" => byteOut <= x"55";
when x"EC" => byteOut <= x"7F";
when x"ED" => byteOut <= x"71";
when x"EE" => byteOut <= x"63";
when x"EF" => byteOut <= x"6D";
when x"F0" => byteOut <= x"D7";
when x"F1" => byteOut <= x"D9";
when x"F2" => byteOut <= x"CB";
when x"F3" => byteOut <= x"C5";
when x"F4" => byteOut <= x"EF";
when x"F5" => byteOut <= x"E1";
when x"F6" => byteOut <= x"F3";
when x"F7" => byteOut <= x"FD";
when x"F8" => byteOut <= x"A7";
when x"F9" => byteOut <= x"A9";
when x"FA" => byteOut <= x"BB";
when x"FB" => byteOut <= x"B5";
when x"FC" => byteOut <= x"9F";
when x"FD" => byteOut <= x"91";
when x"FE" => byteOut <= x"83";
when x"FF" => byteOut <= x"8D";
when others => byteOut <= x"00";
end case;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity invMixColumn is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end invMixColumn;
architecture Behavioral of invMixColumn is
signal t0_x1, t0_x9, t0_x11, t0_x13, t0_x14 : STD_LOGIC_VECTOR(7 downto 0);
signal t1_x1, t1_x9, t1_x11, t1_x13, t1_x14 : STD_LOGIC_VECTOR(7 downto 0);
signal t2_x1, t2_x9, t2_x11, t2_x13, t2_x14 : STD_LOGIC_VECTOR(7 downto 0);
signal t3_x1, t3_x9, t3_x11, t3_x13, t3_x14 : STD_LOGIC_VECTOR(7 downto 0);
component x9
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component x11
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component x13
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component x14
Port ( byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
begin
t0_x1 <= wordIn(31 downto 24);
t1_x1 <= wordIn(23 downto 16);
t2_x1 <= wordIn(15 downto 8);
t3_x1 <= wordIn(7 downto 0);
t0x9: x9 port map(byteIn => t0_x1, byteOut => t0_x9);
t1x9: x9 port map(byteIn => t1_x1, byteOut => t1_x9);
t2x9: x9 port map(byteIn => t2_x1, byteOut => t2_x9);
t3x9: x9 port map(byteIn => t3_x1, byteOut => t3_x9);
t0x11: x11 port map(byteIn => t0_x1, byteOut => t0_x11);
t1x11: x11 port map(byteIn => t1_x1, byteOut => t1_x11);
t2x11: x11 port map(byteIn => t2_x1, byteOut => t2_x11);
t3x11: x11 port map(byteIn => t3_x1, byteOut => t3_x11);
t0x13: x13 port map(byteIn => t0_x1, byteOut => t0_x13);
t1x13: x13 port map(byteIn => t1_x1, byteOut => t1_x13);
t2x13: x13 port map(byteIn => t2_x1, byteOut => t2_x13);
t3x13: x13 port map(byteIn => t3_x1, byteOut => t3_x13);
t0x14: x14 port map(byteIn => t0_x1, byteOut => t0_x14);
t1x14: x14 port map(byteIn => t1_x1, byteOut => t1_x14);
t2x14: x14 port map(byteIn => t2_x1, byteOut => t2_x14);
t3x14: x14 port map(byteIn => t3_x1, byteOut => t3_x14);
process(CLK, RESET, wordIn)
begin
if RESET = '1' then
wordOut <= (others => '0');
elsif rising_edge(CLK) then
wordOut(31 downto 24) <= t0_x14 XOR t1_x11 XOR t2_x13 XOR t3_x9;
wordOut(23 downto 16) <= t0_x9 XOR t1_x14 XOR t2_x11 XOR t3_x13;
wordOut(15 downto 8) <= t0_x13 XOR t1_x9 XOR t2_x14 XOR t3_x11;
wordOut(7 downto 0) <= t0_x11 XOR t1_x13 XOR t2_x9 XOR t3_x14;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
e434c5c68c88bf18cad35898322f2d67
| 0.406664 | 3.149283 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug20597/20597.vhd
| 3 | 445 |
library ieee;
use ieee.std_logic_1164.all;
entity e is
end entity e;
architecture a of e is
signal operator_for_cmp : std_logic_vector(7 downto 0) := (others => 'X');
begin
process (operator_for_cmp) is
begin
case operator_for_cmp is
when "00000000" =>
null;
when "00000001" =>
null;
when "00000002" => -- Me being stupid
null;
when "00000003" => --Again
when others => null;
end case;
end process;
end architecture;
|
gpl-2.0
|
82c7f0850aba9790f8949375488ddc82
| 0.665169 | 2.986577 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.a-Alu.core/a.b.a.a-Adder.core/a.b.a.a.a-P4Adder.vhd
| 1 | 2,069 |
--------------------------------------------------------------------------------
-- FILE: P4Adder
-- DESC: The Adder used in P4 micro-processor
--
-- Author:
-- Create: 2015-05-27
-- Update: 2015-05-27
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity P4Adder is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE;
SPARSITY : integer := C_ADD_SPARSITY
);
port(
cin : in std_logic;
a, b : in std_logic_vector(DATA_SIZE-1 downto 0);
s : out std_logic_vector(DATA_SIZE-1 downto 0);
cout : out std_logic
);
end P4Adder;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture p4_adder_arch of P4Adder is
component P4CarryGenerator is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE;
SPARSITY: integer := C_ADD_SPARSITY
);
port(
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
cin: in std_logic;
cout: out std_logic_vector(DATA_SIZE/SPARSITY-1 downto 0)
);
end component;
component AdderSumGenerator is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
SPARSITY : integer := C_ADD_SPARSITY
);
port (
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
cin: in std_logic_vector(DATA_SIZE/SPARSITY-1 downto 0);
sum: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
signal carry : std_logic_vector(DATA_SIZE/SPARSITY downto 0);
begin
carry(0) <= cin;
CG0: P4CarryGenerator
generic map (DATA_SIZE, SPARSITY)
port map(a, b, cin, carry(DATA_SIZE/SPARSITY downto 1));
SG0: AdderSumGenerator
generic map (DATA_SIZE, SPARSITY)
port map(a, b, carry(DATA_SIZE/SPARSITY-1 downto 0), s);
cout <= carry(DATA_SIZE/SPARSITY);
end p4_adder_arch;
|
mit
|
929a1a129b3ba948fa6987886ce11b8f
| 0.523441 | 3.542808 | false | false | false | false |
ddelafue/SimpleGPU
|
demo_master_slave/amm_master_qsys_with_pcie/amm_master_qsys_with_pcie_inst.vhd
| 1 | 15,331 |
component amm_master_qsys_with_pcie is
port (
clk_50_clk : in std_logic := 'X'; -- clk
custom_module_conduit_rdwr_cntl : in std_logic := 'X'; -- rdwr_cntl
custom_module_conduit_n_action : in std_logic := 'X'; -- n_action
custom_module_conduit_add_data_sel : in std_logic := 'X'; -- add_data_sel
custom_module_conduit_rdwr_address : in std_logic_vector(27 downto 0) := (others => 'X'); -- rdwr_address
custom_module_conduit_display_data : out std_logic_vector(31 downto 0); -- display_data
pcie_ip_clocks_sim_clk250_export : out std_logic; -- clk250_export
pcie_ip_clocks_sim_clk500_export : out std_logic; -- clk500_export
pcie_ip_clocks_sim_clk125_export : out std_logic; -- clk125_export
pcie_ip_pcie_rstn_export : in std_logic := 'X'; -- export
pcie_ip_pipe_ext_pipe_mode : in std_logic := 'X'; -- pipe_mode
pcie_ip_pipe_ext_phystatus_ext : in std_logic := 'X'; -- phystatus_ext
pcie_ip_pipe_ext_rate_ext : out std_logic; -- rate_ext
pcie_ip_pipe_ext_powerdown_ext : out std_logic_vector(1 downto 0); -- powerdown_ext
pcie_ip_pipe_ext_txdetectrx_ext : out std_logic; -- txdetectrx_ext
pcie_ip_pipe_ext_rxelecidle0_ext : in std_logic := 'X'; -- rxelecidle0_ext
pcie_ip_pipe_ext_rxdata0_ext : in std_logic_vector(7 downto 0) := (others => 'X'); -- rxdata0_ext
pcie_ip_pipe_ext_rxstatus0_ext : in std_logic_vector(2 downto 0) := (others => 'X'); -- rxstatus0_ext
pcie_ip_pipe_ext_rxvalid0_ext : in std_logic := 'X'; -- rxvalid0_ext
pcie_ip_pipe_ext_rxdatak0_ext : in std_logic := 'X'; -- rxdatak0_ext
pcie_ip_pipe_ext_txdata0_ext : out std_logic_vector(7 downto 0); -- txdata0_ext
pcie_ip_pipe_ext_txdatak0_ext : out std_logic; -- txdatak0_ext
pcie_ip_pipe_ext_rxpolarity0_ext : out std_logic; -- rxpolarity0_ext
pcie_ip_pipe_ext_txcompl0_ext : out std_logic; -- txcompl0_ext
pcie_ip_pipe_ext_txelecidle0_ext : out std_logic; -- txelecidle0_ext
pcie_ip_powerdown_pll_powerdown : in std_logic := 'X'; -- pll_powerdown
pcie_ip_powerdown_gxb_powerdown : in std_logic := 'X'; -- gxb_powerdown
pcie_ip_reconfig_busy_busy_altgxb_reconfig : in std_logic := 'X'; -- busy_altgxb_reconfig
pcie_ip_reconfig_fromgxb_0_data : out std_logic_vector(4 downto 0); -- data
pcie_ip_reconfig_togxb_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- data
pcie_ip_refclk_export : in std_logic := 'X'; -- export
pcie_ip_rx_in_rx_datain_0 : in std_logic := 'X'; -- rx_datain_0
pcie_ip_test_in_test_in : in std_logic_vector(39 downto 0) := (others => 'X'); -- test_in
pcie_ip_tx_out_tx_dataout_0 : out std_logic; -- tx_dataout_0
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_addr : out std_logic_vector(11 downto 0); -- addr
sdram_ba : out std_logic_vector(1 downto 0); -- ba
sdram_cas_n : out std_logic; -- cas_n
sdram_cke : out std_logic; -- cke
sdram_cs_n : out std_logic; -- cs_n
sdram_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- dq
sdram_dqm : out std_logic_vector(3 downto 0); -- dqm
sdram_ras_n : out std_logic; -- ras_n
sdram_we_n : out std_logic; -- we_n
video_vga_controller_0_external_interface_CLK : out std_logic; -- CLK
video_vga_controller_0_external_interface_HS : out std_logic; -- HS
video_vga_controller_0_external_interface_VS : out std_logic; -- VS
video_vga_controller_0_external_interface_BLANK : out std_logic; -- BLANK
video_vga_controller_0_external_interface_SYNC : out std_logic; -- SYNC
video_vga_controller_0_external_interface_R : out std_logic_vector(7 downto 0); -- R
video_vga_controller_0_external_interface_G : out std_logic_vector(7 downto 0); -- G
video_vga_controller_0_external_interface_B : out std_logic_vector(7 downto 0) -- B
);
end component amm_master_qsys_with_pcie;
u0 : component amm_master_qsys_with_pcie
port map (
clk_50_clk => CONNECTED_TO_clk_50_clk, -- clk_50.clk
custom_module_conduit_rdwr_cntl => CONNECTED_TO_custom_module_conduit_rdwr_cntl, -- custom_module_conduit.rdwr_cntl
custom_module_conduit_n_action => CONNECTED_TO_custom_module_conduit_n_action, -- .n_action
custom_module_conduit_add_data_sel => CONNECTED_TO_custom_module_conduit_add_data_sel, -- .add_data_sel
custom_module_conduit_rdwr_address => CONNECTED_TO_custom_module_conduit_rdwr_address, -- .rdwr_address
custom_module_conduit_display_data => CONNECTED_TO_custom_module_conduit_display_data, -- .display_data
pcie_ip_clocks_sim_clk250_export => CONNECTED_TO_pcie_ip_clocks_sim_clk250_export, -- pcie_ip_clocks_sim.clk250_export
pcie_ip_clocks_sim_clk500_export => CONNECTED_TO_pcie_ip_clocks_sim_clk500_export, -- .clk500_export
pcie_ip_clocks_sim_clk125_export => CONNECTED_TO_pcie_ip_clocks_sim_clk125_export, -- .clk125_export
pcie_ip_pcie_rstn_export => CONNECTED_TO_pcie_ip_pcie_rstn_export, -- pcie_ip_pcie_rstn.export
pcie_ip_pipe_ext_pipe_mode => CONNECTED_TO_pcie_ip_pipe_ext_pipe_mode, -- pcie_ip_pipe_ext.pipe_mode
pcie_ip_pipe_ext_phystatus_ext => CONNECTED_TO_pcie_ip_pipe_ext_phystatus_ext, -- .phystatus_ext
pcie_ip_pipe_ext_rate_ext => CONNECTED_TO_pcie_ip_pipe_ext_rate_ext, -- .rate_ext
pcie_ip_pipe_ext_powerdown_ext => CONNECTED_TO_pcie_ip_pipe_ext_powerdown_ext, -- .powerdown_ext
pcie_ip_pipe_ext_txdetectrx_ext => CONNECTED_TO_pcie_ip_pipe_ext_txdetectrx_ext, -- .txdetectrx_ext
pcie_ip_pipe_ext_rxelecidle0_ext => CONNECTED_TO_pcie_ip_pipe_ext_rxelecidle0_ext, -- .rxelecidle0_ext
pcie_ip_pipe_ext_rxdata0_ext => CONNECTED_TO_pcie_ip_pipe_ext_rxdata0_ext, -- .rxdata0_ext
pcie_ip_pipe_ext_rxstatus0_ext => CONNECTED_TO_pcie_ip_pipe_ext_rxstatus0_ext, -- .rxstatus0_ext
pcie_ip_pipe_ext_rxvalid0_ext => CONNECTED_TO_pcie_ip_pipe_ext_rxvalid0_ext, -- .rxvalid0_ext
pcie_ip_pipe_ext_rxdatak0_ext => CONNECTED_TO_pcie_ip_pipe_ext_rxdatak0_ext, -- .rxdatak0_ext
pcie_ip_pipe_ext_txdata0_ext => CONNECTED_TO_pcie_ip_pipe_ext_txdata0_ext, -- .txdata0_ext
pcie_ip_pipe_ext_txdatak0_ext => CONNECTED_TO_pcie_ip_pipe_ext_txdatak0_ext, -- .txdatak0_ext
pcie_ip_pipe_ext_rxpolarity0_ext => CONNECTED_TO_pcie_ip_pipe_ext_rxpolarity0_ext, -- .rxpolarity0_ext
pcie_ip_pipe_ext_txcompl0_ext => CONNECTED_TO_pcie_ip_pipe_ext_txcompl0_ext, -- .txcompl0_ext
pcie_ip_pipe_ext_txelecidle0_ext => CONNECTED_TO_pcie_ip_pipe_ext_txelecidle0_ext, -- .txelecidle0_ext
pcie_ip_powerdown_pll_powerdown => CONNECTED_TO_pcie_ip_powerdown_pll_powerdown, -- pcie_ip_powerdown.pll_powerdown
pcie_ip_powerdown_gxb_powerdown => CONNECTED_TO_pcie_ip_powerdown_gxb_powerdown, -- .gxb_powerdown
pcie_ip_reconfig_busy_busy_altgxb_reconfig => CONNECTED_TO_pcie_ip_reconfig_busy_busy_altgxb_reconfig, -- pcie_ip_reconfig_busy.busy_altgxb_reconfig
pcie_ip_reconfig_fromgxb_0_data => CONNECTED_TO_pcie_ip_reconfig_fromgxb_0_data, -- pcie_ip_reconfig_fromgxb_0.data
pcie_ip_reconfig_togxb_data => CONNECTED_TO_pcie_ip_reconfig_togxb_data, -- pcie_ip_reconfig_togxb.data
pcie_ip_refclk_export => CONNECTED_TO_pcie_ip_refclk_export, -- pcie_ip_refclk.export
pcie_ip_rx_in_rx_datain_0 => CONNECTED_TO_pcie_ip_rx_in_rx_datain_0, -- pcie_ip_rx_in.rx_datain_0
pcie_ip_test_in_test_in => CONNECTED_TO_pcie_ip_test_in_test_in, -- pcie_ip_test_in.test_in
pcie_ip_tx_out_tx_dataout_0 => CONNECTED_TO_pcie_ip_tx_out_tx_dataout_0, -- pcie_ip_tx_out.tx_dataout_0
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_addr => CONNECTED_TO_sdram_addr, -- sdram.addr
sdram_ba => CONNECTED_TO_sdram_ba, -- .ba
sdram_cas_n => CONNECTED_TO_sdram_cas_n, -- .cas_n
sdram_cke => CONNECTED_TO_sdram_cke, -- .cke
sdram_cs_n => CONNECTED_TO_sdram_cs_n, -- .cs_n
sdram_dq => CONNECTED_TO_sdram_dq, -- .dq
sdram_dqm => CONNECTED_TO_sdram_dqm, -- .dqm
sdram_ras_n => CONNECTED_TO_sdram_ras_n, -- .ras_n
sdram_we_n => CONNECTED_TO_sdram_we_n, -- .we_n
video_vga_controller_0_external_interface_CLK => CONNECTED_TO_video_vga_controller_0_external_interface_CLK, -- video_vga_controller_0_external_interface.CLK
video_vga_controller_0_external_interface_HS => CONNECTED_TO_video_vga_controller_0_external_interface_HS, -- .HS
video_vga_controller_0_external_interface_VS => CONNECTED_TO_video_vga_controller_0_external_interface_VS, -- .VS
video_vga_controller_0_external_interface_BLANK => CONNECTED_TO_video_vga_controller_0_external_interface_BLANK, -- .BLANK
video_vga_controller_0_external_interface_SYNC => CONNECTED_TO_video_vga_controller_0_external_interface_SYNC, -- .SYNC
video_vga_controller_0_external_interface_R => CONNECTED_TO_video_vga_controller_0_external_interface_R, -- .R
video_vga_controller_0_external_interface_G => CONNECTED_TO_video_vga_controller_0_external_interface_G, -- .G
video_vga_controller_0_external_interface_B => CONNECTED_TO_video_vga_controller_0_external_interface_B -- .B
);
|
mit
|
bd08d6f691b3106706d75cd75d974fce
| 0.404996 | 4.423254 | false | true | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/mb_lite/gprf.vhd
| 3 | 2,366 |
----------------------------------------------------------------------------------------------
--
-- Input file : gprf.vhd
-- Design name : gprf
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The general purpose register infers memory blocks to implement
-- the register file. All outputs are registered, possibly by using
-- registered memory elements.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.core_Pkg.ALL;
USE work.std_Pkg.ALL;
ENTITY gprf IS PORT
(
gprf_o : OUT gprf_out_type;
gprf_i : IN gprf_in_type;
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END gprf;
-- This architecture is the default implementation. It
-- consists of three dual port memories. Other
-- architectures can be added while configurations can
-- control the implemented architecture.
ARCHITECTURE arch OF gprf IS
BEGIN
a : dsram GENERIC MAP
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
PORT MAP
(
dat_o => gprf_o.dat_a_o,
adr_i => gprf_i.adr_a_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
b : dsram GENERIC MAP
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
PORT MAP
(
dat_o => gprf_o.dat_b_o,
adr_i => gprf_i.adr_b_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
d : dsram GENERIC MAP
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
PORT MAP
(
dat_o => gprf_o.dat_d_o,
adr_i => gprf_i.adr_d_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
END arch;
|
mit
|
9aa7d84764ba7b34670940656e8f828a
| 0.467878 | 3.479412 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/building_blocks/invShiftRows.vhd
| 2 | 2,424 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/15/2015 03:27:35 PM
-- Design Name:
-- Module Name: invShiftRows - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity invShiftRows is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
blockIn : in STD_LOGIC_VECTOR (127 downto 0);
blockOut : out STD_LOGIC_VECTOR (127 downto 0));
end invShiftRows;
architecture Behavioral of invShiftRows is
begin
process(CLK, RESET, blockIn)
begin
if RESET = '1' then
blockOut <= (others => '0');
elsif rising_edge(CLK) then
blockOut(127 downto 120) <= blockIn(127 downto 120); --Block[0] = Block[0]
blockOut(119 downto 112) <= blockIn(23 downto 16); --Block[1] = Block[13]
blockOut(111 downto 104) <= blockIn(47 downto 40); --Block[2] = Block[10]
blockOut(103 downto 96) <= blockIn(71 downto 64); --Block[3] = Block[7]
blockOut(95 downto 88) <= blockIn(95 downto 88); --Block[4] = Block[4]
blockOut(87 downto 80) <= blockIn(119 downto 112); --Block[5] = Block[1]
blockOut(79 downto 72) <= blockIn(15 downto 8); --Block[6] = Block[14]
blockOut(71 downto 64) <= blockIn(39 downto 32); --Block[7] = Block[11]
blockOut(63 downto 56) <= blockIn(63 downto 56); --Block[8] = Block[8]
blockOut(55 downto 48) <= blockIn(87 downto 80); --Block[9] = Block[5]
blockOut(47 downto 40) <= blockIn(111 downto 104); --Block[10] = Block[2]
blockOut(39 downto 32) <= blockIn(7 downto 0); --Block[11] = Block[15]
blockOut(31 downto 24) <= blockIn(31 downto 24); --Block[12] = Block[12]
blockOut(23 downto 16) <= blockIn(55 downto 48); --Block[13] = Block[9]
blockOut(15 downto 8) <= blockIn(79 downto 72); --Block[14] = Block[6]
blockOut(7 downto 0) <= blockIn(103 downto 96); --Block[15] = Block[3]
end if;
end process;
end Behavioral;
|
gpl-2.0
|
b994981fa7690c8c100652d2dc75aaf4
| 0.526815 | 3.769829 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc88.vhd
| 4 | 1,870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc88.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x03p05n02i00088ent IS
END c04s03b01x03p05n02i00088ent;
ARCHITECTURE c04s03b01x03p05n02i00088arch OF c04s03b01x03p05n02i00088ent IS
BEGIN
TESTING: PROCESS
type rec_type is
record
a : bit;
b : character;
c : boolean;
end record;
variable x : rec_type ;
BEGIN
assert NOT( x.a = '0' and x.b = Nul and x.c = false )
report "***PASSED TEST:c04s03b01x03p05n02i00088"
severity NOTE;
assert ( x.a = '0' and x.b = Nul and x.c = false )
report "***FAILED TEST:c04s03b01x03p05n02i00088 - Variable default assignment failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x03p05n02i00088arch;
|
gpl-2.0
|
807f7f94ddc9c67b2348848a5eb5553a
| 0.651872 | 3.638132 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_09.vhd
| 4 | 5,353 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_09.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all, std.textio.all;
architecture file_loaded of memory is
begin
mem_behavior : process is
constant high_address : natural := mem_size - 1;
type memory_array is
array (natural range 0 to high_address / 4) of dlx_bv_word;
variable mem : memory_array;
-- . . . -- other variables as in architecture preloaded
procedure load is
file binary_file : text open read_mode is load_file_name;
variable L : line;
variable ch : character;
variable line_number : natural := 0;
variable addr : natural;
variable word : dlx_bv_word;
procedure read_hex_natural(L : inout line; n : out natural) is
variable result : natural := 0;
begin
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := result*16 + character'pos(ch) - character'pos('0');
elsif 'A' <= ch and ch <= 'F' then
result := result*16 + character'pos(ch) - character'pos('A') + 10;
elsif 'a' <= ch and ch <= 'f' then
result := result*16 + character'pos(ch) - character'pos('a') + 10;
else
report "Format error in file " & load_file_name
& " on line " & integer'image(line_number) severity error;
end if;
end loop;
n := result;
end read_hex_natural;
procedure read_hex_word(L : inout line; word : out dlx_bv_word) is
variable digit : natural;
variable r : natural := 0;
begin
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
digit := character'pos(ch) - character'pos('0');
elsif 'A' <= ch and ch <= 'F' then
digit := character'pos(ch) - character'pos('A') + 10;
elsif 'a' <= ch and ch <= 'f' then
digit := character'pos(ch) - character'pos('a') + 10;
else
report "Format error in file " & load_file_name
& " on line " & integer'image(line_number)
severity error;
end if;
word(r to r+3) := natural_to_bv(digit, 4);
r := r + 4;
end loop;
end read_hex_word;
begin
while not endfile(binary_file) loop
readline(binary_file, L);
line_number := line_number + 1;
read_hex_natural(L, addr);
read(L, ch); -- the space between addr and data
read_hex_word(L, word);
mem(addr / 4) := word;
end loop;
end load;
procedure do_write is -- . . . -- as in architecture preloaded
procedure do_read is -- . . . -- as in architecture preloaded
begin
load; -- read binary memory image into memory array
-- . . . -- as in architecture preloaded
end process mem_behavior;
end architecture file_loaded;
|
gpl-2.0
|
078d608542f11f08bd90d92efb83c200
| 0.414908 | 5.374498 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_sensor.vhd
| 4 | 2,178 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_sensor is
end tb_sensor;
architecture tb_sensor of tb_sensor is
-- Component declarations
-- Signal declarations
terminal vin : electrical;
signal clk, q : bit;
signal lclclkinitwire : bit := '0';
begin
-- Signal assignments
-- Component instances
v1 : entity work.v_sine(ideal)
generic map(
freq => 10.0,
amplitude => 1.0
)
port map(
pos => vin,
neg => electrical_ref
);
sens1 : entity work.sensor_wa(detailed_timing)
generic map(
threshold => 0.25,
tipd_clk => 10 ns,
tipd_input => 20.0e-9,
topd_q => 10 ns
)
port map(
input => vin,
clk => clk,
q => q
);
-- ctrl
P_ctrl :
process
begin
if (lclclkinitwire /= '1')
then
clk <= '0';
wait for 1000.000 ns;
else
clk <= '1';
wait for 5240.000 ns;
clk <= '0';
wait for 34760.000 ns;
end if;
end process P_ctrl;
KillerProc :
process
begin
wait for 1 ns;
lclclkinitwire <= '1';
wait;
end process;
end tb_sensor;
|
gpl-2.0
|
c1be8641e12a15281baceb783e8af657
| 0.608815 | 3.882353 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2128.vhd
| 4 | 2,157 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2128.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02128ent IS
END c07s02b04x00p20n01i02128ent;
ARCHITECTURE c07s02b04x00p20n01i02128arch OF c07s02b04x00p20n01i02128ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_5 is boolean_v (1 to 5);
SUBTYPE boolean_4 is boolean_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : boolean_5;
variable l_operand : boolean := true;
variable r_operand : boolean_4 := (true, false, true, false);
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = (true, true, false, true, false)) and (result(1) = true))
report "***PASSED TEST: c07s02b04x00p20n01i02128"
severity NOTE;
assert ((result = (true, true, false, true, false)) and (result(1) = true))
report "***FAILED TEST: c07s02b04x00p20n01i02128 - Concatenation of element and BOOLEAN array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02128arch;
|
gpl-2.0
|
3a2f1381a74fd8734660ad7531d818fa
| 0.662958 | 3.680887 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Gura/Modular/celda_A.vhd
| 1 | 1,442 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_A is
generic(
NUM_BITS : positive := 163
);
port(
A : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
B : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c0 : in STD_LOGIC;
c1 : in STD_LOGIC;
toA : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_A is
----------------------------------------------------------------------------------------------------
signal R1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal A1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal B1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
A1 <= A when c0 = '1' else
(others => '0');
B1 <= B when c1 = '1' else
(others => '0');
R1 <= A1 xor B1;
toA <= '0'&R1(NUM_BITS downto 1);
end behave;
|
gpl-3.0
|
1f6c4fb2fa1992090c45938085da7316
| 0.343273 | 4.534591 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-leftof.vhdl
| 4 | 432 |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'leftof(2) = 1 report "TEST FAILED. leftof 2 = 1" severity FAILURE;
report "TEST PASSED leftof 2 = 1" severity NOTE;
assert small'leftof(3) = 2 report "TEST FAILED. leftof 3 = 2" severity FAILURE;
report "TEST PASSED leftof 3 = 2" severity NOTE;
wait;
end process p;
end only;
|
gpl-2.0
|
6e2dda089fe667579231eb03ff87d47b
| 0.701389 | 3.348837 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd
| 4 | 1,698 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity mux is
end entity mux;
architecture test of mux is
constant prop_delay : time := 5 ns;
signal a, b, sel, z : bit;
begin
-- code from book
mux : process (a, b, sel) is
begin
case sel is
when '0' =>
z <= a after prop_delay;
when '1' =>
z <= b after prop_delay;
end case;
end process mux;
-- end code from book
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0010",
"0100",
"0111",
"1001",
"1010",
"1101",
"1111" );
begin
for i in stim_vector'range loop
(a, b, sel) <= stim_vector(i)(0 to 2);
wait for 10 ns;
assert z = stim_vector(i)(3);
end loop;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
b301017a2d966d78df9eef880f2e8c7e
| 0.64841 | 3.748344 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_reg_file.vhd
| 1 | 10,455 |
-- #################################################################################################
-- # << NEO430 - CPU Register File >> #
-- # ********************************************************************************************* #
-- # General data registers, program counter, status register and constant generator. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_reg_file is
generic (
BOOTLD_USE : boolean := true; -- implement and use bootloader?
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory?
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, low-active, async
-- data input --
alu_i : in std_ulogic_vector(15 downto 0); -- data from alu
addr_i : in std_ulogic_vector(15 downto 0); -- data from addr unit
flag_i : in std_ulogic_vector(04 downto 0); -- new ALU flags
-- control --
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0);
-- data output --
data_o : out std_ulogic_vector(15 downto 0); -- read data
sreg_o : out std_ulogic_vector(15 downto 0) -- current SR
);
end neo430_reg_file;
architecture neo430_reg_file_rtl of neo430_reg_file is
-- boot address for PC --
-- boot from beginning of boot ROM (boot_base_c) if bootloader is used, otherwise boot from beginning of IMEM (imem_base_c)
-- By not using a reset-like init of the PC, the whole register file (except for SR and CG)
-- can be mapped to distributed RAM saving logic resources
constant pc_boot_addr_c : std_ulogic_vector(15 downto 0) := cond_sel_stdulogicvector_f(BOOTLD_USE, boot_base_c, imem_base_c);
-- register file (including dummy regs) --
type reg_file_t is array (15 downto 0) of std_ulogic_vector(15 downto 0);
signal reg_file : reg_file_t;
signal sreg : std_ulogic_vector(15 downto 0);
signal sreg_int : std_ulogic_vector(15 downto 0);
--- RAM attribute to inhibit bypass-logic - Altera only! ---
attribute ramstyle : string;
attribute ramstyle of reg_file : signal is "no_rw_check";
-- misc --
signal in_data : std_ulogic_vector(15 downto 0); -- input selection
begin
-- Input Operand Selection --------------------------------------------------
-- -----------------------------------------------------------------------------
in_data <= pc_boot_addr_c when (ctrl_i(ctrl_rf_boot_c) = '1') else
addr_i when (ctrl_i(ctrl_rf_in_sel_c) = '1') else alu_i;
-- Register File Write Access -----------------------------------------------
-- -----------------------------------------------------------------------------
sreg_write: process(rst_i, clk_i)
begin
if (rst_i = '0') then
sreg <= (others => '0'); -- here we NEED a true hardware reset
elsif rising_edge(clk_i) then
-- physical status register --
if ((ctrl_i(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) = reg_sr_c) and (ctrl_i(ctrl_rf_wb_en_c) = '1')) then -- valid SREG write
sreg(sreg_c_c) <= in_data(sreg_c_c);
sreg(sreg_z_c) <= in_data(sreg_z_c);
sreg(sreg_n_c) <= in_data(sreg_n_c);
sreg(sreg_i_c) <= in_data(sreg_i_c);
sreg(sreg_s_c) <= in_data(sreg_s_c);
sreg(sreg_v_c) <= in_data(sreg_v_c);
sreg(sreg_q_c) <= in_data(sreg_q_c);
if (use_xalu_c = true) then -- implement parity computation?
sreg(sreg_p_c) <= in_data(sreg_p_c);
end if;
if (IMEM_AS_ROM = false) then -- r-flag is 0 when IMEM is ROM
sreg(sreg_r_c) <= in_data(sreg_r_c);
end if;
else -- automatic update
sreg(sreg_q_c) <= '0'; -- auto-clear
-- disable sleep mode --
if (ctrl_i(ctrl_rf_dsleep_c) = '1') then
sreg(sreg_s_c) <= '0';
end if;
-- disable interrupt enable --
if (ctrl_i(ctrl_rf_dgie_c) = '1') then
sreg(sreg_i_c) <= '0';
end if;
-- update ALU flags --
if (ctrl_i(ctrl_rf_fup_c) = '1') then
sreg(sreg_c_c) <= flag_i(flag_c_c);
sreg(sreg_z_c) <= flag_i(flag_z_c);
sreg(sreg_n_c) <= flag_i(flag_n_c);
sreg(sreg_v_c) <= flag_i(flag_v_c);
if (use_xalu_c = true) then -- implement parity computation?
sreg(sreg_p_c) <= flag_i(flag_p_c);
end if;
end if;
end if;
end if;
end process sreg_write;
-- construct logical status register --
sreg_combine: process(sreg)
begin
-- SREG for system --
sreg_o <= (others => '0');
sreg_o(sreg_c_c) <= sreg(sreg_c_c);
sreg_o(sreg_z_c) <= sreg(sreg_z_c);
sreg_o(sreg_n_c) <= sreg(sreg_n_c);
sreg_o(sreg_i_c) <= sreg(sreg_i_c);
sreg_o(sreg_s_c) <= sreg(sreg_s_c);
sreg_o(sreg_v_c) <= sreg(sreg_v_c);
sreg_o(sreg_q_c) <= sreg(sreg_q_c);
sreg_o(sreg_r_c) <= sreg(sreg_r_c);
if (use_xalu_c = true) then -- implement parity computation?
sreg_o(sreg_p_c) <= sreg(sreg_p_c);
end if;
-- SREG for user --
sreg_int <= (others => '0');
sreg_int(sreg_c_c) <= sreg(sreg_c_c);
sreg_int(sreg_z_c) <= sreg(sreg_z_c);
sreg_int(sreg_n_c) <= sreg(sreg_n_c);
sreg_int(sreg_i_c) <= sreg(sreg_i_c);
sreg_int(sreg_s_c) <= sreg(sreg_s_c);
sreg_int(sreg_v_c) <= sreg(sreg_v_c);
--sreg_int(sreg_q_c) <= sreg(sreg_q_c); -- is always zero for user
sreg_int(sreg_r_c) <= sreg(sreg_r_c);
if (use_xalu_c = true) then -- implement parity computation?
sreg_int(sreg_p_c) <= sreg(sreg_p_c);
end if;
end process sreg_combine;
-- general purpose register file (including PC, SP, dummy SR and dummy CG) --
rf_write: process(clk_i)
begin
if rising_edge(clk_i) then
if (ctrl_i(ctrl_rf_wb_en_c) = '1') then -- valid register file write
reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_adr3_c downto ctrl_rf_adr0_c)))) <= in_data;
end if;
end if;
end process rf_write;
-- Register File Read Access ------------------------------------------------
-- -----------------------------------------------------------------------------
rf_read: process(ctrl_i, reg_file, sreg_int)
variable const_sel_v : std_ulogic_vector(2 downto 0);
begin
if ((ctrl_i(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) = reg_sr_c) or
(ctrl_i(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) = reg_cg_c)) then
-- constant generator / SR read access --
const_sel_v := ctrl_i(ctrl_rf_adr0_c) & ctrl_i(ctrl_rf_as1_c) & ctrl_i(ctrl_rf_as0_c);
case const_sel_v is
when "000" => data_o <= sreg_int; -- read SR
when "001" => data_o <= x"0000"; -- absolute addressing mode
when "010" => data_o <= x"0004"; -- +4
when "011" => data_o <= x"0008"; -- +8
when "100" => data_o <= x"0000"; -- 0
when "101" => data_o <= x"0001"; -- +1
when "110" => data_o <= x"0002"; -- +2
when "111" => data_o <= x"FFFF"; -- -1
when others => data_o <= (others => '-');
end case;
else -- gp register file read access
data_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_adr3_c downto ctrl_rf_adr0_c))));
end if;
end process rf_read;
end neo430_reg_file_rtl;
|
bsd-3-clause
|
004bc4ab5d60a1f5e47b261fa7be8ec8
| 0.493544 | 3.777095 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_06.vhd
| 4 | 2,273 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_ch_16_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_16_06 is
end entity ch_16_06;
----------------------------------------------------------------
architecture test of ch_16_06 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
-- code from book:
disconnect address_bus : resolved_word after 3 ns;
disconnect others : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
b5e0dd13bf5d6f474b770350abb34b11
| 0.612407 | 3.925734 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/SingleFile/f2m_divider_113.vhd
| 1 | 9,177 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "ECC reconfigurable" ---
-- Organization : INAOE, Computer Science Department ---
-- Date : April, 2007. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
-- Para usar otro campo, cambia la constante F y el generic NUM_BITS.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_113 is
generic(
NUM_BITS : positive := 113
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_113 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 113
constant F : std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000001";
-- m = 163, the irreductible polynomial
--constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par, u_mas_v_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, INIT, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & y;
B <= F;
U <= '0' & x;
v <= (others => '0');
x_div_y <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
e01b5689406a884c2fbe2855d650424d
| 0.505503 | 4.740186 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc91.vhd
| 4 | 12,478 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc91.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c04s03b02x00p01n01i00091pkg IS
--
--
-- Declaration of composite types
-- - array types and subtypes
--
TYPE ut_chary IS ARRAY (CHARACTER RANGE <>) OF INTEGER; --unconstrained array type
TYPE ct_word IS ARRAY (0 TO 15) OF BIT; --constrained array type
SUBTYPE ust_subchary IS ut_chary; --unconstrained array subtype
SUBTYPE cst_str10 IS STRING ( 1 TO 10 ); --constrained array subtype
SUBTYPE cst_digit IS ut_chary ('0' TO '9'); --constrained array subtype
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE rt_date IS
RECORD
day : INTEGER RANGE 0 TO 31;
month : month_name;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
SUBTYPE rst_date IS rt_date;
END c04s03b02x00p01n01i00091pkg;
USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
ENTITY c04s03b02x00p01n01i00091ent_a IS
PORT (
SIGNAL STRING_prt : IN STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : IN ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : IN ct_word;
SIGNAL cst_str10_prt : IN cst_str10;
SIGNAL cst_digit_prt : IN cst_digit;
SIGNAL rt_date_prt : IN rt_date;
SIGNAL rst_date_prt : IN rst_date
);
END c04s03b02x00p01n01i00091ent_a;
ARCHITECTURE c04s03b02x00p01n01i00091arch_a OF c04s03b02x00p01n01i00091ent_a IS
BEGIN
PROCESS
BEGIN
--
FOR I IN 1 TO 7
LOOP
ASSERT STRING_prt(I) = NUL REPORT "STRING_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 0 TO 7
LOOP
ASSERT BIT_VECTOR_prt(I) = '0' REPORT "BIT_VECTOR_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN NUL TO ENQ
LOOP
ASSERT ut_chary_prt(I) = INTEGER'LEFT
REPORT "ut_chary_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 0 TO 15
LOOP
ASSERT ct_word_prt(I) = '0' REPORT "ct_word_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN 1 TO 10
LOOP
ASSERT cst_str10_prt(I) = NUL REPORT "cst_str10_prt not properly intialized" SEVERITY FAILURE;
END LOOP;
FOR I IN '0' TO '9'
LOOP
ASSERT cst_digit_prt(I) = INTEGER'LEFT
REPORT "cst_digit_prt not properly intialized" SEVERITY FAILURE; END LOOP;
ASSERT rt_date_prt.day = 0 REPORT " rt_date_prt.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_prt.month = Jan REPORT " rt_date_prt.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_prt.year = 0 REPORT " rt_date_prt.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.day = 0 REPORT "rst_date_prt.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.month = Jan REPORT "rst_date_prt.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_prt.year = 0 REPORT "rst_date_prt.year not properly intialized" SEVERITY FAILURE;
assert NOT( STRING_prt(1) = NUL and
STRING_prt(2) = NUL and
STRING_prt(3) = NUL and
STRING_prt(4) = NUL and
STRING_prt(5) = NUL and
STRING_prt(6) = NUL and
STRING_prt(7) = NUL and
BIT_VECTOR_prt(1) = '0' and
BIT_VECTOR_prt(2) = '0' and
BIT_VECTOR_prt(3) = '0' and
BIT_VECTOR_prt(4) = '0' and
BIT_VECTOR_prt(5) = '0' and
BIT_VECTOR_prt(6) = '0' and
BIT_VECTOR_prt(7) = '0' and
ut_chary_prt(NUL) = integer'left and
ut_chary_prt(SOH) = integer'left and
ut_chary_prt(STX) = integer'left and
ut_chary_prt(ETX) = integer'left and
ut_chary_prt(EOT) = integer'left and
ut_chary_prt(ENQ) = integer'left and
ct_word_prt( 0) = '0' and
ct_word_prt( 1) = '0' and
ct_word_prt( 2) = '0' and
ct_word_prt( 3) = '0' and
ct_word_prt( 4) = '0' and
ct_word_prt( 5) = '0' and
ct_word_prt( 6) = '0' and
ct_word_prt( 7) = '0' and
ct_word_prt( 8) = '0' and
ct_word_prt( 9) = '0' and
ct_word_prt(10) = '0' and
ct_word_prt(11) = '0' and
ct_word_prt(12) = '0' and
ct_word_prt(13) = '0' and
ct_word_prt(14) = '0' and
ct_word_prt(15) = '0' and
cst_str10_prt( 1) = NUL and
cst_str10_prt( 2) = NUL and
cst_str10_prt( 3) = NUL and
cst_str10_prt( 4) = NUL and
cst_str10_prt( 5) = NUL and
cst_str10_prt( 6) = NUL and
cst_str10_prt( 7) = NUL and
cst_str10_prt( 8) = NUL and
cst_str10_prt( 9) = NUL and
cst_str10_prt(10) = NUL and
cst_digit_prt('0') = integer'left and
cst_digit_prt('1') = integer'left and
cst_digit_prt('2') = integer'left and
cst_digit_prt('3') = integer'left and
cst_digit_prt('4') = integer'left and
cst_digit_prt('5') = integer'left and
cst_digit_prt('6') = integer'left and
cst_digit_prt('7') = integer'left and
cst_digit_prt('8') = integer'left and
cst_digit_prt('9') = integer'left and
rt_date_prt.day = 0 and
rt_date_prt.month = Jan and
rt_date_prt.year = 0 and
rst_date_prt.day = 0 and
rst_date_prt.month = Jan and
rst_date_prt.year = 0 )
report "***PASSED TEST: c04s03b02x00p01n01i00091"
severity NOTE;
assert ( STRING_prt(1) = NUL and
STRING_prt(2) = NUL and
STRING_prt(3) = NUL and
STRING_prt(4) = NUL and
STRING_prt(5) = NUL and
STRING_prt(6) = NUL and
STRING_prt(7) = NUL and
BIT_VECTOR_prt(1) = '0' and
BIT_VECTOR_prt(2) = '0' and
BIT_VECTOR_prt(3) = '0' and
BIT_VECTOR_prt(4) = '0' and
BIT_VECTOR_prt(5) = '0' and
BIT_VECTOR_prt(6) = '0' and
BIT_VECTOR_prt(7) = '0' and
ut_chary_prt(NUL) = integer'left and
ut_chary_prt(SOH) = integer'left and
ut_chary_prt(STX) = integer'left and
ut_chary_prt(ETX) = integer'left and
ut_chary_prt(EOT) = integer'left and
ut_chary_prt(ENQ) = integer'left and
ct_word_prt( 0) = '0' and
ct_word_prt( 1) = '0' and
ct_word_prt( 2) = '0' and
ct_word_prt( 3) = '0' and
ct_word_prt( 4) = '0' and
ct_word_prt( 5) = '0' and
ct_word_prt( 6) = '0' and
ct_word_prt( 7) = '0' and
ct_word_prt( 8) = '0' and
ct_word_prt( 9) = '0' and
ct_word_prt(10) = '0' and
ct_word_prt(11) = '0' and
ct_word_prt(12) = '0' and
ct_word_prt(13) = '0' and
ct_word_prt(14) = '0' and
ct_word_prt(15) = '0' and
cst_str10_prt( 1) = NUL and
cst_str10_prt( 2) = NUL and
cst_str10_prt( 3) = NUL and
cst_str10_prt( 4) = NUL and
cst_str10_prt( 5) = NUL and
cst_str10_prt( 6) = NUL and
cst_str10_prt( 7) = NUL and
cst_str10_prt( 8) = NUL and
cst_str10_prt( 9) = NUL and
cst_str10_prt(10) = NUL and
cst_digit_prt('0') = integer'left and
cst_digit_prt('1') = integer'left and
cst_digit_prt('2') = integer'left and
cst_digit_prt('3') = integer'left and
cst_digit_prt('4') = integer'left and
cst_digit_prt('5') = integer'left and
cst_digit_prt('6') = integer'left and
cst_digit_prt('7') = integer'left and
cst_digit_prt('8') = integer'left and
cst_digit_prt('9') = integer'left and
rt_date_prt.day = 0 and
rt_date_prt.month = Jan and
rt_date_prt.year = 0 and
rst_date_prt.day = 0 and
rst_date_prt.month = Jan and
rst_date_prt.year = 0 )
report "***FAILED TEST: c04s03b02x00p01n01i00091 - Variables as the interface objects that appear as variable parameters of subprogram."
severity ERROR;
wait;
END PROCESS;
END c04s03b02x00p01n01i00091arch_a;
USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
ENTITY c04s03b02x00p01n01i00091ent IS
END c04s03b02x00p01n01i00091ent;
ARCHITECTURE c04s03b02x00p01n01i00091arch OF c04s03b02x00p01n01i00091ent IS
COMPONENT c04s03b02x00p01n01i00091ent_a
PORT (
SIGNAL STRING_prt : IN STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : IN ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : IN ct_word;
SIGNAL cst_str10_prt : IN cst_str10;
SIGNAL cst_digit_prt : IN cst_digit;
SIGNAL rt_date_prt : IN rt_date;
SIGNAL rst_date_prt : IN rst_date
);
END COMPONENT;
for c : c04s03b02x00p01n01i00091ent_a use entity work.c04s03b02x00p01n01i00091ent_a(c04s03b02x00p01n01i00091arch_a);
SIGNAL STRING_prt : STRING (1 TO 7);
SIGNAL BIT_VECTOR_prt : BIT_VECTOR (0 TO 7);
SIGNAL ut_chary_prt : ut_chary (NUL TO ENQ);
SIGNAL ct_word_prt : ct_word;
SIGNAL cst_str10_prt : cst_str10;
SIGNAL cst_digit_prt : cst_digit;
SIGNAL rt_date_prt : rt_date;
SIGNAL rst_date_prt : rst_date;
BEGIN
C : c04s03b02x00p01n01i00091ent_a
PORT MAP ( STRING_prt,
BIT_VECTOR_prt,
ut_chary_prt,
ct_word_prt,
cst_str10_prt,
cst_digit_prt,
rt_date_prt,
rst_date_prt );
END c04s03b02x00p01n01i00091arch;
|
gpl-2.0
|
d49ce4c2038ab8d8d77cf758455008fa
| 0.502324 | 3.372432 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1372.vhd
| 4 | 6,488 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1372.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01372ent IS
END c08s05b00x00p03n01i01372ent;
ARCHITECTURE c08s05b00x00p03n01i01372arch OF c08s05b00x00p03n01i01372ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
--
BEGIN
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01372"
severity NOTE;
assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***FAILED TEST:c08s05b00x00p03n01i01372 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01372arch;
|
gpl-2.0
|
87040ff8d3c580ab099b87234a5560de
| 0.582922 | 2.957156 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.b-Extender.vhd
| 1 | 1,369 |
--------------------------------------------------------------------------------
-- FILE: Extender
-- DESC: Extend a short size number to specific size.
--
-- Author:
-- Create: 2015-05-28
-- Update: 2015-06-10
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Extender is
generic(
SRC_SIZE : integer := 1;
DEST_SIZE: integer := C_SYS_DATA_SIZE
);
port(
s : in std_logic := '0'; -- signed extend?
i : in std_logic_vector(SRC_SIZE-1 downto 0);
o : out std_logic_vector(DEST_SIZE-1 downto 0)
);
end Extender;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture extender_arch of Extender is
signal ext_bit : std_logic := '0';
begin
GE0: if DEST_SIZE <= SRC_SIZE generate
o <= i(DEST_SIZE-1 downto 0);
end generate;
GE1: if DEST_SIZE > SRC_SIZE generate
ext_bit <= s and i(SRC_SIZE-1);
o(SRC_SIZE-1 downto 0) <= i;
o(DEST_SIZE-1 downto SRC_SIZE) <= (others => ext_bit);
end generate;
end extender_arch;
|
mit
|
96be85a7536ffec6fbd7c40d39d26ad3
| 0.422936 | 4.148485 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_v_source.vhd
| 4 | 1,436 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_v_source is
end tb_v_source ;
architecture TB_v_source of tb_v_source is
terminal in_src, out_flt : electrical;
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
vio : entity work.v_source(source_sine)
port map(
p => in_src,
m => ELECTRICAL_REF
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => in_src,
p2 => electrical_ref
);
end TB_v_source ;
|
gpl-2.0
|
b3cf227f410c4e3f5fd0fb7e31d71fa1
| 0.666435 | 4.056497 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd
| 4 | 1,446 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
entity moving_mass_wa is
port ( terminal external_attachment : translational );
end entity moving_mass_wa;
----------------------------------------------------------------
architecture behavioral of moving_mass_wa is
constant mass : real := 10.0;
constant stiffness : real := 2.0;
constant damping : real := 5.0;
quantity position across driving_force through external_attachment;
quantity velocity : real;
begin
velocity == position'dot;
driving_force == mass*velocity'dot + damping*velocity + stiffness*position;
end architecture behavioral;
|
gpl-2.0
|
f1b12db502ce82c631bc2c261309201d
| 0.70332 | 4.329341 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd
| 4 | 2,116 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity adc is
port ( quantity gain : in voltage;
terminal a : electrical;
signal clk : in bit;
signal d_out : out bit );
end entity adc;
architecture ideal of adc is
constant ref : real := 5.0;
quantity v_in across a;
quantity v_amplified : voltage;
begin
v_amplified == v_in * gain;
adc_behavior: process is
variable stored_d : bit;
begin
if clk = '1' then
if v_amplified > ref / 2.0 then
stored_d := '1';
else
stored_d := '0';
end if;
end if;
d_out <= stored_d after 5 ns;
wait on clk;
end process adc_behavior;
end architecture ideal;
architecture struct of adc is
terminal a_amplified, ref, half_ref: electrical;
quantity v_ref across i_ref through ref;
signal d : bit;
begin
res1 : entity work.resistor(ideal)
port map ( ref, half_ref);
res2 : entity work.resistor(ideal)
port map ( half_ref, electrical_ref );
amp : entity work.vc_amp(ideal)
port map ( gain, a, a_amplified );
comp : entity work.comparator(ideal)
port map ( a_amplified, half_ref, d);
ff : entity work.d_ff(basic)
port map ( d, clk, d_out );
v_ref == 5.0;
end architecture struct;
|
gpl-2.0
|
66aed1bd6920d2bafb99c69a9b5c0a44
| 0.6569 | 3.798923 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/perf02/sub_160.vhd
| 3 | 1,824 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_160 is
port (
output : out std_logic_vector(63 downto 0);
lt : out std_logic;
le : out std_logic;
sign : in std_logic;
ge : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end sub_160;
architecture augh of sub_160 is
signal carry_inA : std_logic_vector(65 downto 0);
signal carry_inB : std_logic_vector(65 downto 0);
signal carry_res : std_logic_vector(65 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(64 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(63) & in_b(63) & carry_res(64);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "001" or msb_abr = "111") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011" or msb_abr = "111") else
'0';
ge <= tmp_ge;
lt <= not(tmp_ge);
le <= tmp_le;
end architecture;
|
gpl-2.0
|
90c3f9e850f2eae8df083e8214a79ea4
| 0.620066 | 2.554622 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2466.vhd
| 4 | 2,094 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2466.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02466ent IS
END c07s03b02x02p03n02i02466ent;
ARCHITECTURE c07s03b02x02p03n02i02466arch OF c07s03b02x02p03n02i02466ent IS
type UN_ARR is array (integer range <>) of character;
subtype CON_ARR is UN_ARR( 1 to 5 ) ;
signal S : CON_ARR := ('A','Z', others => 'C'); -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT(S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C')
report "***PASSED TEST: c07s03b02x02p03n02i02466"
severity NOTE;
assert (S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C')
report "***FAILED TEST: c07s03b02x02p03n02i02466 - An array aggregate with an others choice may appear as the expression defining the initial value of the drivers of one or more signals in an initialization specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02466arch;
|
gpl-2.0
|
3d0d21cbabdb305f07e4c22be0bd857e
| 0.661891 | 3.507538 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Gura/Modular/gura_modular_131.vhd
| 1 | 5,438 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_131 is
generic(
NUM_BITS : positive := 131
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_131 is
----------------------------------------------------------------------------------------------------
-- m = 131, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001101";
-- control signals
signal CASO: std_logic_vector(1 downto 0);
signal c_4, c_5,c_6,a_greater_b,a_eq_b: std_logic;
signal CA, CB : STD_LOGIC_VECTOR(7 downto 0);
signal U, A, V, B,X2, Y2, temp1, toA, toB, toU, toV: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
X2 <= x & '0';
Y2 <= y & '0';
caso <= "01" when (A(0) = '1' and B(0) = '0') or CurrentState = LOAD1 else
"10" when A(0) = '0' else
"11";
c_5 <= '0' when rst = '1' or currentState = LOAD1 else
'1';
c_6 <= '1' when CurrentState = LOAD1 else
'0';
a_greater_b <= '1' when CA > CB else
'0';
a_eq_b <= '1' when A = B else
'0';
--a_eq_b <= '1' when CA = "00000000" else
-- '0';
c_4 <= '0' when CurrentState = Load1 or temp1(0) = '0' else
'1';
celda_reg_A: entity celda_a(behave)
generic map (NUM_BITS)
port map( A, B,caso(1), caso(0), toA);
celda_reg_U: entity celda_U(behave)
generic map (NUM_BITS)
port map(U, V, caso(1), caso(0), temp1);
celda_reg_mod_P: entity mod_P(behave)
generic map (NUM_BITS)
port map(temp1, P, c_4, toU);
celda_reg_B: entity celda_B(behave)
generic map (NUM_BITS)
port map(toA,P,Y2,c_5,c_6, toB);
celda_reg_V: entity celda_v(behave)
generic map (NUM_BITS)
port map(toU,X2,c_5,c_6,toV);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= (others => '0');
U <= (others => '0');
B <= toB;
V <= toV;
CA <= "10000010" ;
CB <= "10000001" ;
x_div_y <= (others => '0');
done <= '0';
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
A <= toA;
U <= toU;
B <= toB;
V <= toV;
currentState <= Cycle;
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
elsif CASO = "10" then
A <= toA;
CA <= CA-1;
U <= toU;
elsif CASO = "01" then
B <= toB;
CB <= CB -1;
V <= toV;
elsif a_greater_b = '1' then
A <= toA;
CA <= CA-1;
U <= toU;
else
B <= toB;
CB <= CB-1;
V <= toV;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
468eeb0d5b9c01f43222071f4b2700e2
| 0.39886 | 3.972243 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug15993/testbench_15993.vhdl
| 3 | 3,700 |
-- Test Bench
-- inspired from http://ghdl.free.fr/ghdl/A-full-adder.html#A-full-adder
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------------
ENTITY add_tb IS
END add_tb;
-------------------------------------------------------------------------------
ARCHITECTURE behave OF add_tb IS
COMPONENT add4
GENERIC ( n : INTEGER := 4 );
PORT ( a, b : IN STD_LOGIC_VECTOR ( n-1 DOWNTO 0 );
cin : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR ( n DOWNTO 0 ) );
END COMPONENT;
FOR ALL: add4 USE ENTITY work.addern;
SIGNAL i0, i1 : STD_LOGIC_VECTOR ( 3 DOWNTO 0 );
SIGNAL s : STD_LOGIC_VECTOR ( 4 DOWNTO 0 );
SIGNAL ci : STD_LOGIC;
subtype hexstring is string(1 to 12);
function to_hex(n: in std_logic_vector) return hexstring is
variable n_int : std_logic_vector(n'high + 3 downto 0);
variable digit : unsigned(3 downto 0);
variable d_pos : natural;
variable s : hexstring := (others => ' ');
begin
-- assert n'high < 32 report "Hex conversion failed; supports 32 bits max!" severity warning;
n_int := (others => '0');
n_int(n'range) := n;
for i in 1 to (n'length + 3)/4 loop
d_pos := ((n'length + 3)/4 - i) * 4;
digit := unsigned(n_int(d_pos+3 downto d_pos));
-- look after metavalues...
if Is_X(std_logic_vector(digit)) then
s(i) := 'X';
elsif digit > 9 then
s(i) := character'val(character'pos('A')
+ to_integer(digit) - 10);
else
s(i) := character'val(character'pos('0')
+ to_integer(digit));
end if;
end loop;
return s;
end to_hex;
BEGIN
adder0: add4
PORT MAP ( a => i0, b => i1, cin => ci, sum => s );
-- This process does the real job.
PROCESS
TYPE pattern_type IS RECORD
-- The inputs of the adder.
i0, i1 : STD_LOGIC_VECTOR( 3 DOWNTO 0 );
ci : STD_LOGIC;
-- The expected outputs of the adder.
s : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
END RECORD;
-- The patterns to apply.
TYPE pattern_array IS ARRAY (natural RANGE <>) OF pattern_type;
CONSTANT patterns : pattern_array :=
(("0000", "0000", '0', "00000"),
("0000", "0001", '0', "00001"),
("0001", "0000", '0', "00001"),
("0001", "0001", '0', "00010"),
("0001", "0001", '1', "00011"),
("0001", "0010", '0', "00011"),
("0001", "0010", '1', "00100"),
("0010", "0010", '0', "00100"));
BEGIN
-- Check each pattern.
FOR i IN patterns'RANGE LOOP
-- Set the inputs.
i0 <= patterns(i).i0;
i1 <= patterns(i).i1;
ci <= patterns(i).ci;
-- Wait for the results.
WAIT FOR 1 ns;
-- Check the outputs.
ASSERT s = patterns(i).s
REPORT "bad sum : value " & to_hex(s) & "should be " & to_hex(patterns(i).s) SEVERITY note;
-- assert co = patterns(i).co
-- report "bad carray out value" severity error;
END LOOP;
ASSERT false REPORT "end of test" SEVERITY note;
-- Wait forever; this will finish the simulation.
WAIT;
END PROCESS;
END behave;
|
gpl-2.0
|
8755058da462f1a791172b7fdc913da4
| 0.46 | 3.974221 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc450.vhd
| 4 | 3,091 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc450.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00450ent IS
END c03s02b01x01p19n01i00450ent;
ARCHITECTURE c03s02b01x01p19n01i00450arch OF c03s02b01x01p19n01i00450ent IS
type four_value is ('Z','0','1','X'); --enumerated type
constant C77 : four_value := 'Z';
function complex_scalar(s : four_value) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return four_value is
begin
return C77;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : four_value;
signal S2 : four_value;
signal S3 : four_value := C77;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C77) and (S2 = C77))
report "***PASSED TEST: c03s02b01x01p19n01i00450"
severity NOTE;
assert ((S1 = C77) and (S2 = C77))
report "***FAILED TEST: c03s02b01x01p19n01i00450 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00450arch;
|
gpl-2.0
|
d931b902b6470b90df5c87a804af755b
| 0.64704 | 3.640754 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_163_3.vhd
| 1 | 14,764 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- Sin celda y sin maquina de estados
--------------------------------------------------------
-- x^163 + x^7 + x^6 + x^3 + 1
entity serial_multiplier_163 is
generic (
NUM_BITS : positive := 163 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_163;
-----------------------------------------------------------
architecture behave of serial_multiplier_163 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
signal xor_2 : std_logic;
signal xor_3 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
--type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
--signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
-- Result of the multiplication
xor_1 <= Cx_int(2) xor Cx_int(NUM_BITS-1);
xor_2 <= Cx_int(5) xor Cx_int(NUM_BITS-1);
xor_3 <= Cx_int(6) xor Cx_int(NUM_BITS-1);
--Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
bx_int <= Bx_shift; -- Shift Bx to left one position
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
done <= done_int;
cx <= cx_int;
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "00000000"; -- m-1 value, in this case, it is 112, be sure to set the correct value
cx_int <= (others => '0');
Done_int <= '0';
else
if done_int = '0' then
counter <= counter + 1;
Cx_int(0) <= ( Ax(0) and Bx_int(NUM_BITS-1) ) xor Cx_int(NUM_BITS-1);
Cx_int(1) <= ( Ax(1) and Bx_int(NUM_BITS-1) ) xor Cx_int(0);
Cx_int(2) <= ( Ax(2) and Bx_int(NUM_BITS-1) ) xor Cx_int(1);
Cx_int(3) <= ( Ax(3) and Bx_int(NUM_BITS-1) ) xor xor_1;
Cx_int(4) <= ( Ax(4) and Bx_int(NUM_BITS-1) ) xor Cx_int(3);
Cx_int(5) <= ( Ax(5) and Bx_int(NUM_BITS-1) ) xor Cx_int(4);
Cx_int(6) <= ( Ax(6) and Bx_int(NUM_BITS-1) ) xor xor_2;
Cx_int(7) <= ( Ax(7) and Bx_int(NUM_BITS-1) ) xor xor_3;
Cx_int(8) <= ( Ax(8) and Bx_int(NUM_BITS-1) ) xor Cx_int(7);
Cx_int(9) <= ( Ax(9) and Bx_int(NUM_BITS-1) ) xor Cx_int(8);
Cx_int(10) <= ( Ax(10) and Bx_int(NUM_BITS-1) ) xor Cx_int(9);
Cx_int(11) <= ( Ax(11) and Bx_int(NUM_BITS-1) ) xor Cx_int(10);
Cx_int(12) <= ( Ax(12) and Bx_int(NUM_BITS-1) ) xor Cx_int(11);
Cx_int(13) <= ( Ax(13) and Bx_int(NUM_BITS-1) ) xor Cx_int(12);
Cx_int(14) <= ( Ax(14) and Bx_int(NUM_BITS-1) ) xor Cx_int(13);
Cx_int(15) <= ( Ax(15) and Bx_int(NUM_BITS-1) ) xor Cx_int(14);
Cx_int(16) <= ( Ax(16) and Bx_int(NUM_BITS-1) ) xor Cx_int(15);
Cx_int(17) <= ( Ax(17) and Bx_int(NUM_BITS-1) ) xor Cx_int(16);
Cx_int(18) <= ( Ax(18) and Bx_int(NUM_BITS-1) ) xor Cx_int(17);
Cx_int(19) <= ( Ax(19) and Bx_int(NUM_BITS-1) ) xor Cx_int(18);
Cx_int(20) <= ( Ax(20) and Bx_int(NUM_BITS-1) ) xor Cx_int(19);
Cx_int(21) <= ( Ax(21) and Bx_int(NUM_BITS-1) ) xor Cx_int(20);
Cx_int(22) <= ( Ax(22) and Bx_int(NUM_BITS-1) ) xor Cx_int(21);
Cx_int(23) <= ( Ax(23) and Bx_int(NUM_BITS-1) ) xor Cx_int(22);
Cx_int(24) <= ( Ax(24) and Bx_int(NUM_BITS-1) ) xor Cx_int(23);
Cx_int(25) <= ( Ax(25) and Bx_int(NUM_BITS-1) ) xor Cx_int(24);
Cx_int(26) <= ( Ax(26) and Bx_int(NUM_BITS-1) ) xor Cx_int(25);
Cx_int(27) <= ( Ax(27) and Bx_int(NUM_BITS-1) ) xor Cx_int(26);
Cx_int(28) <= ( Ax(28) and Bx_int(NUM_BITS-1) ) xor Cx_int(27);
Cx_int(29) <= ( Ax(29) and Bx_int(NUM_BITS-1) ) xor Cx_int(28);
Cx_int(30) <= ( Ax(30) and Bx_int(NUM_BITS-1) ) xor Cx_int(29);
Cx_int(31) <= ( Ax(31) and Bx_int(NUM_BITS-1) ) xor Cx_int(30);
Cx_int(32) <= ( Ax(32) and Bx_int(NUM_BITS-1) ) xor Cx_int(31);
Cx_int(33) <= ( Ax(33) and Bx_int(NUM_BITS-1) ) xor Cx_int(32);
Cx_int(34) <= ( Ax(34) and Bx_int(NUM_BITS-1) ) xor Cx_int(33);
Cx_int(35) <= ( Ax(35) and Bx_int(NUM_BITS-1) ) xor Cx_int(34);
Cx_int(36) <= ( Ax(36) and Bx_int(NUM_BITS-1) ) xor Cx_int(35);
Cx_int(37) <= ( Ax(37) and Bx_int(NUM_BITS-1) ) xor Cx_int(36);
Cx_int(38) <= ( Ax(38) and Bx_int(NUM_BITS-1) ) xor Cx_int(37);
Cx_int(39) <= ( Ax(39) and Bx_int(NUM_BITS-1) ) xor Cx_int(38);
Cx_int(40) <= ( Ax(40) and Bx_int(NUM_BITS-1) ) xor Cx_int(39);
Cx_int(41) <= ( Ax(41) and Bx_int(NUM_BITS-1) ) xor Cx_int(40);
Cx_int(42) <= ( Ax(42) and Bx_int(NUM_BITS-1) ) xor Cx_int(41);
Cx_int(43) <= ( Ax(43) and Bx_int(NUM_BITS-1) ) xor Cx_int(42);
Cx_int(44) <= ( Ax(44) and Bx_int(NUM_BITS-1) ) xor Cx_int(43);
Cx_int(45) <= ( Ax(45) and Bx_int(NUM_BITS-1) ) xor Cx_int(44);
Cx_int(46) <= ( Ax(46) and Bx_int(NUM_BITS-1) ) xor Cx_int(45);
Cx_int(47) <= ( Ax(47) and Bx_int(NUM_BITS-1) ) xor Cx_int(46);
Cx_int(48) <= ( Ax(48) and Bx_int(NUM_BITS-1) ) xor Cx_int(47);
Cx_int(49) <= ( Ax(49) and Bx_int(NUM_BITS-1) ) xor Cx_int(48);
Cx_int(50) <= ( Ax(50) and Bx_int(NUM_BITS-1) ) xor Cx_int(49);
Cx_int(51) <= ( Ax(51) and Bx_int(NUM_BITS-1) ) xor Cx_int(50);
Cx_int(52) <= ( Ax(52) and Bx_int(NUM_BITS-1) ) xor Cx_int(51);
Cx_int(53) <= ( Ax(53) and Bx_int(NUM_BITS-1) ) xor Cx_int(52);
Cx_int(54) <= ( Ax(54) and Bx_int(NUM_BITS-1) ) xor Cx_int(53);
Cx_int(55) <= ( Ax(55) and Bx_int(NUM_BITS-1) ) xor Cx_int(54);
Cx_int(56) <= ( Ax(56) and Bx_int(NUM_BITS-1) ) xor Cx_int(55);
Cx_int(57) <= ( Ax(57) and Bx_int(NUM_BITS-1) ) xor Cx_int(56);
Cx_int(58) <= ( Ax(58) and Bx_int(NUM_BITS-1) ) xor Cx_int(57);
Cx_int(59) <= ( Ax(59) and Bx_int(NUM_BITS-1) ) xor Cx_int(58);
Cx_int(60) <= ( Ax(60) and Bx_int(NUM_BITS-1) ) xor Cx_int(59);
Cx_int(61) <= ( Ax(61) and Bx_int(NUM_BITS-1) ) xor Cx_int(60);
Cx_int(62) <= ( Ax(62) and Bx_int(NUM_BITS-1) ) xor Cx_int(61);
Cx_int(63) <= ( Ax(63) and Bx_int(NUM_BITS-1) ) xor Cx_int(62);
Cx_int(64) <= ( Ax(64) and Bx_int(NUM_BITS-1) ) xor Cx_int(63);
Cx_int(65) <= ( Ax(65) and Bx_int(NUM_BITS-1) ) xor Cx_int(64);
Cx_int(66) <= ( Ax(66) and Bx_int(NUM_BITS-1) ) xor Cx_int(65);
Cx_int(67) <= ( Ax(67) and Bx_int(NUM_BITS-1) ) xor Cx_int(66);
Cx_int(68) <= ( Ax(68) and Bx_int(NUM_BITS-1) ) xor Cx_int(67);
Cx_int(69) <= ( Ax(69) and Bx_int(NUM_BITS-1) ) xor Cx_int(68);
Cx_int(70) <= ( Ax(70) and Bx_int(NUM_BITS-1) ) xor Cx_int(69);
Cx_int(71) <= ( Ax(71) and Bx_int(NUM_BITS-1) ) xor Cx_int(70);
Cx_int(72) <= ( Ax(72) and Bx_int(NUM_BITS-1) ) xor Cx_int(71);
Cx_int(73) <= ( Ax(73) and Bx_int(NUM_BITS-1) ) xor Cx_int(72);
Cx_int(74) <= ( Ax(74) and Bx_int(NUM_BITS-1) ) xor Cx_int(73);
Cx_int(75) <= ( Ax(75) and Bx_int(NUM_BITS-1) ) xor Cx_int(74);
Cx_int(76) <= ( Ax(76) and Bx_int(NUM_BITS-1) ) xor Cx_int(75);
Cx_int(77) <= ( Ax(77) and Bx_int(NUM_BITS-1) ) xor Cx_int(76);
Cx_int(78) <= ( Ax(78) and Bx_int(NUM_BITS-1) ) xor Cx_int(77);
Cx_int(79) <= ( Ax(79) and Bx_int(NUM_BITS-1) ) xor Cx_int(78);
Cx_int(80) <= ( Ax(80) and Bx_int(NUM_BITS-1) ) xor Cx_int(79);
Cx_int(81) <= ( Ax(81) and Bx_int(NUM_BITS-1) ) xor Cx_int(80);
Cx_int(82) <= ( Ax(82) and Bx_int(NUM_BITS-1) ) xor Cx_int(81);
Cx_int(83) <= ( Ax(83) and Bx_int(NUM_BITS-1) ) xor Cx_int(82);
Cx_int(84) <= ( Ax(84) and Bx_int(NUM_BITS-1) ) xor Cx_int(83);
Cx_int(85) <= ( Ax(85) and Bx_int(NUM_BITS-1) ) xor Cx_int(84);
Cx_int(86) <= ( Ax(86) and Bx_int(NUM_BITS-1) ) xor Cx_int(85);
Cx_int(87) <= ( Ax(87) and Bx_int(NUM_BITS-1) ) xor Cx_int(86);
Cx_int(88) <= ( Ax(88) and Bx_int(NUM_BITS-1) ) xor Cx_int(87);
Cx_int(89) <= ( Ax(89) and Bx_int(NUM_BITS-1) ) xor Cx_int(88);
Cx_int(90) <= ( Ax(90) and Bx_int(NUM_BITS-1) ) xor Cx_int(89);
Cx_int(91) <= ( Ax(91) and Bx_int(NUM_BITS-1) ) xor Cx_int(90);
Cx_int(92) <= ( Ax(92) and Bx_int(NUM_BITS-1) ) xor Cx_int(91);
Cx_int(93) <= ( Ax(93) and Bx_int(NUM_BITS-1) ) xor Cx_int(92);
Cx_int(94) <= ( Ax(94) and Bx_int(NUM_BITS-1) ) xor Cx_int(93);
Cx_int(95) <= ( Ax(95) and Bx_int(NUM_BITS-1) ) xor Cx_int(94);
Cx_int(96) <= ( Ax(96) and Bx_int(NUM_BITS-1) ) xor Cx_int(95);
Cx_int(97) <= ( Ax(97) and Bx_int(NUM_BITS-1) ) xor Cx_int(96);
Cx_int(98) <= ( Ax(98) and Bx_int(NUM_BITS-1) ) xor Cx_int(97);
Cx_int(99) <= ( Ax(99) and Bx_int(NUM_BITS-1) ) xor Cx_int(98);
Cx_int(100) <= ( Ax(100) and Bx_int(NUM_BITS-1) ) xor Cx_int(99);
Cx_int(101) <= ( Ax(101) and Bx_int(NUM_BITS-1) ) xor Cx_int(100);
Cx_int(102) <= ( Ax(102) and Bx_int(NUM_BITS-1) ) xor Cx_int(101);
Cx_int(103) <= ( Ax(103) and Bx_int(NUM_BITS-1) ) xor Cx_int(102);
Cx_int(104) <= ( Ax(104) and Bx_int(NUM_BITS-1) ) xor Cx_int(103);
Cx_int(105) <= ( Ax(105) and Bx_int(NUM_BITS-1) ) xor Cx_int(104);
Cx_int(106) <= ( Ax(106) and Bx_int(NUM_BITS-1) ) xor Cx_int(105);
Cx_int(107) <= ( Ax(107) and Bx_int(NUM_BITS-1) ) xor Cx_int(106);
Cx_int(108) <= ( Ax(108) and Bx_int(NUM_BITS-1) ) xor Cx_int(107);
Cx_int(109) <= ( Ax(109) and Bx_int(NUM_BITS-1) ) xor Cx_int(108);
Cx_int(110) <= ( Ax(110) and Bx_int(NUM_BITS-1) ) xor Cx_int(109);
Cx_int(111) <= ( Ax(111) and Bx_int(NUM_BITS-1) ) xor Cx_int(110);
Cx_int(112) <= ( Ax(112) and Bx_int(NUM_BITS-1) ) xor Cx_int(111);
Cx_int(113) <= ( Ax(113) and Bx_int(NUM_BITS-1) ) xor Cx_int(112);
Cx_int(114) <= ( Ax(114) and Bx_int(NUM_BITS-1) ) xor Cx_int(113);
Cx_int(115) <= ( Ax(115) and Bx_int(NUM_BITS-1) ) xor Cx_int(114);
Cx_int(116) <= ( Ax(116) and Bx_int(NUM_BITS-1) ) xor Cx_int(115);
Cx_int(117) <= ( Ax(117) and Bx_int(NUM_BITS-1) ) xor Cx_int(116);
Cx_int(118) <= ( Ax(118) and Bx_int(NUM_BITS-1) ) xor Cx_int(117);
Cx_int(119) <= ( Ax(119) and Bx_int(NUM_BITS-1) ) xor Cx_int(118);
Cx_int(120) <= ( Ax(120) and Bx_int(NUM_BITS-1) ) xor Cx_int(119);
Cx_int(121) <= ( Ax(121) and Bx_int(NUM_BITS-1) ) xor Cx_int(120);
Cx_int(122) <= ( Ax(122) and Bx_int(NUM_BITS-1) ) xor Cx_int(121);
Cx_int(123) <= ( Ax(123) and Bx_int(NUM_BITS-1) ) xor Cx_int(122);
Cx_int(124) <= ( Ax(124) and Bx_int(NUM_BITS-1) ) xor Cx_int(123);
Cx_int(125) <= ( Ax(125) and Bx_int(NUM_BITS-1) ) xor Cx_int(124);
Cx_int(126) <= ( Ax(126) and Bx_int(NUM_BITS-1) ) xor Cx_int(125);
Cx_int(127) <= ( Ax(127) and Bx_int(NUM_BITS-1) ) xor Cx_int(126);
Cx_int(128) <= ( Ax(128) and Bx_int(NUM_BITS-1) ) xor Cx_int(127);
Cx_int(129) <= ( Ax(129) and Bx_int(NUM_BITS-1) ) xor Cx_int(128);
Cx_int(130) <= ( Ax(130) and Bx_int(NUM_BITS-1) ) xor Cx_int(129);
Cx_int(131) <= ( Ax(131) and Bx_int(NUM_BITS-1) ) xor Cx_int(130);
Cx_int(132) <= ( Ax(132) and Bx_int(NUM_BITS-1) ) xor Cx_int(131);
Cx_int(133) <= ( Ax(133) and Bx_int(NUM_BITS-1) ) xor Cx_int(132);
Cx_int(134) <= ( Ax(134) and Bx_int(NUM_BITS-1) ) xor Cx_int(133);
Cx_int(135) <= ( Ax(135) and Bx_int(NUM_BITS-1) ) xor Cx_int(134);
Cx_int(136) <= ( Ax(136) and Bx_int(NUM_BITS-1) ) xor Cx_int(135);
Cx_int(137) <= ( Ax(137) and Bx_int(NUM_BITS-1) ) xor Cx_int(136);
Cx_int(138) <= ( Ax(138) and Bx_int(NUM_BITS-1) ) xor Cx_int(137);
Cx_int(139) <= ( Ax(139) and Bx_int(NUM_BITS-1) ) xor Cx_int(138);
Cx_int(140) <= ( Ax(140) and Bx_int(NUM_BITS-1) ) xor Cx_int(139);
Cx_int(141) <= ( Ax(141) and Bx_int(NUM_BITS-1) ) xor Cx_int(140);
Cx_int(142) <= ( Ax(142) and Bx_int(NUM_BITS-1) ) xor Cx_int(141);
Cx_int(143) <= ( Ax(143) and Bx_int(NUM_BITS-1) ) xor Cx_int(142);
Cx_int(144) <= ( Ax(144) and Bx_int(NUM_BITS-1) ) xor Cx_int(143);
Cx_int(145) <= ( Ax(145) and Bx_int(NUM_BITS-1) ) xor Cx_int(144);
Cx_int(146) <= ( Ax(146) and Bx_int(NUM_BITS-1) ) xor Cx_int(145);
Cx_int(147) <= ( Ax(147) and Bx_int(NUM_BITS-1) ) xor Cx_int(146);
Cx_int(148) <= ( Ax(148) and Bx_int(NUM_BITS-1) ) xor Cx_int(147);
Cx_int(149) <= ( Ax(149) and Bx_int(NUM_BITS-1) ) xor Cx_int(148);
Cx_int(150) <= ( Ax(150) and Bx_int(NUM_BITS-1) ) xor Cx_int(149);
Cx_int(151) <= ( Ax(151) and Bx_int(NUM_BITS-1) ) xor Cx_int(150);
Cx_int(152) <= ( Ax(152) and Bx_int(NUM_BITS-1) ) xor Cx_int(151);
Cx_int(153) <= ( Ax(153) and Bx_int(NUM_BITS-1) ) xor Cx_int(152);
Cx_int(154) <= ( Ax(154) and Bx_int(NUM_BITS-1) ) xor Cx_int(153);
Cx_int(155) <= ( Ax(155) and Bx_int(NUM_BITS-1) ) xor Cx_int(154);
Cx_int(156) <= ( Ax(156) and Bx_int(NUM_BITS-1) ) xor Cx_int(155);
Cx_int(157) <= ( Ax(157) and Bx_int(NUM_BITS-1) ) xor Cx_int(156);
Cx_int(158) <= ( Ax(158) and Bx_int(NUM_BITS-1) ) xor Cx_int(157);
Cx_int(159) <= ( Ax(159) and Bx_int(NUM_BITS-1) ) xor Cx_int(158);
Cx_int(160) <= ( Ax(160) and Bx_int(NUM_BITS-1) ) xor Cx_int(159);
Cx_int(161) <= ( Ax(161) and Bx_int(NUM_BITS-1) ) xor Cx_int(160);
Cx_int(162) <= ( Ax(162) and Bx_int(NUM_BITS-1) ) xor Cx_int(161);
end if;
if counter = "10100010" then
done_int <= '1';
end if;
end if;
end if;
end process;
SHIFT_REGISTER: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
Bx_shift <= Bx;
else
Bx_shift <= Bx_shift(NUM_BITS-2 downto 0) & '0'; -- carga paralela
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
c4a3cfd9179c668d15aa758f7d55fdc7
| 0.526212 | 2.356584 | false | false | false | false |
tristanseifert/68komputer
|
HexDisplay.vhd
| 1 | 1,638 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- This is a simple seven-segment hexadecimal display driver. Connect up
-- InVal to a nybble, Display to a display, and values 0-F will be displayed
-- in glorious characters.
--
-- When reset, the display will show three vertical bars.
--
entity HexDisplay is
PORT (
clk: IN std_logic;
reset: IN std_logic;
Display: OUT std_logic_vector(6 downto 0) := (others => '1');
InVal: IN std_logic_vector(3 downto 0)
);
end HexDisplay;
architecture behavioral of HexDisplay is
begin
process (reset, clk, InVal)
begin
if reset='1'
then
Display <= "0110110";
elsif rising_edge(clk) then
case InVal is
when x"0" =>
Display <= "1000000";
when x"1" =>
Display <= "1001111";
when x"2" =>
Display <= "0100100";
when x"3" =>
Display <= "0110000";
when x"4" =>
Display <= "0011001";
when x"5" =>
Display <= "0010010";
when x"6" =>
Display <= "0000010";
when x"7" =>
Display <= "1111000";
when x"8" =>
Display <= "0000000";
when x"9" =>
Display <= "0011000";
when x"A" =>
Display <= "0001000";
when x"B" =>
Display <= "0000011";
when x"C" =>
Display <= "1000110";
when x"D" =>
Display <= "0100001";
when x"E" =>
Display <= "0000110";
when x"F" =>
Display <= "0001110";
end case;
end if;
end process;
end behavioral;
|
bsd-2-clause
|
2cf5631ff74e7462e9bb4e20452a48c8
| 0.544567 | 3.131931 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug04/std_logic_warning.vhdl
| 1 | 1,357 |
library ieee;
use ieee.std_logic_1164.std_logic;
use ieee.std_logic_1164.to_x01;
use ieee.std_logic_1164.is_x;
package std_logic_warning is
function "="(l, r : std_logic) return boolean;
end package;
package body std_logic_warning is
use ieee.std_logic_1164."=";
function "="(l, r : std_logic) return boolean is
begin
if is_x(l) or is_x(r) then
report "std_logic_warning.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return l = r; -- std_logic_1164."="(l, r);
end function;
end package body;
library ieee;
use ieee.std_logic_1164.std_ulogic;
use ieee.std_logic_1164.std_logic;
-- use ieee.std_logic_1164.all;
use work.std_logic_warning.all;
entity warning_test is
end entity;
architecture foo of warning_test is
signal a: std_logic;
signal b: std_logic;
begin
UNLABELLED:
process
begin
wait for 1 ns;
a <= 'X';
wait for 1 ns;
b <= '1';
wait for 1 ns;
a <= '0';
wait for 1 ns;
b <= '0';
wait;
end process;
MONITOR:
process (a,b)
begin
assert a = b
report "a = b " & "( " & std_logic'image(a)
& "=" & std_logic'image(b) & " )"
severity NOTE;
end process;
end architecture;
|
gpl-2.0
|
8ae5c1e6e5f007b9ec5f0468af205c68
| 0.568902 | 3.342365 | false | false | false | false |
mmoraless/ecc_vhdl
|
scalar_mul_serial/binaryMethod_serial_113.vhd
| 1 | 11,927 |
----------------------------------------------------------------------------|
-- Author : Miguel Morales-Sandoval Copyrights (R) |
-- Project : " Reconfigurable ECC" |
-- Organization : INAOE, Computer Science Department |
-- Date : Originally created March, 2007. |
----------------------------------------------------------------------------|
-- / o o \ This is the binary method to compute |
-- / - o o - \ scalar multiplication in affine |
-- / --- o o --- \ coordinates. It uses a module that |
-- / ---- o o ---- \ implements the ECC-ADD and ECC-DOUBLE |
-- /------ o o ----- \ at the same time. The operations are |
-- / ----- o o ----- \ performed serially. This is a m- bit |
-- / o o o o o o \ implementation. |
-- x x x |
-- x ----- x |
-- x ------- x |
-- x --------- x |
-- x --------- x |
-- ------------- |
-- _ _ _ _ ___ ___ |
-- | || \ | | / _ \ | _ || __| |
-- | || \| || |_| ||| ||||__ |
-- | || \ | || _ |||_||||__ |
-- |_||_|\__||_| |_||___||___| |
----------------------------------------------------------------------------|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity binaryMethod is
generic(
--------------------------------------------------------------
-- para la entrada y salida
CW : positive := 15; -- 15 29 29, 23, 11, 5, 7, 5 :- bits que "faltan" para ser multiplo de 32
WORD : positive := 32; -- 32 32 32, 32, 32, 32, 32, 32 :- Numero de palabra de entrada
ITR : positive := 4; -- 4 5 6, 8, 9, 9, 13, 18 :- No. de iteraciones en la máquina de estados
--------------------------------------------------------------
-- 113 131 163, 233, 277, 283, 409, 571
-- para el squarer
--------------------------------------------------------------
-- D : positive := 11; -- 11 10 9, 76, 14, 14, 89, 12 -- el "grado mas grande" para el polinomio en el campo m + 2
-- NUM2_BITS: positive := 225; --225 261 325, 465, 553, 565, 817, 1141 -- 2*NUMBITS -1
--------------------------------------------------------------
--113 131 163, 233, 277, 283, 409, 571
-- El nivel de seguridad
NUM_BITS: positive := 113
);
port(
valid_data_in :in std_logic;
valid_data_out :out std_logic;
ack_master :in std_logic;
ack_slave :out std_logic;
data_in : in std_logic_vector(WORD-1 downto 0);
data_out : out std_logic_vector(WORD-1 downto 0);
op : in std_logic; -- 0 -> Scalar multiplication, 1 -> SUM of points
clk : in std_logic;
rst : in std_logic
);
end;
------------------------------------------------------------------
architecture behave of BinaryMethod is
------------------------------------------------------------------
-- se agregaron mas estados para controlar la carga de los
-- operadores de la multiplicación escalar o de la suma
type CurrentState_type is (END_STATE, WAIT_DATA, WAIT_MORE, SEND_MORE, SEND_DATA, MODE0, WAIT_FINISH);
signal CurrentState: CurrentState_type;
------------------------------------------------------------------
signal Q_X: std_logic_vector(NUM_BITS-1 downto 0); -- Registros para manterner las operaciones ADD y Double
signal Q_Y: std_logic_vector(NUM_BITS-1 downto 0);
signal P_X: std_logic_vector(NUM_BITS-1 downto 0);
signal P_Y: std_logic_vector(NUM_BITS-1 downto 0);
signal counter: std_logic_vector(7 downto 0); -- Counter, indicates the number of iterations (m)
------------------------------------------------------------------
signal RstADD : std_logic; -- Interface signals for the ADD-Double module
signal ADD_X : std_logic_vector(NUM_BITS-1 downto 0);
signal ADD_Y : std_logic_vector(NUM_BITS-1 downto 0);
signal DoneADD: std_logic;
signal op_ADD: std_logic;
------------------------------------------------------------------
signal internal_regk : std_logic_vector(NUM_BITS-1 downto 0); -- Register to keep the shifth value of the scalar
signal K_SHIFT : std_logic_vector(NUM_BITS-1 downto 0); -- The combinatorial shifter for the scalar
------------------------------------------------------------------
-- Estas señales se agregaron para controlar y carga y salida de
-- valores desde/hacia el modulo KP
signal B_x_in : std_logic_vector((NUM_BITS+CW)-1 downto 0); -- 1 Registros de NUM_BITS bits para el siguiente corrimiento
signal B_X_shift : std_logic_vector((NUM_BITS+CW)-1 downto 0); -- Corrimiento combinacional
signal counter_word : std_logic_vector(4 downto 0); -- Contador para la carga del dato
signal mux_input : std_logic_vector(WORD-1 downto 0); -- Contador para la carga del dato
------------------------------------------------------------------
begin
------------------------------------------------------------------
-- The ADD module
ECC_ADD: entity ECC_add_serial_113(behave)
--Generic Map (D, NUM2_BITS, NUM_BITS)
Generic Map (NUM_BITS)
Port Map(Q_X, Q_Y, P_X, P_Y, clk, RstADD, op_ADD, ADD_X, ADD_Y, DoneADD);
k_shift <= internal_regk(NUM_BITS-2 downto 0) & '0'; -- Shift the scalar every time
mux_input <= data_in when currentState = WAIT_DATA else
(others => '0');
B_x_shift <= B_x_in((NUM_BITS+CW)-WORD-1 downto 0) & mux_input;
data_out <= B_x_in(NUM_BITS+CW-1 downto NUM_BITS+CW-WORD);
------------------------------------------------------------------
-- Finite state machine that implements the LEFT-TO-RIGTH
-- binary method, ADD and DOUBLING are performed serially
------------------------------------------------------------------
SCALAR_MUL_FSM: process (CLK)
Begin -- Inferencias de 6 registros de m y m+CW bits
if CLK'event and CLK = '1' then
if Rst = '1' then -- synchronous reset
Q_X <= (others => '0'); -- registros internos
Q_Y <= (others => '0'); -- para suma y double
P_X <= (others => '0');
P_Y <= (others => '0');
B_x_in <= (others => '0');
internal_regk <= (others => '0'); -- registro de corrimiento del escalar k
RstADD <= '0'; -- Señales de control para los bloques ADD y DOUBLE
counter_word <= (others => '0'); -- contador para capturar las palabras de entrada
counter <= (others => '0'); -- contador para la multiplicación escalar
CurrentState <= WAIT_DATA; -- El estado para esperar la primera secuencia de WORDS
ack_slave <= '0';
valid_data_out <= '0'; -- Señal de salida que habilida WORDs validos a la salida
else
case CurrentState is
----------------------------------------------------
when WAIT_DATA =>
if valid_data_in = '1' then
B_X_in <= B_x_shift;
ack_slave <= '1';
if counter_word = "00100" then -- ITR
P_X <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
elsif counter_word = "01000" then -- 2*ITR
P_Y <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
elsif counter_word = "01100" then -- 3*ITR
if op = '0' then -- multiplicación escalar
internal_regk <= B_x_in(NUM_BITS-1 downto 0); -- Lo que se leyo es el escalar, comenzar a ejecutar kP
op_ADD <= '0'; --Double
RstADD <= '1';
CurrentState <= MODE0;
else
Q_x <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
end if;
elsif counter_word = "10000" then --4*ITR
Q_Y <= B_X_in(NUM_BITS-1 downto 0); -- Ya tenemos los dos puntos, hacemos la suma
op_ADD <= '1'; --ADD
RstADD <= '1';
CurrentState <= MODE0;
else
CurrentState <= WAIT_MORE;
end if;
end if;
----------------------------------------------------
when WAIT_MORE => -- Espera a que el host regrese subtype señal de dato valido a cero
if valid_data_in = '0' then
ack_slave <= '0';
CurrentState <= WAIT_DATA;
Counter_word <= Counter_word + "00001";
end if;
----------------------------------------------------
when MODE0 =>
RstADD <= '0'; -- Emite el pulso al Modulo de suma y espera a que termine la operacion
CurrentState <= WAIT_FINISH;
----------------------------------------------------
when WAIT_FINISH =>
if DoneADD = '1' then -- Espera hasta que la operacion ADD termina
if op = '1' then -- solo esta suma, terminar
B_x_in <= "000000000000000" & ADD_X;
counter_word <= (others => '0');
CurrentState <= SEND_DATA;
valid_data_out <= '1';
else
Q_X <= ADD_X; -- Almacenar el resultado actual
Q_Y <= ADD_Y;
if internal_regk(NUM_BITS-1) = '1' and op_ADD = '0' then-- se comienza una nueva operacion si es qu es necesario realizar una suma
op_ADD <= '1'; -- add
RSTADD <= '1';
CurrentState <= MODE0;
else
counter <= counter + 1; -- incrementa el counter para indicar que ya se consumio un bit del escalar
if counter = "01110000" then --112 = NUM_BITS-1, if all iterations has been performed, then the operation is compleated
B_x_in <= "000000000000000" & ADD_X;
counter_word <= (others => '0');
valid_data_out <= '1';
CurrentState <= SEND_DATA;
else -- if not all iterations have been performed, do the following
internal_regk <= k_shift; -- update the scalar shifted
op_ADD <= '0'; -- operacion double
RstADD <= '1'; -- double
CurrentState <= MODE0;
end if;
end if;
end if;
end if;
----------------------------------------------------
when SEND_DATA => -- ya hay una palabra valida a la salida, esperar a que el host la lea
--espera el ack del receptor
if ack_master = '1' then
Counter_word <= Counter_word + "00001";
valid_data_out <= '0';
CurrentState <= SEND_MORE;
end if;
----------------------------------------------------
when SEND_MORE => -- pone una palabra valida mas
if ack_master = '0' then
if counter_word = "00100" then -- ITR = 4
B_x_in <= "000000000000000" & ADD_Y;
valid_data_out <= '1';
CurrentState <= SEND_DATA;
elsif counter_word = "01000" then -- 2*ITR = 8
CurrentState <= END_STATE;
else
B_x_in <= B_x_shift;
valid_data_out <= '1';
CurrentState <= SEND_DATA;
end if;
end if;
when END_STATE => -- do nothing, wait until the reset signal goes to '1'
valid_data_out <= '0';
----------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
de710db42769ddd0d9ad01787f2a4834
| 0.445879 | 3.758903 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/mlite_pack.vhd
| 2 | 21,630 |
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
GENERIC (
lpm_width : NATURAL;
lpm_widthad : NATURAL;
rden_used : STRING;
intended_device_family : STRING;
lpm_indata : STRING;
lpm_wraddress_control : STRING;
lpm_rdaddress_control : STRING;
lpm_outdata : STRING;
use_eab : STRING;
lpm_type : STRING);
PORT (
wren : IN STD_LOGIC ;
wrclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"16");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "ALTERA_LPM");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "ALTERA_LPM"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
opcode_test_out : out std_logic_vector(31 downto 0);
pc_future_test_out : out std_logic_vector(31 downto 2);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component ram
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "ALTERA_LPM"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
mit
|
1a071e1b30a57f4d8330cf68001ec4ea
| 0.547203 | 3.62069 | false | false | false | false |
123gmax/Digital-Lab
|
Lab1/Ganesh/counter/counter.vhd
| 1 | 2,447 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ganesh Hegde and Alex
--
-- Create Date: 09/01/2015 10:52:25 AM
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port (
UP: in std_logic;
AUTO: in std_logic;
LOAD: in std_logic;
VALUE: in std_logic_vector(3 downto 0);
TICK: in std_logic;
COUNT: out std_logic_vector(3 downto 0);
RESET: in std_logic;
clk: in std_logic
);
end counter;
architecture Behavioral of counter is
signal n_count:unsigned(3 downto 0);
signal p_count:unsigned(3 downto 0);
signal sum: unsigned(3 downto 0);
signal addend: unsigned(3 downto 0);
signal clk_1sec:std_logic;
signal pulse: std_logic;
signal clk_count : unsigned(26 downto 0);
begin
--Clock process
process(clk,RESET)
begin
if(RESET ='1') then
clk_1sec <= '0';
clk_count <= (others => '0');
elsif (clk' event and clk ='1') then
clk_count <= clk_count + 1;
clk_1sec <= std_logic(clk_count(26));
end if;
end process;
--State register
process(pulse,RESET)
begin
if(RESET = '1') then
p_count <= (others =>'0');
elsif(pulse' event and pulse ='1') then
p_count <= n_count;
end if;
end process;
--State reg clock logic
with AUTO select
pulse <= TICK when '0',
clk_1sec when others;
--Next state logic
with LOAD select
n_count <= sum when '0',
unsigned(VALUE) when others;
--UP/DOWN select
with UP select
addend <= "1111" when '0',
"0001" when others;
--Adder
sum <= p_count + addend;
--Output Logic
COUNT <= std_logic_vector(p_count);
end Behavioral;
|
gpl-2.0
|
104520492de51ec3d23b044ac817eb4b
| 0.566408 | 3.782071 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1495.vhd
| 4 | 1,961 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1495.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p09n01i01495ent IS
END c08s08b00x00p09n01i01495ent;
ARCHITECTURE c08s08b00x00p09n01i01495arch OF c08s08b00x00p09n01i01495ent IS
SUBTYPE string_30 is STRING(1 to 30);
SUBTYPE string_4 is STRING(1 to 4);
BEGIN
TESTING: PROCESS
VARIABLE str : string_30 := "1234567890abcdefghijlkmnopqrst";
variable k : integer := 0;
BEGIN
case string_4'(str(1 to 4)) is
when "1234" => k := 5;
when OTHERS => k := 6;
end case;
assert NOT(k=5)
report "***PASSED TEST: c08s08b00x00p09n01i01495"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c08s08b00x00p09n01i01495 - Expression being a qualified expression failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p09n01i01495arch;
|
gpl-2.0
|
f982724d631cb869f503d5e6f998f820
| 0.660887 | 3.624769 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd
| 4 | 1,686 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity comparator is
port ( terminal plus_in, minus_in : electrical;
signal output : out std_ulogic );
end entity comparator;
----------------------------------------------------------------
architecture hysteresis of comparator is
constant threshold_margin : real := 0.2;
quantity v_in across plus_in to minus_in;
begin
comp_behavior : process is
variable threshold : real := threshold_margin;
begin
if v_in > threshold then
output <= '1' after 10 ns;
threshold := -threshold_margin;
else
output <= '0' after 10 ns;
threshold := threshold_margin;
end if;
wait on v_in'above(threshold);
end process comp_behavior;
end architecture hysteresis;
|
gpl-2.0
|
daebd8623b133bc2db45e9778f2aa9a4
| 0.661329 | 4.345361 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd
| 4 | 1,495 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_freq_detect is
end tb_freq_detect;
architecture TB_freq_detect of tb_freq_detect is
terminal in_src, freq_out : electrical;
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 200.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
freq1 : entity work.freq_detect(threshold_crossing)
port map(
input => in_src,
freq_out => freq_out
);
end TB_freq_detect;
|
gpl-2.0
|
a0a73f43fa323174ff19967ef66a438a
| 0.668896 | 4.129834 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor_node.vhd
| 4 | 2,715 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity processor_node is
end entity processor_node;
-- code from book
architecture dataflow of processor_node is
-- not in book
subtype word is bit_vector(31 downto 0);
type word_vector is array (natural range <>) of word;
function resolve_unique ( drivers : word_vector ) return word is
begin
if drivers'length > 0 then
return drivers(drivers'left);
else
return X"00000000";
end if;
end function resolve_unique;
-- end not in book
signal address_bus : resolve_unique word bus;
-- . . .
-- not in book
signal cache_miss, dirty, replace_section,
snoop_hit, flag_update : bit := '0';
constant tag_section0 : bit_vector(11 downto 0) := X"000";
constant tag_section1 : bit_vector(11 downto 0) := X"001";
constant set_index : bit_vector(15 downto 0) := X"6666";
constant snoop_address : word := X"88888888";
-- end not in book
begin
cache_to_address_buffer : block ( cache_miss = '1' and dirty = '1' ) is
begin
address_bus <= guarded
tag_section0 & set_index & B"0000" when replace_section = '0' else
tag_section1 & set_index & B"0000";
end block cache_to_address_buffer;
snoop_to_address_buffer : block ( snoop_hit = '1' and flag_update = '1' ) is
begin
address_bus <= guarded snoop_address(31 downto 4) & B"0000";
end block snoop_to_address_buffer;
-- . . .
-- not in book
stimulus : process is
begin
wait for 10 ns;
dirty <= '0'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
dirty <= '1'; cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
replace_section <= '1';
cache_miss <= '1', '0' after 5 ns; wait for 10 ns;
flag_update <= '0'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
flag_update <= '1'; snoop_hit <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture dataflow;
-- end code from book
|
gpl-2.0
|
729c439a8bc4eb826b6b776df6cedbe4
| 0.661878 | 3.562992 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd
| 4 | 2,087 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
begin
process_1_b : process is
-- code from book:
type symbol is ('a', 't', 'd', 'h', digit, cr, error);
type state is range 0 to 6;
type transition_matrix is array (state, symbol) of state;
variable transition_table : transition_matrix;
-- end of code from book
variable next_state : state;
-- code from book:
type point is array (1 to 3) of real;
type matrix is array (1 to 3, 1 to 3) of real;
variable p, q : point;
variable transform : matrix;
-- end of code from book
begin
next_state :=
-- code from book:
transition_table(5, 'd');
-- end of code from book
for i in 1 to 3 loop
for j in 1 to 3 loop
if i = j then
transform(i, j) := -1.0;
else
transform(i, j) := 0.0;
end if;
end loop;
end loop;
p := (1.0, 2.0, 3.0);
-- code from book:
for i in 1 to 3 loop
q(i) := 0.0;
for j in 1 to 3 loop
q(i) := q(i) + transform(i, j) * p(j);
end loop;
end loop;
-- end of code from book
wait;
end process process_1_b;
end architecture test;
|
gpl-2.0
|
a08f6f3a70bf119162ccd3ea91f50888
| 0.607571 | 3.787659 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_control.vhd
| 1 | 37,906 |
-- #################################################################################################
-- # << NEO430 - Main Control Unit >> #
-- # ********************************************************************************************* #
-- # Central CPU control unit (micro sequencer / FSM). #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_control is
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, low-active, async
-- memory interface --
instr_i : in std_ulogic_vector(15 downto 0); -- instruction word from memory
-- control --
sreg_i : in std_ulogic_vector(15 downto 0); -- current status register
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- control signals
irq_vec_o : out std_ulogic_vector(01 downto 0); -- irq channel address
imm_o : out std_ulogic_vector(15 downto 0); -- branch offset
-- irq lines --
irq_i : in std_ulogic_vector(03 downto 0) -- IRQ lines^
);
end neo430_control;
architecture neo430_control_rtl of neo430_control is
-- instruction register --
signal ir : std_ulogic_vector(15 downto 0);
signal ir_wren : std_ulogic;
-- branch system --
signal branch_taken : std_ulogic;
-- state machine --
type state_t is (RESET, IFETCH_0, IFETCH_1, DECODE,
TRANS_0, TRANS_1, TRANS_2, TRANS_3, TRANS_4, TRANS_5, TRANS_6,
PUSHCALL_0, PUSHCALL_1, PUSHCALL_2,
RETI_0, RETI_1, RETI_2, RETI_3,
IRQ_0, IRQ_1, IRQ_2, IRQ_3, IRQ_4, IRQ_5);
signal state, state_nxt : state_t;
signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
signal am_nxt, am : std_ulogic_vector(03 downto 0); -- addressing mode
signal mem_rd, mem_rd_ff : std_ulogic; -- memory read buffers
signal src_nxt, src : std_ulogic_vector(03 downto 0); -- source reg
signal sam_nxt, sam : std_ulogic_vector(01 downto 0); -- CMD according SRC addressing mode
-- irq system --
signal irq_fire : std_ulogic;
signal irq_start, irq_ack : std_ulogic;
signal irq_ack_mask, irq_buf : std_ulogic_vector(3 downto 0);
signal irq_vec_nxt, irq_vec : std_ulogic_vector(1 downto 0);
signal i_flag_ff0, i_flag_ff1 : std_ulogic;
begin
-- Branch Condition Check ---------------------------------------------------
-- -----------------------------------------------------------------------------
cond_check: process(instr_i, sreg_i)
begin
case instr_i(12 downto 10) is -- condition
when cond_ne_c => branch_taken <= not sreg_i(sreg_z_c); -- JNE/JNZ
when cond_eq_c => branch_taken <= sreg_i(sreg_z_c); -- JEQ/JZ
when cond_lo_c => branch_taken <= not sreg_i(sreg_c_c); -- JNC/JLO
when cond_hs_c => branch_taken <= sreg_i(sreg_c_c); -- JC/JHS
when cond_mi_c => branch_taken <= sreg_i(sreg_n_c); -- JN
when cond_ge_c => branch_taken <= not (sreg_i(sreg_n_c) xor sreg_i(sreg_v_c)); -- JGE
when cond_le_c => branch_taken <= sreg_i(sreg_n_c) xor sreg_i(sreg_v_c); -- JL
when cond_al_c => branch_taken <= '1'; -- JMP (always)
when others => branch_taken <= '0'; -- undefined
end case;
end process cond_check;
-- branch offset (sign-extended) from instruction REGISTER --
imm_o <= ir(9) & ir(9) & ir(9) & ir(9) & ir(9) & ir(9 downto 0) & '0';
-- Arbiter State Machine Sync -----------------------------------------------
-- -----------------------------------------------------------------------------
arbiter_sync0: process(rst_i, clk_i)
begin
-- the arbiter requires a defined initial state
if (rst_i = '0') then
state <= RESET; -- this is crucial!
elsif rising_edge(clk_i) then
state <= state_nxt;
end if;
end process arbiter_sync0;
arbiter_sync1: process(clk_i)
begin
if rising_edge(clk_i) then
-- these signals do not need a specific reset state
ctrl <= ctrl_nxt;
src <= src_nxt;
mem_rd_ff <= mem_rd;
am <= am_nxt;
sam <= sam_nxt;
if (ir_wren = '1') then
ir <= instr_i; -- instruction register
end if;
end if;
end process arbiter_sync1;
-- control bus output --
ctrl_o <= ctrl;
-- someone using the DADD instruction? --
dadd_sanity_check: process(ir)
begin
if (ir(15 downto 12) = "1010") then -- DADD
assert false report "DADD instruction not supported!" severity warning;
end if;
end process dadd_sanity_check;
-- Arbiter State Machine Comb -----------------------------------------------
-- -----------------------------------------------------------------------------
arbiter_comb: process(state, instr_i, ir, ctrl, branch_taken, src, am, sam, mem_rd_ff, irq_start, sreg_i)
variable spec_cmd_v, valid_wb_v, move_cmd_v : std_ulogic;
begin
-- NOTES --
-- Signals in states/sub states marked with a "-->" are moved out of case statement and are set as pseudo default.
-- The general assigning of this signal does not effect states, which actually do not require this signal.
-- However, this saves some mux logic in the states.
-- arbiter defaults --
state_nxt <= state;
src_nxt <= src; -- source reg
am_nxt <= am; -- total addressing mode [OP class I/II, src_addr_mode(1), src_addr_mode(0), dst_addr_mode]
sam_nxt <= sam; -- default source addressing mode
ir_wren <= '0'; -- write to instruction register
mem_rd <= '0'; -- normal ("slow") memory read
irq_ack <= '0'; -- ack irq to irq-controller
-- control defaults --
ctrl_nxt <= (others => '0'); -- all off
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source reg A
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c); -- keep ALU function
ctrl_nxt(ctrl_rf_as1_c downto ctrl_rf_as0_c) <= sam; -- default SRC addressing mode
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2 as address offset
ctrl_nxt(ctrl_mem_rd_c) <= mem_rd_ff; -- delayed memory read
ctrl_nxt(ctrl_alu_bw_c) <= ctrl(ctrl_alu_bw_c); -- keep byte/word mode
-- special single ALU operation? --
spec_cmd_v := '0';
if (ir(15 downto 9) = "0001001") then -- CALL or PUSH or RETI
spec_cmd_v := '1';
end if;
-- is MOV operation? --
move_cmd_v := '0';
-- use ctrl's signals here, since MOV operation can be set by IR and by the FSM itself
if (ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) = alu_mov_c) then
move_cmd_v := '1';
end if;
-- valid write back? --
valid_wb_v := '1';
if (ir(15 downto 12) = alu_cmp_c) or (ir(15 downto 12) = alu_bit_c) then
valid_wb_v := '0'; -- CMP and BIT instructions only write status flags
end if;
-- state machine --
case state is
when RESET => -- init PC with boot address
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_boot_c) <= '1'; -- load boot address
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
state_nxt <= IFETCH_0;
when IFETCH_0 => -- output and update PC & IRQ check (stay here for SLEEP)
-- ------------------------------------------------------------
sam_nxt <= "00"; -- SRC address mode = REG, required for all special operations + IRQ
ctrl_nxt(ctrl_alu_bw_c) <= '0'; -- word mode, also required for all IRQ states
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output PC/IRQ vector
if (irq_start = '1') then -- execute IRQ
state_nxt <= IRQ_0;
elsif (sreg_i(sreg_s_c) = '0') then -- no sleep mode = normal execution
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= IFETCH_1;
end if;
when IFETCH_1 => -- wait for memory
-- ------------------------------------------------------------
state_nxt <= DECODE;
when DECODE => -- decode applied instruction & store it to IR
-- ------------------------------------------------------------
ir_wren <= '1'; -- update instruction register
ctrl_nxt(ctrl_alu_bw_c) <= instr_i(6); -- byte/word mode
sam_nxt <= instr_i(5 downto 4);
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC (used by branch instructions only)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "000"; -- add immediate offset (used by branch instructions only)
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback (used by branch instructions only)
if (instr_i(15 downto 14) = "00") then -- branch or format II instruction
if (instr_i(13) = '1') then -- BRANCH INSTRUCTION
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_wb_en_c) <= branch_taken; -- valid RF write back if branch taken
state_nxt <= IFETCH_0;
elsif (instr_i(12 downto 10) = "100") then -- FORMAT II INSTRUCTION
-- ------------------------------------------------------------
am_nxt(0) <= instr_i(4) or instr_i(5); -- dst addressing mode
am_nxt(3) <= '0'; -- class II
if (instr_i(3 downto 0) = reg_cg_c) or ((instr_i(3 downto 0) = reg_sr_c) and (instr_i(5) = '1')) then -- source special?
am_nxt(2 downto 1) <= "00"; -- source addressing mode
else
am_nxt(2 downto 1) <= instr_i(5 downto 4); -- source addressing mode
end if;
src_nxt <= instr_i(3 downto 0); -- src is also dst
if (instr_i(15 downto 9) /= "0001001") then -- not PUSH/CALL/RETI?
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= "00" & instr_i(8 downto 7); -- ALU function (rrc/swpb/rra/sxt)
else
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= alu_mov_c; -- to move OpA -> RF/MEM
end if;
case instr_i(9 downto 7) is
when "100" => state_nxt <= TRANS_0; -- PUSH (via single ALU OP)
when "101" => state_nxt <= TRANS_0; -- CALL (via single ALU OP)
when "110" => state_nxt <= RETI_0; -- RETI
when "111" => state_nxt <= IFETCH_0; -- !!!UNDEFINED OPCODE!!!
when others => state_nxt <= TRANS_0; -- single ALU OP (FORMAT II)
end case;
else -- !!!UNDEFINED OPCODE!!!
-- ------------------------------------------------------------
state_nxt <= IFETCH_0;
end if;
else -- FORMAT I INSTRUCTION
-- ------------------------------------------------------------
am_nxt(3) <= '1'; -- class I
if (instr_i(11 downto 8) = reg_cg_c) or ((instr_i(11 downto 8) = reg_sr_c) and (instr_i(5) = '1')) then -- source special?
am_nxt(2 downto 1) <= "00"; -- source addressing mode for r2 & r3
else
am_nxt(2 downto 1) <= instr_i(5 downto 4); -- source addressing mode
end if;
am_nxt(0) <= instr_i(7); -- dst addressing mode
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= instr_i(15 downto 12); -- ALU function
src_nxt <= instr_i(11 downto 8);
if (instr_i(15 downto 12) = "1010") then -- !!!INVALID ALUOP!!!
state_nxt <= IFETCH_0;
else
state_nxt <= TRANS_0;
end if;
end if;
when TRANS_0 => -- operand transfer cycle 0
-- ------------------------------------------------------------
-- (pseudo) defaults
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback (only relevant for when 2,3,5)
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_adr_mar_wr_c) <= am(0); -- write to MAR [relevant for memory writeback when using CLASS II operations]
--
case am is -- addressing mode
when "0001" | "0000" | "1000" =>
-- "0001" = CLASS II, SRC: Reg, DST: Indexed
-- "0000" = CLASS II, SRC/DST: register direct
-- "1000" = CLASS I, SRC/DST: Reg
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write OpA
if (spec_cmd_v = '1') then -- push or call
state_nxt <= PUSHCALL_0;
elsif (am(3) = '0') then -- CLASS II operation
state_nxt <= TRANS_6;
else
state_nxt <= TRANS_3;
end if;
when "1001" | "1010" | "0010" | "0011" =>
-- "1001" = CLASS I, SRC: register direct, DST: indexed
--
-- "1010" = CLASS I, SRC: indexed/symbolic/absolute, DST: register direct
-- "001-" = CLASS II, SRC: indexed/symbolic/absolute, DST: indexed/symbolic/absolute OR register direct
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
--> ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
--> ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
if (am(2 downto 1) = "00") then -- "1001" = CLASS I, SRC: register direct, DST: indexed
state_nxt <= TRANS_3;
else
state_nxt <= TRANS_2;
end if;
when "1011" =>
-- "1011" = CLASS I, SRC: indexed/symbolic/absolute, DST: indexed
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
--> ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= TRANS_1;
when "0100" | "0101" | "1100" | "1101" =>
-- "010-" = CLASS II, SRC/DST: indirect
-- "1100" = CLASS I, SRC: indirect, DST: register direct
-- "1101" = CLASS I, SRC: indirect, DST: indexed
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A
--> cctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
state_nxt <= TRANS_1;
when others =>
-- "011-" = CLASS II, SRC/DST: indirect auto inc
-- "1110" = CLASS I, SRC: indirect auto inc, DST: register direct
-- "1111" = CLASS I, SRC: indirect auto inc, DST: indexed
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A
--> cctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
if (ir(6) = '0') or (src = reg_pc_c) then -- word mode (force if accessing PC)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
else -- byte mode
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "001"; -- add +1
end if;
--> ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= TRANS_1;
end case;
when TRANS_1 => -- operand transfer cycle 1
-- ------------------------------------------------------------
-- (pseudo) defaults
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback (only relevant for last two 'when')
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
--
case am is -- addressing mode
-- "000-" = CLASS II, SRC/DST: register direct [ACTUAL DON'T CARE; STATE NOT USED]
-- "1000" = CLASS I, SRC: register direct, DST: register direct [ACTUAL DON'T CARE; STATE NOT USED]
-- "1001" = CLASS I, SRC: register direct, DST: indexed [ACTUAL DON'T CARE; STATE NOT USED]
-- ==> DONT CARE
-- "001-" = CLASS II, SRC/DST: indexed/symbolic/absolute [ACTUAL DON'T CARE; STATE NOT USED]
-- "1010" = CLASS I, SRC: indexed/symbolic/absolute, DST: register direct [ACTUAL DON'T CARE; STATE NOT USED]
-- ==> DONT CARE
when "0100" | "0101" | "1100" | "0110" | "0111" | "1110" =>
-- "010-" = CLASS II, SRC/DST: indirect
-- "1100" = CLASS I, SRC: indirect, DST: register direct
--
-- "011-" = CLASS II, SRC/DST: indirect auto inc,
-- "1110" = CLASS I, SRC: indirect auto inc, DST: register direct
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write OpA
if (spec_cmd_v = '1') then -- push or call
state_nxt <= PUSHCALL_0;
else
if (am(3) = '0') then -- CLASS II
state_nxt <= TRANS_6;
else -- CLASS I
state_nxt <= TRANS_3;
end if;
end if;
when "1101" | "1111" =>
-- "1101" = CLASS I, SRC: indirect, DST: indexed
--
-- "1111" = CLASS I, SRC: indirect auto inc, DST: indexed
--> ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
--> ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
--> ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write OpA
state_nxt <= TRANS_3; -- no PUSHCALL check required
when others =>
-- "1011" = CLASS I, SRC: indexed/symbolic/absolute, DST: indexed
--> ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
--> ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
--> ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= TRANS_2;
end case;
when TRANS_2 => -- operand transfer cycle 2
-- ------------------------------------------------------------
-- "001-" = CLASS II: SRC/DST: indexed/symbolic/absolute
-- "1010" = CLASS I, SRC: indexed/symbolic/absolute, DST: register direct
-- "1011" = CLASS I, SRC: indexed/symbolic/absolute, DST: indexed
-- OTHERS = DONT CARE [state not reachable]
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "1--"; -- add memory data in (only relevant for first 'when')
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "1--"; -- add memory data in
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
mem_rd <= '1'; -- Memory read
state_nxt <= TRANS_3;
when TRANS_3 => -- operand transfer cycle 3
-- ------------------------------------------------------------
-- (pseudo) defaults
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= ir(3 downto 0); -- source: reg B
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "1--"; -- add memory data in
--
case am is -- addressing mode
when "1001" | "1011" | "1101" | "1111" =>
-- "1001" = CLASS I, SRC: register direct, DST: indexed
-- "1011" = CLASS I, SRC: indexed/symbolic/absolute, DST: indexed
-- "1101" = CLASS I, SRC: indirect, DST: indexed
-- "1111" = CLASS I, SRC: indirect auto inc, DST: indexed
ctrl_nxt(ctrl_rf_as1_c) <= '0'; -- DST address mode = REG or INDEXED
ctrl_nxt(ctrl_rf_as0_c) <= ir(7); -- DST address mode = REG or INDEXED
--> ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "1--"; -- add memory data in
--> ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
if (ctrl(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) /= alu_mov_c) then -- no read for MOV
mem_rd <= '1'; -- Memory read
end if;
state_nxt <= TRANS_4;
when others =>
ctrl_nxt(ctrl_rf_as1_c downto ctrl_rf_as0_c) <= "00"; -- DST address mode = REG
ctrl_nxt(ctrl_alu_opb_wr_c) <= '1'; -- write OpB
if (am(2 downto 1) = "01") then
state_nxt <= TRANS_4;
else
state_nxt <= TRANS_6;
end if;
end case;
when TRANS_4 => -- operand transfer cycle 4
-- ------------------------------------------------------------
-- (pseudo) defaults
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= src; -- source: reg A (only relevant for 3rd 'when')
--
case am is -- addressing mode
when "0010" | "0011" | "1010" | "1011" =>
-- "001-" = CLASS II, SRC/DST: indexed/symbolic/absolute
-- "1010" = CLASS I, SRC: indexed/symbolic/absolute, DST: register direct
-- "1011" = CLASS I, SRC: indexed/symbolic/absolute, DST: indexed
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write to OpA
if (spec_cmd_v = '1') then -- push or call
state_nxt <= PUSHCALL_0;
elsif ((am(3) and am(0)) = '1') and (move_cmd_v = '0') then -- skip processing of second operand when executing MOV instruction
state_nxt <= TRANS_5;
else
state_nxt <= TRANS_6;
end if;
when "1001" =>
-- "1001" = CLASS I, SRC: register direct, DST: indexed
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write OpA
if (move_cmd_v = '1') then -- skip processing of second operand when executing MOV instruction
state_nxt <= TRANS_6;
else
state_nxt <= TRANS_5;
end if;
when others => -- NOP / DONT CARE
-- "000-" = CLASS II, SRD/DST: DONT CARE
-- "1000" = CLASS I, SRC: register direct, DST: register direct = DONT CARE
-- "-10-" : NOP
-- "-11-" : NOP
if (move_cmd_v = '1') then -- skip processing of second operand when executing MOV instruction
state_nxt <= TRANS_6;
else
state_nxt <= TRANS_5;
end if;
end case;
when TRANS_5 => -- operand transfer cycle 5
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opb_wr_c) <= '1'; -- write to OpB
state_nxt <= TRANS_6;
when TRANS_6 => -- operand transfer cycle 6: RF or MEM write-back
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= ir(3 downto 0); -- destination
ctrl_nxt(ctrl_rf_fup_c) <= not spec_cmd_v; -- update ALU status flags
if (am(0) = '0') then -- DST: register direct (register file)
ctrl_nxt(ctrl_rf_wb_en_c) <= valid_wb_v; -- valid RF write back (not for CMP/BIT!)
else -- DST: indexed (memory)
ctrl_nxt(ctrl_mem_wr_c) <= valid_wb_v; -- valid MEM write back (not for CMP/BIT!)
end if;
state_nxt <= IFETCH_0; -- done!
when PUSHCALL_0 => -- PUSH/CALL cycle 0 (stack update)
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= alu_mov_c; -- keep this for all following states
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "011"; -- add -2
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
if (ir(7) = '1') then -- CALL
state_nxt <= PUSHCALL_1;
else -- PUSH
state_nxt <= PUSHCALL_2;
end if;
when PUSHCALL_1 => -- CALL cycle 1 (buffer PC so it can be written to memory)
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source/destination: PC
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write to OpA
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= PUSHCALL_2;
when PUSHCALL_2 => -- PUSH/CALL cycle 2 (write data to memory)
-- ------------------------------------------------------------
ctrl_nxt(ctrl_mem_wr_c) <= '1'; -- memory write request
state_nxt <= IFETCH_0; -- done!
when RETI_0 => -- RETI cycle 0: Output address of old SR; SP=SP+2
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= alu_mov_c; -- keep this for all following states
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= RETI_1;
when RETI_1 => -- RETI cycle 1: Buffer status register from MEM in OpA; Output address of old PC; SP=SP+2
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output RF.out to address bus
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "010"; -- add +2
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write to OpA
state_nxt <= RETI_2;
when RETI_2 => -- RETI cycle 4: Write status register; buffer return address from MEM in OpA
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write to OpA
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sr_c; -- destination: SR
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= RETI_3;
when RETI_3 => -- RETI cycle 5: Write return address to PC
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- destination: PC
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= IFETCH_0; -- done!
when IRQ_0 => -- IRQ processing cycle 0: SP=SP-2, disable sleep mode
-- ------------------------------------------------------------
ctrl_nxt(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) <= alu_mov_c; -- keep this for all following states
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "011"; -- add -2
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
ctrl_nxt(ctrl_rf_dsleep_c) <= '1'; -- disable sleep mode
state_nxt <= IRQ_1;
when IRQ_1 => -- IRQ processing cycle 1: Buffer PC for memory write
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- source: PC
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write PC to OpA
state_nxt <= IRQ_2;
when IRQ_2 => -- IRQ processing cycle 2: Write PC to memory (push), SP=SP-2
-- ------------------------------------------------------------
ctrl_nxt(ctrl_mem_wr_c) <= '1'; -- write memory request (store PC)
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sp_c; -- source/destination: SP
ctrl_nxt(ctrl_adr_mar_wr_c) <= '1'; -- write to MAR
ctrl_nxt(ctrl_adr_off2_c downto ctrl_adr_off0_c) <= "011"; -- add -2
ctrl_nxt(ctrl_adr_mar_sel_c) <= '1'; -- use result from adder
ctrl_nxt(ctrl_rf_in_sel_c) <= '1'; -- select addr gen feedback
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= IRQ_3;
when IRQ_3 => -- IRQ processing cycle 3: Buffer SR for memory write, set IRQ vector address, disable interrupt enable flag in SR
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_sr_c; -- source: SR
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write SR to OpA
ctrl_nxt(ctrl_adr_bp_en_c) <= '1'; -- directly output PC/IRQ vector
ctrl_nxt(ctrl_adr_ivec_oe_c) <= '1'; -- output IRQ vector
ctrl_nxt(ctrl_mem_rd_c) <= '1'; -- Memory read (fast)
ctrl_nxt(ctrl_rf_dgie_c) <= '1'; -- disable interrupt enable flag
irq_ack <= '1'; -- acknowledge started IRQ handler
state_nxt <= IRQ_4;
when IRQ_4 => -- IRQ processing cycle 4: Write SR (push), get IRQ vector
-- ------------------------------------------------------------
ctrl_nxt(ctrl_mem_wr_c) <= '1'; -- write memory request
ctrl_nxt(ctrl_alu_in_sel_c) <= '1'; -- get data from memory
ctrl_nxt(ctrl_alu_opa_wr_c) <= '1'; -- write to OpA
state_nxt <= IRQ_5;
when IRQ_5 => -- IRQ processing cycle 5: Store IRQ vector to PC
-- ------------------------------------------------------------
ctrl_nxt(ctrl_rf_adr3_c downto ctrl_rf_adr0_c) <= reg_pc_c; -- destination: PC
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write back
state_nxt <= IFETCH_0; -- done!
when others => -- invalid
-- ------------------------------------------------------------
state_nxt <= RESET;
end case;
end process arbiter_comb;
-- Interrupt Controller -----------------------------------------------------
-- -----------------------------------------------------------------------------
irq_buffer: process(clk_i)
begin
if rising_edge(clk_i) then
-- delay I flag 2 cycles to allow the interrupted program to execute at least one insruction even if we have
-- a permanent interrupt request
i_flag_ff0 <= sreg_i(sreg_i_c);
i_flag_ff1 <= i_flag_ff0;
-- interrupt vector and queue buffer --
for i in 0 to 3 loop
irq_buf(i) <= (irq_buf(i) or irq_i(i)) and (not sreg_i(sreg_q_c)) and (not irq_ack_mask(i));
end loop; -- i
-- interrupt control --
if (irq_start = '0') or (sreg_i(sreg_i_c) = '0') then -- idle or IRQs disabled
irq_start <= '0';
if (irq_fire = '1') then -- IRQ triggered
irq_vec <= irq_vec_nxt; -- capture source
irq_start <= '1';
end if;
else -- active IRQ
if (irq_ack = '1') then -- handler started?
irq_start <= '0';
end if;
end if;
end if;
end process irq_buffer;
-- valid start of IRQ handler --
irq_fire <= '1' when (irq_buf /= "0000") and (i_flag_ff1 = '1') and (sreg_i(sreg_i_c) = '1') else '0';
-- acknowledge mask --
irq_ack_mask_gen: process(irq_ack, irq_vec)
variable irq_tmp_v : std_ulogic_vector(2 downto 0);
begin
irq_tmp_v := irq_ack & irq_vec;
case irq_tmp_v is
when "100" => irq_ack_mask <= "0001";
when "101" => irq_ack_mask <= "0010";
when "110" => irq_ack_mask <= "0100";
when "111" => irq_ack_mask <= "1000";
when others => irq_ack_mask <= "0000";
end case;
end process;
-- interrupt priority encoder --
irq_priority: process(irq_buf)
begin
-- use "case" here to avoid a MUX chain
case irq_buf is
when "0001" | "0011" | "0101" | "0111" | "1001" | "1011" | "1101" | "1111" => -- "---1"
irq_vec_nxt <= "00";
when "0010" | "0110" | "1010" | "1110" => -- "--10"
irq_vec_nxt <= "01";
when "0100" | "1100" => -- "-100"
irq_vec_nxt <= "10";
when others => -- "1000" ("0000" -> dont't care)
irq_vec_nxt <= "11";
end case;
end process irq_priority;
-- interrupt vector output --
irq_vec_o <= irq_vec; -- the final address is constructed in the address generator
end neo430_control_rtl;
|
bsd-3-clause
|
b896bf479351938d70083a4bf45ec895
| 0.501002 | 3.609751 | false | false | false | false |
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