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herenvarno/dlx
|
dlx_vhd/src/0-Consts.vhd
| 1 | 11,250 |
--------------------------------------------------------------------------------
-- FILE: Consts
-- DESC: Define all constants.
--
-- Author:
-- Create: 2015-05-20
-- Update: 2015-09-20
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package Consts is
constant C_SYS_DATA_SIZE : integer := 32; -- Data size
constant C_SYS_ISTR_SIZE : integer := 32; -- Instruction size
constant C_SYS_ADDR_SIZE : integer := 32; -- Address size
constant C_SYS_CWRD_SIZE : integer := 20; -- Control Word size
constant C_SYS_OPCD_SIZE : integer := 6; -- Operation code size
constant C_SYS_FUNC_SIZE : integer := 11; -- Function code size
constant C_SYS_IMME_SIZE : integer := 16; -- Immediate value size
constant C_CTR_CALU_SIZE : integer := 5; -- ALU Operation Code size
constant C_CTR_DRCW_SIZE : integer := 4; -- Data Memory Control word size
constant C_ADD_SPARSITY : integer := 4; -- Sparsity of Adder carray generator
constant C_MUL_STAGE : integer := 10; -- Stage of multiply operation
constant C_DIV_STAGE : integer := 34; -- Stage of division operation
constant C_SQRT_STAGE : integer := 18; -- Stage of square root operation
constant C_REG_NUM : integer := 32; -- Number of Register in Register File
constant C_REG_GLOBAL_NUM : integer := 8; -- Number of Global register in register file
constant C_REG_GENERAL_NUM : integer := 8; -- Number of General registers (I/L/O) in register file
constant C_REG_WINDOW_NUM : integer := 8; -- Number of Windows in register file
constant C_RAM_IRAM_SIZE : integer := 10240; -- IRAM size
constant C_RAM_DRAM_SIZE : integer := 1024; -- DRAM size
constant C_BPU_ADDR_SIZE : integer := 5; -- BPU ADDR SIZE
-- ALU Operations
constant OP_ADD : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00000"; --0x00
constant OP_AND : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00001"; --0x01
constant OP_OR : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00010"; --0x02
constant OP_XOR : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00011"; --0x03
constant OP_SLL : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00100"; --0x04
constant OP_SRL : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00101"; --0x05
constant OP_SRA : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00111"; --0x07
constant OP_MULTU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "01000"; --0x08 -- unsigned
constant OP_MULT : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "01001"; --0x09 -- signed
constant OP_DIVU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "01010"; --0x0a -- unsigned
constant OP_DIV : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "01011"; --0x0b -- signed
constant OP_SQRT : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "01100"; --0x0c -- SQRT unsigned
constant OP_SUB : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10000"; --0x10
constant OP_SGT : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10001"; --0x11
constant OP_SGE : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10010"; --0x12
constant OP_SLT : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10011"; --0x13
constant OP_SLE : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10100"; --0x14
constant OP_SGTU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10101"; --0x15
constant OP_SGEU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10110"; --0x16
constant OP_SLTU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10111"; --0x17
constant OP_SLEU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "11000"; --0x18
constant OP_SEQ : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "11001"; --0x19
constant OP_SNE : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "11010"; --0x1a
-- Control Word
constant CW_S1_LATCH : integer := 0;
constant CW_S2_JUMP : integer := 1; -- JUMP HAPPENS ?
constant CW_S2_SEL_JA_0 : integer := 2; -- ADDR0 = NPC + EXT_I or ADDR = NPC + EXT_J ?
constant CW_S2_SEL_JA_1 : integer := 3; -- ADDR1 = ADDR0 or ADD1 = REG_A ?
constant CW_S2_LINK : integer := 4;
constant CW_S2_EXT_S : integer := 5;
constant CW_S2_LATCH : integer := 6;
constant CW_S3_SEL_B : integer := 7;
constant CW_S3_LD_FLAG : integer := 8;
constant CW_S3_WB_FLAG : integer := 9;
constant CW_S3_LATCH : integer := 10;
constant CW_S4_DRAM_T_0 : integer := 11;
constant CW_S4_DRAM_T_1 : integer := 12;
constant CW_S4_DRAM_T_2 : integer := 13;
constant CW_S4_DRAM_WR : integer := 14;
constant CW_S4_SEL_WB : integer := 15;
constant CW_S4_LD_FLAG : integer := 16;
constant CW_S4_WB_FLAG : integer := 17;
constant CW_S4_LATCH : integer := 18;
constant CW_S5_EN_WB : integer := 19;
-- Instructions -- OpCode
constant OPCD_R : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000000"; --0x00
constant OPCD_F : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000001"; --0x01
constant OPCD_J : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000010"; --0x02
constant OPCD_JAL : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000011"; --0x03
constant OPCD_BEQZ : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000100"; --0x04
constant OPCD_BNEZ : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000101"; --0x05
constant OPCD_ADDI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001000"; --0x08
constant OPCD_ADDUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001001"; --0x09
constant OPCD_SUBI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001010"; --0x0a
constant OPCD_SUBUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001011"; --0x0b
constant OPCD_ANDI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001100"; --0x0c
constant OPCD_ORI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001101"; --0x0d
constant OPCD_XORI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001110"; --0x0e
constant OPCD_LHI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001111"; --0x0f
constant OPCD_JR : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010010"; --0x12
constant OPCD_JALR : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010011"; --0x13
constant OPCD_SLLI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010100"; --0x14
constant OPCD_NOP : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010101"; --0x15
constant OPCD_SRLI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010110"; --0x16
constant OPCD_SRAI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010111"; --0x17
constant OPCD_SEQI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011000"; --0x18
constant OPCD_SNEI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011001"; --0x19
constant OPCD_SLTI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011010"; --0x1a
constant OPCD_SGTI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011011"; --0x1b
constant OPCD_SLEI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011100"; --0x1c
constant OPCD_SGEI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011101"; --0x1d
constant OPCD_LB : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "100000"; --0x20
constant OPCD_LH : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "100001"; --0x21
constant OPCD_LW : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "100011"; --0x23
constant OPCD_LBU : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "100100"; --0x24
constant OPCD_LHU : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "100101"; --0x25
constant OPCD_SB : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "101000"; --0x28
constant OPCD_SH : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "101001"; --0x29
constant OPCD_SW : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "101011"; --0x2b
constant OPCD_SLTUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "111010"; --0x3a
constant OPCD_SGTUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "111011"; --0x3b
constant OPCD_SLEUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "111100"; --0x3c
constant OPCD_SGEUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "111101"; --0x3d
-- Instructions --FUNC
-- R TYPE
constant FUNC_SLL : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000000100"; --0x04
constant FUNC_SRL : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000000110"; --0x06
constant FUNC_SRA : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000000111"; --0x07
constant FUNC_ADD : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100000"; --0x20
constant FUNC_ADDU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100001"; --0x21
constant FUNC_SUB : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100010"; --0x22
constant FUNC_SUBU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100011"; --0x23
constant FUNC_AND : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100100"; --0x24
constant FUNC_OR : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100101"; --0x25
constant FUNC_XOR : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100110"; --0x26
constant FUNC_SEQ : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101000"; --0x28
constant FUNC_SNE : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101001"; --0x29
constant FUNC_SLT : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101010"; --0x2a
constant FUNC_SGT : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101011"; --0x2b
constant FUNC_SLE : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101100"; --0x2c
constant FUNC_SGE : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101101"; --0x2d
constant FUNC_SLTU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000111010"; --0x3a
constant FUNC_SGTU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000111011"; --0x3b
constant FUNC_SLEU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000111100"; --0x3c
constant FUNC_SGEU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000111101"; --0x3d
-- F TYPE
constant FUNC_MULT : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000001110"; --0x0e
constant FUNC_DIV : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000001111"; --0x0f
constant FUNC_MULTU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000010110"; --0x16
constant FUNC_DIVU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000010111"; --0x17
constant FUNC_SQRT : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100000"; --0x20
-- STALL GENERATOR STATES
constant SG_ST0 : integer := 0;
constant SG_ST1 : integer := 1;
constant SG_ST2 : integer := 2;
constant SG_ST3 : integer := 3;
constant SG_ST4 : integer := 4;
constant SG_ST5 : integer := 5;
constant SG_ST6 : integer := 6;
constant SG_ST7 : integer := 7;
constant SG_ST8 : integer := 8;
constant SG_ST9 : integer := 9;
constant SG_ST10 : integer := 10;
constant SG_ST11 : integer := 11;
constant SG_ST12 : integer := 12;
constant SG_ST13 : integer := 13;
constant SG_ST14 : integer := 14;
constant SG_ST15 : integer := 15;
constant SG_ST16 : integer := 16;
constant SG_ST17 : integer := 17;
constant SG_ST18 : integer := 18;
constant SG_ST19 : integer := 19;
constant SG_ST20 : integer := 20;
constant SG_ST21 : integer := 21;
constant SG_ST22 : integer := 22;
constant SG_ST23 : integer := 23;
end package Consts;
|
mit
|
4eda99d3bd34d289ec92517cc7f65531
| 0.668089 | 2.559727 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/limit_checker.vhd
| 4 | 2,533 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
package project_util is
-- code from book (in text)
function "<" ( bv1, bv2 : bit_vector ) return boolean;
subtype word is std_logic_vector(31 downto 0);
-- end code from book
end package project_util;
package body project_util is
function "<" ( bv1, bv2 : bit_vector ) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "vectors are of different length in ""<"" comparison"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return std.standard."<" ( tmp1, tmp2 );
end function "<";
end package body project_util;
-- code from book
library ieee; use ieee.std_logic_1164.all;
use work.project_util.all;
entity limit_checker is
port ( input, lower_bound, upper_bound : in word;
out_of_bounds : out std_logic );
end entity limit_checker;
--------------------------------------------------
architecture behavioral of limit_checker is
subtype bv_word is bit_vector(31 downto 0);
function word_to_bitvector ( w : in word ) return bv_word is
begin
return To_bitvector ( w, xmap => '0' );
end function word_to_bitvector;
begin
algorithm : process (input, lower_bound, upper_bound) is
begin
if "<" ( bv1 => word_to_bitvector(input),
bv2 => word_to_bitvector(lower_bound) )
or "<" ( bv1 => word_to_bitvector(upper_bound),
bv2 => word_to_bitvector(input) ) then
out_of_bounds <= '1';
else
out_of_bounds <= '0';
end if;
end process algorithm;
end architecture behavioral;
-- end code from book
|
gpl-2.0
|
0bb6638776c10dc299e8305fab7968d0
| 0.666403 | 3.671014 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc448.vhd
| 4 | 3,238 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc448.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00448ent IS
END c03s02b01x01p19n01i00448ent;
ARCHITECTURE c03s02b01x01p19n01i00448arch OF c03s02b01x01p19n01i00448ent IS
type positive_vector is array (natural range <>) of positive;
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : positive := 4;
constant C70 : positive_vector_st :=(others => C1);
function complex_scalar(s : positive_vector_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return positive_vector_st is
begin
return C70;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : positive_vector_st;
signal S2 : positive_vector_st;
signal S3 : positive_vector_st := C70;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C70) and (S2 = C70))
report "***PASSED TEST: c03s02b01x01p19n01i00448"
severity NOTE;
assert ((S1 = C70) and (S2 = C70))
report "***FAILED TEST: c03s02b01x01p19n01i00448 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00448arch;
|
gpl-2.0
|
bb810f3720f789da37c78f122c304ee0
| 0.656578 | 3.658757 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-src.vhd
| 4 | 1,904 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-src.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
use qsim.qsim_types.all;
use random.random.all;
architecture source of test_bench is
signal a : arc_type;
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(0),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => a,
info_detail => info_detail );
monitor : process is
variable L : line;
begin
wait on a;
write(L, string'("monitor: at "));
write(L, now, unit => ns);
write(L, string'(" received "));
write(L, a.token, ns);
writeline(output, L);
end process monitor;
end architecture source;
|
gpl-2.0
|
f129c32ec112828b620cfa75cce52a7b
| 0.598739 | 4.033898 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_20.vhd
| 3 | 2,194 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_20.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- code from book
library ieee;
use ieee.std_logic_1164.all;
entity reg_ctrl is
port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
reg_rd, reg_wr : out std_ulogic );
end entity reg_ctrl;
architecture bool_eqn of reg_ctrl is
begin
rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
and not cpu_clk;
end architecture bool_eqn;
-- end code from book
entity fg_07_20 is
end entity fg_07_20;
library ieee;
use ieee.std_logic_1164.all;
library stimulus;
architecture test of fg_07_20 is
signal reg_addr_decoded, rd, wr, io_en,
cpu_clk, reg_rd, reg_wr : std_ulogic := '0';
signal test_vector : std_ulogic_vector(1 to 5);
use stimulus.stimulus_generators.all;
begin
dut : entity work.reg_ctrl
port map ( reg_addr_decoded, rd, wr, io_en, cpu_clk, reg_rd, reg_wr );
stimulus_proc : process is
begin
all_possible_values( bv => test_vector,
delay_between_values => 10 ns );
wait;
end process stimulus_proc;
(reg_addr_decoded, rd, wr, io_en, cpu_clk) <= test_vector;
end architecture test;
|
gpl-2.0
|
ea0f2b0013880ef9472afb09839cdc21
| 0.634458 | 3.527331 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_09.vhd
| 4 | 1,667 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_09 is
end entity inline_09;
----------------------------------------------------------------
architecture test of inline_09 is
begin
process_2_d : process is
-- code from book:
variable N : integer := 1;
--
constant C : integer := 1;
-- end of code from book
constant expression : integer := 7;
begin
-- code from book:
-- error: Case choice must be a locally static expression
-- case expression is -- example of an illegal case statement
-- when N | N+1 => -- . . .
-- when N+2 to N+5 => -- . . .
-- when others => -- . . .
-- end case;
--
case expression is
when C | C+1 => -- . . .
when C+2 to C+5 => -- . . .
when others => -- . . .
end case;
-- end of code from book
wait;
end process process_2_d;
end architecture test;
|
gpl-2.0
|
8921bf531f606b9454a5541c560ed505
| 0.609478 | 4.075795 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/Modular/celda_A.vhd
| 1 | 1,862 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_A is
generic(
NUM_BITS : positive := 163
);
port(
A : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
B : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c0 : in STD_LOGIC;
c1 : in STD_LOGIC;
c3 : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
toA : out STD_LOGIC_VECTOR(NUM_BITS downto 0); -- U = x/y mod Fx,
RegA : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_A is
----------------------------------------------------------------------------------------------------
signal R1,R2 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal A1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal B1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
A1 <= A when c0 = '1' else
(others => '0');
B1 <= B when c1 = '1' else
(others => '0');
R1 <= A1 xor B1;
R2 <= '0'&R1(NUM_BITS downto 1);
toA <= R2;
celda_A_process: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
RegA <= (others => '0');
else
if c3 = '1' then
RegA <= R2;
end if;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
96cb69795c06ee0fac6387fb1dba38ca
| 0.381847 | 3.936575 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket89/project/src93/adaptations_pkg.vhd
| 3 | 10,518 |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : adaptations_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.standard_textio_additions.all;
use work.types_pkg.all;
package adaptations_pkg is
constant C_ALERT_FILE_NAME : string := "_Alert.txt";
constant C_LOG_FILE_NAME : string := "_Log.txt";
constant C_SHOW_BITVIS_UTILITY_LIBRARY_INFO : boolean := true; -- Set this to false when you no longer need the initial info
constant C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO : boolean := true; -- Set this to false when you no longer need the release info
-------------------------------------------------------------------------------
-- Log format
-------------------------------------------------------------------------------
--Bitvis: [<ID>] <time> <Scope> Msg
--PPPPPPPPIIIIII TTTTTTTT SSSSSSSSSSSSSS MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM
constant C_LOG_PREFIX : string := "Bitvis: "; -- Note: ': ' is recommended as final characters
constant C_LOG_PREFIX_WIDTH : natural := C_LOG_PREFIX'length;
constant C_LOG_MSG_ID_WIDTH : natural := 20;
constant C_LOG_TIME_WIDTH : natural := 16; -- 3 chars used for unit eg. " ns"
constant C_LOG_TIME_BASE : time := ns; -- Unit in which time is shown in log (ns | ps)
constant C_LOG_TIME_DECIMALS : natural := 1; -- Decimals to show for given C_LOG_TIME_BASE
constant C_LOG_SCOPE_WIDTH : natural := 16;
constant C_LOG_LINE_WIDTH : natural := 150;
constant C_LOG_INFO_WIDTH : natural := C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH;
constant C_USE_BACKSLASH_N_AS_LF : boolean := true; -- If true interprets '\n' as Line feed
constant C_SINGLE_LINE_ALERT : boolean := false; -- If true prints alerts on a single line.
constant C_SINGLE_LINE_LOG : boolean := false; -- If true prints log messages on a single line.
constant C_TB_SCOPE_DEFAULT : string := "TB seq."; -- Default scope in test sequencer
constant C_LOG_TIME_TRUNC_WARNING : boolean := true; -- Yields a single TB_WARNING if time stamp truncated. Otherwise none
signal global_show_log_id : boolean := true;
signal global_show_log_scope : boolean := true;
-- UVVM dedicated. May be moved to separate UVVM adaptation package
signal global_show_msg_for_uvvm_cmd : boolean := true;
-- End of UVVM dedicated
-------------------------------------------------------------------------------
-- Verbosity control
-- NOTE: Do not enter new IDs without proper evaluation:
-- 1. Is it - or could it be covered by an existing ID
-- 2. Could it be combined with other needs for a more general new ID
-- Feel free to suggest new ID for future versions of Bitvis Utility Library ([email protected])
-------------------------------------------------------------------------------
type t_msg_id is (
-- Bitvis utility methods
NO_ID, -- Used as default prior to setting actual ID when transfering ID as a field in a record
ID_UTIL_BURIED, -- Used for buried log messages where msg and scope cannot be modified from outside
ID_UTIL_SETUP, -- Used for Utility setup
ID_LOG_MSG_CTRL, -- Used inside Utility library only - when enabling/disabling msg IDs.
ID_ALERT_CTRL, -- Used inside Utility library only - when setting IGNORE or REGARD on various alerts.
ID_NEVER, -- Used for avoiding log entry. Cannot be enabled.
ID_CLOCK_GEN, -- Used for logging when clock generators are enabled or disabled
ID_GEN_PULSE, -- Used for logging when a gen_pulse procedure starts pulsing a signal
-- General
ID_POS_ACK, -- To write a positive acknowledge on a check
-- Directly inside test sequencers
ID_LOG_HDR, -- ONLY allowed in test sequencer, Log section headers
ID_LOG_HDR_LARGE, -- ONLY allowed in test sequencer, Large log section headers
ID_LOG_HDR_XL, -- ONLY allowed in test sequencer, Extra large log section headers
ID_SEQUENCER, -- ONLY allowed in test sequencer, Normal log (not log headers)
ID_SEQUENCER_SUB, -- ONLY allowed in test sequencer, Subprograms defined in sequencer
-- BFMs
ID_BFM, -- Used inside a BFM (to log BFM access)
ID_BFM_WAIT, -- Used inside a BFM to indicate that it is waiting for something (e.g. for ready)
-- Packet related data Ids with three levels of granularity, for differentiating between frames, packets and segments.
-- Segment Ids, finest granularity of packet data
ID_SEGMENT_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_SEGMENT_COMPLETE, -- Notify that a packet has been transmitted or received
ID_SEGMENT_HDR, -- AS ID_SEGMENT_COMPLETE, but also writes header info
ID_SEGMENT_DATA, -- AS ID_SEGMENT_COMPLETE, but also writes packet data (could be huge)
-- Packet Ids, medium granularity of packet data
ID_PACKET_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_PACKET_COMPLETE, -- Notify that a packet has been transmitted or received
ID_PACKET_HDR, -- AS ID_PACKET_COMPLETED, but also writes header info
ID_PACKET_DATA, -- AS ID_PACKET_COMPLETED, but also writes packet data (could be huge)
-- Frame Ids, roughest granularity of packet data
ID_FRAME_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_FRAME_COMPLETE, -- Notify that a packet has been transmitted or received
ID_FRAME_HDR, -- AS ID_FRAME_COMPLETE, but also writes header info
ID_FRAME_DATA, -- AS ID_FRAME_COMPLETE, but also writes packet data (could be huge)
-- Distributed command systems
ID_UVVM_SEND_CMD,
ID_UVVM_CMD_ACK,
ID_UVVM_CMD_RESULT,
ID_INTERPRETER, -- Message from VVC interpreter about correctly received and queued/issued command
ID_INTERPRETER_WAIT, -- Message from VVC interpreter that it is actively waiting for a command
ID_IMMEDIATE, -- Message from VVC interpreter that an IMMEDIATE command has been executed
ID_IMMEDIATE_WAIT, -- Message from VVC interpreter that an IMMEDIATE command is waiting for command to complete
ID_EXECUTOR, -- Message from VVC executor about correctly received command - prior to actual execution
ID_EXECUTOR_WAIT, -- Message from VVC executor that it is actively waiting for a command
-- VVC system
ID_VVC_CONSTRUCTOR, -- Constructor message from VVCs
-- Special purpose - Not really IDs
ALL_MESSAGES -- Applies to ALL message ID apart from ID_NEVER
);
type t_msg_id_panel is array (t_msg_id'left to t_msg_id'right) of t_enabled;
constant C_DEFAULT_MSG_ID_PANEL : t_msg_id_panel := (
ID_NEVER => DISABLED,
ID_UTIL_BURIED => DISABLED,
others => ENABLED
);
type t_msg_id_indent is array (t_msg_id'left to t_msg_id'right) of string(1 to 4);
constant C_MSG_ID_INDENT : t_msg_id_indent := (
ID_IMMEDIATE_WAIT => " ..",
ID_INTERPRETER => " " & NUL & NUL,
ID_INTERPRETER_WAIT => " ..",
ID_EXECUTOR => " " & NUL & NUL,
ID_EXECUTOR_WAIT => " ..",
ID_UVVM_SEND_CMD => "->" & NUL & NUL,
ID_UVVM_CMD_ACK => " ",
others => "" & NUL & NUL & NUL & NUL
);
-------------------------------------------------------------------------
-- Alert counters
-------------------------------------------------------------------------
-- Default values. These can be overwritten in each sequencer by using
-- set_alert_attention or set_alert_stop_limit (see quick ref).
constant C_DEFAULT_ALERT_ATTENTION : t_alert_attention := (others => REGARD);
-- 0 = Never stop
constant C_DEFAULT_STOP_LIMIT : t_alert_counters := (note to manual_check => 0,
others => 1);
-------------------------------------------------------------------------
-- Deprecate
-------------------------------------------------------------------------
-- These values are used to indicate outdated sub-programs
constant C_DEPRECATE_SETTING : t_deprecate_setting := DEPRECATE_ONCE;
shared variable deprecated_subprogram_list : t_deprecate_list := (others=>(others => ' '));
end package adaptations_pkg;
package body adaptations_pkg is
end package body adaptations_pkg;
|
gpl-2.0
|
144cc609adb6b73bfe4a07720e210106
| 0.599258 | 4.464346 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/fixed_generic_pkg.vhdl
| 4 | 66,882 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Fixed-point package (Generic package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.fixed_float_types.all;
package fixed_generic_pkg is
generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
-- Extra bits used in divide routines
fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
no_warning : BOOLEAN := false
);
-- Author David Bishop ([email protected])
constant CopyRightNotice : STRING :=
"Copyright 2008 by IEEE. All rights reserved.";
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
alias U_ufixed is UNRESOLVED_ufixed;
alias U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is (resolved) UNRESOLVED_ufixed;
subtype sfixed is (resolved) UNRESOLVED_sfixed;
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function "?=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function "?=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "?=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the indices
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNRESOLVED_UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNRESOLVED_UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : UNRESOLVED_SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : UNRESOLVED_SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (value : UNRESOLVED_ufixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function to_ostring (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function to_hstring (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function to_string (value : UNRESOLVED_sfixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function to_ostring (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function to_hstring (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
end package fixed_generic_pkg;
|
gpl-2.0
|
8d5cdc4790200e22e1dbe49491991ab1
| 0.618627 | 4.146949 | false | false | false | false |
siavooshpayandehazad/high_level_test_pattern_gen
|
Test/AP_Alu.vhd
| 1 | 4,627 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.LIB.ALL;
ENTITY AP_Alu IS
PORT(
clock : IN std_logic;
rst : IN std_logic;
OP_A : IN AP_data_width;
OP_B : IN AP_data_width;
ALU_OP : IN std_logic_vector(3 downto 0);
RESULT : OUT AP_data_width;
carry_out : OUT std_logic;
zero_out : OUT std_logic;
sign_out : OUT std_logic;
overflow_out : OUT std_logic
);
END AP_Alu;
ARCHITECTURE behave OF AP_Alu IS
signal carry, zero, sign, overflow : std_logic;
signal carry_new, zero_new, sign_new, overflow_new : std_logic;
BEGIN
alu_process : process(OP_A, OP_B, ALU_OP)
variable RESULT_INTERN : AP_data_width;
variable RESULT_TEMP : std_logic_vector(AP_WIDTH downto 0);
begin
RESULT_INTERN := (others => '0');
carry_new <= carry;
zero_new <= zero;
sign_new <= sign;
overflow_new <= overflow;
case ALU_OP is
when "0000" => -- mov
RESULT_INTERN := OP_B;
when "0001" => -- add
RESULT_TEMP := ('0' & OP_A) + OP_B;
carry_new <= RESULT_TEMP(AP_WIDTH);
sign_new <= RESULT_TEMP(AP_WIDTH-1);
overflow_new <= (not(OP_A(AP_WIDTH-1) XOR OP_B(AP_WIDTH-1)))
AND (OP_A(AP_WIDTH-1) XOR RESULT_TEMP(AP_WIDTH-1));
if RESULT_TEMP(AP_WIDTH - 1 downto 0) = "00000000" then
zero_new <= '1';
else
zero_new <= '0';
end if;
RESULT_INTERN := RESULT_TEMP(AP_WIDTH-1 downto 0);
when "0010" | "0011" => -- sub, cmp
RESULT_TEMP := ('0' & OP_A) - OP_B;
carry_new <= RESULT_TEMP(AP_WIDTH);
sign_new <= RESULT_TEMP(AP_WIDTH-1);
overflow_new <= (OP_A(AP_WIDTH-1) XOR OP_B(AP_WIDTH-1))
AND (OP_A(AP_WIDTH-1) XOR RESULT_TEMP(AP_WIDTH-1));
if RESULT_TEMP(AP_WIDTH - 1 downto 0) = "00000000" then
zero_new <= '1';
else
zero_new <= '0';
end if;
if ALU_OP = "0010" then
RESULT_INTERN := RESULT_TEMP(AP_WIDTH-1 downto 0);
else
RESULT_INTERN := OP_A; -- bei Alu-Ops ist RF_en immer gesetzt
end if;
when "0100" => -- and
RESULT_INTERN := OP_A AND OP_B;
when "0101" => -- or
RESULT_INTERN := OP_A OR OP_B;
when "0110" => -- xor
RESULT_INTERN := OP_A XOR OP_B;
when "0111" => -- not
RESULT_INTERN := NOT OP_B;
when "1000" => -- shl
RESULT_INTERN := OP_A(AP_WIDTH-2 downto 0) & carry;
carry_new <= OP_A(AP_WIDTH-1);
when "1001" => -- shr
RESULT_INTERN := carry & OP_A(AP_WIDTH-1 downto 1);
carry_new <= OP_A(0);
when "1010" => -- asr
RESULT_INTERN := OP_A(AP_WIDTH-1) & OP_A(AP_WIDTH-1 downto 1);
carry_new <= OP_A(0);
when "1011" => -- inc
RESULT_TEMP := ('0' & OP_A) + 1;
carry_new <= RESULT_TEMP(AP_WIDTH);
sign_new <= RESULT_TEMP(AP_WIDTH-1);
overflow_new <= (not(OP_A(AP_WIDTH-1) XOR OP_B(AP_WIDTH-1)))
AND (OP_A(AP_WIDTH-1) XOR RESULT_TEMP(AP_WIDTH-1));
if RESULT_TEMP(AP_WIDTH - 1 downto 0) = "00000000" then
zero_new <= '1';
else
zero_new <= '0';
end if;
RESULT_INTERN := RESULT_TEMP(AP_WIDTH-1 downto 0);
when "1100" => -- dec
RESULT_TEMP := ('0' & OP_A) - 1;
carry_new <= RESULT_TEMP(AP_WIDTH);
sign_new <= RESULT_TEMP(AP_WIDTH-1);
overflow_new <= (OP_A(AP_WIDTH-1) XOR OP_B(AP_WIDTH-1))
AND (OP_A(AP_WIDTH-1) XOR RESULT_TEMP(AP_WIDTH-1));
if RESULT_TEMP(AP_WIDTH - 1 downto 0) = "00000000" then
zero_new <= '1';
else
zero_new <= '0';
end if;
RESULT_INTERN := RESULT_TEMP(AP_WIDTH-1 downto 0);
when "1101" =>
carry_new <= '1';
RESULT_INTERN := OP_A;
when "1110" =>
carry_new <= '0';
RESULT_INTERN := OP_A;
-- when "1111" =>
when others =>
end case;
RESULT <= RESULT_INTERN;
end process;
flag_process : process(clock, rst)
begin
if (rst = '1') then
carry <= '0';
zero <= '0';
sign <= '0';
overflow <= '0';
elsif (clock'event and clock = '1') then
carry <= carry_new;
zero <= zero_new;
sign <= sign_new;
overflow <= overflow_new;
end if;
end process;
carry_out <= carry;
zero_out <= zero;
sign_out <= sign;
overflow_out <= overflow;
END behave;
|
gpl-3.0
|
17b4459eafd72913f155995b0e8b62aa
| 0.511995 | 3.177885 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Gura/Modular/celda_B.vhd
| 1 | 1,279 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_B is
generic(
NUM_BITS : positive := 163
);
port(
U : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
P : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
Y2 : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c_1 : in STD_LOGIC;
c_2 : in STD_LOGIC;
toB : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_B is
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
toB <= Y2 when c_1 = '0' and c_2 = '0' else
P when c_1 = '0' and c_2 = '1' else
U;
end behave;
|
gpl-3.0
|
bd1f52eccd5bfa0b1ae7210bc731a870
| 0.304144 | 4.881679 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_17.vhd
| 4 | 2,853 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_17.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity single_board_computer is
end entity single_board_computer;
-- end not in book
architecture structural of single_board_computer is
-- . . . -- type and signal declarations
-- not in book
subtype word is bit_vector(31 downto 0);
signal sys_clk : bit;
signal cpu_a_d, latched_addr : word;
-- end not in book
component processor is
port ( clk : in bit; a_d : inout word; -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component processor;
component memory is
port ( addr : in bit_vector(25 downto 0); -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component memory;
component serial_interface is
port ( clk : in bit; address : in bit_vector(3 downto 0); -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end component serial_interface;
begin
cpu : component processor
port map ( clk => sys_clk, a_d => cpu_a_d, -- . . . );
-- not in book
other_port => open );
-- end not in book
main_memory : component memory
port map ( addr => latched_addr(25 downto 0), -- . . . );
-- not in book
other_port => open );
-- end not in book
serial_interface_a : component serial_interface
port map ( clk => sys_clk, address => latched_addr(3 downto 0), -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture structural;
|
gpl-2.0
|
6902b6ee9911fbf733e022e3c0e63407
| 0.532072 | 4.322727 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket89/project/src93/types_pkg.vhd
| 3 | 4,681 |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : types_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.standard_textio_additions.all;
package types_pkg is
file ALERT_FILE : text;
file LOG_FILE : text;
constant C_LOG_HDR_FOR_WAVEVIEW_WIDTH : natural := 100; -- For string in waveview indicating last log header
type t_void is (VOID);
type t_natural_array is array (natural range <>) of natural;
type t_integer_array is array (natural range <>) of integer;
-- Note: Most types below have a matching to_string() in 'string_methods_pkg.vhd'
type t_info_target is (LOG_INFO, ALERT_INFO, USER_INFO);
type t_alert_level is (NOTE, TB_NOTE, WARNING, TB_WARNING, MANUAL_CHECK, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
type t_enabled is (ENABLED, DISABLED);
type t_attention is (REGARD, EXPECT, IGNORE);
type t_radix is (BIN, HEX, DEC, HEX_BIN_IF_INVALID);
type t_radix_prefix is (EXCL_RADIX, INCL_RADIX);
type t_order is (INTERMEDIATE, FINAL);
type t_ascii_allow is (ALLOW_ALL, ALLOW_PRINTABLE_ONLY);
type t_blocking_mode is (BLOCKING, NON_BLOCKING);
type t_from_point_in_time is (FROM_NOW, FROM_LAST_EVENT);
type t_format_zeros is (AS_IS, SKIP_LEADING_0);
type t_format_string is (AS_IS, TRUNCATE, SKIP_LEADING_SPACE);
type t_log_format is (FORMATTED, UNFORMATTED);
type t_log_if_block_empty is (WRITE_HDR_IF_BLOCK_EMPTY, SKIP_LOG_IF_BLOCK_EMPTY, NOTIFY_IF_BLOCK_EMPTY);
type t_alert_counters is array (t_alert_level'left to t_alert_level'right) of natural;
type t_alert_attention is array (t_alert_level'left to t_alert_level'right) of t_attention;
type t_attention_counters is array (t_attention'left to t_attention'right) of natural; -- Only used to build below type
type t_alert_attention_counters is array (t_alert_level'left to t_alert_level'right) of t_attention_counters;
type t_quietness is (NON_QUIET, QUIET);
type t_deprecate_setting is (NO_DEPRECATE, DEPRECATE_ONCE, ALWAYS_DEPRECATE);
type t_deprecate_list is array(0 to 9) of string(1 to 100);
type t_global_ctrl is record
attention : t_alert_attention;
stop_limit : t_alert_counters;
end record;
type t_current_log_hdr is record
normal : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
large : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
xl : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
end record;
-------------------------------------
-- BFMs and above
-------------------------------------
type t_transaction_result is (ACK, NAK, ERROR); -- add more when needed
end package types_pkg;
package body types_pkg is
end package body types_pkg;
|
gpl-2.0
|
18db107b38c9905412d5b3b42bd16dd9
| 0.628071 | 3.987223 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/edge_triggered_register.vhd
| 4 | 1,485 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity edge_triggered_register is
port ( clock : in bit;
d_in : in real; d_out : out real );
end entity edge_triggered_register;
--------------------------------------------------
architecture check_timing of edge_triggered_register is
begin
store_and_check : process (clock) is
variable stored_value : real;
variable pulse_start : time;
begin
case clock is
when '1' =>
pulse_start := now;
stored_value := d_in;
d_out <= stored_value;
when '0' =>
assert now = 0 ns or (now - pulse_start) >= 5 ns
report "clock pulse too short";
end case;
end process store_and_check;
end architecture check_timing;
|
gpl-2.0
|
612d521f8cdab618cf34858852e054e4
| 0.664646 | 4.10221 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc744.vhd
| 4 | 6,069 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc744.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00744pkg is
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c: character;
d: severity_level;
e: integer;
f: real;
g: time;
h: natural;
i: positive;
j: string(1 to 7);
k: bit_vector(0 to 3);
end record;
type array_rec_std is array (integer range <>) of record_std_package;
end c01s01b01x01p05n02i00744pkg;
use work.c01s01b01x01p05n02i00744pkg.all;
ENTITY c01s01b01x01p05n02i00744ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
port(
S1 : inout boolean_vector (zero to fifteen);
S2 : inout severity_level_vector (zero to fifteen);
S3 : inout integer_vector (zero to fifteen);
S4 : inout real_vector (zero to fifteen);
S5 : inout time_vector (zero to fifteen);
S6 : inout natural_vector (zero to fifteen);
S7 : inout positive_vector (zero to fifteen);
S48: inout array_rec_std (zero to seven)
);
END c01s01b01x01p05n02i00744ent;
ARCHITECTURE c01s01b01x01p05n02i00744arch OF c01s01b01x01p05n02i00744ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for i in S1'range loop
S1(i) <= C1;
end loop;
for i in S2'range loop
S2(i) <= C4;
end loop;
for i in S3'range loop
S3(i) <= C5;
end loop;
for i in S4'range loop
S4(i) <= C6;
end loop;
for i in S5'range loop
S5(i) <= C7;
end loop;
for i in S6'range loop
S6(i) <= C8;
end loop;
for i in S7'range loop
S7(i) <= C9;
end loop;
for i in S48'range loop
S48(i) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
end loop;
wait for 10 ns;
for i in zero to 7 loop
if (S1(i) /= true) then
k := 1;
end if;
assert S1(i) = true report " boolean_vector(zero to fifteen) error in the left generic value" severity error;
if (S2(i) /= note) then
k := 1;
end if;
assert S2(i) = note report " severity_level_vector(zero to fifteen) error in the left generic value" severity error;
if (S3(i) /= 3) then
k := 1;
end if;
assert S3(i) = 3 report " integer_vector(zero to fifteen) error in the left generic value" severity error;
if (S4(i) /= 3.0) then
k := 1;
end if;
assert S4(i) = 3.0 report " real_vector(zero to fifteen) error in the left generic value" severity error;
if (S5(i) /= 3 ns) then
k := 1;
end if;
assert S5(i) = 3 ns report " time_vector (zero to fifteen) error in the left generic value" severity error;
if (S6(i) /= 1) then
k := 1;
end if;
assert S6(i) = 1 report " natural_vector(zero to fifteen) error in the left generic value" severity error;
if (S7(i) /= 1) then
k := 1;
end if;
assert S7(i) = 1 report " positive_vector(zero to fifteen) error in the left generic value" severity error;
if (S48(i) /= (true,'1','s',note,3,3.0,3 ns,1,1,"shishir","0011")) then
k := 1;
end if;
assert S48(i) = (true,'1','s',note,3,3.0,3 ns,1,1,"shishir","0011") report " array_rec_std(zero to seven) error in the left generic value" severity error;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c01s01b01x01p05n02i00744"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c01s01b01x01p05n02i00744 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00744arch;
|
gpl-2.0
|
794c452f174b7ad91d423b95e8eddf42
| 0.565826 | 3.477937 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd
| 4 | 1,228 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
port ( terminal node1, node2 : electrical );
end entity capacitor;
architecture leakage of capacitor is
constant c : real := 1.0E-6;
constant r_leak : real := 10.0E6;
quantity v_cap across i_cap, i_leak through node1 to node2;
begin
i_cap == c * v_cap'dot;
i_leak == v_cap / r_leak;
end architecture leakage;
|
gpl-2.0
|
8150eba43504658bcea33639c63b999b
| 0.718241 | 3.84953 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc675.vhd
| 4 | 3,254 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc675.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:30 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:38 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00675ent IS
END c03s04b01x00p23n01i00675ent;
ARCHITECTURE c03s04b01x00p23n01i00675arch OF c03s04b01x00p23n01i00675ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ( '0', '1', 'Z' );
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
type FT is file of LOGIC_SWITCH;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.49";
-- Declare a variable into which we will read.
constant CON : LOGIC_SWITCH := '1';
variable VAR : LOGIC_SWITCH ;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00675"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00675 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00675arch;
|
gpl-2.0
|
29c7221586295833d8eb62dc5d4036c6
| 0.546404 | 3.944242 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join-b.vhd
| 4 | 4,580 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_join-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
architecture behavior of join is
begin
joiner : process
use qsim.token_fifo_adt.all;
variable source : positive range in_arc'range;
variable token_fifo : fifo_type := new_fifo;
variable current_fifo_size : natural := 0;
variable head_token : token_type;
variable number_of_tokens_joined : natural := 0;
type counter_array is array (positive range in_arc'range) of natural;
variable number_joined_from_source : counter_array := (others => 0);
use std.textio.all;
file info_file : text;
variable L : line;
-- Modeltech bug mt043 workaround
variable in_arc_last_value : arc_vector(in_arc'range) := in_arc;
--
procedure write_summary is
begin
write(L, string'("Summary information for join "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens joined = "));
write(L, natural(number_of_tokens_joined));
writeline(info_file, L);
for source in in_arc'range loop
write(L, string'(" Number from input("));
write(L, source);
write(L, string'(") = "));
write(L, natural(number_joined_from_source(source)));
write(L, string'(" ("));
write(L, real(number_joined_from_source(source))
/ real(number_of_tokens_joined),
digits => 4);
write(L, ')');
writeline(info_file, L);
end loop;
writeline(info_file, L);
end write_summary;
procedure write_trace is
begin
write(L, string'("Join "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" joined from input "));
write(L, source);
write(L, ' ');
write(L, in_arc(source).token, time_unit);
writeline(info_file, L);
end write_trace;
procedure accept_new_tokens is
begin
for index in 1 to in_arc'length loop
-- Modeltech bug mt043 workaround
-- if in_arc(index).transaction /= in_arc'last_value(index).transaction then
if in_arc(index).transaction /= in_arc_last_value(index).transaction then
--
source := index;
insert(token_fifo, in_arc(source).token);
current_fifo_size := current_fifo_size + 1;
number_of_tokens_joined := number_of_tokens_joined + 1;
number_joined_from_source(source) := number_joined_from_source(source) + 1;
if info_detail = trace then
write_trace;
end if;
end if;
end loop;
-- Modeltech bug mt043 workaround
in_arc_last_value := in_arc;
--
end procedure accept_new_tokens;
begin
file_open(info_file, info_file_name, write_mode);
loop
wait on info_detail'transaction, in_arc;
if info_detail'active and info_detail = summary then
write_summary;
end if;
if in_arc'event then
accept_new_tokens;
while current_fifo_size > 0 loop
remove(token_fifo, head_token);
current_fifo_size := current_fifo_size - 1;
out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
token => head_token );
wait for 0 fs; -- delta delay before next output token
if info_detail'active and info_detail = summary then
write_summary;
end if;
if in_arc'event then
accept_new_tokens;
end if;
end loop;
end if;
end loop;
end process joiner;
end behavior;
|
gpl-2.0
|
4c13221d463731fade4dced55ffc8efb
| 0.603493 | 3.823038 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket65/bug1.vhdl
| 3 | 476 |
entity ent1 is
end entity;
architecture a of ent1 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value1); -- Error
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
|
gpl-2.0
|
4fbb0df88577f536ff419ed9d54f690a
| 0.657563 | 3.260274 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_04.vhd
| 4 | 2,356 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_ch_16_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_16_04 is
end entity ch_16_04;
----------------------------------------------------------------
architecture test of ch_16_04 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
-- code from book:
signal memory_data_bus : resolved_word bus;
disconnect memory_data_bus : resolved_word after 3 ns;
-- end of code from book
signal mem_sel, mem_write : boolean;
signal cache_data_bus : word;
begin
-- code from book:
mem_write_buffer : block (mem_sel and mem_write) is
begin
memory_data_bus <=
guarded reject 2 ns inertial cache_data_bus after 4 ns;
end block mem_write_buffer;
-- end of code from book
stimulus : process is
begin
cache_data_bus <= X"DDDDDDDD";
wait for 10 ns;
mem_sel <= true; mem_write <= true;
wait for 10 ns;
cache_data_bus <= X"AAAAAAAA";
wait for 10 ns;
mem_sel <= false; mem_write <= false;
wait for 10 ns;
cache_data_bus <= X"11111111";
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
ae29758618675ecb09fe3bf5c38c3d05
| 0.620968 | 3.894215 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2472.vhd
| 4 | 2,049 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2472.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02472ent IS
END c07s03b02x02p03n02i02472ent;
ARCHITECTURE c07s03b02x02p03n02i02472arch OF c07s03b02x02p03n02i02472ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 4 );
function F return CONSTRAINED_ARRAY is
begin
return CONSTRAINED_ARRAY'(2 => 'h', others => '7');
-- check in function return statement.
end F;
variable k : CONSTRAINED_ARRAY;
BEGIN
k := F;
assert NOT(k = "7h77")
report "***PASSED TEST: c07s03b02x02p03n02i02472"
severity NOTE;
assert (k = "7h77")
report "***FAILED TEST: c07s03b02x02p03n02i02472 - Others cannot be used with an unconstrained array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02472arch;
|
gpl-2.0
|
dcb38aa05eee941b019b22677995d7b9
| 0.667155 | 3.759633 | false | true | false | false |
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.b.g-tbDiv.vhd
| 1 | 1,978 |
--------------------------------------------------------------------------------
-- FILE: tbDiv
-- DESC: Testbench for Divider
--
-- Author:
-- Create: 2015-09-10
-- Update: 2015-09-10
-- Status: UNTESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity tbDiv is
end tbDiv;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture behav of tbDiv is
constant N: integer :=32;
constant S: integer :=10;
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal en: std_logic:='0';
signal ia: std_logic_vector(N-1 downto 0):=x"00000000";
signal ib: std_logic_vector(N-1 downto 0):=x"00000000";
signal oy: std_logic_vector(N-1 downto 0):=x"00000000";
component Div is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
STAGE : integer := C_DIV_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
en: in std_logic:='0';
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0') -- Data Out
);
end component;
begin
DIV0: Div
generic map (N, S)
port map (rst, clk, en, ia, ib, oy);
-- Clock generator
PCLOCK : process(clk)
begin
clk <= not(clk) after 0.5 ns;
end process;
-- Reset test
rst <= '0', '1' after 2 ns;
en <= '0', '1' after 3 ns, '0' after 15 ns;
ia<=x"00000000", x"ff05070e" after 1 ns;
ib<=x"00000001", x"244398fe" after 1 ns;
end behav;
configuration tb_div_cfg of tbDiv is
for behav
end for;
end tb_div_cfg;
|
mit
|
19ead0602f42880c5753e5991a7987c3
| 0.483316 | 3.410345 | false | false | false | false |
velentr/foundry.vhdl
|
uarttx.vhd
| 1 | 6,104 |
--------------------------------------------------------------------------------
--
-- uarttx.vhd
--
-- Universal asynchronous receiver/transmitter---transmitter design.
--
-- This file contains the design for the transmitter on a UART. The UART will
-- take in data in parallel on the data bus. It will then output the character
-- in serial on the TX line. This implementation uses N-bit characters, 1 stop
-- bit, and no parity bit. The baud rate is the same as the input clock
-- frequency. The design is parameterized on the number of bits in each
-- character.
--
-- To transmit data, output the desired character to the 'data' input and send
-- the 'rdy' line low. These signals must be latched until the UART sends the
-- 'ack' line low to acknowledge the data. Note that the 'ack' signal will be
-- pulsed low for only a single clock.
--
-- The data is transmitted MSB first; that is, the data is transmitted from the
-- most-significant bit first, down to the least-significant bit last.
--
-- Dependencies:
-- None.
--
-- Revision History:
-- 22 Apr 2015 Brian Kubisiak Initial revision.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
-- uarttx
--
-- Parameters:
-- N (integer) Number of bits per character.
--
-- Inputs:
-- reset (std_logic) Active-low line to reset the UART transmitter.
-- clk (std_logic) Baud rate clock. The UART will transmit one bit
-- on every rising edge of the clock.
-- data (std_logic_vector) Next character to send over the UART.
-- rdy (std_logic) Active-low line indicating that data is ready to
-- transmit. It should be sent low for at least one
-- baud.
--
-- Outputs:
-- tx (std_logic) Transmit line for transmitting the serial data.
-- ack (std_logic) Active-low signal acknowledging the ready data,
-- indicating that the new data will now be
-- transmitted.
--
entity uarttx is
generic ( N : integer := 8 );
port
(
reset : in std_logic; -- Reset the UART.
clk : in std_logic; -- Baud clock.
data : in std_logic_vector(N-1 downto 0); -- Parallel data output.
rdy : in std_logic; -- New data ready.
ack : out std_logic; -- Ack data ready.
tx : out std_logic -- Serial data input.
);
end entity;
architecture procedural of uarttx is
-- Register for shifting data out on the transmit line
signal shfttx : std_logic_vector(N-1 downto 0);
-- Counter for indicating the number of bits transmitted. Tere is 1 start
-- bit, N data bits, and 1 stop bit for a total of N+2 bits.
signal state : integer range 0 to N+1;
-- Latches the rdy signal, resetting whenever the resetrdy signal is active.
signal rdylatch : std_logic;
begin
--
-- DataRdyLatch
--
-- This process latches the data ready signal at the end of each character
-- transmission. The latch will hold for an entire cycle.
--
DataRdyLatch: process(clk)
begin
if rising_edge(clk) then
-- When reset is active, the latch signal goes inactive.
if (reset = '0') then
rdylatch <= '1';
-- When transmitting the stop bit, check to see if new data is
-- ready. If it is ready, latch the ready signal.
elsif (state = N+1) then
rdylatch <= rdy;
-- Else, just keep holding the latch.
else
rdylatch <= rdylatch;
end if;
end if;
end process;
--
-- TransmitData
--
-- Transmit the data one bit at a time over the 'tx' line whenever data is
-- valid. After transmission, if new data is available, transfer it to the
-- shift register and start the transmission cycle again. When data is
-- shifted into the shift register, send an acknowledgement pulse.
--
TransmitData: process(clk)
begin
if rising_edge(clk) then
-- By default, latch the shift register.
shfttx <= shfttx;
-- Do not acknowledge any transmissions.
ack <= '1';
-- When resetting or no data available, output stop bit.
if (reset = '0' or rdylatch = '1') then
-- Output stop bit
tx <= '1';
-- Hold in this state to receive new data to transmit.
state <= N+1;
-- If we are beginning a transmission, output the start bit
elsif (state = 0) then
-- Beginning of transmission; output start bit and advance to
-- next state.
tx <= '0';
state <= 1;
-- At the end of a transmission, start new transmission. Note that
-- we can only get here if new data is available (rdylatch = '0').
elsif (state = N+1) then
-- All data has been sent; output a stop bit.
tx <= '1';
-- Start a new transmission.
state <= 0;
-- Load the new data into the shift register.
shfttx <= data;
-- Acknowledge the new transmission
ack <= '0';
-- Otherwise, we are in the process of shifting out the data.
else
-- Output the next MSB from the shift register.
tx <= shfttx(N-1);
-- Shift the data.
shfttx <= shfttx(N-2 downto 0) & 'X';
-- Advance to next state.
state <= state + 1;
end if;
end if;
end process;
end architecture procedural;
|
mit
|
a3ede8af34df59f72b0d57e592ab5422
| 0.53555 | 4.518135 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg-b.vhd
| 4 | 1,545 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_cg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture behavior of clock_gen is
constant clock_period : delay_length := 2 * (Tpw + Tps);
begin
reset_driver :
reset <= '1', '0' after 2.5 * clock_period + Tps;
clock_driver : process is
begin
phi1 <= '0';
phi2 <= '0';
wait for clock_period / 2;
loop
phi1 <= '1', '0' after Tpw;
phi2 <= '1' after clock_period / 2,
'0' after clock_period / 2 + Tpw;
wait for clock_period;
end loop;
end process clock_driver;
end architecture behavior;
|
gpl-2.0
|
9921e566474bacf218931f4facb32fc7
| 0.606472 | 3.87218 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug10/FIFO.vhdl
| 3 | 1,641 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FIFO is
generic(Depth : integer := 3);
port(
iClk : in std_logic;
iReset : in std_logic;
-- write port
iWrEn : in std_logic;
iData : in std_logic_vector(7 downto 0);
oHasSpace : out std_logic;
-- read port
iRdEn : in std_logic;
oData : out std_logic_vector(7 downto 0);
oHasData : out std_logic
);
end FIFO;
architecture behaviour of FIFO is
constant DMSB : integer := Depth - 1;
constant Size : integer := 2 ** DEPTH;
type regArrayT is array(0 to Size-1) of std_logic_vector(7 downto 0);
signal free : unsigned(Depth downto 0) := (others => '0');
signal rIdx, wIdx : unsigned(DMSB downto 0) := (others => '0');
signal regArray : regArrayT;
signal rdEn, wrEn : std_logic;
signal hasData, hasSpace : std_logic;
begin
oData <= regArray(to_integer(rIdx));
hasData <= '0' when free = Size else '1';
oHasData <= hasData;
hasSpace <= '0' when free = to_unsigned(0, Depth) else '1';
oHasSpace <= hasSpace;
rdEn <= iRdEn and hasData;
wrEn <= iWrEn and hasSpace;
main: process(iClk) begin
if iClk'event and iClk = '1' then
if iReset = '1' then
free <= to_unsigned(Size, Depth + 1);
rIdx <= (others => '0');
wIdx <= (others => '0');
elsif wrEn = '1' and rdEn = '1' then
rIdx <= rIdx + 1;
regArray(to_integer(wIdx)) <= iData;
wIdx <= wIdx + 1;
elsif rdEn = '1' then
rIdx <= rIdx + 1;
free <= free + 1;
elsif wrEn = '1' then
regArray(to_integer(wIdx)) <= iData;
wIdx <= wIdx + 1;
free <= free - 1;
end if;
end if;
end process;
end behaviour;
|
gpl-2.0
|
1734f1768c70491a0e747649574605ef
| 0.61426 | 2.730449 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/generate_clock.vhd
| 4 | 1,707 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity generate_clock is
end entity generate_clock;
library ieee; use ieee.std_logic_1164.all;
architecture test of generate_clock is
-- code from book
procedure generate_clock ( signal clk : out std_ulogic;
constant Tperiod, Tpulse, Tphase : in time ) is
begin
wait for Tphase;
loop
clk <= '1', '0' after Tpulse;
wait for Tperiod;
end loop;
end procedure generate_clock;
-- end code from book
-- code from book (in text)
signal phi1, phi2 : std_ulogic := '0';
-- . . .
-- end code from book
begin
-- code from book (in text)
gen_phi1 : generate_clock ( phi1, Tperiod => 50 ns, Tpulse => 20 ns,
Tphase => 0 ns );
gen_phi2 : generate_clock ( phi2, Tperiod => 50 ns, Tpulse => 20 ns,
Tphase => 25 ns );
-- end code from book
end architecture test;
|
gpl-2.0
|
76ced902b425336f39aa000169145539
| 0.651435 | 4.103365 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/MeasFreq.vhd
| 4 | 1,388 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity MeasFreq is
generic ( thres : real := 0.0 );
port ( terminal input : electrical;
signal f_out : out real := 0.0 );
end entity MeasFreq;
----------------------------------------------------------------
architecture ThresDetect of MeasFreq is
quantity vin across input;
begin
detect : process ( vin'above(thres) ) is
variable t_old : real := real'low;
begin
if vin'above(thres) then
f_out <= 1.0 / (now - t_old);
t_old := now;
end if;
end process detect;
end ThresDetect;
|
gpl-2.0
|
8c040b429c95c85be268d0ecaa4d694c
| 0.672911 | 4.05848 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd
| 4 | 1,751 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp_wa is
port ( terminal positive_supply, negative_supply : electrical;
terminal plus_in, minus_in, output : electrical );
end entity opamp_wa;
----------------------------------------------------------------
architecture saturating of opamp_wa is
constant gain : real := 50.0;
quantity v_pos := 15.0 across positive_supply;
quantity v_neg := -15.0 across negative_supply;
quantity v_in across plus_in to minus_in;
quantity v_out across i_out through output;
quantity v_amplified : voltage;
begin
if v_in'above(v_pos / gain) use
v_amplified == v_pos;
elsif not v_in'above(v_neg / gain) use
v_amplified == v_neg;
else
v_amplified == gain * v_in;
end use;
break on v_in'above(v_pos/gain), v_in'above(v_neg/gain);
v_out == v_amplified; -- 'slew(1.0e6,-1.0e6);
end architecture saturating;
|
gpl-2.0
|
824b4b83fd804fa5d9cfedff8983861d
| 0.671045 | 3.823144 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_07.vhd
| 4 | 2,175 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_07.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_07 is
end entity fg_07_07;
architecture test of fg_07_07 is
subtype word32 is bit_vector(31 downto 0);
-- code in book
procedure addu ( a, b : in word32;
result : out word32; overflow : out boolean ) is
variable sum : word32;
variable carry : bit := '0';
begin
for index in sum'reverse_range loop
sum(index) := a(index) xor b(index) xor carry;
carry := ( a(index) and b(index) ) or ( carry and ( a(index) xor b(index) ) );
end loop;
result := sum;
overflow := carry = '1';
end procedure addu;
-- end code in book
begin
stimulus : process is
-- code in book (in text)
variable PC, next_PC : word32;
variable overflow_flag : boolean;
-- . . .
-- end code in book
begin
PC := X"0000_0010";
-- code in book (in text)
addu ( PC, X"0000_0004", next_PC, overflow_flag);
-- end code in book
PC := X"FFFF_FFFC";
addu ( PC, X"0000_0004", next_PC, overflow_flag);
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
df8222be9b4ebc8308d7be44dc3278de
| 0.57977 | 3.954545 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic_body.vhd
| 4 | 21,292 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: bv_arithmetic_body.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
package body bv_arithmetic is
----------------------------------------------------------------
-- Type conversions
----------------------------------------------------------------
function bv_to_natural ( bv : in bit_vector ) return natural is
variable result : natural := 0;
begin
for index in bv'range loop
result := result * 2 + bit'pos( bv(index) );
end loop;
return result;
end function bv_to_natural;
function natural_to_bv ( nat : in natural;
length : in natural ) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(length - 1 downto 0) := (others => '0');
begin
for index in result'reverse_range loop
result(index) := bit'val( temp rem 2 );
temp := temp / 2;
exit when temp = 0;
end loop;
return result;
end function natural_to_bv;
function bv_to_integer ( bv : in bit_vector ) return integer is
variable temp : bit_vector(bv'range);
variable result : integer := 0;
begin
if bv(bv'left) = '1' then -- negative number
temp := not bv;
else
temp := bv;
end if;
for index in bv'range loop -- sign bit of temp = '0'
result := result * 2 + bit'pos( temp(index) );
end loop;
if bv(bv'left) = '1' then
result := (-result) - 1;
end if;
return result;
end function bv_to_integer;
function integer_to_bv ( int : in integer;
length : in natural ) return bit_vector is
variable temp : integer;
variable result : bit_vector(length - 1 downto 0) := (others => '0');
begin
if int < 0 then
temp := - (int + 1);
else
temp := int;
end if;
for index in result'reverse_range loop
result(index) := bit'val( temp rem 2 );
temp := temp / 2;
exit when temp = 0;
end loop;
if int < 0 then
result := not result;
result(result'left) := '1';
end if;
return result;
end function integer_to_bv;
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
procedure bv_add ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv_result'length - 1 downto 0);
variable carry_in : bit;
variable carry_out : bit := '0';
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_add: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor op2(index) xor carry_in;
carry_out := (op1(index) and op2(index))
or (carry_in and (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := carry_out /= carry_in;
end if;
end procedure bv_add;
function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv1'length - 1 downto 0);
variable carry_in : bit;
variable carry_out : bit := '0';
begin
if bv1'length /= bv2'length then
report """+"": operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor op2(index) xor carry_in;
carry_out := (op1(index) and op2(index))
or (carry_in and (op1(index) xor op2(index)));
end loop;
end if;
return result;
end function "+";
procedure bv_sub ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
-- subtraction implemented by adding ((not bv2) + 1), ie -bv2
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv_result'length - 1 downto 0);
variable carry_in : bit;
variable carry_out : bit := '1';
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_sub: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor (not op2(index)) xor carry_in;
carry_out := (op1(index) and (not op2(index)))
or (carry_in and (op1(index) xor (not op2(index))));
end loop;
bv_result := result;
overflow := carry_out /= carry_in;
end if;
end procedure bv_sub;
function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is
-- subtraction implemented by adding ((not bv2) + 1), ie -bv2
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv1'length - 1 downto 0);
variable carry_in : bit;
variable carry_out : bit := '1';
begin
if bv1'length /= bv2'length then
report """-"": operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor (not op2(index)) xor carry_in;
carry_out := (op1(index) and (not op2(index)))
or (carry_in and (op1(index) xor (not op2(index))));
end loop;
end if;
return result;
end function "-";
procedure bv_addu ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv_result'length - 1 downto 0);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_addu: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor carry;
carry := (op1(index) and op2(index))
or (carry and (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := carry = '1';
end if;
end procedure bv_addu;
function bv_addu ( bv1, bv2 : in bit_vector ) return bit_vector is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv1'length - 1 downto 0);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "bv_addu: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor carry;
carry := (op1(index) and op2(index))
or (carry and (op1(index) xor op2(index)));
end loop;
end if;
return result;
end function bv_addu;
procedure bv_subu ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv_result'length - 1 downto 0);
variable borrow : bit := '0';
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_subu: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor borrow;
borrow := (not op1(index) and op2(index))
or (borrow and not (op1(index) xor op2(index)));
end loop;
bv_result := result;
overflow := borrow = '1';
end if;
end procedure bv_subu;
function bv_subu ( bv1, bv2 : in bit_vector ) return bit_vector is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
variable result : bit_vector(bv1'length - 1 downto 0);
variable borrow : bit := '0';
begin
if bv1'length /= bv2'length then
report "bv_subu: operands of different lengths"
severity failure;
else
for index in result'reverse_range loop
result(index) := op1(index) xor op2(index) xor borrow;
borrow := (not op1(index) and op2(index))
or (borrow and not (op1(index) xor op2(index)));
end loop;
end if;
return result;
end function bv_subu;
procedure bv_neg ( bv : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
constant zero : bit_vector(bv'range) := (others => '0');
begin
bv_sub( zero, bv, bv_result, overflow );
end procedure bv_neg;
function "-" ( bv : in bit_vector ) return bit_vector is
constant zero : bit_vector(bv'range) := (others => '0');
begin
return zero - bv;
end function "-";
procedure bv_mult ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable multu_result : bit_vector(bv1'range);
variable multu_overflow : boolean;
variable abs_min_int : bit_vector(bv1'range) := (others => '0');
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_mult: operands of different lengths"
severity failure;
else
abs_min_int(bv1'left) := '1';
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if op1(op1'left) = '1' then
op1 := - bv1;
end if;
if op2(op2'left) = '1' then
op2 := - bv2;
end if;
bv_multu(op1, op2, multu_result, multu_overflow);
if negative_result then
overflow := multu_overflow or (multu_result > abs_min_int);
bv_result := - multu_result;
else
overflow := multu_overflow or (multu_result(multu_result'left) = '1');
bv_result := multu_result;
end if;
end if;
end procedure bv_mult;
function "*" ( bv1, bv2 : in bit_vector ) return bit_vector is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable result : bit_vector(bv1'range);
begin
if bv1'length /= bv2'length then
report """*"": operands of different lengths"
severity failure;
else
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if op1(op1'left) = '1' then
op1 := - bv1;
end if;
if op2(op2'left) = '1' then
op2 := - bv2;
end if;
result := bv_multu(op1, op2);
if negative_result then
result := - result;
end if;
end if;
return result;
end function "*";
procedure bv_multu ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean ) is
alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;
constant len : natural := bv1'length;
constant accum_len : natural := len * 2;
variable accum : bit_vector(accum_len - 1 downto 0) := (others => '0');
constant zero : bit_vector(accum_len - 1 downto len):= (others => '0');
variable addu_overflow : boolean;
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_multu: operands of different lengths"
severity failure;
else
for count in 0 to len - 1 loop
if op2(count) = '1' then
bv_addu( accum(count + len - 1 downto count), op1,
accum(count + len - 1 downto count), addu_overflow);
accum(count + len) := bit'val(boolean'pos(addu_overflow));
end if;
end loop;
bv_result := accum(len - 1 downto 0);
overflow := accum(accum_len-1 downto len) /= zero;
end if;
end procedure bv_multu;
function bv_multu ( bv1, bv2 : in bit_vector ) return bit_vector is
-- Use bv_multu with overflow detection, but ignore overflow flag
variable result : bit_vector(bv1'range);
variable tmp_overflow : boolean;
begin
bv_multu(bv1, bv2, result, tmp_overflow);
return result;
end function bv_multu;
procedure bv_div ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
div_by_zero : out boolean;
overflow : out boolean ) is
-- Need overflow, in case divide b"10...0" (min_int) by -1
-- Don't use bv_to_int, in case size bigger than host machine!
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable divu_result : bit_vector(bv1'range);
begin
if bv1'length /= bv2'length or bv1'length /= bv_result'length then
report "bv_div: operands of different lengths"
severity failure;
else
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if op1(op1'left) = '1' then
op1 := - bv1;
end if;
if op2(op2'left) = '1' then
op2 := - bv2;
end if;
bv_divu(op1, op2, divu_result, div_by_zero);
if negative_result then
overflow := false;
bv_result := - divu_result;
else
overflow := divu_result(divu_result'left) = '1';
bv_result := divu_result;
end if;
end if;
end procedure bv_div;
function "/" ( bv1, bv2 : in bit_vector ) return bit_vector is
variable negative_result : boolean;
variable op1 : bit_vector(bv1'range) := bv1;
variable op2 : bit_vector(bv2'range) := bv2;
variable result : bit_vector(bv1'range);
begin
if bv1'length /= bv2'length then
report """/"": operands of different lengths"
severity failure;
else
negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
if op1(op1'left) = '1' then
op1 := - bv1;
end if;
if op2(op2'left) = '1' then
op2 := - bv2;
end if;
result := bv_divu(op1, op2);
if negative_result then
result := - result;
end if;
end if;
return result;
end function "/";
procedure bv_divu ( bv1, bv2 : in bit_vector;
bv_quotient : out bit_vector;
bv_remainder : out bit_vector;
div_by_zero : out boolean ) is
constant len : natural := bv1'length;
constant zero_divisor : bit_vector(len-1 downto 0) := (others => '0');
alias dividend : bit_vector(bv1'length-1 downto 0) is bv1;
variable divisor : bit_vector(bv2'length downto 0) := '0' & bv2;
variable quotient : bit_vector(len-1 downto 0);
variable remainder : bit_vector(len downto 0) := (others => '0');
variable ignore_overflow : boolean;
begin
if bv1'length /= bv2'length
or bv1'length /= bv_quotient'length or bv1'length /= bv_remainder'length then
report "bv_divu: operands of different lengths"
severity failure;
else
-- check for zero divisor
if bv2 = zero_divisor then
div_by_zero := true;
return;
end if;
-- perform division
for iter in len-1 downto 0 loop
if remainder(len) = '0' then
remainder := remainder sll 1;
remainder(0) := dividend(iter);
bv_sub(remainder, divisor, remainder, ignore_overflow);
else
remainder := remainder sll 1;
remainder(0) := dividend(iter);
bv_add(remainder, divisor, remainder, ignore_overflow);
end if;
quotient(iter) := not remainder(len);
end loop;
if remainder(len) = '1' then
bv_add(remainder, divisor, remainder, ignore_overflow);
end if;
bv_quotient := quotient;
bv_remainder := remainder(len - 1 downto 0);
div_by_zero := false;
end if;
end procedure bv_divu;
procedure bv_divu ( bv1, bv2 : in bit_vector;
bv_quotient : out bit_vector;
div_by_zero : out boolean ) is
variable ignore_remainder : bit_vector(bv_quotient'range);
begin
bv_divu(bv1, bv2, bv_quotient, ignore_remainder, div_by_zero);
end procedure bv_divu;
function bv_divu ( bv1, bv2 : in bit_vector ) return bit_vector is
variable result : bit_vector(bv1'range);
variable tmp_div_by_zero : boolean;
begin
bv_divu(bv1, bv2, result, tmp_div_by_zero);
return result;
end function bv_divu;
----------------------------------------------------------------
-- Arithmetic comparison operators.
-- Perform comparisons on bit vector encoded signed integers.
-- (For unsigned integers, built in lexical comparison does
-- the required operation.)
----------------------------------------------------------------
function bv_lt ( bv1, bv2 : in bit_vector ) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_lt: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 < tmp2;
end function bv_lt;
function bv_le ( bv1, bv2 : in bit_vector ) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_le: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 <= tmp2;
end function bv_le;
function bv_gt ( bv1, bv2 : in bit_vector ) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_gt: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 > tmp2;
end function bv_gt;
function bv_ge ( bv1, bv2 : in bit_vector ) return boolean is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
assert bv1'length = bv2'length
report "bv_ged: operands of different lengths"
severity failure;
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return tmp1 >= tmp2;
end function bv_ge;
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
function bv_sext ( bv : in bit_vector;
length : in natural ) return bit_vector is
alias bv_norm : bit_vector(bv'length - 1 downto 0) is bv;
variable result : bit_vector(length - 1 downto 0) := (others => bv(bv'left));
variable src_length : natural := bv'length;
begin
if src_length > length then
src_length := length;
end if;
result(src_length - 1 downto 0) := bv_norm(src_length - 1 downto 0);
return result;
end function bv_sext;
function bv_zext ( bv : in bit_vector;
length : in natural ) return bit_vector is
alias bv_norm : bit_vector(bv'length - 1 downto 0) is bv;
variable result : bit_vector(length - 1 downto 0) := (others => '0');
variable src_length : natural := bv'length;
begin
if src_length > length then
src_length := length;
end if;
result(src_length - 1 downto 0) := bv_norm(src_length - 1 downto 0);
return result;
end function bv_zext;
end package body bv_arithmetic;
|
gpl-2.0
|
181760aa4cfca9581a499e29b4336974
| 0.585102 | 3.591768 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd
| 4 | 1,532 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inverting_integrator is
port ( terminal input, output : electrical );
end entity inverting_integrator;
----------------------------------------------------------------
architecture structural of inverting_integrator is
terminal internal : electrical;
begin
r1 : entity work.resistor(ideal)
port map ( node1 => input, node2 => internal ) ;
c1 : entity work.capacitor(leakage)
port map ( node1 => internal, node2 => output );
amp : entity work.opamp(slew_limited)
port map ( plus_in => electrical_ref, minus_in => internal,
output => output );
end architecture structural;
|
gpl-2.0
|
2d4b428bd0a75d28b36ff304e8f7a3b5
| 0.672324 | 4.492669 | false | false | false | false |
nczempin/NICNAC16
|
ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_prod.vhd
| 1 | 10,034 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
ENA => ENA,
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
mit
|
3342380a8e08b1a683e943093441f9ba
| 0.49402 | 3.773599 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd
| 4 | 2,370 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity misc_logic is
end entity misc_logic;
-- end not in book
use work.MVL4.all;
architecture gate_level of misc_logic is
signal src1, src1_enable : MVL4_ulogic;
signal src2, src2_enable : MVL4_ulogic;
signal selected_val : MVL4_logic;
-- . . .
begin
src1_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src1, enable => src1_enable, y => selected_val );
src2_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src2, enable => src2_enable, y => selected_val );
-- . . .
-- not in book
stimulus : process is
begin
wait for 10 ns;
src1_enable <= '0'; src2_enable <= '0'; wait for 10 ns;
src1 <= '0'; src2 <= '1'; wait for 10 ns;
src1_enable <= '1'; wait for 10 ns;
src1 <= 'Z'; wait for 10 ns;
src1 <= '1'; wait for 10 ns;
src1_enable <= '0'; wait for 10 ns;
src2_enable <= '1'; wait for 10 ns;
src2 <= 'Z'; wait for 10 ns;
src2 <= '0'; wait for 10 ns;
src2_enable <= '0'; wait for 10 ns;
src1_enable <= '1'; src2_enable <= '1'; wait for 10 ns;
src1 <= '0'; wait for 10 ns;
src1 <= 'X'; wait for 10 ns;
src1 <= '1'; src2 <= '1'; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture gate_level;
|
gpl-2.0
|
7bc103eae9a58be834b5f1e8918dcb09
| 0.567932 | 3.755943 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/mux4.vhd
| 4 | 1,527 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- test code:
package mux4_types is
-- code from book:
type sel_range is range 0 to 3;
-- end of code from book
end package mux4_types;
use work.mux4_types.all;
-- end test code
library ieee; use ieee.std_logic_1164.all;
entity mux4 is
port ( sel : in sel_range;
d0, d1, d2, d3 : in std_ulogic;
z : out std_ulogic );
end entity mux4;
--------------------------------------------------
architecture demo of mux4 is
begin
out_select : process (sel, d0, d1, d2, d3) is
begin
case sel is
when 0 =>
z <= d0;
when 1 =>
z <= d1;
when 2 =>
z <= d2;
when 3 =>
z <= d3;
end case;
end process out_select;
end architecture demo;
|
gpl-2.0
|
a28944924fcee5b713edca163a1c5b8a
| 0.637852 | 3.697337 | false | false | false | false |
velentr/foundry.vhdl
|
pwm.vhd
| 1 | 4,287 |
--------------------------------------------------------------------------------
--
-- pwm.vhd
--
-- This file contains the logic for a simple PWM output signal. The output of
-- this module is set high whenever the counter is reset back to zero, and is
-- cleared whenever the counter reaches the compare value. This results in a
-- PWM output with a period determined by the period of the counter, and a duty
-- cycle determined by the compare value.
--
-- The design is parameterized on N, which is the number of bits in the counter
-- and compare value. The size of the overall design is O(N).
--
-- Note that due to the design of the comparator, a 100% duty cycle (i.e. the
-- output on for the entire cycle) cannot be achieved. The highest possible
-- duty cycle is (2^N - 1) / 2^N. This sacrifice is made in order to allow a
-- 0% duty cycle, which is usually more important.
--
-- The output of the design is synchronized using the input clock. It is
-- assumed that this clock also determined the counter rate, but this not
-- strictly necessary.
--
-- Dependencies:
-- None.
--
-- Revision History:
-- 29 Mar 2015 Brian Kubisiak Initial revision.
--
--------------------------------------------------------------------------------
-- bring in the necessary packages
library ieee;
use ieee.std_logic_1164.all;
-- PWM
--
-- parameters:
-- N (integer) Number of bits in the counter and compare
-- inputs.
--
-- inputs:
-- Clk (std_logic) System clock for synchronizing the PWM output.
-- Cnt (std_logic_vector) Counter that determines the period of the PWM
-- output.
-- Cmp (std_logic_vector) Compare value for determining the duty cycle of
-- the PWM output.
--
-- outputs:
-- PwmOut (std_logic) Pulse-width-modulated signal, where the period
-- of each pulse is controlled by the Cnt input,
-- and the duty cycle is controlled by the Cmp
-- input.
entity PWM is
-- Number of bits in the counter and compare value.
generic ( N : integer := 8 );
port (
-- System clock for synchronizing output.
Clk : in std_logic;
-- Counter determining the period.
Cnt : in std_logic_vector(N-1 downto 0);
-- Compare value determining the duty cycle.
Cmp : in std_logic_vector(N-1 downto 0);
-- Pulse-width-modulated output.
PwmOut : out std_logic
);
end PWM;
architecture procedural of PWM is
-- This constant is a vector of zeros of length N. It is needed to compare
-- the counter to a generic-length vector of zeroes.
constant ZERO : std_logic_vector(N-1 downto 0) := (others => '0');
-- This signal just buffers the PWM output, allowing the logic to read the
-- value that it is currently outputting.
signal PwmVal : std_logic;
begin
-- Always output the current value of the PWM comparator.
PwmOut <= PwmVal;
--
-- SetOutput
--
-- This process synchronously determines the PWM signal. When the counter
-- reaches the compare value, then the output is cleared. Once the counter
-- is reset to 0, then the output is set again. This creates a PWM output
-- with the same period as the counter and a duty cycle determined by the
-- compare value.
--
-- Note that if the compare value is 0, then the output will always be low.
-- Because of this, the output can never be high all the time.
--
SetOutput: process(clk)
begin
-- Synchronize the output based on the clock.
if rising_edge(clk) then
-- Whenever the counter reaches the compare value, reset the PWM
-- output.
if (Cnt = Cmp) then
PwmVal <= '0';
-- Else, once the counter resets, we can set the PWM output.
elsif (Cnt = ZERO) then
PwmVal <= '1';
-- Otherwise, just latch the current value of the PWM output.
else
PwmVal <= PwmVal;
end if;
end if;
end process SetOutput;
end procedural;
|
mit
|
56b05d2a22a587760908e657c18577a4
| 0.589223 | 4.37449 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/math_real.vhdl
| 4 | 21,197 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_REAL package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common REAL
-- : constants and common REAL elementary mathematical
-- : functions.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice : STRING
:= "Copyright 2008 IEEE. All rights reserved.";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E : REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2 : REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2 : REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI : REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD : REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG : REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X : in REAL) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1, SEED2 : inout POSITIVE; variable X : out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X : in REAL; BASE : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS (X : in REAL) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end package MATH_REAL;
|
gpl-2.0
|
4486e687078f2fa4391cdb7289dde933
| 0.500165 | 3.674294 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/SingleFile/f2m_divider_277.vhd
| 1 | 8,920 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_277 is
generic(
NUM_BITS : positive := 277
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
Ux : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_277 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
--constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par, u_mas_v_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, INIT, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & y;
B <= F;
U <= '0' & x;
v <= (others => '0');
Ux <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
Ux <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
b87e9c415a47b08f41174726c932d774
| 0.499103 | 4.772606 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/fixed_generic_pkg-body.vhdl
| 4 | 217,043 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Fixed-point package (Generic package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point arithmetic
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
package body fixed_generic_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition, silent
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report fixed_generic_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed
is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_sfixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_generic_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_ufixed) -- input
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_ufixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_generic_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type convert a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNRESOLVED_UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_ufixed(arg);
return result;
end function to_fixed;
-- Type convert a "signed" into an "sfixed", used internally
function to_fixed (
arg : UNRESOLVED_SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_sfixed(arg);
return result;
end function to_fixed;
-- Type convert a "ufixed" into an "unsigned", used internally
function to_uns (
arg : UNRESOLVED_ufixed) -- fp vector
return UNRESOLVED_UNSIGNED
is
subtype t is UNRESOLVED_UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
return slv;
end function to_uns;
-- Type convert an "sfixed" into a "signed", used internally
function to_s (
arg : UNRESOLVED_sfixed) -- fp vector
return UNRESOLVED_SIGNED
is
subtype t is UNRESOLVED_SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
return slv;
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_ufixed;
result : out UNRESOLVED_ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNRESOLVED_UNSIGNED (arg'high-arg'low+1 downto 0)
:= (others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_sfixed;
result : out UNRESOLVED_sfixed;
overflowx : out BOOLEAN) is
variable args, ress : UNRESOLVED_SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or (STD_ULOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : UNRESOLVED_ufixed;
remainder : UNRESOLVED_ufixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_ufixed
is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : UNRESOLVED_sfixed;
remainder : UNRESOLVED_sfixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_sfixed
is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- Sign bit not fixed when wrapping
end if;
end if;
return result;
end function round_fixed;
-- converts an sfixed into a ufixed. The output is the same length as the
-- input, because abs("1000") = "1000" = 8.
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);
variable result : UNRESOLVED_ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
return result;
end function to_ufixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- Conversion functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR
is
subtype result_subtype is STD_ULOGIC_VECTOR (arg'length-1 downto 0);
variable result : result_subtype;
begin
if arg'length < 1 then
return NSLV;
end if;
result := result_subtype (arg);
return result;
end function to_sulv;
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR
is
subtype result_subtype is STD_ULOGIC_VECTOR (arg'length-1 downto 0);
variable result : result_subtype;
--variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
--result := STD_ULOGIC_VECTOR (arg);
result := result_subtype (arg);
return result;
end function to_sulv;
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_sulv(arg);
end function to_slv;
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_sulv(arg);
end function to_slv;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report fixed_generic_pkg'instance_name & "TO_UFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNRESOLVED_UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report fixed_generic_pkg'instance_name & "TO_SFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => UNRESOLVED_SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : UNRESOLVED_SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed
is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : UNRESOLVED_SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
-- Addition
function "+" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return UNRESOLVED_ufixed -- ufixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return UNRESOLVED_sfixed -- sfixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
variable result_slv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return UNRESOLVED_ufixed -- ufixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return UNRESOLVED_sfixed -- sfixed(max(a,c)+1 downto min(b,d))
is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
variable result_slv : UNRESOLVED_SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return UNRESOLVED_ufixed -- ufixed(a+c+1 downto b+d)
is
variable lslv : UNRESOLVED_UNSIGNED (l'length-1 downto 0);
variable rslv : UNRESOLVED_UNSIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return UNRESOLVED_sfixed -- sfixed(a+c+1 downto b+d)
is
variable lslv : UNRESOLVED_SIGNED (l'length-1 downto 0);
variable rslv : UNRESOLVED_SIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_SIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
mine (l'low, l'low) - r'high -1);
variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNRESOLVED_UNSIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report fixed_generic_pkg'instance_name
& "DIVIDE(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
mine (l'low, l'low) - r'high);
variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
variable rslv : UNRESOLVED_SIGNED (r'length-1 downto 0);
variable result_slv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report fixed_generic_pkg'instance_name
& "DIVIDE(sfixed) Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed
is
constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
begin
return divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return remainder (l, r);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return remainder (l, r);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
mine(l'low, r'low));
constant rlow : integer := mins(r'low, r'low);
variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
rlow-guard_bits);
variable rresize : UNRESOLVED_ufixed (r'high downto rlow-guard_bits);
variable dresult : UNRESOLVED_ufixed (rresize'range);
variable lslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNRESOLVED_UNSIGNED (rresize'length-1 downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rresize := resize (arg => r,
left_index => rresize'high,
right_index => rresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
rslv := to_uns (rresize);
if (rslv = 0) then
report fixed_generic_pkg'instance_name
& "remainder(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- can't overflow
round_style => round_style);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
mine(r'low, l'low));
variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
result := UNRESOLVED_sfixed (remainder (
l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return modulo (l, r);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return modulo(l, r);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style,
guard_bits => guard_bits);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed
is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (r'high downto
mine(r'low, l'low));
variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_UNSIGNED (left_index-right_index
downto 0);
variable cx : UNRESOLVED_UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (left_index-right_index
downto 0);
variable result_slv : UNRESOLVED_SIGNED (left_index-right_index
downto 0);
variable cx : UNRESOLVED_SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED)
return UNRESOLVED_ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED)
return UNRESOLVED_sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if arg(i) ?= y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed
is
variable argslv : UNRESOLVED_UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed
is
variable argslv : UNRESOLVED_SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operators
function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return and to_sulv(l);
end function "and";
function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nand to_sulv(l);
end function "nand";
function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return or to_sulv(l);
end function "or";
function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nor to_sulv(l);
end function "nor";
function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xor to_sulv(l);
end function "xor";
function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xnor to_sulv(l);
end function "xnor";
function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return and to_sulv(l);
end function "and";
function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nand to_sulv(l);
end function "nand";
function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return or to_sulv(l);
end function "or";
function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nor to_sulv(l);
end function "nor";
function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xor to_sulv(l);
end function "xor";
function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xnor to_sulv(l);
end function "xnor";
-- End reduction operators
function "?=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?= rslv;
end if;
end function "?=";
function "?/=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?/= rslv;
end if;
end function "?/=";
function "?>" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?> rslv;
end if;
end function "?>";
function "?>=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?>= rslv;
end if;
end function "?>=";
function "?<" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?< rslv;
end if;
end function "?<";
function "?<=" (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv ?<= rslv;
end if;
end function "?<=";
function "?=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?= rslv;
end if;
end function "?=";
function "?/=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?/= rslv;
end if;
end function "?/=";
function "?>" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?> rslv;
end if;
end function "?>";
function "?>=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?>= rslv;
end if;
end function "?>=";
function "?<" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?< rslv;
end if;
end function "?<";
function "?<=" (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv ?<= rslv;
end if;
end function "?<=";
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
-- compare functions
function "=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN
is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : UNRESOLVED_SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(maximum(to_uns(lresize), to_uns(rresize)),
left_index, right_index);
end function maximum;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(maximum(to_s(lresize), to_s(rresize)),
left_index, right_index);
end function maximum;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(minimum(to_uns(lresize), to_uns(rresize)),
left_index, right_index);
end function minimum;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
return to_fixed(minimum(to_s(lresize), to_s(rresize)),
left_index, right_index);
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw);
variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : NATURAL; -- internal version of arg
begin
if (result'length < 1) then
return NAUF;
end if;
if arg /= 0 then
argx := arg;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := '0';
else
sresult(I) := '1';
end if;
argx := argx/2;
end loop;
if argx /= 0 then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "TO_UFIXED(NATURAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
return saturate (left_index, right_index);
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw);
variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : INTEGER; -- internal version of arg
variable sign : STD_ULOGIC; -- sign of input
begin
if (result'length < 1) then -- null range
return NASF;
end if;
if arg /= 0 then
if (arg < 0) then
sign := '1';
argx := -(arg + 1);
else
sign := '0';
argx := arg;
end if;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := sign;
else
sresult(I) := not sign;
end if;
argx := argx/2;
end loop;
if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_saturate then -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_ufixed (left_index downto
fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report fixed_generic_pkg'instance_name
& "TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report fixed_generic_pkg'instance_name
& "TO_UFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report fixed_generic_pkg'instance_name
& "TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NAUF;
end if;
result := resize (arg => UNRESOLVED_ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- converted version
function to_ufixed (
arg : UNRESOLVED_UNSIGNED) -- unsigned
return UNRESOLVED_ufixed
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return UNRESOLVED_ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NASF;
end if;
result := resize (arg => UNRESOLVED_sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- converted version
function to_sfixed (
arg : UNRESOLVED_SIGNED) -- signed
return UNRESOLVED_sfixed
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return UNRESOLVED_sfixed(xarg);
end function to_sfixed;
function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function to_sfixed;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
(others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
(others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_generic_pkg'instance_name
& "TO_UFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_generic_pkg'instance_name
& "TO_SFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
size_res : UNRESOLVED_UNSIGNED; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
size_res : UNRESOLVED_SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : UNRESOLVED_ufixed) -- ufixed point input
return REAL
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "TO_REAL (ufixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : UNRESOLVED_sfixed) -- ufixed point input
return REAL
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "TO_REAL (sfixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := to_ufixed (arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL
is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNRESOLVED_UNSIGNED (left_index+1 downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "TO_INTEGER (ufixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : UNRESOLVED_SIGNED (left_index+1 downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : UNRESOLVED_ufixed; -- ufixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (s'range); -- result
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "TO_01(ufixed): null detected, returning NULL"
severity warning;
return NAUF;
end if;
return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
end function to_01;
function to_01 (
s : UNRESOLVED_sfixed; -- sfixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (s'range);
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "TO_01(sfixed): null detected, returning NULL"
severity warning;
return NASF;
end if;
return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
end function to_01;
function Is_X (
arg : UNRESOLVED_ufixed)
return BOOLEAN
is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function Is_X (
arg : UNRESOLVED_sfixed)
return BOOLEAN
is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function To_X01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_ufixed (arghigh downto arglow);
variable result : UNRESOLVED_ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or(to_sulv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style = fixed_saturate and
or (to_sulv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_sfixed (arghigh downto arglow);
variable result : UNRESOLVED_sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) then
reduced := or (to_sulv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNRESOLVED_UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : UNRESOLVED_SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed
is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded math functions for real
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) + r);
end function "+";
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) - r);
end function "-";
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) * r);
end function "*";
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) mod r);
end function "mod";
-- Overloaded math functions for integers
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, 0));
end function "+";
function "+" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, 0));
end function "+";
function "+" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) + r);
end function "+";
-- Overloaded functions
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, 0));
end function "-";
function "-" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, 0));
end function "-";
function "-" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) - r);
end function "-";
-- Overloaded functions
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, 0));
end function "*";
function "*" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, 0));
end function "*";
function "*" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) * r);
end function "*";
-- Overloaded functions
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, 0));
end function "/";
function "/" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, 0));
end function "/";
function "/" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, 0));
end function "rem";
function "rem" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, 0));
end function "rem";
function "rem" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, 0));
end function "mod";
function "mod" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, 0));
end function "mod";
function "mod" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) mod r);
end function "mod";
-- overloaded ufixed compare functions with integer
function "=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?= to_ufixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?/= to_ufixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?>= to_ufixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?<= to_ufixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?> to_ufixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return (l ?< to_ufixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- NATURAL to ufixed
function "=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded ufixed compare functions with real
function "=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?= to_ufixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?/= to_ufixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?>= to_ufixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?<= to_ufixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?> to_ufixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?< to_ufixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- real and ufixed
function "=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_ufixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with integer
function "=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?= to_sfixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?/= to_sfixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?>= to_sfixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?<= to_sfixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?> to_sfixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return (l ?< to_sfixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- integer and sfixed
function "=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with real
function "=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function "?=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?= to_sfixed (r, l'high, l'low));
end function "?=";
function "?/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?/= to_sfixed (r, l'high, l'low));
end function "?/=";
function "?>=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?>= to_sfixed (r, l'high, l'low));
end function "?>=";
function "?<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?<= to_sfixed (r, l'high, l'low));
end function "?<=";
function "?>" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?> to_sfixed (r, l'high, l'low));
end function "?>";
function "?<" (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return (l ?< to_sfixed (r, l'high, l'low));
end function "?<";
function maximum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- REAL and sfixed
function "=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function "?=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?= r);
end function "?=";
function "?/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?/= r);
end function "?/=";
function "?>=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?>= r);
end function "?>=";
function "?<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?<= r);
end function "?<=";
function "?>" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?> r);
end function "?>";
function "?<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return (to_sfixed (l, r'high, r'low) ?< r);
end function "?<";
function maximum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
c := l (l'left);
if (c = ' ' or c = NBSP or c = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : ufixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_generic_pkg'instance_name & "READ(ufixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : ufixed (VALUE'range);
variable i : INTEGER; -- index variable
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := value'high;
GOOD := false;
while i >= VALUE'low loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
return;
elsif i /= -1 then -- Seperator in the wrong spot
return;
end if;
founddot := true;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then -- reading done
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : sfixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_generic_pkg'instance_name & "READ(sfixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
begin -- READ
READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
VALUE := UNRESOLVED_sfixed (value_ufixed);
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_generic_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- purpose: Routines common to the OREAD routines
procedure OREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_generic_pkg'instance_name
& "OREAD(sfixed) "
& mess
severity error;
else
report fixed_generic_pkg'instance_name
& "OREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2triBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-2) := nybble;
i := i - 3;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
igood := true; -- read into a null array
idex := -1;
end if;
end procedure OREAD_common;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD (L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_generic_pkg'instance_name
& "OREAD(ufixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "OREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_generic_pkg'instance_name
& "OREAD(sfixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "OREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_generic_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
-- purpose: Routines common to the HREAD routines
procedure HREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_generic_pkg'instance_name
& "HREAD(sfixed) "
& mess
severity error;
else
report fixed_generic_pkg'instance_name
& "HREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2QuadBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-3) := nybble;
i := i - 4;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
idex := -1;
igood := true; -- read null string
end if;
end procedure HREAD_common;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if igood then
if not ((i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_generic_pkg'instance_name
& "HREAD(ufixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "HREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_generic_pkg'instance_name
& "HREAD(sfixed): Vector truncated."
severity error;
else
if (or (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_generic_pkg'instance_name
& "HREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
-- To_string functions. Useful in "report" statements.
-- Example: report "result was " & to_string(result);
function to_string (value : UNRESOLVED_ufixed) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable subval : UNRESOLVED_ufixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_string (resize (sfixed(value), 0, value'low));
else
return to_string (resize (value, 0, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_string (value : UNRESOLVED_sfixed) return STRING is
variable s : STRING(1 to value'length + 1) := (others => ' ');
variable subval : UNRESOLVED_sfixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_ostring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_ufixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_ostring (resize (sfixed(value), 2, value'low));
else
return to_ostring (resize (value, 2, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value (value'low));
else
lpad := (others => '0');
end if;
return to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_ufixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_hstring (resize (sfixed(value), 3, value'low));
else
return to_hstring (resize (value, 3, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad);
end if;
end if;
end function to_hstring;
function to_ostring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_sfixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
pad := (others => value(value'high));
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_sfixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
pad := (others => value(value'high));
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed
is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed
is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_generic_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_hstring(hstring, size_res'high, size_res'low);
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_hstring (hstring, size_res'high, size_res'low);
end function from_hstring;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
-- purpose: Calculate the string boundaries
procedure calculate_string_boundry (
arg : in STRING; -- input string
left_index : out INTEGER; -- left
right_index : out INTEGER) is -- right
-- examples "10001.111" would return +4, -3
-- "07X.44" would return +2, -2 (then the octal routine would multiply)
-- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range
variable l, r : INTEGER; -- internal indexes
variable founddot : BOOLEAN := false;
begin
if arg'length > 0 then
l := xarg'high - 1;
r := 0;
for i in xarg'range loop
if xarg(i) = '_' then
if r = 0 then
l := l - 1;
else
r := r + 1;
end if;
elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
report fixed_generic_pkg'instance_name
& "Found a space in the input STRING " & xarg
severity error;
elsif xarg(i) = '.' then
if founddot then
report fixed_generic_pkg'instance_name
& "Found two binary points in input string " & xarg
severity error;
else
l := l - i;
r := -i + 1;
founddot := true;
end if;
end if;
end loop;
left_index := l;
right_index := r;
else
left_index := 0;
right_index := 0;
end if;
end procedure calculate_string_boundry;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed
is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
end package body fixed_generic_pkg;
|
gpl-2.0
|
1b70e20eb8f0293315e5a11d50e2093a
| 0.563676 | 3.980395 | false | false | false | false |
123gmax/Digital-Lab
|
Lab1/final_design/counter/tb_counter.vhd
| 2 | 2,008 |
library ieee;
use ieee.std_logic_1164.all;
entity tb_counter is
end tb_counter;
architecture beh of tb_counter is
component counter
Port (
UP: in std_logic;
AUTO: in std_logic;
LOAD: in std_logic;
VALUE: in std_logic_vector(3 downto 0);
TICK: in std_logic;
COUNT: out std_logic_vector(3 downto 0);
RESET: in std_logic;
clk: in std_logic
);
end component;
signal up_in,auto_in,load_in,tick_in,reset_in,clk_in : std_logic;
signal value_in,count_out : std_logic_vector(3 downto 0);
constant clock_period : time:= 10 ns;
constant period_1sec : time:= 50 ns;
begin
uut:counter
port map(UP=>up_in,AUTO=>auto_in,LOAD=>load_in,VALUE=>value_in,TICK=>tick_in,COUNT=>count_out,RESET=>reset_in,clk=>clk_in);
clock_process:process
begin
clk_in <= '0';
wait for clock_period/2;
clk_in <= not clk_in;
wait for clock_period/2;
end process;
test_bench:process
begin
reset_in <= '1';
up_in <= '0';
auto_in <='0';
load_in <='0';
value_in <="0000";
tick_in <= '0';
wait for 10*clock_period;
reset_in <= '0';
wait for period_1sec;
value_in <= "1010";
load_in <= '1';
up_in <= '1'; --Up counter
auto_in <='1'; --Auto count
wait for period_1sec + 5 ns;
load_in <='0';
wait for 10*period_1sec;
up_in <= '0';--Down count
wait for 10*period_1sec;
auto_in <='0';--Manual mode
wait for period_1sec;
tick_in <= not tick_in;--1
wait for 2*period_1sec;
tick_in <= not tick_in;--0
wait for period_1sec*3;
tick_in <= not tick_in;--1
wait for period_1sec;
auto_in <= '1';--Auto mode
up_in <= '1'; -- Up count
wait;
end process;
end beh;
|
gpl-2.0
|
c0a336ee1112c4f51e05b108aab2a730
| 0.508466 | 3.438356 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_07.vhd
| 4 | 2,461 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity fg_16_07 is
end entity fg_16_07;
architecture test of fg_16_07 is
constant reg0 : std_logic_vector(7 downto 0) := "00000000";
constant reg1 : std_logic_vector(7 downto 0) := "11111111";
signal dbus : std_logic_vector(7 downto 0);
signal reg_sel, read, reg_addr : X01 := '0';
begin
-- code from book
reg_read_selector : block (reg_sel = '1' and read = '1') is
begin
dbus <= reg0 when guard and reg_addr = '0' else
reg1 when guard and reg_addr = '1' else
"ZZZZZZZZ";
end block reg_read_selector;
-- end code from book
stimulus : process is
begin
reg_sel <= '1'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
reg_sel <= '0'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
reg_addr <= '1'; wait for 10 ns;
reg_sel <= '1'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
8f38dafc8c72fbec7a3dfe8beb0c087b
| 0.506298 | 4.340388 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_07.vhd
| 4 | 1,831 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_07 is
end entity inline_07;
----------------------------------------------------------------
architecture test of inline_07 is
begin
process_2_b : process is
-- code from book:
subtype index_mode is integer range 0 to 3;
variable instruction_register : integer range 0 to 2**16 - 1;
-- end of code from book
variable index_value : integer;
constant accumulator_A : integer := 1;
constant accumulator_B : integer := 2;
constant index_register : integer := 3;
begin
for i in index_mode loop
instruction_register := i * 2**12;
-- code from book:
case index_mode'((instruction_register / 2**12) rem 2**2) is
when 0 =>
index_value := 0;
when 1 =>
index_value := accumulator_A;
when 2 =>
index_value := accumulator_B;
when 3 =>
index_value := index_register;
end case;
-- end of code from book
end loop;
wait;
end process process_2_b;
end architecture test;
|
gpl-2.0
|
ef1c3bcf1419b23549b1023b2a3a7957
| 0.63681 | 4.238426 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc938.vhd
| 4 | 2,108 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc938.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s04b00x00p07n01i00938pkg is
type color is ( red, white, green, blue );
constant x : color := green;
end c10s04b00x00p07n01i00938pkg;
ENTITY c10s04b00x00p07n01i00938ent IS
END c10s04b00x00p07n01i00938ent;
ARCHITECTURE c10s04b00x00p07n01i00938arch OF c10s04b00x00p07n01i00938ent IS
type rgb is ( red, green, blue );
constant x : rgb := red; -- homograph of x
use work.c10s04b00x00p07n01i00938pkg.all;
procedure xxx is
begin
-- takes the local x
assert (x = red) report "x /= red" severity FAILURE;
assert NOT( x=red )
report "***PASSED TEST: c10s04b00x00p07n01i00938"
severity NOTE;
assert ( x=red )
report "***FAILED TEST: c10s04b00x00p07n01i00938 - A oitentially visible declaration is made visible within the immediate scope of a homograph if the declaration is an enumeration literal."
severity ERROR;
end xxx;
BEGIN
xxx;
END c10s04b00x00p07n01i00938arch;
|
gpl-2.0
|
c9fdf2038a50975b4efdd9cedd71f6e8
| 0.683112 | 3.585034 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Guerric/Modular/celda_v.vhd
| 1 | 1,535 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_v is
generic(
NUM_BITS : positive := 163
);
port(
U : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
P : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
Y2 : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c_1 : in STD_LOGIC;
c_2 : in STD_LOGIC;
en : in STD_LOGIC;
clk : in STD_LOGIC;
V : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_v is
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
Celda_s_process: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if en = '1' then
if c_1 = '0' and c_2 = '0' then
V <= Y2;
elsif c_1 = '0' and c_2 = '1' then
V <= P;
else
V <= U;
end if;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
116520d0f60b97409c4bb10b9465956d
| 0.334202 | 4.360795 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd
| 4 | 1,610 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
entity tb_control_system is
end tb_control_system;
architecture TB_control_system of tb_control_system is
-- Component declarations
-- Signal declarations
quantity in_src, fb : real;
quantity output : real;
begin
-- Signal assignments
-- Component instances
src3 : entity work.src_sine(ideal)
generic map(
freq => 100.0,
amplitude => 1.0
)
port map(
output => in_src
);
XCMP12 : entity work.control_system(simple_feedback)
port map(
target => in_src,
output => output,
feedback => fb
);
gain1 : entity work.gain(simple)
generic map(
k => 1.0
)
port map (
input => output,
output => fb
);
end TB_control_system;
|
gpl-2.0
|
60d1d69cd78fce846b79a0e0859f2aa8
| 0.652795 | 4.138817 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2431.vhd
| 4 | 1,726 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2431.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02431ent IS
END c07s03b02x02p01n01i02431ent;
ARCHITECTURE c07s03b02x02p01n01i02431arch OF c07s03b02x02p01n01i02431ent IS
BEGIN
TESTING: PROCESS
type array_three is array (1 to 6) of integer;
variable x : array_three := (1=>2,2=>3,3=>4,4=>6.32,5=>6,6=>7); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02431 - Expression of each element association must be of the element type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02431arch;
|
gpl-2.0
|
75b848885a6e2fa25dcd8f0cdbfaab26
| 0.672074 | 3.62605 | false | true | false | false |
123gmax/Digital-Lab
|
Lab1/Alex/AirTrafficControl/tb_air_traffic_control.vhd
| 1 | 2,901 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/06/2015 11:59:17 AM
-- Design Name:
-- Module Name: tb_air_traffic_control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_air_traffic_control is
end tb_air_traffic_control;
architecture Behavioral of tb_air_traffic_control is
signal PLANE_TYPE : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal REQ, CLK, GRANTED, DENIED : STD_LOGIC := '0';
component air_traffic_control is
Port ( PLANE_TYPE : in STD_LOGIC_VECTOR (2 downto 0);
REQ : in STD_LOGIC;
CLK : in STD_LOGIC;
GRANTED : out STD_LOGIC;
DENIED : out STD_LOGIC);
end component;
constant clk_period : time :=2ns;
begin
uut: air_traffic_control PORT MAP(
PLANE_TYPE => PLANE_TYPE,
REQ => REQ,
CLK => CLK,
GRANTED => GRANTED,
DENIED => DENIED
);
clk_process: process
begin
CLK <= NOT CLK;
wait for clk_period/2;
end process;
stimulus: process
begin
--Light jet Request
PLANE_TYPE <= "000";
REQ <= '1';
wait for 10ns;
REQ <= '0';
wait for 10ns;
--Heavy Jet Request during take-off
PLANE_TYPE <= "001";
REQ <= '1';
wait for 10ns;
REQ <= '0';
wait for 10ns;
--Wait for take-off to complete
wait for 60ns;
--Repeat Heavy request
REQ <= '1';
wait for 10ns;
REQ <= '0';
wait for 10ns;
--Wait for take-off to complete
wait for 60ns;
--Light jet Request
PLANE_TYPE <= "010";
REQ <= '1';
wait for 10ns;
REQ <= '0';
wait for 10ns;
--Wait for DENY to complete
wait for 60ns;
--Heavy Jet Request
PLANE_TYPE <= "011";
REQ <= '1';
wait for 10ns;
REQ <= '0';
wait for 10ns;
--Wait for Turbulence to clear
wait for 200ns;
--Light jet Request
PLANE_TYPE <= "100";
REQ <= '1';
wait for 10ns;
REQ <= '0';
wait for 10ns;
wait;
end process;
end Behavioral;
|
gpl-2.0
|
2dd533b53044500c228c5a6b488f1840
| 0.506722 | 4.057343 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_15.vhd
| 4 | 1,978 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_15.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package cell_attributes is
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
attribute cell_position : coordinate;
end package cell_attributes;
entity CPU is
end entity CPU;
-- code from book
architecture cell_based of CPU is
component fpu is
port ( -- . . . );
-- not in book
port_name : bit := '0' );
-- end not in book
end component;
use work.cell_attributes.all;
attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
-- . . .
begin
the_fpu : component fpu
port map ( -- . . . );
-- not in book
port_name => open );
-- end not in book
-- . . .
end architecture cell_based;
-- end code from book
|
gpl-2.0
|
24ceba02960f3cf8977b1d9612b4dbc0
| 0.577856 | 4.208511 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/disputed/tc1158.vhd
| 4 | 2,189 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1158.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s06b00x00p02n01i01158pkg is
type I1 is range 1 to 5;
subtype I11 is I1 range 2 to 4;
type A1 is array (I1 range 2 to 4) of BOOLEAN;
end c06s06b00x00p02n01i01158pkg;
use work.c06s06b00x00p02n01i01158pkg.all;
ENTITY c06s06b00x00p02n01i01158ent IS
generic (V_all : A1 := (true,false,true));
port (PT: BOOLEAN);
END c06s06b00x00p02n01i01158ent;
ARCHITECTURE c06s06b00x00p02n01i01158arch OF c06s06b00x00p02n01i01158ent IS
BEGIN
TESTING: PROCESS
variable V : boolean;
attribute AT1 : A1;
attribute AT1 of V : variable is V_all;
variable k : integer := 0;
BEGIN
if I11'BASE'Left = 1 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01158"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01158 - The prefix of an attribute name may be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01158arch;
|
gpl-2.0
|
64a4a485af80c2aac2b422847cb060a4
| 0.660576 | 3.409657 | false | true | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/datapath.vhd
| 1 | 2,346 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity datapath is
port (a,b: in std_logic_vector(31 downto 0);
clk,rst: in std_logic;
en: in std_logic_vector(1 downto 0);
c: out std_logic_vector(31 downto 0);
done,m47: out std_logic
);
end datapath;
architecture arch_datapath_1 of datapath is
component reg is
port (clk,en,rst: in std_logic;
a:in std_logic_vector((31) downto 0);
r: out std_logic_vector((31) downto 0)
);
end component;
component mul_int1 is
port (in1: in std_logic_vector(23 downto 0);
in2: in std_logic_vector(23 downto 0);
clk,rst: in std_logic;
done:out std_logic;
res: out std_logic_vector(47 downto 0):=(others=>'0')
);
end component;
component extractor is
port (
ext_in:in std_logic_vector(47 downto 0 );
ext_out:out std_logic_vector(22 downto 0 )
);
end component;
signal rra,rrb: std_logic_vector(31 downto 0);
alias signa: std_logic is rra(31);
alias signb: std_logic is rrb(31);
alias expa: std_logic_vector(7 downto 0) is rra(30 downto 23);
alias expb: std_logic_vector(7 downto 0) is rrb(30 downto 23);
alias manta: std_logic_vector(22 downto 0) is rra(22 downto 0);
alias mantb: std_logic_vector(22 downto 0) is rrb(22 downto 0);
signal mana,manb: std_logic_vector(23 downto 0);
signal done_mul: std_logic;
signal mul_out: std_logic_vector(47 downto 0);
signal ext_out: std_logic_vector(22 downto 0);
signal signf: std_logic;
signal expf:std_logic_vector(7 downto 0):=(others=>'0');
signal expg:std_logic_vector(7 downto 0):=(others=>'0');
signal exph:std_logic_vector(7 downto 0):=(others=>'0');
signal ric: std_logic_vector(31 downto 0);
begin
mana<='1' & manta;
manb<='1' & mantb;
rega: reg port map(clk=>clk,en=>en(0),rst=>rst,a=>a,r=>rra);
regb: reg port map(clk=>clk,en=>en(0),rst=>rst,a=>b,r=>rrb);
mult: mul_int1 port map(in1=>mana,in2=>manb,clk=>clk,rst=>rst,done=>done_mul,res=>mul_out);
ext: extractor port map(ext_in=>mul_out,ext_out=>ext_out);
signf<=signa xor signb;
expg<=std_logic_vector(expa+expb);
exph<=std_logic_vector(expg)-"01111111";
expf<=exph+("0000000" & mul_out(47));
ric<=signf & expf & ext_out;
regc: reg port map(clk=>clk,en=>en(1),rst=>rst,a=>ric,r=>c);
done<=done_mul;
m47<=mul_out(47);
end arch_datapath_1;
|
mit
|
7a5abc3c55691d31c7673885af67f2de
| 0.664535 | 2.665909 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_02.vhd
| 4 | 1,882 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_tb_01_02.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_01_02 is
end entity test_bench_01_02;
architecture test_reg4_struct of test_bench_01_02 is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(struct)
port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
stimulus : process is
begin
wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1010"); wait for 20 ns;
en <= '1'; wait for 20 ns;
clk <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0101"); wait for 20 ns;
clk <= '0'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0000"); wait for 20 ns;
en <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1111"); wait for 20 ns;
wait;
end process stimulus;
end architecture test_reg4_struct;
|
gpl-2.0
|
e7afca9821a33bab783ba8da1f67b980
| 0.585547 | 3.250432 | false | true | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.a-Alu.core/a.b.a.b-Shifter.vhd
| 1 | 2,119 |
--------------------------------------------------------------------------------
-- FILE: Shifter
-- DESC: Shift A by B bits
--
-- Author:
-- Create: 2015-05-25
-- Update: 2015-05-27
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Shifter is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
l_r : in std_logic; -- LEFT/RIGHT
l_a : in std_logic; -- LOGIC/ARITHMETIC
s_r : in std_logic; -- SHIFT/ROTATE
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
o : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0')
);
end Shifter;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture shifter_arch of Shifter is
constant B_SIZE : integer := MyLog2Ceil(DATA_SIZE);
begin
P0: process (a, b, l_r, l_a, s_r) is
begin
if s_r = '1' then
if l_r = '1' then
o <= to_StdLogicVector((to_bitvector(a)) ror (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
else
o <= to_StdLogicVector((to_bitvector(a)) rol (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
end if;
else
if l_r = '1' then
if l_a = '1' then
o <= to_StdLogicVector((to_bitvector(a)) sra (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
else
o <= to_StdLogicVector((to_bitvector(a)) srl (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
end if;
else
if l_a = '1' then
o <= to_StdLogicVector((to_bitvector(a)) sla (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
else
o <= to_StdLogicVector((to_bitvector(a)) sll (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
end if;
end if;
end if;
end process;
end shifter_arch;
|
mit
|
a41f3d25eea4bbdc6e98734d4f218ed6
| 0.483247 | 3.45114 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1366.vhd
| 4 | 6,566 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1366.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01366ent IS
END c08s05b00x00p03n01i01366ent;
ARCHITECTURE c08s05b00x00p03n01i01366arch OF c08s05b00x00p03n01i01366ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
--
BEGIN
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***PASSED TEST: c08s05b00x00p03n01i01366"
severity NOTE;
assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***FAILED TEST: c08s05b00x00p03n01i01366 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01366arch;
|
gpl-2.0
|
ca51ad0dc99d5bc34506ac35802db3ac
| 0.58346 | 2.93387 | false | false | false | false |
stnolting/neo430
|
rtl/fpga_specific/lattice_ice40up/neo430_imem.ice40up_spram.vhd
| 1 | 10,935 |
-- #################################################################################################
-- # << NEO430 - Instruction memory ("IMEM") for Lattice ice40 UltraPlus >> #
-- # ********************************************************************************************* #
-- # This memory includes the in-place executable image of the application. See the #
-- # processor's documentary to get more information. #
-- # Note: IMEM is split up into two 8-bit memories - some EDA tools have problems to synthesize #
-- # a pre-initialized 16-bit memory with byte-enable signals. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
use neo430.neo430_application_image.all; -- this file is generated by the image generator
library iCE40UP;
use iCE40UP.components.all;
entity neo430_imem is
generic (
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory?
BOOTLD_USE : boolean := true -- implement and use bootloader?
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic_vector(01 downto 0); -- write enable
upen_i : in std_ulogic; -- update enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_imem;
architecture neo430_imem_rtl of neo430_imem is
-- advanced configuration ------------------------------------------------------------------------------------
constant spram_sleep_mode_en_c : boolean := false; -- put IMEM into sleep mode when idle (for low power)
-- -------------------------------------------------------------------------------------------------------
-- ROM types --
type imem_file8_t is array (0 to IMEM_SIZE/2-1) of std_ulogic_vector(07 downto 0);
-- init function and split 1x16-bit memory into 2x8-bit memories --
impure function init_imem(hilo : std_ulogic; init : application_init_image_t) return imem_file8_t is
variable mem_v : imem_file8_t;
begin
for i in 0 to IMEM_SIZE/2-1 loop
if (hilo = '0') then -- low byte
mem_v(i) := init(i)(07 downto 00);
else -- high byte
mem_v(i) := init(i)(15 downto 08);
end if;
end loop; -- i
return mem_v;
end function init_imem;
-- local signals --
signal acc_en : std_ulogic;
signal mem_cs : std_ulogic;
signal rdata : std_ulogic_vector(15 downto 0);
signal rden : std_ulogic;
signal mem_sel : std_ulogic;
signal addr : integer;
-- internal "RAM" type - implemented if bootloader is used and IMEM is RAM and initialized with app code --
signal imem_file_init_ram_l : imem_file8_t := init_imem('0', application_init_image);
signal imem_file_init_ram_h : imem_file8_t := init_imem('1', application_init_image);
-- internal "ROM" type - implemented if bootloader is NOT used; always initialize with app code --
constant imem_file_rom_l : imem_file8_t := init_imem('0', application_init_image);
constant imem_file_rom_h : imem_file8_t := init_imem('1', application_init_image);
-- internal "RAM" type - implemented if bootloader is used and IMEM is RAM --
signal imem_file_ram_l : imem_file8_t;
signal imem_file_ram_h : imem_file8_t;
-- RAM attribute to inhibit bypass-logic - Intel only! --
attribute ramstyle : string;
attribute ramstyle of imem_file_init_ram_l : signal is "no_rw_check";
attribute ramstyle of imem_file_init_ram_h : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_l : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_h : signal is "no_rw_check";
-- RAM attribute to inhibit bypass-logic - Lattice only! --
attribute syn_ramstyle : string;
attribute syn_ramstyle of imem_file_init_ram_l : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_init_ram_h : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_ram_l : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_ram_h : signal is "no_rw_check";
-- SPRAM signals --
signal spram_clk : std_logic;
signal spram_addr : std_logic_vector(13 downto 0);
signal spram_di : std_logic_vector(15 downto 0);
signal spram_do_lo : std_logic_vector(15 downto 0);
signal spram_do_hi : std_logic_vector(15 downto 0);
signal spram_be : std_logic_vector(03 downto 0);
signal spram_we : std_logic;
signal spram_pwr_n : std_logic;
signal spram_cs : std_logic_vector(01 downto 0);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i >= imem_base_c) and (addr_i < std_ulogic_vector(unsigned(imem_base_c) + IMEM_SIZE)) else '0';
addr <= to_integer(unsigned(addr_i(index_size_f(IMEM_SIZE/2) downto 1))); -- word aligned
mem_cs <= acc_en and (rden_i or wren_i(1) or wren_i(0));
-- Memory Access ------------------------------------------------------------
-- -----------------------------------------------------------------------------
imem_spram_lo_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di, -- I
MASKWE => spram_be, -- I
WE => spram_we, -- I
CS => spram_cs(0), -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_lo -- O
);
-- instantiate second SPRAM if IMEM size > 32kB --
imem_spram_hi_bank:
if (IMEM_SIZE > 32*1024) generate
imem_spram_hi_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di, -- I
MASKWE => spram_be, -- I
WE => spram_we, -- I
CS => spram_cs(1), -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_hi -- O
);
end generate;
-- access logic and signal type conversion --
spram_clk <= std_logic(clk_i);
spram_addr <= std_logic_vector(addr_i(13+1 downto 0+1));
spram_di <= std_logic_vector(data_i(15 downto 0));
spram_we <= '1' when ((acc_en and upen_i and (wren_i(0) or wren_i(1))) = '1') else '0'; -- global write enable
rdata <= std_ulogic_vector(spram_do_lo) when (mem_sel = '0') else std_ulogic_vector(spram_do_hi); -- lo/hi memory bank
spram_cs(0) <= '1' when (addr_i(15) = '0') else '0'; -- low memory bank
spram_cs(1) <= '1' when (addr_i(15) = '1') else '0'; -- high memory bank
spram_be(1 downto 0) <= "11" when (wren_i(0) = '1') else "00"; -- low byte write enable
spram_be(3 downto 2) <= "11" when (wren_i(1) = '1') else "00"; -- high byte write enable
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
buffer_ff: process(clk_i)
begin
-- sanity check --
if (IMEM_AS_ROM = true) or (BOOTLD_USE = false) then
assert false report "ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity error;
end if;
if (IMEM_SIZE > 48*1024) then
assert false report "I-mem size out of range! Max 48kB!" severity error;
end if;
-- buffer --
if rising_edge(clk_i) then
mem_sel <= addr_i(15);
rden <= rden_i and acc_en;
end if;
end process buffer_ff;
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
end neo430_imem_rtl;
|
bsd-3-clause
|
fc459a5a5fd39645c891a24237c3ebbe
| 0.515684 | 4.083271 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_07.vhd
| 4 | 2,796 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_07 is
end entity ch_05_07;
----------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture test of ch_05_07 is
signal clk, d : std_ulogic;
constant Tpw_clk : delay_length := 10 ns;
constant Tsu : delay_length := 4 ns;
begin
process_05_3_c : process (clk, d) is
begin
-- code from book:
if clk'event and (clk = '1' or clk = 'H')
and (clk'last_value = '0' or clk'last_value = 'L')
then
assert d'last_event >= Tsu
report "Timing error: d changed within setup time of clk";
end if;
-- end of code from book
end process process_05_3_c;
----------------
process_05_3_d : process (clk, d) is
begin
-- code from book:
assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
report "Clock frequency too high";
-- end of code from book
end process process_05_3_d;
----------------
process_05_3_e : process is
begin
-- code from book:
wait until clk = '1';
-- end of code from book
report "clk changed to '1'";
end process process_05_3_e;
----------------
stimulus_05_3_c_d : process is
begin
clk <= '1' after 15 ns,
'0' after 30 ns,
'1' after 40 ns,
'0' after 50 ns,
'H' after 60 ns,
'0' after 70 ns,
'1' after 80 ns,
'L' after 90 ns,
'H' after 100 ns,
'L' after 120 ns,
'1' after 125 ns, -- should cause error
'0' after 130 ns; -- should cause error
d <= '1' after 35 ns,
'0' after 77 ns, -- should cause error
'1' after 102 ns;
wait;
end process stimulus_05_3_c_d;
end architecture test;
|
gpl-2.0
|
3dd2dcac55bb0ad0fe5e9bc8f1055fa9
| 0.553648 | 3.728 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca-b.vhd
| 4 | 1,723 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_acca-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of accumulator_adder is
begin
behavior : process (a, b) is
constant Tpd_in_out : time := 3 ns;
variable carry_in : std_ulogic;
variable carry_out : std_ulogic := '0';
begin
for index in 0 to 21 loop
carry_in := carry_out; -- of previous bit
s(index) <= a(index) xor b(index) xor carry_in after Tpd_in_out;
carry_out := (a(index) and b(index))
or (carry_in and (a(index) xor b(index)));
end loop;
ovf <= carry_out xor carry_in after Tpd_in_out; -- ovf is carry_out /= carry_in
end process behavior;
end architecture behavioral;
|
gpl-2.0
|
ea8597276441d35498946bffa10a3ace
| 0.596053 | 4.102381 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1318.vhd
| 4 | 1,976 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1318.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p07n01i01318ent IS
END c08s04b00x00p07n01i01318ent;
ARCHITECTURE c08s04b00x00p07n01i01318arch OF c08s04b00x00p07n01i01318ent IS
signal s1, s2 : CHARACTER := NUL;
BEGIN
TESTING: PROCESS
type AT is array (INTEGER range <>) of CHARACTER;
variable av : AT(0 to 1) := ('1', '2');
BEGIN
assert s1 = NUL;
assert s2 = NUL;
(s1, s2) <= av;
wait on s1;
assert s1 = '1';
assert s2 = '2';
assert NOT( s1 = '1' and s2 = '2' )
report "***PASSED TEST: c08s04b00x00p07n01i01318"
severity NOTE;
assert ( s1 = '1' and s2 = '2' )
report "***FAILED TEST: c08s04b00x00p07n01i01318 - Aggregate (array type) signal assignment test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p07n01i01318arch;
|
gpl-2.0
|
a1394d9a5e20188d9164caa8e56e3a51
| 0.644737 | 3.534884 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/ticket29/debugtools.vhdl
| 3 | 2,422 |
library ieee;
use Std.TextIO.all;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package debugtools is
function to_string(sv: Std_Logic_Vector) return string;
function to_hstring(sv: Std_Logic_Vector) return string;
function to_hstring(sv: unsigned) return string;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
end debugtools;
package body debugtools is
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
function to_string(sv: Std_Logic_Vector) return string is
use Std.TextIO.all;
variable bv: bit_vector(sv'range) := to_bitvector(sv);
variable lp: line;
begin
write(lp, bv);
return lp.all;
end;
function to_hstring(sv: Std_Logic_Vector) return string is
use Std.TextIO.all;
variable bv: bit_vector(sv'range) := to_bitvector(sv);
variable lp: line;
begin
hwrite(lp, bv);
return lp.all;
end;
function to_hstring(sv: unsigned) return string is
use Std.TextIO.all;
begin
return to_hstring(std_logic_vector(sv));
end;
end debugtools;
|
gpl-2.0
|
b423765f0182eefd279925a4b38d2542
| 0.521883 | 3.137306 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1945.vhd
| 4 | 16,582 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1945.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01945pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- ----------------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01945pkg.all;
ENTITY c07s02b01x00p01n02i01945ent IS
END c07s02b01x00p01n02i01945ent;
ARCHITECTURE c07s02b01x00p01n02i01945arch OF c07s02b01x00p01n02i01945ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
--
-- Test AND operator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01945"
severity NOTE;
assert ( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01945 - Logical operator AND for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01945arch;
|
gpl-2.0
|
b8189b3f0ef4a45d62ca67951de7c532
| 0.545169 | 2.617109 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_12.vhd
| 4 | 1,700 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_05_12 is
end entity fg_05_12;
architecture test of fg_05_12 is
signal a, z : bit;
begin
-- code from book
asym_delay : process (a) is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
begin
if a = '1' then
z <= transport a after Tpd_01;
else -- a = '0'
z <= transport a after Tpd_10;
end if;
end process asym_delay;
-- end code from book
stimulus : process is
begin
a <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
53b2083459557fc67bc3d920080e6f9e
| 0.586471 | 3.981265 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_02.vhd
| 4 | 2,154 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_a_02 is
end entity fg_a_02;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_02 is
signal clk, a, b : std_ulogic;
begin
stimulus : process is
begin
clk <= '0'; a <= '0'; b <= '0'; wait for 10 ns;
clk <= '1', '0' after 10 ns; wait for 20 ns;
b <= '1'; wait for 10 ns;
clk <= '1', '0' after 20 ns; a <= '0' after 10 ns;
wait;
end process stimulus;
b1 : block is
signal q : std_ulogic;
begin
-- code from book
process (clk) is
variable d : std_ulogic;
begin
if a = b then
d := '1';
else
d := '0';
end if;
if rising_edge(clk) then
q <= d;
end if;
end process;
-- end code from book
end block b1;
b2 : block is
signal q : std_ulogic;
begin
-- code from book
process (clk) is
begin
if rising_edge(clk) then
if a = b then
q <= '1';
else
q <= '0';
end if;
end if;
end process;
-- end code from book
end block b2;
end architecture test;
|
gpl-2.0
|
8371eaf3c989a2a8cc42fde41724b65d
| 0.552461 | 3.733102 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1761.vhd
| 4 | 2,128 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1761.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b01x00p21n01i01761ent IS
END c09s05b01x00p21n01i01761ent;
ARCHITECTURE c09s05b01x00p21n01i01761arch OF c09s05b01x00p21n01i01761ent IS
signal TS1,TS2 : integer;
signal B,C : integer;
signal D,E,F : bit;
BEGIN
TS1 <= transport 1 after 10 ns when B = C else
2 after 10 ns when B > C else
3 after 10 ns;
TS2 <= transport 4-1 after 10 ns when D = '1' else
5+1 after 10 ns when E = '1' else
6*2 after 10 ns when F = '1' else
8/2 after 10 ns;
TESTING: PROCESS(TS1,TS2)
BEGIN
if ( now > 1 ns) then
assert NOT(TS1=1 and TS2=4)
report "***PASSED TEST: c09s05b01x00p21n01i01761"
severity NOTE;
assert (TS1=1 and TS2=4)
report "***FAILED TEST: c09s05b01x00p21n01i01761 - Conditions in the conditional signal assignment statement should be valid."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s05b01x00p21n01i01761arch;
|
gpl-2.0
|
42723c6fb909e9aeac2366acf7c6ce84
| 0.648966 | 3.540765 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Squarer/squarer_113.vhd
| 1 | 4,608 |
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2007.
--Squarer, solo logica combinacional,
--optimizado para el polinomio de reduccion que se este empleando,
-- funciona solo si el máximo grado del polinomio de reduccion D más 2 es menor a m.
-- Se trata básicamente de un multiplicador de digito combinacional. El tamaño del digito es D+2;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-----------------------------------------------------------------------------------
entity squarer_113 is
generic(
NUM_BITS : positive := 113 --113 163, 233, 277, 283, 409, 571 -- Orden del campo finito
);
port(
-- clk : in std_logic;
-- en : in std_logic;
A_x : in std_logic_vector(NUM_BITS-1 downto 0);-- 2
A2_x : out std_logic_vector(NUM_BITS-1 downto 0)-- A2_x = (A_x) mod Fx
);
end;
---------------------------------------------------------------------------------------------------
architecture behave of squarer_113 is
begin
A2_x(112) <= A_x(56) xor A_x(108);
A2_x(111) <= A_x(112);
A2_x(110) <= A_x(55) xor A_x(107);
A2_x(109) <= A_x(111);
A2_x(108) <= A_x(54) xor A_x(106);
A2_x(107) <= A_x(110);
A2_x(106) <= A_x(53) xor A_x(105);
A2_x(105) <= A_x(109);
A2_x(104) <= A_x(52) xor A_x(104);
A2_x(103) <= A_x(108);
A2_x(102) <= A_x(51) xor A_x(103);
A2_x(101) <= A_x(107);
A2_x(100) <= A_x(50) xor A_x(102);
A2_x(99) <= A_x(106);
A2_x(98) <= A_x(49) xor A_x(101);
A2_x(97) <= A_x(105);
A2_x(96) <= A_x(48) xor A_x(100);
A2_x(95) <= A_x(104);
A2_x(94) <= A_x(47) xor A_x(99);
A2_x(93) <= A_x(103);
A2_x(92) <= A_x(46) xor A_x(98);
A2_x(91) <= A_x(102);
A2_x(90) <= A_x(45) xor A_x(97);
A2_x(89) <= A_x(101);
A2_x(88) <= A_x(44) xor A_x(96);
A2_x(87) <= A_x(100);
A2_x(86) <= A_x(43) xor A_x(95);
A2_x(85) <= A_x(99);
A2_x(84) <= A_x(42) xor A_x(94);
A2_x(83) <= A_x(98);
A2_x(82) <= A_x(41) xor A_x(93);
A2_x(81) <= A_x(97);
A2_x(80) <= A_x(40) xor A_x(92);
A2_x(79) <= A_x(96);
A2_x(78) <= A_x(39) xor A_x(91);
A2_x(77) <= A_x(95);
A2_x(76) <= A_x(38) xor A_x(90);
A2_x(75) <= A_x(94);
A2_x(74) <= A_x(37) xor A_x(89);
A2_x(73) <= A_x(93);
A2_x(72) <= A_x(36) xor A_x(88);
A2_x(71) <= A_x(92);
A2_x(70) <= A_x(35) xor A_x(87);
A2_x(69) <= A_x(91);
A2_x(68) <= A_x(34) xor A_x(86);
A2_x(67) <= A_x(90);
A2_x(66) <= A_x(33) xor A_x(85);
A2_x(65) <= A_x(89);
A2_x(64) <= A_x(32) xor A_x(84);
A2_x(63) <= A_x(88);
A2_x(62) <= A_x(31) xor A_x(83);
A2_x(61) <= A_x(87);
A2_x(60) <= A_x(30) xor A_x(82);
A2_x(59) <= A_x(86);
A2_x(58) <= A_x(29) xor A_x(81);
A2_x(57) <= A_x(85);
A2_x(56) <= A_x(28) xor A_x(80);
A2_x(55) <= A_x(84);
A2_x(54) <= A_x(27) xor A_x(79);
A2_x(53) <= A_x(83);
A2_x(52) <= A_x(26) xor A_x(78);
A2_x(51) <= A_x(82);
A2_x(50) <= A_x(25) xor A_x(77);
A2_x(49) <= A_x(81);
A2_x(48) <= A_x(24) xor A_x(76);
A2_x(47) <= A_x(80);
A2_x(46) <= A_x(23) xor A_x(75);
A2_x(45) <= A_x(79);
A2_x(44) <= A_x(22) xor A_x(74);
A2_x(43) <= A_x(78);
A2_x(42) <= A_x(21) xor A_x(73);
A2_x(41) <= A_x(77);
A2_x(40) <= A_x(20) xor A_x(72);
A2_x(39) <= A_x(76);
A2_x(38) <= A_x(19) xor A_x(71);
A2_x(37) <= A_x(75);
A2_x(36) <= A_x(18) xor A_x(70);
A2_x(35) <= A_x(74);
A2_x(34) <= A_x(17) xor A_x(69);
A2_x(33) <= A_x(73);
A2_x(32) <= A_x(16) xor A_x(68);
A2_x(31) <= A_x(72);
A2_x(30) <= A_x(15) xor A_x(67);
A2_x(29) <= A_x(71);
A2_x(28) <= A_x(14) xor A_x(66);
A2_x(27) <= A_x(70);
A2_x(26) <= A_x(13) xor A_x(65);
A2_x(25) <= A_x(69);
A2_x(24) <= A_x(12) xor A_x(64);
A2_x(23) <= A_x(68);
A2_x(22) <= A_x(11) xor A_x(63);
A2_x(21) <= A_x(67);
A2_x(20) <= A_x(10) xor A_x(62);
A2_x(19) <= A_x(66);
A2_x(18) <= A_x(9) xor A_x(61);
A2_x(17) <= A_x(65);
A2_x(16) <= A_x(8) xor A_x(60) xor A_x(112);
A2_x(15) <= A_x(64);
A2_x(14) <= A_x(7) xor A_x(59) xor A_x(111);
A2_x(13) <= A_x(63);
A2_x(12) <= A_x(6) xor A_x(58) xor A_x(110);
A2_x(11) <= A_x(62);
A2_x(10) <= A_x(5) xor A_x(57) xor A_x(109);
A2_x(9) <= A_x(61);
A2_x(8) <= A_x(4);
A2_x(7) <= A_x(60) xor A_x(112);
A2_x(6) <= A_x(3);
A2_x(5) <= A_x(59) xor A_x(111);
A2_x(4) <= A_x(2);
A2_x(3) <= A_x(58) xor A_x(110);
A2_x(2) <= A_x(1);
A2_x(1) <= A_x(57) xor A_x(109);
A2_x(0) <= A_x(0);
end behave;
|
gpl-3.0
|
1e7f834afbd91ed7d68a44d552799c8c
| 0.465929 | 1.79021 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_alu.vhd
| 1 | 13,056 |
-- #################################################################################################
-- # << NEO430 - Arithmetical/Logical Unit >> #
-- # ********************************************************************************************* #
-- # Main data processing ALU and operand registers. DADD instruction is not supported! #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_alu is
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
-- operands --
reg_i : in std_ulogic_vector(15 downto 0); -- data from reg file
mem_i : in std_ulogic_vector(15 downto 0); -- data from memory
sreg_i : in std_ulogic_vector(15 downto 0); -- current SR
-- control --
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0);
-- results --
data_o : out std_ulogic_vector(15 downto 0); -- result
flag_o : out std_ulogic_vector(04 downto 0) -- new ALU flags
);
end neo430_alu;
architecture neo430_alu_rtl of neo430_alu is
signal op_data : std_ulogic_vector(15 downto 0); -- operand data
signal op_a_ff : std_ulogic_vector(15 downto 0); -- operand register A
signal op_b_ff : std_ulogic_vector(15 downto 0); -- operand register B
signal add_res : std_ulogic_vector(17 downto 0); -- adder/subtractor kernel result
signal alu_res : std_ulogic_vector(15 downto 0); -- alu result
signal data_res : std_ulogic_vector(15 downto 0); -- final alu result
signal zero : std_ulogic; -- zero detector
signal negative : std_ulogic; -- sign detector
signal parity : std_ulogic; -- parity detector
begin
-- Input Operand Selection --------------------------------------------------
-- -----------------------------------------------------------------------------
op_data <= reg_i when (ctrl_i(ctrl_alu_in_sel_c) = '0') else mem_i;-- when (ctrl_i(ctrl_alu_bw_c) = '0') else (x"00" & mem_i(7 downto 0));
-- Operand Registers --------------------------------------------------------
-- -----------------------------------------------------------------------------
operand_register: process(clk_i)
begin
if rising_edge(clk_i) then
-- operand registers --
if (ctrl_i(ctrl_alu_opa_wr_c) = '1') then
op_a_ff <= op_data;
end if;
if (ctrl_i(ctrl_alu_opb_wr_c) = '1') then
op_b_ff <= op_data;
end if;
end if;
end process operand_register;
-- Binary Arithmetic Core ---------------------------------------------------
-- -----------------------------------------------------------------------------
binary_arithmetic_core: process(ctrl_i, op_a_ff, op_b_ff, sreg_i)
variable op_a_v : std_ulogic_vector(15 downto 0);
variable carry_v : std_ulogic;
variable carry_null_v : std_ulogic;
variable a_lo_v, a_hi_v : std_ulogic_vector(8 downto 0);
variable b_lo_v, b_hi_v : std_ulogic_vector(8 downto 0);
variable add_lo_v, add_hi_v : std_ulogic_vector(8 downto 0);
variable carry_in_v : std_ulogic_vector(0 downto 0);
variable ova_16_v, ova_8_v : std_ulogic;
begin
-- add/sub control (for operand A= --
if (ctrl_i(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) = alu_add_c) or
(ctrl_i(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) = alu_addc_c) then -- addition
op_a_v := op_a_ff;
carry_null_v := '0';
else -- subtraction
op_a_v := not op_a_ff;
carry_null_v := '1';
end if;
-- carry input --
if (ctrl_i(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) = alu_addc_c) or
(ctrl_i(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) = alu_subc_c) then -- use carry in
carry_in_v(0) := sreg_i(sreg_c_c);
else
carry_in_v(0) := carry_null_v; -- set default NO ACTIVE CARRY input
end if;
-- operands --
a_lo_v := '0' & op_a_v(07 downto 0);
a_hi_v := '0' & op_a_v(15 downto 8);
b_lo_v := '0' & op_b_ff(07 downto 0);
b_hi_v := '0' & op_b_ff(15 downto 8);
-- adder core --
add_lo_v := std_ulogic_vector(unsigned(a_lo_v) + unsigned(b_lo_v) + unsigned(carry_in_v(0 downto 0)));
add_hi_v := std_ulogic_vector(unsigned(a_hi_v) + unsigned(b_hi_v) + unsigned(add_lo_v(8 downto 8)));
-- overflow logic for the actual ADDER CORE (thx Edward!): plus + plus = minus || minus + minus = plus --
ova_16_v := ((not op_a_v(15)) and (not op_b_ff(15)) and add_hi_v(7)) or (op_a_v(15) and op_b_ff(15) and (not add_hi_v(7)));
ova_8_v := ((not op_a_v(7)) and (not op_b_ff(7)) and add_lo_v(7)) or (op_a_v(7) and op_b_ff(7) and (not add_lo_v(7)));
-- output --
add_res(15 downto 0) <= add_hi_v(7 downto 0) & add_lo_v(7 downto 0); -- result
if (ctrl_i(ctrl_alu_bw_c) = '1') then -- byte mode flags
add_res(16) <= add_lo_v(8);
add_res(17) <= ova_8_v;
else -- word mode flags
add_res(16) <= add_hi_v(8);
add_res(17) <= ova_16_v;
end if;
end process binary_arithmetic_core;
-- ALU Core -----------------------------------------------------------------
-- -----------------------------------------------------------------------------
alu_core: process(ctrl_i, op_a_ff, op_b_ff, sreg_i, negative, zero, parity, add_res)
begin
-- defaults --
alu_res <= op_a_ff;
flag_o(flag_c_c) <= sreg_i(sreg_c_c); -- keep
flag_o(flag_v_c) <= sreg_i(sreg_v_c); -- keep
flag_o(flag_n_c) <= negative; -- update
flag_o(flag_z_c) <= zero; -- update
flag_o(flag_p_c) <= parity; -- update
-- function selection --
case ctrl_i(ctrl_alu_cmd3_c downto ctrl_alu_cmd0_c) is
when alu_add_c | alu_addc_c | alu_sub_c | alu_subc_c | alu_cmp_c =>
-- alu_add_c : r <= a + b
-- alu_addc_c : r <= a + b + c
-- alu_sub_c : r <= b - a
-- alu_subc_c : r <= b - a - 1 + c
-- alu_cmp_c : b - a (no write back, done by ctrl arbiter)
alu_res <= add_res(15 downto 0);
flag_o(flag_c_c) <= add_res(16);
flag_o(flag_v_c) <= add_res(17);
when alu_and_c => -- r <= a & b
alu_res <= op_a_ff and op_b_ff;
flag_o(flag_c_c) <= not zero;
flag_o(flag_v_c) <= '0';
when alu_xor_c => -- r <= a xor b
alu_res <= op_a_ff xor op_b_ff;
flag_o(flag_c_c) <= not zero;
flag_o(flag_v_c) <= op_a_ff(15) and op_b_ff(15); -- word mode
if (ctrl_i(ctrl_alu_bw_c) = '1') then -- byte mode
flag_o(flag_v_c) <= op_a_ff(7) and op_b_ff(7);
end if;
when alu_bic_c => -- r <= !a & b
alu_res <= (not op_a_ff) and op_b_ff;
flag_o(flag_c_c) <= sreg_i(sreg_c_c); -- keep
flag_o(flag_v_c) <= sreg_i(sreg_v_c); -- keep
flag_o(flag_n_c) <= sreg_i(sreg_n_c); -- keep
flag_o(flag_z_c) <= sreg_i(sreg_z_c); -- keep
when alu_bis_c => -- r <= a | b
alu_res <= op_a_ff or op_b_ff;
flag_o(flag_c_c) <= sreg_i(sreg_c_c); -- keep
flag_o(flag_v_c) <= sreg_i(sreg_v_c); -- keep
flag_o(flag_n_c) <= sreg_i(sreg_n_c); -- keep
flag_o(flag_z_c) <= sreg_i(sreg_z_c); -- keep
when alu_bit_c => -- r <= a & b (no write back, done by ctrl arbiter)
alu_res <= op_a_ff and op_b_ff;
flag_o(flag_c_c) <= not zero;
flag_o(flag_v_c) <= '0';
when alu_rra_c | alu_rrc_c =>
-- alu_rra_c : r <= a >> 1, rotate right arithmetically
-- alu_rrc_c : r <= a >> 1, rotate right through carry
if (ctrl_i(ctrl_alu_cmd1_c) = alu_rra_c(1)) then -- alu_rra_c
alu_res <= op_a_ff(15) & op_a_ff(15 downto 1); -- word mode
if (ctrl_i(ctrl_alu_bw_c) = '1') then -- byte mode
alu_res(7) <= op_a_ff(7);
end if;
else -- alu_rrc_c
alu_res <= sreg_i(sreg_c_c) & op_a_ff(15 downto 1); -- word mode
if (ctrl_i(ctrl_alu_bw_c) = '1') then -- byte mode
alu_res(7) <= sreg_i(sreg_c_c);
end if;
end if;
flag_o(flag_c_c) <= op_a_ff(0);
flag_o(flag_v_c) <= '0';
when alu_sxt_c => -- r <= a, sign extend byte
for i in 8 to 15 loop
alu_res(i) <= op_a_ff(7);
end loop;
alu_res(7 downto 0) <= op_a_ff(7 downto 0);
flag_o(flag_c_c) <= not zero;
flag_o(flag_v_c) <= '0';
when alu_swap_c => -- r <= swap bytes of a
alu_res <= op_a_ff(7 downto 0) & op_a_ff(15 downto 8);
flag_o(flag_c_c) <= sreg_i(sreg_c_c); -- keep
flag_o(flag_v_c) <= sreg_i(sreg_v_c); -- keep
flag_o(flag_n_c) <= sreg_i(sreg_n_c); -- keep
flag_o(flag_z_c) <= sreg_i(sreg_z_c); -- keep
when alu_mov_c => -- r <= a
alu_res <= op_a_ff;
flag_o(flag_c_c) <= sreg_i(sreg_c_c); -- keep
flag_o(flag_v_c) <= sreg_i(sreg_v_c); -- keep
flag_o(flag_n_c) <= sreg_i(sreg_n_c); -- keep
flag_o(flag_z_c) <= sreg_i(sreg_z_c); -- keep
when others => -- undefined
alu_res <= (others => '-');
flag_o(flag_c_c) <= '-';
flag_o(flag_v_c) <= '-';
flag_o(flag_n_c) <= '-';
flag_o(flag_z_c) <= '-';
flag_o(flag_p_c) <= '-';
end case;
end process alu_core;
-- Post processing logic ----------------------------------------------------
-- -----------------------------------------------------------------------------
-- word/byte mode mask --
data_res(07 downto 0) <= alu_res(07 downto 0);
data_res(15 downto 8) <= alu_res(15 downto 8) when (ctrl_i(ctrl_alu_bw_c) = '0') else x"00";
-- zero flag --
zero <= not or_all_f(data_res);
-- parity flag --
parity <= (not xor_all_f(data_res)) when (use_xalu_c = true) else '-'; -- if implemented
-- negative flag --
negative <= data_res(7) when (ctrl_i(ctrl_alu_bw_c) = '1') else data_res(15);
-- final data output --
data_o <= data_res;
end neo430_alu_rtl;
|
bsd-3-clause
|
25fff89ae4003fd2ab6aaa9cee08e20a
| 0.470052 | 3.413333 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.a-ControlUnit.core/a.a.b-StallGenerator.vhd
| 1 | 9,521 |
--------------------------------------------------------------------------------
-- FILE: StallGenerator
-- DESC: Generate stall for each stage
--
-- Author:
-- Create: 2015-07-29
-- Update: 2015-09-28
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity StallGenerator is
generic(
CWRD_SIZE : integer := C_SYS_CWRD_SIZE
);
port(
rst : in std_logic;
clk : in std_logic;
sig_ral : in std_logic := '0'; -- from DataPath
sig_bpw : in std_logic := '0'; -- from Branch
sig_jral : in std_logic := '0'; -- from DataPath
sig_mul : in std_logic := '0'; -- from DataPath
sig_div : in std_logic := '0'; -- from DataPath
sig_sqrt : in std_logic := '0'; -- from DataPath
stall_flag : out std_logic_vector(4 downto 0):=(others=>'0')
);
end StallGenerator;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture stall_generator_arch of StallGenerator is
signal s_ral : std_logic_vector(4 downto 0) := "00000";
signal s_bpw : std_logic_vector(4 downto 0) := "00000";
signal s_jral: std_logic_vector(4 downto 0) := "00000";
signal s_mul : std_logic_vector(4 downto 0) := "00000";
signal s_div : std_logic_vector(4 downto 0) := "00000";
signal s_sqrt: std_logic_vector(4 downto 0) := "00000";
signal s_stu : std_logic_vector(4 downto 0) := "11111";
signal c_state_ral, n_state_ral : integer := SG_ST0;
signal c_state_bpw, n_state_bpw : integer := SG_ST0;
signal c_state_jral, n_state_jral : integer := SG_ST0;
signal c_state_mul, n_state_mul : integer := SG_ST0;
signal c_state_div, n_state_div : integer := SG_ST0;
signal c_state_sqrt, n_state_sqrt : integer := SG_ST0;
signal c_state_stu, n_state_stu : integer := SG_ST0;
constant MUL_STAGE : integer := C_MUL_STAGE;
constant DIV_STAGE : integer := C_DIV_STAGE;
constant SQRT_STAGE : integer := C_SQRT_STAGE;
begin
-- A OR B WAIT SIGNAL
-- NEXT STATE GENERATOR
P_NSG1: process(sig_ral, c_state_ral)
begin
if (sig_ral='1') then
n_state_ral<=SG_ST1;
else
if c_state_ral = SG_ST0 or c_state_ral >= SG_ST2 then
n_state_ral <= SG_ST0;
else
n_state_ral <= c_state_ral + 1;
end if;
end if;
end process;
-- OUTPUT GENERATOR
P_OUT1: process(c_state_ral)
begin
case c_state_ral is
when SG_ST0 => s_ral <= "00000";
when SG_ST1 => s_ral <= "00010";
when SG_ST2 => s_ral <= "00001";
when others => s_ral <= "00000";
end case;
end process;
-- NEXT STATE REGISTER
P_REG1: process(rst, clk)
begin
if rst='0' then
c_state_ral <= SG_ST0;
else
if rising_edge(clk) then
c_state_ral <= n_state_ral;
end if;
end if;
end process;
-- BRANCH PREDICT ERROR
-- NEXT STATE GENERATOR
P_NSG2: process(sig_bpw, c_state_bpw)
begin
if (sig_bpw='1') then
n_state_bpw<=SG_ST1;
else
if c_state_bpw = SG_ST0 or c_state_bpw >= SG_ST2 then
n_state_bpw <= SG_ST0;
else
n_state_bpw <= c_state_bpw + 1;
end if;
end if;
end process;
-- OUTPUT GENERATOR
P_OUT2: process(c_state_bpw)
begin
case c_state_bpw is
when SG_ST0 => s_bpw <= "00000";
when SG_ST1 => s_bpw <= "00010";
when SG_ST2 => s_bpw <= "00001";
when others => s_bpw <= "00000";
end case;
end process;
-- NEXT STATE REGISTER
P_REG2: process(rst, clk)
begin
if rst='0' then
c_state_bpw <= SG_ST0;
else
if rising_edge(clk) then
c_state_bpw <= n_state_bpw;
end if;
end if;
end process;
-- JR WAIT SIGNAL
-- NEXT STATE GENERATOR
P_NSG3: process(sig_jral, c_state_jral)
begin
if (sig_jral='1') then
n_state_jral<=SG_ST1;
else
if c_state_jral = SG_ST0 or c_state_jral >= SG_ST3 then
n_state_jral <= SG_ST0;
else
n_state_jral <= c_state_jral + 1;
end if;
end if;
end process;
-- OUTPUT GENERATOR
P_OUT3: process(c_state_jral)
begin
case c_state_jral is
when SG_ST0 => s_jral <= "00000";
when SG_ST1 => s_jral <= "00100";
when SG_ST2 => s_jral <= "00010";
when SG_ST3 => s_jral <= "00001";
when others => s_jral <= "00000";
end case;
end process;
-- NEXT STATE REGISTER
P_REG3: process(rst, clk)
begin
if rst='0' then
c_state_jral <= SG_ST0;
else
if rising_edge(clk) then
c_state_jral <= n_state_jral;
end if;
end if;
end process;
-- MUL SIGNAL
-- NEXT STATE GENERATOR
P_NSG4: process(sig_mul, sig_ral, c_state_mul)
begin
if (sig_mul='1') and (sig_ral='0') and ((c_state_mul=SG_ST0) or (c_state_mul=MUL_STAGE)) then
n_state_mul<=SG_ST1;
else
if c_state_mul = SG_ST0 or c_state_mul >= MUL_STAGE then
n_state_mul <= SG_ST0;
else
n_state_mul <= c_state_mul + 1;
end if;
end if;
end process;
-- OUTPUT GENERATOR
P_OUT4: process(c_state_mul)
begin
if c_state_mul=SG_ST0 then
s_mul <= "00000";
elsif c_state_mul=SG_ST1 then
s_mul <= "11110";
elsif c_state_mul>SG_ST1 and c_state_mul<MUL_STAGE-1 then
s_mul <= "11111";
elsif c_state_mul=MUL_STAGE-1 then
s_mul <= "00011";
elsif c_state_mul=MUL_STAGE then
s_mul <= "00001";
else
s_mul <= "00000";
end if;
end process;
-- NEXT STATE REGISTER
P_REG4: process(rst, clk)
begin
if rst='0' then
c_state_mul <= SG_ST0;
else
if rising_edge(clk) then
c_state_mul <= n_state_mul;
end if;
end if;
end process;
-- DIV SIGNAL
-- NEXT STATE GENERATOR
P_NSG6: process(sig_div, sig_ral, c_state_div)
begin
if (sig_div='1') and (sig_ral='0') and ((c_state_div=SG_ST0)or (c_state_div=DIV_STAGE)) then
n_state_div<=SG_ST1;
else
if c_state_div = SG_ST0 or c_state_div >= DIV_STAGE then
n_state_div <= SG_ST0;
else
n_state_div <= c_state_div + 1;
end if;
end if;
end process;
-- OUTPUT GENERATOR
P_OUT6: process(c_state_div)
begin
if c_state_div=SG_ST0 then
s_div <= "00000";
elsif c_state_div=SG_ST1 then
s_div <= "11110";
elsif c_state_div>SG_ST1 and c_state_div<DIV_STAGE-1 then
s_div <= "11111";
elsif c_state_div=DIV_STAGE-1 then
s_div <= "00011";
elsif c_state_div=DIV_STAGE then
s_div <= "00001";
else
s_div <= "00000";
end if;
end process;
-- NEXT STATE REGISTER
P_REG6: process(rst, clk)
begin
if rst='0' then
c_state_div <= SG_ST0;
else
if rising_edge(clk) then
c_state_div <= n_state_div;
end if;
end if;
end process;
-- SQRT SIGNAL
-- NEXT STATE GENERATOR
P_NSG7: process(sig_sqrt, sig_ral, c_state_sqrt)
begin
if (sig_sqrt='1') and (sig_ral='0') and ((c_state_sqrt=SG_ST0)or (c_state_sqrt=SQRT_STAGE)) then
n_state_sqrt<=SG_ST1;
else
if c_state_sqrt = SG_ST0 or c_state_sqrt >= SQRT_STAGE then
n_state_sqrt <= SG_ST0;
else
n_state_sqrt <= c_state_sqrt + 1;
end if;
end if;
end process;
-- OUTPUT GENERATOR
P_OUT7: process(c_state_sqrt)
begin
if c_state_sqrt=SG_ST0 then
s_sqrt <= "00000";
elsif c_state_sqrt=SG_ST1 then
s_sqrt <= "11110";
elsif c_state_sqrt>SG_ST1 and c_state_sqrt<SQRT_STAGE-1 then
s_sqrt <= "11111";
elsif c_state_sqrt=SQRT_STAGE-1 then
s_sqrt <= "00011";
elsif c_state_sqrt=SQRT_STAGE then
s_sqrt <= "00001";
else
s_sqrt <= "00000";
end if;
end process;
-- NEXT STATE REGISTER
P_REG7: process(rst, clk)
begin
if rst='0' then
c_state_sqrt <= SG_ST0;
else
if rising_edge(clk) then
c_state_sqrt <= n_state_sqrt;
end if;
end if;
end process;
-- START UP
-- NEXT STATE GENERATOR
P_NSG5: process(c_state_stu)
begin
if c_state_stu >= SG_ST5 then
n_state_stu <= SG_ST5;
else
n_state_stu <= c_state_stu + 1;
end if;
end process;
-- OUTPUT GENERATOR
P_OUT5: process(c_state_stu)
begin
case c_state_stu is
when SG_ST0 => s_stu <= "11111";
when SG_ST1 => s_stu <= "00111";
when SG_ST2 => s_stu <= "00011";
when SG_ST3 => s_stu <= "00001";
when SG_ST4 => s_stu <= "00000";
when SG_ST5 => s_stu <= "00000";
when others => s_stu <= "00000";
end case;
end process;
-- NEXT STATE REGISTER
P_REG5: process(rst, clk)
begin
if rst='0' then
c_state_stu <= SG_ST0;
else
if rising_edge(clk) then
c_state_stu <= n_state_stu;
end if;
end if;
end process;
P_FIN: process(s_ral, s_bpw, s_mul, s_div, s_sqrt, s_stu, sig_ral, sig_bpw, sig_jral, sig_mul, sig_div, sig_sqrt, c_state_mul, c_state_div, c_state_sqrt)
variable stall_flag_tmp: std_logic_vector(4 downto 0);
begin
stall_flag_tmp := s_ral or s_bpw or s_mul or s_div or s_sqrt or s_stu;
if (sig_ral='1') then
stall_flag_tmp := stall_flag_tmp or "11100";
end if;
if (sig_bpw='1') then
stall_flag_tmp := stall_flag_tmp or "00100";
end if;
if (sig_jral='1') then
stall_flag_tmp := stall_flag_tmp or "11000";
end if;
if (sig_mul='1') and (sig_ral='0') and ((c_state_mul=SG_ST0) or (c_state_mul=MUL_STAGE)) then
stall_flag_tmp := stall_flag_tmp or "11100";
end if;
if (sig_div='1') and (sig_ral='0') and ((c_state_div=SG_ST0) or (c_state_div=DIV_STAGE)) then
stall_flag_tmp := stall_flag_tmp or "11100";
end if;
if (sig_sqrt='1') and (sig_ral='0') and ((c_state_sqrt=SG_ST0) or (c_state_sqrt=SQRT_STAGE)) then
stall_flag_tmp := stall_flag_tmp or "11100";
end if;
stall_flag <= stall_flag_tmp;
end process;
end stall_generator_arch;
|
mit
|
ef4afda981f2ffc9ec802194d059fb0a
| 0.585968 | 2.599945 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_10.vhd
| 4 | 1,702 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_10.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_10 is
end entity ch_05_10;
----------------------------------------------------------------
architecture test of ch_05_10 is
signal data : bit_vector(7 downto 0) := X"FF";
signal s : bit := '0';
begin
process_05_3_l : process is
begin
wait for 10 ns;
-- code from book:
data <= X"00";
-- end of code from book
wait for 10 ns;
-- code from book:
s <= '1';
-- . . .
if s = '1' then -- . . .
-- not in book
report "s is '1'";
else
report "s is '0'";
end if;
-- end not in boook
-- end of code from book
wait;
end process process_05_3_l;
end architecture test;
|
gpl-2.0
|
a81b81ac0a5888eeef4d9d603f315cea
| 0.56228 | 3.90367 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug05/repro.vhdl
| 3 | 613 |
entity sub is
generic (l : natural);
port (a : out bit;
b : bit_vector (0 to 3);
c : bit_vector (0 to l - 1));
end sub;
architecture behav of sub is
begin
a <= b (0) xor c (0);
end behav;
entity tb is
end tb;
architecture behav of tb is
signal a : bit;
signal b: bit_vector (0 to 3);
signal c: bit_vector (0 to 7);
begin
my_sub: entity work.sub
generic map (l => c'length)
port map (a => a, b => b, c => c);
process
begin
wait for 1 ns;
assert a = '0';
b <= x"0";
c <= x"80";
wait for 1 ns;
assert a = '1';
wait;
end process;
end behav;
|
gpl-2.0
|
3c2aa6b192d16847dc4fe677a72f861c
| 0.548124 | 2.919048 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/mb_lite/dsram.vhd
| 3 | 1,654 |
----------------------------------------------------------------------------------------------
--
-- Input file : dsram.vhd
-- Design name : dsram
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Dual Port Synchronous 'read after write' Ram. 1 Read Port and 1
-- Write Port.
--
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.std_Pkg.ALL;
ENTITY dsram IS GENERIC
(
WIDTH : positive := 32;
SIZE : positive := 8
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
ena_i : IN std_ulogic;
dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END dsram;
ARCHITECTURE arch OF dsram IS
TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_ulogic_vector(WIDTH - 1 DOWNTO 0);
SIGNAL ram : ram_type;
BEGIN
PROCESS(clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF ena_i = '1' THEN
IF wre_i = '1' THEN
ram(my_conv_integer(adr_w_i)) <= dat_w_i;
END IF;
dat_o <= ram(my_conv_integer(adr_i));
END IF;
END IF;
END PROCESS;
END arch;
|
mit
|
1462b4a4641f16075a1755dd8b14d445
| 0.471584 | 3.864486 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd
| 4 | 1,713 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_inv_integrator is
end tb_inv_integrator;
architecture TB_inv_integrator of tb_inv_integrator is
-- Component declarations
-- Signal declarations
terminal vin : electrical;
terminal vout : electrical;
begin
-- Signal assignments
-- Component instances
v1 : entity work.v_sine(ideal)
generic map(
amplitude => 0.2,
freq => 1.0e3
)
port map(
pos => vin,
neg => ELECTRICAL_REF
);
inverting_integ1 : entity work.inverting_integrator(structural)
port map(
output => vout,
input => vin
);
RLoad : entity work.load_res(ideal)
generic map(
R => 100.0
)
port map(
node1 => vout,
node2 => ELECTRICAL_REF
);
end TB_inv_integrator;
|
gpl-2.0
|
d7e0608d4c1c56bd2ede46f1b7dadee4
| 0.646235 | 4.293233 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/SingleFile/f2m_divider_163.vhd
| 1 | 8,941 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par, u_mas_v_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & Y;
B <= F;
U <= '0' & X;
v <= (others => '0');
x_div_y <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
-- done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
0c669dd866651163bb894a4d4aa276f9
| 0.499049 | 4.728186 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1269.vhd
| 4 | 1,837 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1269.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p02n01i01269ent IS
END c08s04b00x00p02n01i01269ent;
ARCHITECTURE c08s04b00x00p02n01i01269arch OF c08s04b00x00p02n01i01269ent IS
signal X1 : integer := 1;
signal X2 : integer := 2;
signal T1 : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
T1 <= X1 + X2;
wait for 1 ns;
assert NOT(T1 = 3)
report "***PASSED TEST: c08s04b00x00p02n01i01269"
severity NOTE;
assert (T1 = 3)
report "***FAILED TEST: c08s04b00x00p02n01i01269 - Signal assignment statement consists of a target, a signal assignment operator"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p02n01i01269arch;
|
gpl-2.0
|
6e9edacb614242007d4fb916e4e480cb
| 0.663582 | 3.616142 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Guerric/Modular/celda_s.vhd
| 1 | 1,496 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_s is
generic(
NUM_BITS : positive := 163
);
port(
R : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
X2 : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c_1 : in STD_LOGIC;
c_2 : in STD_LOGIC;
en : in STD_LOGIC;
clk : in STD_LOGIC;
S : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_s is
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
Celda_s_process: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if en = '1' then
if c_1 = '0' and c_2 = '0' then
S <= X2;
elsif c_1 = '0' and c_2 = '1' then
S <= (others => '0');
else
S <= R;
end if;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
fe8a5ccbd71ae75d51a5becd5c6c14e8
| 0.326203 | 4.387097 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc931.vhd
| 4 | 2,066 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc931.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s04b00x00p03n01i00931pkg is
constant x : integer := 2;
constant y : real := 5.0;
subtype register16 is bit_vector(15 downto 0);
end c10s04b00x00p03n01i00931pkg;
use work.c10s04b00x00p03n01i00931pkg.x;
ENTITY c10s04b00x00p03n01i00931ent IS
END c10s04b00x00p03n01i00931ent;
ARCHITECTURE c10s04b00x00p03n01i00931arch OF c10s04b00x00p03n01i00931ent IS
signal i_sig : integer := x;
BEGIN
TESTING: PROCESS
BEGIN
i_sig <= i_sig + x after 10 ns;
wait for 11 ns;
assert NOT(i_sig = 4)
report "***PASSED TEST: c10s04b00x00p03n01i00931"
severity NOTE;
assert (i_sig = 4)
report "***FAILED TEST: c10s04b00x00p03n01i00931 - The identifier is visible in the declarative region if the suffix of a selected name in a use clause is a simple identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s04b00x00p03n01i00931arch;
|
gpl-2.0
|
0660bb2b39c8b4cb90373412865b8d92
| 0.681994 | 3.49577 | false | true | false | false |
stnolting/neo430
|
rtl/core/neo430_cpu.vhd
| 1 | 10,226 |
-- #################################################################################################
-- # << NEO430 - CPU Top Entity >> #
-- # ********************************************************************************************* #
-- # Top entity of the NEO430 CPU. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_cpu is
generic (
BOOTLD_USE : boolean := true; -- implement and use bootloader?
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory?
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, low-active, async
-- memory interface --
mem_rd_o : out std_ulogic; -- memory read enable
mem_imwe_o : out std_ulogic; -- allow writing to IMEM
mem_wr_o : out std_ulogic_vector(01 downto 0); -- byte memory write enable
mem_addr_o : out std_ulogic_vector(15 downto 0); -- address
mem_data_o : out std_ulogic_vector(15 downto 0); -- write data
mem_data_i : in std_ulogic_vector(15 downto 0); -- read data
-- interrupt system --
irq_i : in std_ulogic_vector(03 downto 0) -- interrupt requests
);
end neo430_cpu;
architecture neo430_cpu_rtl of neo430_cpu is
-- local signals --
signal mem_addr : std_ulogic_vector(15 downto 0); -- memory address
signal mdi : std_ulogic_vector(15 downto 0); -- memory data_in
signal mdi_gate : std_ulogic_vector(15 downto 0); -- memory data_in power gate
signal mdo_gate : std_ulogic_vector(15 downto 0); -- memory data_out power gate
signal ctrl_bus : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control spine
signal sreg : std_ulogic_vector(15 downto 0); -- current status register
signal alu_flags : std_ulogic_vector(04 downto 0); -- new ALU flags
signal imm : std_ulogic_vector(15 downto 0); -- branch offset
signal rf_read : std_ulogic_vector(15 downto 0); -- RF read data
signal alu_res : std_ulogic_vector(15 downto 0); -- ALU result
signal addr_fb : std_ulogic_vector(15 downto 0); -- address feedback
signal irq_sel : std_ulogic_vector(01 downto 0); -- IRQ vector
signal dio_swap : std_ulogic; -- data in/out swap
signal bw_ff : std_ulogic; -- byte/word access flag
signal rd_ff : std_ulogic; -- is read access
begin
-- Control Unit -------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_control_inst: neo430_control
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rst_i => rst_i, -- global reset, low-active, async
-- memory interface --
instr_i => mem_data_i, -- instruction word from memory
-- control --
sreg_i => sreg, -- current status register
ctrl_o => ctrl_bus, -- control signals
irq_vec_o => irq_sel, -- irq channel address
imm_o => imm, -- branch offset
-- irq lines --
irq_i => irq_i -- IRQ lines
);
-- Register File ------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_reg_file_inst: neo430_reg_file
generic map (
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader?
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory?
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rst_i => rst_i, -- global reset, low-active, async
-- data input --
alu_i => alu_res, -- data from alu
addr_i => addr_fb, -- data from addr unit
flag_i => alu_flags, -- new ALU flags
-- control --
ctrl_i => ctrl_bus, -- control signals
-- data output --
data_o => rf_read, -- read data
sreg_o => sreg -- current SR
);
-- ALU ----------------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_alu_inst: neo430_alu
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
-- operands --
reg_i => rf_read, -- data from reg file
mem_i => mdi, -- data from memory
sreg_i => sreg, -- current SR
-- control --
ctrl_i => ctrl_bus, -- control signals
-- results --
data_o => alu_res, -- result
flag_o => alu_flags -- new ALU flags
);
-- Address Generator --------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_addr_gen_inst: neo430_addr_gen
port map(
-- global control --
clk_i => clk_i, -- global clock, rising edge
-- data input --
reg_i => rf_read, -- reg file input
mem_i => mdi, -- memory input
imm_i => imm, -- branch offset
irq_sel_i => irq_sel, -- IRQ vector
-- control --
ctrl_i => ctrl_bus, -- control signals
-- data output --
mem_addr_o => mem_addr, -- memory address
dwb_o => addr_fb -- data write back output
);
-- Memory Access ------------------------------------------------------------
-- -----------------------------------------------------------------------------
memory_control: process(clk_i)
begin
if rising_edge(clk_i) then
bw_ff <= ctrl_bus(ctrl_alu_bw_c);
dio_swap <= ctrl_bus(ctrl_alu_bw_c) and mem_addr(0);
rd_ff <= ctrl_bus(ctrl_mem_rd_c);
end if;
end process memory_control;
-- Memory R/W interface --
mem_rd_o <= ctrl_bus(ctrl_mem_rd_c);
-- activate both WE lines when in word mode, use corresponding WE line when in byte mode
mem_wr_o(0) <= ctrl_bus(ctrl_mem_wr_c) when (bw_ff = '0') else (ctrl_bus(ctrl_mem_wr_c) and (not mem_addr(0)));
mem_wr_o(1) <= ctrl_bus(ctrl_mem_wr_c) when (bw_ff = '0') else (ctrl_bus(ctrl_mem_wr_c) and mem_addr(0) );
-- only allow write-access to IMEM when r-flag is set --
mem_imwe_o <= sreg(sreg_r_c);
-- data in/out swap --
mdi_gate <= mem_data_i when ((rd_ff = '1') or (low_power_mode_c = false)) else (others => '0'); -- AND GATE to reduce switching activity in low power mode
mdi <= mdi_gate when (dio_swap = '0') else mdi_gate(7 downto 0) & mdi_gate(15 downto 8);
mdo_gate <= alu_res when (dio_swap = '0') else alu_res(7 downto 0) & alu_res(15 downto 8);
mem_data_o <= mdo_gate when ((ctrl_bus(ctrl_mem_wr_c) = '1') or (low_power_mode_c = false)) else (others => '0'); -- AND GATE to reduce switching activity in low power mode
-- address output --
mem_addr_o <= mem_addr(15 downto 1) & '0'; -- word-aligned addresses only beyond this point
end neo430_cpu_rtl;
|
bsd-3-clause
|
16fd3f85e0def41020c9d1f2730fd9d8
| 0.473695 | 4.407759 | false | false | false | false |
tristanseifert/68komputer
|
VideoController.vhd
| 1 | 8,542 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- Video controller, providing bitmapped display to the system. It uses the SRAM
-- as a video memory, with each pixel occupying 8 bits. This is then taken as an
-- offset into the colour look-up table, or CRAM, and outputted.
--
-- SRAM is organised with each line taking up 1024 bytes, for simpler logic. The
-- addresses are built as row(8..0) | col(9..1). Since the SRAM is 16 bits wide,
-- we only request a read every other pixel.
--
entity VideoController is
PORT (
-- clocks and friends
reset: IN std_logic;
In_Clk_24: IN std_logic;
-- video signals
Out_R: OUT std_logic_vector(3 downto 0);
Out_G: OUT std_logic_vector(3 downto 0);
Out_B: OUT std_logic_vector(3 downto 0);
Out_HSync: OUT std_logic;
Out_VSync: OUT std_logic;
-- SRAM (used to store video datas)
SRAM_Addr: OUT std_logic_vector(17 downto 0);
SRAM_Data: INOUT std_logic_vector(15 downto 0);
SRAM_CE: OUT std_logic;
SRAM_OE: OUT std_logic;
SRAM_WE: OUT std_logic;
SRAM_LB: OUT std_logic;
SRAM_UB: OUT std_logic;
-- Debug status info
debug_state: OUT std_logic_vector(3 downto 0) := (others => '0');
debug_bits: IN std_logic_vector(3 downto 0) := (others => '0');
-- CPU bus
bus_cs: IN std_logic; -- when high, outs is Z
bus_clk: IN std_logic;
bus_address: IN std_logic_vector(18 downto 0);
bus_data: INOUT std_logic_vector(15 downto 0);
bus_rw: IN std_logic;
bus_as: IN std_logic;
bus_dtack: OUT std_logic;
bus_uds: IN std_logic;
bus_lds: IN std_logic
);
end VideoController;
architecture behavioral of VideoController is
signal VidClk: std_logic; -- 25.175 MHz
signal MemClk: std_logic; -- 50.35 MHz
signal ActiveDisplay: std_logic; -- when asserted, colours out
signal col, row: std_logic_vector(9 downto 0);
-- this will *always* hold the last word read from memory
signal pxgen_data: std_logic_vector(15 downto 0) register;
-- CRAM signals
signal cram_read_data: std_logic_vector(23 downto 0);
signal cram_write_data: std_logic_vector(23 downto 0);
signal cram_read_addr: std_logic_vector(7 downto 0) := (others => '0');
signal cram_write_addr: std_logic_vector(7 downto 0) := (others => '0');
signal cram_write_strobe: std_logic := '0';
-- FIFO stuff
signal fifo_read_pend: std_logic register := '0';
signal fifo_rdempty: std_logic := '1';
signal fifo_wrfull: std_logic := '0';
signal fifo_rdreq: std_logic := '0';
signal fifo_wrreq: std_logic := '0';
signal fifo_read_data: std_logic_vector(35 downto 0) := (others => '0');
signal fifo_write_data: std_logic_vector(35 downto 0) := (others => '0');
-- SRAM access state machine
type ram_state_type is (SysReset, CPUSlot0, CPUSlot1, ReadAddrVideo, ReadDataVideo);
signal ram_current_state, ram_next_state: ram_state_type;
begin
-- video clock generator
u_VideoPLL: entity work.VideoPLL(SYN)
port map(
inclk0 => In_Clk_24,
c0 => VidClk,
c1 => MemClk,
areset => reset
);
-- video sync state machine
u_videoSyncer: entity work.VideoSyncGenerator(behavioral)
port map(
reset => reset,
PixelClock => VidClk,
HSync => Out_HSync,
VSync => Out_VSync,
VideoOn => ActiveDisplay,
CurCol => col,
CurRow => row
);
-- Colour RAM
u_cram: entity work.VideoCRAM(SYN)
port map (
data => cram_write_data,
wraddress => cram_write_addr,
wrclock => MemClk,
wren => cram_write_strobe,
q => cram_read_data,
rdaddress => cram_read_addr,
rdclock => MemClk
);
-- CPU Write FIFO
-- Each entry is 36 bits: UDS, LDS, 16 bits of data, and 18 bits of VRAM address.
u_writefifo: entity work.VideoWriteFIFO(SYN)
port map (
data => fifo_write_data,
wrclk => bus_clk,
wrreq => fifo_wrreq,
wrfull => fifo_wrfull,
q => fifo_read_data,
rdclk => MemClk,
rdreq => fifo_rdreq,
rdempty => fifo_rdempty,
aclr => reset
);
-- 68k bus interface. Writes go straight into the FIFO, and will process with
-- no wait states, unless the FIFO is filled. In that case, wait states are
-- inserted until the FIFO is no longer full.
process(bus_clk, reset, bus_cs, bus_rw, fifo_wrfull, bus_uds, bus_lds)
begin
-- in reset state, don't drive the bus
if reset='0' then
bus_data <= (others => 'Z');
bus_dtack <= 'Z';
elsif rising_edge(bus_clk) then
-- is our chip select asserted?
if bus_cs='0' then
-- write cycle
if bus_rw='0' then
if fifo_wrfull='0' then
fifo_write_data <= bus_uds & bus_lds & bus_data & bus_address(18 downto 1);
fifo_wrreq <= '1';
bus_dtack <= '0';
else
-- fifo is full: delay the bus cycle some more
bus_dtack <= '1';
end if;
-- read cycle
else
-- unhandled: lock up machine
bus_dtack <= '1';
end if;
-- not selected: don't drive bus
else
bus_data <= (others => 'Z');
bus_dtack <= 'Z';
-- de-assert FIFO write request
fifo_wrreq <= '0';
end if;
end if;
end process;
-- blank output if active display
process(ActiveDisplay, col, row, cram_read_data, pxgen_data)
begin
if ActiveDisplay='0'
then -- inactivedisplay; render colour 0
cram_read_addr <= (others => '0');
else -- active display; process read pixel data
if col(0)='0'
then cram_read_addr <= pxgen_data(7 downto 0); -- display odd pixel next
else cram_read_addr <= pxgen_data(15 downto 8); -- display even pixel next
end if;
end if;
-- get colour from CRAM
Out_R <= cram_read_data(23 downto 20);
Out_G <= cram_read_data(15 downto 12);
Out_B <= cram_read_data(7 downto 4);
end process;
-- Read/write state machine state advancement
process (MemClk, reset)
begin
if reset='1'
then ram_current_state <= SysReset;
elsif rising_edge(MemClk)
then
ram_current_state <= ram_next_state;
end if;
end process;
-- Read/write state machine
process(reset, ram_current_state, SRAM_Data, row, col, fifo_rdempty)
begin
-- default CRAM and FIFO values
--cram_read_addr <= (others => '0');
fifo_rdreq <= '0';
-- default sram state
SRAM_CE <= '0';
SRAM_OE <= '0';
SRAM_WE <= '1';
SRAM_UB <= '1';
SRAM_LB <= '1';
SRAM_Addr <= (others => '0');
SRAM_Data <= (others => 'Z');
-- state machine
case ram_current_state is
-- Reset state: the mem system is cleared out
when SysReset =>
SRAM_CE <= '1';
SRAM_OE <= '1';
ram_next_state <= CPUSlot0;
-- CPU access slot 0
when CPUSlot0 => -- pixel 1
-- configure SRAM for write, /WE controlled
SRAM_OE <= '1';
SRAM_WE <= '0';
SRAM_UB <= '0';
SRAM_LB <= '0';
-- put address for write slot on bus
SRAM_Addr <= row(8 downto 0) & col(9 downto 1);
SRAM_Data <= col(8 downto 1) & col(8 downto 1);
-- Was a word read out of the FIFO?
if fifo_read_pend='1'
then
SRAM_Addr <= fifo_read_data(17 downto 0);
SRAM_Data <= fifo_read_data(33 downto 18);
SRAM_UB <= fifo_read_data(35);
SRAM_LB <= fifo_read_data(34);
fifo_read_pend <= '0';
--else
end if;
ram_next_state <= CPUSlot1;
when CPUSlot1 =>
ram_next_state <= ReadAddrVideo;
-- process of reading data for video
when ReadAddrVideo => -- pixel 2
SRAM_UB <= '0';
SRAM_LB <= '0';
--if debug_bits(1 downto 0) = "00" then SRAM_Addr <= (row(8 downto 0) & col(9 downto 1)) + 0;
--elsif debug_bits(1 downto 0) = "01" then SRAM_Addr <= (row(8 downto 0) & col(9 downto 1)) + 1;
--elsif debug_bits(1 downto 0) = "10" then SRAM_Addr <= (row(8 downto 0) & col(9 downto 1)) - 1;
--end if;
SRAM_Addr <= (row(8 downto 0) & col(9 downto 1));
-- Request a readout of the FIFO, if it is not empty. There is a 2-cycle
-- delay between asserting rdreq and getting valid output data.
if fifo_rdempty='0'
then
fifo_rdreq <= '1';
fifo_read_pend <= '1';
end if;
ram_next_state <= ReadDataVideo;
-- Data is ready on SRAM, read it out and restore to idle state.
when ReadDataVideo =>
pxgen_data <= SRAM_Data;
ram_next_state <= CPUSlot0;
end case;
end process;
debug_state(1) <= ActiveDisplay;
end behavioral;
|
bsd-2-clause
|
1a1ee2edfb90e82c75debc22ef7b9420
| 0.608757 | 3.001405 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3081.vhd
| 4 | 4,064 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3081.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b02x00p05n01i03081ent IS
END c12s06b02x00p05n01i03081ent;
ARCHITECTURE c12s06b02x00p05n01i03081arch OF c12s06b02x00p05n01i03081ent IS
-- Define the resolution function we'll be using.
function WIRED_OR( Inputs: BIT_VECTOR) return BIT is
constant FLoatValue :BIT := '0';
begin
for I in Inputs'Range loop
if Inputs(I) = '1' then
return '1';
end if;
end loop;
return '0';
end;
-- Define the subtype that has this resolution function.
subtype RBIT is WIRED_OR BIT;
-- This signal will have its 'ACTIVE flag monitored.
signal MONITOR : RBIT := '0';
-- This signal will be used to check MONITOR'ACTIVE whenever
-- we want to verify that is value is OK.
signal CHECK : RBIT := '0';
BEGIN
TESTING: PROCESS
variable testOK : integer := 0;
BEGIN
-- Perform a signal value change on both signals.
MONITOR <= not MONITOR after 10 ns;
CHECK <= not CHECK after 10 ns;
wait on CHECK;
-- Verify that the flags say what we want.
assert( not( MONITOR'STABLE ) );
if (MONITOR'STABLE) then
testOK := 1;
end if;
assert( MONITOR'EVENT );
if (not(MONITOR'EVENT)) then
testOK := 1;
end if;
assert( MONITOR'ACTIVE );
if (not(MONITOR'ACTIVE)) then
testOK := 1;
end if;
assert( not( MONITOR'QUIET ) );
if (MONITOR'QUIET) then
testOK := 1;
end if;
-- Perform no signal value change on MONITOR.
MONITOR <= MONITOR after 10 ns;
CHECK <= not CHECK after 10 ns;
wait on CHECK;
-- Verify that the flags say what we want.
assert( MONITOR'STABLE );
if (not(MONITOR'STABLE)) then
testOK := 1;
end if;
assert( not( MONITOR'EVENT ) );
if (MONITOR'EVENT) then
testOK := 1;
end if;
assert( MONITOR'ACTIVE );
if (not(MONITOR'ACTIVE)) then
testOK := 1;
end if;
assert( not( MONITOR'QUIET ) );
if (MONITOR'QUIET) then
testOK := 1;
end if;
-- Perform no activity at all on MONITOR.
CHECK <= not CHECK after 10 ns;
wait on CHECK;
-- Verify that the flags say what we want.
assert( MONITOR'STABLE );
if (not(MONITOR'STABLE)) then
testOK := 1;
end if;
assert( not( MONITOR'EVENT ) );
if (MONITOR'EVENT) then
testOK := 1;
end if;
assert( not( MONITOR'ACTIVE ) );
if (MONITOR'ACTIVE) then
testOK := 1;
end if;
assert( MONITOR'QUIET );
if (not(MONITOR'QUIET)) then
testOK := 1;
end if;
assert NOT( testOK = 0 )
report "***PASSED TEST: c12s06b02x00p05n01i03081"
severity NOTE;
assert ( testOK = 0 )
report "***FAILED TEST: c12s06b02x00p05n01i03081 - A signal should be active if one of its sources is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p05n01i03081arch;
|
gpl-2.0
|
9986e520abd07c907365779b3dead7ba
| 0.620571 | 3.783985 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_09.vhd
| 4 | 2,414 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_09.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity bus_module is
port ( synch : inout std_ulogic; -- . . . );
-- not in book
other_port : in std_ulogic := 'U' );
-- end not in book
end entity bus_module;
--------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity bus_based_system is
end entity bus_based_system;
-- end not in book
architecture top_level of bus_based_system is
signal synch_control : std_logic;
-- . . .
begin
synch_control_pull_up : synch_control <= 'H';
bus_module_1 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
-- not in book
other_port => open );
-- end not in book
bus_module_2 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture top_level;
|
gpl-2.0
|
91381c8aa27f1c224cf460d0ca9487a5
| 0.492129 | 4.696498 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug23165/mwe_failing/mwe.vhd
| 3 | 795 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mwe is
end mwe;
architecture lulz of mwe is
constant cnt_len : integer := 2;
constant cnt_stages : integer := 2;
type ctl_sig is array (natural range <>) of std_logic_vector(cnt_len-1 downto 0);
signal ctl_cnt : ctl_sig(0 to cnt_stages-1);
signal clk : std_logic := '0';
begin
clk <= not clk after 50 ns;
controller : entity work.counter
generic map(
width => cnt_len
)
port map(
clk => clk,
q => ctl_cnt(0)
);
ctl_cnt_delay : process
begin
wait until rising_edge(clk);
for i in 0 to cnt_stages-2 loop
-- uncomment following line to see that the port map assignment works
-- and that this line just "overwrites" it..
ctl_cnt(i+1) <= ctl_cnt(i);
end loop;
end process;
end lulz;
|
gpl-2.0
|
70727dab0fcd6cfde12899333afed863
| 0.671698 | 2.809187 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.f-Mul.vhd
| 1 | 1,824 |
--------------------------------------------------------------------------------
-- FILE: Mul
-- DESC: Multiplier
--
-- Author:
-- Create: 2015-08-14
-- Update: 2015-08-14
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Mul is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE/2;
STAGE : integer := C_MUL_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
en: in std_logic;
lock: in std_logic;
sign: in std_logic;
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE*2-1 downto 0):=(others=>'0') -- Data Out
);
end Mul;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture mul_arch_struct of Mul is
component BoothMul is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE/2;
STAGE : integer := C_MUL_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
en: in std_logic;
lock: in std_logic;
sign: in std_logic;
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE*2-1 downto 0):=(others=>'0') -- Data Out
);
end component;
begin
BM0: BoothMul
generic map (DATA_SIZE, STAGE)
port map (rst, clk, en, lock, sign, a, b, o);
end mul_arch_struct;
|
mit
|
1a80ae38c7d805926d12eba0fd5c2071
| 0.463268 | 3.507692 | false | false | false | false |
mmoraless/ecc_vhdl
|
ecc_add/NewECCADD_131.vhd
| 1 | 6,089 |
------------------------------------------------------------------------
--Nueva implementacion ADD y Double en una misma arquitectura
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity ECC_add_serial_131 is
generic(
-- 163, 233, 277, 283, 409, 571
NUM_BITS : positive := 131
);
port(
xP: in std_logic_vector(NUM_BITS-1 downto 0);
yP: in std_logic_vector(NUM_BITS-1 downto 0);
xQ: in std_logic_vector(NUM_BITS-1 downto 0);
yQ: in std_logic_vector(NUM_BITS-1 downto 0);
---------------------------------------------
clk: in std_logic;
rst: in std_logic;
s0: in std_logic; -- 1 = Suma, 0 = Double
---------------------------------------------
X: out std_logic_vector(NUM_BITS-1 downto 0);
Y: out std_logic_vector(NUM_BITS-1 downto 0);
done: out std_logic
);
end;
------------------------------------------------------
architecture behave of ECC_add_serial_131 is
type CurrentState_type is (END_STATE, CHECK_INPUT, SPEND_CYCLE1, SPEND_CYCLE2,CALC_INV, CALC_MUL);
signal CurrentState : CurrentState_type;
constant cero : std_logic_vector(NUM_BITS-1 downto 0):= (others => '0');
--
signal S1 : std_logic_vector(NUM_BITS-1 downto 0);
signal not_s0 : std_logic;
-- 4 multiplexores
signal L3 : std_logic_vector(NUM_BITS-1 downto 0);
signal SQRin : std_logic_vector(NUM_BITS-1 downto 0);
signal Div1 : std_logic_vector(NUM_BITS-1 downto 0);
signal Div2 : std_logic_vector(NUM_BITS-1 downto 0);
--- interface con el inversor
signal rstInv : std_logic;
signal Division : std_logic_vector(NUM_BITS-1 downto 0);
signal doneInv : std_logic;
--- interface del multiplicador
signal rstMul : std_logic;
signal Multiplication : std_logic_vector(NUM_BITS-1 downto 0);
signal doneMul : std_logic;
--- interface del squarer
signal SQR : std_logic_vector(NUM_BITS-1 downto 0);
---------------------------------------------------------------
begin
---------------------------------------------------------------
-- Componentes
---------------------------------------------------------------
SQUARER_1 : entity squarer_131(behave)
--generic map (D, NUM2_BITS, NUM_BITS)
generic map (NUM_BITS)
port map(SQRin, SQR);
---------------------------------------------------------------
MUL_1: entity serial_multiplier_131(behave)
generic map (NUM_BITS)
port map(S1, SQRin, Multiplication,rstMul,clk,doneMul);
---------------------------------------------------------------
INV_1: entity f2m_divider_131(behave)
generic map (NUM_BITS)
port map(Div1, Div2, clk, rstInv, doneInv, Division);
---------------------------------------------------------------
---------------------------------------------------------------
LUT31: entity lut_3in(behave)
generic map (NUM_BITS)
port map(yQ, s0, yP, Div1);
---------------------------------------------------------------
---------------------------------------------------------------
LUT32: entity lut_3in(behave)
generic map (NUM_BITS)
port map(xQ, s0, xP, Div2);
---------------------------------------------------------------
---------------------------------------------------------------
LUT33: entity lut_3in(behave)
generic map (NUM_BITS)
port map(xP, not_s0, Division,SQRin);
---------------------------------------------------------------
---------------------------------------------------------------
LUT41: entity lut_3inadd(behave)
generic map (NUM_BITS)
port map(SQR, Division, Div2, L3);
---------------------------------------------------------------
-- Operaciones combinacionales (Sumas)
S1 <= L3 xor xP;
not_s0 <= not s0;
---------------------------------------------------------------
ADD_FSM: process (CLK)
Begin
if CLK'event and CLK = '1' then
-- Los datos de entrada deben estar presentes al llegar la señal de reset,
-- Si la señal Rst de entrada es síncrona con un reloj (i.e. es proporcionada
-- por un control en la subida del reloj), los datos a la entrada deben asignarse
-- junto con la señal de Rst o al momento de que Rst regrese a '0'
if Rst = '1' then
CurrentState <= CHECK_INPUT;
Done <= '0';
X <= (others =>'0');
Y <= (others =>'0');
rstInv <= '0';
rstMul <= '0';
else
case CurrentState is
when CHECK_INPUT =>
if (xP = cero) and (yP = cero) and s0 = '1' then -- add
X <= xQ;
Y <= yQ;
Done <= '1';
CurrentState <= END_STATE;
elsif (xQ = cero) and (yQ = cero) and s0 = '1' then -- Add
X <= xP;
Y <= yP;
Done <= '1';
CurrentState <= END_STATE;
elsif (xP = cero) and s0 = '0' then -- Double
Done <= '1';
CurrentState <= END_STATE;
else
rstInv <= '1'; -- calcular la division primero.
CurrentState <= SPEND_CYCLE1;
end if;
when SPEND_CYCLE1 => -- Provoca el pulso RST al modulo de inversion.
rstInv <= '0';
CurrentState <= CALC_INV;
when CALC_INV => -- Una vez que termina de calcular la division,
if doneInv = '1' then -- comienza con la multiplicación.
X <= L3;
rstMul <= '1';
CurrentState <= SPEND_CYCLE2;
end if;
when SPEND_CYCLE2 => -- Provoca el pulso RST en el multiplicador
rstMul <= '0';
CurrentState <= CALC_MUL;
when CALC_MUL => -- Espera que el multiplicador termine
if doneMul = '1' then
Y <= Multiplication xor L3 xor yP;
Done <= '1';
CurrentState <= END_STATE; -- Operación ADD terminada
end if;
when END_STATE =>
CurrentState <= END_STATE;
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
945d629401d231548ca4461db05c39f9
| 0.46855 | 3.784338 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/mult.vhd
| 2 | 7,391 |
---------------------------------------------------------------------
-- TITLE: Multiplication and Division Unit
-- AUTHORS: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mult.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the multiplication and division unit in 32 clocks.
--
-- To reduce space, compile your code using the flag "-mno-mul" which
-- will use software base routines in math.c if USE_SW_MULT is defined.
-- Then remove references to the entity mult in mlite_cpu.vhd.
--
-- MULTIPLICATION
-- long64 answer = 0
-- for(i = 0; i < 32; ++i)
-- {
-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
-- b = b >> 1;
-- }
--
-- DIVISION
-- long upper=a, lower=0;
-- a = b << 31;
-- for(i = 0; i < 32; ++i)
-- {
-- lower = lower << 1;
-- if(upper >= a && a && b < 2)
-- {
-- upper = upper - a;
-- lower |= 1;
-- }
-- a = ((b&2) << 30) | (a >> 1);
-- b = b >> 1;
-- }
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.mlite_pack.all;
entity mult is
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end; --entity mult
architecture logic of mult is
constant MODE_MULT : std_logic := '1';
constant MODE_DIV : std_logic := '0';
signal mode_reg : std_logic;
signal negate_reg : std_logic;
signal sign_reg : std_logic;
signal sign2_reg : std_logic;
signal count_reg : std_logic_vector(5 downto 0);
signal aa_reg : std_logic_vector(31 downto 0);
signal bb_reg : std_logic_vector(31 downto 0);
signal upper_reg : std_logic_vector(31 downto 0);
signal lower_reg : std_logic_vector(31 downto 0);
signal a_neg : std_logic_vector(31 downto 0);
signal b_neg : std_logic_vector(31 downto 0);
signal sum : std_logic_vector(32 downto 0);
begin
-- Result
c_mult <= lower_reg when mult_func = MULT_READ_LO and negate_reg = '0' else
bv_negate(lower_reg) when mult_func = MULT_READ_LO
and negate_reg = '1' else
upper_reg when mult_func = MULT_READ_HI else
ZERO;
pause_out <= '1' when (count_reg /= "000000") and
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) else '0';
-- ABS and remainder signals
a_neg <= bv_negate(a);
b_neg <= bv_negate(b);
sum <= bv_adder(upper_reg, aa_reg, mode_reg);
--multiplication/division unit
mult_proc: process(clk, reset_in, a, b, mult_func,
a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
variable count : std_logic_vector(2 downto 0);
begin
count := "001";
if reset_in = '1' then
mode_reg <= '0';
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
count_reg <= "000000";
aa_reg <= ZERO;
bb_reg <= ZERO;
upper_reg <= ZERO;
lower_reg <= ZERO;
elsif rising_edge(clk) then
case mult_func is
when MULT_WRITE_LO =>
lower_reg <= a;
negate_reg <= '0';
when MULT_WRITE_HI =>
upper_reg <= a;
negate_reg <= '0';
when MULT_MULT =>
mode_reg <= MODE_MULT;
aa_reg <= a;
bb_reg <= b;
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
when MULT_SIGNED_MULT =>
mode_reg <= MODE_MULT;
if b(31) = '0' then
aa_reg <= a;
bb_reg <= b;
sign_reg <= a(31);
else
aa_reg <= a_neg;
bb_reg <= b_neg;
sign_reg <= a_neg(31);
end if;
sign2_reg <= '0';
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
when MULT_DIVIDE =>
mode_reg <= MODE_DIV;
aa_reg <= b(0) & ZERO(30 downto 0);
bb_reg <= b;
upper_reg <= a;
count_reg <= "100000";
negate_reg <= '0';
when MULT_SIGNED_DIVIDE =>
mode_reg <= MODE_DIV;
if b(31) = '0' then
aa_reg(31) <= b(0);
bb_reg <= b;
else
aa_reg(31) <= b_neg(0);
bb_reg <= b_neg;
end if;
if a(31) = '0' then
upper_reg <= a;
else
upper_reg <= a_neg;
end if;
aa_reg(30 downto 0) <= ZERO(30 downto 0);
count_reg <= "100000";
negate_reg <= a(31) xor b(31);
when others =>
if count_reg /= "000000" then
if mode_reg = MODE_MULT then
-- Multiplication
if bb_reg(0) = '1' then
upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
lower_reg <= sum(0) & lower_reg(31 downto 1);
sign2_reg <= sign2_reg or sign_reg;
sign_reg <= '0';
bb_reg <= '0' & bb_reg(31 downto 1);
-- The following six lines are optional for speedup
elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
count_reg(5 downto 2) /= "0000" then
upper_reg <= "0000" & upper_reg(31 downto 4);
lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
count := "100";
bb_reg <= "0000" & bb_reg(31 downto 4);
else
upper_reg <= sign2_reg & upper_reg(31 downto 1);
lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
else
-- Division
if sum(32) = '0' and aa_reg /= ZERO and
bb_reg(31 downto 1) = ZERO(31 downto 1) then
upper_reg <= sum(31 downto 0);
lower_reg(0) <= '1';
else
lower_reg(0) <= '0';
end if;
aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
lower_reg(31 downto 1) <= lower_reg(30 downto 0);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
count_reg <= count_reg - count;
end if; --count
end case;
end if;
end process;
end; --architecture logic
|
mit
|
e48e09e45bf6651b34cbbc9796a51469
| 0.444324 | 3.744174 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-snk.vhd
| 4 | 2,136 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-snk.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
architecture sink of test_bench is
use qsim.qsim_types.all;
use random.random.all;
signal a : arc_type;
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(1),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => a,
info_detail => info_detail );
sink1 : entity qsim.sink(behavior)
generic map ( name => "sink1",
time_unit => ns,
info_file_name => "sink1.dat" )
port map ( in_arc => a,
info_detail => info_detail );
monitor : process is
variable L : line;
begin
wait on a;
write(L, string'("monitor: at "));
write(L, now, unit => ns);
write(L, string'(" received "));
write(L, a.token, ns);
writeline(output, L);
end process monitor;
end architecture sink;
|
gpl-2.0
|
5ae8aaa0c8686b933c1ca28d624422c9
| 0.582865 | 4.007505 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd
| 4 | 2,183 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity NMOS_transistor_wa is
port ( terminal gate, drain, source : electrical );
end entity NMOS_transistor_wa;
----------------------------------------------------------------
architecture noisy of NMOS_transistor_wa is
quantity vgs across igs through gate to source;
quantity vds across ids through drain to source;
quantity vsd across source to drain;
quantity vgd across igd through gate to drain;
constant threshold_voltage : voltage := 1.0;
constant k : real := 1.0e-5;
-- declare quantity in frequency domain for AC analysis
begin
if vds >= 0.0 use -- transistor is forward biased
if vgs < threshold_voltage use -- cutoff region
ids == 0.0;
elsif vds > vgs - threshold_voltage use -- saturation region
ids == 0.5 * k * (vgs - threshold_voltage)**2;
else -- linear/triode region
ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
end use;
else -- transistor is reverse biased
if vgd < threshold_voltage use -- cutoff region
ids == 0.0;
elsif vsd > vgd - threshold_voltage use -- saturation region
ids == -0.5 * k * (vgd - threshold_voltage)**2;
else -- linear/triode region
ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
end use;
end use;
igs == 0.0;
igd == 0.0;
end architecture noisy;
|
gpl-2.0
|
f8c5fd4a909687d918118378003791a7
| 0.668346 | 3.990859 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_09.vhd
| 4 | 1,948 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_ch_18_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_18_09 is
end entity ch_18_09;
----------------------------------------------------------------
architecture test of ch_18_09 is
begin
process is
use std.textio.all;
variable L : line;
begin
write(L, 42, justified => left, field => 5);
writeline(output, L);
write(L, 42, justified => right, field => 5);
writeline(output, L);
write(L, 123, field => 2);
writeline(output, L);
-- code from book:
write ( L, string'( "fred" ) );
write ( L, ' ' );
write ( L, bit_vector'( X"3A" ) );
-- end of code from book
writeline(output, L);
write(L, 3.14159, digits => 2);
writeline(output, L);
write(L, 123.4567, digits => 0);
writeline(output, L);
write(L, 40 ns, unit => ps);
writeline(output, L);
write(L, 23 us, unit => ms);
writeline(output, L);
wait;
end process;
end architecture test;
|
gpl-2.0
|
760f2a06677d2b4544546e28b351961e
| 0.570842 | 3.872763 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2089.vhd
| 4 | 2,085 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2089.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02089ent IS
END c07s02b04x00p20n01i02089ent;
ARCHITECTURE c07s02b04x00p20n01i02089arch OF c07s02b04x00p20n01i02089ent IS
TYPE bit_v is array (integer range <>) of bit;
SUBTYPE bit_4 is bit_v (1 to 4);
SUBTYPE bit_null is bit_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : bit_4;
variable l_operand : bit_4 := ('1','0','1','0');
variable r_operand : bit_null;
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result = ('1','0','1','0')) and (result(1) = '1'))
report "***PASSED TEST: c07s02b04x00p20n01i02089"
severity NOTE;
assert ((result = ('1','0','1','0')) and (result(1) = '1'))
report "***FAILED TEST: c07s02b04x00p20n01i02089 - Concatenation of null and BIT array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02089arch;
|
gpl-2.0
|
cb5f9dad255c76a5ad5ae6cc61893169
| 0.639808 | 3.51602 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2010.vhd
| 4 | 1,954 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2010.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02010ent IS
END c07s02b02x00p10n01i02010ent;
ARCHITECTURE c07s02b02x00p10n01i02010arch OF c07s02b02x00p10n01i02010ent IS
BEGIN
TESTING: PROCESS
type a1 is array (1 to 5) of integer;
variable a : a1 := (1,2,3,4,5);
variable b : a1 := (2,3,4,5,6);
variable k : integer := 0;
BEGIN
if ((a < b) or (a <= b) or (a > b) or (a >= b)) then
-- No_failure_here
k := 5;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p10n01i02010"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p10n01i02010 - Ordering operators are defined only for scalar type or any discrete array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02010arch;
|
gpl-2.0
|
9c038762553d327b0ed74fd082dd7481
| 0.648414 | 3.520721 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Guerric/Modular/guerric_modular.vhd
| 1 | 5,662 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- control signals
signal en_VS, C_0, C_1, C_2, C_3, ISPos: std_logic;
signal V, S,X2, Y2, u_pad, r_pad : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, R : STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- Internal registers
signal u_div_2, v_div_2, r_div_2, s_div_2, p_div_2: STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- Internal registers
signal D: STD_LOGIC_VECTOR(3 downto 0); -- Internal registers
signal counter: STD_LOGIC_VECTOR(8 downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, LOAD2, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
X2 <= x & '0';
Y2 <= y & '0';
u_pad <= '0' & U;
R_pad <= '0' & R;
U_div_2 <= '0' & U(NUM_BITS-1 downto 1);
R_div_2 <= '0' & R(NUM_BITS-1 downto 1);
P_div_2 <= p(NUM_BITS downto 1);
S_div_2 <= S(NUM_BITS downto 1);
V_div_2 <= V(NUM_BITS downto 1);
--carga 2x, 2y --carga p, 0 carga U, R
en_VS <= '1' when rst = '1' or CurrentState = LOAD1 or (U(0) = '1' and IsPos = '0') else
'0';
c_0 <= '1' when CurrentState = LOAD1 or U(0) = '1' else
'0';
c_2 <= '0' when rst = '1' else
'1';
c_1 <= '0' when rst = '1' or currentState = LOAD1 else
'1';
c_3 <= '0' when (CurrentState = LOAD1 or R(0) = '0') else
'1';
celda_reg_u: entity work.celda_u(behave)
port map( V_div_2,U_div_2,c_0,clk,rst,U);
celda_reg_r: entity work.celda_r(behave)
port map(R_div_2, P_div_2, S_div_2, c_3, c_0, clk, rst, R);
celda_reg_v: entity work.celda_v(behave)
port map(u_pad,P,Y2,c_1,c_2,en_VS,clk,V);
celda_reg_s: entity work.celda_s(behave)
port map(R_pad,X2,c_1,c_2,en_VS,clk,S);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
x_div_y <= (others => '0');
done <= '0';
counter <= "101001000"; --2*m - 2
IsPos <= '0';
D <= "0001";
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
currentState <= Cycle;
when CYCLE =>
counter <= counter - 1;
if U(0) = '0' then
if IsPos = '0' then D <= D + 1;
elsif D = "0000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
elsif IsPos = '1' then
if D = "0000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
else
D <= D - 1;
IsPos <= '1';
end if;
if counter = "000000000" then
done <= '1';
x_div_y <= S(NUM_BITS-1 downto 0);
CurrentState <= END_STATE;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
dc2036d0f3278ae27ab759151aececb8
| 0.409749 | 3.841248 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.b.a.b-tbShifter.vhd
| 1 | 1,788 |
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
entity tbShifter is
end tbShifter;
architecture tb_shifter_arch of tbShifter is
constant N: integer:=32;
signal a, b : std_logic_vector(N-1 downto 0):=x"00000000";
signal o_sll, o_srl, o_sla, o_sra, o_slr_0, o_srr_0, o_slr_1, o_srr_1: std_logic_vector(N-1 downto 0):=x"00000000";
component Shifter is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
l_r : in std_logic; -- LEFT/RIGHT
l_a : in std_logic; -- LOGIC/ARITHMETIC
s_r : in std_logic; -- SHIFT/ROTATE
a : in std_logic_vector(DATA_SIZE-1 downto 0);
b : in std_logic_vector(DATA_SIZE-1 downto 0);
o : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
begin
SH0 : Shifter
generic map(N)
port map('0', '0', '0', a, b, o_sll);
SH1 : Shifter
generic map(N)
port map('1', '0', '0', a, b, o_srl);
SH2 : Shifter
generic map(N)
port map('0', '1', '0', a, b, o_sla);
SH3 : Shifter
generic map(N)
port map('1', '1', '0', a, b, o_sra);
SH4 : Shifter
generic map(N)
port map('0', '0', '1', a, b, o_slr_0);
SH5 : Shifter
generic map(N)
port map('1', '0', '1', a, b, o_srr_0);
SH6 : Shifter
generic map(N)
port map('0', '1', '1', a, b, o_slr_1);
SH7 : Shifter
generic map(N)
port map('1', '1', '1', a, b, o_srr_1);
a <= x"ffffffff", x"04532434" after 1 ns, x"2234e826" after 2 ns, x"a323f443" after 3 ns, x"8b651a8b" after 4 ns, x"ffffffff" after 5 ns;
b <= x"00000001", x"05335f28" after 1.5 ns, x"23323424" after 2.5 ns, x"11645030" after 3.5 ns, x"030035a6" after 4.5 ns, x"00000001" after 5.5 ns, x"12334224" after 7 ns;
end tb_shifter_arch;
configuration tb_shifter_cfg of tbShifter is
for tb_shifter_arch
end for;
end tb_shifter_cfg;
|
mit
|
3fe144d05caba81a8f0ce0d2454f4982
| 0.633669 | 2.343381 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc350.vhd
| 4 | 2,333 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc350.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p01n01i00350ent IS
END c03s02b01x01p01n01i00350ent;
ARCHITECTURE c03s02b01x01p01n01i00350arch OF c03s02b01x01p01n01i00350ent IS
BEGIN
TESTING: PROCESS
variable V1 : STRING(1 to 20);
subtype ST is STRING(1 to 10);
variable V2 : ST;
BEGIN
assert V1'LEFT = 1;
assert V1'RIGHT = 20;
assert ST'LEFT = 1;
assert ST'RIGHT = 10;
assert V2'LEFT = 1;
assert V2'RIGHT = 10;
assert NOT( V1'LEFT = 1 and
V1'RIGHT = 20 and
ST'LEFT = 1 and
ST'RIGHT = 10 and
V2'LEFT = 1 and
V2'RIGHT = 10 )
report "***PASSED TEST: c03s02b01x01p01n01i00350"
severity NOTE;
assert ( V1'LEFT = 1 and
V1'RIGHT = 20 and
ST'LEFT = 1 and
ST'RIGHT = 10 and
V2'LEFT = 1 and
V2'RIGHT = 10 )
report "***FAILED TEST: c03s02b01x01p01n01i00350 - Index constraint test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p01n01i00350arch;
|
gpl-2.0
|
812836b574fc2929590790ad785dc3c3
| 0.587655 | 3.668239 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd
| 4 | 5,136 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity resistor is
generic ( res : resistance );
port ( terminal p1, p2 : electrical );
end entity resistor;
architecture ideal of resistor is
quantity v across i through p1 to p2;
begin
v == i * res;
end architecture ideal;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
generic ( cap : resistance );
port ( terminal p1, p2 : electrical );
end entity capacitor;
architecture ideal of capacitor is
quantity v across i through p1 to p2;
begin
i == cap * v'dot;
end architecture ideal;
-- end not in book
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity lowpass is
generic ( gain : real := 1.0; -- gain for 'dot, 'ltf, and 'ztf
fp : real := 10.0; -- pole in Hz for 'dot, 'ltf, and 'ztf
Fsmp : real := 10.0e3 ); -- sample frequency for ztf
port ( terminal input: electrical;
terminal output: electrical );
end entity lowpass;
----------------------------------------------------------------
architecture RC of lowpass is
constant cap : real := 1.0e-6;
constant res : real := 1.0 / (math_2_pi * cap * fp);
begin
assert false
report "gain is ignored in architecture RC" severity note;
assert false
report "Fsmp is not used in architecture RC" severity note;
R : entity work.resistor(ideal)
generic map( res => res )
port map( p1 => input, p2 => output );
C : entity work.capacitor(ideal)
generic map( cap => cap )
port map( p1 => output, p2 => electrical_ref );
end architecture RC;
----------------------------------------------------------------
architecture dot of lowpass is
quantity vin across input to electrical_ref;
quantity vout across iout through output to electrical_ref;
constant wp : real := fp * math_2_pi; -- pole in rad/s
constant tp : real := 1.0 / wp; -- time constant
begin
assert false
report "Fsmp is not used in architecture dot" severity note;
vin == (vout + tp * vout'dot) / gain;
end architecture dot;
----------------------------------------------------------------
architecture ltf of lowpass is
quantity vin across input to electrical_ref;
quantity vout across iout through output to electrical_ref;
constant wp : real := fp * math_2_pi; -- pole in rad/s
constant num : real_vector := (0 => wp);
constant den : real_vector := (wp, 1.0);
begin
assert false
report "Fsmp is not used in architecture ltf" severity note;
vout == gain*vin'ltf(num, den);
end architecture ltf;
----------------------------------------------------------------
architecture z_minus_1 of lowpass is
quantity vin across input to electrical_ref;
quantity vout across iout through output to electrical_ref;
quantity vin_sampled : real; -- sampled input
quantity vin_zm1, vout_zm1 : real; -- z**-1
constant Tsmp : real := 1.0 / Fsmp; -- sample period
constant wp : real := fp * math_2_pi; -- pole in rad/s
constant n0 : real := Tsmp * wp; -- z0 numerator coefficient
constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient
constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient
constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient
begin
vin_sampled == gain*vin'zoh(Tsmp);
vin_zm1 == vin_sampled'delayed(Tsmp);
vout_zm1 == vout'delayed(Tsmp);
vout == vin_sampled * n0 / d0 + n1 * vin_zm1 / d0 - d1 * vout_zm1 / d0;
end z_minus_1;
----------------------------------------------------------------
architecture ztf of lowpass is
quantity vin across input to electrical_ref;
quantity vout across iout through output to electrical_ref;
constant Tsmp : real := 1.0 / Fsmp; -- sample period
constant wp : real := fp * math_2_pi; -- pole in rad/s
constant n0 : real := Tsmp * wp; -- z0 numerator coefficient
constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient
constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient
constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient
constant num : real_vector := (n0, n1);
constant den : real_vector := (d0, d1);
begin
vout == gain*vin'ztf(num, den, Tsmp);
end ztf;
|
gpl-2.0
|
7afdde96191d5400d31f305209fd2d75
| 0.629868 | 3.827124 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.0-Reg.vhd
| 1 | 1,256 |
--------------------------------------------------------------------------------
-- FILE: Reg
-- DESC: Generic asyncronous register, with RESET and ENABLE
--
-- Author:
-- Create: 2015-05-27
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Reg is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
rst: in std_logic;
en : in std_logic;
clk: in std_logic;
din: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end Reg;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture reg_arch of Reg is -- Asyncronous
begin
PROC2: process(clk, rst)
begin
if rst='0' then -- Reset active low
dout <= (others => '0');
elsif rising_edge(clk) and en='1' then -- Enable active high
dout <= din;
end if;
end process;
end reg_arch;
|
mit
|
00270389d2d3df61c33db7a7cdc08cbe
| 0.405255 | 4.361111 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.vhd
| 1 | 22,716 |
--------------------------------------------------------------------------------
-- FILE: DataPath
-- DESC: Datapath of DLX
--
-- Author:
-- Create: 2015-05-24
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DataPath is
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
OPCD_SIZE : integer := C_SYS_OPCD_SIZE;
IMME_SIZE : integer := C_SYS_IMME_SIZE;
CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Datapath Contrl Word
CALU_SIZE : integer := C_CTR_CALU_SIZE;
DRCW_SIZE : integer := C_CTR_DRCW_SIZE
);
port (
clk : in std_logic;
rst : in std_logic;
istr_addr : out std_logic_vector(ADDR_SIZE-1 downto 0);
istr_val : in std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
ir_out : out std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
pc_out : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
reg_a_out : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
ld_a_out : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
data_addr : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
data_i_val : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
data_o_val : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
cw : in std_logic_vector(CWRD_SIZE-1 downto 0):=(others=>'0');
dr_cw : out std_logic_vector(DRCW_SIZE-1 downto 0):=(others=>'0');
calu : in std_logic_vector(CALU_SIZE-1 downto 0):=(others=>'0');
sig_bal : out std_logic:='0';
sig_bpw : in std_logic:='0';
sig_jral : out std_logic:='0';
sig_ral : out std_logic:='0';
sig_mul : out std_logic:='0';
sig_div : out std_logic:='0';
sig_sqrt : out std_logic:='0'
);
end DataPath;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture data_path_arch of DataPath is
component Mux is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
sel: in std_logic;
din0: in std_logic_vector(DATA_SIZE-1 downto 0);
din1: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Mux4 is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
sel: in std_logic_vector(1 downto 0);
din0: in std_logic_vector(DATA_SIZE-1 downto 0);
din1: in std_logic_vector(DATA_SIZE-1 downto 0);
din2: in std_logic_vector(DATA_SIZE-1 downto 0);
din3: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Reg is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
rst: in std_logic;
en : in std_logic;
clk: in std_logic;
din: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Adder is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
cin: in std_logic;
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
s : out std_logic_vector(DATA_SIZE-1 downto 0);
cout: out std_logic
);
end component;
component RegisterFile is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_NUM : integer := C_REG_NUM
);
port(
clk : in std_logic; -- clock
rst : in std_logic; -- reset
en : in std_logic; -- enable
rd1_en : in std_logic; -- read port 1
rd2_en : in std_logic; -- read port 2
wr_en : in std_logic; -- write port
link_en : in std_logic;
rd1_addr: in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of read port 1
rd2_addr: in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of read port 2
wr_addr : in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of write port
d_out1 : out std_logic_vector(DATA_SIZE-1 downto 0); -- data out 1 bus
d_out2 : out std_logic_vector(DATA_SIZE-1 downto 0); -- data out 2 bus
d_in : in std_logic_vector(DATA_SIZE-1 downto 0); -- data in bus
d_link : in std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Alu is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
f : in std_logic_vector(4 downto 0); -- Function
a : in std_logic_vector(DATA_SIZE-1 downto 0); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0); -- Data B
o : out std_logic_vector(DATA_SIZE-1 downto 0) -- Data Out
);
end component;
component Mul is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE/2;
STAGE : integer := C_MUL_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
en: in std_logic;
lock: in std_logic;
sign: in std_logic;
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE*2-1 downto 0):=(others=>'0') -- Data Out
);
end component;
component Div is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
DIV_STAGE : integer := C_DIV_STAGE;
SQRT_STAGE : integer := C_SQRT_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
en: in std_logic:='0';
lock: in std_logic:='0';
sign: in std_logic:='0';
func: in std_logic:='0';
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0') -- Data Out
);
end component;
component Extender is
generic(
SRC_SIZE : integer := 1;
DEST_SIZE: integer := C_SYS_DATA_SIZE
);
port(
s : std_logic := '0';
i : in std_logic_vector(SRC_SIZE-1 downto 0);
o : out std_logic_vector(DEST_SIZE-1 downto 0)
);
end component;
component FwdMux1 is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_ADDR_SIZE : integer := MyLog2Ceil(C_REG_NUM)
);
port(
reg_c : in std_logic_vector(DATA_SIZE-1 downto 0);
reg_f : in std_logic_vector(DATA_SIZE-1 downto 0);
addr_c : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
addr_f : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
valid_f : in std_logic;
dirty_f : in std_logic;
output : out std_logic_vector(DATA_SIZE-1 downto 0);
match_dirty_f: out std_logic
);
end component;
component FwdMux2 is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_ADDR_SIZE : integer := MyLog2Ceil(C_REG_NUM)
);
port(
reg_c : in std_logic_vector(DATA_SIZE-1 downto 0);
reg_f : in std_logic_vector(DATA_SIZE-1 downto 0);
reg_ff : in std_logic_vector(DATA_SIZE-1 downto 0);
addr_c : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
addr_f : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
addr_ff : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
valid_f : in std_logic;
valid_ff: in std_logic;
dirty_f : in std_logic;
dirty_ff: in std_logic;
en : in std_logic:='1';
output : out std_logic_vector(DATA_SIZE-1 downto 0);
match_dirty_f : out std_logic;
match_dirty_ff : out std_logic
);
end component;
constant REG_NUM : integer := C_REG_NUM;
constant REG_ADDR_SIZE : integer := MyLog2Ceil(REG_NUM);
constant MUL_STAGE : integer := C_MUL_STAGE;
constant DIV_STAGE : integer := C_DIV_STAGE;
constant SQRT_STAGE : integer := C_SQRT_STAGE;
-- Program Counters
signal s1_pc, s2_pc, s1_jpc, s2_jpc, s1_npc, s2_npc: std_logic_vector(ADDR_SIZE-1 downto 0):= (others=>'0');
signal s1_4 : std_logic_vector(DATA_SIZE-1 downto 0) := (2 => '1', others => '0');
-- Instruction
signal s2_istr : std_logic_vector(ISTR_SIZE-1 downto 0):= (others=>'0');
-- Register File
signal s2_rf_en : std_logic:='0';
signal s2_rd1_addr, s3_rd1_addr, s2_rd2_addr, s3_rd2_addr, s4_rd2_addr, s2_wr_addr, s2_wr_addr_r, s2_wr_addr_i, s3_wr_addr, s4_wr_addr, s5_wr_addr, s6_wr_addr : std_logic_vector(REG_ADDR_SIZE-1 downto 0):=(others=>'0');
signal s2_wr_addr_sel: std_logic:='0';
-- ALU operands
signal s2_a, s2_b, s3_a, s3_b, s4_a, s4_b : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s2_imm_i : std_logic_vector(IMME_SIZE-1 downto 0):=(others=>'0');
signal s2_imm_j : std_logic_vector(ISTR_SIZE-OPCD_SIZE-1 downto 0):=(others=>'0');
signal s2_imm_l_ext, s2_imm_h_ext, s2_imm_j_ext, s2_imm_i_ext, s3_imm_i_ext : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s3_a_keep, s3_b_keep, s3_a_sel, s3_b_fwd, s3_b_sel, s4_b_fwd : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s3_mul_op, s3_div_op, s3_sqrt_op, s3_div_sqrt_op : std_logic:='0';
signal s3_exe_sel : std_logic_vector(1 downto 0):= "00";
signal s3_alu_out, s3_mul_out, s3_div_out, s3_exe_out, s4_exe_out : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s3_mul_lock, s3_div_lock, s3_mul_sign, s3_div_sign:std_logic:='0';
signal s4_mem_in, s4_mem_out : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s4_result, s5_result, s6_result : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s3_reg_a_wait, s3_reg_b_wait: std_logic:='0';
signal s2_jump_addr_imm, s2_jump_addr_rel, s2_jump_addr_reg:std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
signal s2_branch_flag, s2_jr_flag, s2_j_flag, s2_jump_flag, s3_jump_flag: std_logic;
signal s2_a_f_b_en, s2_a_ff_b_en, s2_a_f_j_en, s2_a_ff_j_en: std_logic;
signal s4_reg_a_wait, s4_reg_b_wait: std_logic:='0';
signal s3_a_sel_f_en,s3_a_sel_ff_en, s3_b_sel_f_en, s3_b_sel_ff_en:std_logic;
signal s2_jump_test:std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
signal s2_pc_sel, s2_pc_notsel, s3_pc_notsel:std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
signal s6_en_wb: std_logic:='0';
begin
-- PIPELINE STATE 1 : [IF]
istr_addr <= s1_pc; -- to IRAM
-- NPC=PC+4
ADD_4: Adder
generic map (ADDR_SIZE)
port map ('0', s1_pc, s1_4, s1_npc, open);
MUX_bpw: Mux
generic map(ADDR_SIZE)
port map (sig_bpw, s2_pc_sel, s3_pc_notsel, s1_pc);
-- REGISTERS : [IF]||[ID]
REG_PC: Reg
generic map (ADDR_SIZE)
port map (rst, cw(CW_S1_LATCH), clk, s1_pc, s2_pc);
REG_NPC: Reg
generic map (ADDR_SIZE)
port map (rst, cw(CW_S1_LATCH), clk, s1_npc, s2_npc);
-- PIPELINE STAGE 2: [ID]
s2_istr <= istr_val; -- from IRAM
ir_out <= s2_istr; -- to Control Unit
pc_out <= s2_pc;
s2_rd1_addr <= s2_istr(ISTR_SIZE-OPCD_SIZE-1 downto ISTR_SIZE-OPCD_SIZE-REG_ADDR_SIZE);
s2_rd2_addr <= s2_istr(ISTR_SIZE-OPCD_SIZE-REG_ADDR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE-2*REG_ADDR_SIZE);
s2_imm_i <= s2_istr(IMME_SIZE-1 downto 0);
s2_imm_j <= s2_istr(ISTR_SIZE-OPCD_SIZE-1 downto 0);
-- Choose from NPC and JUMP ADDRESS in case of JUMP.
MUX_PC: Mux
generic map (ADDR_SIZE)
port map (cw(CW_S2_JUMP), s2_npc, s2_jpc, s2_pc_sel);
MUX_NOTPC: Mux
generic map (ADDR_SIZE)
port map (cw(CW_S2_JUMP), s2_jpc, s2_npc, s2_pc_notsel);
----------------------------------------------------------------------------
-- FIXME
-- Weired!!!
-- Have to set the highest bit to 0 to avoid "Bound check failure"
----------------------------------------------------------------------------
s2_jpc <= s2_jump_test and x"7fffffff";
----------------------------------------------------------------------------
-- NOTE:
-- This process is used to extract the correct write back address from instruction.
-- If it's a R-TYPE instruction, the write back address should be s2_wr_addr_r,
-- ohterwise, it should be s2_wr_addr_i.
----------------------------------------------------------------------------
s2_wr_addr_r <= s2_istr(ISTR_SIZE-OPCD_SIZE-2*REG_ADDR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE-3*REG_ADDR_SIZE);
s2_wr_addr_i <= s2_istr(ISTR_SIZE-OPCD_SIZE-REG_ADDR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE-2*REG_ADDR_SIZE);
P0:process(s2_istr(ISTR_SIZE-1 downto OPCD_SIZE))
begin
if (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_R) then
s2_wr_addr_sel <= '0'; -- R_TYPE
elsif (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_F) then
s2_wr_addr_sel <= '0'; -- F_TYPE
else
s2_wr_addr_sel <= '1'; -- OTHER TYPES
end if;
end process;
MUX_WB_ADDR: Mux
generic map (REG_ADDR_SIZE)
port map (s2_wr_addr_sel, s2_wr_addr_r, s2_wr_addr_i, s2_wr_addr);
----------------------------------------------------------------------------
-- NOTE:
-- This 3 extenders are used to extend variable/address. The L-EXTENDER extends
-- immediate variable as well as relative address in either signed or unsigned
-- mode; While the J-EXTENDER deal with the 26-bit relative address in signed mode.
-- The H-EXTENDER extends 16-bit variable with 0s in lower side.(ONLY FOR LHI)
----------------------------------------------------------------------------
EXT_L: Extender
generic map(IMME_SIZE, DATA_SIZE)
port map(cw(CW_S2_EXT_S), s2_imm_i, s2_imm_l_ext);
EXT_J: Extender
generic map(ISTR_SIZE-OPCD_SIZE, ADDR_SIZE)
port map('1', s2_imm_j, s2_imm_j_ext);
-- EXT_H
s2_imm_h_ext(DATA_SIZE-1 downto DATA_SIZE/2) <= s2_imm_i;
s2_imm_h_ext(DATA_SIZE/2-1 downto 0) <= (others=>'0');
-- EXT_I final
s2_imm_i_ext <= s2_imm_h_ext when s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_LHI else s2_imm_l_ext;
----------------------------------------------------------------------------
-- NOTE:
-- Register File
----------------------------------------------------------------------------
s2_rf_en <= (cw(CW_S2_LATCH) or cw(CW_S5_EN_WB));
RF0: RegisterFile
generic map(DATA_SIZE, REG_NUM)
port map(clk, rst, s2_rf_en, cw(CW_S2_LATCH), cw(CW_S2_LATCH), cw(CW_S5_EN_WB), cw(CW_S2_LINK), s2_rd1_addr, s2_rd2_addr, s5_wr_addr, s2_a, s2_b, s5_result, s2_npc);
----------------------------------------------------------------------------
-- NOTE:
-- Jump address calculation
----------------------------------------------------------------------------
MUX_JPC0: Mux
generic map (ADDR_SIZE)
port map (cw(CW_S2_SEL_JA_0), s2_imm_i_ext, s2_imm_j_ext, s2_jump_addr_imm);
ADDER_ADDR: Adder
generic map(ADDR_SIZE)
port map('0', s2_npc, s2_jump_addr_imm, s2_jump_addr_rel, open);
MUX_JPC1: Mux
generic map (ADDR_SIZE)
port map (cw(CW_S2_SEL_JA_1), s2_jump_addr_rel, s2_jump_addr_reg, s2_jump_test);
PROG: process(s2_istr, s2_branch_flag,s2_jr_flag,s2_j_flag)
begin
if (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_BEQZ) or (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_BNEZ) then
s2_branch_flag <= '1';
else
s2_branch_flag <= '0';
end if;
if (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_JR) or (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_JALR) then
s2_jr_flag <= '1';
else
s2_jr_flag <= '0';
end if;
if (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_J) or (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_JAL) then
s2_j_flag <= '1';
else
s2_j_flag <= '0';
end if;
s2_jump_flag <= s2_branch_flag or s2_jr_flag or s2_j_flag;
end process;
s2_a_f_b_en <= cw(CW_S3_WB_FLAG) and s2_branch_flag;
s2_a_ff_b_en <= cw(CW_S4_WB_FLAG) and s2_branch_flag;
FWDMUX_2AB: FwdMux2
generic map(DATA_SIZE, REG_ADDR_SIZE)
port map(s2_a, s3_exe_out, s4_result, s2_rd1_addr, s3_wr_addr, s4_wr_addr, s2_a_f_b_en, s2_a_ff_b_en, cw(CW_S3_LD_FLAG), '0', '1', reg_a_out, sig_bal, open);
s2_a_f_j_en <= cw(CW_S3_WB_FLAG) and s2_jr_flag;
s2_a_ff_j_en <= cw(CW_S4_WB_FLAG) and s2_jr_flag;
FWDMUX_2AJ: FwdMux2
generic map(DATA_SIZE, REG_ADDR_SIZE)
port map(s2_a, s3_exe_out, s4_result, s2_rd1_addr, s3_wr_addr, s4_wr_addr, s2_a_f_j_en, s2_a_ff_j_en, cw(CW_S3_LD_FLAG), '0', '1', s2_jump_addr_reg, sig_jral, open);
-- REGISTERS : [ID]||[EXE]
REG_A: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_a, s3_a);
REG_B: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_b, s3_b);
REG_I: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_imm_i_ext, s3_imm_i_ext);
REG_WR2: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_wr_addr, s3_wr_addr);
REG_A_ADDR_2: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_rd1_addr, s3_rd1_addr);
REG_B_ADDR_2: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_rd2_addr, s3_rd2_addr);
REG_PC_NOT_SEL: Reg
generic map(ADDR_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_pc_notsel, s3_pc_notsel);
PROCJUMPFLAG: process(clk)
begin
if rising_edge(clk) and cw(CW_S2_LATCH)='1' then
s3_jump_flag <= s2_jump_flag;
end if;
end process;
-- PIPELIE STAGE 3 : [EXE]
MUX_KEEP_A:Mux
generic map(DATA_SIZE)
port map(s4_reg_b_wait, s3_a, s4_a, s3_a_keep);
MUX_KEEP_B:Mux
generic map(DATA_SIZE)
port map(s4_reg_a_wait, s3_b, s4_b, s3_b_keep);
----------------------------------------------------------------------------
-- NOTE:
-- When stage 3 is JUMP/BRANCH instruction, no need to forward, because JUMP/BRANCH
-- instructions have nothing to do in stage 3,4 and 5.
----------------------------------------------------------------------------
s3_a_sel_f_en <= cw(CW_S4_WB_FLAG) and (not s3_jump_flag);
s3_a_sel_ff_en <= cw(CW_S5_EN_WB) and (not s3_jump_flag);
FWDMUX_A: FwdMux2
generic map(DATA_SIZE, REG_ADDR_SIZE)
port map(s3_a_keep, s4_exe_out, s5_result, s3_rd1_addr, s4_wr_addr, s5_wr_addr, s3_a_sel_f_en, s3_a_sel_ff_en, cw(CW_S4_LD_FLAG), '0', '1', s3_a_sel, s3_reg_a_wait, open);
s3_b_sel_f_en <= cw(CW_S4_WB_FLAG) and (not cw(CW_S3_SEL_B)) and (not s3_jump_flag);
s3_b_sel_ff_en <= cw(CW_S5_EN_WB) and (not cw(CW_S3_SEL_B)) and (not s3_jump_flag);
FWDMUX_B: FwdMux2
generic map(DATA_SIZE, REG_ADDR_SIZE)
port map(s3_b_keep, s4_exe_out, s5_result, s3_rd2_addr, s4_wr_addr, s5_wr_addr, s3_b_sel_f_en, s3_b_sel_ff_en, cw(CW_S4_LD_FLAG), '0', '1', s3_b_fwd, s3_reg_b_wait, open);
PW: process(s3_reg_a_wait, s3_reg_b_wait)
begin
sig_ral<=(s3_reg_a_wait or s3_reg_b_wait);
end process;
MUXB: Mux
generic map(DATA_SIZE)
port map(cw(CW_S3_SEL_B), s3_b_fwd, s3_imm_i_ext, s3_b_sel);
ALU0: Alu
generic map(DATA_SIZE)
port map(calu, s3_a_sel, s3_b_sel, s3_alu_out);
MUL0: Mul
generic map(DATA_SIZE/2, MUL_STAGE)
port map(rst, clk, s3_mul_op, s3_mul_lock, s3_mul_sign, s3_a_sel(DATA_SIZE/2-1 downto 0), s3_b_sel(DATA_SIZE/2-1 downto 0), s3_mul_out);
DIV0: Div
generic map(DATA_SIZE, DIV_STAGE, SQRT_STAGE)
port map(rst, clk, s3_div_sqrt_op, s3_div_lock, s3_div_sign, s3_sqrt_op, s3_a_sel, s3_b_sel, s3_div_out);
----------------------------------------------------------------------------
-- FIXME
-- only signed mult and unsigned div can produce correct value.
----------------------------------------------------------------------------
s3_mul_op <= '1' when calu="01000" or calu="01001" else '0';
sig_mul <= s3_mul_op;
s3_div_op <= '1' when calu="01010" or calu="01011" else '0';
sig_div <= s3_div_op;
s3_sqrt_op <= '1' when calu="01100" else '0';
sig_sqrt <= s3_sqrt_op;
s3_div_sqrt_op <= s3_div_op or s3_sqrt_op;
s3_exe_sel <= s3_div_sqrt_op & s3_mul_op;
s3_mul_sign <= '1' when calu="01001" else '0';
s3_div_sign <= '1' when calu="01011" else '0';
s3_div_lock <= (s3_reg_a_wait or s3_reg_b_wait);
s3_mul_lock <= (s3_reg_a_wait or s3_reg_b_wait);
MUXEXE: Mux4
generic map(DATA_SIZE)
port map(s3_exe_sel, s3_alu_out, s3_mul_out, s3_div_out, (others=>'0'), s3_exe_out);
-- REGISTERS : [EXE]||[MEM]
REG_ALU: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S3_LATCH), clk, s3_exe_out, s4_exe_out);
REG_BB: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S3_LATCH), clk, s3_b_fwd, s4_b_fwd);
REG_B_ADDR_3: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S3_LATCH), clk, s3_rd2_addr, s4_rd2_addr);
REG_WR3: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S3_LATCH), clk, s3_wr_addr, s4_wr_addr);
----------------------------------------------------------------------------
-- NOTE:
-- COMP: REG_OPRD_A_WAIT, REG_OPRD_B_WAIT
-- DESC: Registers for keeping the operand A and B to PIPELINE STATGE 4 [MEM].
-- When A causes a STALL, due to forward value is not ready (Load After Read)
-- in stage 4, and B uses the value of double-forward (from stage 5)
-- which is valid. We need to keep the value of B because once the
-- STALL complete, the valid value of B in stage 5 will be stored in Register File.
-- At this moment, other instruction occupies the stage 2, so we cannot
-- get the value of B for the instruction in stage 3. Therefore, we
-- need this two registers to store the value of A and B.
----------------------------------------------------------------------------
REG_OPRD_A_WAIT: Reg
generic map(DATA_SIZE)
port map(rst, '1', clk, s3_a_sel, s4_a);
REG_OPRD_B_WAIT: Reg
generic map(DATA_SIZE)
port map(rst, '1', clk, s3_b_sel, s4_b);
PROCWAIT: process(clk)
begin
if rising_edge(clk) then
s4_reg_a_wait <= s3_reg_a_wait;
s4_reg_b_wait <= s3_reg_b_wait;
end if;
end process;
-- PIPELINE STAGE 4 : [MEM]
-- Signals to Data RAM
data_addr <= s4_exe_out; -- to DRAM
data_o_val <= s4_mem_in; -- to DRAM
s4_mem_out <= data_i_val; -- from DRAM
dr_cw <= cw(CW_S4_DRAM_WR downto CW_S4_DRAM_T_0); -- to DRAM
ld_a_out <= s4_mem_out;
FWDMUX_BB: FwdMux2
generic map(DATA_SIZE, REG_ADDR_SIZE)
port map(s4_b_fwd, s5_result, s6_result, s4_rd2_addr, s5_wr_addr, s6_wr_addr, cw(CW_S5_EN_WB), s6_en_wb, '0', '0', cw(CW_S4_DRAM_WR), s4_mem_in, open, open);
MUX_RESULT: Mux
generic map(DATA_SIZE)
port map(cw(CW_S4_SEL_WB), s4_exe_out, s4_mem_out, s4_result);
-- REGISTERS : [MEM]||[WB]
REG_RESULT: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S4_LATCH), clk, s4_result, s5_result);
REG_WR4: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S4_LATCH), clk, s4_wr_addr, s5_wr_addr);
-- PIPELINE STAGE 5 : [WB]
-- No component needed in pipeline 5, because every operation happens in Register File.
-- DELAY s5_result is to forwarding for STORE;
-- REGISTERS : [WB]||[EXTRA STAGE]
REG_RESULT5: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S5_EN_WB), clk, s5_result, s6_result);
REG_WR5: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S5_EN_WB), clk, s5_wr_addr, s6_wr_addr);
REG5:process(rst, clk)
begin
if rst='0' then
s6_en_wb <= '0';
else
if rising_edge(clk) and cw(CW_S5_EN_WB)='1' then
s6_en_wb <= '1';
end if;
end if;
end process;
end data_path_arch;
|
mit
|
f346e5a5db5e9a8e6eebad9c0c70c378
| 0.595307 | 2.509501 | false | false | false | false |
tristanseifert/68komputer
|
BusPLL.vhd
| 1 | 16,668 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: BusPLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.0 Build 156 04/24/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY BusPLL IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END BusPLL;
ARCHITECTURE SYN OF buspll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=BusPLL",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "BusPLL.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL BusPLL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
bsd-2-clause
|
f7696d3f08e4dc493261fa399d6fe2b8
| 0.684245 | 3.284335 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_09.vhd
| 4 | 1,780 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_09 is
end entity inline_09;
----------------------------------------------------------------
architecture test of inline_09 is
begin
process is
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : bit_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list, cell_to_be_deleted : value_ptr;
begin
value_list := new value_cell'( B"1000", value_list );
value_list := new value_cell'( B"0010", value_list );
value_list := new value_cell'( B"0000", value_list );
-- code from book:
cell_to_be_deleted := value_list;
value_list := value_list.next_cell;
deallocate(cell_to_be_deleted);
while value_list /= null loop
cell_to_be_deleted := value_list;
value_list := value_list.next_cell;
deallocate(cell_to_be_deleted);
end loop;
-- end of code from book
wait;
end process;
end architecture test;
|
gpl-2.0
|
d20e3ee904f5442acf5f69d7d0e9ed5a
| 0.658427 | 3.912088 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket89/project/src93/license_open_pkg.vhd
| 3 | 6,924 |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : license_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
package license_pkg is
impure function show_license(
constant dummy : in t_void
) return boolean;
impure function show_bitvis_utility_library_info(
constant dummy : in t_void
) return boolean;
impure function show_bitvis_utility_library_release_info(
constant dummy : in t_void
) return boolean;
end package license_pkg;
package body license_pkg is
impure function show_license(
constant dummy : in t_void
) return boolean is
constant C_VERSION : string := "v2.5.1"; -- June 2015
constant C_SEPARATOR : string :=
"=====================================================================================================";
constant C_LICENSE_STR : string :=
LF & LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF &
" Bitvis Utility Library " & C_VERSION & " is being used by this simulation." & LF &
" This is a *** LICENSED PRODUCT *** as given in the copyright notice of the VHDL code." & LF &
" The free license granted is subject to the conditions given in the VHDL copyright notice." & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF & LF;
begin
report (C_LICENSE_STR);
return true;
end;
impure function show_bitvis_utility_library_info(
constant dummy : in t_void
) return boolean is
constant C_SEPARATOR : string :=
"=====================================================================================================";
constant C_LICENSE_STR : string :=
LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF &
"This info section may be turned off via C_SHOW_BITVIS_UTILITY_LIBRARY_INFO in adaptations_pkg.vhd" & LF & LF &
"Important Simulator setup: " & LF &
"- Set simulator to break on severity 'FAILURE' " & LF &
"- Set simulator transcript to a monospace font (e.g. Courier new)" & LF & LF &
"Bitvis Utility Library setup:" & LF &
"- It is recommended to go through the two powerpoint presentations provided with the download" & LF &
"- There is a Quick-Reference in the doc-directory" & LF &
"- In order to change layout or behaviour - please check the src*/adaptations_pkg.vhd" & LF &
" This is intended for personal or company customization" & LF & LF &
"License conditions are given in License.txt" & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF & LF;
begin
if C_SHOW_BITVIS_UTILITY_LIBRARY_INFO then
report (C_LICENSE_STR);
end if;
return true;
end;
impure function show_bitvis_utility_library_release_info(
constant dummy : in t_void
) return boolean is
constant C_IMPORTANT_UPDATE_FOR_THIS_VERSION : boolean := true; -- ***** NOTE: Evaluate a change here
constant C_SEPARATOR : string :=
"=====================================================================================================";
constant C_LICENSE_STR : string :=
LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF &
"This release info may be turned off via C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO in adaptations_pkg.vhd" & LF & LF &
"Important Issues for this version update: " & LF &
"- Two procedures have changed name (see CHANGES.TXT)" & LF &
" The old names will still work for a few more version updates, but a deprecate-message will be displayed" & LF &
" (The deprecate-message may be turned off, but we recommend to rather change the actual procedure names)" & LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF & LF;
begin
if C_SHOW_BITVIS_UTILITY_LIBRARY_RELEASE_INFO and C_IMPORTANT_UPDATE_FOR_THIS_VERSION then
report (C_LICENSE_STR);
end if;
return true;
end;
end package body license_pkg;
|
gpl-2.0
|
467ed84cfac545c0fea4ecebd8294a6f
| 0.48989 | 5.23356 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/Architecture1_Pipeline/AES128_V1_AXIS.vhd
| 1 | 9,461 |
------------------------------------------------------------------------------
-- hw_acc - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: hw_acc
-- Version: 1.00.a
-- Description: Example Axi Streaming core (VHDL).
-- Date: Mon Sep 15 15:41:21 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- ACLK : Synchronous clock
-- ARESETN : System reset, active low
-- S_AXIS_TREADY : Ready to accept data in
-- S_AXIS_TDATA : Data in
-- S_AXIS_TLAST : Optional data in qualifier
-- S_AXIS_TVALID : Data in is valid
-- M_AXIS_TVALID : Data out is valid
-- M_AXIS_TDATA : Data Out
-- M_AXIS_TLAST : Optional data out qualifier
-- M_AXIS_TREADY : Connected slave device is ready to accept data out
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity myip_v1_0 is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ACLK : in std_logic;
ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of ACLK : signal is "Clk";
end myip_v1_0;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
-- In this section, we povide an example implementation of ENTITY hw_acc
-- that does the following:
--
-- 1. Read all inputs
-- 2. Add each input to the contents of register 'sum' which
-- acts as an accumulator
-- 3. After all the inputs have been read, write out the
-- content of 'sum' into the output stream NUMBER_OF_OUTPUT_WORDS times
--
-- You will need to modify this example or implement a new architecture for
-- ENTITY hw_acc to implement your coprocessor
architecture EXAMPLE of myip_v1_0 is
-- Total number of input data.
constant KEY_LENGTH : natural := 4;
constant PIPELINE_LENGTH : natural := 69;
type STATE_TYPE is (IDLE, READ_KEY, EXPAND_KEY, STALL, DECRYPT);
signal state : STATE_TYPE;
-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to KEY_LENGTH - 1;
component AES128_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
READY_TO_DECRYPT : out STD_LOGIC;
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal ENABLE : STD_LOGIC := '0';
signal RESET : STD_LOGIC := '0';
signal READY_TO_DECRYPT : STD_LOGIC := '0';
signal decrypt_cnt : natural range 0 to PIPELINE_LENGTH - 1;
signal stall_cycles : natural range 0 to 2 := 2;
begin
-- CAUTION:
-- The sequence in which data are read in and written out should be
-- consistent with the sequence they are written and read in the
-- driver's hw_acc.c file
RESET <= not ARESETN; --AXIS reset is active low
M_AXIS_TLAST <= '0'; --Unused
aes: AES128_V1 port map( CLK => ACLK,
RESET => RESET,
ENABLE => ENABLE,
READY_TO_DECRYPT => READY_TO_DECRYPT,
WORD_IN => S_AXIS_TDATA,
WORD_OUT => M_AXIS_TDATA);
--Pro: The pipeline will not be corrupted if a clock cycle is skipped since it is active only when read and write are available.
--Con: The pipeline must be manually flushed.
ENABLE <= '0' when (state = IDLE) else
'1' when (state = EXPAND_KEY or state = STALL) else
S_AXIS_TVALID;
S_AXIS_TREADY <= '1' when (state = READ_KEY or state = DECRYPT) else
'0';
The_SW_accelerator : process (ACLK) is
begin -- process The_SW_accelerator
M_AXIS_TVALID <= '0'; --Default case: output data is not valid
if ACLK'event and ACLK = '1' then -- Rising clock edge
if ARESETN = '0' then -- Synchronous reset (active low)
-- CAUTION: make sure your reset polarity is consistent with the
-- system reset polarity
state <= IDLE;
nr_of_reads <= KEY_LENGTH - 1;
else
case state is
when IDLE =>
if (S_AXIS_TVALID = '1') then --Begin reading key
state <= READ_KEY;
nr_of_reads <= KEY_LENGTH - 1;
end if;
when READ_KEY => --Read the 4 words that comprise the key
if (S_AXIS_TVALID = '1') then
if (nr_of_reads = 0) then
state <= EXPAND_KEY;
else
nr_of_reads <= nr_of_reads - 1;
end if;
end if;
when EXPAND_KEY => --Cycle until key expansion is done.
if (READY_TO_DECRYPT = '1') then
state <= STALL;
stall_cycles <= 2;
end if;
when STALL => --Wait for one block cycle.
if (stall_cycles = 0) then
state <= DECRYPT;
decrypt_cnt <= PIPELINE_LENGTH - 1;
else
stall_cycles <= stall_cycles - 1;
end if;
when DECRYPT =>
if (S_AXIS_TVALID = '1') then --Output is only valid if something was pushed.
if (decrypt_cnt = 0) then --The first decrypted word has exited the pipeline and everything following should be valid data.
M_AXIS_TVALID <= '1'; --The 70th rising edge AFTER the key was input marks the first valid output.
-- This signal is asserted at the 69th rising edge, to be read one cycle after.
else
decrypt_cnt <= decrypt_cnt - 1;
end if;
end if;
end case;
end if;
end if;
end process The_SW_accelerator;
end architecture EXAMPLE;
|
gpl-2.0
|
2ac833c5b298b1a5ac622c2e5bdfe102
| 0.481239 | 4.658296 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket19/psl_test_cover2.vhd
| 1 | 1,260 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_cover2 is
end entity psl_test_cover2;
architecture test of psl_test_cover2 is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 20 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_COVER test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- cover directive seems not supported (ignored by GHDL)
-- psl cover always (s_write -> not(s_read));
end architecture test;
|
gpl-2.0
|
35acbe6d8543b15dc92d55eb2497fc9b
| 0.583333 | 3.111111 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink-b.vhd
| 4 | 4,519 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_sink-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of sink is
begin
token_consumer : process is
variable number_of_tokens_consumed : natural := 0;
variable life_time : real; -- in time_unit
variable sum_of_life_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_life_times : real := 0.0; --in time_unit**2
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable mean_life_time : real
:= sum_of_life_times / real(number_of_tokens_consumed);
variable std_dev_of_life_times : real
:= sqrt ( ( sum_of_squares_of_life_times
- sum_of_life_times**2 / real(number_of_tokens_consumed) )
/ real( number_of_tokens_consumed - 1 ) );
begin
write(L, string'("Summary information for sink "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens consumed = "));
write(L, natural(number_of_tokens_consumed));
writeline(info_file, L);
write(L, string'(" Mean life_time = "));
write(L, mean_life_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of life_times = "));
write(L, std_dev_of_life_times * time_unit, unit => time_unit);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace is
begin
write(L, string'("Sink "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" consumed "));
write(L, in_arc.token, time_unit);
writeline(info_file, L);
end procedure write_trace;
begin
file_open(info_file, info_file_name, write_mode);
loop
wait on info_detail'transaction, in_arc;
if info_detail'active and info_detail = summary then
write_summary;
end if;
if in_arc'event then
number_of_tokens_consumed := number_of_tokens_consumed + 1;
life_time := real( (now - in_arc.token.creation_time) / time_unit );
sum_of_life_times := sum_of_life_times + life_time;
sum_of_squares_of_life_times := sum_of_squares_of_life_times + life_time ** 2;
if info_detail = trace then
write_trace;
end if;
end if;
end loop;
end process token_consumer;
end architecture behavior;
|
gpl-2.0
|
bbe29e928a4971efe8c702c310710319
| 0.476212 | 4.687759 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/numeric_std.vhdl
| 4 | 75,989 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number
-- : in vector form
-- : -- > UNRESOLVED_SIGNED: represents a SIGNED number
-- : in vector form
-- : The base element type is type STD_ULOGIC.
-- : Aliases U_UNSIGNED and U_SIGNED are defined for the types
-- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively.
-- : Two numeric subtypes are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The element subtypes are the same subtype as STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
constant CopyRightNotice : STRING
:= "Copyright © 2008 IEEE. All rights reserved.";
--============================================================================
-- Numeric Array Type Definitions
--============================================================================
type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;
type UNRESOLVED_SIGNED is array (NATURAL range <>) of STD_ULOGIC;
-- FIXME: was alias
subtype U_UNSIGNED is UNRESOLVED_UNSIGNED;
subtype U_SIGNED is UNRESOLVED_SIGNED;
subtype UNSIGNED is (resolved) UNRESOLVED_UNSIGNED;
subtype SIGNED is (resolved) UNRESOLVED_SIGNED;
--============================================================================
-- Arithmetic Operators:
--===========================================================================
-- Id: A.1
function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Returns the absolute value of an UNRESOLVED_SIGNED vector ARG.
-- Id: A.2
function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Returns the value of the unary minus operation on a
-- UNRESOLVED_SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Adds two UNRESOLVED_UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit UNRESOLVED_UNSIGNED
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNRESOLVED_UNSIGNED
-- Id: A.4
function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Adds two UNRESOLVED_SIGNED vectors that may be of different lengths.
-- Id: A.4R
function "+"(L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.4 where R is bit 0 of a non-negative.
-- Id: A.4L
function "+"(L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.4 where L is bit 0 of a non-negative.
-- Id: A.5
function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Adds an UNRESOLVED_UNSIGNED vector, L, with a nonnegative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Adds a nonnegative INTEGER, L, with an UNRESOLVED_UNSIGNED vector, R.
-- Id: A.7
function "+" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Adds an INTEGER, L(may be positive or negative), to an UNRESOLVED_SIGNED
-- vector, R.
-- Id: A.8
function "+" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Adds an UNRESOLVED_SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Subtracts two UNRESOLVED_UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNRESOLVED_UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNRESOLVED_UNSIGNED
-- Id: A.10
function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Subtracts an UNRESOLVED_SIGNED vector, R, from another UNRESOLVED_SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.10R
function "-"(L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.10 where R is bit 0 of a non-negative.
-- Id: A.10L
function "-"(L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.10 where R is bit 0 of a non-negative.
-- Id: A.11
function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Subtracts a nonnegative INTEGER, R, from an UNRESOLVED_UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Subtracts an UNRESOLVED_UNSIGNED vector, R, from a nonnegative INTEGER, L.
-- Id: A.13
function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Subtracts an INTEGER, R, from an UNRESOLVED_SIGNED vector, L.
-- Id: A.14
function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Subtracts an UNRESOLVED_SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Performs the multiplication operation on two UNRESOLVED_UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two UNRESOLVED_SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_UNSIGNED vector, L, with a nonnegative
-- INTEGER, R. R is converted to an UNRESOLVED_UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_UNSIGNED vector, R, with a nonnegative
-- INTEGER, L. L is converted to an UNRESOLVED_UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
-- Id: A.19
function "*" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_SIGNED vector, L, with an INTEGER, R. R is
-- converted to an UNRESOLVED_SIGNED vector of SIZE L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies an UNRESOLVED_SIGNED vector, R, with an INTEGER, L. L is
-- converted to an UNRESOLVED_SIGNED vector of SIZE R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_UNSIGNED vector, L, by another UNRESOLVED_UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_SIGNED vector, L, by another UNRESOLVED_SIGNED vector, R.
-- Id: A.23
function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_UNSIGNED vector, L, by a nonnegative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a nonnegative INTEGER, L, by an UNRESOLVED_UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNRESOLVED_SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by an UNRESOLVED_SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNRESOLVED_UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNRESOLVED_SIGNED vectors.
-- Id: A.29
function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNRESOLVED_UNSIGNED vector and R is a
-- nonnegative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNRESOLVED_UNSIGNED vector and L is a
-- nonnegative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is UNRESOLVED_SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is UNRESOLVED_SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNRESOLVED_UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNRESOLVED_SIGNED vectors.
-- Id: A.35
function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNRESOLVED_UNSIGNED vector and R
-- is a nonnegative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNRESOLVED_UNSIGNED vector and L
-- is a nonnegative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.40
function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.42
function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.4
function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.5
function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.6
function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNRESOLVED_SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.10
function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.11
function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.12
function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.16
function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.17
function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.18
function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.22
function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.23
function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.24
function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.28
function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.29
function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.30
function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.34
function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.35
function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.36
function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the lesser of two UNRESOLVED_UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.38
function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the lesser of two UNRESOLVED_SIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNRESOLVED_UNSIGNED vector, R.
-- Id: C.40
function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the lesser of an INTEGER, L, and an UNRESOLVED_SIGNED
-- vector, R.
-- Id: C.41
function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the lesser of an UNRESOLVED_UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
-- Id: C.42
function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the lesser of an UNRESOLVED_SIGNED vector, L, and
-- an INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the greater of two UNRESOLVED_UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.44
function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the greater of two UNRESOLVED_SIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNRESOLVED_UNSIGNED vector, R.
-- Id: C.46
function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the greater of an INTEGER, L, and an UNRESOLVED_SIGNED
-- vector, R.
-- Id: C.47
function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED
-- Result: Returns the greater of an UNRESOLVED_UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
-- Id: C.48
function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED
-- Result: Returns the greater of an UNRESOLVED_SIGNED vector, L, and
-- an INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.50
function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.52
function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.53
function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.54
function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNRESOLVED_SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.56
function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.58
function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.59
function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.60
function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.62
function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.64
function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.65
function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.66
function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.68
function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.70
function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.71
function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.72
function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.74
function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.76
function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.77
function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.78
function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNRESOLVED_UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.80
function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNRESOLVED_SIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNRESOLVED_UNSIGNED vector.
-- Id: C.82
function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is an UNRESOLVED_SIGNED vector.
-- Id: C.83
function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNRESOLVED_UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.84
function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNRESOLVED_SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNRESOLVED_UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNRESOLVED_UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
-- Id: S.3
function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNRESOLVED_SIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNRESOLVED_SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost
-- element, ARG'LEFT. The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNRESOLVED_UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNRESOLVED_UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of an UNRESOLVED_SIGNED
-- vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of an UNRESOLVED_SIGNED
-- vector COUNT times.
--============================================================================
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE StdL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNRESOLVED_SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNRESOLVED_SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNRESOLVED_UNSIGNED vector.
-- Result: Converts the UNRESOLVED_UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts an UNRESOLVED_SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
-- Id: D.4
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a UNRESOLVED_SIGNED vector of the specified SIZE.
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0)
function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0)
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.15
function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector AND operation
-- Id: L.16
function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar AND operation
-- Id: L.17
function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector OR operation
-- Id: L.18
function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar OR operation
-- Id: L.19
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NAND operation
-- Id: L.20
function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NAND operation
-- Id: L.21
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NOR operation
-- Id: L.22
function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NOR operation
-- Id: L.23
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XOR operation
-- Id: L.24
function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XOR operation
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XNOR operation
-- Id: L.27
function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector AND operation
-- Id: L.28
function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar AND operation
-- Id: L.29
function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector OR operation
-- Id: L.30
function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar OR operation
-- Id: L.31
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NAND operation
-- Id: L.32
function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NAND operation
-- Id: L.33
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NOR operation
-- Id: L.34
function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NOR operation
-- Id: L.35
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XOR operation
-- Id: L.36
function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XOR operation
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of and'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of or'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of and'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of or'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
--============================================================================
-- Match Functions
--============================================================================
-- Id: M.1
function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.2
function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.3
function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.5
function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- Id: T.2
function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- Id: T.3
function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.4
function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.5
function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L'|'Z' are translated to 'X'.
-- Id: T.6
function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than '0'|'1'|'H'|'L'|'Z' are translated to 'X'.
-- Id: T.7
function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than 'U'|'0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.8
function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', 'L' is translated to '0',
-- and values other than 'U'|'0'|'1'|'H'|'L' are translated to 'X'.
-- Id: T.9
function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: TRUE if S contains a 'U'|'X'|'Z'|'W'|'-' value, FALSE otherwise.
-- Id: T.10
function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: TRUE if S contains a 'U'|'X'|'Z'|'W'|'-' value, FALSE otherwise.
--============================================================================
-- string conversion and write operations
--============================================================================
-- the following operations are predefined
-- function to_string (value : UNRESOLVED_UNSIGNED) return STRING;
-- function to_string (value : UNRESOLVED_SIGNED) return STRING;
-- explicitly defined operations
alias to_bstring is to_string [UNRESOLVED_UNSIGNED return STRING];
alias to_bstring is to_string [UNRESOLVED_SIGNED return STRING];
alias to_binary_string is to_string [UNRESOLVED_UNSIGNED return STRING];
alias to_binary_string is to_string [UNRESOLVED_SIGNED return STRING];
function to_ostring (value : UNRESOLVED_UNSIGNED) return STRING;
function to_ostring (value : UNRESOLVED_SIGNED) return STRING;
alias to_octal_string is to_ostring [UNRESOLVED_UNSIGNED return STRING];
alias to_octal_string is to_ostring [UNRESOLVED_SIGNED return STRING];
function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING;
function to_hstring (value : UNRESOLVED_SIGNED) return STRING;
alias to_hex_string is to_hstring [UNRESOLVED_UNSIGNED return STRING];
alias to_hex_string is to_hstring [UNRESOLVED_SIGNED return STRING];
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED);
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNRESOLVED_SIGNED);
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_UNSIGNED];
alias BREAD is READ [LINE, UNRESOLVED_SIGNED];
alias BINARY_READ is READ [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_UNSIGNED];
alias BINARY_READ is READ [LINE, UNRESOLVED_SIGNED];
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_UNSIGNED];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_SIGNED];
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED);
alias HEX_READ is HREAD [LINE, UNRESOLVED_UNSIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_SIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_UNSIGNED];
alias HEX_READ is HREAD [LINE, UNRESOLVED_SIGNED];
alias BWRITE is WRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_UNSIGNED, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_SIGNED, SIDE, WIDTH];
end package NUMERIC_STD;
|
gpl-2.0
|
2e3cc03eb6a63d7c538c9bc84281f0a4
| 0.600311 | 4.330598 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd
| 4 | 1,538 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_mux2 is
end entity tb_mux2;
architecture test of tb_mux2 is
signal a, b, sel, z : bit;
begin
dut : entity work.mux2(behavioral)
port map ( a => a, b => b, sel => sel, z => z );
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0100",
"1001",
"1101",
"0010",
"0111",
"1010",
"1111" );
begin
for i in stim_vector'range loop
(a, b, sel) <= stim_vector(i)(0 to 2);
wait for 10 ns;
assert z = stim_vector(i)(3);
end loop;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
8704dd320900c71c3c79614ea76d1db4
| 0.657997 | 3.73301 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/processor.vhd
| 4 | 2,110 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity processor is
end entity processor;
-- code from book
architecture rtl of processor is
component latch is
generic ( width : positive );
port ( d : in std_ulogic_vector(0 to width - 1);
q : out std_ulogic_vector(0 to width - 1);
-- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component latch;
component ROM is
port ( d_out : out std_ulogic_vector; -- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component ROM;
subtype std_logic_word is std_logic_vector(0 to 31);
signal source1, source2, destination : std_logic_word;
-- . . .
begin
temp_register : component latch
generic map ( width => 32 )
port map ( d => std_ulogic_vector(destination),
std_logic_vector(q) => source1, -- . . . );
-- not in book
other_port => open );
-- end not in book
constant_ROM : component ROM
port map ( std_logic_word(d_out) => source2, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture rtl;
-- end code from book
|
gpl-2.0
|
30e9544eb5165ed3dc87c4fee32f8e08
| 0.6109 | 3.988658 | false | false | false | false |
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