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peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3033.vhd
| 4 | 2,647 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3033.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b01x00p01n02i03033ent IS
END c12s02b01x00p01n02i03033ent;
ARCHITECTURE c12s02b01x00p01n02i03033arch OF c12s02b01x00p01n02i03033ent IS
subtype subi is integer range 1 to 10;
signal s1,s2,s3 : subi;
BEGIN
bl1: block
generic (gi : subi);
generic map (gi => 1);
port (s11 : OUT subi);
port map (s11 => s1);
begin
assert (gi=1)
report "Generic GI did not take on the correct low value of 1"
severity failure;
s11 <= gi;
end block;
bl2: block
generic (gi : subi);
generic map (gi => 5);
port (s22 : OUT subi);
port map (s22 => s2);
begin
assert (gi=5)
report "Generic GI did not take on the correct middle value of 5"
severity failure;
s22 <= gi;
end block;
bl3: block
generic (gi : subi);
generic map (gi => 10);
port (s33 : OUT subi);
port map (s33 => s3);
begin
assert (gi=10)
report "Generic GI did not take on the correct high value of 10"
severity failure;
s33 <= gi;
end block;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( s1 = 1 and s2 = 5 and s3 = 10 )
report "***PASSED TEST: c12s02b01x00p01n02i03033"
severity NOTE;
assert ( s1 = 1 and s2 = 5 and s3 = 10 )
report "***FAILED TEST: c12s02b01x00p01n02i03033 - Generic constants does not conform to their subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s02b01x00p01n02i03033arch;
|
gpl-2.0
|
bf728223279df1b772b2e1f4333c77ae
| 0.635059 | 3.55302 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc661.vhd
| 4 | 3,143 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc661.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:56 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:24 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:35 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00661ent IS
END c03s04b01x00p01n01i00661ent;
ARCHITECTURE c03s04b01x00p01n01i00661arch OF c03s04b01x00p01n01i00661ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type natural_vector is array (natural range <>) of natural;
subtype natural_vector_range is natural_vector(hi_to_low_range);
constant C1 : natural_vector_range := (others => 3);
type natural_vector_range_file is file of natural_vector_range;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : natural_vector_range_file open read_mode is "iofile.03";
variable v : natural_vector_range := C1;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C1) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00661"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00661 - File reading of natural_vector_range_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00661arch;
|
gpl-2.0
|
5c8aca65c90347f4deb7aefad5310578
| 0.561884 | 3.998728 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc669.vhd
| 4 | 7,982 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc669.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:58 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:27 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:37 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00669ent IS
END c03s04b01x00p01n01i00669ent;
ARCHITECTURE c03s04b01x00p01n01i00669arch OF c03s04b01x00p01n01i00669ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
i: record_array_st;
end record;
type array_rec_rec is array (integer range <>) of record_of_records;
type array_rec_rec_file is file of array_rec_rec;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C28 : boolean_vector_st := (others => C1);
constant C29 : severity_level_vector_st := (others => C4);
constant C30 : integer_vector_st := (others => C5);
constant C31 : real_vector_st := (others => C6);
constant C32 : time_vector_st := (others => C7);
constant C33 : natural_vector_st := (others => C8);
constant C34 : positive_vector_st := (others => C9);
constant C35 : record_array_st := (C28,C29,C30,C31,C32,C33,C34);
constant C37 : record_of_records := (C26,C27,C35);
constant C59: array_rec_rec(0 to 7) :=(others => C37);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : array_rec_rec_file open read_mode is "iofile.15";
variable v : array_rec_rec(0 to 7);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 8) report "wrong length passed during read operation";
if (v /= C59) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00669"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00669 - File reading of array_rec_rec_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00669arch;
|
gpl-2.0
|
6eda3bee70a79d505e1f29e3db4c311d
| 0.526184 | 3.920432 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1985.vhd
| 4 | 6,616 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1985.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01985ent IS
END c07s02b02x00p02n01i01985ent;
ARCHITECTURE c07s02b02x00p02n01i01985arch OF c07s02b02x00p02n01i01985ent IS
BEGIN
TESTING: PROCESS
constant meg : integer := 1000000;
variable bigpos : integer := 2000 * meg;
variable bigneg : integer := -2000 * meg;
variable smallpos : integer := 2000;
variable smallneg : integer := -2000;
variable zero : integer := 0;
BEGIN
assert NOT( ( bigneg < smallneg) and
( bigneg < zero) and
( bigneg < smallpos) and
( bigneg < bigpos) and
( smallneg < zero) and
( smallneg < smallpos) and
( smallneg < bigpos) and
( zero < smallpos) and
( zero < bigpos) and
( smallpos < bigpos) and
( not(bigneg >= smallneg)) and
( not(bigneg >= zero)) and
( not(bigneg >= smallpos)) and
( not(bigneg >= bigpos)) and
( not(smallneg >= zero)) and
( not(smallneg >= smallpos)) and
( not(smallneg >= bigpos)) and
( not(zero >= smallpos)) and
( not(zero >= bigpos)) and
( not(smallpos >= bigpos)) and
( bigneg <= smallneg) and
( bigneg <= zero) and
( bigneg <= smallpos) and
( bigneg <= bigpos) and
( smallneg <= zero) and
( smallneg <= smallpos) and
( smallneg <= bigpos) and
( zero <= smallpos) and
( zero <= bigpos) and
( smallpos <= bigpos) and
( bigneg <= bigneg) and
( smallneg <= smallneg) and
( zero <= zero) and
( smallpos <= smallpos) and
( bigpos <= bigpos) and
( not(bigneg > smallneg)) and
( not(bigneg > zero)) and
( not(bigneg > smallpos)) and
( not(bigneg > bigpos)) and
( not(smallneg > zero)) and
( not(smallneg > smallpos)) and
( not(smallneg > bigpos)) and
( not(zero > smallpos)) and
( not(zero > bigpos)) and
( not(smallpos > bigpos)) and
( not(bigneg > bigneg)) and
( not(smallneg > smallneg)) and
( not(zero > zero)) and
( not(smallpos > smallpos)) and
( not(bigpos > bigpos)) )
report "***PASSED TEST: c07s02b02x00p02n01i01985"
severity NOTE;
assert ( ( bigneg < smallneg) and
( bigneg < zero) and
( bigneg < smallpos) and
( bigneg < bigpos) and
( smallneg < zero) and
( smallneg < smallpos) and
( smallneg < bigpos) and
( zero < smallpos) and
( zero < bigpos) and
( smallpos < bigpos) and
( not(bigneg >= smallneg)) and
( not(bigneg >= zero)) and
( not(bigneg >= smallpos)) and
( not(bigneg >= bigpos)) and
( not(smallneg >= zero)) and
( not(smallneg >= smallpos)) and
( not(smallneg >= bigpos)) and
( not(zero >= smallpos)) and
( not(zero >= bigpos)) and
( not(smallpos >= bigpos)) and
( bigneg <= smallneg) and
( bigneg <= zero) and
( bigneg <= smallpos) and
( bigneg <= bigpos) and
( smallneg <= zero) and
( smallneg <= smallpos) and
( smallneg <= bigpos) and
( zero <= smallpos) and
( zero <= bigpos) and
( smallpos <= bigpos) and
( bigneg <= bigneg) and
( smallneg <= smallneg) and
( zero <= zero) and
( smallpos <= smallpos) and
( bigpos <= bigpos) and
( not(bigneg > smallneg)) and
( not(bigneg > zero)) and
( not(bigneg > smallpos)) and
( not(bigneg > bigpos)) and
( not(smallneg > zero)) and
( not(smallneg > smallpos)) and
( not(smallneg > bigpos)) and
( not(zero > smallpos)) and
( not(zero > bigpos)) and
( not(smallpos > bigpos)) and
( not(bigneg > bigneg)) and
( not(smallneg > smallneg)) and
( not(zero > zero)) and
( not(smallpos > smallpos)) and
( not(bigpos > bigpos)) )
report "***FAILED TEST: c07s02b02x00p02n01i01985 - Relational operators truth table test for data type of Integer failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01985arch;
|
gpl-2.0
|
e63eef249bb5c813d4e6cc54a2aa0b28
| 0.456469 | 4.649332 | false | false | false | false |
stnolting/neo430
|
rtl/top_templates/neo430_top_avm.vhd
| 1 | 14,344 |
-- #################################################################################################
-- # << NEO430 - Processor Top Entity with Avalon-Compatible Master Interface >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_top_avm is
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := false; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
FREQ_GEN_USE : boolean := true; -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- global control --
clk_i : in std_logic; -- global clock, rising edge
rst_i : in std_logic; -- global reset, async, low-active
-- GPIO --
gpio_o : out std_logic_vector(15 downto 0); -- parallel output
gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_logic_vector(03 downto 0); -- pwm channels
-- arbitrary frequency generator --
freq_gen_o : out std_logic_vector(02 downto 0); -- programmable frequency output
-- UART --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic; -- UART receive data
-- SPI --
spi_sclk_o : out std_logic; -- serial clock line
spi_mosi_o : out std_logic; -- serial data line out
spi_miso_i : in std_logic; -- serial data line in
spi_cs_o : out std_logic_vector(05 downto 0); -- SPI CS
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- external interrupts --
ext_irq_i : in std_logic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_logic_vector(07 downto 0); -- external interrupt request acknowledges
-- Avalon master interface --
avm_address : out std_logic_vector(31 downto 0);
avm_readdata : in std_logic_vector(31 downto 0);
avm_writedata : out std_logic_vector(31 downto 0);
avm_byteenable : out std_logic_vector(03 downto 0);
avm_write : out std_logic;
avm_read : out std_logic;
avm_waitrequest : in std_logic
);
end neo430_top_avm;
architecture neo430_top_avm_rtl of neo430_top_avm is
-- internal wishbone (unresolved) bus --
type wb_bus_ul_t is record
adr : std_ulogic_vector(31 downto 0); -- address
di : std_ulogic_vector(31 downto 0); -- slave input data
do : std_ulogic_vector(31 downto 0); -- slave output data
we : std_ulogic; -- write enable
sel : std_ulogic_vector(03 downto 0); -- byte enable
stb : std_ulogic; -- strobe
cyc : std_ulogic; -- valid cycle
ack : std_ulogic; -- transfer acknowledge
end record;
signal wb_core : wb_bus_ul_t;
-- internal wishbone bus --
type wb_bus_t is record
adr : std_logic_vector(31 downto 0); -- address
di : std_logic_vector(31 downto 0); -- slave input data
do : std_logic_vector(31 downto 0); -- slave output data
we : std_logic; -- write enable
sel : std_logic_vector(03 downto 0); -- byte enable
stb : std_logic; -- strobe
cyc : std_logic; -- valid cycle
ack : std_logic; -- transfer acknowledge
end record;
signal wb_conv : wb_bus_t;
-- other signals for conversion --
signal clk_i_int : std_ulogic;
signal rst_i_int : std_ulogic;
signal gpio_o_int : std_ulogic_vector(15 downto 0);
signal gpio_i_int : std_ulogic_vector(15 downto 0);
signal pwm_o_int : std_ulogic_vector(03 downto 0);
signal uart_txd_o_int : std_ulogic;
signal uart_rxd_i_int : std_ulogic;
signal spi_sclk_o_int : std_ulogic;
signal spi_mosi_o_int : std_ulogic;
signal spi_miso_i_int : std_ulogic;
signal spi_cs_o_int : std_ulogic_vector(05 downto 0);
signal irq_i_int : std_ulogic_vector(07 downto 0);
signal irq_ack_o_int : std_ulogic_vector(07 downto 0);
signal freq_gen_o_int : std_ulogic_vector(02 downto 0);
constant usrcode_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(USER_CODE);
-- misc --
signal trans_en : std_logic;
begin
-- CPU ----------------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_top_inst: neo430_top
generic map (
-- general configuration --
CLOCK_SPEED => CLOCK_SPEED, -- main clock in Hz
IMEM_SIZE => IMEM_SIZE, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => DMEM_SIZE, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => usrcode_c, -- custom user code
-- module configuration --
MULDIV_USE => MULDIV_USE, -- implement multiplier/divider unit? (default=true)
WB32_USE => WB32_USE, -- implement WB32 unit? (default=true)
WDT_USE => WDT_USE, -- implement WDT? (default=true)
GPIO_USE => GPIO_USE, -- implement GPIO unit? (default=true)
TIMER_USE => TIMER_USE, -- implement timer? (default=true)
UART_USE => UART_USE, -- implement UART? (default=true)
CRC_USE => CRC_USE, -- implement CRC unit? (default=true)
CFU_USE => CFU_USE, -- implement CF unit? (default=false)
PWM_USE => PWM_USE, -- implement PWM controller? (default=true)
TWI_USE => TWI_USE, -- implement two wire serial interface? (default=true)
SPI_USE => SPI_USE, -- implement SPI? (default=true)
TRNG_USE => TRNG_USE, -- implement TRNG? (default=false)
EXIRQ_USE => EXIRQ_USE, -- implement EXIRQ? (default=true)
FREQ_GEN_USE => FREQ_GEN_USE, -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => clk_i_int, -- global clock, rising edge
rst_i => rst_i_int, -- global reset, async, low-active
-- parallel io --
gpio_o => gpio_o_int, -- parallel output
gpio_i => gpio_i_int, -- parallel input
-- pwm channels --
pwm_o => pwm_o_int, -- pwm channels
-- arbitrary frequency generator --
freq_gen_o => freq_gen_o_int, -- programmable frequency output
-- serial com --
uart_txd_o => uart_txd_o_int, -- UART send data
uart_rxd_i => uart_rxd_i_int, -- UART receive data
spi_sclk_o => spi_sclk_o_int, -- serial clock line
spi_mosi_o => spi_mosi_o_int, -- serial data line out
spi_miso_i => spi_miso_i_int, -- serial data line in
spi_cs_o => spi_cs_o_int, -- SPI CS
twi_sda_io => twi_sda_io, -- twi serial data line
twi_scl_io => twi_scl_io, -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o => wb_core.adr, -- address
wb_dat_i => wb_core.di, -- read data
wb_dat_o => wb_core.do, -- write data
wb_we_o => wb_core.we, -- read/write
wb_sel_o => wb_core.sel, -- byte enable
wb_stb_o => wb_core.stb, -- strobe
wb_cyc_o => wb_core.cyc, -- valid cycle
wb_ack_i => wb_core.ack, -- transfer acknowledge
-- interrupts --
ext_irq_i => irq_i_int, -- external interrupt request line
ext_ack_o => irq_ack_o_int -- external interrupt request acknowledge
);
-- Output Type Conversion ---------------------------------------------------
-- -----------------------------------------------------------------------------
clk_i_int <= std_ulogic(clk_i);
rst_i_int <= std_ulogic(rst_i);
gpio_i_int <= std_ulogic_vector(gpio_i);
uart_rxd_i_int <= std_ulogic(uart_rxd_i);
spi_miso_i_int <= std_ulogic(spi_miso_i);
irq_i_int <= std_ulogic_vector(ext_irq_i);
gpio_o <= std_logic_vector(gpio_o_int);
pwm_o <= std_logic_vector(pwm_o_int);
uart_txd_o <= std_logic(uart_txd_o_int);
spi_sclk_o <= std_logic(spi_sclk_o_int);
spi_mosi_o <= std_logic(spi_mosi_o_int);
spi_cs_o <= std_logic_vector(spi_cs_o_int);
ext_ack_o <= std_logic_vector(irq_ack_o_int);
freq_gen_o <= std_logic_vector(freq_gen_o_int);
-- Wishbone-to-Avalon Bridge ------------------------------------------------
-- -----------------------------------------------------------------------------
-- Type Conversion --
wb_conv.adr <= std_logic_vector(wb_core.adr);
wb_conv.do <= std_logic_vector(wb_core.do);
wb_conv.we <= std_logic(wb_core.we);
wb_conv.sel <= std_logic_vector(wb_core.sel);
wb_conv.stb <= std_logic(wb_core.stb);
wb_conv.cyc <= std_logic(wb_core.cyc);
wb_core.di <= std_ulogic_vector(wb_conv.di);
wb_core.ack <= std_ulogic(wb_conv.ack);
active_transfer: process(clk_i_int)
begin
if rising_edge(clk_i_int) then
trans_en <= wb_conv.cyc and (trans_en or wb_conv.stb); -- keep STB virtually alive
end if;
end process active_transfer;
-- Wishbone -> Avalon
avm_address <= wb_conv.adr;
avm_writedata <= wb_conv.do;
avm_byteenable <= wb_conv.sel;
avm_write <= wb_conv.cyc and (wb_conv.stb or trans_en) and wb_conv.we;
avm_read <= wb_conv.cyc and (wb_conv.stb or trans_en) and (not wb_conv.we);
-- Avalon -> Wishbone
wb_conv.di <= avm_readdata;
wb_conv.ack <= wb_conv.cyc and (not avm_waitrequest);
end neo430_top_avm_rtl;
|
bsd-3-clause
|
003e9aa9eaced5c5263178be5fedd3fb
| 0.53423 | 3.894651 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc432.vhd
| 4 | 3,301 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc432.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00432ent IS
END c03s02b01x01p19n01i00432ent;
ARCHITECTURE c03s02b01x01p19n01i00432arch OF c03s02b01x01p19n01i00432ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2severity_level_cons_vector is array (row,column) of severity_level;
constant C1 : s2severity_level_cons_vector := (others => (others => note));
function complex_scalar(s : s2severity_level_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return s2severity_level_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : s2severity_level_cons_vector;
signal S2 : s2severity_level_cons_vector;
signal S3 : s2severity_level_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00432"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00432 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00432arch;
|
gpl-2.0
|
29fcfbbfb202c3bd63eddcff685800d0
| 0.657377 | 3.603712 | false | true | false | false |
velentr/foundry.vhdl
|
adder.vhd
| 1 | 3,923 |
--------------------------------------------------------------------------------
-- adder.vhd
--
-- This file contains a simple N-bit full adder/subtractor using a carry chain.
-- The carry out of each bit is used to calculate that sum of the next bit.
-- This will slow the operation down slightly, but will reduce the amount of
-- logic required.
--
-- When 'Sub' is inactive, the operation 'OpA + OpB' is performed. If 'Sub' is
-- inactive, then 'OpA - OpB' is performed.
--
-- Note that the generic parameter N determines the number of bits of the input
-- and output, as well as the indices of the carry outputs. It should generally
-- be an even number for the half-carry to work properly.
--
-- The size of this cell is O(N). The speed of this cell is O(N).
--
-- Dependencies:
-- None.
--
-- Revision History:
-- 27 Jan 2015 Brian Kubisiak Initial revision.
-- 18 Jul 2015 Brian Kubisiak Small tweaks, updated documentation.
--
--------------------------------------------------------------------------------
-- bring in the necessary packages
library ieee;
use ieee.std_logic_1164.all;
-- Adder
--
-- parameters:
-- N (integer) Number of bits in the operands/result.
-- inputs:
-- Cin (std_logic) Carry/borrow for the adder.
-- OpA (std_logic_vector) First operand to the adder/subtractor.
-- OpB (std_logic_vector) Second operand to the adder/subtractor.
-- Sub (std_logic) Perform 'a - b' instead of 'a + b'. Active
-- high.
--
-- outputs:
-- Res (std_logic_vector) Result of the addition
-- Cout (std_logic) Carry out of bit N-1
-- Coutv (std_logic) Carry out of bit N-2, used for finding oflow
-- HCout (std_logic) Carry out of bit (N/2)-1 (half carry)
--
entity Adder is
-- N determines the size of the adder. Should be an even number.
generic (N : integer);
port (
-- Carry input.
Cin : in std_logic;
-- Indicates subtraction should be performed, active high.
Sub : in std_logic;
-- Operands on which to perform addition/subtraction.
OpA : in std_logic_vector(N-1 downto 0);
OpB : in std_logic_vector(N-1 downto 0);
-- Carry output of bit N-1.
Cout : out std_logic;
-- Carry out of bit N-2, used for finding overflow.
Coutv : out std_logic;
-- Carry out of bit (N/2)-1.
HCout : out std_logic;
-- Result of the addition/subtraction
Res : out std_logic_vector(N-1 downto 0)
);
end Adder;
--
-- This adder/subtractor uses a for-generate loop to create a carry chain of
-- full adders/subtractors. It saves the carry bits, so these can easily be
-- output.
--
architecture carry_chain of Adder is
-- This signal holds the carries into each bit
signal carry : std_logic_vector(N downto 0);
-- This is the second operand, inverted if subtracting
signal OpBmod: std_logic_vector(N-1 downto 0);
begin
-- Invert the carry input if subtracting
carry(0) <= Cin xor Sub;
-- Invert operand B if subtracting
InvB: for I in 0 to N-1 generate
OpBmod(I) <= OpB(I) xor Sub;
end generate InvB;
-- Chain together all the carry bits
FullAdder: for I in 0 to N-1 generate
-- Calculate each result bit based on the inputs and the carry in
Res(I) <= OpA(I) xor OpBmod(I) xor carry(I);
-- Base the next carry on the result
carry(I+1) <= ((OpA(I) xor OpBmod(I)) and carry(I))
or (OpA(I) and OpBmod(I));
end generate FullAdder;
-- Now we can just output the carry bits, inverted if we were subtracting
Cout <= carry(N) xor sub;
Coutv <= carry(N-1) xor sub;
HCout <= carry(N/2) xor sub;
end carry_chain;
|
mit
|
ef2178e85bc9b15e92c0497008ddd3a6
| 0.584247 | 3.801357 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd
| 4 | 1,473 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
library ieee; use ieee.math_real.all;
entity lowpass is
port ( terminal input : electrical;
terminal output : electrical );
end entity lowpass;
----------------------------------------------------------------
architecture ltf of lowpass is
quantity vin across input to electrical_ref;
quantity vout across iout through output to electrical_ref;
constant wp : real := 10.0 * math_2_pi; -- pole in rad/s
constant num : real_vector := (0 => wp); -- numerator in s
constant den : real_vector := (wp, 1.0); -- denominator in s
begin
vout == vin'ltf(num, den);
end architecture ltf;
|
gpl-2.0
|
4e7dc810a00cc7f78b49cb3ab56f0dca
| 0.690428 | 4.149296 | false | false | false | false |
tristanseifert/68komputer
|
VideoWriteFIFO.vhd
| 1 | 7,646 |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: VideoWriteFIFO.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.0 Build 156 04/24/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY VideoWriteFIFO IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC
);
END VideoWriteFIFO;
ARCHITECTURE SYN OF videowritefifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_hint : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
rdreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(35 DOWNTO 0);
rdempty <= sub_wire2;
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone II",
lpm_hint => "MAXIMIZE_SPEED=5,",
lpm_numwords => 32,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 36,
lpm_widthu => 5,
overflow_checking => "ON",
rdsync_delaypipe => 4,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 4
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "32"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "36"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "36"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "36"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL "data[35..0]"
-- Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL "q[35..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 36 0 data 0 0 36 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 36 0 @q 0 0 36 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoWriteFIFO.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoWriteFIFO.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoWriteFIFO.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoWriteFIFO.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoWriteFIFO_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
bsd-2-clause
|
798e1c0b72f829892daa31dc23227b51
| 0.650929 | 3.505731 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/game/wtr_clk.vhd
| 1 | 1,538 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: WTR_CLK
-- AUTHORS: Ondřej Dujíček <[email protected]>
-- Vojtěch Jeřábek <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity WTR_CLK is
generic (
FLIP_FLOPS : natural := 26
);
Port (
CLK : in std_logic;
RST : in std_logic;
CLOCK_DEFI : in std_logic_vector(FLIP_FLOPS-1 downto 0);
ENABLE_OUT : out std_logic
);
end WTR_CLK;
architecture Behavioral of WTR_CLK is
signal counter_p : std_logic_vector(FLIP_FLOPS-1 downto 0);
begin
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
ENABLE_OUT <= '1';
counter_p <= (others=>'0');
else
if (counter_p = clock_defi) then
ENABLE_OUT <= '1';
counter_p <= (others=>'0');
else
ENABLE_OUT <= '0';
counter_p <= counter_p+1;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
02ba6f03466ea03025788593a9433c8c
| 0.441906 | 4.107239 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc571.vhd
| 4 | 2,847 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc571.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:34 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:32 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:06 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00571ent IS
END c03s04b01x00p01n01i00571ent;
ARCHITECTURE c03s04b01x00p01n01i00571arch OF c03s04b01x00p01n01i00571ent IS
type integer_cons_vector is array (15 downto 0) of integer;
type integer_cons_vector_file is file of integer_cons_vector;
constant C19 : integer_cons_vector := (others => 3);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : integer_cons_vector_file open read_mode is "iofile.30";
variable v : integer_cons_vector;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C19) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00571"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00571 - File reading operation (integer_cons_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00571arch;
|
gpl-2.0
|
f228db01549da027b117ace6e80cee8a
| 0.565508 | 3.948682 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/perf02/result.vhd
| 3 | 1,394 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity result is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0)
);
end result;
architecture augh of result is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
gpl-2.0
|
4ca6ae1d4c8a62cecb83de80d027118c
| 0.672166 | 2.91023 | false | false | false | false |
123gmax/Digital-Lab
|
Lab1/final_design/counter/counter.vhd
| 2 | 2,365 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ganesh Hegde and Alex
--
-- Create Date: 09/01/2015 10:52:25 AM
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port (
UP: in std_logic;
AUTO: in std_logic;
LOAD: in std_logic;
VALUE: in std_logic_vector(3 downto 0);
TICK: in std_logic;
COUNT: out std_logic_vector(3 downto 0);
RESET: in std_logic;
clk: in std_logic
);
end counter;
architecture beh of counter is
signal n_count:unsigned(3 downto 0);
signal p_count:unsigned(3 downto 0);
signal sum: unsigned(3 downto 0);
signal addend: unsigned(3 downto 0);
signal clk_1sec:std_logic;
signal pulse: std_logic;
signal clk_count : unsigned(26 downto 0);
begin
--Clock process
process(clk,RESET)
begin
if(RESET ='1') then
clk_1sec <= '0';
clk_count <= (others => '0');
elsif (clk' event and clk ='1') then
clk_count <= clk_count + 1;
clk_1sec <= std_logic(clk_count(26));
end if;
end process;
--State register
process(pulse,LOAD,VALUE)
begin
if(LOAD = '1') then
p_count <= unsigned(VALUE);
elsif(pulse' event and pulse ='1') then
p_count <= n_count;
end if;
end process;
--State reg clock logic
with AUTO select
pulse <= TICK when '0',
clk_1sec when others;
--Next state logic
n_count <= sum;
--UP/DOWN select
with UP select
addend <= "1111" when '0',
"0001" when others;
--Adder
sum <= p_count + addend;
--Output Logic
COUNT <= std_logic_vector(p_count);
end beh;
|
gpl-2.0
|
4424935de674cc981a51d3352521e6e0
| 0.566173 | 3.736177 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd
| 4 | 2,262 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity computer_system is
end entity computer_system;
-- end not in book
architecture abstract of computer_system is
subtype word is bit_vector(31 downto 0);
signal address : natural;
signal read_data, write_data : word;
signal mem_read, mem_write : bit := '0';
signal mem_ready : bit := '0';
begin
cpu : process is
variable instr_reg : word;
variable PC : natural;
-- . . . -- other declarations
begin
loop
address <= PC;
mem_read <= '1';
wait until mem_ready = '1';
instr_reg := read_data;
mem_read <= '0';
wait until mem_ready = '0';
PC := PC + 4;
-- . . . -- execute the instruction
end loop;
end process cpu;
memory : process is
type memory_array is array (0 to 2**14 - 1) of word;
variable store : memory_array := (
-- . . .
-- not in book
0 => X"0000_0000",
1 => X"0000_0004",
2 => X"0000_0008",
3 => X"0000_000C",
4 => X"0000_0010",
5 => X"0000_0014",
others => X"0000_0000"
-- end not in book
);
begin
wait until mem_read = '1' or mem_write = '1';
if mem_read = '1' then
read_data <= store( address / 4 );
mem_ready <= '1';
wait until mem_read = '0';
mem_ready <= '0';
else
-- . . . -- perform write access
end if;
end process memory;
end architecture abstract;
|
gpl-2.0
|
b0c6d1c54bd3fd8833d99606877e0155
| 0.600354 | 3.788945 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd
| 4 | 2,108 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity lowpass is
generic ( fp : real := 10.0; -- pole in Hz for 'zoh, 'delayed
Fsmp : real := 10.0e3 ); -- sample frequency for 'zoh, 'delayed
port ( terminal input : electrical;
terminal output: electrical );
end entity lowpass;
----------------------------------------------------------------
architecture z_minus_1 of lowpass is
quantity vin across input to electrical_ref;
quantity vout across iout through output to electrical_ref;
quantity vin_sampled : real; -- discrete sample of input quantity
quantity vin_zm1, vout_zm1 : real; -- z**-1
constant Tsmp : real := 1.0 / Fsmp; -- sample period
constant wp : real := fp * math_2_pi; -- pole in rad/s
constant n0 : real := Tsmp * wp; -- z0 numerator coefficient
constant n1 : real := Tsmp * wp; -- z-1 numerator coefficient
constant d0 : real := Tsmp * wp + 2.0; -- z0 denominator coefficient
constant d1 : real := Tsmp * wp - 2.0; -- z-1 denominator coefficient
begin
vin_sampled == vin'zoh(Tsmp);
vin_zm1 == vin_sampled'delayed(Tsmp);
vout_zm1 == vout'delayed(Tsmp);
vout == vin_sampled * n0 / d0 + n1 * vin_zm1 / d0 - d1 * vout_zm1 / d0;
end z_minus_1;
|
gpl-2.0
|
fb0747d090526a0b0f1e3fee39f22cdd
| 0.661765 | 3.757576 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc759.vhd
| 4 | 8,149 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc759.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00759pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
end c01s01b01x01p05n02i00759pkg;
use work.c01s01b01x01p05n02i00759pkg.ALL;
ENTITY c01s01b01x01p05n02i00759ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen :integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen10 : string := "shishir";
Cgen11 : bit_vector := B"0011";
Cgen12 : boolean_vector := (true,false);
Cgen13 : severity_level_vector := (note,error);
Cgen14 : integer_vector := (1,2,3,4);
Cgen15 : real_vector := (1.0,2.0,3.0,4.0);
Cgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
Cgen17 : natural_vector := (1,2,3,4);
Cgen18 : positive_vector := (1,2,3,4) );
END c01s01b01x01p05n02i00759ent;
ARCHITECTURE c01s01b01x01p05n02i00759arch OF c01s01b01x01p05n02i00759ent IS
constant Vgen1 : boolean := true;
constant Vgen2 : bit := '1';
constant Vgen3 : character := 's';
constant Vgen4 : severity_level := note;
constant Vgen5 : integer := 3;
constant Vgen6 : real := 3.0;
constant Vgen7 : time := 3 ns;
constant Vgen8 : natural := 1;
constant Vgen9 : positive := 1;
constant Vgen10 : string (one to seven):= "shishir";
constant Vgen11 : bit_vector(zero to three) := B"0011";
constant Vgen12 : boolean_vector(zero to one) := (true,false);
constant Vgen13 : severity_level_vector(zero to one) := (note,error);
constant Vgen14 : integer_vector(zero to three) := (1,2,3,4);
constant Vgen15 : real_vector(zero to three) := (1.0,2.0,3.0,4.0);
constant Vgen16 : time_vector(zero to three) := (1 ns, 2 ns, 3 ns, 4 ns);
constant Vgen17 : natural_vector(zero to three) := (1,2,3,4);
constant Vgen18 : positive_vector(zero to three) := (1,2,3,4);
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen10 = C10 report "Initializing signal with generic Vgen10 does not work" severity error;
assert Vgen11 = C11 report "Initializing signal with generic Vgen11 does not work" severity error;
assert Vgen12 = C12 report "Initializing signal with generic Vgen12 does not work" severity error;
assert Vgen13 = C13 report "Initializing signal with generic Vgen13 does not work" severity error;
assert Vgen14 = C14 report "Initializing signal with generic Vgen14 does not work" severity error;
assert Vgen15 = C15 report "Initializing signal with generic Vgen15 does not work" severity error;
assert Vgen16 = C16 report "Initializing signal with generic Vgen16 does not work" severity error;
assert Vgen17 = C17 report "Initializing signal with generic Vgen17 does not work" severity error;
assert Vgen18 = C18 report "Initializing signal with generic Vgen18 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***PASSED TEST: c01s01b01x01p05n02i00759"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***FAILED TEST: c01s01b01x01p05n02i00759 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00759arch;
|
gpl-2.0
|
ea32b2e8c505535c3ae1721aad329a85
| 0.603755 | 3.75357 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/Architecture1_Pipeline/decryptionFinalCore_V1.vhd
| 1 | 7,110 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 02:47:07 PM
-- Design Name:
-- Module Name: decryptionFinalCore_V1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decryptionFinalCore_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
memorySourceSelector : in STD_LOGIC;
keySelector : in STD_LOGIC_VECTOR (1 downto 0);
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end decryptionFinalCore_V1;
architecture Behavioral of decryptionFinalCore_V1 is
component addRoundKey is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
keyIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component memoryUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SELB : in STD_LOGIC;
wordAIn : in STD_LOGIC_VECTOR (31 downto 0);
wordBin : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component invShiftRows is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
blockIn : in STD_LOGIC_VECTOR (127 downto 0);
blockOut : out STD_LOGIC_VECTOR (127 downto 0));
end component;
component invSubByte is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
signal mu0_Out, mu1_Out, mu2_Out, mu3_Out, mu4_Out, mu5_Out : STD_LOGIC_VECTOR(31 downto 0);
signal invSubBytes_In, invSubBytes_Out, addRoundKey_KeyIn: STD_LOGIC_VECTOR(31 downto 0);
signal invShiftRows_In, invShiftRows_Out : STD_LOGIC_VECTOR(127 downto 0);
signal ZERO_BIT : STD_LOGIC := '0';
signal ZERO_WORD : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
ZERO_BIT <= '0';
ZERO_WORD <= (others => '0');
mu0: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO_BIT,
wordAIn => WORD_IN,
wordBIn => ZERO_WORD,
wordOut => mu0_Out);
mu1: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO_BIT,
wordAIn => mu0_Out,
wordBIn => ZERO_WORD,
wordOut => mu1_Out);
mu2: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO_BIT,
wordAIn => mu1_Out,
wordBIn => ZERO_WORD,
wordOut => mu2_Out);
invShiftRows_In <= mu2_Out & mu1_Out & mu0_Out & WORD_IN;
invShiftRows0: invShiftRows port map( CLK => CLK,
RESET => RESET,
blockIn => invShiftRows_In,
blockOut => invShiftRows_Out);
mu3: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => memorySourceSelector,
wordAIn => invShiftRows_Out(31 downto 0),
wordBIn => invShiftRows_Out(31 downto 0),
wordOut => mu3_Out);
mu4: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => memorySourceSelector,
wordAIn => mu3_Out,
wordBIn => invShiftRows_Out(63 downto 32),
wordOut => mu4_Out);
mu5: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => memorySourceSelector,
wordAIn => mu4_Out,
wordBIn => invShiftRows_Out(95 downto 64),
wordOut => mu5_Out);
invSubBytes_In <= invShiftRows_Out(127 downto 96) when (memorySourceSelector = '1')
else mu5_Out;
invSubBytes0: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(7 downto 0),
byteOut => invSubBytes_Out(7 downto 0));
invSubBytes1: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(15 downto 8),
byteOut => invSubBytes_Out(15 downto 8));
invSubBytes2: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(23 downto 16),
byteOut => invSubBytes_Out(23 downto 16));
invSubBytes3: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(31 downto 24),
byteOut => invSubBytes_Out(31 downto 24));
addRoundKeySelector: process(cipherKey, keySelector)
begin
case keySelector is
when "11" => addRoundKey_KeyIn <= cipherKey(127 downto 96);
when "10" => addRoundKey_KeyIn <= cipherKey(95 downto 64);
when "01" => addRoundKey_KeyIn <= cipherKey(63 downto 32);
when "00" => addRoundKey_KeyIn <= cipherKey(31 downto 0);
when others => addRoundKey_KeyIn <= (others => '0');
end case;
end process;
addRoundKey0: addRoundKey port map( CLK => CLK,
RESET => RESET,
wordIn => invSubBytes_Out,
keyIn => addRoundKey_KeyIn,
wordOut => WORD_OUT);
end Behavioral;
|
gpl-2.0
|
e6913216d7fb43ee8d43678158bb8ffe
| 0.431083 | 5.398633 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/control/ps2.vhd
| 1 | 4,840 |
-- ps2.vhd - Kompletni radic portu PS2
-- Autori: Jakub Cabal
-- Posledni zmena: 19.11.2014
-- Popis: Tato jednotka zajistuje kompletni komunikaci s portem PS2
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PS2 is
Port (
CLK : in STD_LOGIC; -- Vychozi hodinovy signal
RST : in STD_LOGIC; -- Vychozi synchronni reset
PS2C : in STD_LOGIC; -- Hodinovy signal z PS2 portu
PS2D : in STD_LOGIC; -- Seriova vstupni data z PS2 portu
KEY_W : out STD_LOGIC; -- Znaci ze byla stisknuta klavesa W
KEY_S : out STD_LOGIC; -- Znaci ze byla stisknuta klavesa S
KEY_A : out STD_LOGIC; -- Znaci ze byla stisknuta klavesa A
KEY_D : out STD_LOGIC; -- Znaci ze byla stisknuta klavesa D
KEY_SPACE : out STD_LOGIC -- Znaci ze byla stisknuta klavesa SPACE
);
end PS2;
architecture FULL of PS2 is
signal sig_ps2c_deb : STD_LOGIC;
signal sig_ps2rx_valid : STD_LOGIC;
signal sig_ps2rx_data : STD_LOGIC_VECTOR(7 downto 0);
signal sig_key_code : STD_LOGIC_VECTOR(7 downto 0);
signal sig_key_w : STD_LOGIC;
signal sig_key_s : STD_LOGIC;
signal sig_key_a : STD_LOGIC;
signal sig_key_d : STD_LOGIC;
signal sig_key_space : STD_LOGIC;
begin
----------------------------------------------------------------------
-- Propojeni vnitrnich podkomponent
----------------------------------------------------------------------
-- PS2 Debouncer
ps2_debouncer_i: entity work.DEBOUNCER
port map(
CLK => CLK,
RST => RST,
DIN => PS2C,
DOUT => sig_ps2c_deb
);
-- Prijem seriovych dat z PS2
ps2_rx_1: entity work.PS2_RX
port map(
CLK => CLK,
RST => RST,
PS2C => sig_ps2c_deb,
PS2D => PS2D,
PS2RX_DATA => sig_ps2rx_data,
PS2RX_VALID => sig_ps2rx_valid
);
-- Ziskani kodu klavesy
kb_code_1: entity work.KB_CODE
port map(
CLK => CLK,
RST => RST,
PS2RX_DATA => sig_ps2rx_data,
PS2RX_VALID => sig_ps2rx_valid,
KEY_CODE => sig_key_code
);
----------------------------------------------------------------------
-- Generovani vystupnich signalu
----------------------------------------------------------------------
-- Generovani signalu o zmacknute klavesy W
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
sig_key_w <= '0';
elsif (sig_key_code = X"1D") then
sig_key_w <= '1';
else
sig_key_w <= '0';
end if;
end if;
end process;
rised1: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_key_w,
VYSTUP => KEY_W
);
-- Generovani signalu o zmacknute klavesy S
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
sig_key_s <= '0';
elsif (sig_key_code = X"1B") then
sig_key_s <= '1';
else
sig_key_s <= '0';
end if;
end if;
end process;
rised2: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_key_s,
VYSTUP => KEY_S
);
-- Generovani signalu o zmacknute klavesy A
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
sig_key_a <= '0';
elsif (sig_key_code = X"1C") then
sig_key_a <= '1';
else
sig_key_a <= '0';
end if;
end if;
end process;
rised3: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_key_a,
VYSTUP => KEY_A
);
-- Generovani signalu o zmacknute klavesy D
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
sig_key_d <= '0';
elsif (sig_key_code = X"23") then
sig_key_d <= '1';
else
sig_key_d <= '0';
end if;
end if;
end process;
rised4: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_key_d,
VYSTUP => KEY_D
);
-- Generovani signalu o zmacknute klavesy SPACE
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
sig_key_space <= '0';
elsif (sig_key_code = X"29") then
sig_key_space <= '1';
else
sig_key_space <= '0';
end if;
end if;
end process;
rised5: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_key_space,
VYSTUP => KEY_SPACE
);
end FULL;
|
mit
|
e7ad27a1de5289ba1515256ae4d03151
| 0.484917 | 3.482014 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket14/tb.vhd
| 3 | 486 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb is
end tb;
architecture behav of tb is
signal clk : std_logic;
begin -- behav
process
begin
for i in 1 to 5 loop
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end loop; -- i
end process;
inst : entity work.scrambler port map (
clk => clk,
en => '0',
reset => '0',
seed => '0',
d_in => '0',
d_out => open);
end behav;
|
gpl-2.0
|
c982b93c8e9aa0c3af2e4fe86d2c43e9
| 0.534979 | 3.018634 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/pc_next.vhd
| 2 | 2,187 |
---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_future_test : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_future_test <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
|
mit
|
3f606e4b3ce6f0f7b2ef8d2c7d8b645e
| 0.565158 | 3.344037 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug15/phys.vhdl
| 3 | 409 |
package physical is
type FREQ is range 0 to INTEGER'high units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
-- THz = 1000 GHz;
end units;
end package;
entity tb is
end;
use work.physical.all;
architecture test of tb is
constant CLOCK_FREQ : FREQ := 100.0 MHz;
procedure p (a : freq := 1.0 Mhz) is
begin
end p;
begin
p (clock_freq);
-- empty
end architecture;
|
gpl-2.0
|
1df4a9fdaaf2c166e97153f4ae0754f4
| 0.628362 | 3.220472 | false | false | false | false |
stnolting/neo430
|
rtl/fpga_specific/lattice_ice40up/neo430_dmem.ice40up_spram.vhd
| 1 | 6,920 |
-- #################################################################################################
-- # << NEO430 - Data memory ("DMEM") for Lattice ice40 UltraPlus >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
library iCE40UP;
use iCE40UP.components.all;
entity neo430_dmem is
generic (
DMEM_SIZE : natural := 2*1024 -- internal DMEM size in bytes
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic_vector(01 downto 0); -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_dmem;
architecture neo430_dmem_rtl of neo430_dmem is
-- local signals --
signal acc_en : std_ulogic;
signal rdata : std_ulogic_vector(15 downto 0);
signal rden : std_ulogic;
signal addr : integer;
-- RAM --
type dmem_file_t is array (0 to DMEM_SIZE/2-1) of std_ulogic_vector(7 downto 0);
signal dmem_file_l : dmem_file_t;
signal dmem_file_h : dmem_file_t;
-- RAM attribute to inhibit bypass-logic - Intel only! --
attribute ramstyle : string;
attribute ramstyle of dmem_file_l : signal is "no_rw_check";
attribute ramstyle of dmem_file_h : signal is "no_rw_check";
-- RAM attribute to inhibit bypass-logic - Lattice ICE40up only! --
attribute syn_ramstyle : string;
attribute syn_ramstyle of dmem_file_l : signal is "no_rw_check";
attribute syn_ramstyle of dmem_file_h : signal is "no_rw_check";
-- SPRAM signals --
signal spram_clk : std_logic;
signal spram_addr : std_logic_vector(13 downto 0);
signal spram_di : std_logic_vector(15 downto 0);
signal spram_do : std_logic_vector(15 downto 0);
signal spram_be : std_logic_vector(03 downto 0);
signal spram_we : std_logic;
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i >= dmem_base_c) and (addr_i < std_ulogic_vector(unsigned(dmem_base_c) + DMEM_SIZE)) else '0';
addr <= to_integer(unsigned(addr_i(index_size_f(DMEM_SIZE/2) downto 1))); -- word aligned
-- Memory Access ------------------------------------------------------------
-- -----------------------------------------------------------------------------
dmem_spram_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di, -- I
MASKWE => spram_be, -- I
WE => spram_we, -- I
CS => '1', -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => '0', -- I
PWROFF_N => '1', -- I
DO => spram_do -- O
);
-- signal type conversion --
spram_clk <= std_logic(clk_i);
spram_addr <= std_logic_vector(addr_i(13+1 downto 0+1));
spram_di <= std_logic_vector(data_i(15 downto 0));
spram_we <= '1' when ((acc_en and (wren_i(0) or wren_i(1))) = '1') else '0'; -- global write enable
rdata <= std_ulogic_vector(spram_do);
spram_be(1 downto 0) <= "11" when (wren_i(0) = '1') else "00"; -- low byte write enable
spram_be(3 downto 2) <= "11" when (wren_i(1) = '1') else "00"; -- high byte write enable
buffer_ff: process(clk_i)
begin
-- sanity check
if (DMEM_SIZE > 12*1024) then
assert false report "D-mem size out of range! Max 12kB!" severity error;
end if;
-- buffer --
if rising_edge(clk_i) then
rden <= rden_i and acc_en;
end if;
end process buffer_ff;
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
end neo430_dmem_rtl;
|
bsd-3-clause
|
f85098af6f062e7759cc4da0990e6b4e
| 0.484971 | 4.438743 | false | false | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/toplevel.vhd
| 3 | 3,468 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplier is
port (clk : in std_logic;
reset : in std_logic;
addrA : in std_logic_vector(2 downto 0);
addrB : in std_logic_vector(2 downto 0);
showAB: in std_logic;
start: in std_logic;
result: out std_logic_vector(31 downto 0);
outAB : out std_logic_vector(31 downto 0);
ready : out std_logic_vector(7 downto 0)
);
end multiplier;
architecture synt of multiplier is
signal romAOut : std_logic_vector (31 downto 0);
signal romBOut : std_logic_vector (31 downto 0);
component graph_driver
port (in_graph : in std_logic_vector(31 downto 0);
out_graph : out std_logic_vector(31 downto 0)
);
end component;
signal outAB_graph_s: std_logic_vector(31 downto 0);
signal result_graph_s: std_logic_vector(31 downto 0);
component romMemOpA
port(
addr : in std_logic_vector (2 downto 0);
dataOut : out std_logic_vector (31 downto 0)
);
end component;
component romMemOpB
port(
addr : in std_logic_vector (2 downto 0);
dataOut : out std_logic_vector (31 downto 0)
);
end component;
component device
port (a,b: in std_logic_vector(31 downto 0);
clk,en,rst: in std_logic;
c: out std_logic_vector(31 downto 0);
done: out std_logic
);
end component;
signal en_mul:std_logic;
signal rst_mul:std_logic;
signal result_graph_ss: std_logic_vector(31 downto 0);
signal done_mult: std_logic;
signal graph: std_logic_vector(31 downto 0);
type state is (initial, multiply, view_result);
signal CurrentState, NextState : state;
begin
process(CurrentState,start) begin
NextState<=initial;
result_graph_s<=(others=>'0');
case CurrentState is
when initial =>
en_mul<='0';
rst_mul<='0';
-----result<="11110000010000000010010011110001";
if(start='0') then
NextState<=multiply;
else
NextState<=initial;
end if;
when multiply =>
en_mul<='1';
rst_mul<='1';
if(done_mult='1') then
NextState<=view_result;
else
NextState<=multiply;
end if;
when view_result =>
if(start='0') then
NextState<=initial;
else
NextState<=view_result;
end if;
end case;
end process;
transitions:process (clk, reset) begin
if reset='0'then
CurrentState <= initial;
elsif (clk'event and clk='1')then
CurrentState <= NextState;
end if;
end process;
uOpA: romMemOpA
port map (
addr => addrA,
dataOut => romAOut
);
uOpB: romMemOpB
port map (
addr => addrB,
dataOut => romBOut
);
uMult: device
port map (
a => romAOut,
b => romBOut,
clk=>clk ,
en=> en_mul,
rst=> rst_mul,
c => result_graph_ss,
done=>done_mult
);
outtAB_graph: graph_driver port map(in_graph=>outAB_graph_s,out_graph=>outAB);
result_graph: graph_driver port map(in_graph=>result_graph_ss,out_graph=>result);
-- When the button assoiciated to outAB is pushed romAOut is displayed
outAB_graph_s<= romAOut when showAB = '0'
else romBOut;
ready(7 downto 0) <= (others => done_mult);
end synt;
|
mit
|
5726d642d8a99f42f36dc73eaa2e0a45
| 0.589389 | 3.616267 | false | false | false | false |
siavooshpayandehazad/high_level_test_pattern_gen
|
Test/AP.vhd
| 1 | 15,876 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.LIB.ALL;
ENTITY AP IS
PORT(
clock : IN std_logic;
rst : IN std_logic;
-- AP Memory/Arbiter
MemDataIn : IN AP_data_width;
MemDataOut: OUT AP_data_width;
MemAddr : OUT AP_mem_addr_width;
wrMem : OUT std_logic;
startArb : OUT std_logic;
arbMode : OUT std_logic;
arbReady : IN std_logic;
-- Fault State Memory
FSdataIn : IN AP_data_width;
FSdataOut : OUT AP_data_width;
FSwrite : OUT std_logic;
FSaddr : OUT std_logic_vector (6 downto 0);
SlotNr : OUT std_logic_vector (1 downto 0);
slot : IN std_logic;
lRP : IN std_logic;
rRP : IN std_logic;
resetFS : OUT std_logic;
-- PuT
PuTHalt : IN std_logic;
PuTContinue : OUT std_logic;
PuTReset : OUT std_logic
);
END AP;
ARCHITECTURE behave OF AP IS
-- COMPONENTS ---------
COMPONENT AP_regFile IS
PORT(
clock : IN std_logic;
rst : IN std_logic;
enable : IN std_logic;
wrAddr : IN AP_reg_select;
wrData : IN AP_data_width;
rp1Addr : IN AP_reg_select;
rp2Addr : IN AP_reg_select;
rp1Data : OUT AP_data_width;
rp2Data : OUT AP_data_width
);
END COMPONENT;
COMPONENT AP_reg_generic IS
GENERIC (reg_width : natural := 8);
PORT(
clock : IN std_logic;
rst : IN std_logic;
enable : IN std_logic;
input : IN std_logic_vector (reg_width-1 downto 0);
output : OUT std_logic_vector (reg_width-1 downto 0)
);
END COMPONENT;
COMPONENT AP_Alu IS
PORT(
clock : IN std_logic;
rst : IN std_logic;
OP_A : IN AP_data_width;
OP_B : IN AP_data_width;
ALU_OP : IN std_logic_vector(3 downto 0);
RESULT : OUT AP_data_width;
carry_out : OUT std_logic;
zero_out : OUT std_logic;
sign_out : OUT std_logic;
overflow_out : OUT std_logic
);
END COMPONENT;
-- SIGNALS ------------
signal RF_wrAddr, RF_Addr1, RF_Addr2 : AP_reg_select;
signal RF_en, IR_en, FSaddr_en, SlotNr_en, MBR_en, MAR_H_en, MAR_L_en, PC_en, rstTimer, incTimer : std_logic;
signal carry, overflow, sign, zero : std_logic;
signal RF_in, RF_out1, RF_out2, IR_out, Alu_in1, Alu_in2, Alu_out : AP_data_width;
signal MAR_L_out, MAR_L_in, MBR_out, MBR_in : AP_data_width;
signal MAR_H_out, MAR_H_in : std_logic_vector(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
signal Alu_opc : std_logic_vector(3 downto 0);
signal timer : std_logic_vector(3 downto 0);
signal FSaddr_in : std_logic_vector(6 downto 0);
signal SlotNr_in, SlotNr_out : std_logic_vector(1 downto 0);
signal PC_out, PC_in : AP_mem_addr_width;
signal instCh_in, instCh_out : std_logic_vector(0 downto 0);
signal instCh_en : std_logic;
BEGIN
SlotNr <= SlotNr_out;
control: process(IR_out, timer, PC_out, RF_out1, RF_out2, Alu_out,
MemDataIN, MBR_out, MAR_L_out, MAR_H_out, FSdataIn,
arbReady, carry, zero, sign, overflow, PuTHalt, SlotNr_out)
variable jmpCond : std_logic := '0';
begin
-- default-values
IR_en <= '0';
PC_en <= '0';
RF_en <= '0';
MBR_en <= '0';
MAR_H_en <= '0';
MAR_L_en <= '0';
FSaddr_en <= '0';
FSwrite <= '0';
wrMem <= '0';
rstTimer <= '0';
startArb <= '0';
arbMode <= '0';
incTimer <= '1';
PuTContinue <= '0';
PuTReset <= '0';
SlotNr_en <= '0';
instCh_en <= '0';
resetFS <= '0';
PC_in <= PC_out;
MemAddr <= PC_out;
Alu_opc <= (others => '0');
RF_Addr1 <= IR_out(3 downto 2);
RF_Addr2 <= IR_out(1 downto 0);
RF_wrAddr <= IR_out(3 downto 2);
Alu_in1 <= RF_out1;
Alu_in2 <= RF_out2;
RF_in <= Alu_out;
MBR_in <= MemDataIN;
MAR_H_in <= RF_out1(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
MAR_L_in <= RF_out1;
MemDataOut <= MBR_out;
FSaddr_in <= RF_out1(6 downto 0);
FSdataOut <= RF_out1;
SlotNr_in <= Alu_out(1 downto 0);
instCh_in <= IR_out(0 downto 0);
if(timer = "0000") then
-- fetch
MemAddr <= PC_out;
IR_en <= '1';
PC_en <= '1';
PC_in <= PC_out + 1;
else
if(IR_out(7) = '0') then
-- AluOp with 2 Operands
Alu_opc <= IR_out(7 downto 4);
RF_Addr1 <= IR_out(3 downto 2);
RF_Addr2 <= IR_out(1 downto 0);
RF_wrAddr <= IR_out(3 downto 2);
Alu_in1 <= RF_out1;
Alu_in2 <= RF_out2;
RF_in <= Alu_out;
RF_en <= '1';
rstTimer <= '1';
elsif(IR_out(7 downto 5) = "101") then
-- AluOp with 1 Operand
Alu_opc <= IR_out(5 downto 2);
RF_Addr1 <= IR_out(1 downto 0);
RF_wrAddr <= IR_out(1 downto 0);
Alu_in1 <= RF_out1;
RF_in <= Alu_out;
RF_en <= '1';
rstTimer <= '1';
elsif(IR_out(7 downto 5) /= "111") then
-- Ops with 1 Operand
RF_Addr1 <= IR_out(1 downto 0);
RF_wrAddr <= IR_out(1 downto 0);
case IR_out(7 downto 2) is
when "100000" =>
-- load
if(timer = "0001") then
MemAddr <= MAR_H_out & MAR_L_out;
MBR_en <= '1';
MBR_in <= MemDataIN;
elsif(timer = "0010") then
RF_in <= MBR_out;
RF_en <= '1';
rstTimer <= '1';
end if;
when "100001" =>
-- store
if(timer = "0001") then
MBR_in <= RF_out1;
MBR_en <= '1';
elsif(timer = "0010") then
wrMem <= '1';
MemAddr <= MAR_H_out & MAR_L_out;
rstTimer <= '1';
end if;
when "100010" =>
-- ldc
if(timer = "0001") then
PC_en <= '1';
PC_in <= PC_out + 1;
MBR_in <= MemDataIN;
MBR_en <= '1';
elsif(timer = "0010") then
RF_in <= MBR_out;
RF_en <= '1';
rstTimer <= '1';
end if;
when "100011" =>
-- setMarL
MAR_L_in <= RF_out1;
MAR_L_en <= '1';
rstTimer <= '1';
when "100100" =>
-- setMarH
MAR_H_in <= RF_out1(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
MAR_H_en <= '1';
rstTimer <= '1';
when "100101" | "100110" =>
-- incMar | decMar
if(timer = "0001") then
Alu_in1 <= MAR_L_out;
Alu_in2 <= "000000" & IR_out(1 downto 0);
if(IR_out(7 downto 2) = "100101") then
Alu_opc <= "0001"; -- add
else
Alu_opc <= "0010"; -- sub
end if;
MAR_L_in <= Alu_out;
MAR_L_en <= '1';
elsif(timer = "0010") then
if(carry = '1') then
Alu_in1(AP_WIDTH - 1 downto AP_ADDR_WIDTH - AP_WIDTH) <= (others => '0');
Alu_in1(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0) <= MAR_H_out;
if(IR_out(7 downto 2) = "100101") then
Alu_opc <= "1011"; -- inc
else
Alu_opc <= "1100"; -- dec
end if;
MAR_H_in <= Alu_out(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
MAR_H_en <= '1';
end if;
rstTimer <= '1';
end if;
when "110000" =>
-- setFSaddr
FSaddr_en <= '1';
FSaddr_in <= RF_out1(6 downto 0);
rstTimer <= '1';
when "110001" =>
-- readFS
RF_in <= FSdataIn;
RF_en <= '1';
rstTimer <= '1';
when "110010" =>
-- writeFS
FSdataOut <= RF_out1;
FSwrite <= '1';
rstTimer <= '1';
when others =>
rstTimer <= '1';
end case;
elsif(IR_out(7 downto 5) = "111") then
-- no Operands
if(IR_out(4) = '0') then
-- jumps
if(timer = "0001") then
case IR_out(4 downto 0) is
when "00000" =>
jmpCond := '1';
when "00001" =>
jmpCond := carry;
when "00010" =>
jmpCond := not carry;
when "00011" =>
jmpCond := sign;
when "00100" =>
jmpCond := not sign;
when "00101" =>
jmpCond := overflow;
when "00110" =>
jmpCond := not overflow;
when "00111" =>
jmpCond := zero;
when "01000" =>
jmpCond := not zero;
when "01001" =>
jmpCond := slot;
when "01010" =>
if(SlotNr_out = "11") then
jmpCond := '0';
else
jmpCond := '1';
end if;
when "01011" =>
jmpCond := not lRP;
when "01100" =>
jmpCond := not rRP;
when "01111" =>
jmpCond := not PuTHalt;
when others =>
jmpCond := '0';
end case;
PC_en <= '1';
PC_in <= PC_out + 1;
if(jmpCond = '1') then
MBR_in <= MemDataIN;
MBR_en <= '1';
end if;
elsif(timer = "0010") then
if(jmpCond = '0') then
PC_en <= '1';
PC_in <= PC_out + 1;
rstTimer <= '1';
else
PC_in(AP_ADDR_WIDTH-1 downto AP_WIDTH)
<= MBR_out(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
PC_en <= '1';
MBR_in <= MemDataIN;
MBR_en <= '1';
end if;
elsif(timer = "0011") then
PC_in(AP_WIDTH-1 downto 0) <= MBR_out;
PC_en <= '1';
MemAddr <= MAR_H_out & MAR_L_out; -- im PC könnte in diesem Takt eine zu hohe Adresse stehen (falls der adressierbare Bereich größer ist als der Speicher)
rstTimer <= '1';
end if;
else -- IR_out(4) /= '0' -> no Operand, no jump
case IR_out(4 downto 0) is
when "10000" | "10001" =>
-- fetchInstr | storeInstr.
arbMode <= IR_out(0);
incTimer <= '0';
if(timer = "0001") then
MemAddr <= MAR_H_out & MAR_L_out;
startArb <= not IR_out(0) or instCh_out(0);
incTimer <= '1';
elsif(arbReady = '1') then
rstTimer <= '1';
end if;
when "10010" =>
-- continuePuT
PuTContinue <= '1';
rstTimer <= '1';
when "10011" =>
-- resetPuT
PuTReset <= '1';
rstTimer <= '1';
when "10100" =>
-- resetFS
resetFS <= '1';
rstTimer <= '1';
when "10101" =>
-- setMar
if(timer = "0001") then
MBR_in <= MemDataIN;
MBR_en <= '1';
PC_en <= '1';
PC_in <= PC_out + 1;
elsif(timer = "0010") then
MAR_H_in <= MBR_out(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
MAR_H_en <= '1';
MBR_in <= MemDataIN;
MBR_en <= '1';
PC_en <= '1';
PC_in <= PC_out + 1;
elsif(timer = "0011") then
MAR_L_in <= MBR_out;
MAR_L_en <= '1';
rstTimer <= '1';
end if;
when "11000" | "11001" =>
-- rstInstChanged | setInstChanged
instCh_in <= IR_out(0 downto 0);
instCh_en <= '1';
rstTimer <= '1';
when "11010" =>
-- rstSlotNr
SlotNr_in <= "00";
SlotNr_en <= '1';
rstTimer <= '1';
when "11011" | "11100" =>
-- incSlotNr | decSlotNr
Alu_in1 <= "000000" & SlotNr_out;
Alu_opc <= IR_out(3 downto 0);
SlotNr_in <= Alu_out(1 downto 0);
SlotNr_en <= '1';
rstTimer <= '1';
when others =>
rstTimer <= '1';
end case;
end if;
end if;
end if;
end process;
timer_process: process(clock, rst)
begin
if (rst = '1') then
timer <= (others => '0');
elsif (clock'event and clock = '1') then
if(rstTimer = '1') then
timer <= (others => '0');
elsif(incTimer = '1') then
timer <= timer + 1;
end if;
end if;
end process;
PC: AP_reg_generic
GENERIC MAP (reg_width => AP_ADDR_WIDTH)
PORT MAP (
clock => clock,
rst => rst,
enable => PC_en,
input => PC_in,
output => PC_out
);
IR: AP_reg_generic
GENERIC MAP (reg_width => AP_WIDTH)
PORT MAP (
clock => clock,
rst => rst,
enable => IR_en,
input => MemDataIN,
output => IR_out
);
MBR: AP_reg_generic
GENERIC MAP (reg_width => AP_WIDTH)
PORT MAP (
clock => clock,
rst => rst,
enable => MBR_en,
input => MBR_in,
output => MBR_out
);
MAR_H: AP_reg_generic
GENERIC MAP (reg_width => AP_ADDR_WIDTH - AP_WIDTH)
PORT MAP (
clock => clock,
rst => rst,
enable => MAR_H_en,
input => MAR_H_in,
output => MAR_H_out
);
MAR_L: AP_reg_generic
GENERIC MAP (reg_width => AP_WIDTH)
PORT MAP (
clock => clock,
rst => rst,
enable => MAR_L_en,
input => MAR_L_in,
output => MAR_L_out
);
FS_addr: AP_reg_generic
GENERIC MAP (reg_width => 7)
PORT MAP (
clock => clock,
rst => rst,
enable => FSaddr_en,
input => FSaddr_in,
output => FSaddr
);
SlotNr_reg: AP_reg_generic
GENERIC MAP (reg_width => 2)
PORT MAP (
clock => clock,
rst => rst,
enable => SlotNr_en,
input => SlotNr_in,
output => SlotNr_out
);
regFile: AP_regFile
PORT MAP (
clock => clock,
rst => rst,
enable => RF_en,
wrAddr => RF_wrAddr,
wrData => RF_in,
rp1Addr => RF_Addr1,
rp2Addr => RF_Addr2,
rp1Data => RF_out1,
rp2Data => RF_out2
);
ALU: AP_Alu
PORT MAP (
clock => clock,
rst => rst,
OP_A => Alu_in1,
OP_B => Alu_in2,
ALU_OP => Alu_opc,
RESULT => Alu_out,
carry_out => carry,
zero_out => zero,
sign_out => sign,
overflow_out => overflow
);
InstChanged: AP_reg_generic
GENERIC MAP (reg_width => 1)
PORT MAP (
clock => clock,
rst => rst,
enable => instCh_en,
input => instCh_in,
output => instCh_out
);
END behave;
|
gpl-3.0
|
742d80f15c5b330219ccd1b01a062130
| 0.42391 | 3.691235 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_muldiv.vhd
| 1 | 11,228 |
-- #################################################################################################
-- # << NEO430 - 16-Bit Unsigned Multiplier & Divider Unit >> #
-- # ********************************************************************************************* #
-- # NOTE: This unit uses "repeated trial subtraction" as division algorithm (restoring). #
-- # NOTE: This unit uses "shifted add" as multiplication algorithm. Set 'use_dsp_mul_c' in the #
-- # package file to TRUE to use DSP slices for multiplication. #
-- # #
-- # The division unit only supports unsigned divisions. #
-- # The multiplication unit supports signed and unsigned division. #
-- # #
-- # Division: DIVIDEND / DIVIDER = QUOTIENT + REMAINDER (16-bit) / DIVIDER (16-bit) #
-- # Multiplication: FACTOR1 * FACTOR2 = PRODUCT (32-bit) #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_muldiv is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_muldiv;
architecture neo430_muldiv_rtl of neo430_muldiv is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(muldiv_size_c); -- low address boundary bit
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wr_en : std_ulogic; -- only full 16-bit word accesses!
signal rd_en : std_ulogic;
-- accessible regs --
signal opa, opb : std_ulogic_vector(15 downto 0);
signal resx, resy : std_ulogic_vector(15 downto 0);
signal operation : std_ulogic; -- '1' division, '0' multiplication
signal signed_op : std_ulogic;
-- arithmetic core & arbitration --
signal start : std_ulogic;
signal run : std_ulogic;
signal enable : std_ulogic_vector(15 downto 0);
signal try_sub : std_ulogic_vector(16 downto 0);
signal remainder : std_ulogic_vector(15 downto 0);
signal quotient : std_ulogic_vector(15 downto 0);
signal product : std_ulogic_vector(31 downto 0);
signal do_add : std_ulogic_vector(16 downto 0);
signal sign_cycle : std_ulogic;
signal opa_sext : std_ulogic;
signal opb_sext : std_ulogic;
signal p_sext : std_ulogic;
signal dsp_mul_res : std_ulogic_vector(33 downto 0);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = muldiv_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= muldiv_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wr_en <= acc_en and wren_i;
rd_en <= acc_en and rden_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
start <= '0';
opa_sext <= opa(opa'left) and signed_op;
opb_sext <= opb(opb'left) and signed_op;
if (wr_en = '1') then -- only full word accesses!
-- operands --
if (addr = muldiv_opa_resx_addr_c) then -- dividend or factor 1
opa <= data_i;
end if;
if (addr = muldiv_opb_umul_resy_addr_c) or
(addr = muldiv_opb_smul_addr_c) or
(addr = muldiv_opb_udiv_addr_c) then -- divisor or factor 2
opb <= data_i;
start <= '1'; -- trigger operation
end if;
-- operation: division/multiplication --
if (addr = muldiv_opb_umul_resy_addr_c) or (addr = muldiv_opb_smul_addr_c) then -- multiplication
operation <= '0';
else -- division
operation <= '1';
end if;
-- signed/unsigned operation --
if (addr = muldiv_opb_smul_addr_c) then
signed_op <= '1';
else
signed_op <= '0';
end if;
end if;
end if;
end process wr_access;
-- Arithmetic core ----------------------------------------------------------
-- -----------------------------------------------------------------------------
arithmetic_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- arbitration --
enable <= enable(14 downto 0) & start;
if (start = '1') then
run <= '1';
elsif (enable(15) = '1') then -- all done?
run <= '0';
end if;
-- division core --
if (operation = '1') then
if (start = '1') then -- load dividend
quotient <= opa;
remainder <= (others => '0');
elsif (run = '1') then
quotient <= quotient(14 downto 0) & (not try_sub(16));
if (try_sub(16) = '0') then -- still overflowing
remainder <= try_sub(15 downto 0);
else -- underflow
remainder <= remainder(14 downto 0) & quotient(15);
end if;
end if;
-- multiplication core --
else
if (use_dsp_mul_c = false) then -- implement serial multiplication
if (start = '1') then -- load factor 1
product(31 downto 16) <= (others => opa_sext);
product(15 downto 0) <= opa;
elsif (run = '1') then
product(31 downto 15) <= do_add(16 downto 0);
product(14 downto 0) <= product(15 downto 1);
end if;
else -- use DSP for multiplication
product(31 downto 0) <= dsp_mul_res(31 downto 0);
end if;
end if;
end if;
end process arithmetic_core;
-- DSP multiplication --
dsp_mul_res <= std_ulogic_vector(signed(opa_sext & opa) * signed(opb_sext & opb));
-- DIV: try another subtraction --
try_sub <= std_ulogic_vector(unsigned('0' & remainder(14 downto 0) & quotient(15)) - unsigned('0' & opb));
-- MUL: do another addition --
mul_update: process(product, sign_cycle, p_sext, opb_sext, opb)
begin
if (product(0) = '1') then
if (sign_cycle = '1') then -- for signed operation only: take care of negative weighted MSB
do_add <= std_ulogic_vector(unsigned(p_sext & product(31 downto 16)) - unsigned(opb_sext & opb));
else
do_add <= std_ulogic_vector(unsigned(p_sext & product(31 downto 16)) + unsigned(opb_sext & opb));
end if;
else
do_add <= p_sext & product(31 downto 16);
end if;
end process mul_update;
sign_cycle <= enable(enable'left) and signed_op;
p_sext <= product(product'left) and signed_op;
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rd_en = '1') then -- valid read access
if (addr = muldiv_opa_resx_addr_c) then
data_o <= resx; -- quotient or product low word
else -- muldiv_opb_umul_resy_addr_c =>
data_o <= resy; -- remainder or product high word
end if;
end if;
end if;
end process rd_access;
-- result selection --
resx <= product(15 downto 0) when (operation = '0') else quotient;
resy <= product(31 downto 16) when (operation = '0') else remainder;
end neo430_muldiv_rtl;
|
bsd-3-clause
|
8f6e36f6b862439bced558092c2f56ad
| 0.481831 | 4.538399 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc419.vhd
| 4 | 3,125 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc419.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00419ent IS
END c03s02b01x01p19n01i00419ent;
ARCHITECTURE c03s02b01x01p19n01i00419arch OF c03s02b01x01p19n01i00419ent IS
type time_cons_vector is array (15 downto 0) of time;
constant C1 : time_cons_vector := (others => 3 ns);
function complex_scalar(s : time_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return time_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : time_cons_vector;
signal S2 : time_cons_vector;
signal S3 : time_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00419"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00419 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00419arch;
|
gpl-2.0
|
51fe7c09304116d4a8cce676d322cfce
| 0.65216 | 3.616898 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-r.vhd
| 4 | 12,770 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlx-r.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
use work.alu_types.all,
work.reg_file_types.all;
architecture rtl of dlx is
component alu is
port ( s1 : in dlx_word;
s2 : in dlx_word;
result : out dlx_word;
func : in alu_func;
zero, negative, overflow : out std_logic );
end component alu;
component reg_file is
port ( a1 : in reg_file_addr;
q1 : out dlx_word;
a2 : in reg_file_addr;
q2 : out dlx_word;
a3 : in reg_file_addr;
d3 : in dlx_word;
write_en : in std_logic );
end component reg_file;
component latch is
port ( d : in dlx_word;
q : out dlx_word;
latch_en : in std_logic );
end component latch;
component ir_extender is
port ( d : in dlx_word;
q : out dlx_word;
immed_size_26 : in std_logic;
immed_unsigned : in std_logic;
immed_en : in std_logic );
end component ir_extender;
component reg_multiple_out is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end component reg_multiple_out;
component reg_multiple_plus_one_out is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q0 : out dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end component reg_multiple_plus_one_out;
component reg_multiple_plus_one_out_reset is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q0 : out dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs);
reset : in std_logic );
end component reg_multiple_plus_one_out_reset;
component mux2 is
port ( i0, i1 : in dlx_word;
y : out dlx_word;
sel : in std_logic);
end component mux2;
component controller is
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
width : out dlx_mem_width;
write_enable : out std_logic;
mem_enable : out std_logic;
ifetch : out std_logic;
ready : in std_logic;
alu_in_latch_en : out std_logic;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in std_logic;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
reg_write : out std_logic;
c_latch_en : out std_logic;
a_latch_en, a_out_en : out std_logic;
b_latch_en, b_out_en : out std_logic;
temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
mem_addr_mux_sel : out std_logic;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
mdr_mux_sel : out std_logic;
ir_latch_en : out std_logic;
ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
ir_immed1_en, ir_immed2_en : out std_logic;
current_instruction : in dlx_word;
mem_addr : std_logic_vector(1 downto 0);
const1, const2 : out dlx_word );
end component controller;
signal s1_bus, s2_bus : dlx_word;
signal dest_bus : dlx_word;
signal alu_in1, alu_in2 : dlx_word;
signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
signal mdr_in : dlx_word;
signal current_instruction : dlx_word;
signal pc_to_mem : dlx_address;
signal mar_to_mem : dlx_address;
signal alu_in_latch_en : std_logic;
signal alu_function : alu_func;
signal alu_zero, alu_negative, alu_overflow : std_logic;
signal reg_s1_addr, reg_s2_addr, reg_dest_addr : reg_file_addr;
signal reg_write : std_logic;
signal a_out_en, a_latch_en : std_logic;
signal b_out_en, b_latch_en : std_logic;
signal c_latch_en : std_logic;
signal temp_out_en1, temp_out_en2, temp_latch_en : std_logic;
signal iar_out_en1, iar_out_en2, iar_latch_en : std_logic;
signal pc_out_en1, pc_out_en2, pc_latch_en : std_logic;
signal mar_out_en1, mar_out_en2, mar_latch_en : std_logic;
signal mem_addr_mux_sel : std_logic;
signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : std_logic;
signal mdr_mux_sel : std_logic;
signal ir_latch_en : std_logic;
signal ir_immed1_size_26, ir_immed2_size_26 : std_logic;
signal ir_immed1_unsigned, ir_immed2_unsigned : std_logic;
signal ir_immed1_en, ir_immed2_en : std_logic;
begin
alu_s1_reg : component latch
port map ( d => s1_bus, q => alu_in1, latch_en => alu_in_latch_en );
alu_s2_reg : component latch
port map ( d => s2_bus, q => alu_in2, latch_en => alu_in_latch_en );
the_alu : component alu
port map ( s1 => alu_in1, s2 => alu_in2, result => dest_bus,
func => alu_function,
zero => alu_zero, negative => alu_negative, overflow => alu_overflow );
the_reg_file : component reg_file
port map ( a1 => reg_s1_addr, q1 => reg_file_out1,
a2 => reg_s2_addr, q2 => reg_file_out2,
a3 => reg_dest_addr, d3 => reg_file_in,
write_en => reg_write );
c_reg : component latch
port map ( d => dest_bus, q => reg_file_in, latch_en => c_latch_en );
a_reg : component reg_multiple_out
generic map ( num_outputs => 1 )
port map ( d => reg_file_out1, q(1) => s1_bus,
latch_en => a_latch_en, out_en(1) => a_out_en );
b_reg : component reg_multiple_out
generic map ( num_outputs => 1 )
port map ( d => reg_file_out2, q(1) => s2_bus,
latch_en => b_latch_en, out_en(1) => b_out_en );
temp_reg : component reg_multiple_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
latch_en => temp_latch_en,
out_en(1) => temp_out_en1, out_en(2) => temp_out_en2 );
iar_reg : component reg_multiple_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
latch_en => iar_latch_en,
out_en(1) => iar_out_en1, out_en(2) => iar_out_en2 );
pc_reg : component reg_multiple_plus_one_out_reset
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => pc_to_mem,
latch_en => pc_latch_en,
out_en(1) => pc_out_en1, out_en(2) => pc_out_en2,
reset => reset );
mar_reg : component reg_multiple_plus_one_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => mar_to_mem,
latch_en => mar_latch_en,
out_en(1) => mar_out_en1, out_en(2) => mar_out_en2 );
mem_addr_mux : component mux2
port map ( i0 => pc_to_mem, i1 => mar_to_mem, y => a,
sel => mem_addr_mux_sel );
mdr_reg : component reg_multiple_out
generic map ( num_outputs => 3 )
port map ( d => mdr_in, q(1) => s1_bus, q(2) => s2_bus, q(3) => d,
latch_en => mdr_latch_en,
out_en(1) => mdr_out_en1, out_en(2) => mdr_out_en2,
out_en(3) => mdr_out_en3 );
mdr_mux : component mux2
port map ( i0 => dest_bus, i1 => d, y => mdr_in,
sel => mdr_mux_sel );
instr_reg : component latch
port map ( d => d, q => current_instruction,
latch_en => ir_latch_en );
ir_extender1 : component ir_extender
port map ( d => current_instruction, q => s1_bus,
immed_size_26 => ir_immed1_size_26,
immed_unsigned => ir_immed1_unsigned,
immed_en => ir_immed1_en );
ir_extender2 : component ir_extender
port map ( d => current_instruction, q => s2_bus,
immed_size_26 => ir_immed2_size_26,
immed_unsigned => ir_immed2_unsigned,
immed_en => ir_immed2_en );
the_controller : component controller
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt,
width => width, write_enable => write_enable, mem_enable => mem_enable,
ifetch => ifetch, ready => ready,
alu_in_latch_en => alu_in_latch_en, alu_function => alu_function,
alu_zero => alu_zero, alu_negative => alu_negative,
alu_overflow => alu_overflow,
reg_s1_addr => reg_s1_addr, reg_s2_addr => reg_s2_addr,
reg_dest_addr => reg_dest_addr, reg_write => reg_write,
c_latch_en => c_latch_en,
a_latch_en => a_latch_en, a_out_en => a_out_en,
b_latch_en => b_latch_en, b_out_en => b_out_en,
temp_latch_en => temp_latch_en,
temp_out_en1 => temp_out_en1, temp_out_en2 => temp_out_en2,
iar_latch_en => iar_latch_en,
iar_out_en1 => iar_out_en1, iar_out_en2 => iar_out_en2,
pc_latch_en => pc_latch_en,
pc_out_en1 => pc_out_en1, pc_out_en2 => pc_out_en2,
mem_addr_mux_sel => mem_addr_mux_sel, mar_latch_en => mar_latch_en,
mar_out_en1 => mar_out_en1, mar_out_en2 => mar_out_en2,
mdr_mux_sel => mdr_mux_sel, mdr_latch_en => mdr_latch_en,
mdr_out_en1 => mdr_out_en1, mdr_out_en2 => mdr_out_en2,
mdr_out_en3 => mdr_out_en3,
ir_latch_en => ir_latch_en,
ir_immed1_size_26 => ir_immed1_size_26,
ir_immed2_size_26 => ir_immed2_size_26,
ir_immed1_unsigned => ir_immed1_unsigned,
ir_immed2_unsigned => ir_immed2_unsigned,
ir_immed1_en => ir_immed1_en, ir_immed2_en => ir_immed2_en,
current_instruction => current_instruction,
mem_addr => mar_to_mem(1 downto 0),
const1 => s1_bus, const2 => s2_bus );
end architecture rtl;
|
gpl-2.0
|
603701f8d10c0056582ac4dc37263c03
| 0.495067 | 3.546237 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2396.vhd
| 4 | 2,921 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2396.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p07n01i02396ent IS
END c07s03b02x00p07n01i02396ent;
ARCHITECTURE c07s03b02x00p07n01i02396arch OF c07s03b02x00p07n01i02396ent IS
BEGIN
TESTING: PROCESS
-- Declare ascending and descending ranges.
subtype BYTE is BIT_VECTOR( 0 to 7 );
-- Declare array variables of these types.
variable BYTEV : BYTE;
BEGIN
BYTEV := BYTE'( 7 => '0', 6 => '1', 4 => '1',
2 => '1', 0 => '1', 5 => '0',
3 => '0', 1 => '0' );
assert( BYTEV( 1 ) = '0' );
assert( BYTEV( 3 ) = '0' );
assert( BYTEV( 5 ) = '0' );
assert( BYTEV( 7 ) = '0' );
assert( BYTEV( 0 ) = '1' );
assert( BYTEV( 2 ) = '1' );
assert( BYTEV( 4 ) = '1' );
assert( BYTEV( 6 ) = '1' );
wait for 1 ns;
assert NOT( ( BYTEV( 1 ) = '0' ) and
( BYTEV( 3 ) = '0' ) and
( BYTEV( 5 ) = '0' ) and
( BYTEV( 7 ) = '0' ) and
( BYTEV( 0 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 6 ) = '1' ))
report "***PASSED TEST: c07s03b02x00p07n01i02396"
severity NOTE;
assert ( ( BYTEV( 1 ) = '0' ) and
( BYTEV( 3 ) = '0' ) and
( BYTEV( 5 ) = '0' ) and
( BYTEV( 7 ) = '0' ) and
( BYTEV( 0 ) = '1' ) and
( BYTEV( 2 ) = '1' ) and
( BYTEV( 4 ) = '1' ) and
( BYTEV( 6 ) = '1' ))
report "***FAILED TEST: c07s03b02x00p07n01i02396 - Named association should be able to appear in any order."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p07n01i02396arch;
|
gpl-2.0
|
94493637412c22607bdd641df35e2207
| 0.524478 | 3.481526 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr-b.vhd
| 4 | 6,755 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_srvr-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of server is
begin
service : process is
variable served_token : token_type;
variable release_time : time;
variable number_of_tokens_served : natural := 0;
variable service_time : natural; -- in time_unit
variable sum_of_service_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_service_times : real := 0.0; --in time_unit**2
variable random_info : random_info_record;
variable random_number : real;
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable measured_mean_service_time : real
:= sum_of_service_times / real(number_of_tokens_served);
variable measured_std_dev_of_service_times : real
:= sqrt ( ( sum_of_squares_of_service_times
- sum_of_service_times**2 / real(number_of_tokens_served) )
/ real( number_of_tokens_served - 1 ) );
begin
write(L, string'("Summary information for server "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Service distribution: "));
write(L, distribution_type'image(distribution));
write(L, string'(" with mean service time of "));
write(L, mean_service_time, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens served = "));
write(L, natural(number_of_tokens_served));
writeline(info_file, L);
write(L, string'(" Mean service time = "));
write(L, measured_mean_service_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of service times = "));
write(L, measured_std_dev_of_service_times * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Utilization = "));
write(L, sum_of_service_times / real(now / time_unit), digits => 4);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace_service is
begin
write(L, string'("Server "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" served "));
write(L, in_arc.token, time_unit);
writeline(info_file, L);
end procedure write_trace_service;
procedure write_trace_release is
begin
write(L, string'("Server "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" released "));
write(L, served_token, time_unit);
writeline(info_file, L);
end procedure write_trace_release;
begin
file_open(info_file, info_file_name, write_mode);
case distribution is
when fixed =>
init_fixed(random_info, real(mean_service_time / time_unit));
when uniform =>
init_uniform( random_info,
lower_bound => 0.0,
upper_bound => 2.0 * real(mean_service_time / time_unit),
seed => seed );
when exponential =>
init_exponential( random_info,
mean => real(mean_service_time / time_unit),
seed => seed );
end case;
in_ready <= true;
loop
wait on info_detail'transaction, in_arc;
if info_detail'active and info_detail = summary then
write_summary;
end if;
if in_arc'event then
in_ready <= false;
if info_detail = trace then
write_trace_service;
end if;
served_token := in_arc.token;
generate_random(random_info, random_number);
service_time := natural(random_number);
release_time := service_time * time_unit + now;
loop
wait on info_detail'transaction for release_time - now;
if info_detail'active and info_detail = summary then
write_summary;
end if;
exit when release_time = now;
end loop;
in_ready <= true;
out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
token => served_token );
number_of_tokens_served := number_of_tokens_served + 1;
sum_of_service_times := sum_of_service_times + real(service_time);
sum_of_squares_of_service_times := sum_of_squares_of_service_times
+ real(service_time) ** 2;
if info_detail = trace then
write_trace_release;
end if;
end if;
end loop;
end process service;
end architecture behavior;
|
gpl-2.0
|
5867897c303b74c97bb293e94b1d3c3b
| 0.502295 | 4.567275 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_06.vhd
| 4 | 1,417 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture fixed_length_series of cos is
begin
summation : process (theta) is
variable sum, term : real;
begin
sum := 1.0;
term := 1.0;
for n in 1 to 9 loop
term := (-term) * theta**2 / real(((2*n-1) * 2*n));
sum := sum + term;
end loop;
result <= sum;
end process summation;
end architecture fixed_length_series;
|
gpl-2.0
|
90a08d923234445ad309460af5eca1c1
| 0.60127 | 4.083573 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd
| 4 | 2,104 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_19a is
end entity inline_19a;
architecture test of inline_19a is
signal reset, trigger_n : std_ulogic;
terminal rc_ext : electrical;
quantity v_rc_ext across rc_ext;
constant half_vdd : voltage := 2.5;
begin
block_1 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
-- ...
if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
q <= '0'; q_n <= '1';
break;
elsif trigger_n = '0' or trigger_n = 'L' then
q <= '1'; q_n <= '0';
break;
end if;
-- ...
-- end code from book
wait;
end process;
end block block_1;
block_2 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
q_n <= '1' after 20 ns;
break;
-- end code from book
wait;
end process;
end block block_2;
block_3 : block is
signal q, q_n : std_ulogic;
begin
process is
begin
-- code from book
q_n <= '1';
break;
-- end code from book
wait;
end process;
end block block_3;
end architecture test;
|
gpl-2.0
|
bba2155d630f6e71aef86c5a5ab96c1a
| 0.615494 | 3.737123 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc313.vhd
| 4 | 1,881 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc313.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x01p01n02i00313ent IS
END c03s01b04x01p01n02i00313ent;
ARCHITECTURE c03s01b04x01p01n02i00313arch OF c03s01b04x01p01n02i00313ent IS
constant C1 : REAL := -1.0E38 ;
constant C2 : REAL := +1.0E38 ;
BEGIN
TESTING: PROCESS
variable k1 : real;
variable k2 : real;
BEGIN
k1 := C1;
k2 := C2;
assert NOT(k1=C1 and k2=C2)
report "***PASSED TEST: c03s01b04x01p01n02i00313"
severity NOTE;
assert (k1=C1 and k2=C2)
report "***FAILED TEST: c03s01b04x01p01n02i00313 - The range of REAL is host-independent, but it is guaranteed to include the range -1E38 to +1E38."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x01p01n02i00313arch;
|
gpl-2.0
|
bb5f7b84f1bcaabcf2483ce71e96e049
| 0.665603 | 3.496283 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd
| 4 | 1,795 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_std_logic_to_analog is
end tb_std_logic_to_analog;
architecture TB_std_logic2analog of tb_std_logic_to_analog is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical ;
signal ina : std_logic ;
begin
-- Signal assignments
-- Component instances
d2a1 : entity work.std_logic_to_analog(ideal)
port map(
d => ina, -- bit type pin
a => ana_out
);
clk1 : entity work.clock_duty(ideal)
generic map(
off_time => 2 ms,
on_time => 1 ms
)
port map(
CLOCK_OUT => ina -- std_logic type pin
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ana_out,
p2 => electrical_ref
);
end TB_std_logic2analog;
|
gpl-2.0
|
1c63f2aea4b5a045bf3415c1ede00e1c
| 0.649025 | 3.860215 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/negate.vhd
| 4 | 1,571 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity negate is
end entity negate;
architecture test of negate is
subtype word32 is bit_vector(31 downto 0);
-- code in book
procedure negate ( a : inout word32 ) is
variable carry_in : bit := '1';
variable carry_out : bit;
begin
a := not a;
for index in a'reverse_range loop
carry_out := a(index) and carry_in;
a(index) := a(index) xor carry_in;
carry_in := carry_out;
end loop;
end procedure negate;
-- end code in book
begin
stimulus : process is
-- code in book (in text)
variable op1 : word32;
-- . . .
-- end code in book
begin
op1 := X"0000_0002";
-- code in book (in text)
negate ( op1 );
-- end code in book
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
1946b81f50f4349640c9ede777defc17
| 0.672183 | 3.879012 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2104.vhd
| 4 | 2,135 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2104.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02104ent IS
END c07s02b04x00p20n01i02104ent;
ARCHITECTURE c07s02b04x00p20n01i02104arch OF c07s02b04x00p20n01i02104ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_8 is positive_v (1 to 8);
SUBTYPE positive_4 is positive_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : positive_8;
variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
variable r_operand : positive_4 := ( 89 , 89 , 1 , 1 );
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT(result = ( 1 , 89 , 1 , 89 , 89 , 89 , 1 , 1 ))
report "***PASSED TEST: c07s02b04x00p20n01i02104"
severity NOTE;
assert (result = ( 1 , 89 , 1 , 89 , 89 , 89 , 1 , 1 ))
report "***FAILED TEST: c07s02b04x00p20n01i02104 - Concatenation of two POSITIVE arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02104arch;
|
gpl-2.0
|
6734ac62a4db5ab16fd7adc86965aa24
| 0.645433 | 3.582215 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3010.vhd
| 4 | 1,984 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3010.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p07n01i03010pkg is
constant X1 : integer;
constant X2 : integer;
end c02s06b00x00p07n01i03010pkg;
package body c02s06b00x00p07n01i03010pkg is
constant X1: integer := 1;
constant X2: integer := X1;
end c02s06b00x00p07n01i03010pkg;
use work.c02s06b00x00p07n01i03010pkg.all;
ENTITY c02s06b00x00p07n01i03010ent IS
END c02s06b00x00p07n01i03010ent;
ARCHITECTURE c02s06b00x00p07n01i03010arch OF c02s06b00x00p07n01i03010ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(X1=1 and X2=1)
report "***PASSED TEST: c02s06b00x00p07n01i03010"
severity NOTE;
assert (X1=1 and X2=1)
report "***FAILED TEST: c02s06b00x00p07n01i03010 - Deferred constant declaration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p07n01i03010arch;
|
gpl-2.0
|
daba08352ef17e4b8a4cf9c4c06a54bf
| 0.696069 | 3.368421 | false | true | false | false |
stnolting/neo430
|
rtl/core/neo430_dmem.vhd
| 1 | 6,152 |
-- #################################################################################################
-- # << NEO430 - Data memory ("DMEM") >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_dmem is
generic (
DMEM_SIZE : natural := 2*1024 -- internal DMEM size in bytes
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic_vector(01 downto 0); -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_dmem;
architecture neo430_dmem_rtl of neo430_dmem is
-- local signals --
signal acc_en : std_ulogic;
signal rdata : std_ulogic_vector(15 downto 0);
signal rden : std_ulogic;
signal addr : integer;
-- RAM --
type dmem_file_t is array (0 to DMEM_SIZE/2-1) of std_ulogic_vector(7 downto 0);
signal dmem_file_l : dmem_file_t;
signal dmem_file_h : dmem_file_t;
-- RAM attribute to inhibit bypass-logic - Intel only! --
attribute ramstyle : string;
attribute ramstyle of dmem_file_l : signal is "no_rw_check";
attribute ramstyle of dmem_file_h : signal is "no_rw_check";
-- RAM attribute to inhibit bypass-logic - Lattice ICE40up only! --
attribute syn_ramstyle : string;
attribute syn_ramstyle of dmem_file_l : signal is "no_rw_check";
attribute syn_ramstyle of dmem_file_h : signal is "no_rw_check";
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i >= dmem_base_c) and (addr_i < std_ulogic_vector(unsigned(dmem_base_c) + DMEM_SIZE)) else '0';
addr <= to_integer(unsigned(addr_i(index_size_f(DMEM_SIZE/2) downto 1))); -- word aligned
-- Memory Access ------------------------------------------------------------
-- -----------------------------------------------------------------------------
dmem_file_access: process(clk_i)
begin
-- check max size --
if (DMEM_SIZE > dmem_max_size_c) then
assert false report "D-mem size out of range! Max 12kB!" severity error;
end if;
if rising_edge(clk_i) then
rden <= rden_i and acc_en;
if (acc_en = '1') then -- reduce switching activity when not accessed
if (wren_i(0) = '1') then -- write low byte
dmem_file_l(addr) <= data_i(07 downto 0);
end if;
rdata(07 downto 0) <= dmem_file_l(addr);
if (wren_i(1) = '1') then -- write high byte
dmem_file_h(addr) <= data_i(15 downto 8);
end if;
rdata(15 downto 8) <= dmem_file_h(addr);
end if;
end if;
end process dmem_file_access;
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
end neo430_dmem_rtl;
|
bsd-3-clause
|
11db9bf45350a261d2f8e9a6e7e0efb1
| 0.472692 | 4.836478 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1995.vhd
| 4 | 1,922 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1995.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n01i01995ent IS
END c07s02b02x00p07n01i01995ent;
ARCHITECTURE c07s02b02x00p07n01i01995arch OF c07s02b02x00p07n01i01995ent IS
BEGIN
TESTING: PROCESS
type PHYS is range 1 to 260
units
A;
B = 10 A;
C = 10 B;
end units;
variable k : integer := 0;
variable m : PHYS := 10 A;
BEGIN
if (m /= 2 B) then
k := 5;
else
k := 3;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n01i01995"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n01i01995 - Inequality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i01995arch;
|
gpl-2.0
|
5899741b5c5303e77d8768cb3fd631a7
| 0.638918 | 3.626415 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd
| 4 | 1,495 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY ball_wa IS
END ENTITY ball_wa;
ARCHITECTURE simple OF ball_wa IS
QUANTITY v: real;
QUANTITY s: real;
CONSTANT G: real := 9.81;
CONSTANT Air_Res: real := 0.1;
SIGNAL damping: real := -0.7;
signal v_at_impact : real:= 0.0;
signal impact: boolean;
BEGIN
if domain = quiescent_domain use
v == 0.0;
s == 30.0;
elsif impact use
v == damping*v_at_impact;
s == 0.0;
else
s'dot == v;
v'dot == -G;
end use;
process begin
wait until not s'above(0.0);
if v < -1.0e-9 then
v_at_impact <= v;
impact <= true, false after 1 us;
else
damping <= 0.0;
impact <= true;
end if;
end process;
break on impact;
END architecture simple;
|
gpl-2.0
|
62c0131abe6f15ed49366a3c0ed79536
| 0.674916 | 3.285714 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2011.vhd
| 4 | 2,521 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2011.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02011ent IS
END c07s02b02x00p10n01i02011ent;
ARCHITECTURE c07s02b02x00p10n01i02011arch OF c07s02b02x00p10n01i02011ent IS
TYPE int_vector is array (integer range <>) of INTEGER;
SUBTYPE int_8 is int_vector(0 to 7);
SUBTYPE int_4 is int_vector(0 to 3);
BEGIN
TESTING: PROCESS
CONSTANT slice_8a : int_8 := (1,2,3,4,5,6,7,8);
VARIABLE slice_8b : int_8 := (1,2,3,4,5,6,7,8);
VARIABLE target_1 : boolean;
VARIABLE target_2 : boolean;
VARIABLE target_3 : boolean;
VARIABLE target_4 : boolean;
BEGIN
target_1 := slice_8a (3 to 3) < slice_8b (6 to 6);
target_2 := slice_8a (3 to 3) <= slice_8b (7 to 7);
target_3 := slice_8a (3 to 3) > slice_8b (2 to 2);
target_4 := slice_8a (3 to 3) >= slice_8b (1 to 1);
wait for 5 ns;
assert NOT( target_1 and
target_2 and
target_3 and
target_4 )
report "***PASSED TEST: c07s02b02x00p10n01i02011"
severity NOTE;
assert ( target_1 and
target_2 and
target_3 and
target_4 )
report "***FAILED TEST: c07s02b02x00p10n01i02011 - Ordering operators are loperable over the set of relational operations."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02011arch;
|
gpl-2.0
|
3ff127cf8073e0faa37d7532b093809a
| 0.625942 | 3.472452 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/textio.vhd
| 4 | 3,529 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package textio is
type line is access string;
type text is file of string;
type side is (right, left);
subtype width is natural;
file input : text open read_mode is "std_input";
file output : text open write_mode is "std_output";
-- use this declaration for VHDL-2001
procedure readline(file f: text; l: inout line);
-- use this declaration for VHDL-AMS
procedure readline(file f: text; l: out line);
procedure read ( L : inout line; value: out bit; good : out boolean );
procedure read ( L : inout line; value: out bit );
procedure read ( L : inout line; value: out bit_vector; good : out boolean );
procedure read ( L : inout line; value: out bit_vector );
procedure read ( L : inout line; value: out boolean; good : out boolean );
procedure read ( L : inout line; value: out boolean );
procedure read ( L : inout line; value: out character; good : out boolean );
procedure read ( L : inout line; value: out character );
procedure read ( L : inout line; value: out integer; good : out boolean );
procedure read ( L : inout line; value: out integer );
procedure read ( L : inout line; value: out real; good : out boolean );
procedure read ( L : inout line; value: out real );
procedure read ( L : inout line; value: out string; good : out boolean );
procedure read ( L : inout line; value: out string );
procedure read ( L : inout line; value: out time; good : out boolean );
procedure read ( L : inout line; value: out time );
procedure writeline ( file f : text; L : inout line );
procedure write ( L : inout line; value : in bit;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in bit_vector;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in boolean;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in character;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in integer;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0 );
procedure write ( L : inout line; value : in string;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in time;
justified: in side := right; field: in width := 0;
unit: in time := ns );
end package textio;
|
gpl-2.0
|
a7e6bf3b8e66c74d8594a5e35753a82e
| 0.634174 | 4.033143 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_pk_test.vhd
| 4 | 2,111 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_pk_test.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package stimulus_generators is
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length );
end package stimulus_generators;
package body stimulus_generators is
type digit_table is array ( natural range 0 to 1 ) of bit;
constant digit : digit_table := ( '0', '1' );
function natural_to_bv ( nat : in natural;
length : in natural ) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(0 to length - 1);
begin
for index in result'reverse_range loop
result(index) := digit( temp rem 2 );
temp := temp / 2;
end loop;
return result;
end function natural_to_bv;
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length ) is
begin
bv <= natural_to_bv(0, bv'length);
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= natural_to_bv(value, bv'length);
end loop;
end procedure all_possible_values;
end package body stimulus_generators;
|
gpl-2.0
|
f8efe03961103ac644fdfea81d229578
| 0.639507 | 4.036329 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_05.vhd
| 4 | 2,034 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_17_05 is
end entity fg_17_05;
----------------------------------------------------------------
architecture test of fg_17_05 is
signal s : bit_vector(0 to 3);
begin
process is
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : bit_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list, current_cell : value_ptr;
begin
value_list := new value_cell'( B"1000", value_list );
value_list := new value_cell'( B"0010", value_list );
value_list := new value_cell'( B"0000", value_list );
-- code from book:
current_cell := value_list;
while current_cell /= null loop
s <= current_cell.value;
wait for 10 ns;
current_cell := current_cell.next_cell;
end loop;
-- end of code from book
wait;
end process;
end architecture test;
|
gpl-2.0
|
c8cd3810411581088e580dd890e51637
| 0.570305 | 4.185185 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/sr2676/reset-test.vhdl
| 3 | 1,984 |
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.reset_types.all;
entity reset_testbench is
end reset_testbench;
architecture behavior of reset_testbench is
component power_on_reset
port (
clk: in std_logic;
reset: in std_logic;
core_en: out std_logic;
sys_clken: out std_logic;
cfg_drv: out std_logic;
rd_pmbrd_rev : out std_logic;
clk_33mhz_en: out std_logic;
cur_state: out reset_state
);
end component;
--for por_0: power_on_reset use entity work.power_on_reset;
signal clk: std_logic;
signal reset: std_logic;
signal core_en: std_logic;
signal sys_clken: std_logic;
signal cfg_drv: std_logic;
signal rd_pmbrd_rev: std_logic;
signal clk_33mhz_en: std_logic;
signal current_state: reset_state;
constant CLK50MHZ_period: time := 20 ns;
constant CLK33_period: time := 33 ns;
constant LB_LCLK0_period: time := 16 ns;
begin
por_0: power_on_reset port map (
clk => clk,
reset => reset,
core_en => core_en,
sys_clken => sys_clken,
cfg_drv => cfg_drv,
rd_pmbrd_rev => rd_pmbrd_rev,
clk_33mhz_en => clk_33mhz_en,
cur_state => current_state
);
CLK50MHZ_process :process
begin
clk <= '0';
wait for CLK50MHZ_period/2;
clk <= '1';
wait for CLK50MHZ_period/2;
end process;
stim: process
variable l: line;
begin
report "asserting reset" severity note;
reset <= '1';
report "current_state is " & reset_state'image(current_state);
wait until current_state = reset_state'value("RST");
report "saw state RST" severity note;
wait for CLK50MHZ_period * 3;
report "de-asserting reset" severity note;
reset <= '0';
wait until core_en = '1';
report "saw core_en" severity note;
-- personality module id
wait until rd_pmbrd_rev = '1';
report "saw rd_pmbrd_rev assert" severity note;
wait until rd_pmbrd_rev = '0';
report "saw rd_pmbrd_rev de-assert" severity note;
wait for CLK50MHZ_period * 100;
report "end of test" severity note;
wait;
end process;
end behavior;
|
gpl-2.0
|
b0275790ca1f3b6c03fd6eb2b34b494c
| 0.696069 | 2.798307 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.b-tbDataPath.vhd
| 1 | 2,880 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
entity tbDataPath is
end tbDataPath;
architecture tb_data_path_arch of tbDataPath is
constant ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
constant DATA_SIZE : integer := C_SYS_DATA_SIZE;
constant ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
constant OPCD_SIZE : integer := C_SYS_OPCD_SIZE;
constant IMME_SIZE : integer := C_SYS_IMME_SIZE;
constant CWRD_SIZE : integer := C_SYS_CWRD_SIZE;
constant CALU_SIZE : integer := C_CTR_CALU_SIZE;
constant DRCW_SIZE : integer := C_CTR_DRCW_SIZE;
component DataPath is
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
OPCD_SIZE : integer := C_SYS_OPCD_SIZE;
IMME_SIZE : integer := C_SYS_IMME_SIZE;
CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Datapath Contrl Word
CALU_SIZE : integer := C_CTR_CALU_SIZE;
DRCW_SIZE : integer := C_CTR_DRCW_SIZE
);
port (
clk : in std_logic;
rst : in std_logic;
istr_addr : out std_logic_vector(ADDR_SIZE-1 downto 0);
istr_val : in std_logic_vector(ISTR_SIZE-1 downto 0);
ir_out : out std_logic_vector(ISTR_SIZE-1 downto 0);
reg_a_out : out std_logic_vector(DATA_SIZE-1 downto 0);
data_addr : out std_logic_vector(ADDR_SIZE-1 downto 0);
data_i_val : in std_logic_vector(DATA_SIZE-1 downto 0);
data_o_val : out std_logic_vector(DATA_SIZE-1 downto 0);
cw : in std_logic_vector(CWRD_SIZE-1 downto 0);
dr_cw : out std_logic_vector(DRCW_SIZE-1 downto 0);
calu : in std_logic_vector(CALU_SIZE-1 downto 0)
);
end component;
signal clk : std_logic := '0';
signal rst : std_logic;
signal istr_addr : std_logic_vector(ADDR_SIZE-1 downto 0);
signal istr_val : std_logic_vector(ISTR_SIZE-1 downto 0);
signal ir_out : std_logic_vector(ISTR_SIZE-1 downto 0);
signal reg_a_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal data_addr : std_logic_vector(ADDR_SIZE-1 downto 0);
signal data_i_val : std_logic_vector(DATA_SIZE-1 downto 0);
signal data_o_val : std_logic_vector(DATA_SIZE-1 downto 0);
signal cw : std_logic_vector(CWRD_SIZE-1 downto 0);
signal dr_cw : std_logic_vector(DRCW_SIZE-1 downto 0);
signal calu : std_logic_vector(CALU_SIZE-1 downto 0);
begin
DP: DataPath
port map(clk,rst,istr_addr,istr_val,ir_out,reg_a_out,data_addr,data_i_val,data_o_val,cw,dr_cw,calu);
CLK0: process(clk)
begin
clk <= not (clk) after 0.5 ns;
end process;
rst <= '0', '1' after 1 ns;
istr_val <= x"20410001", x"20420002" after 2 ns, x"20430003" after 3 ns, x"20440004" after 4 ns;
data_i_val <= x"00000000";
cw <= "1010101000011";
calu <= "00000";
end tb_data_path_arch;
configuration tb_data_path_cfg of tbDataPath is
for tb_data_path_arch
end for;
end tb_data_path_cfg;
|
mit
|
c1ad6cfd8947daf0994ae78416594893
| 0.676389 | 2.651934 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug02/repro3.vhdl
| 3 | 844 |
entity repro3 is
end repro3;
package repro3_pkg is
procedure inc (a : inout integer);
type prot is protected
procedure get (a : integer);
end protected prot;
end repro3_pkg;
package body repro3_pkg is
procedure inc (a : inout integer) is
begin
a := a + 1;
end inc;
procedure inc (a : inout time) is
begin
a := a + 1 ns;
end inc;
type prot is protected body
variable v : integer;
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
procedure get (a : integer) is
begin
v := a;
end get;
end protected body prot;
end repro3_pkg;
use work.repro3_pkg.all;
architecture behav of repro3 is
begin -- behav
process
variable a : integer := 2;
begin
inc (a);
assert a = 3 report "bad value of a";
wait;
end process;
end behav;
|
gpl-2.0
|
00e1608dc0235c4b8c29c3abc27b30e3
| 0.629147 | 3.487603 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_BuckConverter.vhd
| 4 | 1,909 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity tb_BuckConverter is
port ( ctrl : std_logic );
end tb_BuckConverter;
----------------------------------------------------------------
architecture tb_BuckConverter of tb_BuckConverter is
terminal vin : electrical;
terminal vmid : electrical;
terminal vout : electrical;
begin
L1 : entity work.inductor(ideal)
generic map ( ind => 6.5e-3 )
port map ( p1 => vmid, p2 => vout );
C1 : entity work.capacitor(ideal)
generic map ( cap => 1.5e-6 )
port map ( p1 => vout, p2 => electrical_ref );
VinDC : entity work.v_constant(ideal)
generic map ( level => 42.0 )
port map ( pos => vin, neg => electrical_ref );
RLoad : entity work.resistor(ideal)
generic map ( res => 2.4 )
port map ( p1 => vout, p2 => electrical_ref );
D1 : entity work.diode(ideal)
port map ( p => electrical_ref, n => vmid );
sw1 : entity work.switch_dig(ideal)
port map ( sw_state => ctrl, p2 => vmid, p1 => vin );
end architecture tb_BuckConverter;
|
gpl-2.0
|
bfec3f481a668e7a8899756486f6c62a
| 0.662127 | 3.841046 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1909.vhd
| 4 | 1,916 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1909.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p09n03i01909ent IS
END c07s02b00x00p09n03i01909ent;
ARCHITECTURE c07s02b00x00p09n03i01909arch OF c07s02b00x00p09n03i01909ent IS
signal Q : BIT := '1';
signal R : BIT := '0';
signal S : BIT := '1';
signal PP,P2 : BIT := '1' ;
signal R1 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
R1 <= ((Q and S) or R) and (P2 and PP) ;
wait for 5 ns;
assert NOT( R1 = '1' )
report "***PASSED TEST: c07s02b00x00p09n03i01909"
severity NOTE;
assert ( R1 = '1' )
report "***FAILED TEST: c07s02b00x00p09n03i01909 - The parentheses can be used to control the association of operators and operands."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p09n03i01909arch;
|
gpl-2.0
|
ec5b0af1435d0eb5237bfeedeb3a9c45
| 0.649269 | 3.528545 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc471.vhd
| 4 | 4,000 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc471.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00471ent IS
END c03s02b01x01p19n01i00471ent;
ARCHITECTURE c03s02b01x01p19n01i00471arch OF c03s02b01x01p19n01i00471ent IS
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (integer range <>) of record_std_package;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C66: array_rec_std(0 to 7) := (others => C50) ;
function complex_scalar(s : array_rec_std(0 to 7)) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_std is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_std(0 to 7);
signal S2 : array_rec_std(0 to 7);
signal S3 : array_rec_std(0 to 7):= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00471"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00471 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00471arch;
|
gpl-2.0
|
63929ad40b92ab16bc352a694b6ce188
| 0.5955 | 3.686636 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl.vhd
| 4 | 1,561 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity sw_LoopCtrl is
generic ( r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
sw_state : integer range 1 to 2 := 1 );
port ( terminal c, p1, p2 : electrical );
end entity sw_LoopCtrl;
----------------------------------------------------------------
architecture ideal of sw_LoopCtrl is
quantity v1 across i1 through c to p1;
quantity v2 across i2 through c to p2;
quantity r1, r2 : resistance;
begin
sw1 : if sw_state = 1 generate
r1 == r_closed;
r2 == r_open;
end generate sw1;
sw2 : if sw_state = 2 generate
r1 == r_open;
r2 == r_closed;
end generate sw2;
v1 == r1 * i1;
v2 == r2 * i2;
end architecture ideal;
|
gpl-2.0
|
603ce05c9163f27269dac7c7a63b716b
| 0.661115 | 3.743405 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_22.vhd
| 4 | 4,071 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity cache is
end entity cache;
-- end not in book
architecture behavioral of cache is
-- not in book
subtype word is bit_vector(0 to 31);
signal mem_addr : natural;
signal mem_data_in : word;
signal mem_read, mem_ack : bit := '0';
-- end not in book
begin
behavior : process is
-- not in book
constant block_size : positive := 4;
type cache_block is array (0 to block_size - 1) of word;
type store_array is array (0 to 15) of cache_block;
variable data_store : store_array;
variable entry_index : natural := 1;
variable miss_base_address : natural := 16;
-- end not in book
-- . . .
procedure read_block( start_address : natural;
entry : out cache_block ) is
variable memory_address_reg : natural;
variable memory_data_reg : word;
procedure read_memory_word is
begin
mem_addr <= memory_address_reg;
mem_read <= '1';
wait until mem_ack = '1';
memory_data_reg := mem_data_in;
mem_read <= '0';
wait until mem_ack = '0';
end procedure read_memory_word;
begin -- read_block
for offset in 0 to block_size - 1 loop
memory_address_reg := start_address + offset;
read_memory_word;
entry(offset) := memory_data_reg;
end loop;
end procedure read_block;
begin -- behavior
-- . . .
read_block( miss_base_address, data_store(entry_index) );
-- . . .
-- not in book
wait;
-- end not in book
end process behavior;
-- not in book
memory : process is
type store_array is array (0 to 31) of word;
constant store : store_array :=
( X"00000000", X"00000001", X"00000002", X"00000003",
X"00000004", X"00000005", X"00000006", X"00000007",
X"00000008", X"00000009", X"0000000a", X"0000000b",
X"0000000c", X"0000000d", X"0000000e", X"0000000f",
X"00000010", X"00000011", X"00000012", X"00000013",
X"00000014", X"00000015", X"00000016", X"00000017",
X"00000018", X"00000019", X"0000001a", X"0000001b",
X"0000001c", X"0000001d", X"0000001e", X"0000001f" );
begin
wait until mem_read = '1';
mem_data_in <= store(mem_addr);
mem_ack <= '1';
wait until mem_read = '0';
mem_ack <= '0';
end process memory;
-- end not in book
end architecture behavioral;
|
gpl-2.0
|
593d4d3d4d42afde3f0f872d06231614
| 0.505281 | 4.458927 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2968.vhd
| 4 | 2,154 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2968.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n02i02968ent IS
END c02s03b01x00p02n02i02968ent;
ARCHITECTURE c02s03b01x00p02n02i02968arch OF c02s03b01x00p02n02i02968ent IS
type newt is (one,two,three,four);
function "abs" (constant c1 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of right operator"
severity failure;
assert NOT( c1=10 )
report "***PASSED TEST: c02s03b01x00p02n02i02968"
severity NOTE;
assert ( c1=10 )
report "***FAILED TEST: c02s03b01x00p02n02i02968 - Error in association of operands."
severity ERROR;
return three;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
wait for 5 ns;
n1 := two;
assert (n1=two)
report "Error in initial conditions detected"
severity failure;
n1:= abs 10;
assert (n1=three)
report "Error in call to operloaded operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n02i02968arch;
|
gpl-2.0
|
5814f54bc4b27ad455920b411d69ff2f
| 0.665274 | 3.688356 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd
| 4 | 30,719 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
-- w2 == w1*ratio;
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- library IEEE;
-- use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang > ang_max use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang > ang_min use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : clock.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Digital clock with 50% duty cycle
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clock is
generic (
period : time); -- Clock period
port (
clk_out : out std_logic);
end entity clock;
architecture ideal of clock is
begin
CreateClock: process
begin
clk_out <= '0';
wait for period/2;
clk_out <= '1';
wait for period/2;
end process CreateClock;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Z-domain Lead Lag Filter
--
-- Z-Domain Transfer Function:
--
-- Y(z) a0(z) - a1(z-1)
-- ---- = k * ---------------
-- X(z) b0(z) - b1(z-1)
--
-- Normalizing Gain = k
--
-- Difference Equation:
--
-- Y(K) = AX(k) - BX(k-1) + CY(k-1)
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity lead_lag_diff is
port (
signal clk : in std_logic; -- clock
terminal input: electrical;
terminal output: electrical);
end entity lead_lag_diff;
architecture bhv of lead_lag_diff is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
CONSTANT k : real := 400.0; -- Normalize gain
signal z_out : real := 0.0;
begin
proc : process (clk)
variable zi_dly1 : real := 0.0; -- Input delayed 1 clk cycle
variable zo_dly1 : real := 0.0; -- Output delayed 1 clk cycle
variable z_new : real := 0.0; -- New output value this clk cycle
begin -- proc
zo_dly1 := z_out; -- Store previous output value
z_new := 0.6163507*vin - 0.6144184*zi_dly1 + 0.2307692*zo_dly1;
zi_dly1 := vin; -- Store previous input value
z_out <= z_new;
end process;
vout == k*z_out'ramp(100.0e-9); -- Ensure continuous transitions on output
end bhv;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo_z is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo_z;
architecture rudder_servo_z of rudder_servo_z is
-- Component declarations
-- Signal declarations
signal clk : std_logic;
terminal error : electrical;
terminal limit_in : electrical;
terminal ll_in : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
XCMP21 : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => limit_in,
output => servo_out
);
clock1 : entity work.clock(ideal)
generic map(
period => 200us
)
port map(
CLK_OUT => clk
);
XCMP23 : entity work.lead_lag_diff(bhv)
port map(
input => ll_in,
output => limit_in,
clk => clk
);
end rudder_servo_z;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_sine.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/03
-------------------------------------------------------------------------------
-- Description: Electrical sinusoidal voltage source
-- Includes frequency domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/03 1.1 Mentor Graphics Changed generics from real to
-- voltage.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity v_sine is
generic (
freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_sine;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS2_Z_Domain_Diff is
end TB_CS2_Z_Domain_Diff;
architecture TB_CS2_Z_Domain_Diff of TB_CS2_Z_Domain_Diff is
-- Component declarations
-- Signal declarations
terminal ctl_horn_in : rotational;
terminal fb_rot2v : electrical;
terminal gear_in : rotational_v;
terminal link_in : translational;
terminal link_out : translational;
terminal mot_in : electrical;
terminal rudder : rotational;
terminal src_in : electrical;
begin
-- Signal assignments
-- Component instances
gear1 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => gear_in,
rot2 => ctl_horn_in
);
gain_fb : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => fb_rot2v,
input => ctl_horn_in
);
gear_horn : entity work.horn_r2t(bhv)
port map(
theta => ctl_horn_in,
pos => link_in
);
rudder_horn : entity work.horn_t2r(bhv)
port map(
theta => rudder,
pos => link_out
);
motor1 : entity work.DC_Motor(basic)
generic map(
r_wind => 2.2,
kt => 3.43e-3,
l => 2.03e-3,
d => 5.63e-6,
j => 168.0e-9
)
port map(
p1 => mot_in,
p2 => ELECTRICAL_REF,
shaft_rotv => gear_in
);
stop1 : entity work.stop_r(ideal)
generic map(
damp_stop => 1.0e2,
k_stop => 1.0e6,
ang_max => 1.05,
ang_min => -1.05
)
port map(
ang1 => ctl_horn_in,
ang2 => ROTATIONAL_REF
);
\Linkage\ : entity work.tran_linkage(a1)
port map(
p2 => link_out,
p1 => link_in
);
XCMP5 : entity work.rudder(bhv)
generic map(
k => 0.2
)
port map(
rot => rudder
);
rudder_servo_z1 : entity work.rudder_servo_z
port map(
servo_out => mot_in,
servo_in => src_in,
pos_fb => fb_rot2v
);
v3 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 4.8
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
end TB_CS2_Z_Domain_Diff;
--
|
gpl-2.0
|
71259a417ef699658b1266dc9925ed46
| 0.571991 | 4.413649 | false | false | false | false |
123gmax/Digital-Lab
|
Lab1/Alex/counter/tb_counter_4_bit.vhd
| 1 | 2,616 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/01/2015 11:33:30 AM
-- Design Name:
-- Module Name: tb_counter_4_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_counter_4_bit is
end tb_counter_4_bit;
architecture Behavioral of tb_counter_4_bit is
signal CLK, direction, auto, tick, load : STD_LOGIC := '0';
signal load_input, output : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
component counter_4_bit is
Port( CLK : in STD_LOGIC;
direction : in STD_LOGIC;
auto : in STD_LOGIC;
tick : in STD_LOGIC;
load : in STD_LOGIC;
load_input : in STD_LOGIC_VECTOR(3 downto 0);
output : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
constant clk_period : time := 2ns;
begin
clk_process: process
begin
CLK <= NOT CLK;
wait for clk_period/2;
end process;
uut: counter_4_bit PORT MAP(
CLK => CLK,
direction => direction,
auto => auto,
tick => tick,
load => load,
load_input => load_input,
output => output
);
stimulus_process: process
begin
auto <= '1';
direction <= '1';
wait for 40ns;
direction <= '0';
wait for 34ns;
auto <= '0';
direction <= '1';
wait for 1ns;
for i in 0 to 3 loop
tick <= '1';
wait for 1ns;
tick <= '0';
wait for 1ns;
end loop;
direction <= '0';
wait for 1ns;
for i in 0 to 5 loop
tick <= '1';
wait for 1ns;
tick <= '0';
wait for 1ns;
end loop;
auto <= '1';
wait for 30ns;
load_input <= "0101";
load <='1';
wait for 1ns;
load <= '0';
wait;
end process;
end Behavioral;
|
gpl-2.0
|
1a382a3a2f26d15fa62be09e0c4be661
| 0.48815 | 4.074766 | false | false | false | false |
stnolting/neo430
|
rtl/top_templates/neo430_top_std_logic.vhd
| 1 | 12,974 |
-- #################################################################################################
-- # << NEO430 - Processor Top Entity using resolved signal types (std_logic) only >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_top_std_logic is
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := false; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
FREQ_GEN_USE : boolean := true; -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- global control --
clk_i : in std_logic; -- global clock, rising edge
rst_i : in std_logic; -- global reset, async, low-active
-- gpio --
gpio_o : out std_logic_vector(15 downto 0); -- parallel output
gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_logic_vector(03 downto 0); -- pwm channels
-- arbitrary frequency generator --
freq_gen_o : out std_logic_vector(02 downto 0); -- programmable frequency output
-- serial com --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic; -- UART receive data
spi_sclk_o : out std_logic; -- serial clock line
spi_mosi_o : out std_logic; -- serial data line out
spi_miso_i : in std_logic; -- serial data line in
spi_cs_o : out std_logic_vector(05 downto 0); -- SPI CS
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_dat_i : in std_logic_vector(31 downto 0); -- read data
wb_dat_o : out std_logic_vector(31 downto 0); -- write data
wb_we_o : out std_logic; -- read/write
wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_logic; -- strobe
wb_cyc_o : out std_logic; -- valid cycle
wb_ack_i : in std_logic; -- transfer acknowledge
-- external interrupts --
ext_irq_i : in std_logic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_logic_vector(07 downto 0) -- external interrupt request acknowledges
);
end neo430_top_std_logic;
architecture neo430_top_std_logic_rtl of neo430_top_std_logic is
-- other signals for conversion --
constant usrcode_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(USER_CODE);
signal clk_i_int : std_ulogic;
signal rst_i_int : std_ulogic;
signal gpio_o_int : std_ulogic_vector(15 downto 0);
signal gpio_i_int : std_ulogic_vector(15 downto 0);
signal pwm_o_int : std_ulogic_vector(03 downto 0);
signal uart_txd_o_int : std_ulogic;
signal uart_rxd_i_int : std_ulogic;
signal spi_sclk_o_int : std_ulogic;
signal spi_mosi_o_int : std_ulogic;
signal spi_miso_i_int : std_ulogic;
signal spi_cs_o_int : std_ulogic_vector(05 downto 0);
signal irq_i_int : std_ulogic_vector(07 downto 0);
signal irq_ack_o_int : std_ulogic_vector(07 downto 0);
signal wb_adr_o_int : std_ulogic_vector(31 downto 0);
signal wb_dat_i_int : std_ulogic_vector(31 downto 0);
signal wb_dat_o_int : std_ulogic_vector(31 downto 0);
signal wb_we_o_int : std_ulogic;
signal wb_sel_o_int : std_ulogic_vector(03 downto 0);
signal wb_stb_o_int : std_ulogic;
signal wb_cyc_o_int : std_ulogic;
signal wb_ack_i_int : std_ulogic;
signal freq_gen_o_int : std_ulogic_vector(02 downto 0);
begin
-- CPU ----------------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_top_inst: neo430_top
generic map (
-- general configuration --
CLOCK_SPEED => CLOCK_SPEED, -- main clock in Hz
IMEM_SIZE => IMEM_SIZE, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => DMEM_SIZE, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => usrcode_c, -- custom user code
-- module configuration --
MULDIV_USE => MULDIV_USE, -- implement multiplier/divider unit? (default=true)
WB32_USE => WB32_USE, -- implement WB32 unit? (default=true)
WDT_USE => WDT_USE, -- implement WDT? (default=true)
GPIO_USE => GPIO_USE, -- implement GPIO unit? (default=true)
TIMER_USE => TIMER_USE, -- implement timer? (default=true)
UART_USE => UART_USE, -- implement UART? (default=true)
CRC_USE => CRC_USE, -- implement CRC unit? (default=true)
CFU_USE => CFU_USE, -- implement CF unit? (default=false)
PWM_USE => PWM_USE, -- implement PWM controller? (default=true)
TWI_USE => TWI_USE, -- implement two wire serial interface? (default=true)
SPI_USE => SPI_USE, -- implement SPI? (default=true)
TRNG_USE => TRNG_USE, -- implement TRNG? (default=false)
EXIRQ_USE => EXIRQ_USE, -- implement EXIRQ? (default=true)
FREQ_GEN_USE => FREQ_GEN_USE, -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => clk_i_int, -- global clock, rising edge
rst_i => rst_i_int, -- global reset, async, low-active
-- parallel io --
gpio_o => gpio_o_int, -- parallel output
gpio_i => gpio_i_int, -- parallel input
-- pwm channels --
pwm_o => pwm_o_int, -- pwm channels
-- arbitrary frequency generator --
freq_gen_o => freq_gen_o_int, -- programmable frequency output
-- serial com --
uart_txd_o => uart_txd_o_int, -- UART send data
uart_rxd_i => uart_rxd_i_int, -- UART receive data
spi_sclk_o => spi_sclk_o_int, -- serial clock line
spi_mosi_o => spi_mosi_o_int, -- serial data line out
spi_miso_i => spi_miso_i_int, -- serial data line in
spi_cs_o => spi_cs_o_int, -- SPI CS 0..7
twi_sda_io => twi_sda_io, -- twi serial data line
twi_scl_io => twi_scl_io, -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o => wb_adr_o_int, -- address
wb_dat_i => wb_dat_i_int, -- read data
wb_dat_o => wb_dat_o_int, -- write data
wb_we_o => wb_we_o_int, -- read/write
wb_sel_o => wb_sel_o_int, -- byte enable
wb_stb_o => wb_stb_o_int, -- strobe
wb_cyc_o => wb_cyc_o_int, -- valid cycle
wb_ack_i => wb_ack_i_int, -- transfer acknowledge
-- interrupts --
ext_irq_i => irq_i_int, -- external interrupt request line
ext_ack_o => irq_ack_o_int -- external interrupt request acknowledge
);
-- Type Conversion ----------------------------------------------------------
-- -----------------------------------------------------------------------------
clk_i_int <= std_ulogic(clk_i);
rst_i_int <= std_ulogic(rst_i);
gpio_i_int <= std_ulogic_vector(gpio_i);
uart_rxd_i_int <= std_ulogic(uart_rxd_i);
spi_miso_i_int <= std_ulogic(spi_miso_i);
wb_dat_i_int <= std_ulogic_vector(wb_dat_i);
wb_ack_i_int <= std_ulogic(wb_ack_i);
irq_i_int <= std_ulogic_vector(ext_irq_i);
gpio_o <= std_logic_vector(gpio_o_int);
pwm_o <= std_logic_vector(pwm_o_int);
uart_txd_o <= std_logic(uart_txd_o_int);
spi_sclk_o <= std_logic(spi_sclk_o_int);
spi_mosi_o <= std_logic(spi_mosi_o_int);
spi_cs_o <= std_logic_vector(spi_cs_o_int);
wb_adr_o <= std_logic_vector(wb_adr_o_int);
wb_dat_o <= std_logic_vector(wb_dat_o_int);
wb_we_o <= std_logic(wb_we_o_int);
wb_sel_o <= std_logic_vector(wb_sel_o_int);
wb_stb_o <= std_logic(wb_stb_o_int);
wb_cyc_o <= std_logic(wb_cyc_o_int);
ext_ack_o <= std_logic_vector(irq_ack_o_int);
freq_gen_o <= std_logic_vector(freq_gen_o_int);
end neo430_top_std_logic_rtl;
|
bsd-3-clause
|
f42cce6b9c9c59c228176f3f2e50c1e5
| 0.53245 | 3.819252 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1370.vhd
| 4 | 6,565 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1370.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01370ent IS
END c08s05b00x00p03n01i01370ent;
ARCHITECTURE c08s05b00x00p03n01i01370arch OF c08s05b00x00p03n01i01370ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
--
BEGIN
v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***PASSED TEST: c08s05b00x00p03n01i01370"
severity NOTE;
assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
report "***FAILED TEST: c08s05b00x00p03n01i01370 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01370arch;
|
gpl-2.0
|
ac244f00e0f523f6e182a01bf1f5bdf2
| 0.583549 | 2.933423 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_02.vhd
| 4 | 1,606 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_02 is
end entity inline_02;
----------------------------------------------------------------
architecture test of inline_02 is
signal sel : integer range 0 to 1 := 0;
signal input_0 : integer := 0;
signal input_1 : integer := 10;
signal result : integer;
begin
process_1_b : process (sel, input_0, input_1) is
begin
-- code from book:
if sel = 0 then
result <= input_0; -- executed if sel = 0
else
result <= input_1; -- executed if sel /= 0
end if;
-- end of code from book
end process process_1_b;
stimulus : process is
begin
sel <= 1 after 40 ns;
input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns;
input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
afadddad0e05d47c3a027b600334df7c
| 0.654421 | 3.955665 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc76.vhd
| 4 | 2,249 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc76.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p10n04i00076ent IS
END c04s03b01x02p10n04i00076ent;
ARCHITECTURE c04s03b01x02p10n04i00076arch OF c04s03b01x02p10n04i00076ent IS
function F (constant S : BIT_VECTOR) return bit;
function F (constant S : BIT_VECTOR) return bit is
variable res_bit : bit := bit'('0');
begin
for I in S'LOW to S'HIGH loop
if S(I) = bit'('1') then
res_bit := bit'('1');
exit;
end if;
end loop;
return res_bit;
end;
signal X : F bit; -- X is a resolved signal.
signal P,Q : bit := '1';
BEGIN
TESTING: PROCESS(P)
BEGIN
X <= P;
END PROCESS TESTING;
TESTING1: PROCESS(Q)
BEGIN
X <= Q; --NO_Failure Here
END PROCESS TESTING1;
TEST: PROCESS
BEGIN
wait for 10 ns;
assert NOT(X='1')
report "***PASSED TEST: c04s03b01x02p10n04i00076"
severity NOTE;
assert (X='1')
report "***FAILED TEST:c04s03b01x02p10n04i00076 - A signal with multiple source should be a resolved signal."
severity ERROR;
wait;
END PROCESS TEST;
END c04s03b01x02p10n04i00076arch;
|
gpl-2.0
|
490b9f2f7e3f04132cfef6443001322b
| 0.642508 | 3.609952 | false | true | false | false |
tristanseifert/68komputer
|
VideoSRAMController.vhd
| 1 | 2,153 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- This controller provides a simple interface to access the on-board SRAM for
-- video hardware. It exposes two ports: a read-only port for the pixel generator,
-- and a read/write port for the CPU. The latter utilises a FIFO, whereas the
-- read-only port guarantees data output one cycle after /Vid_AS is asserted.
--
entity VideoSRAMController is
PORT(
-- management signals
reset: IN std_logic;
clk: IN std_logic;
-- interface to SRAM
SRAM_Addr: OUT std_logic_vector(17 downto 0) := (others => '0');
SRAM_Data: INOUT std_logic_vector(15 downto 0) := (others => 'Z');
SRAM_CE: OUT std_logic := '1';
SRAM_OE: OUT std_logic := '1';
SRAM_WE: OUT std_logic := '1';
SRAM_LB: OUT std_logic := '1';
SRAM_UB: OUT std_logic := '1';
-- video read interface
Vid_AS_N: IN std_logic; -- active 0
Vid_Addr: IN std_logic_vector(17 downto 0);
Vid_Data: OUT std_logic_vector(15 downto 0) := (others => '0');
Vid_Data_Ready: OUT std_logic
);
end VideoSRAMController;
architecture behavioral of VideoSRAMController is
type rw_state_type is (Idle, ReadAddrVideo, ReadDataVideo);
signal current_state, next_state: rw_state_type;
begin
-- Read/write state machine
process(current_state, Vid_Addr, SRAM_Data)
begin
case current_state is
-- Idle state: deselect the SRAM
when Idle =>
SRAM_CE <= '1';
SRAM_OE <= '1';
SRAM_WE <= '0';
SRAM_UB <= '1';
SRAM_LB <= '1';
Vid_Data_Ready <= '0';
next_state <= Idle;
-- process of reading data for video
when ReadAddrVideo =>
SRAM_CE <= '0';
SRAM_OE <= '0';
SRAM_WE <= '1';
SRAM_UB <= '0';
SRAM_LB <= '0';
SRAM_Addr <= Vid_Addr;
next_state <= ReadDataVideo;
-- Data is ready on SRAM, read it out and restore to idle state.
when ReadDataVideo =>
Vid_Data <= SRAM_Data;
Vid_Data_Ready <= '1';
next_state <= Idle;
end case;
end process;
end behavioral;
|
bsd-2-clause
|
9d01d3b1d52aae8e3228d4a558a1e191
| 0.616349 | 2.998607 | false | false | false | false |
nczempin/NICNAC16
|
ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_exdes.vhd
| 1 | 4,495 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_exdes IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END blk_mem_gen_v7_3_exdes;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_v7_3 IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : blk_mem_gen_v7_3
PORT MAP (
--Port A
ENA => ENA,
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
mit
|
8b74cc93f8701a409032ccc9519fe448
| 0.570412 | 4.600819 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_08.vhd
| 4 | 3,454 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package textio is
type line is access string;
type text is file of string;
type side is (right, left);
subtype width is natural;
file input : text open read_mode is "std_input";
file output : text open write_mode is "std_output";
procedure readline(file f: text; l: out line);
procedure read ( L : inout line; value: out bit; good : out boolean );
procedure read ( L : inout line; value: out bit );
procedure read ( L : inout line; value: out bit_vector; good : out boolean );
procedure read ( L : inout line; value: out bit_vector );
procedure read ( L : inout line; value: out boolean; good : out boolean );
procedure read ( L : inout line; value: out boolean );
procedure read ( L : inout line; value: out character; good : out boolean );
procedure read ( L : inout line; value: out character );
procedure read ( L : inout line; value: out integer; good : out boolean );
procedure read ( L : inout line; value: out integer );
procedure read ( L : inout line; value: out real; good : out boolean );
procedure read ( L : inout line; value: out real );
procedure read ( L : inout line; value: out string; good : out boolean );
procedure read ( L : inout line; value: out string );
procedure read ( L : inout line; value: out time; good : out boolean );
procedure read ( L : inout line; value: out time );
procedure writeline ( file f : text; L : inout line );
procedure write ( L : inout line; value : in bit;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in bit_vector;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in boolean;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in character;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in integer;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0 );
procedure write ( L : inout line; value : in string;
justified: in side := right; field: in width := 0 );
procedure write ( L : inout line; value : in time;
justified: in side := right; field: in width := 0;
unit: in time := ns );
end package textio;
|
gpl-2.0
|
94dc24570603103c333df97db0d9b79d
| 0.634916 | 3.850613 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_20.vhd
| 4 | 4,683 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_20.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_05_20 is
end entity fg_05_20;
architecture test of fg_05_20 is
constant Tpd : delay_length := 2 ns;
function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry_in : bit;
variable carry_out : bit := '0';
begin
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor op2(index) xor carry_in;
carry_out := (op1(index) and op2(index))
or (carry_in and (op1(index) xor op2(index)));
end loop;
return result;
end function "+";
function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is
-- subtraction implemented by adding ((not bv2) + 1), ie -bv2
alias op1 : bit_vector(1 to bv1'length) is bv1;
alias op2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry_in : bit;
variable carry_out : bit := '1';
begin
for index in result'reverse_range loop
carry_in := carry_out; -- of previous bit
result(index) := op1(index) xor (not op2(index)) xor carry_in;
carry_out := (op1(index) and (not op2(index)))
or (carry_in and (op1(index) xor (not op2(index))));
end loop;
return result;
end function "-";
type alu_function_type is (alu_pass_a, alu_add, alu_sub,
alu_add_unsigned, alu_sub_unsigned,
alu_and, alu_or);
signal alu_function : alu_function_type := alu_pass_a;
signal a, b : bit_vector(15 downto 0);
signal functional_result, equivalent_result : bit_vector(15 downto 0);
begin
functional_alu : block is
port ( result : out bit_vector(15 downto 0) );
port map ( result => functional_result );
begin
-- code from book
alu : with alu_function select
result <= a + b after Tpd when alu_add | alu_add_unsigned,
a - b after Tpd when alu_sub | alu_sub_unsigned,
a and b after Tpd when alu_and,
a or b after Tpd when alu_or,
a after Tpd when alu_pass_a;
-- end code from book
end block functional_alu;
--------------------------------------------------
equivalent_alu : block is
port ( result : out bit_vector(15 downto 0) );
port map ( result => equivalent_result );
begin
-- code from book
alu : process is
begin
case alu_function is
when alu_add | alu_add_unsigned => result <= a + b after Tpd;
when alu_sub | alu_sub_unsigned => result <= a - b after Tpd;
when alu_and => result <= a and b after Tpd;
when alu_or => result <= a or b after Tpd;
when alu_pass_a => result <= a after Tpd;
end case;
wait on alu_function, a, b;
end process alu;
-- end code from book
end block equivalent_alu;
--------------------------------------------------
stimulus : process is
begin
alu_function <= alu_add; wait for 10 ns;
a <= X"000A"; wait for 10 ns;
b <= X"0003"; wait for 10 ns;
alu_function <= alu_sub; wait for 10 ns;
alu_function <= alu_and; wait for 10 ns;
alu_function <= alu_or; wait for 10 ns;
alu_function <= alu_pass_a; wait for 10 ns;
wait;
end process stimulus;
verifier :
assert functional_result = equivalent_result
report "Functional and equivalent models give different results";
end architecture test;
|
gpl-2.0
|
c9b9a12eb192a1fcbe8a1ca02b8fae68
| 0.5836 | 3.758427 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd
| 4 | 1,557 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity lead_lag_ztf is
generic ( a1 : real := 2.003140;
a2 : real := -1.996860;
b1 : real := 3.250000;
b2 : real := -0.750000;
k : real := 400.0; -- normalizing gain
tsampl : real := 0.1e-3; -- sample period
init_delay : real := 0.0 ); -- optional delay
port ( quantity input : in real;
quantity output : out real );
end entity lead_lag_ztf;
----------------------------------------------------------------
architecture simple of lead_lag_ztf is
constant num: real_vector := (a1, a2);
constant den: real_vector := (b1, b2);
begin
output == k * input'ztf(num, den, tsampl, init_delay); -- implement transfer function
end architecture simple;
|
gpl-2.0
|
a9f579cf4f4c996fe8791f84f6c97e01
| 0.628131 | 3.982097 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/Architecture1_Pipeline/AES128_V1.vhd
| 1 | 17,089 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 01:55:45 PM
-- Design Name:
-- Module Name: AES128_V1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity AES128_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
READY_TO_DECRYPT : out STD_LOGIC;
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end AES128_V1;
architecture Behavioral of AES128_V1 is
component keyExpansion is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
START : in STD_LOGIC;
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
DONE : out STD_LOGIC;
IDLE : out STD_LOGIC;
MUTATING : out STD_LOGIC;
expandedKey : out STD_LOGIC_VECTOR (1407 downto 0));
end component;
component controlUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
loadSourceSelector : out STD_LOGIC;
addRoundKeySelector1 : out STD_LOGIC_VECTOR(1 downto 0);
addRoundKeySelector2 : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
component addRoundKey is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
keyIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component memoryUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SELB : in STD_LOGIC;
wordAIn : in STD_LOGIC_VECTOR (31 downto 0);
wordBin : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component invShiftRows is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
blockIn : in STD_LOGIC_VECTOR (127 downto 0);
blockOut : out STD_LOGIC_VECTOR (127 downto 0));
end component;
component invSubByte is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component invMixColumn is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component decryptionLoopCore_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
memorySourceSelector : in STD_LOGIC;
keySelector : in STD_LOGIC_VECTOR (1 downto 0);
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component decryptionFinalCore_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
memorySourceSelector : in STD_LOGIC;
keySelector : in STD_LOGIC_VECTOR (1 downto 0);
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal keyExpansion_EN : STD_LOGIC;
signal controlUnit_EN : STD_LOGIC;
signal keyExpansion_DONE : STD_LOGIC;
signal controlUnit_ENABLE : STD_LOGIC;
signal mu1_Out, mu2_Out, mu3_out : STD_LOGIC_VECTOR(31 downto 0);
signal cipherKey : STD_LOGIC_VECTOR(127 downto 0);
--The expanded key and aliases to improve readability.
--Key0 is the original key (same key as was input)
--Key10 is the last expanded key (first used in decrption / last used in encryption)
signal expandedKey : STD_LOGIC_VECTOR(1407 downto 0);
alias key0 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(1407 downto 1280);
alias key1 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(1279 downto 1152);
alias key2 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(1151 downto 1024);
alias key3 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(1023 downto 896);
alias key4 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(895 downto 768);
alias key5 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(767 downto 640);
alias key6 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(639 downto 512);
alias key7 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(511 downto 384);
alias key8 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(383 downto 256);
alias key9 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(255 downto 128);
alias key10 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(127 downto 0);
signal addRoundKey_Key10 : STD_LOGIC_VECTOR(31 downto 0);
signal addRoundKey0_Out : STD_LOGIC_VECTOR(31 downto 0);
--Control Unit output Signals
signal loadSourceSelector : STD_LOGIC;
signal addRoundKeySelector1, addRoundKeySelector2 : STD_LOGIC_VECTOR(1 downto 0);
--Decryption loop interconnect signals.
signal decryptLoop8_Out,
decryptLoop7_Out,
decryptLoop6_Out,
decryptLoop5_Out,
decryptLoop4_Out,
decryptLoop3_Out,
decryptLoop2_Out,
decryptLoop1_Out,
decryptLoop0_Out : STD_LOGIC_VECTOR(31 downto 0);
--ZERO signals to connect to the unused ports in some of the memory units
signal ZERO : STD_LOGIC:= '0';
signal ZEROES : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
ZERO <= '0';
ZEROES <= (others => '0');
READY_TO_DECRYPT <= controlUnit_ENABLE;
mainProcess: process(CLK, RESET)
variable wordCount : NATURAL range 0 to 2 := 0;
type STATE_TYPE is (RECEIVE_KEY, EXPAND_KEY, DECRYPT);
variable state : STATE_TYPE := RECEIVE_KEY;
begin
if RESET = '1' then
state := RECEIVE_KEY;
wordCount := 0;
elsif rising_edge(CLK)then
keyExpansion_EN <= '0';
if ENABLE = '1' then
case state is
when RECEIVE_KEY =>
if wordCount >= 2 then
keyExpansion_EN <= '1';
state := EXPAND_KEY;
else
wordCount := wordCount + 1;
end if;
when EXPAND_KEY =>
if keyExpansion_DONE = '1' then
state := DECRYPT;
end if;
when DECRYPT =>
state := DECRYPT;
when others =>
state := RECEIVE_KEY;
end case;
end if;
end if;
end process;
enableControlUnitLatch: process(keyExpansion_DONE, RESET)
begin
if RESET = '1' then
controlUnit_Enable <= '0';
elsif keyExpansion_DONE = '1' then
controlUnit_Enable <= '1';
end if;
end process;
mu1: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO,
wordAIn => WORD_IN,
wordBIn => ZEROES,
wordOut => mu1_Out);
mu2: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO,
wordAIn => mu1_Out,
wordBIn => ZEROES,
wordOut => mu2_Out);
mu3: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO,
wordAIn => mu2_Out,
wordBIn => ZEROES,
wordOut => mu3_Out);
cipherKey <= mu3_Out & mu2_Out & mu1_Out & WORD_IN;
keyExp: keyExpansion port map( CLK => CLK,
RESET => RESET,
START => keyExpansion_EN,
cipherKey => cipherKey,
DONE => keyExpansion_DONE,
IDLE => open,
MUTATING => open,
expandedKey => expandedKey);
ctrlUnit: controlUnit port map( CLK => CLK,
RESET => RESET,
ENABLE => controlUnit_ENABLE,
loadSourceSelector => loadSourceSelector,
addRoundKeySelector1 => addRoundKeySelector1,
addRoundKeySelector2 => addRoundKeySelector2);
--This is the selector for the word that needs to be added in the addRoundKey stage BEFORE the decryption loop.
addRoundKeySelector0: process(key10, addRoundKeySelector1)
begin
case addRoundKeySelector1 is
when "11" => addRoundKey_Key10 <= key10(127 downto 96);
when "10" => addRoundKey_Key10 <= key10(95 downto 64);
when "01" => addRoundKey_Key10 <= key10(63 downto 32);
when "00" => addRoundKey_Key10 <= key10(31 downto 0);
when others => addRoundKey_Key10 <= (others => '0');
end case;
end process;
addRoundKey0: addRoundKey port map( CLK => CLK,
RESET => RESET,
wordIn => WORD_IN,
keyIn => addRoundKey_Key10,
wordOut => addRoundKey0_Out);
--BEGIN DECRYPTION LOOP
--The decryption loop consists of 9 iterations of the steps:
-- 1) invertShiftRows
-- 2) invertSubBytes
-- 3) addRoundKey
-- 4) invertMixColumns
decryptLoop0: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key9,
WORD_IN => addRoundKey0_Out,
WORD_OUT => decryptLoop0_out);
decryptLoop1: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key8,
WORD_IN => decryptLoop0_out,
WORD_OUT => decryptLoop1_out);
decryptLoop2: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key7,
WORD_IN => decryptLoop1_out,
WORD_OUT => decryptLoop2_out);
decryptLoop3: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key6,
WORD_IN => decryptLoop2_out,
WORD_OUT => decryptLoop3_out);
decryptLoop4: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key5,
WORD_IN => decryptLoop3_out,
WORD_OUT => decryptLoop4_out);
decryptLoop5: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key4,
WORD_IN => decryptLoop4_out,
WORD_OUT => decryptLoop5_out);
decryptLoop6: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key3,
WORD_IN => decryptLoop5_out,
WORD_OUT => decryptLoop6_out);
decryptLoop7: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key2,
WORD_IN => decryptLoop6_out,
WORD_OUT => decryptLoop7_out);
decryptLoop8: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key1,
WORD_IN => decryptLoop7_out,
WORD_OUT => decryptLoop8_out);
decryptFinalStep: decryptionFinalCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key0,
WORD_IN => decryptLoop8_out,
WORD_OUT => WORD_OUT);
end Behavioral;
|
gpl-2.0
|
c61353ced3c2473e690a7a02dda6d869
| 0.425654 | 6.090164 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/switch_dig_2in.vhd
| 4 | 2,582 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity switch_dig_2in is
port ( sw_state : in std_ulogic; -- Digital control input
terminal p_in1, p_in2, p_out : electrical ); -- Analog output
end entity switch_dig_2in;
----------------------------------------------------------------
architecture ideal of switch_dig_2in is
constant r_open : resistance := 1.0e6; -- Open switch resistance
constant r_closed : resistance := 0.001; -- Closed switch resistance
constant trans_time : real := 0.00001; -- Transition time to each position
signal r_sig1 : resistance := r_closed; -- Closed switch resistance variable
signal r_sig2 : resistance := r_open; -- Open switch resistance variable
quantity v1 across i1 through p_in1 to p_out; -- V & I for in1 to out
quantity v2 across i2 through p_in2 to p_out; -- V & I for in2 to out
quantity r1 : resistance; -- Time-varying resistance for in1 to out
quantity r2 : resistance; -- Time-varying resistance for in2 to out
begin
process (sw_state) is -- Sensitivity to digital control input
begin
if sw_state = '0' or sw_state = 'L' then -- Close sig1, open sig2
r_sig1 <= r_closed;
r_sig2 <= r_open;
elsif sw_state = '1' or sw_state = 'H' then -- Open sig1, close sig2
r_sig1 <= r_open;
r_sig2 <= r_closed;
end if;
end process;
r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
v1 == r1 * i1; -- Apply Ohm's law to in1
v2 == r2 * i2; -- Apply Ohm's law to in2
end architecture ideal;
|
gpl-2.0
|
0e491c60930322f3e48cf58579e008d3
| 0.649884 | 3.736614 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/SingleFile/f2m_divider_233.vhd
| 1 | 8,920 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_233 is
generic(
NUM_BITS : positive := 233
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
Ux : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_233 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
--constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
constant F: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par, u_mas_v_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, INIT, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & y;
B <= F;
U <= '0' & x;
v <= (others => '0');
Ux <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
Ux <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
5378104cc171b67276aa270017524227
| 0.499103 | 4.772606 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2737.vhd
| 4 | 22,389 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2737.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p03n01i02737ent IS
END c13s06b00x00p03n01i02737ent;
ARCHITECTURE c13s06b00x00p03n01i02737arch OF c13s06b00x00p03n01i02737ent IS
constant s01: string:="A "; -- 1
constant s02: string:="B "; -- 2
constant s03: string:="C "; -- 3
constant s04: string:="D "; -- 4
constant s05: string:="E "; -- 5
constant s06: string:="F "; -- 6
constant s07: string:="G "; -- 7
constant s08: string:="H "; -- 8
constant s09: string:="I "; -- 9
constant s10: string:="J "; -- 10
constant s11: string:="K "; -- 11
constant s12: string:="L "; -- 12
constant s13: string:="M "; -- 13
constant s14: string:="N "; -- 14
constant s15: string:="O "; -- 15
constant s16: string:="P "; -- 16
constant s17: string:="Q "; -- 17
constant s18: string:="R "; -- 18
constant s19: string:="S "; -- 19
constant s20: string:="T "; -- 20
constant s21: string:="U "; -- 21
constant s22: string:="V "; -- 22
constant s23: string:="W "; -- 23
constant s24: string:="X "; -- 24
constant s25: string:="Y "; -- 25
constant s26: string:="Z "; -- 26
constant s27: string:="0 "; -- 27
constant s28: string:="1 "; -- 28
constant s29: string:="2 "; -- 29
constant s30: string:="3 "; -- 30
constant s31: string:="4 "; -- 31
constant s32: string:="5 "; -- 32
constant s33: string:="6 "; -- 33
constant s34: string:="7 "; -- 34
constant s35: string:="8 "; -- 35
constant s36: string:="9 "; -- 36
constant s37: string:=""" "; -- 37
constant s38: string:="# "; -- 38
constant s39: string:="& "; -- 39
constant s40: string:="' "; -- 40
constant s41: string:="( "; -- 41
constant s42: string:=") "; -- 42
constant s43: string:="* "; -- 43
constant s44: string:="+ "; -- 44
constant s45: string:=", "; -- 45
constant s46: string:="- "; -- 46
constant s47: string:=". "; -- 47
constant s48: string:="/ "; -- 48
constant s49: string:=": "; -- 49
constant s50: string:="; "; -- 50
constant s51: string:="< "; -- 51
constant s52: string:="= "; -- 52
constant s53: string:="> "; -- 53
constant s54: string:="_ "; -- 54
constant s55: string:="| "; -- 55
constant s56: string:=" "; -- 56
constant s57: string:="a "; -- 57
constant s58: string:="b "; -- 58
constant s59: string:="c "; -- 59
constant s60: string:="d "; -- 60
constant s61: string:="e "; -- 61
constant s62: string:="f "; -- 62
constant s63: string:="g "; -- 63
constant s64: string:="h "; -- 64
constant s65: string:="i "; -- 65
constant s66: string:="j "; -- 66
constant s67: string:="k "; -- 67
constant s68: string:="l "; -- 68
constant s69: string:="m "; -- 69
constant s70: string:="n "; -- 70
constant s71: string:="o "; -- 71
constant s72: string:="p "; -- 72
constant s73: string:="q "; -- 73
constant s74: string:="r "; -- 74
constant s75: string:="s "; -- 75
constant s76: string:="t "; -- 76
constant s77: string:="u "; -- 77
constant s78: string:="v "; -- 78
constant s79: string:="w "; -- 79
constant s80: string:="x "; -- 80
constant s81: string:="y "; -- 81
constant s82: string:="z "; -- 82
constant s83: string:="! "; -- 83
constant s84: string:="$ "; -- 84
constant s85: string:="% "; -- 85
constant s86: string:="@ "; -- 86
constant s87: string:="? "; -- 87
constant s88: string:="[ "; -- 88
constant s89: string:="\ "; -- 89
constant s90: string:="] "; -- 90
constant s91: string:="^ "; -- 91
constant s92: string:="` "; -- 92
constant s93: string:="{ "; -- 93
constant s94: string:="} "; -- 94
constant s95: string:="~ "; -- 95
------------------------------------------------------------
constant c01: string:=('A',' '); -- 1
constant c02: string:=('B',' '); -- 2
constant c03: string:=('C',' '); -- 3
constant c04: string:=('D',' '); -- 4
constant c05: string:=('E',' '); -- 5
constant c06: string:=('F',' '); -- 6
constant c07: string:=('G',' '); -- 7
constant c08: string:=('H',' '); -- 8
constant c09: string:=('I',' '); -- 9
constant c10: string:=('J',' '); -- 10
constant c11: string:=('K',' '); -- 11
constant c12: string:=('L',' '); -- 12
constant c13: string:=('M',' '); -- 13
constant c14: string:=('N',' '); -- 14
constant c15: string:=('O',' '); -- 15
constant c16: string:=('P',' '); -- 16
constant c17: string:=('Q',' '); -- 17
constant c18: string:=('R',' '); -- 18
constant c19: string:=('S',' '); -- 19
constant c20: string:=('T',' '); -- 20
constant c21: string:=('U',' '); -- 21
constant c22: string:=('V',' '); -- 22
constant c23: string:=('W',' '); -- 23
constant c24: string:=('X',' '); -- 24
constant c25: string:=('Y',' '); -- 25
constant c26: string:=('Z',' '); -- 26
constant c27: string:=('0',' '); -- 27
constant c28: string:=('1',' '); -- 28
constant c29: string:=('2',' '); -- 29
constant c30: string:=('3',' '); -- 30
constant c31: string:=('4',' '); -- 31
constant c32: string:=('5',' '); -- 32
constant c33: string:=('6',' '); -- 33
constant c34: string:=('7',' '); -- 34
constant c35: string:=('8',' '); -- 35
constant c36: string:=('9',' '); -- 36
constant c37: string:=('"',' '); -- 37
constant c38: string:=('#',' '); -- 38
constant c39: string:=('&',' '); -- 39
constant c40: string:=(''',' '); -- 40
constant c41: string:=('(',' '); -- 41
constant c42: string:=(')',' '); -- 42
constant c43: string:=('*',' '); -- 43
constant c44: string:=('+',' '); -- 44
constant c45: string:=(',',' '); -- 45
constant c46: string:=('-',' '); -- 46
constant c47: string:=('.',' '); -- 47
constant c48: string:=('/',' '); -- 48
constant c49: string:=(':',' '); -- 49
constant c50: string:=(';',' '); -- 50
constant c51: string:=('<',' '); -- 51
constant c52: string:=('=',' '); -- 52
constant c53: string:=('>',' '); -- 53
constant c54: string:=('_',' '); -- 54
constant c55: string:=('|',' '); -- 55
constant c56: string:=(' ',' '); -- 56
constant c57: string:=('a',' '); -- 57
constant c58: string:=('b',' '); -- 58
constant c59: string:=('c',' '); -- 59
constant c60: string:=('d',' '); -- 60
constant c61: string:=('e',' '); -- 61
constant c62: string:=('f',' '); -- 62
constant c63: string:=('g',' '); -- 63
constant c64: string:=('h',' '); -- 64
constant c65: string:=('i',' '); -- 65
constant c66: string:=('j',' '); -- 66
constant c67: string:=('k',' '); -- 67
constant c68: string:=('l',' '); -- 68
constant c69: string:=('m',' '); -- 69
constant c70: string:=('n',' '); -- 70
constant c71: string:=('o',' '); -- 71
constant c72: string:=('p',' '); -- 72
constant c73: string:=('q',' '); -- 73
constant c74: string:=('r',' '); -- 74
constant c75: string:=('s',' '); -- 75
constant c76: string:=('t',' '); -- 76
constant c77: string:=('u',' '); -- 77
constant c78: string:=('v',' '); -- 78
constant c79: string:=('w',' '); -- 79
constant c80: string:=('x',' '); -- 80
constant c81: string:=('y',' '); -- 81
constant c82: string:=('z',' '); -- 82
constant c83: string:=('!',' '); -- 83
constant c84: string:=('$',' '); -- 84
constant c85: string:=('%',' '); -- 85
constant c86: string:=('@',' '); -- 86
constant c87: string:=('?',' '); -- 87
constant c88: string:=('[',' '); -- 88
constant c89: string:=('\',' '); -- 89
constant c90: string:=(']',' '); -- 90
constant c91: string:=('^',' '); -- 91
constant c92: string:=('`',' '); -- 92
constant c93: string:=('{',' '); -- 93
constant c94: string:=('}',' '); -- 94
constant c95: string:=('~',' '); -- 95
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
assert (s01=c01) report "problem with 1 - 'A' " severity failure;
assert (s02=c02) report "problem with 2 - 'B' " severity failure;
assert (s03=c03) report "problem with 3 - 'C' " severity failure;
assert (s04=c04) report "problem with 4 - 'D' " severity failure;
assert (s05=c05) report "problem with 5 - 'E' " severity failure;
assert (s06=c06) report "problem with 6 - 'F' " severity failure;
assert (s07=c07) report "problem with 7 - 'G' " severity failure;
assert (s08=c08) report "problem with 8 - 'H' " severity failure;
assert (s09=c09) report "problem with 9 - 'I' " severity failure;
assert (s10=c10) report "problem with 10 - 'J' " severity failure;
assert (s11=c11) report "problem with 11 - 'K' " severity failure;
assert (s12=c12) report "problem with 12 - 'L' " severity failure;
assert (s13=c13) report "problem with 13 - 'M' " severity failure;
assert (s14=c14) report "problem with 14 - 'N' " severity failure;
assert (s15=c15) report "problem with 15 - 'O' " severity failure;
assert (s16=c16) report "problem with 16 - 'P' " severity failure;
assert (s17=c17) report "problem with 17 - 'Q' " severity failure;
assert (s18=c18) report "problem with 18 - 'R' " severity failure;
assert (s19=c19) report "problem with 19 - 'S' " severity failure;
assert (s20=c20) report "problem with 20 - 'T' " severity failure;
assert (s21=c21) report "problem with 21 - 'U' " severity failure;
assert (s22=c22) report "problem with 22 - 'V' " severity failure;
assert (s23=c23) report "problem with 23 - 'W' " severity failure;
assert (s24=c24) report "problem with 24 - 'X' " severity failure;
assert (s25=c25) report "problem with 25 - 'Y' " severity failure;
assert (s26=c26) report "problem with 26 - 'Z' " severity failure;
assert (s27=c27) report "problem with 27 - '0' " severity failure;
assert (s28=c28) report "problem with 28 - '1' " severity failure;
assert (s29=c29) report "problem with 29 - '2' " severity failure;
assert (s30=c30) report "problem with 30 - '3' " severity failure;
assert (s31=c31) report "problem with 31 - '4' " severity failure;
assert (s32=c32) report "problem with 32 - '5' " severity failure;
assert (s33=c33) report "problem with 33 - '6' " severity failure;
assert (s34=c34) report "problem with 34 - '7' " severity failure;
assert (s35=c35) report "problem with 35 - '8' " severity failure;
assert (s36=c36) report "problem with 36 - '9' " severity failure;
assert (s37=c37) report "problem with 37 - '""' " severity failure;
assert (s38=c38) report "problem with 38 - '#' " severity failure;
assert (s39=c39) report "problem with 39 - '&' " severity failure;
assert (s40=c40) report "problem with 40 - ''' " severity failure;
assert (s41=c41) report "problem with 41 - '(' " severity failure;
assert (s42=c42) report "problem with 42 - ')' " severity failure;
assert (s43=c43) report "problem with 43 - '*' " severity failure;
assert (s44=c44) report "problem with 44 - '+' " severity failure;
assert (s45=c45) report "problem with 45 - ',' " severity failure;
assert (s46=c46) report "problem with 46 - '-' " severity failure;
assert (s47=c47) report "problem with 47 - '.' " severity failure;
assert (s48=c48) report "problem with 48 - '/' " severity failure;
assert (s49=c49) report "problem with 49 - ':' " severity failure;
assert (s50=c50) report "problem with 50 - ';' " severity failure;
assert (s51=c51) report "problem with 51 - '<' " severity failure;
assert (s52=c52) report "problem with 52 - '=' " severity failure;
assert (s53=c53) report "problem with 53 - '>' " severity failure;
assert (s54=c54) report "problem with 54 - '_' " severity failure;
assert (s55=c55) report "problem with 55 - '|' " severity failure;
assert (s56=c56) report "problem with 56 - ' ' " severity failure;
assert (s57=c57) report "problem with 57 - 'a' " severity failure;
assert (s58=c58) report "problem with 58 - 'b' " severity failure;
assert (s59=c59) report "problem with 59 - 'c' " severity failure;
assert (s60=c60) report "problem with 60 - 'd' " severity failure;
assert (s61=c61) report "problem with 61 - 'e' " severity failure;
assert (s62=c62) report "problem with 62 - 'f' " severity failure;
assert (s63=c63) report "problem with 63 - 'g' " severity failure;
assert (s64=c64) report "problem with 64 - 'h' " severity failure;
assert (s65=c65) report "problem with 65 - 'i' " severity failure;
assert (s66=c66) report "problem with 66 - 'j' " severity failure;
assert (s67=c67) report "problem with 67 - 'k' " severity failure;
assert (s68=c68) report "problem with 68 - 'l' " severity failure;
assert (s69=c69) report "problem with 69 - 'm' " severity failure;
assert (s70=c70) report "problem with 70 - 'n' " severity failure;
assert (s71=c71) report "problem with 71 - 'o' " severity failure;
assert (s72=c72) report "problem with 72 - 'p' " severity failure;
assert (s73=c73) report "problem with 73 - 'q' " severity failure;
assert (s74=c74) report "problem with 74 - 'r' " severity failure;
assert (s75=c75) report "problem with 75 - 's' " severity failure;
assert (s76=c76) report "problem with 76 - 't' " severity failure;
assert (s77=c77) report "problem with 77 - 'u' " severity failure;
assert (s78=c78) report "problem with 78 - 'v' " severity failure;
assert (s79=c79) report "problem with 79 - 'w' " severity failure;
assert (s80=c80) report "problem with 80 - 'x' " severity failure;
assert (s81=c81) report "problem with 81 - 'y' " severity failure;
assert (s82=c82) report "problem with 82 - 'z' " severity failure;
assert (s83=c83) report "problem with 83 - '!' " severity failure;
assert (s84=c84) report "problem with 84 - '$' " severity failure;
assert (s85=c85) report "problem with 85 - '%' " severity failure;
assert (s86=c86) report "problem with 86 - '@' " severity failure;
assert (s87=c87) report "problem with 87 - '?' " severity failure;
assert (s88=c88) report "problem with 88 - '[' " severity failure;
assert (s89=c89) report "problem with 89 - '\' " severity failure;
assert (s90=c90) report "problem with 90 - ']' " severity failure;
assert (s91=c91) report "problem with 91 - '^' " severity failure;
assert (s92=c92) report "problem with 92 - '`' " severity failure;
assert (s93=c93) report "problem with 93 - '{' " severity failure;
assert (s94=c94) report "problem with 94 - '}' " severity failure;
assert (s95=c95) report "problem with 95 - '~' " severity failure;
assert NOT( (s01=c01) and
(s02=c02) and
(s03=c03) and
(s04=c04) and
(s05=c05) and
(s06=c06) and
(s07=c07) and
(s08=c08) and
(s09=c09) and
(s10=c10) and
(s11=c11) and
(s12=c12) and
(s13=c13) and
(s14=c14) and
(s15=c15) and
(s16=c16) and
(s17=c17) and
(s18=c18) and
(s19=c19) and
(s20=c20) and
(s21=c21) and
(s22=c22) and
(s23=c23) and
(s24=c24) and
(s25=c25) and
(s26=c26) and
(s27=c27) and
(s28=c28) and
(s29=c29) and
(s30=c30) and
(s31=c31) and
(s32=c32) and
(s33=c33) and
(s34=c34) and
(s35=c35) and
(s36=c36) and
(s37=c37) and
(s38=c38) and
(s39=c39) and
(s40=c40) and
(s41=c41) and
(s42=c42) and
(s43=c43) and
(s44=c44) and
(s45=c45) and
(s46=c46) and
(s47=c47) and
(s48=c48) and
(s49=c49) and
(s50=c50) and
(s51=c51) and
(s52=c52) and
(s53=c53) and
(s54=c54) and
(s55=c55) and
(s56=c56) and
(s57=c57) and
(s58=c58) and
(s59=c59) and
(s60=c60) and
(s61=c61) and
(s62=c62) and
(s63=c63) and
(s64=c64) and
(s65=c65) and
(s66=c66) and
(s67=c67) and
(s68=c68) and
(s69=c69) and
(s70=c70) and
(s71=c71) and
(s72=c72) and
(s73=c73) and
(s74=c74) and
(s75=c75) and
(s76=c76) and
(s77=c77) and
(s78=c78) and
(s79=c79) and
(s80=c80) and
(s81=c81) and
(s82=c82) and
(s83=c83) and
(s84=c84) and
(s85=c85) and
(s86=c86) and
(s87=c87) and
(s88=c88) and
(s89=c89) and
(s90=c90) and
(s91=c91) and
(s92=c92) and
(s93=c93) and
(s94=c94) and
(s95=c95) )
report "***PASSED TEST: c13s06b00x00p03n01i02737"
severity NOTE;
assert ( (s01=c01) and
(s02=c02) and
(s03=c03) and
(s04=c04) and
(s05=c05) and
(s06=c06) and
(s07=c07) and
(s08=c08) and
(s09=c09) and
(s10=c10) and
(s11=c11) and
(s12=c12) and
(s13=c13) and
(s14=c14) and
(s15=c15) and
(s16=c16) and
(s17=c17) and
(s18=c18) and
(s19=c19) and
(s20=c20) and
(s21=c21) and
(s22=c22) and
(s23=c23) and
(s24=c24) and
(s25=c25) and
(s26=c26) and
(s27=c27) and
(s28=c28) and
(s29=c29) and
(s30=c30) and
(s31=c31) and
(s32=c32) and
(s33=c33) and
(s34=c34) and
(s35=c35) and
(s36=c36) and
(s37=c37) and
(s38=c38) and
(s39=c39) and
(s40=c40) and
(s41=c41) and
(s42=c42) and
(s43=c43) and
(s44=c44) and
(s45=c45) and
(s46=c46) and
(s47=c47) and
(s48=c48) and
(s49=c49) and
(s50=c50) and
(s51=c51) and
(s52=c52) and
(s53=c53) and
(s54=c54) and
(s55=c55) and
(s56=c56) and
(s57=c57) and
(s58=c58) and
(s59=c59) and
(s60=c60) and
(s61=c61) and
(s62=c62) and
(s63=c63) and
(s64=c64) and
(s65=c65) and
(s66=c66) and
(s67=c67) and
(s68=c68) and
(s69=c69) and
(s70=c70) and
(s71=c71) and
(s72=c72) and
(s73=c73) and
(s74=c74) and
(s75=c75) and
(s76=c76) and
(s77=c77) and
(s78=c78) and
(s79=c79) and
(s80=c80) and
(s81=c81) and
(s82=c82) and
(s83=c83) and
(s84=c84) and
(s85=c85) and
(s86=c86) and
(s87=c87) and
(s88=c88) and
(s89=c89) and
(s90=c90) and
(s91=c91) and
(s92=c92) and
(s93=c93) and
(s94=c94) and
(s95=c95) )
report "***FAILED TEST: c13s06b00x00p03n01i02737 - All string literal of length 1 are equal in value to their corresponding character values."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p03n01i02737arch;
|
gpl-2.0
|
d1c2d4c47f8b895384b5598c64c1613a
| 0.492072 | 3.337159 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.a-Alu.core/a.b.a.a-Adder.core/a.b.a.a.0-P4AdderCarryGenerator.vhd
| 1 | 3,762 |
--------------------------------------------------------------------------------
-- FILE: P4Adder
-- DESC: The Adder used in P4 micro-processor
--
-- Author:
-- Create: 2015-05-27
-- Update: 2015-05-27
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity P4CarryGenerator is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE;
SPARSITY: integer := C_ADD_SPARSITY
);
port(
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
cin: in std_logic;
cout: out std_logic_vector(DATA_SIZE/SPARSITY-1 downto 0)
);
end P4CarryGenerator;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture p4_carry_generator_arch of P4CarryGenerator is
constant layer : integer := MyLog2Ceil(DATA_SIZE)+1;
type sigmat_t is array (layer-1 downto 0) of std_logic_vector(DATA_SIZE-1 downto 0);
signal p_sigmat, g_sigmat: sigmat_t;
begin
GEi: for i in 0 to layer-1 generate
GEj: for j in 0 to DATA_SIZE-1 generate
-- if part1 (0th row)
GE0: if i=0 generate
-- if part1 (0th row), LSB, consider ci
GE00: if j=0 generate
p_sigmat(i)(j) <= a(j) xor b(j);
g_sigmat(i)(j) <= (a(j) and b(j)) or (a(j) and cin) or (b(j) and cin);
end generate;
-- if part1 (0th row), not LSB, do not consider ci
GE01: if j>0 generate
p_sigmat(i)(j) <= a(j) xor b(j);
g_sigmat(i)(j) <= (a(j) and b(j));
end generate;
end generate;
GE1: if i>0 and i<=MyLog2Ceil(SPARSITY) generate
-- if part2
G10: if ((j+1) mod (2**i) = 0) generate
-- if G node
GE100: if j<2**i generate
g_sigmat(i)(j) <= g_sigmat(i-1)(j) or (p_sigmat(i-1)(j) and g_sigmat(i-1)(j-2**(i-1)));
end generate;
-- if PG node
GE101: if j>=2**i generate
p_sigmat(i)(j) <= p_sigmat(i-1)(j) and p_sigmat(i-1)(j-2**(i-1));
g_sigmat(i)(j) <= g_sigmat(i-1)(j) or (p_sigmat(i-1)(j) and g_sigmat(i-1)(j-2**(i-1)));
end generate;
end generate;
end generate;
-- if part3
GE2: if i>MyLog2Ceil(SPARSITY) generate
-- only the position of node which is n times of sparsity, and the position is in higher part of adjusted current row position will be keep, other nodes, don't care.
GE20: if((j mod (2**i))>=2**(i-1) and (j mod (2**i))<2**i) and (((j+1) mod SPARSITY) =0) generate
-- if G node
GE200: if (j<2**i) generate
g_sigmat(i)(j) <= g_sigmat(i-1)(j) or (p_sigmat(i-1)(j) and g_sigmat(i-1)((j/2**(i-1))*2**(i-1)-1));
end generate;
-- if PG node
GE201: if (j>=2**i) generate
p_sigmat(i)(j) <= p_sigmat(i-1)(j) and p_sigmat(i-1)((j/2**(i-1))*2**(i-1)-1);
g_sigmat(i)(j) <= g_sigmat(i-1)(j) or (p_sigmat(i-1)(j) and g_sigmat(i-1)((j/2**(i-1))*2**(i-1)-1));
end generate;
end generate;
-- if node is on the LOWER part of adjusted current row position, then make it as a buffer in order to be used by following nodes.
GE21: if((j mod (2**i))<2**(i-1) and (j mod (2**i))>=0) and (((j+1) mod SPARSITY) =0) generate
p_sigmat(i)(j) <= p_sigmat(i-1)(j);
g_sigmat(i)(j) <= g_sigmat(i-1)(j);
end generate;
end generate;
-- if last row, sign G signal to cout array
GE3: if i=layer-1 generate
GE30: if ((j+1) mod SPARSITY) =0 generate
cout(j/SPARSITY) <= g_sigmat(i)(j);
end generate;
end generate;
end generate;
end generate;
end p4_carry_generator_arch;
|
mit
|
6ea4e5a20bb86800f1a68a1fb7e27919
| 0.526582 | 2.887183 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_27.vhd
| 4 | 3,216 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_27.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
use work.counter_types.all;
-- end not in book
entity counter is
port ( clk, clr : in bit;
q0, q1 : out digit );
end entity counter;
--------------------------------------------------
architecture registered of counter is
signal current_val0, current_val1, next_val0, next_val1 : digit;
begin
val0_reg : entity work.reg4(struct)
port map ( d0 => next_val0(0), d1 => next_val0(1),
d2 => next_val0(2), d3 => next_val0(3),
q0 => current_val0(0), q1 => current_val0(1),
q2 => current_val0(2), q3 => current_val0(3),
clk => clk, clr => clr );
val1_reg : entity work.reg4(struct)
port map ( d0 => next_val1(0), d1 => next_val1(1),
d2 => next_val1(2), d3 => next_val1(3),
q0 => current_val1(0), q1 => current_val1(1),
q2 => current_val1(2), q3 => current_val1(3),
clk => clk, clr => clr );
incr0 : entity work.add_1(boolean_eqn) -- . . .;
-- not in book
port map ( d0 => current_val0(0), d1 => current_val0(1),
d2 => current_val0(2), d3 => current_val0(3),
y0 => next_val0(0), y1 => next_val0(1),
y2 => next_val0(2), y3 => next_val0(3) );
-- end not in book
incr1 : entity work.add_1(boolean_eqn) -- . . .;
-- not in book
port map ( d0 => current_val1(0), d1 => current_val1(1),
d2 => current_val1(2), d3 => current_val1(3),
y0 => next_val1(0), y1 => next_val1(1),
y2 => next_val1(2), y3 => next_val1(3) );
-- end not in book
buf0 : entity work.buf4(basic) -- . . .;
-- not in book
port map ( a0 => current_val0(0), a1 => current_val0(1),
a2 => current_val0(2), a3 => current_val0(3),
y0 => q0(0), y1 => q0(1),
y2 => q0(2), y3 => q0(3) );
-- end not in book
buf1 : entity work.buf4(basic) -- . . .;
-- not in book
port map ( a0 => current_val1(0), a1 => current_val1(1),
a2 => current_val1(2), a3 => current_val1(3),
y0 => q1(0), y1 => q1(1),
y2 => q1(2), y3 => q1(3) );
-- end not in book
end architecture registered;
|
gpl-2.0
|
c3f32458c62f542a0dbde49e171e34f4
| 0.532338 | 3.196819 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/building_blocks/invShiftRows_tb.vhd
| 1 | 1,846 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 07:54:52 PM
-- Design Name:
-- Module Name: invShiftRows_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity invShiftRows_tb is
end invShiftRows_tb;
architecture Behavioral of invShiftRows_tb is
component invShiftRows is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
blockIn : in STD_LOGIC_VECTOR (127 downto 0);
blockOut : out STD_LOGIC_VECTOR (127 downto 0));
end component;
constant clk_period : time := 2ns;
signal CLK, RESET : STD_LOGIC;
signal blockIn, blockOut : STD_LOGIC_VECTOR(127 downto 0);
begin
uut: invShiftRows port map( CLK => CLK,
RESET => RESET,
blockIn => blockIn,
blockOut => blockOut);
clk_process: process
begin
CLK <= '1';
wait for clk_period/2;
CLK <= '0';
wait for clk_period/2;
end process;
stim_process: process
begin
wait for 5*clk_period;
blockIn <= x"00112233445566778899AABBCCDDEEFF";
wait for clk_period;
RESET <= '1';
wait for clk_period;
RESET <= '0';
wait for clk_period;
blockIn <= x"FFEEDDCCBBAA99887766554433221100";
wait for clk_period;
blockIn <= x"632FAFA2EB93C7209F92ABCBA0C0302B";
wait for 5*clk_period;
end process;
end Behavioral;
|
gpl-2.0
|
372144eedca5fbe26d8551ef4b113e07
| 0.516251 | 4.323185 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt-b.vhd
| 4 | 2,553 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_multt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of multiplier_test is
signal a, b : std_ulogic_vector(15 downto 0) := (others => '0');
signal p : std_ulogic_vector(31 downto 0);
begin
dut : entity work.multiplier(behavioral)
port map (a, b, p);
stimulus : process is
begin
a <= X"8000"; b <= X"8000"; -- -1 * -1
wait for 50 ns;
a <= X"0001"; b <= X"0001"; -- 2**-15 * 2**-15
wait for 50 ns;
a <= X"0001"; b <= X"0000"; -- 2**-15 * 0
wait for 50 ns;
a <= X"0000"; b <= X"0001"; -- 0 * 2**-15
wait for 50 ns;
a <= X"0001"; b <= X"8000"; -- 2**-15 * -1
wait for 50 ns;
a <= X"8000"; b <= X"0001"; -- -1 * 2**-15
wait for 50 ns;
a <= X"4000"; b <= X"4000"; -- 0.5 * 0.5
wait for 50 ns;
a <= X"C000"; b <= X"4000"; -- -0.5 * 0.5
wait for 50 ns;
a <= X"4000"; b <= X"C000"; -- 0.5 * -0.5
wait for 50 ns;
a <= X"C000"; b <= X"C000"; -- -0.5 * -0.5
wait for 50 ns;
wait;
end process stimulus;
end architecture bench;
|
gpl-2.0
|
691055445c21fc2a076a6f9231adc963
| 0.453976 | 3.976636 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.b.c-tbRegisterFile.vhd
| 1 | 2,481 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
use work.Funcs.all;
entity tbRegisterFile is
end tbRegisterFile;
architecture tb_register_file_arch of tbRegisterFile is
signal clk: std_logic := '0';
signal rst: std_logic;
signal en: std_logic;
signal rd1_en: std_logic;
signal rd2_en: std_logic;
signal wr_en: std_logic;
signal rd1_addr: std_logic_vector(4 downto 0);
signal rd2_addr: std_logic_vector(4 downto 0);
signal wr_addr: std_logic_vector(4 downto 0);
signal d_out1: std_logic_vector(31 downto 0);
signal d_out2: std_logic_vector(31 downto 0);
signal d_in: std_logic_vector(31 downto 0);
component RegisterFile is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_NUM : integer := C_REG_NUM
);
port(
clk : in std_logic; -- clock
rst : in std_logic; -- reset
en : in std_logic; -- enable
rd1_en : in std_logic; -- read port 1
rd2_en : in std_logic; -- read port 2
wr_en : in std_logic; -- write port
rd1_addr: in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of read port 1
rd2_addr: in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of read port 2
wr_addr : in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of write port
d_out1 : out std_logic_vector(DATA_SIZE-1 downto 0); -- data out 1 bus
d_out2 : out std_logic_vector(DATA_SIZE-1 downto 0); -- data out 2 bus
d_in : in std_logic_vector(DATA_SIZE-1 downto 0) -- data in bus
);
end component;
begin
RG:RegisterFile
generic map(32, 32)
port map (clk, rst, en, rd1_en, rd2_en, wr_en, rd1_addr, rd2_addr, wr_addr, d_out1, d_out2, d_in);
rst <= '0','1' after 5 ns;
en <= '0','1' after 3 ns;
wr_en <= '0','1' after 6 ns, '0' after 7 ns, '1' after 10 ns, '0' after 20 ns;
rd1_en <= '1','0' after 5 ns, '1' after 13 ns, '0' after 20 ns;
rd2_en <= '0','1' after 17 ns;
wr_addr <= "10110", "01000" after 9 ns, "00000" after 19 ns;
rd1_addr <="10110", "01000" after 9 ns, "00000" after 19 ns;
rd2_addr <= "11100", "01000" after 9 ns;
d_in<=(others => '0'),(others => '1') after 8 ns;
PCLOCK : process(clk)
begin
clk <= not(clk) after 0.5 ns;
end process;
end tb_register_file_arch;
configuration tb_register_file_cfg of tbRegisterFile is
for tb_register_file_arch
end for;
end tb_register_file_cfg;
|
mit
|
9c4b06f69259860dda98268a9a28226c
| 0.621524 | 2.741436 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc435.vhd
| 4 | 3,227 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc435.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00435ent IS
END c03s02b01x01p19n01i00435ent;
ARCHITECTURE c03s02b01x01p19n01i00435arch OF c03s02b01x01p19n01i00435ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2time_cons_vector is array (row,column) of time;
constant C1 : s2time_cons_vector := (others => (others => 3 ns));
function complex_scalar(s : s2time_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return s2time_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : s2time_cons_vector;
signal S2 : s2time_cons_vector;
signal S3 : s2time_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00435"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00435 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00435arch;
|
gpl-2.0
|
7c932517f648077eee0d5ac9fd474408
| 0.64983 | 3.601563 | false | true | false | false |
velentr/foundry.vhdl
|
register.vhd
| 1 | 2,820 |
--------------------------------------------------------------------------------
--
-- register.vhd
--
-- This file contains the logic for a single register. The contents of the
-- register will always be output. The register will change its value to the
-- input on every rising edge of the clock, whenever the 'nLd' input is
-- asserted. The design is parametrized on 'N', the size of the register.
--
-- The size of this cell is O(N).
--
-- Dependencies:
-- None.
--
-- Revision History:
-- 07 May 2015 Brian Kubisiak Initial revision.
--
--------------------------------------------------------------------------------
-- bring in the necessary packages
library ieee;
use ieee.std_logic_1164.all;
-- Reg
--
-- parameters:
-- N (integer) Number of bits in the register.
--
-- inputs:
-- Clk (std_logic) System clock for latching the input.
-- DataIn (std_logic_vector) Data input for loading into the register.
-- nLd (std_logic) Active-low signal indicating the input
-- should be latched on the next rising clock
-- edge.
--
-- outputs:
-- DataOut (std_logic_vector) Value currently stored in the register.
--
entity Reg is
generic ( N : integer := 8 ); -- Number of bits.
port (
Clk : in std_logic; -- System clock.
DataIn : in std_logic_vector(N-1 downto 0); -- Data input.
nLd : in std_logic; -- Latch the input.
DataOut : out std_logic_vector(N-1 downto 0) -- Value in register.
);
end Reg;
architecture procedural of Reg is
-- Current value in the register. It will always be output, and will be
-- loaded on the rising edge of the clock whenever 'nLd' is asserted.
signal value : std_logic_vector(N-1 downto 0);
begin
-- Always output the current value of the register.
DataOut <= value;
--
-- LoadReg
--
-- This process will latch the register value on every clock, unless the
-- 'nLd' signal is asserted. If this is asserted, then the new value is
-- taken from the data input.
--
LoadReg: process(clk)
begin
-- Latch the data using the given clock.
if rising_edge(clk) then
-- When loading, store the new value.
if (nLd = '0') then
value <= DataIn;
-- Else, when not loading, latch the current value.
elsif (nLd = '1') then
value <= value;
-- For simulation, latch unknown value when input is unknown.
else
value <= (others => 'X');
end if;
end if;
end process;
end procedural;
|
mit
|
568d5579f6035e24c5d67dbe1622b327
| 0.532979 | 4.358578 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_pll.vhd
| 4 | 2,589 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-- File : C:\VHDL-AMS\CaseStudies\CS4_CommSystem\Default\genhdl\vhdl\tb_pll.vhd
-- CDB : C:\VHDL-AMS\CaseStudies\CS4_CommSystem\default\default.cdb
-- By : CDB2VHDL Netlister version 16.1.0.2
-- Time : Fri Apr 05 12:08:46 2002
-- Entity/architecture declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity tb_pll is
end tb_pll;
architecture tb_pll of tb_pll is
-- Component declarations
-- Signal declarations
signal f_ref : real;
terminal lf_out : electrical;
terminal v_ref : electrical;
signal vco_f : real;
terminal vco_out : electrical;
begin
-- Signal assignments
-- Component instances
PLL6 : entity work.PLL(behavioral)
generic map(
Fp => 20.0e3,
Fz => 1.0e6,
Kv => 100.0e3,
Fc => 1.0e6
)
port map(
input => v_ref,
lf_out => lf_out,
vco_out => vco_out
);
v1 : entity work.v_SweptSine(bhv)
generic map(
StartFreq => 900.0e3,
SweepRate => 2000.0e6,
FinishFreq => 1.1e6,
InitDelay => 80.0e-6,
PeakAmp => 5.0
)
port map(
pos => v_ref,
neg => ELECTRICAL_REF
);
MeasFreq9 : entity work.MeasFreq(ThresDetect)
port map(
input => v_ref,
f_out => f_ref
);
MeasFreq10 : entity work.MeasFreq(ThresDetect)
port map(
input => vco_out,
f_out => vco_f
);
end tb_pll;
|
gpl-2.0
|
d1724655ca74e282aee5842cd802a624
| 0.62611 | 3.636236 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2963.vhd
| 4 | 3,770 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2963.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p03n01i02963pkg is
FUNCTION boo (P1:integer;X:bit:='1') RETURN integer;
FUNCTION boo (P2:integer;X:bit_vector:="1010") RETURN integer;
FUNCTION boo (P3:integer;X:boolean:=TRUE) RETURN integer;
FUNCTION boo (P4:integer;X:character:='Z') RETURN integer;
FUNCTION boo (P5:integer;X:integer:=55) RETURN integer;
FUNCTION boo (P6:integer;X:real:=10.01) RETURN integer;
FUNCTION boo (P7:integer;X:string:="STRING") RETURN integer;
FUNCTION boo (P8:integer;X:time:=10 ns) RETURN integer;
end c02s03b00x00p03n01i02963pkg;
package bodyc02s03b00x00p03n01i02963pkg is
FUNCTION boo (P1:integer;X:bit:='1') RETURN integer IS
BEGIN
assert false report "boo with BIT param" severity note;
RETURN 1;
END;
FUNCTION boo (P2:integer;X:bit_vector:="1010") RETURN integer IS
BEGIN
assert false report "boo with BIT_VECTOR param" severity note;
RETURN 2;
END;
FUNCTION boo (P3:integer;X:boolean:=TRUE) RETURN integer IS
BEGIN
assert false report "boo with BOOLEAN param" severity note;
RETURN 3;
END;
FUNCTION boo (P4:integer;X:character:='Z') RETURN integer IS
BEGIN
assert false report "boo with CHARACTER param" severity note;
RETURN 4;
END;
FUNCTION boo (P5:integer;X:integer:=55) RETURN integer IS
BEGIN
assert false report "boo with INTEGER param" severity note;
RETURN 5;
END;
FUNCTION boo (P6:integer;X:real:=10.01) RETURN integer IS
BEGIN
assert false report "boo with REAL param" severity note;
RETURN 6;
END;
FUNCTION boo (P7:integer;X:string:="STRING") RETURN integer IS
BEGIN
assert false report "boo with STRING param" severity note;
RETURN 7;
END;
FUNCTION boo (P8:integer;X:time:=10 ns) RETURN integer IS
BEGIN
assert false report "boo with TIME param" severity note;
RETURN 8;
END;
end c02s03b00x00p03n01i02963pkg;
ENTITY c02s03b00x00p03n01i02963ent IS
PORT (b1,b2,b3,b4,b5,b6,b7,b8: INOUT integer);
END c02s03b00x00p03n01i02963ent;
use work.c02s03b00x00p03n01i02963pkg.all;
ARCHITECTURE c02s03b00x00p03n01i02963arch OF c02s03b00x00p03n01i02963ent IS
SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
c1 <= boo(b1);
c2 <= boo(b2);
c3 <= boo(b3);
c4 <= boo(b4);
c5 <= boo(b5);
c6 <= boo(b6);
c7 <= boo(b7);
c8 <= boo(b8);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c02s03b00x00p03n01i02963 - A call to an overloaded subprogram is ambiguous."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p03n01i02963arch;
|
gpl-2.0
|
995d5aff41a046e6995fa37514fc35ba
| 0.685146 | 3.345164 | false | false | false | false |
nczempin/NICNAC16
|
ipcore_dir/blk_mem_gen_v7_3/simulation/bmg_stim_gen.vhd
| 1 | 12,646 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
DATA_IN : IN STD_LOGIC_VECTOR (15 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0):= hex_to_std_logic_vector("0",16);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (255 downto 0) of std_logic_vector(15 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"blk_mem_gen_v7_3.mif",
DEFAULT_DATA,
16,
256);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 256 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
ENA <= DO_READ ;
END ARCHITECTURE;
|
mit
|
69b181064aec316fc7517bbadbb5be8d
| 0.546655 | 3.677232 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_233.vhd
| 1 | 4,719 |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_233 is
generic (
NUM_BITS : positive := 233 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_233;
-----------------------------------------------------------
architecture behave of serial_multiplier_233 is
-----------------------------------------------------------
-- m = 233 x233 + x74 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "11101000"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
if counter = "00000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
Done <= '1';
else
bx_int <= bx_shift;
end if;
when END_STATE =>
CurrentState <= END_STATE;
Done <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
8ab2c0d15d3fee46b9bb6895c6fa4135
| 0.488451 | 4.373494 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller_types_and_utilities.vhd
| 4 | 2,333 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package cpu_types is
constant word_size : positive := 16;
subtype word is bit_vector(word_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
end package cpu_types;
package bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
end package bit_vector_unsigned_arithmetic;
package body bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
alias norm1 : bit_vector(1 to bv1'length) is bv1;
alias norm2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "arguments of different length" severity failure;
else
for index in norm1'reverse_range loop
result(index) := norm1(index) xor norm2(index) xor carry;
carry := ( norm1(index) and norm2(index) )
or ( carry and ( norm1(index) or norm2(index) ) );
end loop;
end if;
return result;
end function "+";
end package body bit_vector_unsigned_arithmetic;
-- code from book
package DMA_controller_types_and_utilities is
alias word is work.cpu_types.word;
alias status_value is work.cpu_types.status_value;
alias "+" is work.bit_vector_unsigned_arithmetic."+"
[ bit_vector, bit_vector return bit_vector ];
-- . . .
end package DMA_controller_types_and_utilities;
-- end code from book
|
gpl-2.0
|
543b95a09c6b382883d6bb03eb047e5d
| 0.687955 | 3.756844 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/base/reset_sync.vhd
| 1 | 1,181 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: RESET_SYNC
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RESET_SYNC is
Port (
CLK : in std_logic; -- Clock
ASYNC_RST : in std_logic; -- High active async reset input
OUT_RST : out std_logic -- High active sync async reset output
);
end RESET_SYNC;
architecture FULL of RESET_SYNC is
signal meta_reg : std_logic;
signal reset_reg : std_logic;
begin
process (CLK, ASYNC_RST)
begin
if (ASYNC_RST = '1') then
meta_reg <= '1';
reset_reg <= '1';
elsif (rising_edge(CLK)) then
meta_reg <= '0';
reset_reg <= meta_reg;
end if;
end process;
OUT_RST <= reset_reg;
end FULL;
|
mit
|
fed2c62396f37fe191bb365bb3d20dff
| 0.470787 | 4.294545 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc667.vhd
| 4 | 4,662 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc667.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:57 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:26 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00667ent IS
END c03s04b01x00p01n01i00667ent;
ARCHITECTURE c03s04b01x00p01n01i00667arch OF c03s04b01x00p01n01i00667ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type array_rec_cons is array (integer range <>) of record_cons_array;
constant C1 : boolean := true;
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C58 : array_rec_cons (0 to 7) := (others => C27);
type array_rec_cons_file is file of array_rec_cons;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : array_rec_cons_file open read_mode is "iofile.13";
variable v : array_rec_cons(0 to 7);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 8) report "wrong length passed during read operation";
if (v /= C58) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00667"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00667 - File reading of array_rec_cons_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00667arch;
|
gpl-2.0
|
2273baa3e34b71dba600db50a097da58
| 0.555556 | 3.86888 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/MAIA/inverter_maia_grade.vhd
| 1 | 6,297 |
----------------------------------------------------------------------------------------------------
-- inverter_maia.vhd ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the Modified Almost Inverse Algorithm.
-- The input buses need to have valid data when Reset signal is asserted.
-- All internal registers and operations are performed one bit more than the input
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
--------------------------------------------------------
entity inverter_maia is
generic(
NUM_BITS : positive := 163 -- The order of the finite field
);
port(
ax : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- input polynomial of grade m-1
Fx : in STD_LOGIC_VECTOR(NUM_BITS downto 0); -- prime polynomial of grade m
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
z : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end inverter_maia;
---------------------------------------------------------
architecture behave of inverter_maia is
---------------------------------------------------------
signal B,C,U,V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal processing registers, one bit more
signal Bx_Op1 : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Multiplexer which depends on if B is ever or odd
signal Ux_div_x : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- U and B divided by x
signal Bx_div_x : STD_LOGIC_VECTOR(NUM_BITS downto 0);
constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
signal grade_u : std_logic_vector(7 downto 0); -- Return the grade of U and V, it is assumed they are less than 256
signal grade_v : std_logic_vector(7 downto 0);
signal done_gu, done_gv, rst_grade: std_logic;
----------------------------------------------------------------------------------
-- States fot the FSM controlling the execution of the algorithm
----------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, WAIT_GRADE, LOOP_U0, CALC_GRADE, NEXT_STEP);
signal State: CurrentState_type;
----------------------------------------------------------------------------------
begin
------------------------------------------------------
Ux_div_x <= '0' & U(NUM_BITS downto 1); -- Dividing U and B by x
Bx_div_x <= '0' & Bx_Op1(NUM_BITS downto 1);
------------------------------------------------------
Bx_Op1 <= B xor Fx when B(0) = '1' else -- Multiplexer for operand B
B;
------------------------------------------------------
-- Two instances for computing the grade of U and V
------------------------------------------------------
gradeU: entity work.grade(grade)
port map (rst_grade, clk, U, done_gu, grade_u);
gradeV: entity work.grade(grade)
port map (rst_grade, clk, V, done_gv, grade_v);
-------------------------------------------------------
-- The Modified ALmost Inverse Algorithm implementation
-------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then -- initialize internal registers
State <= LOOP_U0;
B <= UNO;
U <= '0'&Ax;
V <= Fx;
C <= (others => '0');
z <= (others => '0'); -- set to zero the output register
Done <= '0';
rst_grade <= '0';
else
case State is
-----------------------------------------------------------------------------------
when LOOP_U0 => -- Stay here while U be even
if U(0) = '1' then
if U = UNO then -- The algorithm finishes when U = 1
Z <= B(NUM_BITS-1 downto 0);
Done <= '1';
State <= END_STATE;
else -- Compute the grade of the the currents values of U and V
rst_grade <= '1';
State <= CALC_GRADE;
end if;
else -- Divide U and B and repeat the process
U <= Ux_div_x;
B <= Bx_div_x;
end if;
-----------------------------------------------------------------------------------
when CALC_GRADE => -- generate the reset signal and wait for the result
rst_grade <= '0';
state <= WAIT_GRADE;
-----------------------------------------------------------------------------------
when WAIT_GRADE =>
if done_gu = '1' and done_gv = '1' then
if(grade_u < grade_v) then -- Interchange the registers U <-> V and B <-> C
U <= V;
V <= U;
B <= C;
C <= B;
end if;
State <= NEXT_STEP; -- wait a cycle to compute with the current values assigned
end if;
-----------------------------------------------------------------------------------
when NEXT_STEP => -- update U and B with the values previously assigned
U <= U xor V;
B <= B xor C;
State <= LOOP_U0;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
State <= END_STATE;
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
349a0e9eade0920d19ed3fda5b0eabea
| 0.4175 | 4.623348 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system.vhd
| 4 | 2,057 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity computer_system is
end entity computer_system;
-- end not in book
architecture top_level of computer_system is
function resolve_bits ( bits : bit_vector ) return bit is
variable result : bit := '0';
begin
for index in bits'range loop
result := result or bits(index);
exit when result = '1';
end loop;
return result;
end function resolve_bits;
signal write_en : resolve_bits bit bus;
-- . . .
-- not in book
constant Tpd : delay_length := 2 ns;
signal clock, hold_req : bit := '0';
-- end not in book
begin
CPU : process is
-- . . .
begin
write_en <= '0' after Tpd;
-- . . .
loop
wait until clock = '1';
if hold_req = '1' then
write_en <= null after Tpd;
wait on clock until clock = '1' and hold_req = '0';
write_en <= '0' after Tpd;
end if;
-- . . .
end loop;
end process CPU;
-- . . .
-- not in book
clock_gen : clock <= '1' after 5 ns, '0' after 10 ns when clock = '0';
stimulus : hold_req <= '1' after 40 ns, '0' after 80 ns;
process is
begin
write_en <= null, '1' after 50 ns, '0' after 60 ns, null after 70 ns;
wait;
end process;
-- end not in book
end architecture top_level;
|
gpl-2.0
|
f8c6a5790f297b8a80cfa28ec8114743
| 0.640739 | 3.692998 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system-1.vhd
| 4 | 2,416 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity computer_system_abstract is
end entity computer_system_abstract;
-- code from book
architecture abstract of computer_system_abstract is
-- not in book
subtype word is bit_vector(31 downto 0);
type word_vector is array (natural range <>) of word;
function resolve_word ( drivers : word_vector ) return word is
begin
if drivers'length > 0 then
return drivers(drivers'left);
else
return X"00000000";
end if;
end function resolve_word;
-- end not in book
-- . . .
signal address_bus : resolve_word word bus;
signal hold_req : bit;
-- . . .
-- not in book
signal clk : bit := '0';
-- end not in book
begin
cpu : block is
signal guard : boolean := false;
signal cpu_internal_address : word;
-- . . .
begin
cpu_address_driver:
address_bus <= guarded cpu_internal_address;
-- . . . -- other bus drivers
controller : process is
-- . . .
begin
-- . . .
-- . . . -- determine when to disable cpu bus drivers
guard <= false;
wait on clk until hold_req = '0' and clk = '1';
guard <= true; -- reenable cpu bus drivers
-- . . .
-- not in book
wait until clk = '1';
-- end not in book
end process controller;
-- . . . -- cpu data-path processes
-- not in book
cpu_internal_address <= X"11111111";
-- end not in book
end block cpu;
-- . . . -- blocks for DMA and other modules
-- not in book
clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
-- end not in book
end architecture abstract;
-- end code from book
|
gpl-2.0
|
b21a7707837c3838a757559dcbf24705
| 0.638659 | 3.934853 | false | false | false | false |
velentr/foundry.vhdl
|
uartrx.vhd
| 1 | 5,778 |
--------------------------------------------------------------------------------
--
-- uartrx.vhd
--
-- Universal asynchronous receiver/transmitter---receiver design.
--
-- This file contains the design for the receiver on a UART. The UART will take
-- in data serially on the RX line, starting with a single low start bit. This
-- implementation uses N-bit characters, 1 stop bit, and no parity bit. The
-- baud rate is the same as the input clock frequency. The design is
-- parameterized on the number of bits in the character.
--
-- Once a full character has been received over the serial line, the 'rdy'
-- output will be pulsed low for one clock to indicate that data is ready. This
-- data will remain latched until the next pulse on the 'rdy' signal.
--
-- If the stop bit is '0' instead of '1', then the 'err' signal will be pulsed
-- low instead of 'rdy'. Even if an error occurred, the received data will
-- still be output.
--
-- The data is loaded as if we received the MSB first. That is, each new bit is
-- shifted into the LSB of the shift register.
--
-- Dependencies:
-- None.
--
-- Revision History:
-- 17 Apr 2015 Brian Kubisiak Initial revision.
-- 21 Apr 2015 Brian Kubisiak Changed to MSB-first.
-- 22 Apr 2015 Brian Kubisiak Updated documentation.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
-- uartrx
--
-- Parameters:
-- N (integer) Number of bits per character.
--
-- Inputs:
-- reset (std_logic) Active-low line to reset the UART receiver.
-- clk (std_logic) Baud rate clock. The UART will sample the input
-- signal on every rising edge of the clock.
-- rx (std_logic) Receive line carrying the serial data.
--
-- Outputs:
-- data (std_logic_vector) Last character received over the UART.
-- rdy (std_logic) Active-low line indicating when the data is
-- ready. Once a character is received, this will
-- pulse low for one clock.
-- err (std_logic) Active-low signal indicating an error occurred.
-- Currently, this means that the stop bit was not
-- high.
--
entity uartrx is
generic ( N : integer := 8 );
port
(
reset : in std_logic; -- Reset the UART.
clk : in std_logic; -- Baud clock.
rx : in std_logic; -- Serial data input.
data : out std_logic_vector(N-1 downto 0); -- Parallel data output.
rdy : out std_logic; -- New data ready.
err : out std_logic -- Error occurred.
);
end entity;
architecture procedural of uartrx is
-- Shift register for loading new data from the serial line.
signal shftrx : std_logic_vector(N-1 downto 0);
-- Buffer for outputting the received data.
signal outbuf : std_logic_vector(N-1 downto 0);
-- Counter for indicating the number of bits received. There is 1 start bit,
-- N data bits, and 1 stop bit for a total of N+2 bits.
signal state : integer range 0 to N+1;
begin
-- Always output the buffered data.
data <= outbuf;
--
-- LoadNextBit
--
-- On each clock edge, this process will shift a new bit into the shift
-- register. Once the character is full, it will pulse the 'rdy' signal low
-- and output the data. It will then wait for the next start bit to begin
-- receiving again.
--
-- If the stop bit is found to be '0' instead of '1', then the 'err' signal
-- will be pulsed low instead of 'rdy'.
--
LoadNextBit: process (clk)
begin
if rising_edge(clk) then
-- By default, data is not ready and no error has occurred.
rdy <= '1';
err <= '1';
-- By default, latch the output buffer and shift register.
outbuf <= outbuf;
shftrx <= shftrx;
-- First, check for reset conditions.
if (reset = '0') then
-- When resetting, we set the counter back to zero to wait for
-- the next start bit.
state <= 0;
-- If no bits loaded, wait for start bit.
elsif (state = 0) then
if (rx = '0') then
-- Start bit received, begin shifting in data.
state <= 1;
else
-- Otherwise, continue waiting.
state <= 0;
end if;
-- All data has been received.
elsif (state = N+1) then
-- Reset counter regardless of data validity.
state <= 0;
-- Always output the shifted data, even if it is found to be
-- invalid.
outbuf <= shftrx;
-- Check for a valid stop bit.
if (rx = '1') then
-- Stop bit is valid; indicate data is ready.
rdy <= '0';
else
-- Stop bit invalid; indicate an error occurred.
err <= '0';
end if;
-- Still just shifting in the data.
else
-- Shift the new data bit into the LSB of the shift register.
shftrx <= shftrx(N-2 downto 0) & rx;
-- Go to next state.
state <= state + 1;
end if;
end if;
end process;
end architecture procedural;
|
mit
|
1cce9fae35b053b2906026bde26907ba
| 0.52821 | 4.482545 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_04.vhd
| 4 | 1,738 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_04 is
end entity fg_a_04;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_04 is
signal clk, reset, d, q, q_n : std_ulogic;
begin
-- code from book
ff1 : process (reset, clk) is
begin
if reset = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff1;
q_n <= not q;
-- end code from book
stimulus : process is
begin
reset <= '0'; clk <= '0'; d <= '1'; wait for 10 ns;
reset <= '1', '0' after 30 ns;
clk <= '1' after 10 ns, '0' after 20 ns;
wait for 40 ns;
clk <= '1', '0' after 20 ns;
d <= '0' after 10 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
ba40e6cc267eec40b369bc296b4800fb
| 0.594361 | 3.554192 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/max3.vhd
| 4 | 1,501 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity max3 is
port ( a, b, c : in integer; z : out integer );
end entity max3;
--------------------------------------------------
architecture check_error of max3 is
begin
maximizer : process (a, b, c)
variable result : integer;
begin
if a > b then
if a > c then
result := a;
else
result := a; -- Oops! Should be: result := c;
end if;
elsif b > c then
result := b;
else
result := c;
end if;
assert result >= a and result >= b and result >= c
report "inconsistent result for maximum"
severity failure;
z <= result;
end process maximizer;
end architecture check_error;
|
gpl-2.0
|
3b05b527beda01fac5c00aa615c1d4be
| 0.631579 | 4.181058 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd
| 4 | 1,714 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity triangle_waveform is
port ( terminal pos, neg : electrical );
end entity triangle_waveform;
----------------------------------------------------------------
architecture ideal of triangle_waveform is
constant freq : real := 10_000.0; -- in Hz
constant period : real := 1.0 / freq;
constant amplitude : voltage := 5.0;
constant offset : voltage := 0.0;
signal square_wave : real := 0.0;
quantity v across i through pos to neg;
limit v : voltage with period / 10.0;
begin
process is
variable state : bit := '0';
begin
if state = '1' then
square_wave <= 1.0;
else
square_wave <= 0.0;
end if;
state := not state;
wait for period / 2.0;
end process;
v == offset + amplitude * square_wave'ramp(period / 2.0);
end architecture ideal;
|
gpl-2.0
|
ee09ee5e24828b1f4df9d299b5abcc59
| 0.649942 | 4.13012 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/reg_bank.vhd
| 2 | 10,179 |
---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
entity reg_bank is
generic(memory_type : string := "DUAL_PORT_");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
intr_enable_reg, data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0);
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
--------------------------------------------------------------
---- Pick only ONE of the dual-port RAM implementations below!
--------------------------------------------------------------
-- Option #1
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
-- tri_port_mem:
-- if memory_type = "TRI_PORT_X" generate
-- ram_proc: process(clk, addr_read1, addr_read2,
-- addr_write, reg_dest_new, write_enable)
-- variable tri_port_ram : ram_type;
-- begin
-- data_out1 <= tri_port_ram(conv_integer(addr_read1));
-- data_out2 <= tri_port_ram(conv_integer(addr_read2));
-- if rising_edge(clk) then
-- if write_enable = '1' then
-- tri_port_ram(conv_integer(addr_write)) := reg_dest_new;
-- end if;
-- end if;
-- end process;
-- end generate; --tri_port_mem
-- Option #2
-- Two dual-port RAMs, each with one read-port and one write-port
dual_port_mem:
if memory_type = "DUAL_PORT_" generate
ram_proc2: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable dual_port_ram1 : ram_type;
variable dual_port_ram2 : ram_type;
begin
data_out1 <= dual_port_ram1(conv_integer(addr_read1));
data_out2 <= dual_port_ram2(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;
dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
end generate; --dual_port_mem
-- Option #3
-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
-- distributed RAM for all Xilinx FPGAs
-- From library UNISIM; use UNISIM.vcomponents.all;
xilinx_16x1d:
if memory_type = "XILINX_16X" generate
signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
signal data_out2A, data_out2B : std_logic_vector(31 downto 0);
signal weA, weB : std_logic;
begin
weA <= write_enable and not addr_write(4); --lower 16 registers
weB <= write_enable and addr_write(4); --upper 16 registers
reg_loop: for i in 0 to 31 generate
begin
--Read port 1 lower 16 registers
reg_bit1a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1A(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 1 upper 16 registers
reg_bit1b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1B(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 2 lower 16 registers
reg_bit2a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2A(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
--Read port 2 upper 16 registers
reg_bit2b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2B(i), -- Port B 1-bit data output
SPO => open -- Port A 1-bit data output
);
end generate; --reg_loop
data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;
data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
end generate; --xilinx_16x1d
end; --architecture ram_block
|
mit
|
5d0320360d9c5572a10d540cfb097352
| 0.532665 | 3.562828 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd
| 4 | 3,613 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_opamp_2pole is
end tb_opamp_2pole;
architecture TB_opamp_2pole of tb_opamp_2pole is
-- Component declarations
-- Signal declarations
terminal in_src, op_neg2, out_opamp2 : electrical;
terminal out_opamp1, op_neg1, out_opamp3_res, op_neg3_res : electrical;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
OP1 : entity work.opamp_2pole(dot)
port map(
in_pos => electrical_ref,
in_neg => op_neg1,
output => out_opamp1
);
R1in : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => in_src,
p2 => op_neg1
);
R1F : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => op_neg1,
p2 => out_opamp1
);
Rload1 : entity work.resistor(ideal)
generic map(
res => 1.0e3
)
port map(
p1 => out_opamp1,
p2 => electrical_ref
);
OP2 : entity work.opamp_2pole(ltf)
port map(
in_pos => electrical_ref,
in_neg => op_neg2,
output => out_opamp2
);
R2in : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => in_src,
p2 => op_neg2
);
R2F : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => op_neg2,
p2 => out_opamp2
);
Rload2 : entity work.resistor(ideal)
generic map(
res => 1.0e3
)
port map(
p1 => out_opamp2,
p2 => electrical_ref
);
OP3R : entity work.opamp_2pole_res(ltf)
port map(
in_pos => electrical_ref,
in_neg => op_neg3_res,
output => out_opamp3_res
);
Rin3R : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => in_src,
p2 => op_neg3_res
);
R3F : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => op_neg3_res,
p2 => out_opamp3_res
);
Rload3R : entity work.resistor(ideal)
generic map(
res => 1.0e3
)
port map(
p1 => out_opamp3_res,
p2 => electrical_ref
);
end TB_opamp_2pole;
|
gpl-2.0
|
38ca3dae79dc730509434af1a36f0a13
| 0.532798 | 3.709446 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_03.vhd
| 4 | 1,914 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_03.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_03 is
end entity ch_07_03;
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture test of ch_07_03 is
constant T_delay_adder : delay_length := 10 ns;
-- code from book:
function bv_add ( bv1, bv2 : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bv1 + bv2;
-- end not in book
end function bv_add;
signal source1, source2, sum : bit_vector(0 to 31);
-- end of code from book
begin
-- code from book:
adder : sum <= bv_add(source1, source2) after T_delay_adder;
-- end of code from book
stimulus : process is
begin
wait for 50 ns;
source1 <= X"00000002"; source2 <= X"00000003"; wait for 50 ns;
source2 <= X"FFFFFFF0"; wait for 50 ns;
source1 <= X"00000010"; wait for 50 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
9500f71786707c49c8353318b5f1dae7
| 0.621735 | 3.797619 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxt.vhd
| 4 | 2,024 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxt.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package dlx_types is
-- little-endian addresses
subtype dlx_address is std_logic_vector(31 downto 0);
subtype dlx_bv_address is bit_vector(31 downto 0);
-- big-endian data words
subtype dlx_word is std_logic_vector(0 to 31);
subtype dlx_bv_word is bit_vector(0 to 31);
type dlx_word_array is array (natural range <>) of dlx_word;
-- tristate bus driving value
constant disabled_dlx_word : dlx_word := ( others => 'Z' );
-- type for specifying data width on the data bus
subtype dlx_mem_width is std_logic_vector(1 downto 0);
constant dlx_mem_width_byte : dlx_mem_width := "01";
constant dlx_mem_width_halfword : dlx_mem_width := "10";
constant dlx_mem_width_word : dlx_mem_width := "00";
-- type for controlling trace information generated by model
type dlx_debug_control is
( none,
msg_every_100_instructions, msg_each_instruction,
trace_each_instruction, trace_each_step );
end package dlx_types;
|
gpl-2.0
|
43196c3f76ceca4636ce9939766eafdd
| 0.660573 | 3.862595 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1721.vhd
| 4 | 1,955 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1721.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b01x00p01n02i01721ent IS
END c12s06b01x00p01n02i01721ent;
ARCHITECTURE c12s06b01x00p01n02i01721arch OF c12s06b01x00p01n02i01721ent IS
-- Global signals.
SIGNAL B : BIT := '1';
BEGIN
-- If one driver created, it will take on the indicated value.
TESTING: PROCESS
BEGIN
B <= '0' after 10 ns;
B <= '1' after 10 ns;
B <= '0' after 10 ns;
wait on B;
assert NOT( B='0' )
report "***PASSED TEST: c12s06b01x00p01n02i01721"
severity NOTE;
assert ( B='0' )
report "***FAILED TEST: c12s06b01x00p01n02i01721 - At least one driver gets created for eah signal which is assigned to either directly or indirectly inside of a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b01x00p01n02i01721arch;
|
gpl-2.0
|
9ba87d8347ed89fe00b9ef5ed72c7efe
| 0.662404 | 3.688679 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/bug18361/cnt.vhdl
| 3 | 1,771 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CNT_V is
Generic(clk_divisor: natural);
Port(clk : in std_logic;
reset : in std_logic;
q_o : out std_logic);
end CNT_V;
architecture behv of CNT_V is
--components
--constants
--signals
signal q: std_logic;
begin
q_o <= q;
count: process(clk, reset) is
--variable
variable idx: natural range 0 to clk_divisor-1;
begin
if reset = '1' then
idx:= 0;
q <= '0';
elsif rising_edge(clk) then
if idx = clk_divisor - 1 then
q <= '1';
idx := 0;
else
q <= '0';
idx := idx + 1;
end if;
end if;
end process;
end behv;
-- Testbench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cnt_v_tb is
end cnt_v_tb;
architecture TB of cnt_v_tb is
component CNT_V is
Generic(clk_divisor: natural);
Port(clk : in std_logic;
reset : in std_logic;
q_o : out std_logic);
end component;
--components
--constants
--signals
signal clk : std_logic;
signal reset : std_logic;
signal q_o : std_logic;
begin
DUV: cnt_v
--generic map(clk_divisor => 10) -- here ist the error
port map( clk, reset, q_o);
--stimuli here
--Stimuli for Signal "clk" 40 mhz
process
begin
clk <= '1';
wait for 12.5 ns;
clk <= '0';
wait for 12.5 ns;
end process;
process
begin
--initialisation
reset <= '1';
wait for 20 ns;
--stimuli
reset <= '0';
wait for 22 ns;
-- do some stuff
wait;
end process;
end TB;
|
gpl-2.0
|
42576236de495326432c6fa68839460e
| 0.523433 | 3.445525 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2165.vhd
| 4 | 2,047 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2165.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02165ent IS
END c07s02b04x00p22n01i02165ent;
ARCHITECTURE c07s02b04x00p22n01i02165arch OF c07s02b04x00p22n01i02165ent IS
TYPE time_v is array (integer range <>) of time;
SUBTYPE time_2 is time_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : time_2;
variable l_operand : time := 78 ns ;
variable r_operand : time := 23 ns ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result = ( 78 ns, 23 ns ))
report "***PASSED TEST: c07s02b04x00p22n01i02165"
severity NOTE;
assert (result = ( 78 ns, 23 ns ))
report "***FAILED TEST: c07s02b04x00p22n01i02165 - Concatenation of element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02165arch;
|
gpl-2.0
|
cb17c052aefcabb28823ffdd90d4076d
| 0.660967 | 3.648841 | false | true | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/game/wtr_ctrl.vhd
| 1 | 19,022 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: WTR_CTRL
-- AUTHORS: Ondřej Dujíček <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_unsigned.ALL;
entity WTR_CTRL is
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ADR : out STD_LOGIC_VECTOR(7 downto 0) :=(others=>'0');
CELL_IN : in STD_LOGIC_VECTOR(31 downto 0);
CELL_OUT : out STD_LOGIC_VECTOR(31 downto 0) :=(others=>'0');
WE_OUT : out STD_LOGIC := '0';
RE_OUT : out STD_LOGIC := '0';
WIN_BIT : out STD_LOGIC := '0';
KNLG_next : in STD_LOGIC;
START : in STD_LOGIC;
FAIL_OUT : out STD_LOGIC
);
end WTR_CTRL;
architecture Behavioral of WTR_CTRL is
-- casovac
signal rst_clk : STD_LOGIC;
signal start2 : STD_LOGIC;
-- I/O data
signal s_cell_in : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
signal s_cell_in_next : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
signal s_cell_out : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
signal s_cell_out_next : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
-- data o trubkach
signal typ_tr : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); -- typ trubky
signal rot_tr : STD_LOGIC_VECTOR(1 downto 0) := (others=>'0'); -- natoèení trubky
signal r,l,up,down : STD_LOGIC := '0';
signal bit_check : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal bit_check_next : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal cesta_vody : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
signal cesta_vody_next : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
-- adresy
signal adr_x_next : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
signal adr_y_next : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
signal adr_x : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
signal adr_y : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
signal s_adr : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
signal now_addr : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); -- adresa aktualni bunky, pouziva se ke cteni a zapisu
signal now_addr_next : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); -- adresa aktualni bunky, pouziva se ke cteni a zapisu
signal adr_xn_1_next : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_yn_1_next : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_xn_1 : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_yn_1 : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_xn_2_next : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_yn_2_next : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_xn_2 : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_yn_2 : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
-- win, lose signaly
signal fail_bit_next : STD_LOGIC := '0';
signal WIN_BIT_next : STD_LOGIC := '0';
-- ostatni signaly
signal tmp1 : STD_LOGIC_VECTOR(4 downto 0) := (others=>'0'); --- counter na trubky
signal tmp1_next : STD_LOGIC_VECTOR(4 downto 0) := (others=>'0'); --- counter na trubky
signal knlg : STD_LOGIC;
type state_type0 is (m1,m2,m3,m4,m5,m6,m0,m7,m8,m9,m10,m11,m12,m13,m16,m17,m18,m19); -- mody prace s bunkou
signal next_state, present_state : state_type0 := m0; -- vnitrni signaly typu state
-- konstanty
constant clock_defi : STD_LOGIC_VECTOR(25 downto 0) := "00001101111111011110000100"; -- cim vetsi tim pomalejsi
begin
-- zapojeni podkomponenty
-- casovani 10 - 14 to je 5 bit 00001 voda ma tect 00011 voda tece a je v prvnim policku casovac na 0.2s az 0.5s
wtr_clk_unit : entity work.WTR_CLK
generic map (
Flip_flops => 26 -- odpovída nastavenemu clock defi
)
port map (
CLK => CLK,
RST => rst_clk,
CLOCK_DEFI => clock_defi, -- nastavuje hodnotu casovace
ENABLE_OUT => start2
);
-- rozdeleni ulozenych dat
up <= s_cell_in(6);
r <= s_cell_in(7);
down <= s_cell_in(8);
l <= s_cell_in(9);
typ_tr <= s_cell_in(3 downto 0);
rot_tr <= s_cell_in(5 downto 4);
s_adr <= std_logic_vector(unsigned(adr_y) & unsigned(adr_x));
ADR <= now_addr;
CELL_OUT <= s_cell_out_next;
WIN_BIT <= win_bit_next;
FAIL_OUT <= fail_bit_next;
-----------------------------------------------------------------------------------------------------
-- STAVOVY AUTOMAT - THE DUJDA SYSTEM
-----------------------------------------------------------------------------------------------------
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then -- synchronni reset
present_state <= m0;
now_addr <= (others=>'0');
s_cell_out <= (others=>'0');
s_cell_in <= (others=>'0');
tmp1 <= (others=>'0');
bit_check <= (others=>'0');
adr_xn_1 <= (others=>'0');
adr_yn_1 <= (others=>'0');
adr_xn_2 <= (others=>'0');
adr_yn_2 <= (others=>'0');
adr_x <= (others=>'0');
adr_y <= (others=>'0');
knlg <= '0';
cesta_vody <= (others=>'0');
else
present_state <= next_state;
now_addr <= now_addr_next;
s_cell_out <= s_cell_out_next;
s_cell_in <= s_cell_in_next;
tmp1 <= tmp1_next;
bit_check <= bit_check_next;
adr_xn_1 <= adr_xn_1_next;
adr_yn_1 <= adr_yn_1_next;
adr_xn_2 <= adr_xn_2_next;
adr_yn_2 <= adr_yn_2_next;
adr_x <= adr_x_next;
adr_y <= adr_y_next;
knlg <= knlg_next;
cesta_vody <= cesta_vody_next;
end if;
end if;
end process;
process(present_state,up,l,r,down,start,adr_x,adr_y,typ_tr,rot_tr, adr_xn_1, adr_yn_1, bit_check,
KNLG_next, knlg, s_adr, start2, tmp1, s_cell_in, s_cell_out, now_addr, CELL_IN, cesta_vody, adr_xn_2, adr_yn_2)
begin
bit_check_next <= bit_check;
adr_xn_1_next <= adr_xn_1;
adr_yn_1_next <= adr_yn_1;
adr_xn_2_next <= adr_xn_2;
adr_yn_2_next <= adr_yn_2;
adr_x_next <= adr_x;
adr_y_next <= adr_y;
now_addr_next <= now_addr;
s_cell_out_next <= s_cell_out;
s_cell_in_next <= s_cell_in;
tmp1_next <= tmp1;
rst_clk <= '0';
cesta_vody_next <= cesta_vody;
case present_state is
-- startovni stav
when m0=>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
adr_x_next <= (others=>'0');
adr_y_next <= (others=>'0');
now_addr_next <= (others=>'0'); -- nastaveni adresy startovniho policka
if (start = '1') then
next_state<= m1;
else
next_state<= m0;
end if;
------------------------------------------------------------
-- cteni dat o aktualni bunce
when m1 =>
fail_bit_next <= '0';
win_bit_next <= '0';
WE_OUT <= '0';
if (knlg = '1') then
RE_OUT <= '0';
s_cell_in_next <= CELL_IN;
next_state <= m17;
else
RE_OUT <= '1';
next_state <= m1;
end if;
------------------------------------------------------------
-- kontrola zdali jsme na startovnim policku
when m17 =>
RE_OUT <= '0';
WE_OUT <= '0';
fail_bit_next <= '0';
win_bit_next <= '0';
s_cell_out_next <= s_cell_in;
if (s_adr = "00000000") then
next_state <= m8;
else
next_state <= m16;
end if;
------------------------------------------------------------
-- kontrola jestli je spravne zapojena prvni trubka
when m8 =>
RE_OUT <= '0';
WE_OUT <= '0';
fail_bit_next <= '0';
win_bit_next <= '0';
if (l='1') then -- kontrola pripojení první trubky
next_state<= m2;
else
next_state<= m3;
end if;
------------------------------------------------------------
-- kontrola pripojeni druhe trubky
when m16=>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
case bit_check is
when "00" =>
if (l='1') then
next_state <= m2;
else
next_state <= m3;
end if;
when "01" =>
if (r='1') then
next_state <= m2;
else
next_state <= m3;
end if;
when "10" =>
if (down='1') then
next_state <= m2;
else
next_state <= m3;
end if;
when "11" =>
if (up='1') then
next_state <= m2;
else
next_state <= m3;
end if;
when others =>
next_state <= m3;
end case;
------------------------------------------------------------
-- zjisteni typu trubky
when m2=>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
case typ_tr is
when "0000" =>
next_state <= m3; -- prazdne pole
when "0010" =>
next_state <= m4; -- trubka L-ko
when "0001" =>
next_state <= m5; -- rovna trubka
when "0011" =>
next_state <= m6; -- krizova trubka
when others =>
next_state <= m3; -- zed nebo jine
end case;
------------------------------------------------------------
-- trubka L, zjistovani natoceni
when m4 =>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
case rot_tr is
when "10" => -- L = z hora do prava
if (adr_yn_1<adr_y) then
next_state<= m10; -- doprava
cesta_vody_next <= "1011"; -- zhora doprava
else
next_state<= m12; -- nahoru
cesta_vody_next <= "0111"; -- zprava nahoru
end if;
when "11" => -- P z prava dolu
if (adr_yn_1>adr_y) then
next_state<= m10; -- doprava
cesta_vody_next <= "1001"; -- zdola doprava
else
next_state<= m13; -- dolu
cesta_vody_next <= "1000"; -- zprava dolu
end if;
when "00" => -- 7 z dola do leva + osetreny prvni stav
if (adr_yn_1>adr_y) then
next_state<= m11; -- doleva
cesta_vody_next <= "1010"; -- zdola doleva
else
next_state<= m13; -- dolu
cesta_vody_next <= "0110"; -- zleva dolu
end if;
when "01" => -- d z leva nahoru
if (adr_yn_1<adr_y) then
next_state<= m11; -- doleva
cesta_vody_next <= "1100"; -- zhora doleva
else
next_state<= m12; -- nahoru
cesta_vody_next <= "0101"; -- zleva nahoru
end if;
when others => -- kdyby se neco posralo
next_state <= m3;
end case;
------------------------------------------------------------
-- rovna trubka, zjistovani natoceni
when m5 =>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
case rot_tr is
when "00" =>
if (adr_xn_1>adr_x) then
next_state<= m11; -- doleva
cesta_vody_next <= "0010";
else
next_state<= m10; -- doprava
cesta_vody_next <= "0001";
end if;
when "01" =>
if (adr_yn_1<adr_y) then
next_state<= m13; -- dolu
cesta_vody_next <= "0100";
else
next_state<= m12; -- nahoru
cesta_vody_next <= "0011";
end if;
when others =>
next_state <= m3;
end case;
------------------------------------------------------------
-- krizova trubka, zjistovani natoceni
when m6 =>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
if (adr_xn_1<adr_x) then
next_state<= m10; -- tece doprava
cesta_vody_next <= "0001";
elsif (adr_xn_1>adr_x) then
next_state<= m11; -- tece doleva
cesta_vody_next <= "0010";
elsif (adr_yn_1<adr_y) then
next_state<= m13; -- tece dolu
cesta_vody_next <= "0100";
elsif (adr_yn_1>adr_y) then
next_state<= m12; -- tece nahoru
cesta_vody_next <= "0011";
elsif (s_adr="00000000") then
next_state<=m10; -- tece doprava
cesta_vody_next <= "0001";
else
next_state<=m3;
end if;
------------------------------------------------------------
-- voda potece doprava
when m10 => --- ptam se do prava
adr_x_next<= std_logic_vector(unsigned(adr_x) + 1);
bit_check_next<="00";
adr_xn_1_next <= adr_x;
adr_yn_1_next <= adr_y;
adr_xn_2_next <= adr_xn_1;
adr_yn_2_next <= adr_yn_1;
next_state<= m18;
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
rst_clk<='1';
------------------------------------------------------------
-- voda potece doleva
when m11 => --- ptam se do leva
adr_x_next<= std_logic_vector(unsigned(adr_x) - 1);
bit_check_next<="01";
adr_xn_1_next <= adr_x;
adr_yn_1_next <= adr_y;
adr_xn_2_next <= adr_xn_1;
adr_yn_2_next <= adr_yn_1;
next_state<= m18;
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
rst_clk<='1';
------------------------------------------------------------
-- voda potece nahoru
when m12 => --- ptam se nahoru
adr_y_next<= std_logic_vector(unsigned(adr_y) - 1);
bit_check_next<="10";
adr_xn_1_next <= adr_x;
adr_yn_1_next <= adr_y;
adr_xn_2_next <= adr_xn_1;
adr_yn_2_next <= adr_yn_1;
next_state<= m18;
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
rst_clk<='1';
------------------------------------------------------------
-- voda potece dolu
when m13 => --- ptam se dolu
adr_y_next<= std_logic_vector(unsigned(adr_y) + 1);
bit_check_next<="11";
adr_xn_1_next <= adr_x;
adr_yn_1_next <= adr_y;
adr_xn_2_next <= adr_xn_1;
adr_yn_2_next <= adr_yn_1;
next_state<= m18;
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
rst_clk<='1';
------------------------------------------------------------
-- kontrola jestli voda prosla celou trubkou
when m18=>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
if (start2='1') then
if (tmp1="11111") then
--tmp1_next <= "00000";
next_state <= m7;
--now_addr_next <= s_adr; -- nastaveni adresy noveho policka
else
tmp1_next<=std_logic_vector(unsigned(tmp1)+1);
next_state<=m19;
end if;
else
next_state <= m18;
end if;
------------------------------------------------------------
-- zapis vody, zapne casovani a pricte vodu
when m19=>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '1';
WE_OUT <= '1';
if ((cesta_vody = "0011") OR (cesta_vody = "0100")) then
s_cell_out_next(15 downto 10) <= s_cell_in(15 downto 10);
s_cell_out_next(21 downto 16) <= tmp1 & '1';
s_cell_out_next(25 downto 22) <= s_cell_in(25 downto 22);
s_cell_out_next(29 downto 26) <= cesta_vody;
else
s_cell_out_next(15 downto 10) <= tmp1 & '1';
s_cell_out_next(21 downto 16) <= s_cell_in(21 downto 16);
s_cell_out_next(25 downto 22) <= cesta_vody;
s_cell_out_next(29 downto 26) <= s_cell_in(29 downto 26);
end if;
if (KNLG_next = '1') then
next_state <= m18;
else
next_state <= m19;
end if;
------------------------------------------------------------
-- kontrola jestli trubka neni zapojena do cile nebo do zdi
when m7 =>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
tmp1_next <= "00000";
now_addr_next <= s_adr; -- nastaveni adresy noveho policka
if ((adr_yn_1="0000")and (up='1') and (typ_tr/="0011")) then
next_state<=m3;
elsif((adr_yn_1="1100")and (down='1')and (typ_tr/="0011")) then
next_state<=m3;
elsif((adr_xn_1="1101")and (r='1') and (adr_yn_1/="1100")and (typ_tr/="0011")) then
next_state<=m3;
elsif((adr_xn_1="1101")and (r='1') and (adr_yn_1="1100") and (typ_tr/="0011")) then -- win
next_state<=m9;
elsif((adr_xn_1="0000")and (l='1')and(adr_yn_1/="0000") and (typ_tr/="0011")) then
next_state<=m3;
-- krizova --- fix
elsif (typ_tr="0011") then
if (adr_xn_2<adr_xn_1) then
if ((adr_xn_1="1101") and (adr_yn_1/="1100")) then
next_state <= m3;
elsif ((adr_xn_1="1101") and (adr_yn_1="1100")) then
next_state <= m9;
else
next_state<=m1;
end if;
elsif ((adr_xn_2>adr_xn_1) and (adr_xn_1="0000")) then
next_state<= m3;
elsif ((adr_yn_2<adr_yn_1) and (adr_yn_1="1100")) then
next_state<= m3;
elsif ((adr_yn_2>adr_yn_1) and (adr_yn_1="0000")) then
next_state<= m3;
else
next_state<=m1;
end if;
else
next_state<=m1;
end if;
------------------------------------------------------------
-- Prohra
when m3 =>
fail_bit_next <= '1';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
next_state<=m3;
------------------------------------------------------------
-- Vyhra
when m9 =>
fail_bit_next <= '0';
win_bit_next <= '1';
RE_OUT <= '0';
WE_OUT <= '0';
next_state <= m9;
------------------------------------------------------------
-- ostatni stavy
when others =>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
next_state <= m0;
end case;
end process;
end Behavioral;
|
mit
|
1d8456eaff1d31fb00699726d8268147
| 0.453679 | 3.278343 | false | false | false | false |
mmoraless/ecc_vhdl
|
ecc_add/NewECCADD_113.vhd
| 1 | 6,089 |
------------------------------------------------------------------------
--Nueva implementacion ADD y Double en una misma arquitectura
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity ECC_add_serial_113 is
generic(
-- 163, 233, 277, 283, 409, 571
NUM_BITS : positive := 113
);
port(
xP: in std_logic_vector(NUM_BITS-1 downto 0);
yP: in std_logic_vector(NUM_BITS-1 downto 0);
xQ: in std_logic_vector(NUM_BITS-1 downto 0);
yQ: in std_logic_vector(NUM_BITS-1 downto 0);
---------------------------------------------
clk: in std_logic;
rst: in std_logic;
s0: in std_logic; -- 1 = Suma, 0 = Double
---------------------------------------------
X: out std_logic_vector(NUM_BITS-1 downto 0);
Y: out std_logic_vector(NUM_BITS-1 downto 0);
done: out std_logic
);
end;
------------------------------------------------------
architecture behave of ECC_add_serial_113 is
type CurrentState_type is (END_STATE, CHECK_INPUT, SPEND_CYCLE1, SPEND_CYCLE2,CALC_INV, CALC_MUL);
signal CurrentState : CurrentState_type;
constant cero : std_logic_vector(NUM_BITS-1 downto 0):= (others => '0');
--
signal S1 : std_logic_vector(NUM_BITS-1 downto 0);
signal not_s0 : std_logic;
-- 4 multiplexores
signal L3 : std_logic_vector(NUM_BITS-1 downto 0);
signal SQRin : std_logic_vector(NUM_BITS-1 downto 0);
signal Div1 : std_logic_vector(NUM_BITS-1 downto 0);
signal Div2 : std_logic_vector(NUM_BITS-1 downto 0);
--- interface con el inversor
signal rstInv : std_logic;
signal Division : std_logic_vector(NUM_BITS-1 downto 0);
signal doneInv : std_logic;
--- interface del multiplicador
signal rstMul : std_logic;
signal Multiplication : std_logic_vector(NUM_BITS-1 downto 0);
signal doneMul : std_logic;
--- interface del squarer
signal SQR : std_logic_vector(NUM_BITS-1 downto 0);
---------------------------------------------------------------
begin
---------------------------------------------------------------
-- Componentes
---------------------------------------------------------------
SQUARER_1 : entity squarer_113(behave)
--generic map (D, NUM2_BITS, NUM_BITS)
generic map (NUM_BITS)
port map(SQRin, SQR);
---------------------------------------------------------------
MUL_1: entity serial_multiplier_113(behave)
generic map (NUM_BITS)
port map(S1, SQRin, Multiplication,rstMul,clk,doneMul);
---------------------------------------------------------------
INV_1: entity f2m_divider_113(behave)
generic map (NUM_BITS)
port map(Div1, Div2, clk, rstInv, doneInv, Division);
---------------------------------------------------------------
---------------------------------------------------------------
LUT31: entity lut_3in(behave)
generic map (NUM_BITS)
port map(yQ, s0, yP, Div1);
---------------------------------------------------------------
---------------------------------------------------------------
LUT32: entity lut_3in(behave)
generic map (NUM_BITS)
port map(xQ, s0, xP, Div2);
---------------------------------------------------------------
---------------------------------------------------------------
LUT33: entity lut_3in(behave)
generic map (NUM_BITS)
port map(xP, not_s0, Division,SQRin);
---------------------------------------------------------------
---------------------------------------------------------------
LUT41: entity lut_3inadd(behave)
generic map (NUM_BITS)
port map(SQR, Division, Div2, L3);
---------------------------------------------------------------
-- Operaciones combinacionales (Sumas)
S1 <= L3 xor xP;
not_s0 <= not s0;
---------------------------------------------------------------
ADD_FSM: process (CLK)
Begin
if CLK'event and CLK = '1' then
-- Los datos de entrada deben estar presentes al llegar la señal de reset,
-- Si la señal Rst de entrada es síncrona con un reloj (i.e. es proporcionada
-- por un control en la subida del reloj), los datos a la entrada deben asignarse
-- junto con la señal de Rst o al momento de que Rst regrese a '0'
if Rst = '1' then
CurrentState <= CHECK_INPUT;
Done <= '0';
X <= (others =>'0');
Y <= (others =>'0');
rstInv <= '0';
rstMul <= '0';
else
case CurrentState is
when CHECK_INPUT =>
if (xP = cero) and (yP = cero) and s0 = '1' then -- add
X <= xQ;
Y <= yQ;
Done <= '1';
CurrentState <= END_STATE;
elsif (xQ = cero) and (yQ = cero) and s0 = '1' then -- Add
X <= xP;
Y <= yP;
Done <= '1';
CurrentState <= END_STATE;
elsif (xP = cero) and s0 = '0' then -- Double
Done <= '1';
CurrentState <= END_STATE;
else
rstInv <= '1'; -- calcular la division primero.
CurrentState <= SPEND_CYCLE1;
end if;
when SPEND_CYCLE1 => -- Provoca el pulso RST al modulo de inversion.
rstInv <= '0';
CurrentState <= CALC_INV;
when CALC_INV => -- Una vez que termina de calcular la division,
if doneInv = '1' then -- comienza con la multiplicación.
X <= L3;
rstMul <= '1';
CurrentState <= SPEND_CYCLE2;
end if;
when SPEND_CYCLE2 => -- Provoca el pulso RST en el multiplicador
rstMul <= '0';
CurrentState <= CALC_MUL;
when CALC_MUL => -- Espera que el multiplicador termine
if doneMul = '1' then
Y <= Multiplication xor L3 xor yP;
Done <= '1';
CurrentState <= END_STATE; -- Operación ADD terminada
end if;
when END_STATE =>
CurrentState <= END_STATE;
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
3645d22ac05ded9f34ee61e02388f824
| 0.46855 | 3.784338 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_06.vhd
| 4 | 2,210 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_06.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_06 is
end entity fg_a_06;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_06 is
-- code from book
constant terminal_count : integer := 2**6 - 1;
subtype counter_range is integer range 0 to terminal_count;
signal count : counter_range;
-- . . .
-- end code from book
signal clk, reset : std_ulogic;
begin
-- code from book
counter6 : process (reset, clk)
begin
if reset = '0' then
count <= 0;
elsif rising_edge(clk) then
if count < terminal_count then
count <= count + 1;
else
count <= 0;
end if;
end if;
end process counter6;
-- end code from book
stimulus : process is
begin
reset <= '1'; clk <= '0'; wait for 10 ns;
clk <= '1', '0' after 10 ns; wait for 20 ns;
clk <= '1', '0' after 10 ns; wait for 20 ns;
clk <= '1', '0' after 10 ns; wait for 20 ns;
reset <= '0', '1' after 30 ns;
clk <= '1' after 10 ns, '0' after 20 ns;
wait for 40 ns;
for i in 1 to terminal_count + 10 loop
clk <= '1', '0' after 10 ns;
wait for 20 ns;
end loop;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
b3e6cd5a66c54302be9ea559b62096bc
| 0.597738 | 3.640857 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_01.vhd
| 4 | 1,823 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_fg_04_01.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- not in book:
library ch4_pkgs;
use ch4_pkgs.pk_04_01.all;
-- end not in book
entity coeff_ram is
port ( rd, wr : in bit; addr : in coeff_ram_address;
d_in : in real; d_out : out real );
end entity coeff_ram;
--------------------------------------------------
architecture abstract of coeff_ram is
begin
memory : process is
type coeff_array is array (coeff_ram_address) of real;
variable coeff : coeff_array;
begin
for index in coeff_ram_address loop
coeff(index) := 0.0;
end loop;
loop
wait on rd, wr, addr, d_in;
if rd = '1' then
d_out <= coeff(addr);
end if;
if wr = '1' then
coeff(addr) := d_in;
end if;
end loop;
end process memory;
end architecture abstract;
|
gpl-2.0
|
42ae4216553eb4c20d79ac9c25c3cb55
| 0.586945 | 3.886994 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3204.vhd
| 4 | 2,184 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3204.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library STD;
use STD.TEXTIO.all;
ENTITY c14s03b00x00p59n01i03204ent IS
END c14s03b00x00p59n01i03204ent;
ARCHITECTURE c14s03b00x00p59n01i03204arch OF c14s03b00x00p59n01i03204ent IS
BEGIN
TESTING: PROCESS
file F_out : Text open write_mode is "iofile.47";
variable L_out : Line;
type TA is array (INTEGER range <>) of TIME;
constant A : TA := (-1 fs, 37582 ns, 1 ms + 1 ns + 1 ps);
BEGIN
for i in A'RANGE loop
Write(L_out, A(i), UNIT=>fs, FIELD=>25);
WriteLine(F_out, L_out);
Write(L_out, A(i), UNIT=>ps, FIELD=>25);
WriteLine(F_out, L_out);
Write(L_out, A(i), UNIT=>ns, FIELD=>25);
WriteLine(F_out, L_out);
WriteLine(F_out, L_out);
end loop;
wait for 10 fs;
assert FALSE
report "***PASSED TEST: c14s03b00x00p59n01i03204 - This test will output an output file, and that file will be compared with s010401.ref file."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p59n01i03204arch;
|
gpl-2.0
|
4faace934541f8c95ec3deda7da06d13
| 0.645147 | 3.472178 | false | true | false | false |
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