repo_name
stringlengths 6
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stringlengths 6
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int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
123gmax/Digital-Lab
|
AES128/Architecture1_Pipeline/AES128_V1_tb.vhd
| 1 | 3,164 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/29/2015 10:58:56 AM
-- Design Name:
-- Module Name: AES128_V1_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity AES128_V1_tb is
end AES128_V1_tb;
architecture Behavioral of AES128_V1_tb is
component AES128_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
READY_TO_DECRYPT : out STD_LOGIC;
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end component;
constant clk_period : time := 2ns;
signal CLK, RESET, ENABLE, READY_TO_DECRYPT : STD_LOGIC := '0';
signal WORD_IN, WORD_OUT : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
uut: AES128_V1 port map( CLK => CLK,
RESET => RESET,
ENABLE => ENABLE,
READY_TO_DECRYPT => READY_TO_DECRYPT,
WORD_IN => WORD_IN,
WORD_OUT => WORD_OUT);
clk_process: process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process;
--Source http://kavaliro.com/wp-content/uploads/2014/03/AES.pdf
stim_process: process
variable I : natural range 0 to 100 := 0;
begin
I := 0;
RESET <= '0';
ENABLE <= '1';
WORD_IN <= x"54686174";
wait for clk_period;
WORD_IN <= x"73206D79";
wait for clk_period;
WORD_IN <= x"204B756E";
wait for clk_period;
WORD_IN <= x"67204675";
while READY_TO_DECRYPT = '0' loop
wait for clk_period;
end loop;
WORD_IN <= x"29C3505F";
wait for clk_period;
WORD_IN <= x"571420F6";
wait for clk_period;
WORD_IN <= x"402299B3";
wait for clk_period;
WORD_IN <= x"1A02D73A";
wait for clk_period;
--It takes 69 clock cycles for the first decrypted word to exit the pipe.
--For this test bench, the first valid word output occurs at the rising edge at 427ns.
WORD_IN <= x"00000000";
wait for 10*clk_period;
WORD_IN <= x"00000001";
wait for 10*clk_period;
WORD_IN <= x"00000002";
wait for 10*clk_period;
WORD_IN <= x"00000003";
wait for 10*clk_period;
WORD_IN <= x"00000004";
wait for 10*clk_period;
WORD_IN <= x"00000005";
wait for 10*clk_period;
WORD_IN <= x"00000006";
wait for 10*clk_period;
WORD_IN <= x"00000007";
wait for 10*clk_period;
end process;
end Behavioral;
|
gpl-2.0
|
1e8dcff90797a86d00d33098058b9d72
| 0.498104 | 3.798319 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_01.vhd
| 4 | 2,311 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_07_01 is
end entity ch_07_01;
----------------------------------------------------------------
architecture test of ch_07_01 is
begin
process_07_2_a : process is
type t1 is (t1_1, t1_2);
type t2 is (t2_1, t2_2);
type t3 is (t3_1, t3_2);
type t4 is (t4_1, t4_2);
constant v4 : t4 := t4_1;
constant val1 : t1 := t1_1;
constant val2 : t2 := t2_1;
variable var3 : t3 := t3_1;
constant val4 : t4 := t4_1;
-- code from book:
procedure p ( f1 : in t1; f2 : in t2; f3 : out t3; f4 : in t4 := v4 ) is
begin
-- . . .
end procedure p;
-- end of code from book
begin
-- code from book:
p ( val1, val2, var3, val4 );
p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 );
p ( val1, val2, f4 => open, f3 => var3 );
p ( val1, val2, var3 );
-- end of code from book
wait;
end process process_07_2_a;
end architecture test;
|
gpl-2.0
|
f290bb7c9e719cd8489ae80b99567495
| 0.475119 | 3.936968 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/access-types/ordered_collection_adt.vhd
| 4 | 6,074 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package «element_type_simple_name»_ordered_collection_adt is
-- template: fill in the placeholders to specialize for a particular type
alias element_type is «element_type»;
alias key_type is «key_type»;
alias key_of is «key_function» [ element_type return key_type ];
alias "<" is «less_than_function» [ key_type, key_type return boolean ];
-- types provided by the package
type ordered_collection_object; -- private
type position_object; -- private
type ordered_collection is access ordered_collection_object;
type position is access position_object;
-- operations on ordered collections
function new_ordered_collection return ordered_collection;
-- returns an empty ordered collection of element_type values
procedure insert ( c : inout ordered_collection; e : in element_type );
-- inserts e into c in position determined by key_of(e)
procedure get_element ( variable p : in position; e : out element_type );
-- returns the element value at position p in its collection
procedure test_null_position ( variable p : in position; is_null : out boolean );
-- test whether p refers to no position in its collection
procedure search ( variable c : in ordered_collection; k : in key_type;
p : out position );
-- searches for an element with key k in c, and returns the position of
-- that element, or, if not found, a position for which test_null_position
-- returns true
procedure find_first ( variable c : in ordered_collection; p : out position );
-- returns the position of the first element of c
procedure advance ( p : inout position );
-- advances p to the next element in its collection,
-- or if there are no more, sets p so that test_null_position returns true
procedure delete ( p : inout position );
-- deletes the element at position p from its collection, and advances p
-- private types: pretend these are not visible
type ordered_collection_object is
record
element : element_type;
next_element, prev_element : ordered_collection;
end record ordered_collection_object;
type position_object is
record
the_collection : ordered_collection;
current_element : ordered_collection;
end record position_object;
end package «element_type_simple_name»_ordered_collection_adt;
package body «element_type_simple_name»_ordered_collection_adt is
function new_ordered_collection return ordered_collection is
variable result : ordered_collection := new ordered_collection_object;
begin
result.next_element := result;
result.prev_element := result;
return result;
end function new_ordered_collection;
procedure insert ( c : inout ordered_collection; e : in element_type ) is
variable current_element : ordered_collection := c.next_element;
variable new_element : ordered_collection;
begin
while current_element /= c
and key_of(current_element.element) < key_of(e) loop
current_element := current_element.next_element;
end loop;
-- insert new element before current_element
new_element := new ordered_collection_object'(
element => e,
next_element => current_element,
prev_element => current_element.prev_element );
new_element.next_element.prev_element := new_element;
new_element.prev_element.next_element := new_element;
end procedure insert;
procedure get_element ( variable p : in position; e : out element_type ) is
begin
e := p.current_element.element;
end procedure get_element;
procedure test_null_position ( variable p : in position; is_null : out boolean ) is
begin
is_null := p.current_element = p.the_collection;
end procedure test_null_position;
procedure search ( variable c : in ordered_collection; k : in key_type;
p : out position ) is
variable current_element : ordered_collection := c.next_element;
begin
while current_element /= c
and key_of(current_element.element) < k loop
current_element := current_element.next_element;
end loop;
if current_element = c or k < key_of(current_element.element) then
p := new position_object'(c, c); -- null position
else
p := new position_object'(c, current_element);
end if;
end procedure search;
procedure find_first ( variable c : in ordered_collection; p : out position ) is
begin
p := new position_object'(c, c.next_element);
end procedure find_first;
procedure advance ( p : inout position ) is
variable is_null : boolean;
begin
test_null_position(p, is_null);
if not is_null then
p.current_element := p.current_element.next_element;
end if;
end procedure advance;
procedure delete ( p : inout position ) is
variable is_null : boolean;
begin
test_null_position(p, is_null);
if not is_null then
p.current_element.next_element.prev_element
:= p.current_element.prev_element;
p.current_element.prev_element.next_element
:= p.current_element.next_element;
p.current_element := p.current_element.next_element;
end if;
end procedure delete;
end package body «element_type_simple_name»_ordered_collection_adt;
|
gpl-2.0
|
047200b87cf25bd653da05c2f31c4d6d
| 0.69674 | 4.090236 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/util_pk_test.vhd
| 4 | 3,156 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: util_pk_test.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package stimulus_generators is
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length );
procedure all_possible_values ( signal bv : out std_ulogic_vector;
delay_between_values : in delay_length );
procedure all_possible_values ( signal bv : out std_logic_vector;
delay_between_values : in delay_length );
end package stimulus_generators;
package body stimulus_generators is
type digit_table is array ( natural range 0 to 1 ) of bit;
constant digit : digit_table := ( '0', '1' );
function natural_to_bv ( nat : in natural;
length : in natural ) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(0 to length - 1);
begin
for index in result'reverse_range loop
result(index) := digit( temp rem 2 );
temp := temp / 2;
end loop;
return result;
end function natural_to_bv;
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length ) is
begin
bv <= natural_to_bv(0, bv'length);
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= natural_to_bv(value, bv'length);
end loop;
end procedure all_possible_values;
procedure all_possible_values ( signal bv : out std_ulogic_vector;
delay_between_values : in delay_length ) is
begin
bv <= To_StdULogicVector(natural_to_bv(0, bv'length));
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= To_StdULogicVector(natural_to_bv(value, bv'length));
end loop;
end procedure all_possible_values;
procedure all_possible_values ( signal bv : out std_logic_vector;
delay_between_values : in delay_length ) is
begin
bv <= To_StdLogicVector(natural_to_bv(0, bv'length));
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= To_StdLogicVector(natural_to_bv(value, bv'length));
end loop;
end procedure all_possible_values;
end package body stimulus_generators;
|
gpl-2.0
|
f48ac72995fd7eec9fd8f4ab38321d01
| 0.654309 | 3.881919 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.f-Mul.core/a.b.f.0-AddSub.vhd
| 1 | 1,608 |
--------------------------------------------------------------------------------
-- FILE: BoothMul
-- DESC: Booth's Multiplier
--
-- Author:
-- Create: 2015-08-16
-- Update: 2015-08-16
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity AddSub is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
as: in std_logic; -- Add(Active High)/Sub(Active Low)
a, b: in std_logic_vector(DATA_SIZE-1 downto 0); -- Operands
re: out std_logic_vector(DATA_SIZE-1 downto 0); -- Return value
cout: out std_logic -- Carry
);
end AddSub;
--------------------------------------------------------------------------------
-- ARCHITECURE
--------------------------------------------------------------------------------
architecture add_sub_arch of AddSub is
component Adder is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
cin: in std_logic;
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
s : out std_logic_vector(DATA_SIZE-1 downto 0);
cout: out std_logic
);
end component;
signal b_new : std_logic_vector(DATA_SIZE-1 downto 0);
signal as_arr: std_logic_vector(DATA_SIZE-1 downto 0);
begin
as_arr <= (others=>as);
b_new <= b xor as_arr;
ADDER0: Adder
generic map(DATA_SIZE)
port map(as, a, b_new, re, cout);
end add_sub_arch;
|
mit
|
292d28a6e9e753d5416770ead1b86f25
| 0.458955 | 3.722222 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_10.vhd
| 4 | 1,772 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_10 is
end entity inline_10;
----------------------------------------------------------------
architecture test of inline_10 is
begin
process is
use std.textio.all;
variable L : line;
-- code from book:
type speed_category is (stopped, slow, fast, maniacal);
variable speed : speed_category;
-- end of code from book
begin
speed := stopped;
-- code from book:
write ( L, speed_category'image(speed) );
-- end of code from book
writeline(output, L);
speed := slow;
write ( L, speed_category'image(speed) );
writeline(output, L);
speed := fast;
write ( L, speed_category'image(speed) );
writeline(output, L);
speed := maniacal;
write ( L, speed_category'image(speed) );
writeline(output, L);
-- code from book:
readline( input, L );
speed := speed_category'value(L.all);
-- end of code from book
wait;
end process;
end architecture test;
|
gpl-2.0
|
1ffe9874cecbf6f0b1f0bf86be98c7f6
| 0.649549 | 4.06422 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_03.vhd
| 4 | 1,789 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
begin
process is
type natural_ptr is access natural;
-- code from book:
variable count1, count2 : natural_ptr;
-- end of code from book
begin
-- code from book:
count1 := new natural'(5);
count2 := new natural'(10);
count2 := count1;
count1.all := 20;
-- end of code from book
assert
-- code from book:
count1 = count2
-- end of code from book
;
-- code from book:
count1 := new natural'(30);
count2 := new natural'(30);
-- end of code from book
assert count1 = count2;
assert
-- code from book:
count1.all = count2.all
-- end of code from book
;
-- code from book:
if count1 /= null then
count1.all := count1.all + 1;
end if;
-- end of code from book
wait;
end process;
end architecture test;
|
gpl-2.0
|
2d8ebae95a82bc0e72dcf72597ca6da2
| 0.632197 | 4.084475 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd
| 4 | 2,121 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_12 is
end entity inline_12;
----------------------------------------------------------------
architecture test of inline_12 is
signal top_a, bottom_a : bit := '0';
signal top_y, bottom_y : bit;
begin
block_3_m : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => top_a, y => top_y );
begin
-- code from book:
inv : process (a) is
begin
y <= inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_3_m;
----------------
block_3_n : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => bottom_a, y => bottom_y);
begin
-- code from book:
inv : process (a) is
begin
y <= reject 2 ns inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_3_n;
----------------
stimulus_3_m_n : process is
begin
top_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 8 ns;
bottom_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 9 ns,
'0' after 11.5 ns,
'1' after 16 ns,
'0' after 18 ns,
'1' after 19 ns,
'0' after 20 ns;
wait;
end process stimulus_3_m_n;
end architecture test;
|
gpl-2.0
|
395fd63d3136a92dc240c98bf37173a8
| 0.564828 | 3.760638 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_09.vhd
| 4 | 2,670 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity computer_system is
end entity computer_system;
-- end not in book
architecture abstract of computer_system is
subtype word is bit_vector(31 downto 0);
signal address : natural;
signal read_data, write_data : word;
signal mem_read, mem_write : bit := '0';
signal mem_ready : bit := '0';
begin
cpu : process is
variable instr_reg : word;
variable PC : natural;
-- . . . -- other declarations
begin
loop
address <= PC;
mem_read <= '1';
wait until mem_ready = '1';
instr_reg := read_data;
mem_read <= '0';
wait until mem_ready = '0';
PC := PC + 4;
-- . . . -- execute the instruction
end loop;
end process cpu;
memory : process is
type memory_array is array (0 to 2**14 - 1) of word;
variable store : memory_array := (
-- . . .
-- not in book
0 => X"0000_0000",
1 => X"0000_0004",
2 => X"0000_0008",
3 => X"0000_000C",
4 => X"0000_0010",
5 => X"0000_0014",
others => X"0000_0000"
-- end not in book
);
begin
wait until mem_read = '1' or mem_write = '1';
if mem_read = '1' then
read_data <= store( address / 4 );
mem_ready <= '1';
wait until mem_read = '0';
mem_ready <= '0';
else
-- . . . -- perform write access
end if;
end process memory;
end architecture abstract;
|
gpl-2.0
|
11345299619f2896ed4b70158b1683b1
| 0.526592 | 4.101382 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd
| 4 | 4,254 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_quad_opamp is
end tb_quad_opamp ;
architecture TB_quad_opamp of tb_quad_opamp is
-- Component declarations
-- Signal declarations
terminal amp_out : electrical_vector(1 to 4);
terminal inm : electrical_vector(1 to 4);
terminal inp : electrical_vector(1 to 4);
begin
-- Signal assignments
-- Component instances
opamp_quad_slew1 : entity work.quad_opamp_wa(slew_limited)
port map(
n1 => inp,
n2 => inm,
output => amp_out
);
R4 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ELECTRICAL_REF,
p2 => amp_out(4)
);
v4 : entity work.v_pulse(ideal)
generic map(
period => 200 us,
width => 100 us,
delay => 10 us,
tp2i => 0.9 us,
ti2p => 0.70 us,
pulse => 5.0
)
port map(
pos => inm(1),
neg => ELECTRICAL_REF
);
R5 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ELECTRICAL_REF,
p2 => amp_out(3)
);
R6 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ELECTRICAL_REF,
p2 => amp_out(2)
);
R7 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ELECTRICAL_REF,
p2 => amp_out(1)
);
v5 : entity work.v_pulse(ideal)
generic map(
pulse => 5.0,
ti2p => 0.70 us,
tp2i => 0.9 us,
delay => 10 us,
width => 100 us,
period => 200 us
)
port map(
pos => inm(2),
neg => ELECTRICAL_REF
);
v6 : entity work.v_pulse(ideal)
generic map(
pulse => 5.0,
ti2p => 0.70 us,
tp2i => 0.9 us,
delay => 10 us,
width => 100 us,
period => 200 us
)
port map(
pos => inm(3),
neg => ELECTRICAL_REF
);
v7 : entity work.v_pulse(ideal)
generic map(
pulse => 5.0,
ti2p => 0.70 us,
tp2i => 0.9 us,
delay => 10 us,
width => 100 us,
period => 200 us
)
port map(
pos => inm(4),
neg => ELECTRICAL_REF
);
R8 : entity work.resistor(ideal)
generic map(
res => 10.0e-3
)
port map(
p1 => ELECTRICAL_REF,
p2 => inp(1)
);
R9 : entity work.resistor(ideal)
generic map(
res => 10.0e-3
)
port map(
p1 => ELECTRICAL_REF,
p2 => inp(2)
);
R10 : entity work.resistor(ideal)
generic map(
res => 10.0e-3
)
port map(
p1 => ELECTRICAL_REF,
p2 => inp(3)
);
R11 : entity work.resistor(ideal)
generic map(
res => 10.0e-3
)
port map(
p1 => ELECTRICAL_REF,
p2 => inp(4)
);
end TB_quad_opamp ;
|
gpl-2.0
|
444e1bba39c007084b48c5b2f4a30979
| 0.490362 | 3.902752 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2288.vhd
| 4 | 3,388 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2288.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02288ent IS
END c07s02b06x00p32n01i02288ent;
ARCHITECTURE c07s02b06x00p32n01i02288arch OF c07s02b06x00p32n01i02288ent IS
BEGIN
TESTING: PROCESS
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
wait for 5 ns;
assert NOT( ((1 A * 10) = 1 nm) and
((1 nm * 1000) = 1 um) and
((1 um * 1000) = 1 mm) and
((1 mm * 10) = 1 cm) and
((10 * 1 A) = 1 nm) and
((1000 * 1 nm) = 1 um) and
((1000 * 1 um) = 1 mm) and
((10 * 1 mm) = 1 cm) and
((1 A * 254000) = 1 mil)and
((1 mil * 1000) = 1 inch)and
((254000 * 1 A) = 1 mil)and
((1000 * 1 mil) = 1 inch))
report "***PASSED TEST: c07s02b06x00p32n01i02288"
severity NOTE;
assert ( ((1 A * 10) = 1 nm) and
((1 nm * 1000) = 1 um) and
((1 um * 1000) = 1 mm) and
((1 mm * 10) = 1 cm) and
((10 * 1 A) = 1 nm) and
((1000 * 1 nm) = 1 um) and
((1000 * 1 um) = 1 mm) and
((10 * 1 mm) = 1 cm) and
((1 A * 254000) = 1 mil)and
((1 mil * 1000) = 1 inch)and
((254000 * 1 A) = 1 mil)and
((1000 * 1 mil) = 1 inch))
report "***FAILED TEST: c07s02b06x00p32n01i02288 - Multiplication of a physical type by an integer test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02288arch;
|
gpl-2.0
|
82199a191b92c2a67a11a063bd77cd73
| 0.502361 | 3.735391 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_search.vhd
| 4 | 2,134 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity list_search is
end entity list_search;
----------------------------------------------------------------
architecture test of list_search is
signal s : bit_vector(0 to 3);
begin
process is
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : bit_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list, current_cell : value_ptr;
variable search_value : bit_vector(0 to 3);
begin
value_list := new value_cell'( B"1000", value_list );
value_list := new value_cell'( B"0010", value_list );
value_list := new value_cell'( B"0000", value_list );
search_value := B"0010";
-- code from book:
current_cell := value_list;
while current_cell /= null
and current_cell.value /= search_value loop
current_cell := current_cell.next_cell;
end loop;
assert current_cell /= null
report "search for value failed";
-- end of code from book
search_value := B"1111";
current_cell := value_list;
while current_cell /= null
and current_cell.value /= search_value loop
current_cell := current_cell.next_cell;
end loop;
assert current_cell /= null
report "search for value failed";
wait;
end process;
end architecture test;
|
gpl-2.0
|
98560fa2a7a13d4c5dab523d63bb9e30
| 0.653702 | 4.034026 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_08.vhd
| 4 | 1,883 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_08 is
end entity ch_04_08;
----------------------------------------------------------------
architecture test of ch_04_08 is
begin
process_04_3_b : process is
-- code from book:
type array1 is array (1 to 100) of integer;
type array2 is array (100 downto 1) of integer;
variable a1 : array1;
variable a2 : array2;
-- end of code from book
begin
a1(11 to 20) := a1(11 to 20);
a2(50 downto 41) := a2(50 downto 41);
a1(10 to 1) := a1(10 to 1);
a2(1 downto 10) := a2(1 downto 10);
a1(10 downto 1) := a1(10 downto 1); -- illegal
a2(1 to 10) := a2(1 to 10); -- illegal;
wait;
end process process_04_3_b;
end architecture test;
|
gpl-2.0
|
a278896e61cfaad4484f15ae0ba4724f
| 0.543282 | 4.03212 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/MAIA/inverter_maia_163.vhd
| 1 | 9,681 |
----------------------------------------------------------------------------------------------------
-- inverter_maia_2.vhd ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the Modified Almost Inverse Algorithm.
-- Diferent to the first implementation, here the test g(U) < g(V) is
-- performed directly by a m+1 bit comparer.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
--------------------------------------------------------
entity inverter_maia_163 is
generic(
NUM_BITS : positive := 163 -- The order of the finite field
);
port(
ax : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- input polynomial of grade m-1
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
z : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end ;
---------------------------------------------------------
architecture behave of inverter_maia_163 is
---------------------------------------------------------
signal B,C,U,V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal processing registers, one bit more
signal Bx_Op1 : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Multiplexer which depends on if B is ever or odd
signal Ux_div_x : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- U and B divided by x
signal Bx_div_x : STD_LOGIC_VECTOR(NUM_BITS downto 0);
--163
constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--233
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--277
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--283
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--409
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--571
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--
-- m = 163 x163 + x7 + x6 + x3 + 1
constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant Fx: std_logic_vector(NUM_BITS1 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------
-- States fot the FSM controlling the execution of the algorithm
----------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, LOOP_U0, NEXT_STEP);
signal State: CurrentState_type;
----------------------------------------------------------------------------------
begin
------------------------------------------------------
Ux_div_x <= '0' & U(NUM_BITS downto 1); -- Dividing U and B by x
Bx_div_x <= '0' & Bx_Op1(NUM_BITS downto 1);
------------------------------------------------------
Bx_Op1 <= B xor Fx when B(0) = '1' else -- Multiplexer for operand B
B;
-------------------------------------------------------
-- The Modified ALmost Inverse Algorithm implementation
-------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then -- initialize internal registers
State <= LOOP_U0;
B <= UNO;
U <= '0'&Ax;
V <= Fx;
C <= (others => '0');
z <= (others => '0'); -- set to zero the output register
Done <= '0';
else
case State is
-----------------------------------------------------------------------------------
when LOOP_U0 => -- Stay here while U be even
if U(0) = '1' then
if U = UNO then -- The algorithm finishes when U = 1
Z <= B(NUM_BITS-1 downto 0);
Done <= '1';
State <= END_STATE;
else
if U < V then -- Interchange the registers U <-> V and B <-> C
U <= V;
V <= U;
B <= C;
C <= B;
end if;
State <= NEXT_STEP;
end if;
else -- Divide U and B and repeat the process
U <= Ux_div_x;
B <= Bx_div_x;
end if;
-----------------------------------------------------------------------------------
when NEXT_STEP => -- update U and B with the values previously assigned
U <= U xor V;
B <= B xor C;
State <= LOOP_U0;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
State <= END_STATE;
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
14582c534754ee168d20afabb659a6f7
| 0.640946 | 6.732267 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1393.vhd
| 4 | 2,019 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1393.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n01i01393ent IS
END c08s05b00x00p04n01i01393ent;
ARCHITECTURE c08s05b00x00p04n01i01393arch OF c08s05b00x00p04n01i01393ent IS
BEGIN
TESTING: PROCESS
type RT is
record
a : CHARACTER;
b : CHARACTER;
end record;
variable v1, v2 : CHARACTER := NUL;
variable rv : RT := ('1', '2');
BEGIN
assert v1 = NUL;
assert v2 = NUL;
(v1, v2) := rv;
assert v1 = '1';
assert v2 = '2';
wait for 1 ns;
assert NOT( v1 = '1' and v2 = '2' )
report "***PASSED TEST: c08s05b00x00p04n01i01393"
severity NOTE;
assert ( v1 = '1' and v2 = '2' )
report "***FAILED TEST: c08s05b00x00p04n01i01393 - Aggregate (record type) assignment for variable test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n01i01393arch;
|
gpl-2.0
|
bc6bba0d0a0a0569588fa4d33102d854
| 0.637444 | 3.535902 | false | true | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.a-ControlUnit.core/a.a.c-Branch.vhd
| 1 | 4,816 |
--------------------------------------------------------------------------------
-- FILE: Branch
-- DESC: The branch unit, decide whether a branch instruction should be taken or not
--
-- Author:
-- Create: 2015-06-03
-- Update: 2015-06-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Branch is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
OPCD_SIZE : integer := C_SYS_OPCD_SIZE;
ADDR_SIZE : integer := C_SYS_ADDR_SIZE
);
port (
rst : in std_logic;
clk : in std_logic;
reg_a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
ld_a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
opcd : in std_logic_vector(OPCD_SIZE-1 downto 0):=(others=>'0');
addr : in std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
sig_bal : in std_logic:='0';
sig_bpw : out std_logic :='0';
sig_brt : out std_logic :='0'
);
end Branch;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture branch_arch of Branch is
constant BPU_ADDR_SIZE: integer:= C_BPU_ADDR_SIZE;
constant BPU_BHT_SIZE: integer := 2**BPU_ADDR_SIZE;
constant BPU_TAG_SIZE: integer := ADDR_SIZE-BPU_ADDR_SIZE-2;
type Bht_t is array (0 to BPU_BHT_SIZE-1) of std_logic_vector(BPU_TAG_SIZE+1 downto 0);
signal bht : Bht_t;
signal sig_brt_tmp, sig_bpw_tmp, sig_brt_delay, sig_bal_delay: std_logic:='0';
signal opcd_delay: std_logic_vector(OPCD_SIZE-1 downto 0):=(others=>'0');
signal addr_delay: std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
signal index_r, index_r_delay : integer:= 0;
signal entry_r, entry_r_delay : std_logic_vector(BPU_TAG_SIZE+1 downto 0);
signal zeros32 : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
begin
P0: process(rst, reg_a, opcd, sig_bal)
variable index : integer:= 0;
variable entry : std_logic_vector(BPU_TAG_SIZE+1 downto 0);
variable tag : std_logic_vector(BPU_TAG_SIZE-1 downto 0);
begin
if rst='0' then
sig_brt <= '0';
sig_brt_tmp <= '0';
else
if sig_bal='1' then
tag := addr(ADDR_SIZE-1 downto BPU_ADDR_SIZE+2);
index := to_integer(unsigned(addr(BPU_ADDR_SIZE+1 downto 2)));
entry := bht(index);
if tag /= entry(BPU_TAG_SIZE+1 downto 2) then -- TAG NOT MATCH --replace
entry := tag & "00";
end if;
sig_brt <= entry(1);
sig_brt_tmp <= entry(1);
index_r <= index;
entry_r <= entry;
else
if ((reg_a=zeros32) and (opcd=OPCD_BEQZ)) or ((reg_a/=zeros32) and (opcd=OPCD_BNEZ)) then
sig_brt <= '1';
sig_brt_tmp <= '1';
else
sig_brt <= '0';
sig_brt_tmp <= '0';
end if;
end if;
end if;
end process;
P1: process(rst, ld_a, opcd_delay, sig_bal_delay)
variable index : integer:= 0;
variable entry : std_logic_vector(BPU_TAG_SIZE+1 downto 0);
variable val : std_logic_vector(1 downto 0);
begin
if rst='0' then
for i in 0 to BPU_BHT_SIZE-1 loop
bht(i) <= (others=>'0');
end loop;
sig_bpw <= '0';
sig_bpw_tmp <= '0';
else
if sig_bal_delay='1' then
if (ld_a=zeros32 and opcd_delay=OPCD_BEQZ and sig_brt_delay='1') or (ld_a/=zeros32 and opcd_delay=OPCD_BNEZ and sig_brt_delay='1') or (ld_a/=zeros32 and opcd_delay=OPCD_BEQZ and sig_brt_delay='0') or (ld_a=zeros32 and opcd_delay=OPCD_BNEZ and sig_brt_delay='0') then
index := index_r_delay;
entry := entry_r_delay;
entry(0) := sig_brt_delay;
bht(index) <= entry;
sig_bpw <= '0';
sig_bpw_tmp <= '0';
else
index := index_r_delay;
val := entry_r_delay(1 downto 0);
if val = "10" then
val := "01";
elsif val = "01" then
val := "10";
else
val(0) := not sig_brt_delay;
end if;
entry := entry_r_delay(BPU_TAG_SIZE+1 downto 2) & val;
bht(index) <= entry;
sig_bpw <= '1';
sig_bpw_tmp <= '1';
end if;
else
sig_bpw <= '0';
sig_bpw_tmp <= '0';
end if;
end if;
end process;
P2: process(rst, clk)
begin
if rst='0' then
sig_bal_delay <= '0';
sig_brt_delay <= '0';
opcd_delay <= (others=>'0');
addr_delay <= (others=>'0');
index_r_delay <= 0;
entry_r_delay <= (others=>'0');
else
if clk'event and clk='1' then
sig_bal_delay <= sig_bal;
sig_brt_delay <= sig_brt_tmp;
opcd_delay <= opcd;
addr_delay <= addr;
index_r_delay <= index_r;
entry_r_delay <= entry_r;
end if;
end if;
end process;
end branch_arch;
|
mit
|
f8a5d9c71999c3d61b9773be3fbf52d1
| 0.547757 | 2.904704 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_pwm.vhd
| 1 | 9,654 |
-- #################################################################################################
-- # << NEO430 - PWM Controller >> #
-- # ********************************************************************************************* #
-- # Simple 4-channel PWM controller with 4 or 8 bit resolution for the duty cycle and selectable #
-- # counter width (frequency resolution) 4 or 8 bits. #
-- # Channel 3 can be used to alternatively modulate the GPIO unit's output port. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_pwm is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- GPIO output PWM --
gpio_pwm_o : out std_ulogic;
-- pwm output channels --
pwm_o : out std_ulogic_vector(03 downto 0)
);
end neo430_pwm;
architecture neo430_pwm_rtl of neo430_pwm is
-- internal configuration --
constant num_pwm_channels_c : natural := 4; -- number of PWM channels - FIXED!
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(pwm_size_c); -- low address boundary bit
-- Control register bits --
constant ctrl_enable_c : natural := 0; -- -/w: PWM enable
constant ctrl_prsc0_bit_c : natural := 1; -- -/w: prescaler select bit 0
constant ctrl_prsc1_bit_c : natural := 2; -- -/w: prescaler select bit 1
constant ctrl_prsc2_bit_c : natural := 3; -- -/w: prescaler select bit 2
constant ctrl_gpio_pwm_c : natural := 4; -- -/w: use channel 3 for GPIO controller output modulation
constant ctrl_size_sel_c : natural := 5; -- -/w: cnt size select (0 = 4-bit, 1 = 8-bit)
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wren : std_ulogic; -- word write enable
-- accessible regs --
type pwm_ch_t is array (0 to num_pwm_channels_c-1) of std_ulogic_vector(7 downto 0);
signal pwm_ch : pwm_ch_t; -- duty cycle
signal enable : std_ulogic; -- enable unit
signal gpio_pwm : std_ulogic; -- use pwm channel 3 to module GPIO unit's output port
signal prsc : std_ulogic_vector(2 downto 0); -- clock prescaler
signal size_sel : std_ulogic; -- select pwm counter size
-- constrained pwm counter --
signal mask : std_ulogic_vector(7 downto 0);
-- prescaler clock generator --
signal prsc_tick : std_ulogic;
-- pwm counter --
signal pwm_cnt : std_ulogic_vector(7 downto 0);
signal pwm_out : std_ulogic_vector(3 downto 0);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = pwm_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= pwm_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wren <= acc_en and wren_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wren = '1') then
if (addr = pwm_ctrl_addr_c) then -- control register
enable <= data_i(ctrl_enable_c);
prsc <= data_i(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c);
size_sel <= data_i(ctrl_size_sel_c);
gpio_pwm <= data_i(ctrl_gpio_pwm_c);
end if;
if (addr = pwm_ch10_addr_c) then
pwm_ch(0) <= data_i(07 downto 0);
pwm_ch(1) <= data_i(15 downto 8);
end if;
if (addr = pwm_ch32_addr_c) then
pwm_ch(2) <= data_i(07 downto 0);
pwm_ch(3) <= data_i(15 downto 8);
end if;
end if;
end if;
end process wr_access;
-- PWM frequency select --
clkgen_en_o <= enable; -- enable clock generator
prsc_tick <= clkgen_i(to_integer(unsigned(prsc)));
-- effective counter width --
mask(3 downto 0) <= "1111";
mask(7 downto 4) <= (others => size_sel);
-- PWM Core -----------------------------------------------------------------
-- -----------------------------------------------------------------------------
pwm_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- pwm counter --
if (enable = '0') then
pwm_cnt <= (others => '0');
elsif (prsc_tick = '1') then
pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1);
end if;
-- channels --
for i in 0 to num_pwm_channels_c-1 loop
-- constrain to virtual size configured by SIZE control register bit
if (unsigned(pwm_cnt and mask) >= unsigned(pwm_ch(i) and mask)) or (enable = '0') then
pwm_out(i) <= '0';
else
pwm_out(i) <= '1';
end if;
end loop; -- i, pwm channel
end if;
end process pwm_core;
-- output --
pwm_o(0) <= pwm_out(0);
pwm_o(1) <= pwm_out(1);
pwm_o(2) <= pwm_out(2);
pwm_o(3) <= pwm_out(3) when (gpio_pwm = '0') else '0'; -- output if channel is not used for GPIO
-- GPIO output modulation --
gpio_pwm_o <= pwm_out(3) when (gpio_pwm = '1') else '1';
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (acc_en = '1') and (rden_i = '1') then
if (addr = pwm_ch10_addr_c) then -- PWM channel 0 & 1
data_o(07 downto 0) <= pwm_ch(0);
data_o(15 downto 8) <= pwm_ch(1);
else -- PWM channel 2 & 3
data_o(07 downto 0) <= pwm_ch(2);
data_o(15 downto 8) <= pwm_ch(3);
end if;
end if;
end if;
end process rd_access;
end neo430_pwm_rtl;
|
bsd-3-clause
|
e0d9ccdc2e43407a07bc2cab3150a466
| 0.478972 | 4.33109 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1880.vhd
| 4 | 1,893 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1880.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01880ent IS
END c07s01b00x00p08n01i01880ent;
ARCHITECTURE c07s01b00x00p08n01i01880arch OF c07s01b00x00p08n01i01880ent IS
type small_int is range 0 to 7;
signal s_int : small_int;
BEGIN
blk : block(s_int = 0)
begin
end block blk;
TESTING : PROCESS
variable tmp : small_int;
BEGIN
case blk is -- block labels illegal here
when 0 => tmp := 0;
when others => tmp := 1;
end case;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01880 - Block labels are not permitted as primaries in a case expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01880arch;
|
gpl-2.0
|
d4253a33274a82b64f1ce316faaf4062
| 0.655045 | 3.719057 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_full.vhd
| 4 | 1,301 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_full is
end entity tb_full;
library util; use util.stimulus_generators.all;
architecture test of tb_full is
signal in1, in2, in3, out1, out2 : bit;
signal test_vector : bit_vector(1 to 3);
begin
dut : configuration work.full
generic map ( inpad_delay => 2 ns, outpad_delay => 3 ns )
port map ( in1 => in1, in2 => in2, in3 => in3, out1 => out1, out2 => out2 );
stimulus : all_possible_values ( test_vector, 50 ns );
(in1, in2, in3) <= test_vector;
end architecture test;
|
gpl-2.0
|
8baeb7157a48fece7ac9e53599359afc
| 0.710223 | 3.654494 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3158.vhd
| 4 | 2,890 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3158.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s03b00x00p16n01i03158ent IS
END c05s03b00x00p16n01i03158ent;
ARCHITECTURE c05s03b00x00p16n01i03158arch OF c05s03b00x00p16n01i03158ent IS
-- Define resolution function for SIG:
function RESFUNC( S : BIT_VECTOR ) return BIT is
begin
for I in S'RANGE loop
if (S(I) = '1') then
return '1';
end if;
end loop;
return '0';
end RESFUNC;
-- Define the signal.
subtype RBIT is RESFUNC BIT;
signal SIG : RBIT bus;
-- Use the implicit disconnect specification here.
-- Define the GUARD signal.
signal GUARD : BOOLEAN := FALSE;
BEGIN
-- Define the guarded signal assignment.
L1: block
begin
SIG <= guarded '1';
end block L1;
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
-- 1. Turn on the GUARD, verify that SIG gets toggled.
GUARD <= TRUE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '1' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
-- 2. Turn off the GUARD, verify that SIG gets turned OFF.
GUARD <= FALSE;
ShouldBeTime := NOW;
wait on SIG;
assert( SIG = '0' ) severity FAILURE;
assert( ShouldBeTime = NOW ) severity FAILURE;
assert NOT( SIG = '0' and ShouldBeTime = NOW )
report "***PASSED TEST: c05s03b00x00p16n01i03158"
severity NOTE;
assert ( SIG = '0' and ShouldBeTime = NOW )
report "***FAILED TEST: c05s03b00x00p16n01i03158 - Default disconnect specification test failed."
severity ERROR;
-- Define a second driver for SIG, just for kicks.
-- Should never get invoked. Not have an effect on the value.
SIG <= '0' after 10 ns;
wait;
END PROCESS TESTING;
END c05s03b00x00p16n01i03158arch;
|
gpl-2.0
|
a6ecb3a730ef4c8c67cbbc85e293f4e4
| 0.654325 | 3.837981 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_03.vhd
| 4 | 2,949 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_12_fg_12_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
entity reg is
generic ( width : positive );
port ( d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1);
clk, reset : in bit );
end entity reg;
--------------------------------------------------
architecture behavioral of reg is
begin
behavior : process (clk, reset) is
constant zero : bit_vector(0 to width - 1) := (others => '0');
begin
if reset = '1' then
q <= zero;
elsif clk'event and clk = '1' then
q <= d;
end if;
end process behavior;
end architecture behavioral;
-- end code from book
entity fg_12_03 is
end entity fg_12_03;
architecture test of fg_12_03 is
-- code from book
subtype state_vector is bit_vector(1 to 5);
-- end code from book
signal clk, reset : bit := '0';
signal word_in, word_out : bit_vector(0 to 31);
signal state_in, state_out : state_vector;
begin
-- code from book
word_reg : entity work.reg(behavioral)
generic map ( width => 32 )
port map ( -- . . . );
-- not in book
d => word_in, q => word_out, clk => clk, reset => reset );
-- end not in book
state_reg : entity work.reg(behavioral)
generic map ( width => state_vector'length )
port map ( -- . . . );
-- not in book
d => state_in, q => state_out, clk => clk, reset => reset );
-- end code from book
clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
reset_gen : reset <= '1' after 80 ns, '0' after 105 ns;
stimulus_word : word_in <= X"11111111" after 25 ns,
X"22222222" after 65 ns,
X"33333333" after 85 ns,
X"44444444" after 125 ns;
stimulus_state : state_in <= "00001" after 25 ns,
"00010" after 65 ns,
"00011" after 85 ns,
"00100" after 125 ns;
end architecture test;
|
gpl-2.0
|
db8c1beec7c1903856b4b5d52d840057
| 0.565276 | 3.83485 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/SingleFile/f2m_divider_131.vhd
| 1 | 9,137 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_131 is
generic(
NUM_BITS : positive := 131
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
Ux : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_131 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 131
constant F : std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001101";
-- m = 163, the irreductible polynomial
--constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant F_x: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par, u_mas_v_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, INIT, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & y;
B <= F;
U <= '0' & x;
v <= (others => '0');
Ux <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
Ux <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
da3c244601e95aabf3892d9e31abbe7a
| 0.506731 | 4.78377 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/building_blocks/invSubByte.vhd
| 2 | 13,352 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/15/2015 02:54:47 PM
-- Design Name:
-- Module Name: invSubByte - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity invSubByte is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end invSubByte;
architecture Behavioral of invSubByte is
begin
process(CLK, RESET, byteIn)
begin
if RESET = '1' then
byteOut <= (others => '0');
elsif rising_edge(CLK) then
case byteIn is
when x"00" => byteOut <= x"52";
when x"01" => byteOut <= x"09";
when x"02" => byteOut <= x"6A";
when x"03" => byteOut <= x"D5";
when x"04" => byteOut <= x"30";
when x"05" => byteOut <= x"36";
when x"06" => byteOut <= x"A5";
when x"07" => byteOut <= x"38";
when x"08" => byteOut <= x"BF";
when x"09" => byteOut <= x"40";
when x"0A" => byteOut <= x"A3";
when x"0B" => byteOut <= x"9E";
when x"0C" => byteOut <= x"81";
when x"0D" => byteOut <= x"F3";
when x"0E" => byteOut <= x"D7";
when x"0F" => byteOut <= x"FB";
when x"10" => byteOut <= x"7C";
when x"11" => byteOut <= x"E3";
when x"12" => byteOut <= x"39";
when x"13" => byteOut <= x"82";
when x"14" => byteOut <= x"9B";
when x"15" => byteOut <= x"2F";
when x"16" => byteOut <= x"FF";
when x"17" => byteOut <= x"87";
when x"18" => byteOut <= x"34";
when x"19" => byteOut <= x"8E";
when x"1A" => byteOut <= x"43";
when x"1B" => byteOut <= x"44";
when x"1C" => byteOut <= x"C4";
when x"1D" => byteOut <= x"DE";
when x"1E" => byteOut <= x"E9";
when x"1F" => byteOut <= x"CB";
when x"20" => byteOut <= x"54";
when x"21" => byteOut <= x"7B";
when x"22" => byteOut <= x"94";
when x"23" => byteOut <= x"32";
when x"24" => byteOut <= x"A6";
when x"25" => byteOut <= x"C2";
when x"26" => byteOut <= x"23";
when x"27" => byteOut <= x"3D";
when x"28" => byteOut <= x"EE";
when x"29" => byteOut <= x"4C";
when x"2A" => byteOut <= x"95";
when x"2B" => byteOut <= x"0B";
when x"2C" => byteOut <= x"42";
when x"2D" => byteOut <= x"FA";
when x"2E" => byteOut <= x"C3";
when x"2F" => byteOut <= x"4E";
when x"30" => byteOut <= x"08";
when x"31" => byteOut <= x"2E";
when x"32" => byteOut <= x"A1";
when x"33" => byteOut <= x"66";
when x"34" => byteOut <= x"28";
when x"35" => byteOut <= x"D9";
when x"36" => byteOut <= x"24";
when x"37" => byteOut <= x"B2";
when x"38" => byteOut <= x"76";
when x"39" => byteOut <= x"5B";
when x"3A" => byteOut <= x"A2";
when x"3B" => byteOut <= x"49";
when x"3C" => byteOut <= x"6D";
when x"3D" => byteOut <= x"8B";
when x"3E" => byteOut <= x"D1";
when x"3F" => byteOut <= x"25";
when x"40" => byteOut <= x"72";
when x"41" => byteOut <= x"F8";
when x"42" => byteOut <= x"F6";
when x"43" => byteOut <= x"64";
when x"44" => byteOut <= x"86";
when x"45" => byteOut <= x"68";
when x"46" => byteOut <= x"98";
when x"47" => byteOut <= x"16";
when x"48" => byteOut <= x"D4";
when x"49" => byteOut <= x"A4";
when x"4A" => byteOut <= x"5C";
when x"4B" => byteOut <= x"CC";
when x"4C" => byteOut <= x"5D";
when x"4D" => byteOut <= x"65";
when x"4E" => byteOut <= x"B6";
when x"4F" => byteOut <= x"92";
when x"50" => byteOut <= x"6C";
when x"51" => byteOut <= x"70";
when x"52" => byteOut <= x"48";
when x"53" => byteOut <= x"50";
when x"54" => byteOut <= x"FD";
when x"55" => byteOut <= x"ED";
when x"56" => byteOut <= x"B9";
when x"57" => byteOut <= x"DA";
when x"58" => byteOut <= x"5E";
when x"59" => byteOut <= x"15";
when x"5A" => byteOut <= x"46";
when x"5B" => byteOut <= x"57";
when x"5C" => byteOut <= x"A7";
when x"5D" => byteOut <= x"8D";
when x"5E" => byteOut <= x"9D";
when x"5F" => byteOut <= x"84";
when x"60" => byteOut <= x"90";
when x"61" => byteOut <= x"D8";
when x"62" => byteOut <= x"AB";
when x"63" => byteOut <= x"00";
when x"64" => byteOut <= x"8C";
when x"65" => byteOut <= x"BC";
when x"66" => byteOut <= x"D3";
when x"67" => byteOut <= x"0A";
when x"68" => byteOut <= x"F7";
when x"69" => byteOut <= x"E4";
when x"6A" => byteOut <= x"58";
when x"6B" => byteOut <= x"05";
when x"6C" => byteOut <= x"B8";
when x"6D" => byteOut <= x"B3";
when x"6E" => byteOut <= x"45";
when x"6F" => byteOut <= x"06";
when x"70" => byteOut <= x"D0";
when x"71" => byteOut <= x"2C";
when x"72" => byteOut <= x"1E";
when x"73" => byteOut <= x"8F";
when x"74" => byteOut <= x"CA";
when x"75" => byteOut <= x"3F";
when x"76" => byteOut <= x"0F";
when x"77" => byteOut <= x"02";
when x"78" => byteOut <= x"C1";
when x"79" => byteOut <= x"AF";
when x"7A" => byteOut <= x"BD";
when x"7B" => byteOut <= x"03";
when x"7C" => byteOut <= x"01";
when x"7D" => byteOut <= x"13";
when x"7E" => byteOut <= x"8A";
when x"7F" => byteOut <= x"6B";
when x"80" => byteOut <= x"3A";
when x"81" => byteOut <= x"91";
when x"82" => byteOut <= x"11";
when x"83" => byteOut <= x"41";
when x"84" => byteOut <= x"4F";
when x"85" => byteOut <= x"67";
when x"86" => byteOut <= x"DC";
when x"87" => byteOut <= x"EA";
when x"88" => byteOut <= x"97";
when x"89" => byteOut <= x"F2";
when x"8A" => byteOut <= x"CF";
when x"8B" => byteOut <= x"CE";
when x"8C" => byteOut <= x"F0";
when x"8D" => byteOut <= x"B4";
when x"8E" => byteOut <= x"E6";
when x"8F" => byteOut <= x"73";
when x"90" => byteOut <= x"96";
when x"91" => byteOut <= x"AC";
when x"92" => byteOut <= x"74";
when x"93" => byteOut <= x"22";
when x"94" => byteOut <= x"E7";
when x"95" => byteOut <= x"AD";
when x"96" => byteOut <= x"35";
when x"97" => byteOut <= x"85";
when x"98" => byteOut <= x"E2";
when x"99" => byteOut <= x"F9";
when x"9A" => byteOut <= x"37";
when x"9B" => byteOut <= x"E8";
when x"9C" => byteOut <= x"1C";
when x"9D" => byteOut <= x"75";
when x"9E" => byteOut <= x"DF";
when x"9F" => byteOut <= x"6E";
when x"A0" => byteOut <= x"47";
when x"A1" => byteOut <= x"F1";
when x"A2" => byteOut <= x"1A";
when x"A3" => byteOut <= x"71";
when x"A4" => byteOut <= x"1D";
when x"A5" => byteOut <= x"29";
when x"A6" => byteOut <= x"C5";
when x"A7" => byteOut <= x"89";
when x"A8" => byteOut <= x"6F";
when x"A9" => byteOut <= x"B7";
when x"AA" => byteOut <= x"62";
when x"AB" => byteOut <= x"0E";
when x"AC" => byteOut <= x"AA";
when x"AD" => byteOut <= x"18";
when x"AE" => byteOut <= x"BE";
when x"AF" => byteOut <= x"1B";
when x"B0" => byteOut <= x"FC";
when x"B1" => byteOut <= x"56";
when x"B2" => byteOut <= x"3E";
when x"B3" => byteOut <= x"4B";
when x"B4" => byteOut <= x"C6";
when x"B5" => byteOut <= x"D2";
when x"B6" => byteOut <= x"79";
when x"B7" => byteOut <= x"20";
when x"B8" => byteOut <= x"9A";
when x"B9" => byteOut <= x"DB";
when x"BA" => byteOut <= x"C0";
when x"BB" => byteOut <= x"FE";
when x"BC" => byteOut <= x"78";
when x"BD" => byteOut <= x"CD";
when x"BE" => byteOut <= x"5A";
when x"BF" => byteOut <= x"F4";
when x"C0" => byteOut <= x"1F";
when x"C1" => byteOut <= x"DD";
when x"C2" => byteOut <= x"A8";
when x"C3" => byteOut <= x"33";
when x"C4" => byteOut <= x"88";
when x"C5" => byteOut <= x"07";
when x"C6" => byteOut <= x"C7";
when x"C7" => byteOut <= x"31";
when x"C8" => byteOut <= x"B1";
when x"C9" => byteOut <= x"12";
when x"CA" => byteOut <= x"10";
when x"CB" => byteOut <= x"59";
when x"CC" => byteOut <= x"27";
when x"CD" => byteOut <= x"80";
when x"CE" => byteOut <= x"EC";
when x"CF" => byteOut <= x"5F";
when x"D0" => byteOut <= x"60";
when x"D1" => byteOut <= x"51";
when x"D2" => byteOut <= x"7F";
when x"D3" => byteOut <= x"A9";
when x"D4" => byteOut <= x"19";
when x"D5" => byteOut <= x"B5";
when x"D6" => byteOut <= x"4A";
when x"D7" => byteOut <= x"0D";
when x"D8" => byteOut <= x"2D";
when x"D9" => byteOut <= x"E5";
when x"DA" => byteOut <= x"7A";
when x"DB" => byteOut <= x"9F";
when x"DC" => byteOut <= x"93";
when x"DD" => byteOut <= x"C9";
when x"DE" => byteOut <= x"9C";
when x"DF" => byteOut <= x"EF";
when x"E0" => byteOut <= x"A0";
when x"E1" => byteOut <= x"E0";
when x"E2" => byteOut <= x"3B";
when x"E3" => byteOut <= x"4D";
when x"E4" => byteOut <= x"AE";
when x"E5" => byteOut <= x"2A";
when x"E6" => byteOut <= x"F5";
when x"E7" => byteOut <= x"B0";
when x"E8" => byteOut <= x"C8";
when x"E9" => byteOut <= x"EB";
when x"EA" => byteOut <= x"BB";
when x"EB" => byteOut <= x"3C";
when x"EC" => byteOut <= x"83";
when x"ED" => byteOut <= x"53";
when x"EE" => byteOut <= x"99";
when x"EF" => byteOut <= x"61";
when x"F0" => byteOut <= x"17";
when x"F1" => byteOut <= x"2B";
when x"F2" => byteOut <= x"04";
when x"F3" => byteOut <= x"7E";
when x"F4" => byteOut <= x"BA";
when x"F5" => byteOut <= x"77";
when x"F6" => byteOut <= x"D6";
when x"F7" => byteOut <= x"26";
when x"F8" => byteOut <= x"E1";
when x"F9" => byteOut <= x"69";
when x"FA" => byteOut <= x"14";
when x"FB" => byteOut <= x"63";
when x"FC" => byteOut <= x"55";
when x"FD" => byteOut <= x"21";
when x"FE" => byteOut <= x"0C";
when x"FF" => byteOut <= x"7D";
when others => byteOut <= x"00";
end case;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
66145b4db6e276a7f1f85d1378c7dc5b
| 0.365488 | 3.496203 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_09.vhd
| 4 | 2,108 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_ch_17_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_17_09 is
end entity ch_17_09;
----------------------------------------------------------------
architecture test of ch_17_09 is
begin
process is
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : bit_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list, cell_to_be_deleted : value_ptr;
begin
value_list := new value_cell'( B"1000", value_list );
value_list := new value_cell'( B"0010", value_list );
value_list := new value_cell'( B"0000", value_list );
-- code from book:
cell_to_be_deleted := value_list;
value_list := value_list.next_cell;
deallocate(cell_to_be_deleted);
while value_list /= null loop
cell_to_be_deleted := value_list;
value_list := value_list.next_cell;
deallocate(cell_to_be_deleted);
end loop;
-- end of code from book
wait;
end process;
end architecture test;
|
gpl-2.0
|
c6a653bf55a51aeb09f6c441e0a6ad73
| 0.575901 | 4.093204 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/Architecture1_Pipeline/keyExpansion.vhd
| 1 | 15,294 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/21/2015 03:25:04 PM
-- Design Name:
-- Module Name: keyExpansion - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity keyExpansion is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
START : in STD_LOGIC;
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
DONE : out STD_LOGIC;
IDLE : out STD_LOGIC;
MUTATING : out STD_LOGIC;
expandedKey : out STD_LOGIC_VECTOR (1407 downto 0));
function rCon (expansionRound : in natural)
return STD_LOGIC_VECTOR is
begin
case expansionRound is
when 0 => return x"8D";
when 1 => return x"01";
when 2 => return x"02";
when 3 => return x"04";
when 4 => return x"08";
when 5 => return x"10";
when 6 => return x"20";
when 7 => return x"40";
when 8 => return x"80";
when 9 => return x"1B";
when 10 => return x"36";
when others => return x"00";
end case;
end rCon;
function subByte(signal byteIn : in STD_LOGIC_VECTOR(7 downto 0))
return STD_LOGIC_VECTOR is
begin
case byteIn is
when x"00" => return x"63";
when x"01" => return x"7C";
when x"02" => return x"77";
when x"03" => return x"7B";
when x"04" => return x"F2";
when x"05" => return x"6B";
when x"06" => return x"6F";
when x"07" => return x"C5";
when x"08" => return x"30";
when x"09" => return x"01";
when x"0A" => return x"67";
when x"0B" => return x"2B";
when x"0C" => return x"FE";
when x"0D" => return x"D7";
when x"0E" => return x"AB";
when x"0F" => return x"76";
when x"10" => return x"CA";
when x"11" => return x"82";
when x"12" => return x"C9";
when x"13" => return x"7D";
when x"14" => return x"FA";
when x"15" => return x"59";
when x"16" => return x"47";
when x"17" => return x"F0";
when x"18" => return x"AD";
when x"19" => return x"D4";
when x"1A" => return x"A2";
when x"1B" => return x"AF";
when x"1C" => return x"9C";
when x"1D" => return x"A4";
when x"1E" => return x"72";
when x"1F" => return x"C0";
when x"20" => return x"B7";
when x"21" => return x"FD";
when x"22" => return x"93";
when x"23" => return x"26";
when x"24" => return x"36";
when x"25" => return x"3F";
when x"26" => return x"F7";
when x"27" => return x"CC";
when x"28" => return x"34";
when x"29" => return x"A5";
when x"2A" => return x"E5";
when x"2B" => return x"F1";
when x"2C" => return x"71";
when x"2D" => return x"D8";
when x"2E" => return x"31";
when x"2F" => return x"15";
when x"30" => return x"04";
when x"31" => return x"C7";
when x"32" => return x"23";
when x"33" => return x"C3";
when x"34" => return x"18";
when x"35" => return x"96";
when x"36" => return x"05";
when x"37" => return x"9A";
when x"38" => return x"07";
when x"39" => return x"12";
when x"3A" => return x"80";
when x"3B" => return x"E2";
when x"3C" => return x"EB";
when x"3D" => return x"27";
when x"3E" => return x"B2";
when x"3F" => return x"75";
when x"40" => return x"09";
when x"41" => return x"83";
when x"42" => return x"2C";
when x"43" => return x"1A";
when x"44" => return x"1B";
when x"45" => return x"6E";
when x"46" => return x"5A";
when x"47" => return x"A0";
when x"48" => return x"52";
when x"49" => return x"3B";
when x"4A" => return x"D6";
when x"4B" => return x"B3";
when x"4C" => return x"29";
when x"4D" => return x"E3";
when x"4E" => return x"2F";
when x"4F" => return x"84";
when x"50" => return x"53";
when x"51" => return x"D1";
when x"52" => return x"00";
when x"53" => return x"ED";
when x"54" => return x"20";
when x"55" => return x"FC";
when x"56" => return x"B1";
when x"57" => return x"5B";
when x"58" => return x"6A";
when x"59" => return x"CB";
when x"5A" => return x"BE";
when x"5B" => return x"39";
when x"5C" => return x"4A";
when x"5D" => return x"4C";
when x"5E" => return x"58";
when x"5F" => return x"CF";
when x"60" => return x"D0";
when x"61" => return x"EF";
when x"62" => return x"AA";
when x"63" => return x"FB";
when x"64" => return x"43";
when x"65" => return x"4D";
when x"66" => return x"33";
when x"67" => return x"85";
when x"68" => return x"45";
when x"69" => return x"F9";
when x"6A" => return x"02";
when x"6B" => return x"7F";
when x"6C" => return x"50";
when x"6D" => return x"3C";
when x"6E" => return x"9F";
when x"6F" => return x"A8";
when x"70" => return x"51";
when x"71" => return x"A3";
when x"72" => return x"40";
when x"73" => return x"8F";
when x"74" => return x"92";
when x"75" => return x"9D";
when x"76" => return x"38";
when x"77" => return x"F5";
when x"78" => return x"BC";
when x"79" => return x"B6";
when x"7A" => return x"DA";
when x"7B" => return x"21";
when x"7C" => return x"10";
when x"7D" => return x"FF";
when x"7E" => return x"F3";
when x"7F" => return x"D2";
when x"80" => return x"CD";
when x"81" => return x"0C";
when x"82" => return x"13";
when x"83" => return x"EC";
when x"84" => return x"5F";
when x"85" => return x"97";
when x"86" => return x"44";
when x"87" => return x"17";
when x"88" => return x"C4";
when x"89" => return x"A7";
when x"8A" => return x"7E";
when x"8B" => return x"3D";
when x"8C" => return x"64";
when x"8D" => return x"5D";
when x"8E" => return x"19";
when x"8F" => return x"73";
when x"90" => return x"60";
when x"91" => return x"81";
when x"92" => return x"4F";
when x"93" => return x"DC";
when x"94" => return x"22";
when x"95" => return x"2A";
when x"96" => return x"90";
when x"97" => return x"88";
when x"98" => return x"46";
when x"99" => return x"EE";
when x"9A" => return x"B8";
when x"9B" => return x"14";
when x"9C" => return x"DE";
when x"9D" => return x"5E";
when x"9E" => return x"0B";
when x"9F" => return x"DB";
when x"A0" => return x"E0";
when x"A1" => return x"32";
when x"A2" => return x"3A";
when x"A3" => return x"0A";
when x"A4" => return x"49";
when x"A5" => return x"06";
when x"A6" => return x"24";
when x"A7" => return x"5C";
when x"A8" => return x"C2";
when x"A9" => return x"D3";
when x"AA" => return x"AC";
when x"AB" => return x"62";
when x"AC" => return x"91";
when x"AD" => return x"95";
when x"AE" => return x"E4";
when x"AF" => return x"79";
when x"B0" => return x"E7";
when x"B1" => return x"C8";
when x"B2" => return x"37";
when x"B3" => return x"6D";
when x"B4" => return x"8D";
when x"B5" => return x"D5";
when x"B6" => return x"4E";
when x"B7" => return x"A9";
when x"B8" => return x"6C";
when x"B9" => return x"56";
when x"BA" => return x"F4";
when x"BB" => return x"EA";
when x"BC" => return x"65";
when x"BD" => return x"7A";
when x"BE" => return x"AE";
when x"BF" => return x"08";
when x"C0" => return x"BA";
when x"C1" => return x"78";
when x"C2" => return x"25";
when x"C3" => return x"2E";
when x"C4" => return x"1C";
when x"C5" => return x"A6";
when x"C6" => return x"B4";
when x"C7" => return x"C6";
when x"C8" => return x"E8";
when x"C9" => return x"DD";
when x"CA" => return x"74";
when x"CB" => return x"1F";
when x"CC" => return x"4B";
when x"CD" => return x"BD";
when x"CE" => return x"8B";
when x"CF" => return x"8A";
when x"D0" => return x"70";
when x"D1" => return x"3E";
when x"D2" => return x"B5";
when x"D3" => return x"66";
when x"D4" => return x"48";
when x"D5" => return x"03";
when x"D6" => return x"F6";
when x"D7" => return x"0E";
when x"D8" => return x"61";
when x"D9" => return x"35";
when x"DA" => return x"57";
when x"DB" => return x"B9";
when x"DC" => return x"86";
when x"DD" => return x"C1";
when x"DE" => return x"1D";
when x"DF" => return x"9E";
when x"E0" => return x"E1";
when x"E1" => return x"F8";
when x"E2" => return x"98";
when x"E3" => return x"11";
when x"E4" => return x"69";
when x"E5" => return x"D9";
when x"E6" => return x"8E";
when x"E7" => return x"94";
when x"E8" => return x"9B";
when x"E9" => return x"1E";
when x"EA" => return x"87";
when x"EB" => return x"E9";
when x"EC" => return x"CE";
when x"ED" => return x"55";
when x"EE" => return x"28";
when x"EF" => return x"DF";
when x"F0" => return x"8C";
when x"F1" => return x"A1";
when x"F2" => return x"89";
when x"F3" => return x"0D";
when x"F4" => return x"BF";
when x"F5" => return x"E6";
when x"F6" => return x"42";
when x"F7" => return x"68";
when x"F8" => return x"41";
when x"F9" => return x"99";
when x"FA" => return x"2D";
when x"FB" => return x"0F";
when x"FC" => return x"B0";
when x"FD" => return x"54";
when x"FE" => return x"BB";
when x"FF" => return x"16";
when others => return x"00";
end case;
end subByte;
function subWord (signal wordIn : STD_LOGIC_VECTOR(31 downto 0)) return STD_LOGIC_VECTOR is
variable B3, B2, B1, B0 : STD_LOGIC_VECTOR(7 downto 0);
begin
B3 := subByte(wordIn(31 downto 24));
B2 := subByte(wordIn(23 downto 16));
B1 := subByte(wordIn(15 downto 8));
B0 := subByte(wordIn(7 downto 0));
return B3 & B2 & B1 & B0;
end subWord;
function rotateWord (signal wordIn : STD_LOGIC_VECTOR(31 downto 0)) return STD_LOGIC_VECTOR is
begin
return wordIn(23 downto 0) & wordIn(31 downto 24);
end rotateWord;
end keyExpansion;
architecture Behavioral of keyExpansion is
type STATE_TYPE is (generatorIdle, getWord, mutateRotWord, mutateSubWord, mutateXorRcon, xorWord, generatorDone);
signal state, nextState : STATE_TYPE := generatorIdle;
signal expandedKeyTemp : STD_LOGIC_VECTOR(1407 downto 0);
signal tempWord : STD_LOGIC_VECTOR(31 downto 0);
begin
process(CLK, RESET, START)
variable expansionRound : natural range 0 to 10;
variable nextByte : natural range 0 to 176;
begin
DONE <= '0';
IDLE <= '0';
MUTATING <= '0';
if RESET = '1' then
nextState <= generatorIdle;
elsif rising_edge(CLK) then
case state is
when generatorIdle =>
IDLE <= '1';
if (START = '1') then
expandedKeyTemp(1407 downto 1280) <= cipherKey;
expansionRound := 1;
nextByte := 16;
nextState <= getWord;
else
nextState <= generatorIdle;
end if;
when getWord =>
tempWord <= expandedKeyTemp(1407 - (nextByte-4)*8 downto 1407 - nextByte*8 + 1);
nextState <= mutateRotWord;
when mutateRotWord =>
nextState <= xorWord;
if (nextByte mod 16 = 0) then
MUTATING <= '1';
tempWord <= rotateWord(tempWord);
nextState <= mutateSubWord;
end if;
when mutateSubWord =>
tempWord <= subWord(tempWord);
nextState <= mutateXorRcon;
when mutateXorRcon =>
tempWord(31 downto 24) <= tempWord(31 downto 24) XOR rCon(expansionRound);
expansionRound := expansionRound + 1;
nextState <= xorWord;
when xorWord =>
expandedKeyTemp(1407 - nextByte*8 downto 1407 - (nextByte + 4)*8 + 1) <= tempWord XOR expandedKeyTemp(1407 - (nextByte - 16)*8 downto 1407 - (nextByte - 12)*8 + 1);
nextByte := nextByte + 4;
if (nextByte >= 176) then
DONE <= '1';
nextState <= generatorDone;
else
nextState <= getWord;
end if;
when generatorDone =>
nextState <= generatorDone;
when others =>
nextState <= generatorIdle;
end case;
end if;
end process;
state <= nextState;
expandedKey <= expandedKeyTemp;
end Behavioral;
|
gpl-2.0
|
b4e68f4a33d1c2ade9e8c47ef6423a95
| 0.432653 | 3.459398 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/mb_lite/decode.vhd
| 3 | 17,812 |
----------------------------------------------------------------------------------------------
--
-- Input file : decode.vhd
-- Design name : decode
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : This combined register file and decoder uses three Dual Port
-- read after write Random Access Memory components. Every clock
-- cycle three data values can be read (ra, rb and rd) and one value
-- can be stored.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.core_Pkg.ALL;
USE work.std_Pkg.ALL;
ENTITY decode IS GENERIC
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
PORT
(
decode_o : OUT decode_out_type;
gprf_o : OUT gprf_out_type;
decode_i : IN decode_in_type;
ena_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END decode;
ARCHITECTURE arch OF decode IS
TYPE decode_reg_type IS RECORD
instruction : std_ulogic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
immediate : std_ulogic_vector(15 DOWNTO 0);
is_immediate : std_ulogic;
msr_interrupt_enable : std_ulogic;
interrupt : std_ulogic;
delay_interrupt : std_ulogic;
END RECORD;
SIGNAL r, rin : decode_out_type;
SIGNAL reg, regin : decode_reg_type;
SIGNAL wb_dat_d : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
decode_o.imm <= r.imm;
decode_o.ctrl_ex <= r.ctrl_ex;
decode_o.ctrl_mem <= r.ctrl_mem;
decode_o.ctrl_wb <= r.ctrl_wb;
decode_o.reg_a <= r.reg_a;
decode_o.reg_b <= r.reg_b;
decode_o.hazard <= r.hazard;
decode_o.program_counter <= r.program_counter;
decode_o.fwd_dec_result <= r.fwd_dec_result;
decode_o.fwd_dec <= r.fwd_dec;
decode_comb: PROCESS(decode_i,decode_i.ctrl_wb,
decode_i.ctrl_mem_wb,
decode_i.ctrl_mem_wb.transfer_size,
r,r.ctrl_ex,r.ctrl_mem,
r.ctrl_mem.transfer_size,r.ctrl_wb,
r.fwd_dec,reg)
VARIABLE v : decode_out_type;
VARIABLE v_reg : decode_reg_type;
VARIABLE opcode : std_ulogic_vector(5 DOWNTO 0);
VARIABLE instruction : std_ulogic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
VARIABLE program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
VARIABLE mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
v := r;
v_reg := reg;
-- Default register values (NOP)
v_reg.immediate := (OTHERS => '0');
v_reg.is_immediate := '0';
v_reg.program_counter := decode_i.program_counter;
v_reg.instruction := decode_i.instruction;
IF decode_i.ctrl_mem_wb.mem_read = '1' THEN
mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wb.transfer_size, decode_i.alu_result(1 DOWNTO 0));
ELSE
mem_result := decode_i.alu_result;
END IF;
wb_dat_d <= mem_result;
IF G_INTERRUPT = true THEN
v_reg.delay_interrupt := '0';
END IF;
IF CFG_REG_FWD_WB = true THEN
v.fwd_dec_result := mem_result;
v.fwd_dec := decode_i.ctrl_wb;
ELSE
v.fwd_dec_result := (OTHERS => '0');
v.fwd_dec.reg_d := (OTHERS => '0');
v.fwd_dec.reg_write := '0';
END IF;
IF (NOT decode_i.flush_id AND r.ctrl_mem.mem_read AND (compare(decode_i.instruction(20 DOWNTO 16), r.ctrl_wb.reg_d) OR compare(decode_i.instruction(15 DOWNTO 11), r.ctrl_wb.reg_d))) = '1' THEN
-- A hazard occurred on register a or b
-- set current instruction and program counter to 0
instruction := (OTHERS => '0');
program_counter := (OTHERS => '0');
v.hazard := '1';
ELSIF CFG_MEM_FWD_WB = false AND (NOT decode_i.flush_id AND r.ctrl_mem.mem_read AND compare(decode_i.instruction(25 DOWNTO 21), r.ctrl_wb.reg_d)) = '1' THEN
-- A hazard occurred on register d
-- set current instruction and program counter to 0
instruction := (OTHERS => '0');
program_counter := (OTHERS => '0');
v.hazard := '1';
ELSIF r.hazard = '1' THEN
-- Recover from hazard. Insert latched instruction
instruction := reg.instruction;
program_counter := reg.program_counter;
v.hazard := '0';
ELSE
instruction := decode_i.instruction;
program_counter := decode_i.program_counter;
v.hazard := '0';
END IF;
v.program_counter := program_counter;
opcode := instruction(31 DOWNTO 26);
v.ctrl_wb.reg_d := instruction(25 DOWNTO 21);
v.reg_a := instruction(20 DOWNTO 16);
v.reg_b := instruction(15 DOWNTO 11);
-- SET IMM value
IF reg.is_immediate = '1' THEN
v.imm := reg.immediate & instruction(15 DOWNTO 0);
ELSE
v.imm := sign_extend(instruction(15 DOWNTO 0), instruction(15), 32);
END IF;
-- Register if an interrupt occurs
IF G_INTERRUPT = true THEN
IF v_reg.msr_interrupt_enable = '1' AND decode_i.interrupt = '1' THEN
v_reg.interrupt := '1';
v_reg.msr_interrupt_enable := '0';
END IF;
END IF;
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
v.ctrl_ex.operation := '0';
v.ctrl_ex.carry := CARRY_ZERO;
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
v.ctrl_ex.delay := '0';
v.ctrl_ex.branch_cond := NOP;
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.transfer_size := WORD;
v.ctrl_mem.mem_read := '0';
v.ctrl_wb.reg_write := '0';
IF G_INTERRUPT = true AND (v_reg.interrupt = '1' AND reg.delay_interrupt = '0' AND decode_i.flush_id = '0' AND v.hazard = '0' AND r.ctrl_ex.delay = '0' AND reg.is_immediate = '0') THEN
-- IF an interrupt occured
-- AND the current instruction is not a branch or return instruction,
-- AND the current instruction is not in a delay slot,
-- AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.
v_reg.msr_interrupt_enable := '0';
v_reg.interrupt := '0';
v.reg_a := (OTHERS => '0');
v.reg_b := (OTHERS => '0');
v.imm := X"00000010";
v.ctrl_wb.reg_d := "01110";
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_wb.reg_write := '1';
ELSIF (decode_i.flush_id OR v.hazard) = '1' THEN
-- clearing these registers is not necessary, but facilitates debugging.
-- On the other hand performance improves when disabled.
IF G_DEBUG = true THEN
v.program_counter := (OTHERS => '0');
v.ctrl_wb.reg_d := (OTHERS => '0');
v.reg_a := (OTHERS => '0');
v.reg_b := (OTHERS => '0');
v.imm := (OTHERS => '0');
END IF;
ELSIF is_zero(opcode(5 DOWNTO 4)) = '1' THEN
-- ADD, SUBTRACT OR COMPARE
-- Alu operation
v.ctrl_ex.alu_op := ALU_ADD;
-- Source operand A
IF opcode(0) = '1' THEN
v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;
ELSE
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
END IF;
-- Source operand B
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
IF (compare(opcode, "000101") AND instruction(1)) = '1' THEN
v.ctrl_ex.operation := '1';
END IF;
-- Carry
CASE opcode(1 DOWNTO 0) IS
WHEN "00" => v.ctrl_ex.carry := CARRY_ZERO;
WHEN "01" => v.ctrl_ex.carry := CARRY_ONE;
WHEN OTHERS => v.ctrl_ex.carry := CARRY_ALU;
END CASE;
-- Carry keep
IF opcode(2) = '1' THEN
v.ctrl_ex.carry_keep := CARRY_KEEP;
ELSE
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
END IF;
-- Flag writeback if reg_d != 0
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
ELSIF (compare(opcode(5 DOWNTO 2), "1000") OR compare(opcode(5 DOWNTO 2), "1010")) = '1' THEN
-- OR, AND, XOR, ANDN
-- ORI, ANDI, XORI, ANDNI
CASE opcode(1 DOWNTO 0) IS
WHEN "00" => v.ctrl_ex.alu_op := ALU_OR;
WHEN "10" => v.ctrl_ex.alu_op := ALU_XOR;
WHEN OTHERS => v.ctrl_ex.alu_op := ALU_AND;
END CASE;
IF opcode(3) = '1' AND compare(opcode(1 DOWNTO 0), "11") = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;
ELSIF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSIF opcode(3) = '0' AND compare(opcode(1 DOWNTO 0), "11") = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
-- Flag writeback if reg_d != 0
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
ELSIF compare(opcode, "101100") = '1' THEN
-- IMM instruction
v_reg.immediate := instruction(15 DOWNTO 0);
v_reg.is_immediate := '1';
ELSIF compare(opcode, "100100") = '1' THEN
-- SHIFT, SIGN EXTEND
IF compare(instruction(6 DOWNTO 5), "11") = '1' THEN
IF instruction(0) = '1' THEN
v.ctrl_ex.alu_op:= ALU_SEXT16;
ELSE
v.ctrl_ex.alu_op:= ALU_SEXT8;
END IF;
ELSE
v.ctrl_ex.alu_op:= ALU_SHIFT;
CASE instruction(6 DOWNTO 5) IS
WHEN "10" => v.ctrl_ex.carry := CARRY_ZERO;
WHEN "01" => v.ctrl_ex.carry := CARRY_ALU;
WHEN OTHERS => v.ctrl_ex.carry := CARRY_ARITH;
END CASE;
END IF;
-- Flag writeback if reg_d != 0
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
ELSIF (compare(opcode, "100110") OR compare(opcode, "101110")) = '1' THEN
-- BRANCH UNCONDITIONAL
v.ctrl_ex.branch_cond := BNC;
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
-- WRITE THE RESULT ALSO TO REGISTER D
IF v.reg_a(2) = '1' THEN
-- Flag writeback if reg_d != 0
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
END IF;
IF v.reg_a(3) = '1' THEN
v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
ELSE
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
END IF;
IF G_INTERRUPT = true THEN
v_reg.delay_interrupt := '1';
END IF;
v.ctrl_ex.delay := v.reg_a(4);
ELSIF (compare(opcode, "100111") OR compare(opcode, "101111")) = '1' THEN
-- BRANCH CONDITIONAL
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
CASE v.ctrl_wb.reg_d(2 DOWNTO 0) IS
WHEN "000" => v.ctrl_ex.branch_cond := BEQ;
WHEN "001" => v.ctrl_ex.branch_cond := BNE;
WHEN "010" => v.ctrl_ex.branch_cond := BLT;
WHEN "011" => v.ctrl_ex.branch_cond := BLE;
WHEN "100" => v.ctrl_ex.branch_cond := BGT;
WHEN OTHERS => v.ctrl_ex.branch_cond := BGE;
END CASE;
IF G_INTERRUPT = true THEN
v_reg.delay_interrupt := '1';
END IF;
v.ctrl_ex.delay := v.ctrl_wb.reg_d(4);
ELSIF compare(opcode, "101101") = '1' THEN
-- RETURN
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_ex.delay := '1';
IF G_INTERRUPT = true THEN
IF v.ctrl_wb.reg_d(0) = '1' THEN
v_reg.msr_interrupt_enable := '1';
END IF;
v_reg.delay_interrupt := '1';
END IF;
ELSIF compare(opcode(5 DOWNTO 4), "11") = '1' THEN
-- SW, LW
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
v.ctrl_ex.carry := CARRY_ZERO;
IF opcode(2) = '1' THEN
-- Store
v.ctrl_mem.mem_write := '1';
v.ctrl_mem.mem_read := '0';
v.ctrl_wb.reg_write := '0';
ELSE
-- Load
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '1';
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
END IF;
CASE opcode(1 DOWNTO 0) IS
WHEN "00" => v.ctrl_mem.transfer_size := BYTE;
WHEN "01" => v.ctrl_mem.transfer_size := HALFWORD;
WHEN OTHERS => v.ctrl_mem.transfer_size := WORD;
END CASE;
v.ctrl_ex.delay := '0';
ELSIF G_USE_HW_MUL = true AND (compare(opcode, "010000") OR compare(opcode, "011000")) = '1' THEN
v.ctrl_ex.alu_op := ALU_MUL;
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
ELSIF G_USE_BARREL = true AND (compare(opcode, "010001") OR compare(opcode, "011001")) = '1' THEN
v.ctrl_ex.alu_op := ALU_BS;
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
ELSE
-- UNKNOWN OPCODE
NULL;
END IF;
rin <= v;
regin <= v_reg;
END PROCESS;
decode_seq: PROCESS(clk_i)
PROCEDURE proc_reset_decode IS
BEGIN
r.reg_a <= (OTHERS => '0');
r.reg_b <= (OTHERS => '0');
r.imm <= (OTHERS => '0');
r.program_counter <= (OTHERS => '0');
r.hazard <= '0';
r.ctrl_ex.alu_op <= ALU_ADD;
r.ctrl_ex.alu_src_a <= ALU_SRC_REGA;
r.ctrl_ex.alu_src_b <= ALU_SRC_REGB;
r.ctrl_ex.operation <= '0';
r.ctrl_ex.carry <= CARRY_ZERO;
r.ctrl_ex.carry_keep <= CARRY_NOT_KEEP;
r.ctrl_ex.delay <= '0';
r.ctrl_ex.branch_cond <= NOP;
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_mem.mem_read <= '0';
r.ctrl_wb.reg_d <= (OTHERS => '0');
r.ctrl_wb.reg_write <= '0';
r.fwd_dec_result <= (OTHERS => '0');
r.fwd_dec.reg_d <= (OTHERS => '0');
r.fwd_dec.reg_write <= '0';
reg.instruction <= (OTHERS => '0');
reg.program_counter <= (OTHERS => '0');
reg.immediate <= (OTHERS => '0');
reg.is_immediate <= '0';
reg.msr_interrupt_enable <= '1';
reg.interrupt <= '0';
reg.delay_interrupt <= '0';
END PROCEDURE proc_reset_decode;
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
proc_reset_decode;
ELSIF ena_i = '1' THEN
r <= rin;
reg <= regin;
END IF;
END IF;
END PROCESS;
gprf0 : gprf PORT MAP
(
gprf_o => gprf_o,
gprf_i.adr_a_i => rin.reg_a,
gprf_i.adr_b_i => rin.reg_b,
gprf_i.adr_d_i => rin.ctrl_wb.reg_d,
gprf_i.dat_w_i => wb_dat_d,
gprf_i.adr_w_i => decode_i.ctrl_wb.reg_d,
gprf_i.wre_i => decode_i.ctrl_wb.reg_write,
ena_i => ena_i,
clk_i => clk_i
);
END arch;
|
mit
|
f7035585e7a7bf4b0171261fe102611c
| 0.472547 | 3.525732 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd
| 4 | 1,897 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
use ieee_proposed.energy_systems.all;
entity inline_02a is
end entity inline_02a;
architecture test of inline_02a is
constant k_Boltzmann : real := K;
constant temp : real := 300.0;
constant res : real := 10_000.0;
terminal r_p1, r_p2 : electrical;
quantity resistor_voltage across resistor_current through r_p1 to r_p2;
constant k_noise : real := 1.0;
function G ( f : real ) return real is
begin
return 1.0;
end function G;
constant k_flicker : real := 1.0;
constant ids : real := 0.01;
constant af : real := 1.0;
-- code from book
quantity thermal_noise_source : real noise 4.0 * k_Boltzmann * temp * res;
--
quantity shaped_noise_source : real noise k_noise * temp * G(frequency);
--
quantity flicker_noise_source : real noise k_flicker * ids**af / frequency;
-- end code from book
begin
-- code from book
resistor_voltage == resistor_current * res + thermal_noise_source;
-- end code from book
end architecture test;
|
gpl-2.0
|
93623dbce4e6ad1564ee0e1aba8dc40b
| 0.704797 | 3.676357 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_09.vhd
| 4 | 2,034 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity latch is
generic ( width : positive );
port ( enable : in bit;
d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1) );
end entity latch;
--------------------------------------------------
architecture behavioral of latch is
begin
transfer_control : block ( enable = '1' ) is
begin
q <= guarded d;
end block transfer_control;
end architecture behavioral;
-- not in book
entity fg_16_09 is
end entity fg_16_09;
architecture test of fg_16_09 is
signal enable : bit := '0';
signal d, q : bit_vector(0 to 7);
begin
dut : entity work.latch(behavioral)
generic map ( width => 8 )
port map ( enable => enable, d => d, q => q );
stimulus : process is
begin
wait for 10 ns;
d <= X"11"; wait for 10 ns;
enable <= '1'; wait for 10 ns;
d <= X"AA"; wait for 10 ns;
enable <= '0'; wait for 10 ns;
d <= X"00"; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
-- end not in book
|
gpl-2.0
|
0dcb9e105beb8e4e5bb630ed63e0a434
| 0.595379 | 3.823308 | false | false | false | false |
nczempin/NICNAC16
|
ipcore_dir/ROM01/example_design/ROM01_prod.vhd
| 1 | 9,957 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: ROM01_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : ROM01.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ROM01_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END ROM01_prod;
ARCHITECTURE xilinx OF ROM01_prod IS
COMPONENT ROM01_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ROM01_exdes
PORT MAP (
--Port A
ENA => ENA,
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
mit
|
6e67fa8d59f997a8ca336fb991d85857
| 0.49292 | 3.825202 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.0-Sipo.vhd
| 1 | 1,612 |
--------------------------------------------------------------------------------
-- FILE: Sipo
-- DESC: Generic Serial in paralle out, with RESET and ENABLE
--
-- Author:
-- Create: 2015-09-09
-- Update: 2015-09-09
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Sipo is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
rst: in std_logic;
en : in std_logic;
clk: in std_logic;
din: in std_logic;
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end Sipo;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture sipo_arch of Sipo is -- Asyncronous
signal data: std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
begin
PROC0: process(clk, rst)
begin
if rst='0' then -- Reset active low
dout <= (others => '0');
elsif rising_edge(clk) and en='1' then -- Enable active high
dout <= data;
end if;
end process;
data(0) <= din and rst;
GE0: for i in 0 to DATA_SIZE-2 generate
begin
PROC1: process(rst, en, clk, data(i))
begin
if rising_edge(clk) then
if en='1' and rst='1' then
data(i+1) <= data(i);
elsif rst='0' then
data(i+1) <= '0';
end if;
end if;
end process;
end generate;
end sipo_arch;
|
mit
|
194ea0f3567264e135a802e4bedd5829
| 0.443548 | 3.722864 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_02.vhd
| 4 | 2,632 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_02 is
end entity ch_04_02;
----------------------------------------------------------------
architecture test of ch_04_02 is
begin
process_04_1_b : process is
-- code from book:
type symbol is ('a', 't', 'd', 'h', digit, cr, error);
type state is range 0 to 6;
type transition_matrix is array (state, symbol) of state;
variable transition_table : transition_matrix;
-- end of code from book
variable next_state : state;
-- code from book:
type point is array (1 to 3) of real;
type matrix is array (1 to 3, 1 to 3) of real;
variable p, q : point;
variable transform : matrix;
-- end of code from book
begin
next_state :=
-- code from book:
transition_table(5, 'd');
-- end of code from book
for i in 1 to 3 loop
for j in 1 to 3 loop
if i = j then
transform(i, j) := -1.0;
else
transform(i, j) := 0.0;
end if;
end loop;
end loop;
p := (1.0, 2.0, 3.0);
-- code from book:
for i in 1 to 3 loop
q(i) := 0.0;
for j in 1 to 3 loop
q(i) := q(i) + transform(i, j) * p(j);
end loop;
end loop;
-- end of code from book
wait;
end process process_04_1_b;
end architecture test;
|
gpl-2.0
|
736a447e30a3ff03c0af0e713c6e1f07
| 0.49924 | 4.279675 | false | false | false | false |
peteut/ghdl
|
libraries/ieee/numeric_std-body.vhdl
| 5 | 83,082 |
-- --------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_STD)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_STD. The NUMERIC_STD package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
--
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- Version: 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
--==============================================================================
--============================= Package Body ===================================
--==============================================================================
package body NUMERIC_STD is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: STD_LOGIC) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: STD_LOGIC) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
-----------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
-----------------Local Subprograms - Relational ops---------------------------
--
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) = STD_LOGIC_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) = STD_LOGIC_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) < STD_LOGIC_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_LOGIC_VECTOR(INTERN_L) < STD_LOGIC_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) <= STD_LOGIC_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_LOGIC_VECTOR(INTERN_L) <= STD_LOGIC_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--=========================Exported Functions ==========================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := TO_01(XARG, 'X');
if (RESULT(RESULT'LEFT)='X') then return RESULT;
end if;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT, XARG01 : SIGNED(ARG_LEFT downto 0);
variable CBIT: STD_LOGIC := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
XARG01 := TO_01(ARG, 'X');
if (XARG01(XARG01'LEFT)='X') then return XARG01;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG01(I)) xor CBIT;
CBIT := CBIT and not(XARG01(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_UNSIGNED(L01, R01, '0');
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_SIGNED(L01, R01, '0');
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_UNSIGNED(L01, not(R01), '1');
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_SIGNED(L01, not(R01), '1');
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) :=
(others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := TO_01(L, 'X');
XR := TO_01(R, 'X');
if ((XL(L_LEFT)='X') or (XR(R_LEFT)='X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FQUOT := (others => 'X');
return FQUOT;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: SIGNED(L_LEFT downto 0) is L;
alias XXR: SIGNED(R_LEFT downto 0) is R;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FQUOT := (others => 'X');
return SIGNED(FQUOT);
end if;
if XL(XL'LEFT)='1' then
XNUM := UNSIGNED(-XL);
QNEG := TRUE;
else
XNUM := UNSIGNED(XL);
end if;
if XR(XR'LEFT)='1' then
XDENOM := UNSIGNED(-XR);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(0)/='X'
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(0)/='X'
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: SIGNED(L_LEFT downto 0) is L;
alias XXR: SIGNED(R_LEFT downto 0) is R;
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
XNUM := UNSIGNED(TO_01(XXL, 'X'));
XDENOM := UNSIGNED(TO_01(XXR, 'X'));
if ((XNUM(XNUM'LEFT)='X') or (XDENOM(XDENOM'LEFT)='X')) then
FREMAIN := (others => 'X');
return SIGNED(FREMAIN);
end if;
if XNUM(XNUM'LEFT)='1' then
XNUM := UNSIGNED(-SIGNED(XNUM));
RNEG := TRUE;
else
XNUM := UNSIGNED(XNUM);
end if;
if XDENOM(XDENOM'LEFT)='1' then
XDENOM := UNSIGNED(-SIGNED(XDENOM));
else
XDENOM := UNSIGNED(XDENOM);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := L rem XR;
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := XL rem R;
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: SIGNED(L_LEFT downto 0) is L;
alias XXR: SIGNED(R_LEFT downto 0) is R;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FREMAIN := (others => 'X');
return SIGNED(FREMAIN);
end if;
if XL(XL'LEFT)='1' then
XNUM := UNSIGNED(-XL);
else
XNUM := UNSIGNED(XL);
end if;
if XR(XR'LEFT)='1' then
XDENOM := UNSIGNED(-XR);
RNEG := TRUE;
else
XDENOM := UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'LENGTH), R01);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R01'LENGTH), R01);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R01'LENGTH), R01);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L01, TO_SIGNED(R, L01'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'LENGTH), R01);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'LENGTH), R01);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R01'LENGTH), R01);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L01, TO_SIGNED(R, L01'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R01'LENGTH), R01);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R01'LENGTH), R01));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
--START-!V87
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--END-!V87
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XXARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable XARG: UNSIGNED(ARG_LEFT downto 0);
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
XARG := TO_01(XXARG, 'X');
if (XARG(XARG'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
variable XARG: SIGNED(ARG'LENGTH-1 downto 0);
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
XARG := TO_01(ARG, 'X');
if (XARG(XARG'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity WARNING;
return 0;
end if;
if XARG(XARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(XARG));
else
return (- (TO_INTEGER(UNSIGNED(- (XARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: STD_LOGIC := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_STD.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(STD_LOGIC_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R));
return RESULT;
end "xor";
--START-!V87
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R));
return RESULT;
end "xnor";
--END-!V87
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(STD_LOGIC_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R));
return RESULT;
end "xor";
--START-!V87
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R));
return RESULT;
end "xnor";
--END-!V87
--============================================================================
-- support constants for STD_MATCH:
type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN;
constant MATCH_TABLE: BOOLEAN_TABLE := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | U |
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | X |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | 0 |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | 1 |
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | Z |
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | W |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | L |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | H |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE) -- | - |
);
-- Id: M.1
function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN is
variable VALUE: STD_ULOGIC;
begin
return MATCH_TABLE(L, R);
end STD_MATCH;
-- Id: M.2
function STD_MATCH (L, R: UNSIGNED) return BOOLEAN is
alias LV: UNSIGNED(1 to L'LENGTH) is L;
alias RV: UNSIGNED(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
-- Id: M.3
function STD_MATCH (L, R: SIGNED) return BOOLEAN is
alias LV: SIGNED(1 to L'LENGTH) is L;
alias RV: SIGNED(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
-- Id: M.4
function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN is
alias LV: STD_LOGIC_VECTOR(1 to L'LENGTH) is L;
alias RV: STD_LOGIC_VECTOR(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
-- Id: M.5
function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN is
alias LV: STD_ULOGIC_VECTOR(1 to L'LENGTH) is L;
alias RV: STD_ULOGIC_VECTOR(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED is
variable RESULT: UNSIGNED(S'LENGTH-1 downto 0);
variable BAD_ELEMENT: BOOLEAN := FALSE;
alias XS: UNSIGNED(S'LENGTH-1 downto 0) is S;
begin
if (S'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAU"
severity WARNING;
return NAU;
end if;
for I in RESULT'RANGE loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := TRUE;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'RANGE loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end TO_01;
-- Id: T.2
function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED is
variable RESULT: SIGNED(S'LENGTH-1 downto 0);
variable BAD_ELEMENT: BOOLEAN := FALSE;
alias XS: SIGNED(S'LENGTH-1 downto 0) is S;
begin
if (S'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAS"
severity WARNING;
return NAS;
end if;
for I in RESULT'RANGE loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := TRUE;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'RANGE loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end TO_01;
--============================================================================
end NUMERIC_STD;
|
gpl-2.0
|
ed0527335cc38be7dbf67f0855d791f0
| 0.570569 | 3.632 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult-b.vhd
| 4 | 3,134 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mult-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of multiplier is
begin
behavior : process (a, b) is
constant Tpd_in_out : time := 40 ns;
variable negative_result : boolean;
variable op1 : std_ulogic_vector(15 downto 0);
variable op2 : std_ulogic_vector(15 downto 0);
variable result : std_ulogic_vector(31 downto 0);
variable carry_in, carry : std_ulogic;
begin
op1 := to_X01(a);
op2 := to_X01(b);
-- make both operands positive, remembering sign of result
negative_result := (op1(15) = '1') xor (op2(15) = '1');
if (op1(15) = '1') then
carry := '1';
for index in 0 to 15 loop
carry_in := carry;
carry := carry_in and not op1(index);
op1(index) := not op1(index) xor carry_in;
end loop;
end if;
if (op2(15) = '1') then
carry := '1';
for index in 0 to 15 loop
carry_in := carry;
carry := carry_in and not op2(index);
op2(index) := not op2(index) xor carry_in;
end loop;
end if;
-- do long multiplication
result := (others => '0');
for count in 0 to 15 loop
carry := '0';
if (op2(count) = '1') then
for index in 0 to 15 loop
carry_in := carry;
carry := (result(index+count) and op1(index))
or (carry_in and (result(index+count) xor op1(index)));
result(index+count) := result(index+count) xor op1(index) xor carry_in;
end loop;
result(count+16) := carry;
end if;
end loop;
-- result now contains unsigned product, with binary point
-- between bits 30 and 29. assign output with sign adjusted.
if negative_result then
carry := '1';
for index in 0 to 31 loop
carry_in := carry;
carry := carry_in and not result(index);
result(index) := not result(index) xor carry_in;
end loop;
end if;
p <= result after Tpd_in_out;
end process behavior;
end architecture behavioral;
|
gpl-2.0
|
119027d1a784550303bbfe3bb5a657df
| 0.565731 | 3.957071 | false | false | false | false |
peteut/ghdl
|
libraries/ieee/numeric_std.vhdl
| 5 | 34,294 |
-- --------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_STD)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_STD. The NUMERIC_STD package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
--
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- Version: 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
--============================================================================
-- Arithmetic Operators:
--===========================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED;R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of SIZE L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of SIZE R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost
-- element, ARG'LEFT. The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED
-- vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED
-- vector COUNT times.
--============================================================================
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --!V87
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --!V87
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --!V87
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --!V87
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --!V87
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --!V87
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --!V87
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --!V87
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified SIZE.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --!V87
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --!V87
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Match Functions
--============================================================================
-- Id: M.1
function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.2
function STD_MATCH (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.3
function STD_MATCH (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.4
function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.5
function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED;
-- Result subtype: UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- Id: T.2
function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED;
-- Result subtype: SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
end NUMERIC_STD;
|
gpl-2.0
|
58c938859f3f988731543dbdb06a4182
| 0.56211 | 4.202696 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_07.vhd
| 4 | 2,581 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_07.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
use work.MVL4.all;
entity ROM is
port ( a : in MVL4_ulogic_vector(15 downto 0);
d : inout MVL4_logic_vector(7 downto 0);
rd : in MVL4_ulogic );
end entity ROM;
-- not in book
architecture behavioral of ROM is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
use work.MVL4.all;
entity SIMM is
port ( a : in MVL4_ulogic_vector(9 downto 0);
d : inout MVL4_logic_vector(31 downto 0);
ras, cas, we, cs : in MVL4_ulogic );
end entity SIMM;
-- not in book
architecture behavioral of SIMM is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
-- not in book
use work.MVL4.all;
entity memory_subsystem is
end entity memory_subsystem;
-- end not in book
architecture detailed of memory_subsystem is
signal internal_data : MVL4_logic_vector(31 downto 0);
-- . . .
-- not in book
signal internal_addr : MVL4_ulogic_vector(31 downto 0);
signal main_mem_addr : MVL4_ulogic_vector(9 downto 0);
signal ROM_select : MVL4_ulogic;
-- end not in book
begin
boot_ROM : entity work.ROM(behavioral)
port map ( a => internal_addr(15 downto 0),
d => internal_data(7 downto 0),
rd => ROM_select );
main_mem : entity work.SIMM(behavioral)
port map ( a => main_mem_addr, d => internal_data, -- . . . );
-- not in book
ras => '0', cas => '0', we => '0', cs => '0' );
-- end not in book
-- . . .
end architecture detailed;
|
gpl-2.0
|
b7d517122bc8de96ac2b04bcabedc721
| 0.598218 | 3.806785 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2281.vhd
| 4 | 2,473 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2281.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02281ent IS
END c07s02b06x00p14n01i02281ent;
ARCHITECTURE c07s02b06x00p14n01i02281arch OF c07s02b06x00p14n01i02281ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- Local declarations.
variable INTV : INTEGER;
variable DISTV : DISTANCE;
variable TIMEV : TIME;
BEGIN
-- Test multiplying two different physical types.
INTV := DISTV * TIMEV; -- ERROR
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02281 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02281arch;
|
gpl-2.0
|
63840f20000806ebf34edf6e66a63a6d
| 0.585119 | 4.074135 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_03.vhd
| 4 | 2,656 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
library ieee; use ieee.std_logic_1164.all;
entity add_and_sub is
port ( a, b, c : in natural;
y : out natural;
ovf : out std_ulogic );
end entity add_and_sub;
--------------------------------------------------
library ieee; use ieee.numeric_std.all;
architecture rtl of add_and_sub is
signal stage2, stage3 : unsigned ( 8 downto 0 );
begin
stage2 <= To_unsigned(a, 9) + to_unsigned(b, 9); -- "+" from numeric_std
stage3 <= stage2 - c; -- "-" from numeric_std
y <= To_integer(stage3) ;
ovf <= stage3(8);
end rtl;
-- end code from book
entity fg_a_03 is
end entity fg_a_03;
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
architecture test of fg_a_03 is
signal a, b, c, y : natural := 0;
signal ovf : std_ulogic;
begin
dut : entity work.add_and_sub
port map ( a, b, c, y, ovf );
stimulus : process is
begin
wait for 10 ns;
a <= 2; b <= 5; c <= 3; wait for 10 ns;
a <= 192; b <= 192; wait for 10 ns;
a <= 10; b <= 11; c <= 22; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
b4e316954a1cc90755afe91b951326d5
| 0.483434 | 4.382838 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/game/random_decoder_fifo.vhd
| 1 | 6,406 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: RANDOM_DECODER_FIFO
-- AUTHORS: Vojtěch Jeřábek <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RANDOM_DECODER_FIFO is
Port(
CLK : in std_logic;
RST : in std_logic;
GENERATE_NEW : in std_logic; -- enable generate one random component
GENERATE_FIVE : in std_logic; -- enable generate five random components
KOMP0 : out std_logic_vector(5 downto 0); -- nejnovejci trubka
KOMP1 : out std_logic_vector(5 downto 0); -- ||
KOMP2 : out std_logic_vector(5 downto 0); -- posouva se dolu
KOMP3 : out std_logic_vector(5 downto 0); -- \/
KOMP4 : out std_logic_vector(5 downto 0) -- nejstarsi trubka, vklada se do hraciho pole
);
end RANDOM_DECODER_FIFO;
architecture Behavioral of RANDOM_DECODER_FIFO is
signal generate_random : std_logic;
signal generate_random_1 : std_logic;
signal generate_random_2 : std_logic;
signal fifo_move : std_logic;
signal generate_random_five : unsigned(11 downto 0);
signal fifo_input : std_logic_vector(3 downto 0);
signal komp0_sig : std_logic_vector(5 downto 0);
signal komp1_sig : std_logic_vector(5 downto 0);
signal komp2_sig : std_logic_vector(5 downto 0);
signal komp3_sig : std_logic_vector(5 downto 0);
signal komp4_sig : std_logic_vector(5 downto 0);
signal komp_sig : std_logic_vector(5 downto 0);
begin
--------------------------------------------------------------------------------
-- vygenerovani 5-ti nahodnych komponent za sebou
process (CLK, RST)
begin
if (RST = '1') then
generate_random_five <= (others=>'0');
generate_random_1 <='0';
elsif(rising_edge(CLK)) then
if (GENERATE_FIVE='1') then
generate_random_five <= "000000000001";
generate_random_1<='0';
else
if (generate_random_five=4096) then
generate_random_five <= (others=>'0');
generate_random_1<='0';
elsif (generate_random_five=0) then
generate_random_1<='0';
generate_random_five <= (others=>'0');
elsif (generate_random_five=237) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=1638) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=2484) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=3186) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=4001) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
else
generate_random_1<='0';
generate_random_five <= generate_random_five + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- vygenerovani 1 nahodne komponenty
process (CLK, RST)
begin
if (RST = '1') then
generate_random_2 <= '0';
elsif (rising_edge(CLK)) then
if (GENERATE_NEW = '1') then
generate_random_2 <= '1';
else
generate_random_2 <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- vygenerovani prirazeni nahodneho cila na KOMP0_sig a posuv ostatnich. KOPM4_sig zanika
process (CLK, RST)
begin
if (RST = '1') then
komp0_sig <= (others=>'0');
komp1_sig <= (others=>'0');
komp2_sig <= (others=>'0');
komp3_sig <= (others=>'0');
komp4_sig <= (others=>'0');
elsif (rising_edge(CLK)) then
if (fifo_move = '1') then
komp0_sig <= komp_sig;
komp1_sig <= komp0_sig;
komp2_sig <= komp1_sig;
komp3_sig <= komp2_sig;
komp4_sig <= komp3_sig;
end if;
end if;
end process;
KOMP0 <= komp0_sig;
KOMP1 <= komp1_sig;
KOMP2 <= komp2_sig;
KOMP3 <= komp3_sig;
KOMP4 <= komp4_sig;
--------------------------------------------------------------------------------
-- prepocet kombinacni logiky nahodneho cisla
with fifo_input select
komp_sig <= "000001" when "0000",
"000001" when "0001",
"010001" when "0010",
"010001" when "0011", --rovne trubky
"000010" when "0100",
"010010" when "0101",
"100010" when "0110",
"110010" when "0111", --zahla trubka
"000011" when "1000",
"000011" when "1001", --kriz, je 2x kvuli lepsi cetnosti
"111111" when "1111",
"000000" when others;
--------------------------------------------------------------------------------
-- instancovani komponenty RANDOM_GENERATOR
random_generator_i: entity work.RANDOM_GENERATOR
generic map (
Number_of_options => 10,
Flip_Flops => 4
)
port map (
CLK => CLK,
RST => RST,
RANDOM_PULSE => generate_random,
RANDOM_OUT => fifo_input,
ENABLE_OUT => fifo_move
);
generate_random <= generate_random_1 OR generate_random_2;
end Behavioral;
|
mit
|
07771a03351055dd8393ca14dcadcdf4
| 0.468999 | 4.277221 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd
| 4 | 1,420 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_accr-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of accumulator_reg is
begin
behavior : process (clk) is
constant Tpd_clk_out : time := 3 ns;
begin
if rising_edge(clk) then
if To_X01(clr) = '1' then
q <= (others => '0') after Tpd_clk_out;
else
q <= d after Tpd_clk_out;
end if;
end if;
end process behavior;
end architecture behavioral;
|
gpl-2.0
|
7aa7c14e16834f02afdada9ad38b9ded
| 0.606338 | 4.139942 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_01.vhd
| 4 | 1,725 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
begin
process_2_a : process is
type t1 is (t1_1, t1_2);
type t2 is (t2_1, t2_2);
type t3 is (t3_1, t3_2);
type t4 is (t4_1, t4_2);
constant v4 : t4 := t4_1;
constant val1 : t1 := t1_1;
constant val2 : t2 := t2_1;
variable var3 : t3 := t3_1;
constant val4 : t4 := t4_1;
-- code from book:
procedure p ( f1 : in t1; f2 : in t2; f3 : out t3; f4 : in t4 := v4 ) is
begin
-- . . .
end procedure p;
-- end of code from book
begin
-- code from book:
p ( val1, val2, var3, val4 );
p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 );
p ( val1, val2, f4 => open, f3 => var3 );
p ( val1, val2, var3 );
-- end of code from book
wait;
end process process_2_a;
end architecture test;
|
gpl-2.0
|
b48ce1725444640bcbc994204f50f11c
| 0.609855 | 3.298279 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc494.vhd
| 4 | 7,189 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc494.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p01n01i00494ent IS
END c03s02b02x00p01n01i00494ent;
ARCHITECTURE c03s02b02x00p01n01i00494arch OF c03s02b02x00p01n01i00494ent IS
type colors is (orange,blue,red,black,white,magenta,ochre,yellow,green);
type TR is RECORD
i : integer;
ch : character;
bi : bit;
bool : boolean;
bv : bit_vector (3000 to 3007);
r : real;
str : STRING (1 to 7);
ti : TIME;
color : colors;
END RECORD;
type TY is array(integer range <>) of TR;
subtype T0 is TY (1 to 10);
subtype T1 is TY (1 to 6);
subtype T2 is TY (5 to 7);
function FUNC1(array1: T0) return T1 is -- formal param object class defaults to constant
variable array2:T1;
begin -- procedure FUNC1
array2 := array1(6) & array1(1) & array1(3) & array1(2) & array1(6) & array1(10); --indexed names
return array2;
end FUNC1;
function FUNC2(array1: TY) return T1 is
variable array2:T1;
begin -- procedure FUNC2
array2 := array1(6) & array1(1) & array1(3) & array1(2) & array1(6) & array1(10); --indexed names
return array2;
end FUNC2;
function FUNC3(array1: T0) return T2 is
variable array2:T2;
begin -- procedure FUNC3
array2 := array1(5 to 6) & array1(1 to 1); --slices
return array2;
end FUNC3;
function FUNC4(array1: T2) return T2 is
variable array2:T2;
begin -- procedure FUNC4
array2 := array1 (7 to 7) & array1(5 to 5) &
array1(5 to 5); --slices
return array2;
end FUNC4;
BEGIN
TESTING: PROCESS
variable arr1: T0;
variable v1,v2:T1;
variable v3,v4:T2;
BEGIN
arr1(1) := (1,'a','0',false,"00000001",1.1,"one ",1.1 ms,orange);
arr1(2) := (2,'b','1',true, "00000010",2.2,"two ",2.2 ms,blue);
arr1(3) := (3,'c','0',false,"00000011",3.3,"three ",3.3 ms,red);
arr1(4) := (4,'d','1',true, "00000100",4.4,"four ",4.4 ms,black);
arr1(5) := (5,'e','0',false,"00000101",5.5,"five ",5.5 ms,white);
arr1(6) := (6,'f','1',true, "00000110",6.6,"six ",6.6 ms,magenta);
arr1(7) := (7,'g','0',false,"00000111",7.7,"seven ",7.7 ms,ochre);
arr1(8) := (8,'h','1',true, "00001000",8.8,"eight ",8.8 ms,yellow);
arr1(9) := (9,'i','0',false,"00001001",9.9,"nine ",9.9 ms,green);
arr1(10):=(10,'j','1',true, "00001010",10.01,"ten ",10.01 ms,white);
wait for 1 ns;
v1 := FUNC1(arr1);
v2 := FUNC2(arr1);
v3 := FUNC3(arr1);
v4 := FUNC4(v3);
wait for 1 ns;
assert NOT( (v1(1) = (6,'f','1',true, "00000110",6.6,"six ",6.6 ms,magenta)) AND
(v1(2) = (1,'a','0',false,"00000001",1.1,"one ",1.1 ms,orange)) AND
(v1(3) = (3,'c','0',false,"00000011",3.3,"three ",3.3 ms,red)) AND
(v1(4) = (2,'b','1',true, "00000010",2.2,"two ",2.2 ms,blue)) AND
(v1(5) = (6,'f','1',true, "00000110",6.6,"six ",6.6 ms,magenta)) AND
(v1(6) = (10,'j','1',true, "00001010",10.01,"ten ",10.01 ms,white)) AND
(v2(1) = (6,'f','1',true, "00000110",6.6,"six ",6.6 ms,magenta)) AND
(v2(2) = (1,'a','0',false,"00000001",1.1,"one ",1.1 ms,orange)) AND
(v2(3) = (3,'c','0',false,"00000011",3.3,"three ",3.3 ms,red)) AND
(v2(4) = (2,'b','1',true, "00000010",2.2,"two ",2.2 ms,blue)) AND
(v2(5) = (6,'f','1',true, "00000110",6.6,"six ",6.6 ms,magenta)) AND
(v2(6) = (10,'j','1',true, "00001010",10.01,"ten ",10.01 ms,white)) AND
(v3(5) = (5,'e','0',false,"00000101",5.5,"five ",5.5 ms,white)) AND
(v3(6) = (6,'f','1',true, "00000110",6.6,"six ",6.6 ms,magenta)) AND
(v3(7) = (1,'a','0',false,"00000001",1.1,"one ",1.1 ms,orange)) AND
(v4(5) = (1,'a','0',false,"00000001",1.1,"one ",1.1 ms,orange)) AND
(v4(6) = (5,'e','0',false,"00000101",5.5,"five ",5.5 ms,white)) AND
(v4(7) = (5,'e','0',false,"00000101",5.5,"five ",5.5 ms,white)))
report "***PASSED TEST: c03s02b02x00p01n01i00494"
severity NOTE;
assert ( (v1(1) = (6,'f','1',true, "00000110",6.6,"six ",6.6 ms,magenta)) AND
(v1(2) = (1,'a','0',false,"00000001",1.1,"one ",1.1 ms,orange)) AND
(v1(3) = (3,'c','0',false,"00000011",3.3,"three ",3.3 ms,red)) AND
(v1(4) = (2,'b','1',true, "00000010",2.2,"two ",2.2 ms,blue)) AND
(v1(5) = (6,'f','1',true, "00000110",6.6,"six ",6.6 ms,magenta)) AND
(v1(6) = (10,'j','1',true, "00001010",10.01,"ten ",10.01 ms,white)) AND
(v2(1) = (6,'f','1',true, "00000110",6.6,"six ",6.6 ms,magenta)) AND
(v2(2) = (1,'a','0',false,"00000001",1.1,"one ",1.1 ms,orange)) AND
(v2(3) = (3,'c','0',false,"00000011",3.3,"three ",3.3 ms,red)) AND
(v2(4) = (2,'b','1',true, "00000010",2.2,"two ",2.2 ms,blue)) AND
(v2(5) = (6,'f','1',true, "00000110",6.6,"six ",6.6 ms,magenta)) AND
(v2(6) = (10,'j','1',true, "00001010",10.01,"ten ",10.01 ms,white)) AND
(v3(5) = (5,'e','0',false,"00000101",5.5,"five ",5.5 ms,white)) AND
(v3(6) = (6,'f','1',true, "00000110",6.6,"six ",6.6 ms,magenta)) AND
(v3(7) = (1,'a','0',false,"00000001",1.1,"one ",1.1 ms,orange)) AND
(v4(5) = (1,'a','0',false,"00000001",1.1,"one ",1.1 ms,orange)) AND
(v4(6) = (5,'e','0',false,"00000101",5.5,"five ",5.5 ms,white)) AND
(v4(7) = (5,'e','0',false,"00000101",5.5,"five ",5.5 ms,white)))
report "***FAILED TEST:c03s02b02x00p01n01i00494 - Problem assigning record subelements in function."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p01n01i00494arch;
|
gpl-2.0
|
91aa1d9cdd1c737c11c66761b2f48196
| 0.520796 | 2.847129 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug20312/repro.vhdl
| 3 | 1,309 |
entity pipeline is
generic (width : natural; depth : natural);
port (i : bit_vector (1 to width);
o : out bit_vector (1 to width);
clk : bit);
end pipeline;
architecture behav of pipeline is
type pipe is array (1 to depth) of bit_vector (1 to width);
begin
process (clk) is
variable tmp : pipe;
begin
if clk = '1' then
o <= tmp (1);
tmp (1 to depth - 1) := tmp (2 to depth);
tmp (depth) := i;
end if;
end process;
end behav;
entity tb is
end tb;
architecture behav of tb is
constant width : natural := 4;
signal i : bit_vector (1 to width);
signal o : bit_vector (1 to width);
signal clk : bit;
begin
p : entity work.pipeline
generic map (width => width, depth => 3)
port map (i => i, o => o, clk => clk);
process is
begin
i <= "1011";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1010";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1001";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1000";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
i <= "1011";
clk <= '0';
wait for 0 ns;
clk <= '1';
wait for 0 ns;
wait;
end process;
end behav;
|
gpl-2.0
|
73483707a70fc64236fee70f664ba2e1
| 0.513369 | 3.280702 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/count2-1.vhd
| 4 | 1,949 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end entity D_flipflop;
architecture behavioral of D_flipflop is
begin
q <= d when clk'event and clk = '1';
end architecture behavioral;
entity inverter is
port ( a : in bit; y : out bit );
end entity inverter;
architecture behavioral of inverter is
begin
y <= not a;
end architecture behavioral;
-- code from book
entity count2 is
port ( clk : in bit; q0, q1 : buffer bit );
end entity count2;
--------------------------------------------------
architecture buffered_outputs of count2 is
component D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end component D_flipflop;
component inverter is
port ( a : in bit; y : out bit );
end component inverter;
signal q0_n, q1_n : bit;
begin
bit0 : component D_flipflop
port map ( clk => clk, d => q0_n, q => q0 );
inv0 : component inverter
port map ( a => q0, y => q0_n );
bit1 : component D_flipflop
port map ( clk => q0_n, d => q1_n, q => q1 );
inv1 : component inverter
port map ( a => q1, y => q1_n );
end architecture buffered_outputs;
-- end code from book
|
gpl-2.0
|
5c9ef7991f736484bd2198ffcb20345b
| 0.664956 | 3.712381 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc472.vhd
| 4 | 4,875 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc472.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00472ent IS
END c03s02b01x01p19n01i00472ent;
ARCHITECTURE c03s02b01x01p19n01i00472arch OF c03s02b01x01p19n01i00472ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type array_rec_cons is array (integer range <>) of record_cons_array;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C66 : array_rec_cons (0 to 7) := (others => C51);
function complex_scalar(s : array_rec_cons(0 to 7)) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_cons is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_cons(0 to 7);
signal S2 : array_rec_cons(0 to 7);
signal S3 : array_rec_cons(0 to 7):= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00472"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00472 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00472arch;
|
gpl-2.0
|
3aa2ace53309aa9f3ca7b1d5321b0da2
| 0.619897 | 3.624535 | false | false | false | false |
mruizglz/UPM-ES-cyclonevbsp
|
cyclonevbsp/soc_system_top.vhd
| 1 | 18,643 |
-- #############################################################################
-- soc_system_top.vhd
--
-- BOARD : DE1-SoC from Terasic
-- Authors : Antonio Carpeño and Mariano Ruiz
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity soc_system_top is
port(
-- -- ADC
-- ADC_CS_n : out std_logic;
-- ADC_DIN : out std_logic;
-- ADC_DOUT : in std_logic;
-- ADC_SCLK : out std_logic;
-- -- Audio
-- AUD_ADCDAT : in std_logic;
-- AUD_ADCLRCK : inout std_logic;
-- AUD_BCLK : inout std_logic;
-- AUD_DACDAT : out std_logic;
-- AUD_DACLRCK : inout std_logic;
-- AUD_XCK : out std_logic;
-- -- CLOCK
CLOCK_50 : in std_logic;
-- CLOCK2_50 : in std_logic;
-- CLOCK3_50 : in std_logic;
-- CLOCK4_50 : in std_logic;
-- -- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- -- I2C for Audio and Video-In
-- FPGA_I2C_SCLK : out std_logic;
-- FPGA_I2C_SDAT : inout std_logic;
-- -- SEG7
HEX0_N : out std_logic_vector(6 downto 0);
HEX1_N : out std_logic_vector(6 downto 0);
HEX2_N : out std_logic_vector(6 downto 0);
HEX3_N : out std_logic_vector(6 downto 0);
HEX4_N : out std_logic_vector(6 downto 0);
HEX5_N : out std_logic_vector(6 downto 0);
-- -- IR
-- IRDA_RXD : in std_logic;
-- IRDA_TXD : out std_logic;
-- -- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- -- LED
LEDR : out std_logic_vector(9 downto 0);
-- -- PS2
-- PS2_CLK : inout std_logic;
-- PS2_CLK2 : inout std_logic;
-- PS2_DAT : inout std_logic;
-- PS2_DAT2 : inout std_logic;
-- -- SW
SW : in std_logic_vector(9 downto 0);
-- -- Video-In
-- TD_CLK27 : inout std_logic;
-- TD_DATA : out std_logic_vector(7 downto 0);
-- TD_HS : out std_logic;
-- TD_RESET_N : out std_logic;
-- TD_VS : out std_logic;
-- -- VGA
-- VGA_B : out std_logic_vector(7 downto 0);
-- VGA_BLANK_N : out std_logic;
-- VGA_CLK : out std_logic;
-- VGA_G : out std_logic_vector(7 downto 0);
-- VGA_HS : out std_logic;
-- VGA_R : out std_logic_vector(7 downto 0);
-- VGA_SYNC_N : out std_logic;
-- VGA_VS : out std_logic;
-- -- GPIO_0
-- GPIO_0 : inout std_logic_vector(35 downto 0);
-- -- GPIO_1
-- GPIO_1 : inout std_logic_vector(35 downto 0);
-- -- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity soc_system_top;
architecture rtl of soc_system_top is
signal hps_fpga_reset_n: std_logic;
signal displays_ena_n: std_logic_vector(5 downto 0);
component soc_system is
port(
clk_clk : in std_logic := 'X';
hps_0_h2f_reset_reset_n : out std_logic; -- reset_n
hps_0_io_hps_io_emac1_inst_TX_CLK : out std_logic;
hps_0_io_hps_io_emac1_inst_TX_CTL : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD0 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD1 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD2 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD3 : out std_logic;
hps_0_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDC : out std_logic;
hps_0_io_hps_io_qspi_inst_CLK : out std_logic;
hps_0_io_hps_io_qspi_inst_SS0 : out std_logic;
hps_0_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_CLK : out std_logic;
hps_0_io_hps_io_sdio_inst_CMD : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_CLK : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_STP : out std_logic;
hps_0_io_hps_io_usb1_inst_DIR : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_NXT : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D4 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D5 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D6 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D7 : inout std_logic := 'X';
hps_0_io_hps_io_spim1_inst_CLK : out std_logic;
hps_0_io_hps_io_spim1_inst_MOSI : out std_logic;
hps_0_io_hps_io_spim1_inst_MISO : in std_logic := 'X';
hps_0_io_hps_io_spim1_inst_SS0 : out std_logic;
hps_0_io_hps_io_uart0_inst_RX : in std_logic := 'X';
hps_0_io_hps_io_uart0_inst_TX : out std_logic;
hps_0_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X';
hps_0_ddr_mem_a : out std_logic_vector(14 downto 0); -- mem_a
hps_0_ddr_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
hps_0_ddr_mem_ck : out std_logic; -- mem_ck
hps_0_ddr_mem_ck_n : out std_logic; -- mem_ck_n
hps_0_ddr_mem_cke : out std_logic; -- mem_cke
hps_0_ddr_mem_cs_n : out std_logic; -- mem_cs_n
hps_0_ddr_mem_ras_n : out std_logic; -- mem_ras_n
hps_0_ddr_mem_cas_n : out std_logic; -- mem_cas_n
hps_0_ddr_mem_we_n : out std_logic; -- mem_we_n
hps_0_ddr_mem_reset_n : out std_logic; -- mem_reset_n
hps_0_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
hps_0_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
hps_0_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
hps_0_ddr_mem_odt : out std_logic; -- mem_odt
hps_0_ddr_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
hps_0_ddr_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X'
);
end component soc_system;
begin
soc_system_inst : component soc_system
port map(
clk_clk => CLOCK_50,
hps_0_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK,
hps_0_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN,
hps_0_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0),
hps_0_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1),
hps_0_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2),
hps_0_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3),
hps_0_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK,
hps_0_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV,
hps_0_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0),
hps_0_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1),
hps_0_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2),
hps_0_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3),
hps_0_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO,
hps_0_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC,
hps_0_io_hps_io_qspi_inst_CLK => HPS_FLASH_DCLK,
hps_0_io_hps_io_qspi_inst_SS0 => HPS_FLASH_NCSO,
hps_0_io_hps_io_qspi_inst_IO0 => HPS_FLASH_DATA(0),
hps_0_io_hps_io_qspi_inst_IO1 => HPS_FLASH_DATA(1),
hps_0_io_hps_io_qspi_inst_IO2 => HPS_FLASH_DATA(2),
hps_0_io_hps_io_qspi_inst_IO3 => HPS_FLASH_DATA(3),
hps_0_io_hps_io_sdio_inst_CLK => HPS_SD_CLK,
hps_0_io_hps_io_sdio_inst_CMD => HPS_SD_CMD,
hps_0_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0),
hps_0_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1),
hps_0_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2),
hps_0_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3),
hps_0_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT,
hps_0_io_hps_io_usb1_inst_STP => HPS_USB_STP,
hps_0_io_hps_io_usb1_inst_DIR => HPS_USB_DIR,
hps_0_io_hps_io_usb1_inst_NXT => HPS_USB_NXT,
hps_0_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0),
hps_0_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1),
hps_0_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2),
hps_0_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3),
hps_0_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4),
hps_0_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5),
hps_0_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6),
hps_0_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7),
hps_0_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK,
hps_0_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI,
hps_0_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO,
hps_0_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS,
hps_0_io_hps_io_uart0_inst_RX => HPS_UART_RX,
hps_0_io_hps_io_uart0_inst_TX => HPS_UART_TX,
hps_0_io_hps_io_i2c0_inst_SDA => HPS_I2C1_SDAT,
hps_0_io_hps_io_i2c0_inst_SCL => HPS_I2C1_SCLK,
hps_0_io_hps_io_i2c1_inst_SDA => HPS_I2C2_SDAT,
hps_0_io_hps_io_i2c1_inst_SCL => HPS_I2C2_SCLK,
hps_0_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N,
hps_0_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N,
hps_0_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO,
hps_0_io_hps_io_gpio_inst_GPIO48 => HPS_I2C_CONTROL,
hps_0_io_hps_io_gpio_inst_GPIO53 => HPS_LED,
hps_0_io_hps_io_gpio_inst_GPIO54 => HPS_KEY_N,
hps_0_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT,
hps_0_ddr_mem_a => HPS_DDR3_ADDR,
hps_0_ddr_mem_ba => HPS_DDR3_BA,
hps_0_ddr_mem_ck => HPS_DDR3_CK_P,
hps_0_ddr_mem_ck_n => HPS_DDR3_CK_N,
hps_0_ddr_mem_cke => HPS_DDR3_CKE,
hps_0_ddr_mem_cs_n => HPS_DDR3_CS_N,
hps_0_ddr_mem_ras_n => HPS_DDR3_RAS_N,
hps_0_ddr_mem_cas_n => HPS_DDR3_CAS_N,
hps_0_ddr_mem_we_n => HPS_DDR3_WE_N,
hps_0_ddr_mem_reset_n => HPS_DDR3_RESET_N,
hps_0_ddr_mem_dq => HPS_DDR3_DQ,
hps_0_ddr_mem_dqs => HPS_DDR3_DQS_P,
hps_0_ddr_mem_dqs_n => HPS_DDR3_DQS_N,
hps_0_ddr_mem_odt => HPS_DDR3_ODT,
hps_0_ddr_mem_dm => HPS_DDR3_DM,
hps_0_ddr_oct_rzqin => HPS_DDR3_RZQ,
reset_reset_n => '1'
);
end;
|
gpl-3.0
|
4460ff3489149c17bd59e64f4cd01824
| 0.422755 | 3.188847 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd
| 4 | 2,152 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book:
entity DRAM_controller is
port ( rd, wr, mem : in bit;
ras, cas, we, ready : out bit );
end entity DRAM_controller;
-- end of code from book
----------------------------------------------------------------
architecture fpld of DRAM_controller is
begin
end architecture fpld;
----------------------------------------------------------------
entity inline_18 is
end entity inline_18;
----------------------------------------------------------------
architecture test of inline_18 is
begin
block_4_a : block is
signal cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy : bit;
begin
-- code from book:
main_mem_controller : entity work.DRAM_controller(fpld)
port map ( cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy );
-- end of code from book
end block block_4_a;
----------------
block_4_b : block is
signal cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy : bit;
begin
-- code from book:
main_mem_controller : entity work.DRAM_controller(fpld)
port map ( rd => cpu_rd, wr => cpu_wr,
mem => cpu_mem, ready => cpu_rdy,
ras => mem_ras, cas => mem_cas, we => mem_we );
-- end of code from book
end block block_4_b;
end architecture test;
|
gpl-2.0
|
764665a8fbf2ad928e072c3d741db536
| 0.588755 | 3.955882 | false | false | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/extractor.vhd
| 1 | 625 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity extractor is
port (
ext_in:in std_logic_vector(47 downto 0 );
ext_out:out std_logic_vector(22 downto 0 )
);
end extractor ;
architecture behaviour of extractor is
begin
process (ext_in)
begin
if (ext_in(47 downto 46)="01")then
ext_out<=ext_in(45 downto 23);
elsif(ext_in(47 downto 46)="10")then
ext_out<=ext_in(46 downto 24);
elsif(ext_in(47 downto 46)="11")then
ext_out<=ext_in (46 downto 24);
else
ext_out<=(others=>'0');
end if ;
end process;
end behaviour;
|
mit
|
4e600e907befab3e7a9cbd728f8adaeb
| 0.6272 | 2.934272 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.d-DataRam.vhd
| 1 | 3,930 |
--------------------------------------------------------------------------------
-- FILE: DataRam
-- DESC: Data Ram, Sequencial structure. Sychronize when clk FALLING edge.
--
-- Author:
-- Create: 2015-05-24
-- Update: 2015-10-03
-- Status: TESTED
--
-- NOTE 1:
-- Control Word:
-- drcw(3) : Write enable. 1--WRITE, 0--READ
-- drcw(2:1) : Data type. 00--WORD(32), 01--HALF WORD(16), 10--BYTE(8)
-- drcw(0) : Sign flag. 1--signed, 0--unsigned
--
-- NOTE 2:
-- Memory organized as BIG ENDIAN
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DataRam is
generic (
DRCW_SIZE : integer := C_CTR_DRCW_SIZE; -- Data RAM Control Word: R/W
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
rst : in std_logic;
clk : in std_logic;
en : in std_logic;
addr : in std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
din : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
dout : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
dr_cw : in std_logic_vector(DRCW_SIZE-1 downto 0):=(others=>'0')
);
end DataRam;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture data_ram_arch of DataRam is
constant DRAM_SIZE : integer := C_RAM_DRAM_SIZE;
type DRam_t is array (0 to DRAM_SIZE-1) of std_logic_vector(7 downto 0);
signal data_area : DRam_t;
begin
----------------------------------------------------------------------------
-- FIXME BUG
-- In the case LOAD AFTER STORE, If control word is slower than din, then the
-- data area will be set to incorrect value.
----------------------------------------------------------------------------
PDR0: process(rst, clk)
variable addr_ph : integer := 0;
begin
if rst='0' then
for i in 0 to DRAM_SIZE-1 loop
data_area(i) <= (others=>'0');
end loop;
dout <= (others => '0');
else
-- if en='1' then
if clk'event and clk='0' then
addr_ph := to_integer(unsigned(addr(MyLog2Ceil(DRAM_SIZE)-1 downto 0)));
if addr_ph >= DRAM_SIZE-4 then
addr_ph := DRAM_SIZE-4;
end if;
if dr_cw(3)='0' then -- READ
if dr_cw(2 downto 1)="01" then -- HALF WORD
dout(7 downto 0) <= data_area(addr_ph+1);
dout(15 downto 8) <= data_area(addr_ph);
if (dr_cw(0)='0') then
dout(DATA_SIZE-1 downto 16) <= (others => '0');
else
dout(DATA_SIZE-1 downto 16) <= (others => data_area(addr_ph)(7));
end if;
elsif dr_cw(2 downto 1)="10" then -- BYTE
dout(7 downto 0) <= data_area(addr_ph);
if (dr_cw(0)='0') then
dout(DATA_SIZE-1 downto 8) <= (others => '0');
else
dout(DATA_SIZE-1 downto 8) <= (others => data_area(addr_ph)(7));
end if;
else -- WORD
dout(7 downto 0) <= data_area(addr_ph+3);
dout(15 downto 8) <= data_area(addr_ph+2);
dout(23 downto 16) <= data_area(addr_ph+1);
dout(31 downto 24) <= data_area(addr_ph);
end if;
else -- WRITE
if dr_cw(2 downto 1)="01" then -- HALF WORD
data_area(addr_ph+1) <= din(7 downto 0);
data_area(addr_ph) <= din(15 downto 8);
elsif dr_cw(2 downto 1)="10" then -- BYTE
data_area(addr_ph) <= din(7 downto 0);
else -- WORD
data_area(addr_ph+3) <= din(7 downto 0);
data_area(addr_ph+2) <= din(15 downto 8);
data_area(addr_ph+1) <= din(23 downto 16);
data_area(addr_ph) <= din(31 downto 24);
end if;
end if;
end if;
-- end if;
end if;
end process;
end data_ram_arch;
|
mit
|
6e984dc6993d5b4df91be775edf839b4
| 0.500509 | 3.174475 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_113.vhd
| 1 | 4,578 |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_113 is
generic (
NUM_BITS : positive := 113 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_113;
-----------------------------------------------------------
architecture behave of serial_multiplier_113 is
-----------------------------------------------------------
-- m = 113 x113 + x9 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000001";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(6 downto 0); -- 8-bit counter, controling the number of iterations: m
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "1110000"; -- m-1 value, in this case, it is 112, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
if counter = "0000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
Done <= '1';
else
bx_int <= bx_shift;
end if;
when END_STATE =>
CurrentState <= END_STATE;
Done <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
e52add845257ff3de4a3e3a000d6b625
| 0.476627 | 4.250696 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2404.vhd
| 4 | 1,887 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2404.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n05i02404ent IS
END c07s03b02x00p08n05i02404ent;
ARCHITECTURE c07s03b02x00p08n05i02404arch OF c07s03b02x00p08n05i02404ent IS
BEGIN
TESTING: PROCESS
type arr is array (1 to 3) of integer;
constant y: arr := (1 => 12, others => 0);
BEGIN
assert NOT(y(1)=12 and y(2)=0 and y(3)=0)
report "***PASSED TEST: c07s03b02x00p08n05i02404"
severity NOTE;
assert (y(1)=12 and y(2)=0 and y(3)=0)
report "***FAILED TEST: c07s03b02x00p08n05i02404 - The element association with the choice others is allowed in a record aggregate and if it specifies all the remaining element."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n05i02404arch;
|
gpl-2.0
|
b5789d271bb6640a856273569c015f2a
| 0.671966 | 3.594286 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2000.vhd
| 4 | 2,132 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2000.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n02i02000ent IS
END c07s02b02x00p07n02i02000ent;
ARCHITECTURE c07s02b02x00p07n02i02000arch OF c07s02b02x00p07n02i02000ent IS
BEGIN
TESTING: PROCESS
type ENUM is ( ONE, TWO, THREE, FOUR, FIVE );
type NEW_INTEGER is range integer'left to integer'right;
type UN_INT_ARRAY is array ( ENUM range <>) of NEW_INTEGER;
subtype INT_ARRAY is UN_INT_ARRAY( ONE to TWO );
variable k : integer := 0;
variable m : INT_ARRAY:= (1,2);
BEGIN
if (m = INT_ARRAY'(1,2)) then
k := 5;
else
k := 0;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n02i02000"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n02i02000 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n02i02000arch;
|
gpl-2.0
|
e87238b47c97c2edb198a75a716daa1d
| 0.652439 | 3.656947 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_03.vhd
| 4 | 1,814 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
library ieee; use ieee.numeric_bit.all;
architecture test of inline_03 is
constant T_delay_adder : delay_length := 10 ns;
-- code from book:
function bv_add ( bv1, bv2 : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bit_vector(unsigned(bv1) + unsigned(bv2));
-- end not in book
end function bv_add;
signal source1, source2, sum : bit_vector(0 to 31);
-- end of code from book
begin
-- code from book:
adder : sum <= bv_add(source1, source2) after T_delay_adder;
-- end of code from book
----------------
stimulus : process is
begin
wait for 50 ns;
source1 <= X"00000002"; source2 <= X"00000003"; wait for 50 ns;
source2 <= X"FFFFFFF0"; wait for 50 ns;
source1 <= X"00000010"; wait for 50 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
165c6f093f27e208eda80ae8e3760864
| 0.637817 | 3.986813 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc600.vhd
| 4 | 2,881 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc600.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:40 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:58 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:18 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00600ent IS
END c03s04b01x00p01n01i00600ent;
ARCHITECTURE c03s04b01x00p01n01i00600arch OF c03s04b01x00p01n01i00600ent IS
type time_vector is array (natural range <>) of time;
type time_vector_file is file of time_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : time_vector_file open read_mode is "iofile.27";
variable v : time_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= (1 ns,2 ns,3 ns,4 ns)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00600"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00600 - File reading operation (time_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00600arch;
|
gpl-2.0
|
0d9e325534b99294f7c4937b5667cf50
| 0.561958 | 3.935792 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_113_3.vhd
| 1 | 10,960 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- Sin celda y sin maquina de estados
--------------------------------------------------------
-- x^113 + x ^9 + 1
entity serial_multiplier_113 is
generic (
NUM_BITS : positive := 113 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_113;
-----------------------------------------------------------
architecture behave of serial_multiplier_113 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
--type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
--signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
-- Result of the multiplication
xor_1 <= Cx_int(8) xor Cx_int(NUM_BITS-1);
--Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
bx_int <= Bx_shift; -- Shift Bx to left one position
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
done <= done_int;
cx <= cx_int;
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "00000000"; -- m-1 value, in this case, it is 112, be sure to set the correct value
cx_int <= (others => '0');
Done_int <= '0';
else
if done_int = '0' then
counter <= counter + 1;
Cx_int(0) <= ( Ax(0) and Bx_int(NUM_BITS-1) ) xor Cx_int(NUM_BITS-1);
Cx_int(1) <= ( Ax(1) and Bx_int(NUM_BITS-1) ) xor Cx_int(0);
Cx_int(2) <= ( Ax(2) and Bx_int(NUM_BITS-1) ) xor Cx_int(1);
Cx_int(3) <= ( Ax(3) and Bx_int(NUM_BITS-1) ) xor Cx_int(2);
Cx_int(4) <= ( Ax(4) and Bx_int(NUM_BITS-1) ) xor Cx_int(3);
Cx_int(5) <= ( Ax(5) and Bx_int(NUM_BITS-1) ) xor Cx_int(4);
Cx_int(6) <= ( Ax(6) and Bx_int(NUM_BITS-1) ) xor Cx_int(5);
Cx_int(7) <= ( Ax(7) and Bx_int(NUM_BITS-1) ) xor Cx_int(6);
Cx_int(8) <= ( Ax(8) and Bx_int(NUM_BITS-1) ) xor Cx_int(7);
Cx_int(9) <= ( Ax(9) and Bx_int(NUM_BITS-1) ) xor xor_1;
Cx_int(10) <= ( Ax(10) and Bx_int(NUM_BITS-1) ) xor Cx_int(9);
Cx_int(11) <= ( Ax(11) and Bx_int(NUM_BITS-1) ) xor Cx_int(10);
Cx_int(12) <= ( Ax(12) and Bx_int(NUM_BITS-1) ) xor Cx_int(11);
Cx_int(13) <= ( Ax(13) and Bx_int(NUM_BITS-1) ) xor Cx_int(12);
Cx_int(14) <= ( Ax(14) and Bx_int(NUM_BITS-1) ) xor Cx_int(13);
Cx_int(15) <= ( Ax(15) and Bx_int(NUM_BITS-1) ) xor Cx_int(14);
Cx_int(16) <= ( Ax(16) and Bx_int(NUM_BITS-1) ) xor Cx_int(15);
Cx_int(17) <= ( Ax(17) and Bx_int(NUM_BITS-1) ) xor Cx_int(16);
Cx_int(18) <= ( Ax(18) and Bx_int(NUM_BITS-1) ) xor Cx_int(17);
Cx_int(19) <= ( Ax(19) and Bx_int(NUM_BITS-1) ) xor Cx_int(18);
Cx_int(20) <= ( Ax(20) and Bx_int(NUM_BITS-1) ) xor Cx_int(19);
Cx_int(21) <= ( Ax(21) and Bx_int(NUM_BITS-1) ) xor Cx_int(20);
Cx_int(22) <= ( Ax(22) and Bx_int(NUM_BITS-1) ) xor Cx_int(21);
Cx_int(23) <= ( Ax(23) and Bx_int(NUM_BITS-1) ) xor Cx_int(22);
Cx_int(24) <= ( Ax(24) and Bx_int(NUM_BITS-1) ) xor Cx_int(23);
Cx_int(25) <= ( Ax(25) and Bx_int(NUM_BITS-1) ) xor Cx_int(24);
Cx_int(26) <= ( Ax(26) and Bx_int(NUM_BITS-1) ) xor Cx_int(25);
Cx_int(27) <= ( Ax(27) and Bx_int(NUM_BITS-1) ) xor Cx_int(26);
Cx_int(28) <= ( Ax(28) and Bx_int(NUM_BITS-1) ) xor Cx_int(27);
Cx_int(29) <= ( Ax(29) and Bx_int(NUM_BITS-1) ) xor Cx_int(28);
Cx_int(30) <= ( Ax(30) and Bx_int(NUM_BITS-1) ) xor Cx_int(29);
Cx_int(31) <= ( Ax(31) and Bx_int(NUM_BITS-1) ) xor Cx_int(30);
Cx_int(32) <= ( Ax(32) and Bx_int(NUM_BITS-1) ) xor Cx_int(31);
Cx_int(33) <= ( Ax(33) and Bx_int(NUM_BITS-1) ) xor Cx_int(32);
Cx_int(34) <= ( Ax(34) and Bx_int(NUM_BITS-1) ) xor Cx_int(33);
Cx_int(35) <= ( Ax(35) and Bx_int(NUM_BITS-1) ) xor Cx_int(34);
Cx_int(36) <= ( Ax(36) and Bx_int(NUM_BITS-1) ) xor Cx_int(35);
Cx_int(37) <= ( Ax(37) and Bx_int(NUM_BITS-1) ) xor Cx_int(36);
Cx_int(38) <= ( Ax(38) and Bx_int(NUM_BITS-1) ) xor Cx_int(37);
Cx_int(39) <= ( Ax(39) and Bx_int(NUM_BITS-1) ) xor Cx_int(38);
Cx_int(40) <= ( Ax(40) and Bx_int(NUM_BITS-1) ) xor Cx_int(39);
Cx_int(41) <= ( Ax(41) and Bx_int(NUM_BITS-1) ) xor Cx_int(40);
Cx_int(42) <= ( Ax(42) and Bx_int(NUM_BITS-1) ) xor Cx_int(41);
Cx_int(43) <= ( Ax(43) and Bx_int(NUM_BITS-1) ) xor Cx_int(42);
Cx_int(44) <= ( Ax(44) and Bx_int(NUM_BITS-1) ) xor Cx_int(43);
Cx_int(45) <= ( Ax(45) and Bx_int(NUM_BITS-1) ) xor Cx_int(44);
Cx_int(46) <= ( Ax(46) and Bx_int(NUM_BITS-1) ) xor Cx_int(45);
Cx_int(47) <= ( Ax(47) and Bx_int(NUM_BITS-1) ) xor Cx_int(46);
Cx_int(48) <= ( Ax(48) and Bx_int(NUM_BITS-1) ) xor Cx_int(47);
Cx_int(49) <= ( Ax(49) and Bx_int(NUM_BITS-1) ) xor Cx_int(48);
Cx_int(50) <= ( Ax(50) and Bx_int(NUM_BITS-1) ) xor Cx_int(49);
Cx_int(51) <= ( Ax(51) and Bx_int(NUM_BITS-1) ) xor Cx_int(50);
Cx_int(52) <= ( Ax(52) and Bx_int(NUM_BITS-1) ) xor Cx_int(51);
Cx_int(53) <= ( Ax(53) and Bx_int(NUM_BITS-1) ) xor Cx_int(52);
Cx_int(54) <= ( Ax(54) and Bx_int(NUM_BITS-1) ) xor Cx_int(53);
Cx_int(55) <= ( Ax(55) and Bx_int(NUM_BITS-1) ) xor Cx_int(54);
Cx_int(56) <= ( Ax(56) and Bx_int(NUM_BITS-1) ) xor Cx_int(55);
Cx_int(57) <= ( Ax(57) and Bx_int(NUM_BITS-1) ) xor Cx_int(56);
Cx_int(58) <= ( Ax(58) and Bx_int(NUM_BITS-1) ) xor Cx_int(57);
Cx_int(59) <= ( Ax(59) and Bx_int(NUM_BITS-1) ) xor Cx_int(58);
Cx_int(60) <= ( Ax(60) and Bx_int(NUM_BITS-1) ) xor Cx_int(59);
Cx_int(61) <= ( Ax(61) and Bx_int(NUM_BITS-1) ) xor Cx_int(60);
Cx_int(62) <= ( Ax(62) and Bx_int(NUM_BITS-1) ) xor Cx_int(61);
Cx_int(63) <= ( Ax(63) and Bx_int(NUM_BITS-1) ) xor Cx_int(62);
Cx_int(64) <= ( Ax(64) and Bx_int(NUM_BITS-1) ) xor Cx_int(63);
Cx_int(65) <= ( Ax(65) and Bx_int(NUM_BITS-1) ) xor Cx_int(64);
Cx_int(66) <= ( Ax(66) and Bx_int(NUM_BITS-1) ) xor Cx_int(65);
Cx_int(67) <= ( Ax(67) and Bx_int(NUM_BITS-1) ) xor Cx_int(66);
Cx_int(68) <= ( Ax(68) and Bx_int(NUM_BITS-1) ) xor Cx_int(67);
Cx_int(69) <= ( Ax(69) and Bx_int(NUM_BITS-1) ) xor Cx_int(68);
Cx_int(70) <= ( Ax(70) and Bx_int(NUM_BITS-1) ) xor Cx_int(69);
Cx_int(71) <= ( Ax(71) and Bx_int(NUM_BITS-1) ) xor Cx_int(70);
Cx_int(72) <= ( Ax(72) and Bx_int(NUM_BITS-1) ) xor Cx_int(71);
Cx_int(73) <= ( Ax(73) and Bx_int(NUM_BITS-1) ) xor Cx_int(72);
Cx_int(74) <= ( Ax(74) and Bx_int(NUM_BITS-1) ) xor Cx_int(73);
Cx_int(75) <= ( Ax(75) and Bx_int(NUM_BITS-1) ) xor Cx_int(74);
Cx_int(76) <= ( Ax(76) and Bx_int(NUM_BITS-1) ) xor Cx_int(75);
Cx_int(77) <= ( Ax(77) and Bx_int(NUM_BITS-1) ) xor Cx_int(76);
Cx_int(78) <= ( Ax(78) and Bx_int(NUM_BITS-1) ) xor Cx_int(77);
Cx_int(79) <= ( Ax(79) and Bx_int(NUM_BITS-1) ) xor Cx_int(78);
Cx_int(80) <= ( Ax(80) and Bx_int(NUM_BITS-1) ) xor Cx_int(79);
Cx_int(81) <= ( Ax(81) and Bx_int(NUM_BITS-1) ) xor Cx_int(80);
Cx_int(82) <= ( Ax(82) and Bx_int(NUM_BITS-1) ) xor Cx_int(81);
Cx_int(83) <= ( Ax(83) and Bx_int(NUM_BITS-1) ) xor Cx_int(82);
Cx_int(84) <= ( Ax(84) and Bx_int(NUM_BITS-1) ) xor Cx_int(83);
Cx_int(85) <= ( Ax(85) and Bx_int(NUM_BITS-1) ) xor Cx_int(84);
Cx_int(86) <= ( Ax(86) and Bx_int(NUM_BITS-1) ) xor Cx_int(85);
Cx_int(87) <= ( Ax(87) and Bx_int(NUM_BITS-1) ) xor Cx_int(86);
Cx_int(88) <= ( Ax(88) and Bx_int(NUM_BITS-1) ) xor Cx_int(87);
Cx_int(89) <= ( Ax(89) and Bx_int(NUM_BITS-1) ) xor Cx_int(88);
Cx_int(90) <= ( Ax(90) and Bx_int(NUM_BITS-1) ) xor Cx_int(89);
Cx_int(91) <= ( Ax(91) and Bx_int(NUM_BITS-1) ) xor Cx_int(90);
Cx_int(92) <= ( Ax(92) and Bx_int(NUM_BITS-1) ) xor Cx_int(91);
Cx_int(93) <= ( Ax(93) and Bx_int(NUM_BITS-1) ) xor Cx_int(92);
Cx_int(94) <= ( Ax(94) and Bx_int(NUM_BITS-1) ) xor Cx_int(93);
Cx_int(95) <= ( Ax(95) and Bx_int(NUM_BITS-1) ) xor Cx_int(94);
Cx_int(96) <= ( Ax(96) and Bx_int(NUM_BITS-1) ) xor Cx_int(95);
Cx_int(97) <= ( Ax(97) and Bx_int(NUM_BITS-1) ) xor Cx_int(96);
Cx_int(98) <= ( Ax(98) and Bx_int(NUM_BITS-1) ) xor Cx_int(97);
Cx_int(99) <= ( Ax(99) and Bx_int(NUM_BITS-1) ) xor Cx_int(98);
Cx_int(100) <= ( Ax(100) and Bx_int(NUM_BITS-1) ) xor Cx_int(99);
Cx_int(101) <= ( Ax(101) and Bx_int(NUM_BITS-1) ) xor Cx_int(100);
Cx_int(102) <= ( Ax(102) and Bx_int(NUM_BITS-1) ) xor Cx_int(101);
Cx_int(103) <= ( Ax(103) and Bx_int(NUM_BITS-1) ) xor Cx_int(102);
Cx_int(104) <= ( Ax(104) and Bx_int(NUM_BITS-1) ) xor Cx_int(103);
Cx_int(105) <= ( Ax(105) and Bx_int(NUM_BITS-1) ) xor Cx_int(104);
Cx_int(106) <= ( Ax(106) and Bx_int(NUM_BITS-1) ) xor Cx_int(105);
Cx_int(107) <= ( Ax(107) and Bx_int(NUM_BITS-1) ) xor Cx_int(106);
Cx_int(108) <= ( Ax(108) and Bx_int(NUM_BITS-1) ) xor Cx_int(107);
Cx_int(109) <= ( Ax(109) and Bx_int(NUM_BITS-1) ) xor Cx_int(108);
Cx_int(110) <= ( Ax(110) and Bx_int(NUM_BITS-1) ) xor Cx_int(109);
Cx_int(111) <= ( Ax(111) and Bx_int(NUM_BITS-1) ) xor Cx_int(110);
Cx_int(112) <= ( Ax(112) and Bx_int(NUM_BITS-1) ) xor Cx_int(111);
end if;
if counter = "01110000" then
done_int <= '1';
end if;
end if;
end if;
end process;
SHIFT_REGISTER: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
Bx_shift <= Bx;
else
Bx_shift <= Bx_shift(NUM_BITS-2 downto 0) & '0'; -- carga paralela
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
a011f2f0cb4f84ea00a60c7e6a585f69
| 0.518339 | 2.412503 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/do_arith_op.vhd
| 4 | 1,956 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity do_arith_op is
end entity do_arith_op;
architecture test of do_arith_op is
type func_code is (add, subtract);
signal op1 : integer := 10;
signal op2 : integer := 3;
signal dest : integer := 0;
signal func : func_code := add;
signal Z_flag : boolean := false;
constant Tpd : delay_length := 3 ns;
begin
stimulus : process is
-- code from book
procedure do_arith_op ( op : in func_code ) is
variable result : integer;
begin
case op is
when add =>
result := op1 + op2;
when subtract =>
result := op1 - op2;
end case;
dest <= result after Tpd;
Z_flag <= result = 0 after Tpd;
end procedure do_arith_op;
-- end code from book
begin
wait for 10 ns;
-- code from book (in text)
do_arith_op ( add );
-- end code from book
wait for 10 ns;
-- code from book (in text)
do_arith_op ( func );
-- end code from book
wait for 10 ns;
do_arith_op ( subtract );
wait for 10 ns;
op2 <= 10;
wait for 10 ns;
do_arith_op ( subtract );
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
ab52719a061aec000d9143c312af2568
| 0.642638 | 3.850394 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd
| 4 | 1,763 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity computer_system is
end entity computer_system;
library util; use util.stimulus_generators.all;
-- end not in book
architecture structure of computer_system is
component decoder_2_to_4 is
generic ( prop_delay : delay_length );
port ( in0, in1 : in bit;
out0, out1, out2, out3 : out bit );
end component decoder_2_to_4;
-- . . .
-- not in book
signal addr : bit_vector(5 downto 4);
signal interface_a_select, interface_b_select,
interface_c_select, interface_d_select : bit;
-- end not in book
begin
interface_decoder : component decoder_2_to_4
generic map ( prop_delay => 4 ns )
port map ( in0 => addr(4), in1 => addr(5),
out0 => interface_a_select, out1 => interface_b_select,
out2 => interface_c_select, out3 => interface_d_select );
-- . . .
-- not in book
all_possible_values(addr, 10 ns);
-- end not in book
end architecture structure;
|
gpl-2.0
|
78d831629b5f54e40ca8ea2970582619
| 0.681225 | 3.751064 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2961.vhd
| 4 | 4,563 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2961.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p02n01i02961pkg is
FUNCTION boo ( PARM_VAL: bit:='1') RETURN bit;
FUNCTION boo ( PARM_VAL: bit_vector:="1010")RETURN bit_vector;
FUNCTION boo ( PARM_VAL: boolean:=TRUE) RETURN boolean;
FUNCTION boo ( PARM_VAL: character:='Z') RETURN character;
FUNCTION boo ( PARM_VAL: integer:=55) RETURN integer;
FUNCTION boo ( PARM_VAL: real:=10.01) RETURN real;
FUNCTION boo ( PARM_VAL: string:="STRING") RETURN string;
FUNCTION boo ( PARM_VAL: time:=10 ns) RETURN time;
end c02s03b00x00p02n01i02961pkg;
package body c02s03b00x00p02n01i02961pkg is
FUNCTION boo ( PARM_VAL: bit:='1') RETURN bit IS
BEGIN
assert false report "boo with BIT param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: bit_vector:="1010") RETURN bit_vector IS
BEGIN
assert false report "boo with BIT_VECTOR param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: boolean:=TRUE) RETURN boolean IS
BEGIN
assert false report "boo with BOOLEAN param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: character:='Z') RETURN character IS
BEGIN
assert false report "boo with CHARACTER param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: integer:=55) RETURN integer IS
BEGIN
assert false report "boo with INTEGER param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: real:=10.01) RETURN real IS
BEGIN
assert false report "boo with REAL param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: string:="STRING") RETURN string IS
BEGIN
assert false report "boo with STRING param" severity note;
RETURN PARM_VAL;
END;
FUNCTION boo ( PARM_VAL: time:=10 ns) RETURN time IS
BEGIN
assert false report "boo with TIME param" severity note;
RETURN PARM_VAL;
END;
end c02s03b00x00p02n01i02961pkg;
ENTITY c02s03b00x00p02n01i02961ent IS
PORT (bb: INOUT bit;
bv: INOUT bit_vector(0 TO 3);
bo: INOUT boolean;
cc: INOUT character;
ii: INOUT integer;
rr: INOUT real;
ss: INOUT string(1 TO 6);
tt: INOUT time);
END c02s03b00x00p02n01i02961ent;
use work.c02s03b00x00p02n01i02961pkg.all;
ARCHITECTURE c02s03b00x00p02n01i02961arch OF c02s03b00x00p02n01i02961ent IS
SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
bb <= boo;
bv <= boo;
bo <= boo;
cc <= boo;
ii <= boo;
rr <= boo;
ss <= boo;
tt <= boo;
WAIT FOR 1 ns;
assert NOT( (bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***PASSED TEST: c02s03b00x00p02n01i02961"
severity NOTE;
assert ( (bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***FAILED TEST: c02s03b00x00p02n01i02961 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02961arch;
|
gpl-2.0
|
6239decc0ccbb11526bb08d0938c3243
| 0.615604 | 3.609968 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo-b.vhd
| 4 | 2,465 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tkfifo-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
package body token_fifo_adt is
function new_fifo return fifo_type is
begin
return new fifo_record'( null, null );
end function new_fifo;
procedure test_empty ( variable fifo : in fifo_type;
variable is_empty : out boolean ) is
begin
is_empty := fifo.head_entry = null;
end procedure test_empty;
procedure insert ( fifo : inout fifo_type;
element : in element_type ) is
variable new_entry : fifo_entry
:= new fifo_entry_record'( next_entry => null,
element => element );
begin
if fifo.tail_entry /= null then
fifo.tail_entry.next_entry := new_entry;
else
fifo.head_entry := new_entry;
end if;
fifo.tail_entry := new_entry;
end procedure insert;
procedure remove ( fifo : inout fifo_type;
element : out element_type ) is
variable empty_fifo : boolean;
variable removed_entry : fifo_entry;
begin
test_empty(fifo, empty_fifo);
if empty_fifo then
report "remove from empty fifo" severity failure;
else
removed_entry := fifo.head_entry;
element := removed_entry.element;
fifo.head_entry := removed_entry.next_entry;
if fifo.head_entry = null then -- fifo now empty
fifo.tail_entry := null;
end if;
deallocate(removed_entry);
end if;
end procedure remove;
end package body token_fifo_adt;
|
gpl-2.0
|
1da907adf4e76d2e02149cdc405c4464
| 0.617039 | 4.15683 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1585.vhd
| 4 | 1,780 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1585.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p02n01i01585ent IS
END c08s11b00x00p02n01i01585ent;
ARCHITECTURE c08s11b00x00p02n01i01585arch OF c08s11b00x00p02n01i01585ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
while k < 10 loop
exit when k = 5;
k := k + 1;
end loop;
assert NOT( k=5 )
report "***PASSED TEST: c08s11b00x00p02n01i01585"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s11b00x00p02n01i01585 - The loop label in the exit statement is optional"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p02n01i01585arch;
|
gpl-2.0
|
d5ff3eb596b4b1a027ab5b621280b8b3
| 0.660112 | 3.692946 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc82.vhd
| 4 | 36,007 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc82.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x03p01n01i00082ent IS
END c04s03b01x03p01n01i00082ent;
ARCHITECTURE c04s03b01x03p01n01i00082arch OF c04s03b01x03p01n01i00082ent IS
--
--
-- Declaration of composite types
-- - array types and subtypes
--
TYPE ut_chary IS ARRAY (CHARACTER RANGE <>) OF INTEGER; -- unconstrained array type
TYPE ct_word IS ARRAY (0 TO 15) OF BIT; -- constrained array type
SUBTYPE ust_subchary IS ut_chary; -- unconstrained array subtype
SUBTYPE cst_str10 IS STRING ( 1 TO 10 ); -- constrained array subtype
SUBTYPE cst_digit IS ut_chary ('0' TO '9'); -- constrained array subtype
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE rt_date IS
RECORD
day : INTEGER RANGE 0 TO 31;
month : month_name;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
SUBTYPE rst_date IS rt_date;
BEGIN
TESTING: PROCESS
--
-- VARIABLE declarations
--
VARIABLE STRING_con_0 : STRING (1 TO 7);
VARIABLE STRING_con_1 : STRING (1 TO 7) := "sailing";
VARIABLE STRING_con_2 : STRING (1 TO 7) := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
VARIABLE BIT_VECTOR_con_0 : BIT_VECTOR (0 TO 7);
VARIABLE BIT_VECTOR_con_1 : BIT_VECTOR (0 TO 7) := B"10101110";
VARIABLE BIT_VECTOR_con_2 : BIT_VECTOR (0 TO 7) := ( '1', '0', '1', '0', '1', '1', '1', '0');
VARIABLE ut_chary_con_0 : ut_chary (NUL TO ENQ);
VARIABLE ut_chary_con_1 : ut_chary (NUL TO ENQ) := ( 1, 2, 3, 9, 8, 7);
VARIABLE ct_word_con_0 : ct_word;
VARIABLE ct_word_con_1 : ct_word := ( '1', '1', '1', '1', '1', '1', '1', '1',
'1', '1', '1', '1', '1', '1', '1', '1');
VARIABLE cst_str10_con_0 : cst_str10;
VARIABLE cst_str10_con_1 : cst_str10 := "abcdefghij";
VARIABLE cst_str10_con_2 : cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j');
VARIABLE cst_digit_con_0 : cst_digit;
VARIABLE cst_digit_con_1 : cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
VARIABLE rt_date_con_0 : rt_date;
VARIABLE rt_date_con_1 : rt_date := (1, Jan, 1989);
VARIABLE rst_date_con_0 : rst_date;
VARIABLE rst_date_con_1 : rst_date := (1, Apr, 2000);
----------------------------------------------------------------------------------------------------------
BEGIN
ASSERT STRING_con_0(1) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(2) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(3) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(4) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(5) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(6) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(7) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(0) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(1) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(2) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(3) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(4) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(5) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(6) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(7) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(NUL) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(SOH) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(STX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(ETX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(EOT) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(ENQ) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(NUL) = 1 REPORT "ut_chary_con_1('a') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(SOH) = 2 REPORT "ut_chary_con_1('b') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(STX) = 3 REPORT "ut_chary_con_1('c') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(ETX) = 9 REPORT "ut_chary_con_1('d') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(EOT) = 8 REPORT "ut_chary_con_1('e') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(ENQ) = 7 REPORT "ut_chary_con_1('f') not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(0) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(1) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(2) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(3) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(4) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(5) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(6) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(7) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(8) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(9) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(10) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(11) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(12) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(13) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(14) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(15) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(0) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(1) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(2) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(3) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(4) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(5) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(6) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(7) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(8) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(9) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(10) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(11) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(12) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(13) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(14) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(15) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(1) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(2) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(3) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(4) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(5) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(6) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(7) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(8) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(9) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(10) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('0') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('1') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('2') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('3') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('4') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('5') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('6') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('7') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('8') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('9') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('0') = 0 REPORT "cst_digit_con_1('0') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('1') = 1 REPORT "cst_digit_con_1('1') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('2') = 2 REPORT "cst_digit_con_1('2') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('3') = 3 REPORT "cst_digit_con_1('3') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('4') = 4 REPORT "cst_digit_con_1('4') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('5') = 5 REPORT "cst_digit_con_1('5') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('6') = 6 REPORT "cst_digit_con_1('6') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('7') = 7 REPORT "cst_digit_con_1('7') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('8') = 8 REPORT "cst_digit_con_1('8') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('9') = 9 REPORT "cst_digit_con_1('9') not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.day = 0 REPORT " rt_date_con_0.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.month = Jan REPORT " rt_date_con_0.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.year = 0 REPORT " rt_date_con_0.year not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.day = 1 REPORT " rt_date_con_1.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.month = Jan REPORT " rt_date_con_1.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.year = 1989 REPORT " rt_date_con_1.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.day = 0 REPORT "rst_date_con_0.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.month = Jan REPORT "rst_date_con_0.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.year = 0 REPORT "rst_date_con_0.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.day = 1 REPORT "rst_date_con_1.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.month = Apr REPORT "rst_date_con_1.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.year = 2000 REPORT "rst_date_con_1.year not properly intialized" SEVERITY FAILURE;
--------------------------------------------------------------------------------------------------------------
assert NOT( STRING_con_0(1) = NUL and
STRING_con_0(2) = NUL and
STRING_con_0(3) = NUL and
STRING_con_0(4) = NUL and
STRING_con_0(5) = NUL and
STRING_con_0(6) = NUL and
STRING_con_0(7) = NUL and
STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_0(0) = '0' and
BIT_VECTOR_con_0(1) = '0' and
BIT_VECTOR_con_0(2) = '0' and
BIT_VECTOR_con_0(3) = '0' and
BIT_VECTOR_con_0(4) = '0' and
BIT_VECTOR_con_0(5) = '0' and
BIT_VECTOR_con_0(6) = '0' and
BIT_VECTOR_con_0(7) = '0' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con_0(NUL) = INTEGER'LEFT and
ut_chary_con_0(SOH) = INTEGER'LEFT and
ut_chary_con_0(STX) = INTEGER'LEFT and
ut_chary_con_0(ETX) = INTEGER'LEFT and
ut_chary_con_0(EOT) = INTEGER'LEFT and
ut_chary_con_0(ENQ) = INTEGER'LEFT and
ut_chary_con_1(NUL) = 1 and
ut_chary_con_1(SOH) = 2 and
ut_chary_con_1(STX) = 3 and
ut_chary_con_1(ETX) = 9 and
ut_chary_con_1(EOT) = 8 and
ut_chary_con_1(ENQ) = 7 and
ct_word_con_0(0) = '0' and
ct_word_con_0(1) = '0' and
ct_word_con_0(2) = '0' and
ct_word_con_0(3) = '0' and
ct_word_con_0(4) = '0' and
ct_word_con_0(5) = '0' and
ct_word_con_0(6) = '0' and
ct_word_con_0(7) = '0' and
ct_word_con_0(8) = '0' and
ct_word_con_0(9) = '0' and
ct_word_con_0(10) = '0' and
ct_word_con_0(11) = '0' and
ct_word_con_0(12) = '0' and
ct_word_con_0(13) = '0' and
ct_word_con_0(14) = '0' and
ct_word_con_0(15) = '0' and
ct_word_con_1(0) = '1' and
ct_word_con_1(1) = '1' and
ct_word_con_1(2) = '1' and
ct_word_con_1(3) = '1' and
ct_word_con_1(4) = '1' and
ct_word_con_1(5) = '1' and
ct_word_con_1(6) = '1' and
ct_word_con_1(7) = '1' and
ct_word_con_1(8) = '1' and
ct_word_con_1(9) = '1' and
ct_word_con_1(10) = '1' and
ct_word_con_1(11) = '1' and
ct_word_con_1(12) = '1' and
ct_word_con_1(13) = '1' and
ct_word_con_1(14) = '1' and
ct_word_con_1(15) = '1' and
cst_str10_con_0(1) = NUL and
cst_str10_con_0(2) = NUL and
cst_str10_con_0(3) = NUL and
cst_str10_con_0(4) = NUL and
cst_str10_con_0(5) = NUL and
cst_str10_con_0(6) = NUL and
cst_str10_con_0(7) = NUL and
cst_str10_con_0(8) = NUL and
cst_str10_con_0(9) = NUL and
cst_str10_con_0(10) = NUL and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con_0('0') = INTEGER'LEFT and
cst_digit_con_0('1') = INTEGER'LEFT and
cst_digit_con_0('2') = INTEGER'LEFT and
cst_digit_con_0('3') = INTEGER'LEFT and
cst_digit_con_0('4') = INTEGER'LEFT and
cst_digit_con_0('5') = INTEGER'LEFT and
cst_digit_con_0('6') = INTEGER'LEFT and
cst_digit_con_0('7') = INTEGER'LEFT and
cst_digit_con_0('8') = INTEGER'LEFT and
cst_digit_con_0('9') = INTEGER'LEFT and
cst_digit_con_1('0') = 0 and
cst_digit_con_1('1') = 1 and
cst_digit_con_1('2') = 2 and
cst_digit_con_1('3') = 3 and
cst_digit_con_1('4') = 4 and
cst_digit_con_1('5') = 5 and
cst_digit_con_1('6') = 6 and
cst_digit_con_1('7') = 7 and
cst_digit_con_1('8') = 8 and
cst_digit_con_1('9') = 9 and
rt_date_con_0.day = 0 and
rt_date_con_0.month = Jan and
rt_date_con_0.year = 0 and
rt_date_con_1.day = 1 and
rt_date_con_1.month = Jan and
rt_date_con_1.year = 1989 and
rst_date_con_0.day = 0 and
rst_date_con_0.month = Jan and
rst_date_con_0.year = 0 and
rst_date_con_1.day = 1 and
rst_date_con_1.month = Apr and
rst_date_con_1.year = 2000 )
report "***PASSED TEST: /src/ch04/sc03/sb01/ss03/p001/s010101.vhd"
severity NOTE;
assert ( STRING_con_0(1) = NUL and
STRING_con_0(2) = NUL and
STRING_con_0(3) = NUL and
STRING_con_0(4) = NUL and
STRING_con_0(5) = NUL and
STRING_con_0(6) = NUL and
STRING_con_0(7) = NUL and
STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_0(0) = '0' and
BIT_VECTOR_con_0(1) = '0' and
BIT_VECTOR_con_0(2) = '0' and
BIT_VECTOR_con_0(3) = '0' and
BIT_VECTOR_con_0(4) = '0' and
BIT_VECTOR_con_0(5) = '0' and
BIT_VECTOR_con_0(6) = '0' and
BIT_VECTOR_con_0(7) = '0' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con_0(NUL) = INTEGER'LEFT and
ut_chary_con_0(SOH) = INTEGER'LEFT and
ut_chary_con_0(STX) = INTEGER'LEFT and
ut_chary_con_0(ETX) = INTEGER'LEFT and
ut_chary_con_0(EOT) = INTEGER'LEFT and
ut_chary_con_0(ENQ) = INTEGER'LEFT and
ut_chary_con_1(NUL) = 1 and
ut_chary_con_1(SOH) = 2 and
ut_chary_con_1(STX) = 3 and
ut_chary_con_1(ETX) = 9 and
ut_chary_con_1(EOT) = 8 and
ut_chary_con_1(ENQ) = 7 and
ct_word_con_0(0) = '0' and
ct_word_con_0(1) = '0' and
ct_word_con_0(2) = '0' and
ct_word_con_0(3) = '0' and
ct_word_con_0(4) = '0' and
ct_word_con_0(5) = '0' and
ct_word_con_0(6) = '0' and
ct_word_con_0(7) = '0' and
ct_word_con_0(8) = '0' and
ct_word_con_0(9) = '0' and
ct_word_con_0(10) = '0' and
ct_word_con_0(11) = '0' and
ct_word_con_0(12) = '0' and
ct_word_con_0(13) = '0' and
ct_word_con_0(14) = '0' and
ct_word_con_0(15) = '0' and
ct_word_con_1(0) = '1' and
ct_word_con_1(1) = '1' and
ct_word_con_1(2) = '1' and
ct_word_con_1(3) = '1' and
ct_word_con_1(4) = '1' and
ct_word_con_1(5) = '1' and
ct_word_con_1(6) = '1' and
ct_word_con_1(7) = '1' and
ct_word_con_1(8) = '1' and
ct_word_con_1(9) = '1' and
ct_word_con_1(10) = '1' and
ct_word_con_1(11) = '1' and
ct_word_con_1(12) = '1' and
ct_word_con_1(13) = '1' and
ct_word_con_1(14) = '1' and
ct_word_con_1(15) = '1' and
cst_str10_con_0(1) = NUL and
cst_str10_con_0(2) = NUL and
cst_str10_con_0(3) = NUL and
cst_str10_con_0(4) = NUL and
cst_str10_con_0(5) = NUL and
cst_str10_con_0(6) = NUL and
cst_str10_con_0(7) = NUL and
cst_str10_con_0(8) = NUL and
cst_str10_con_0(9) = NUL and
cst_str10_con_0(10) = NUL and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con_0('0') = INTEGER'LEFT and
cst_digit_con_0('1') = INTEGER'LEFT and
cst_digit_con_0('2') = INTEGER'LEFT and
cst_digit_con_0('3') = INTEGER'LEFT and
cst_digit_con_0('4') = INTEGER'LEFT and
cst_digit_con_0('5') = INTEGER'LEFT and
cst_digit_con_0('6') = INTEGER'LEFT and
cst_digit_con_0('7') = INTEGER'LEFT and
cst_digit_con_0('8') = INTEGER'LEFT and
cst_digit_con_0('9') = INTEGER'LEFT and
cst_digit_con_1('0') = 0 and
cst_digit_con_1('1') = 1 and
cst_digit_con_1('2') = 2 and
cst_digit_con_1('3') = 3 and
cst_digit_con_1('4') = 4 and
cst_digit_con_1('5') = 5 and
cst_digit_con_1('6') = 6 and
cst_digit_con_1('7') = 7 and
cst_digit_con_1('8') = 8 and
cst_digit_con_1('9') = 9 and
rt_date_con_0.day = 0 and
rt_date_con_0.month = Jan and
rt_date_con_0.year = 0 and
rt_date_con_1.day = 1 and
rt_date_con_1.month = Jan and
rt_date_con_1.year = 1989 and
rst_date_con_0.day = 0 and
rst_date_con_0.month = Jan and
rst_date_con_0.year = 0 and
rst_date_con_1.day = 1 and
rst_date_con_1.month = Apr and
rst_date_con_1.year = 2000 )
report "***FAILED TEST: c04s03b01x03p01n01i00082 - A variable declaration declares a variable of the specified type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x03p01n01i00082arch;
|
gpl-2.0
|
71bd5e8cbbfa88ec86a0776bfcde0dfd
| 0.531647 | 3.248263 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc63.vhd
| 4 | 35,404 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc63.vhd,v 1.2 2001-10-26 16:29:57 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p01n01i00063ent IS
END c04s03b01x02p01n01i00063ent;
ARCHITECTURE c04s03b01x02p01n01i00063arch OF c04s03b01x02p01n01i00063ent IS
--
--
-- Declaration of composite types
-- - array types and subtypes
--
TYPE ut_chary IS ARRAY (CHARACTER RANGE <>) OF INTEGER; -- unconstrained array type
TYPE ct_word IS ARRAY (0 TO 15) OF BIT; -- constrained array type
SUBTYPE ust_subchary IS ut_chary; -- unconstrained array subtype
SUBTYPE cst_str10 IS STRING ( 1 TO 10 ); -- constrained array subtype
SUBTYPE cst_digit IS ut_chary ('0' TO '9'); -- constrained array subtype
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE rt_date IS
RECORD
day : INTEGER RANGE 0 TO 31;
month : month_name;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
SUBTYPE rst_date IS rt_date;
----------------------------------------------------------------------------------------------------------
--
-- SIGNAL declarations
--
SIGNAL STRING_con_0 : STRING (1 TO 7);
SIGNAL STRING_con_1 : STRING (1 TO 7) := "sailing";
SIGNAL STRING_con_2 : STRING (1 TO 7) := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
SIGNAL BIT_VECTOR_con_0 : BIT_VECTOR (0 TO 7);
SIGNAL BIT_VECTOR_con_1 : BIT_VECTOR (0 TO 7) := B"10101110";
SIGNAL BIT_VECTOR_con_2 : BIT_VECTOR (0 TO 7) := ( '1', '0', '1', '0', '1', '1', '1', '0');
SIGNAL ut_chary_con_0 : ut_chary (NUL TO ENQ);
SIGNAL ut_chary_con_1 : ut_chary (NUL TO ENQ) := ( 1, 2, 3, 9, 8, 7);
SIGNAL ct_word_con_0 : ct_word;
SIGNAL ct_word_con_1 : ct_word := ( '1', '1', '1', '1', '1', '1', '1', '1',
'1', '1', '1', '1', '1', '1', '1', '1');
SIGNAL cst_str10_con_0 : cst_str10;
SIGNAL cst_str10_con_1 : cst_str10 := "abcdefghij";
SIGNAL cst_str10_con_2 : cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j');
SIGNAL cst_digit_con_0 : cst_digit;
SIGNAL cst_digit_con_1 : cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
SIGNAL rt_date_con_0 : rt_date;
SIGNAL rt_date_con_1 : rt_date := (1, Jan, 1989);
SIGNAL rst_date_con_0 : rst_date;
SIGNAL rst_date_con_1 : rst_date := (1, Apr, 2000);
----------------------------------------------------------------------------------------------------------
BEGIN
TESTING: PROCESS
BEGIN
--
ASSERT STRING_con_0(1) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(2) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(3) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(4) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(5) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(6) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(7) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(0) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(1) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(2) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(3) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(4) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(5) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(6) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(7) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(NUL) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(SOH) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(STX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(ETX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(EOT) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(ENQ) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(NUL) = 1 REPORT "ut_chary_con_1('a') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(SOH) = 2 REPORT "ut_chary_con_1('b') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(STX) = 3 REPORT "ut_chary_con_1('c') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(ETX) = 9 REPORT "ut_chary_con_1('d') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(EOT) = 8 REPORT "ut_chary_con_1('e') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(ENQ) = 7 REPORT "ut_chary_con_1('f') not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(0) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(1) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(2) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(3) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(4) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(5) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(6) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(7) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(8) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(9) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(10) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(11) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(12) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(13) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(14) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(15) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(0) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(1) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(2) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(3) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(4) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(5) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(6) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(7) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(8) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(9) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(10) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(11) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(12) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(13) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(14) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(15) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(1) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(2) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(3) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(4) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(5) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(6) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(7) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(8) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(9) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(10) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('0') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('1') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('2') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('3') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('4') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('5') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('6') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('7') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('8') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('9') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('0') = 0 REPORT "cst_digit_con_1('0') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('1') = 1 REPORT "cst_digit_con_1('1') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('2') = 2 REPORT "cst_digit_con_1('2') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('3') = 3 REPORT "cst_digit_con_1('3') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('4') = 4 REPORT "cst_digit_con_1('4') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('5') = 5 REPORT "cst_digit_con_1('5') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('6') = 6 REPORT "cst_digit_con_1('6') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('7') = 7 REPORT "cst_digit_con_1('7') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('8') = 8 REPORT "cst_digit_con_1('8') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('9') = 9 REPORT "cst_digit_con_1('9') not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.day = 0 REPORT " rt_date_con_0.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.month = Jan REPORT " rt_date_con_0.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.year = 0 REPORT " rt_date_con_0.year not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.day = 1 REPORT " rt_date_con_1.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.month = Jan REPORT " rt_date_con_1.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.year = 1989 REPORT " rt_date_con_1.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.day = 0 REPORT "rst_date_con_0.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.month = Jan REPORT "rst_date_con_0.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.year = 0 REPORT "rst_date_con_0.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.day = 1 REPORT "rst_date_con_1.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.month = Apr REPORT "rst_date_con_1.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.year = 2000 REPORT "rst_date_con_1.year not properly intialized" SEVERITY FAILURE;
-------------------------------------------------------------------------------------------------------------
assert NOT( STRING_con_0(1) = NUL and
STRING_con_0(2) = NUL and
STRING_con_0(3) = NUL and
STRING_con_0(4) = NUL and
STRING_con_0(5) = NUL and
STRING_con_0(6) = NUL and
STRING_con_0(7) = NUL and
STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_0(0) = '0' and
BIT_VECTOR_con_0(1) = '0' and
BIT_VECTOR_con_0(2) = '0' and
BIT_VECTOR_con_0(3) = '0' and
BIT_VECTOR_con_0(4) = '0' and
BIT_VECTOR_con_0(5) = '0' and
BIT_VECTOR_con_0(6) = '0' and
BIT_VECTOR_con_0(7) = '0' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con_0(NUL) = INTEGER'LEFT and
ut_chary_con_0(SOH) = INTEGER'LEFT and
ut_chary_con_0(STX) = INTEGER'LEFT and
ut_chary_con_0(ETX) = INTEGER'LEFT and
ut_chary_con_0(EOT) = INTEGER'LEFT and
ut_chary_con_0(ENQ) = INTEGER'LEFT and
ut_chary_con_1(NUL) = 1 and
ut_chary_con_1(SOH) = 2 and
ut_chary_con_1(STX) = 3 and
ut_chary_con_1(ETX) = 9 and
ut_chary_con_1(EOT) = 8 and
ut_chary_con_1(ENQ) = 7 and
ct_word_con_0(0) = '0' and
ct_word_con_0(1) = '0' and
ct_word_con_0(2) = '0' and
ct_word_con_0(3) = '0' and
ct_word_con_0(4) = '0' and
ct_word_con_0(5) = '0' and
ct_word_con_0(6) = '0' and
ct_word_con_0(7) = '0' and
ct_word_con_0(8) = '0' and
ct_word_con_0(9) = '0' and
ct_word_con_0(10) = '0' and
ct_word_con_0(11) = '0' and
ct_word_con_0(12) = '0' and
ct_word_con_0(13) = '0' and
ct_word_con_0(14) = '0' and
ct_word_con_0(15) = '0' and
ct_word_con_1(0) = '1' and
ct_word_con_1(1) = '1' and
ct_word_con_1(2) = '1' and
ct_word_con_1(3) = '1' and
ct_word_con_1(4) = '1' and
ct_word_con_1(5) = '1' and
ct_word_con_1(6) = '1' and
ct_word_con_1(7) = '1' and
ct_word_con_1(8) = '1' and
ct_word_con_1(9) = '1' and
ct_word_con_1(10) = '1' and
ct_word_con_1(11) = '1' and
ct_word_con_1(12) = '1' and
ct_word_con_1(13) = '1' and
ct_word_con_1(14) = '1' and
ct_word_con_1(15) = '1' and
cst_str10_con_0(1) = NUL and
cst_str10_con_0(2) = NUL and
cst_str10_con_0(3) = NUL and
cst_str10_con_0(4) = NUL and
cst_str10_con_0(5) = NUL and
cst_str10_con_0(6) = NUL and
cst_str10_con_0(7) = NUL and
cst_str10_con_0(8) = NUL and
cst_str10_con_0(9) = NUL and
cst_str10_con_0(10) = NUL and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con_0('0') = INTEGER'LEFT and
cst_digit_con_0('1') = INTEGER'LEFT and
cst_digit_con_0('2') = INTEGER'LEFT and
cst_digit_con_0('3') = INTEGER'LEFT and
cst_digit_con_0('4') = INTEGER'LEFT and
cst_digit_con_0('5') = INTEGER'LEFT and
cst_digit_con_0('6') = INTEGER'LEFT and
cst_digit_con_0('7') = INTEGER'LEFT and
cst_digit_con_0('8') = INTEGER'LEFT and
cst_digit_con_0('9') = INTEGER'LEFT and
cst_digit_con_1('0') = 0 and
cst_digit_con_1('1') = 1 and
cst_digit_con_1('2') = 2 and
cst_digit_con_1('3') = 3 and
cst_digit_con_1('4') = 4 and
cst_digit_con_1('5') = 5 and
cst_digit_con_1('6') = 6 and
cst_digit_con_1('7') = 7 and
cst_digit_con_1('8') = 8 and
cst_digit_con_1('9') = 9 and
rt_date_con_0.day = 0 and
rt_date_con_0.month = Jan and
rt_date_con_0.year = 0 and
rt_date_con_1.day = 1 and
rt_date_con_1.month = Jan and
rt_date_con_1.year = 1989 and
rst_date_con_0.day = 0 and
rst_date_con_0.month = Jan and
rst_date_con_0.year = 0 and
rst_date_con_1.day = 1 and
rst_date_con_1.month = Apr and
rst_date_con_1.year = 2000 )
report "***PASSED TEST: /src/ch04/sc03/sb01/ss02/p001/s010101.vhd"
severity NOTE;
assert ( STRING_con_0(1) = NUL and
STRING_con_0(2) = NUL and
STRING_con_0(3) = NUL and
STRING_con_0(4) = NUL and
STRING_con_0(5) = NUL and
STRING_con_0(6) = NUL and
STRING_con_0(7) = NUL and
STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_0(0) = '0' and
BIT_VECTOR_con_0(1) = '0' and
BIT_VECTOR_con_0(2) = '0' and
BIT_VECTOR_con_0(3) = '0' and
BIT_VECTOR_con_0(4) = '0' and
BIT_VECTOR_con_0(5) = '0' and
BIT_VECTOR_con_0(6) = '0' and
BIT_VECTOR_con_0(7) = '0' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con_0(NUL) = INTEGER'LEFT and
ut_chary_con_0(SOH) = INTEGER'LEFT and
ut_chary_con_0(STX) = INTEGER'LEFT and
ut_chary_con_0(ETX) = INTEGER'LEFT and
ut_chary_con_0(EOT) = INTEGER'LEFT and
ut_chary_con_0(ENQ) = INTEGER'LEFT and
ut_chary_con_1(NUL) = 1 and
ut_chary_con_1(SOH) = 2 and
ut_chary_con_1(STX) = 3 and
ut_chary_con_1(ETX) = 9 and
ut_chary_con_1(EOT) = 8 and
ut_chary_con_1(ENQ) = 7 and
ct_word_con_0(0) = '0' and
ct_word_con_0(1) = '0' and
ct_word_con_0(2) = '0' and
ct_word_con_0(3) = '0' and
ct_word_con_0(4) = '0' and
ct_word_con_0(5) = '0' and
ct_word_con_0(6) = '0' and
ct_word_con_0(7) = '0' and
ct_word_con_0(8) = '0' and
ct_word_con_0(9) = '0' and
ct_word_con_0(10) = '0' and
ct_word_con_0(11) = '0' and
ct_word_con_0(12) = '0' and
ct_word_con_0(13) = '0' and
ct_word_con_0(14) = '0' and
ct_word_con_0(15) = '0' and
ct_word_con_1(0) = '1' and
ct_word_con_1(1) = '1' and
ct_word_con_1(2) = '1' and
ct_word_con_1(3) = '1' and
ct_word_con_1(4) = '1' and
ct_word_con_1(5) = '1' and
ct_word_con_1(6) = '1' and
ct_word_con_1(7) = '1' and
ct_word_con_1(8) = '1' and
ct_word_con_1(9) = '1' and
ct_word_con_1(10) = '1' and
ct_word_con_1(11) = '1' and
ct_word_con_1(12) = '1' and
ct_word_con_1(13) = '1' and
ct_word_con_1(14) = '1' and
ct_word_con_1(15) = '1' and
cst_str10_con_0(1) = NUL and
cst_str10_con_0(2) = NUL and
cst_str10_con_0(3) = NUL and
cst_str10_con_0(4) = NUL and
cst_str10_con_0(5) = NUL and
cst_str10_con_0(6) = NUL and
cst_str10_con_0(7) = NUL and
cst_str10_con_0(8) = NUL and
cst_str10_con_0(9) = NUL and
cst_str10_con_0(10) = NUL and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con_0('0') = INTEGER'LEFT and
cst_digit_con_0('1') = INTEGER'LEFT and
cst_digit_con_0('2') = INTEGER'LEFT and
cst_digit_con_0('3') = INTEGER'LEFT and
cst_digit_con_0('4') = INTEGER'LEFT and
cst_digit_con_0('5') = INTEGER'LEFT and
cst_digit_con_0('6') = INTEGER'LEFT and
cst_digit_con_0('7') = INTEGER'LEFT and
cst_digit_con_0('8') = INTEGER'LEFT and
cst_digit_con_0('9') = INTEGER'LEFT and
cst_digit_con_1('0') = 0 and
cst_digit_con_1('1') = 1 and
cst_digit_con_1('2') = 2 and
cst_digit_con_1('3') = 3 and
cst_digit_con_1('4') = 4 and
cst_digit_con_1('5') = 5 and
cst_digit_con_1('6') = 6 and
cst_digit_con_1('7') = 7 and
cst_digit_con_1('8') = 8 and
cst_digit_con_1('9') = 9 and
rt_date_con_0.day = 0 and
rt_date_con_0.month = Jan and
rt_date_con_0.year = 0 and
rt_date_con_1.day = 1 and
rt_date_con_1.month = Jan and
rt_date_con_1.year = 1989 and
rst_date_con_0.day = 0 and
rst_date_con_0.month = Jan and
rst_date_con_0.year = 0 and
rst_date_con_1.day = 1 and
rst_date_con_1.month = Apr and
rst_date_con_1.year = 2000 )
report "***FAILED TEST: c04s03b01x02p01n01i00063 - A signal declared a signal of the specified type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x02p01n01i00063arch;
|
gpl-2.0
|
dadfc9906e026e1c2d8bf8a7fa877214
| 0.539148 | 3.196172 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1103.vhd
| 4 | 2,175 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1103.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01103ent IS
END c06s05b00x00p03n01i01103ent;
ARCHITECTURE c06s05b00x00p03n01i01103arch OF c06s05b00x00p03n01i01103ent IS
BEGIN
TESTING: PROCESS
type FIVE is range 1 to 5;
type ABASE is array (FIVE range <>) of BOOLEAN;
subtype A1 is ABASE(FIVE);
type R1 is record
RE1: A1;
end record;
type R2 is record
RE2: R1;
end record;
variable V1: A1;
variable V2: R1 ; -- := (RE1=>(others=>TRUE));
variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE)));
BEGIN
V1(2 to 4) := V2.RE1(2 to 4); -- No_failure_here
assert NOT(V1(2 to 4)=(false,false,false))
report "***PASSED TEST: c06s05b00x00p03n01i01103"
severity NOTE;
assert (V1(2 to 4)=(false,false,false))
report "***FAILED TEST: c06s05b00x00p03n01i01103 - Prefix of a slice can be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01103arch;
|
gpl-2.0
|
153877eb4d6d246a1c33a39f8f06b142
| 0.633563 | 3.536585 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_motor_system.vhd
| 4 | 1,489 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_motor_system is
end tb_motor_system ;
architecture TB_motor_system of tb_motor_system is
-- Component declarations
-- Signal declarations
terminal in_src, x1_out, x2_out, x3_out : electrical;
begin
v7 : entity work.v_sine(ideal)
generic map(
freq => 10.0,
amplitude => 1.0
)
port map(
pos => in_src,
neg => electrical_ref
);
state_var1: entity work.motor_system_wa(simple)
port map(
vp => in_src,
vm => ELECTRICAL_REF,
px1 => x1_out,
px2 => x2_out,
px3 => x3_out
);
end TB_motor_system ;
|
gpl-2.0
|
3ae82fe0030f0ca9630891d2d842ee4e
| 0.667562 | 3.73183 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_07.vhd
| 4 | 2,351 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
library ieee; use ieee.std_logic_1164.all;
entity bidir_buffer is
port ( bidir : inout std_logic;
ena : in std_ulogic;
going_out : in std_ulogic;
coming_in : out std_ulogic );
end entity bidir_buffer;
--------------------------------------------------
architecture behavior of bidir_buffer is
begin
bidir <= going_out when ena = '1' else
'Z';
coming_in <= bidir;
end architecture behavior;
-- end code from book
entity fg_a_07 is
end entity fg_a_07;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_07 is
signal bidir : std_logic;
signal ena, going_out, coming_in : std_ulogic;
begin
dut : entity work.bidir_buffer
port map ( bidir, ena, going_out, coming_in );
ena <= '0', '1' after 10 ns, '0' after 30 ns;
going_out <= '0', '1' after 20 ns;
bidir <= 'Z', '0' after 40 ns, '1' after 50 ns, 'Z' after 60 ns;
end architecture test;
|
gpl-2.0
|
255a37384eee6a47254fb16e00bd7f48
| 0.514249 | 4.49522 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_04a.vhd
| 4 | 1,579 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04a is
end entity inline_04a;
----------------------------------------------------------------
architecture test of inline_04a is
type gear_type is (gear_1, gear_2, neutral);
signal gear : gear_type := gear_1;
signal gear_engaged : boolean := false;
begin
process_1_d : process (gear) is
variable max_acceleration : real := 0.0;
variable reverse_indicator : boolean := true;
begin
-- code from book:
if gear = neutral then
max_acceleration := 0.0;
reverse_indicator := false;
gear_engaged <= false;
end if;
-- end of code from book
end process process_1_d;
stimulus : process is
begin
gear <= gear_2 after 100 ns, neutral after 200 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
8b6b1eb5323a6c5b572485431cec7302
| 0.669411 | 4.090674 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc567.vhd
| 4 | 2,734 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc567.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:33 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:30 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:05 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00567ent IS
END c03s04b01x00p01n01i00567ent;
ARCHITECTURE c03s04b01x00p01n01i00567arch OF c03s04b01x00p01n01i00567ent IS
type integer_file is file of integer;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : integer_file open read_mode is "iofile.18";
variable v : integer;
BEGIN
for i in 1 to 100 loop
assert (endfile(filein) = false)
report"end of file reached before expected"
severity error;
read(filein,v);
if (v /= 3) then
k <= 1;
end if;
end loop;
wait for 50 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00567"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00567 - Implicitly declared procedure READ test failed. It may cause by procedure WRITE failed also."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00567arch;
|
gpl-2.0
|
f8b4498ba756df2f2c032f4055bd5083
| 0.558522 | 4.002928 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1309.vhd
| 4 | 4,533 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1309.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s04b00x00p07n01i01309pkg is
-- Type declarations.
subtype BV2 is BIT_VECTOR( 0 to 1 );
subtype CH2 is STRING( 1 to 2 );
-- Constant declarations.
constant BVC : BV2 := B"00";
constant CHC : CH2 := "bb";
-- Function returns BV2.
function returnBV2 return BV2;
-- Function returns CH2.
function returnCH2 return CH2;
end c08s04b00x00p07n01i01309pkg;
package body c08s04b00x00p07n01i01309pkg is
-- Function returns BV2.
function returnBV2 return BV2 is
begin
return ( BVC );
end returnBV2;
-- Function returns CH2.
function returnCH2 return CH2 is
begin
return( CHC );
end returnCH2;
end c08s04b00x00p07n01i01309pkg;
use work.c08s04b00x00p07n01i01309pkg.all;
ENTITY c08s04b00x00p07n01i01309ent IS
END c08s04b00x00p07n01i01309ent;
ARCHITECTURE c08s04b00x00p07n01i01309arch OF c08s04b00x00p07n01i01309ent IS
-- Local signals.
signal S : BIT;
signal T : BIT;
signal C1, C2 : CHARACTER;
BEGIN
TESTING: PROCESS
-- local variables
variable BITV : BV2 := B"11";
variable STRV : CH2 := "ab";
variable ShouldBeTime : TIME;
variable k : integer := 0;
BEGIN
-- Assign with a variable as the expression.
( S, T ) <= BITV after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on S,T;
if (ShouldBeTime /= Now or S /= BITV(0) or T /= BITV(1)) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((S = BITV( 0 )) and (T = BITV( 1 )));
( C1,C2 ) <= STRV after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on C1,C2;
if (ShouldBeTime /= Now or C1 /= STRV(1) or C2 /= STRV(2)) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((C1 = STRV( 1 )) and (C2 = STRV( 2 )));
-- Assign with a function return value.
( S, T ) <= returnBV2 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on S,T;
if (ShouldBeTime /= Now or S /= BVC(0) or T /= BVC(1)) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((S = BVC( 0 )) and (T = BVC( 1 )));
( C1,C2 ) <= returnCH2 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on C1,C2;
if (ShouldBeTime /= Now or C1 /= CHC(1) or C2 /= CHC(2)) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((C1 = CHC( 1 )) and (C2 = CHC( 2 )));
-- Assign with a qualified expression.
( S, T ) <= BV2'( '0', '1' ) after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on S,T;
if (ShouldBeTime /= Now or S /= '0' or T /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((S = '0') and (T = '1'));
( C1,C2 ) <= CH2'( 'c', 'c' ) after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on C1,C2;
if (ShouldBeTime /= Now or C1 /= 'c' or C2 /= 'c') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((C1 = 'c') and (C2 = 'c'));
assert NOT( k = 0 )
report "***PASSED TEST: c08s04b00x00p07n01i01309"
severity NOTE;
assert ( k = 0 )
report "***FAILED TEST: c08s04b00x00p07n01i01309 - If the target of the signal assignment statement is in the form of an aggregate, then the type of the aggregate must be determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p07n01i01309arch;
|
gpl-2.0
|
9520693fe8b109315fa87de669394063
| 0.601809 | 3.385362 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_05.vhd
| 4 | 1,864 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity flipflop is
generic ( Tsetup : delay_length );
port ( clk, d : in bit; q : out bit );
end entity flipflop;
-- code from book
architecture behavior of flipflop is
begin
timing_check : process (clk) is
begin
if clk = '1' then
assert d'last_event >= Tsetup
report "set up violation detected in " & timing_check'path_name
severity error;
end if;
end process timing_check;
-- . . . -- functionality
end architecture behavior;
-- end code from book
entity fg_20_05 is
end entity fg_20_05;
architecture test of fg_20_05 is
signal clk, d, q : bit;
begin
dut : entity work.flipflop(behavior)
generic map ( Tsetup => 3 ns )
port map ( clk => clk, d => d, q => q );
clk <= '1' after 10 ns, '0' after 20 ns;
d <= '1' after 8 ns;
end architecture test;
|
gpl-2.0
|
aa78b1f218981aa813dd0bb0766679ed
| 0.621781 | 3.811861 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/building_blocks/memoryUnit.vhd
| 2 | 1,437 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/16/2015 11:51:31 AM
-- Design Name:
-- Module Name: memoryUnit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity memoryUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SELB : in STD_LOGIC;
wordAIn : in STD_LOGIC_VECTOR (31 downto 0);
wordBin : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end memoryUnit;
architecture Behavioral of memoryUnit is
begin
process(CLK, RESET, SELB, wordAIn, wordBin)
variable wordAMemory, wordBMemory : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
if RESET = '1' then
wordAMemory := (others => '0');
wordBMemory := (others => '0');
elsif rising_edge(CLK) then
wordAMemory := wordAIn;
wordBMemory := wordBIn;
if SELB = '0' then
wordOut <= wordAMemory;
else
wordOut <= wordBMemory;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
dc3e2f7a742609e11fb4a3cb3afd6d66
| 0.503827 | 4.177326 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc344.vhd
| 4 | 2,116 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc344.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p09n01i00344ent IS
END c03s02b01x00p09n01i00344ent;
ARCHITECTURE c03s02b01x00p09n01i00344arch OF c03s02b01x00p09n01i00344ent IS
BEGIN
TESTING: PROCESS
type T_A1_S is ARRAY(INTEGER range <>) of INTEGER;
subtype ST_A1_S is T_A1_S(INTEGER range 1 to 3);
variable V_A1_S : ST_A1_S;
BEGIN
V_A1_S(1) := 11;
V_A1_S(2) := 22;
V_A1_S(3) := 33;
wait for 5 ns;
assert NOT( V_A1_S(1) = 11 and
V_A1_S(2) = 22 and
V_A1_S(3) = 33 )
report "***PASSED TEST: c03s02b01x00p09n01i00344"
severity NOTE;
assert ( V_A1_S(1) = 11 and
V_A1_S(2) = 22 and
V_A1_S(3) = 33 )
report "***FAILED TEST: c03s02b01x00p09n01i00344 - For each possible index value there should be a distinct element."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p09n01i00344arch;
|
gpl-2.0
|
503eaafb5e219035216c1d7979b1b62f
| 0.617675 | 3.301092 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc487.vhd
| 4 | 2,153 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc487.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p20n01i00487ent IS
END c03s02b01x01p20n01i00487ent;
ARCHITECTURE c03s02b01x01p20n01i00487arch OF c03s02b01x01p20n01i00487ent IS
type MEM is array (positive range <>) of BIT;
type ME1 is array (natural range <>) of Integer;
subtype ME2 is ME1(0 to 3);
subtype M1 is MEM (1 to 5);
procedure F2 (X1 : inout MEM) is
begin
assert NOT((X1'LOW = 1) and (X1'High = 5))
report "***PASSED TEST: c03s02b01x01p20n01i00487"
severity NOTE;
assert ((X1'LOW = 1) and (X1'High = 5))
report "***FAILED TEST: c03s02b01x01p20n01i00487 - For an interface object of mode out, inout, or linkage, if the formal part does not contain a type conversion function, then the index ranges are obtained from the object denoted by the actual designator."
severity ERROR;
end F2;
BEGIN
TESTING: PROCESS
variable S1 : M1 := "01110";
BEGIN
F2(S1) ; -- No_failure_here
wait;
END PROCESS TESTING;
END c03s02b01x01p20n01i00487arch;
|
gpl-2.0
|
4940382e1e3dee1fbeddfd677e0ecd12
| 0.673014 | 3.612416 | false | true | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/control/ps2_rx.vhd
| 1 | 5,740 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: PS2_RX
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PS2_RX is
Port (
CLK : in std_logic; -- Vychozi hodinovy signal
RST : in std_logic; -- Vychozi reset
PS2C : in std_logic; -- Hodinovy signal z PS2 portu
PS2D : in std_logic; -- Seriova vstupni data z PS2 portu
PS2RX_DATA : out std_logic_vector(7 downto 0); -- Vystupni data
PS2RX_VALID : out std_logic -- Data jsou pripravena na vycteni
);
end PS2_RX;
architecture FULL of PS2_RX is
signal ps2_valid : std_logic;
signal parity_valid : std_logic;
signal parity_ctrl : std_logic;
signal parity_ps2 : std_logic;
signal ps2_bit_count : unsigned(3 downto 0);
signal sig_ps2rx_data : std_logic_vector(7 downto 0);
signal sig_ps2rx_data2 : std_logic_vector(7 downto 0);
type state is (idle, dps, load);
signal present_st : state;
signal next_st : state;
begin
----------------------------------------------------------------------------
-- FALLING EDGE DETECTOR OF PS/2 CLOCK
----------------------------------------------------------------------------
falling_edge_detector_i : entity work.FALLING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => PS2C,
VYSTUP => ps2_valid -- Pri sestupne hrane jsou validni data
);
----------------------------------------------------------------------------
-- PS2 RX FSM
----------------------------------------------------------------------------
fsm_reg : process (CLK, RST)
begin
if (RST = '1') then
present_st <= idle;
elsif (rising_edge(CLK)) then
present_st <= next_st;
end if;
end process;
-- Rozhodovaci cast stavoveho automatu
process (present_st, PS2D, ps2_valid, ps2_bit_count)
begin
case present_st is
when idle =>
if (ps2_valid = '1' AND PS2D = '0') then
next_st <= dps;
else
next_st <= idle;
end if;
when dps =>
if (to_integer(ps2_bit_count) = 11) then
next_st <= load;
else
next_st <= dps;
end if;
when load =>
next_st <= idle;
end case;
end process;
-- Vystupni cast stavoveho automatu
process (present_st, parity_valid)
begin
case present_st is
when idle =>
PS2RX_VALID <= '0';
when dps =>
PS2RX_VALID <= '0';
when load =>
PS2RX_VALID <= parity_valid;
end case;
end process;
----------------------------------------------------------------------------
-- BIT COUNTER
----------------------------------------------------------------------------
bit_cnt_p : process (CLK, RST)
begin
if (RST = '1') then
ps2_bit_count <= (others => '0');
elsif (rising_edge(CLK)) then
if (to_integer(ps2_bit_count) = 11) then
ps2_bit_count <= (others => '0');
elsif (ps2_valid = '1') then
ps2_bit_count <= ps2_bit_count + 1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PS/2 DATA
----------------------------------------------------------------------------
process (CLK)
begin
if (rising_edge(CLK)) then
if (ps2_valid = '1') then
if (to_integer(ps2_bit_count) > 0 AND to_integer(ps2_bit_count) < 9) then
sig_ps2rx_data(7 downto 0) <= PS2D & sig_ps2rx_data(7 downto 1);
end if;
end if;
end if;
end process;
process (CLK)
begin
if (rising_edge(CLK)) then
if (ps2_valid = '1') then
if (to_integer(ps2_bit_count) = 9) then
parity_ps2 <= PS2D;
end if;
end if;
end if;
end process;
-- Propagace PS2 dat na vystup
process (CLK)
begin
if (rising_edge(CLK)) then
if (to_integer(ps2_bit_count) = 10) then
sig_ps2rx_data2 <= sig_ps2rx_data;
end if;
end if;
end process;
PS2RX_DATA <= sig_ps2rx_data2;
----------------------------------------------------------------------------
-- DATA PARITY CHECK
----------------------------------------------------------------------------
parity_ctrl <= sig_ps2rx_data2(7) xor sig_ps2rx_data2(6) xor
sig_ps2rx_data2(5) xor sig_ps2rx_data2(4) xor
sig_ps2rx_data2(3) xor sig_ps2rx_data2(2) xor
sig_ps2rx_data2(1) xor sig_ps2rx_data2(0) xor '1';
-- Kontrola parity
process (CLK, RST)
begin
if (RST = '1') then
parity_valid <= '0';
elsif (rising_edge(CLK)) then
if (parity_ctrl = parity_ps2) then
parity_valid <= '1';
else
parity_valid <= '0';
end if;
end if;
end process;
end FULL;
|
mit
|
6b79e8e45f181776a38e4020857c663b
| 0.414983 | 4.214391 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc885.vhd
| 4 | 2,352 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc885.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s01b00x00p10n01i00885ent IS
END c10s01b00x00p10n01i00885ent;
ARCHITECTURE c10s01b00x00p10n01i00885arch OF c10s01b00x00p10n01i00885ent IS
signal S: INTEGER := 356;
BEGIN
TESTING: PROCESS
constant I: INTEGER := 105; -- loop parameter has same name
variable k: integer := 0;
BEGIN
-- assign process constant I to S
S <= I;
wait for 1 ns;
assert ( S = 105 )
report "constant not properly assigned to signal"
severity FAILURE;
-- loop parameter has same name as constant declared in process
for I in 1 to 5 loop
-- assign loop parameter I to S
S <= I;
wait for 1 ns;
if ((S<1) or (S>5)) then
k := 1;
end if;
assert ( ( S >= 1 ) and ( S <= 5 ) )
report "loop parameter not properly assigned to signal"
severity FAILURE;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c10s01b00x00p10n01i00885"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c10s01b00x00p10n01i00885 - A declaration region is formed by the text of a loop statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p10n01i00885arch;
|
gpl-2.0
|
168e23339c7bd50e9205e1a0cd1af700
| 0.644558 | 3.805825 | false | true | false | false |
tristanseifert/68komputer
|
VideoPLL.vhd
| 1 | 17,363 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: VideoPLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.0 Build 156 04/24/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY VideoPLL IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END VideoPLL;
ARCHITECTURE SYN OF videopll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 960,
clk0_duty_cycle => 50,
clk0_multiply_by => 1007,
clk0_phase_shift => "0",
clk1_divide_by => 480,
clk1_duty_cycle => 50,
clk1_multiply_by => 1007,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 41666,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=VideoPLL",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.174999"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.349998"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.35000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "VideoPLL.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "960"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "480"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1007"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
bsd-2-clause
|
a284ebba21c92cb0dfefcbda7c3fcf5b
| 0.684617 | 3.282851 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bb.vhd
| 4 | 3,254 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bb.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_behavioral of mac_test is
signal clk, clr, ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
s_real, s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag, s_real, s_imag,
ovf );
s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
end architecture bench_behavioral;
|
gpl-2.0
|
bce8b2074c9aa99bac114cfe0aaf8efd
| 0.555931 | 3.035448 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc701.vhd
| 4 | 3,130 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc701.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:07 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:41 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:45 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00701ent IS
END c03s04b01x00p23n01i00701ent;
ARCHITECTURE c03s04b01x00p23n01i00701arch OF c03s04b01x00p23n01i00701ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of NATURAL;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.08";
-- Declare a variable into which we will read.
constant CON : NATURAL := 1;
variable VAR : NATURAL;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00701"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00701 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00701arch;
|
gpl-2.0
|
d5b5e94a27a24ecf8f715ec7a27a4934
| 0.545048 | 4.033505 | false | true | false | false |
stnolting/neo430
|
rtl/top_templates/neo430_top_axi4lite.vhd
| 1 | 15,832 |
-- #################################################################################################
-- # << NEO430 - Processor Top Entity with AXI4-Lite-Compatible Master Interface >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_top_axi4lite is
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 32kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 28kB (default=2kB)
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := false; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
FREQ_GEN_USE : boolean := true; -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- GPIO --
gpio_o : out std_logic_vector(15 downto 0); -- parallel output
gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_logic_vector(03 downto 0); -- pwm channels
-- arbitrary frequency generator --
freq_gen_o : out std_logic_vector(02 downto 0); -- programmable frequency output
-- UART --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic; -- UART receive data
-- SPI --
spi_sclk_o : out std_logic; -- serial clock line
spi_mosi_o : out std_logic; -- serial data line out
spi_miso_i : in std_logic; -- serial data line in
spi_cs_o : out std_logic_vector(05 downto 0); -- SPI CS
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- external interrupts --
ext_irq_i : in std_logic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_logic_vector(07 downto 0); -- external interrupt request acknowledges
-- AXI Lite-Compatible Master Interface --
-- Clock and Reset
m_axi_aclk : in std_logic;
m_axi_aresetn : in std_logic;
-- Write Address Channel
m_axi_awaddr : out std_logic_vector(31 downto 0);
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awprot : out std_logic_vector(2 downto 0);
-- Write Data Channel
m_axi_wdata : out std_logic_vector(31 downto 0);
m_axi_wstrb : out std_logic_vector(3 downto 0);
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
-- Read Address Channel
m_axi_araddr : out std_logic_vector(31 downto 0);
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_arprot : out std_logic_vector(2 downto 0);
-- Read Data Channel
m_axi_rdata : in std_logic_vector(31 downto 0);
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
-- Write Response Channel
m_axi_bresp : in std_logic_vector(1 downto 0);
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic
);
end neo430_top_axi4lite;
architecture neo430_top_axi4lite_rtl of neo430_top_axi4lite is
-- internal wishbone bus --
type wb_bus_t is record
adr : std_ulogic_vector(31 downto 0); -- address
di : std_ulogic_vector(31 downto 0); -- slave input data
do : std_ulogic_vector(31 downto 0); -- slave output data
we : std_ulogic; -- write enable
sel : std_ulogic_vector(03 downto 0); -- byte enable
stb : std_ulogic; -- strobe
cyc : std_ulogic; -- valid cycle
ack : std_ulogic; -- transfer acknowledge
end record;
signal wb_core : wb_bus_t;
-- other signals for conversion --
signal gpio_o_int : std_ulogic_vector(15 downto 0);
signal gpio_i_int : std_ulogic_vector(15 downto 0);
signal pwm_o_int : std_ulogic_vector(03 downto 0);
signal uart_txd_o_int : std_ulogic;
signal uart_rxd_i_int : std_ulogic;
signal spi_sclk_o_int : std_ulogic;
signal spi_mosi_o_int : std_ulogic;
signal spi_miso_i_int : std_ulogic;
signal spi_cs_o_int : std_ulogic_vector(05 downto 0);
signal irq_i_int : std_ulogic_vector(07 downto 0);
signal irq_ack_o_int : std_ulogic_vector(07 downto 0);
signal freq_gen_o_int : std_ulogic_vector(02 downto 0);
constant usrcode_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(USER_CODE);
-- AXI arbiter --
signal read_trans : std_ulogic;
signal write_trans : std_ulogic;
signal pending_rd : std_ulogic; -- pending read transfer
signal pending_wr : std_ulogic; -- pending write transfer
signal adr_valid : std_ulogic;
signal wresp_ok : std_logic;
begin
-- CPU ----------------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_top_inst: neo430_top
generic map (
-- general configuration --
CLOCK_SPEED => CLOCK_SPEED, -- main clock in Hz
IMEM_SIZE => IMEM_SIZE, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => DMEM_SIZE, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => usrcode_c, -- custom user code
-- module configuration --
MULDIV_USE => MULDIV_USE, -- implement multiplier/divider unit? (default=true)
WB32_USE => WB32_USE, -- implement WB32 unit? (default=true)
WDT_USE => WDT_USE, -- implement WDT? (default=true)
GPIO_USE => GPIO_USE, -- implement GPIO unit? (default=true)
TIMER_USE => TIMER_USE, -- implement timer? (default=true)
UART_USE => UART_USE, -- implement UART? (default=true)
CRC_USE => CRC_USE, -- implement CRC unit? (default=true)
CFU_USE => CFU_USE, -- implement CF unit? (default=false)
PWM_USE => PWM_USE, -- implement PWM controller? (default=true)
TWI_USE => TWI_USE, -- implement two wire serial interface? (default=true)
SPI_USE => SPI_USE, -- implement SPI? (default=true)
TRNG_USE => TRNG_USE, -- implement TRNG? (default=false)
EXIRQ_USE => EXIRQ_USE, -- implement EXIRQ? (default=true)
FREQ_GEN_USE => FREQ_GEN_USE, -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => m_axi_aclk, -- global clock, rising edge
rst_i => m_axi_aresetn, -- global reset, async, LOW-active
-- parallel io --
gpio_o => gpio_o_int, -- parallel output
gpio_i => gpio_i_int, -- parallel input
-- pwm channels --
pwm_o => pwm_o_int, -- pwm channels
-- arbitrary frequency generator --
freq_gen_o => freq_gen_o_int, -- programmable frequency output
-- serial com --
uart_txd_o => uart_txd_o_int, -- UART send data
uart_rxd_i => uart_rxd_i_int, -- UART receive data
spi_sclk_o => spi_sclk_o_int, -- serial clock line
spi_mosi_o => spi_mosi_o_int, -- serial data line out
spi_miso_i => spi_miso_i_int, -- serial data line in
spi_cs_o => spi_cs_o_int, -- SPI CS
twi_sda_io => twi_sda_io, -- twi serial data line
twi_scl_io => twi_scl_io, -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o => wb_core.adr, -- address
wb_dat_i => wb_core.di, -- read data
wb_dat_o => wb_core.do, -- write data
wb_we_o => wb_core.we, -- read/write
wb_sel_o => wb_core.sel, -- byte enable
wb_stb_o => wb_core.stb, -- strobe
wb_cyc_o => wb_core.cyc, -- valid cycle
wb_ack_i => wb_core.ack, -- transfer acknowledge
-- interrupts --
ext_irq_i => irq_i_int, -- external interrupt request line
ext_ack_o => irq_ack_o_int -- external interrupt request acknowledge
);
-- Output Type Conversion ---------------------------------------------------
-- -----------------------------------------------------------------------------
gpio_i_int <= std_ulogic_vector(gpio_i);
uart_rxd_i_int <= std_ulogic(uart_rxd_i);
spi_miso_i_int <= std_ulogic(spi_miso_i);
irq_i_int <= std_ulogic_vector(ext_irq_i);
gpio_o <= std_logic_vector(gpio_o_int);
pwm_o <= std_logic_vector(pwm_o_int);
uart_txd_o <= std_logic(uart_txd_o_int);
spi_sclk_o <= std_logic(spi_sclk_o_int);
spi_mosi_o <= std_logic(spi_mosi_o_int);
spi_cs_o <= std_logic_vector(spi_cs_o_int);
ext_ack_o <= std_logic_vector(irq_ack_o_int);
freq_gen_o <= std_logic_vector(freq_gen_o_int);
-- Wishbone-to-AXI4-Lite-compatible Bridge ----------------------------------
-- -----------------------------------------------------------------------------
-- transfer type --
read_trans <= wb_core.cyc and wb_core.stb and (not wb_core.we);
write_trans <= wb_core.cyc and wb_core.stb and wb_core.we;
-- arbiter --
axi_arbiter: process(m_axi_aclk)
begin
if rising_edge(m_axi_aclk) then
if (wb_core.cyc = '0') then
pending_rd <= '0';
pending_wr <= '0';
adr_valid <= '0';
m_axi_bready <= '0';
else
-- read/write address valid --
if ((wb_core.cyc and wb_core.stb) = '1') then
adr_valid <= '1';
elsif (m_axi_awready = '1') or (m_axi_arready = '1') then
adr_valid <= '0';
end if;
-- transfer read data --
if (read_trans = '1') then
pending_rd <= '1';
elsif (m_axi_rvalid = '1') then
pending_rd <= '0';
end if;
-- transfer write data --
if (write_trans = '1') then
pending_wr <= '1';
elsif (m_axi_wready = '1') then
pending_wr <= '0';
end if;
-- write response channel -
if (write_trans = '1') then
m_axi_bready <= '1';
elsif (m_axi_bvalid = '1') then
m_axi_bready <= '0';
end if;
end if;
end if;
end process axi_arbiter;
-- Acknowledge Wishbone transfer --
wb_core.ack <= (pending_rd and std_ulogic(m_axi_rvalid)) or -- read transfer
-- (pending_wr and std_ulogic(m_axi_wready)); -- write transfer
(wresp_ok and m_axi_bvalid); -- acknowledged write transfer
-- Read Address Channel --
m_axi_araddr <= std_logic_vector(wb_core.adr);
m_axi_arvalid <= std_logic(adr_valid) and std_logic(pending_rd);
m_axi_arprot <= "000"; -- data access, secure, unprivileged
-- Read Data Channel --
wb_core.di <= std_ulogic_vector(m_axi_rdata);
m_axi_rready <= std_logic(pending_rd);
-- Write Address Channel --
m_axi_awaddr <= std_logic_vector(wb_core.adr);
m_axi_awvalid <= std_logic(adr_valid) and std_logic(pending_wr);
m_axi_awprot <= "000"; -- data access, secure, unprivileged
-- Write Data Channel --
m_axi_wdata <= std_logic_vector(wb_core.do);
m_axi_wstrb <= std_logic_vector(wb_core.sel);
m_axi_wvalid <= std_logic(pending_wr);
-- Write Data Response Channel --
wresp_ok <= '1' when (m_axi_bresp = "00") else '0';
end neo430_top_axi4lite_rtl;
|
bsd-3-clause
|
85f6e55dbd8f40a31965fb880dcda01e
| 0.536445 | 3.821385 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_04.vhd
| 4 | 1,892 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_04 is
end entity ch_03_04;
architecture test of ch_03_04 is
type opcode_type is (opcode_1, opcode_2, halt_opcode);
signal opcode : opcode_type := opcode_1;
signal halt_indicator : boolean := false;
begin
process_3_1_d : process (opcode) is
variable PC : integer := 0;
constant effective_address : integer := 1;
variable executing : boolean := true;
begin
-- code from book:
if opcode = halt_opcode then
PC := effective_address;
executing := false;
halt_indicator <= true;
end if;
-- end of code from book
end process process_3_1_d;
stimulus : process is
begin
opcode <= opcode_2 after 100 ns, halt_opcode after 200 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
4ed0209e41675f0d269e3e6875ce782e
| 0.60148 | 4.232662 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/control.vhd
| 2 | 15,689 |
---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
when "001100" => --SYSCALL
is_syscall := '1';
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
--when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
when "010001" => --FTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--when "110001" => --TGEU
--when "110010" => --TLT
--when "110011" => --TLTU
--when "110100" => --TEQ
--when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
--when "00010" => --BLTZL lbranch=r[rs]<0;
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
--when "00011" => --BGEZL lbranch=r[rs]>=0;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
end if;
--when "010001" => --COP1
--when "010010" => --COP2
--when "010011" => --COP3
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
--when "010110" => --BLEZL lbranch=r[rs]<=0;
--when "010111" => --BGTZL lbranch=r[rs]>0;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
--when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--when "101110" => --SWR //Not Implemented
--when "101111" => --CACHE
--when "110000" => --LL r[rt]=*(long*)ptr;
--when "110001" => --LWC1
--when "110010" => --LWC2
--when "110011" => --LWC3
--when "110101" => --LDC1
--when "110110" => --LDC2
--when "110111" => --LDC3
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
--when "111001" => --SWC1
--when "111010" => --SWC2
--when "111011" => --SWC3
--when "111101" => --SDC1
--when "111110" => --SDC2
--when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH;
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
|
mit
|
8dd70835eb5002582824f45226a8a59b
| 0.526165 | 3.092647 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1902.vhd
| 4 | 3,460 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1902.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01902pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01902pkg;
use work.c07s01b00x00p08n01i01902pkg.all;
ENTITY c07s01b00x00p08n01i01902ent_a IS
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
END c07s01b00x00p08n01i01902ent_a;
ARCHITECTURE c07s01b00x00p08n01i01902arch_a OF c07s01b00x00p08n01i01902ent_a IS
BEGIN
assert true;
END c07s01b00x00p08n01i01902arch_a;
use work.c07s01b00x00p08n01i01902pkg.all;
ENTITY c07s01b00x00p08n01i01902ent IS
END c07s01b00x00p08n01i01902ent;
ARCHITECTURE c07s01b00x00p08n01i01902arch OF c07s01b00x00p08n01i01902ent IS
constant bus_width : natural := 7;
signal s_int : small_int := 0;
signal ibus, obus, obus2 : cmd_bus(small_int);
component test
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width));
signal out_bus : out cmd_bus (0 to small_int(bus_width)));
end component;
BEGIN
b: block ( s_int = 0 )
signal bool : boolean := false;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 =>
tmp := 0;
when others =>
tmp := 1;
end case;
return tmp;
end value;
for c : test use entity work.c07s01b00x00p08n01i01902ent_a(c07s01b00x00p08n01i0190293_arch_a);
begin
obus <= (0 => 1, others => value) after 5 ns;
s: bool <= s_int = ibus'right(1) after 5 ns;
c : test port map ( ibus, b ); -- block label illegal here
p: process ( s_int )
begin
l: for i in small_int loop
assert false
report "block label accepted as primary in a component instantiation port map expression."
severity note ;
exit l;
end loop l;
end process p;
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01902 - Block labels are not permitted as primaries in a component instantiation port map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01902arch;
|
gpl-2.0
|
637a23a5bdfc552eb84f9d7ebb5d4246
| 0.654335 | 3.352713 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-qs.vhd
| 4 | 3,619 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-qs.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
architecture queue_server of test_bench is
use qsim.qsim_types.all;
use random.random.all;
signal source_arc, queue_arc, server_arc : arc_type;
signal server_ready : boolean;
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(1),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => source_arc,
info_detail => info_detail );
queue1 : entity qsim.queue(behavior)
generic map ( name => "queue1",
time_unit => ns,
info_file_name => "queue1.dat" )
port map ( in_arc => source_arc,
out_arc => queue_arc, out_ready => server_ready,
info_detail => info_detail );
server1 : entity qsim.server(behavior)
generic map ( name => "server1",
distribution => fixed, mean_service_time => 120 ns,
seed => sample_seeds(2),
time_unit => ns,
info_file_name => "server1.dat" )
port map ( in_arc => queue_arc, in_ready => server_ready,
out_arc => server_arc,
info_detail => info_detail );
sink1 : entity qsim.sink(behavior)
generic map ( name => "sink1",
time_unit => ns,
info_file_name => "sink1.dat" )
port map ( in_arc => server_arc,
info_detail => info_detail );
source_monitor : process is
variable L : line;
begin
wait on source_arc;
write(L, string'("source_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, source_arc.token, ns);
writeline(output, L);
end process source_monitor;
queue_monitor : process is
variable L : line;
begin
wait on queue_arc;
write(L, string'("queue_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, queue_arc.token, ns);
writeline(output, L);
end process queue_monitor;
server_monitor : process is
variable L : line;
begin
wait on server_arc;
write(L, string'("server_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, server_arc.token, ns);
writeline(output, L);
end process server_monitor;
end architecture queue_server;
|
gpl-2.0
|
4584eb98105177bf73196fcd5c9526cd
| 0.565902 | 3.950873 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc784.vhd
| 4 | 2,624 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc784.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p12n04i00784ent_a IS
port ( C1 : in bit_vector;
C2 : out bit_vector;
C3 : inout bit_vector;
C4 : buffer bit_vector;
C5 : linkage bit_vector);
END c01s01b01x02p12n04i00784ent_a;
ARCHITECTURE c01s01b01x02p12n04i00784arch_a OF c01s01b01x02p12n04i00784ent_a IS
BEGIN
END c01s01b01x02p12n04i00784arch_a;
ENTITY c01s01b01x02p12n04i00784ent IS
port ( P1 : in bit_vector(15 downto 0);
P2 : out bit_vector(15 downto 0);
P3 : inout bit_vector(15 downto 0);
P4 : buffer bit_vector(15 downto 0);
P5 : linkage bit_vector(15 downto 0));
END c01s01b01x02p12n04i00784ent;
ARCHITECTURE c01s01b01x02p12n04i00784arch OF c01s01b01x02p12n04i00784ent IS
component c01s01b01x02p12n04i00784ent_b
port ( C1 : in bit_vector;
C2 : out bit_vector;
C3 : inout bit_vector;
C4 : buffer bit_vector;
C5 : linkage bit_vector);
end component;
for L : c01s01b01x02p12n04i00784ent_b use entity work.c01s01b01x02p12n04i00784ent_a(c01s01b01x02p12n04i00784arch_a);
BEGIN
L : c01s01b01x02p12n04i00784ent_b
port map (C1 => p1, C2 => p2, C3 => p3, C4 => p4, C5 => p5);
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p12n04i00784"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p12n04i00784arch;
|
gpl-2.0
|
c014393e02e3d3572a9adabbe2f3a8a2
| 0.647485 | 3.203907 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3083.vhd
| 4 | 2,028 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3083.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b03x00p02n01i03083ent IS
END c12s06b03x00p02n01i03083ent;
ARCHITECTURE c12s06b03x00p02n01i03083arch OF c12s06b03x00p02n01i03083ent IS
signal S1 : BIT;
signal X1 : BIT;
signal S : integer := 1;
BEGIN
S1 <= transport '1' after 5 ns;
A : block(X1 = '1')
begin
process(GUARD)
begin
if GUARD then
assert false
report "Failure on test. Guard value shouldn't have been changed" ;
S <= 0;
end if;
end process;
end block A;
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT(S = 1)
report "***PASSED TEST: c12s06b03x00p02n01i03083"
severity NOTE;
assert (S = 1)
report "***FAILED TEST: c12s06b03x00p02n01i03083 - GUARD signal is not modified in the test."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b03x00p02n01i03083arch;
|
gpl-2.0
|
ca4708782da4e094a307eea731d05206
| 0.649901 | 3.687273 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_04.vhd
| 4 | 3,272 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity phase_locked_clock_gen is
port ( reference : in std_ulogic;
phi1, phi2 : out std_ulogic );
end entity phase_locked_clock_gen;
architecture std_cell of phase_locked_clock_gen is
--use work.clock_pkg.Tpw;
use work.clock_pkg.all;
begin
phi1_gen : phi1 <= '1', '0' after Tpw when rising_edge(reference);
phi2_gen : phi2 <= '1', '0' after Tpw when falling_edge(reference);
end architecture std_cell;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
entity io_controller is
port ( ref_clock : in std_ulogic; -- . . . );
-- not in book
other_port : in std_ulogic );
-- end not in book
end entity io_controller;
--------------------------------------------------
architecture top_level of io_controller is
-- . . .
-- not in book
signal rd, wr, sel, width, burst : std_ulogic;
signal addr : std_ulogic_vector(1 downto 0);
signal ready : std_ulogic;
signal control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
other_signal : std_ulogic;
-- end not in book
begin
internal_clock_gen : entity work.phase_locked_clock_gen(std_cell)
port map ( reference => ref_clock,
phi1 => work.clock_pkg.clock_phase1,
phi2 => work.clock_pkg.clock_phase2 );
the_bus_sequencer : entity work.bus_sequencer(fsm)
port map ( rd, wr, sel, width, burst, addr(1 downto 0), ready,
control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
-- . . . );
other_signal );
-- not in book
-- . . .
end architecture top_level;
|
gpl-2.0
|
fb722143fc0cfd743aa12b20ea2da130
| 0.500306 | 4.48834 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1167.vhd
| 4 | 1,989 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1167.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p04n02i01167ent IS
END c06s06b00x00p04n02i01167ent;
ARCHITECTURE c06s06b00x00p04n02i01167arch OF c06s06b00x00p04n02i01167ent IS
attribute p: POSITIVE;
signal s: integer;
attribute p of s: signal is 10;
BEGIN
TESTING: PROCESS
BEGIN
if s'p = 10 then -- Success_here
s <= 12;
else
s <= 0;
end if;
wait for 10 ns;
assert NOT( s=12 )
report "***PASSED TEST: c06s06b00x00p04n02i01167"
severity NOTE;
assert ( s=12 )
report "***FAILED TEST: c06s06b00x00p04n02i01167 - The meaning of the prefix of an attribute must be determinable independently of the attribute designator and independently of the fact that it is the prefix of an attribute."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p04n02i01167arch;
|
gpl-2.0
|
f3427e4295f004ae95734e08c55a911a
| 0.670186 | 3.717757 | false | true | false | false |
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.b.a.a-tbAdder.vhd
| 1 | 1,131 |
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
entity tbAdder is
end tbAdder;
architecture tb_adder_arch of tbAdder is
constant N: integer:=32;
signal a, b, s1: std_logic_vector(N-1 downto 0):=x"00000000";
signal cin, cout1: std_logic:='0';
component Adder is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
cin : in std_logic;
a, b : in std_logic_vector(DATA_SIZE-1 downto 0);
s : out std_logic_vector(DATA_SIZE-1 downto 0);
cout : out std_logic
);
end component;
begin
ADDER1 : Adder
generic map(N)
port map(cin, a, b, s1, cout1);
a <= x"ffffffff", x"04532434" after 1 ns, x"2234e826" after 2 ns, x"a323f443" after 3 ns, x"8b651a8b" after 4 ns, x"ffffffff" after 5 ns;
b <= x"00000001", x"05335f28" after 1.5 ns, x"23323424" after 2.5 ns, x"11645030" after 3.5 ns, x"030035a6" after 4.5 ns, x"00000001" after 5.5 ns, x"12334224" after 7 ns;
cin <= '0', '1' after 3.3 ns, '0' after 4.6 ns, '1' after 6 ns;
end tb_adder_arch;
configuration tb_adder_cfg of tbAdder is
for tb_adder_arch
end for;
end tb_adder_cfg;
|
mit
|
68e53f6cd98249b6a4e40da363c46094
| 0.674624 | 2.496689 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1356.vhd
| 4 | 1,997 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1356.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01356ent IS
END c08s05b00x00p03n01i01356ent;
ARCHITECTURE c08s05b00x00p03n01i01356arch OF c08s05b00x00p03n01i01356ent IS
BEGIN
TESTING: PROCESS
type t1 is record
ele1 : integer;
ele2 : real;
end record;
variable f1: t1;
variable i : integer := 0;
variable r : real := 0.0;
BEGIN
f1.ele1 := 1;
f1.ele2 := 2.3;
i := f1.ele1;
r := f1.ele2;
assert NOT((i=1) and (r=2.3))
report "***PASSED TEST: c08s05b00x00p03n01i01356"
severity NOTE;
assert ((i=1) and (r=2.3))
report "***FAILED TEST: c08s05b00x00p03n01i01356 - Target and the expression on the right-hand side should have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01356arch;
|
gpl-2.0
|
7721368935bd77f6cace7dcf8e4eb2ac
| 0.637957 | 3.528269 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd
| 4 | 2,232 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_adc is
end tb_adc;
architecture tb_adc of tb_adc is
-- Component declarations
-- Signal declarations
signal clk_in : bit;
signal clk_in_tmp : std_logic;
signal dig_out1, dig_out2 : bit;
terminal sine_in : electrical;
quantity gain : real;
begin
-- Signal assignments
clk_in <= To_bit(clk_in_tmp); -- convert std_logic to bit
-- Component instances
v1 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 5.0
)
port map(
pos => sine_in,
neg => ELECTRICAL_REF
);
adc25 : entity work.adc(struct)
port map(
gain => gain,
a => sine_in,
d_out => dig_out1,
clk => clk_in
);
adc26 : entity work.adc(ideal)
port map(
gain => gain,
a => sine_in,
d_out => dig_out2,
clk => clk_in
);
clock1 : entity work.clock_duty(ideal)
generic map(
on_time => 1 ms,
off_time => 0.5 ms
)
port map(
CLOCK_OUT => clk_in_tmp
);
src1 : entity work.src_constant(ideal)
generic map(
level => 1.0
)
port map(
output => gain
);
end tb_adc;
|
gpl-2.0
|
207b711530bf9593f252400456abe001
| 0.59543 | 3.808874 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/numeric_bit_unsigned.vhdl
| 4 | 26,358 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT_UNSIGNED package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type BIT_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the BIT_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package NUMERIC_BIT_UNSIGNED is
constant CopyRightNotice : STRING :=
"Copyright 2008 IEEE. All rights reserved.";
-- Id: A.3
function "+" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit bit_vector
-- Id: A.3L
function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function "?>" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function "?<" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function "?<=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function "?>=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function "?=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function "?/=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
return BIT_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Bit_Vector is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_Bit_Vector is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
end package NUMERIC_BIT_UNSIGNED;
|
gpl-2.0
|
5915fe04b65812d8ee1dd49d89a8b607
| 0.540633 | 4.294233 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1678.vhd
| 4 | 1,949 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1678.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p08n01i01678ent IS
END c09s01b00x00p08n01i01678ent;
ARCHITECTURE c09s01b00x00p08n01i01678arch OF c09s01b00x00p08n01i01678ent IS
signal S2 : integer := 2;
BEGIN
B: block
generic ( G1 : INTEGER;
G2 : STRING);
generic map ( G1 => 10,
G2 => "Hi");
port ( P1 : INTEGER);
port map ( P1 => S2);
begin
assert NOT( G1 = 10 and G2 = "Hi" and P1 = 2 )
report "***PASSED TEST: c09s01b00x00p08n01i01678"
severity NOTE;
assert ( G1 = 10 and G2 = "Hi" and P1 = 2 )
report "***FAILED TEST: c09s01b00x00p08n01i01678 - Certain values do not be imported from the enclosing enviornment into the block."
severity ERROR;
end block;
END c09s01b00x00p08n01i01678arch;
|
gpl-2.0
|
d56aca02616b2102cb55ff3cdd293939
| 0.638276 | 3.556569 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc183.vhd
| 4 | 2,495 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc183.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s04b00x00p04n02i00183pkg is
attribute a1 : integer;
attribute a2 : integer;
attribute a1 of c04s04b00x00p04n02i00183pkg : package is 3;
constant c1 : integer := c04s04b00x00p04n02i00183pkg'a1;
attribute a2 of c04s04b00x00p04n02i00183pkg : package is c1 * 2;
function fn1 return integer;
function fn2 return integer;
end c04s04b00x00p04n02i00183pkg;
package body c04s04b00x00p04n02i00183pkg is
constant t1 : integer := 3; --testgen'a1;
constant t2 : integer := 6; --testgen'a2;
function fn1 return integer is
begin
return t1;
end;
function fn2 return integer is
begin
return t2;
end;
end c04s04b00x00p04n02i00183pkg;
use work.c04s04b00x00p04n02i00183pkg.all;
ENTITY c04s04b00x00p04n02i00183ent IS
END c04s04b00x00p04n02i00183ent;
ARCHITECTURE c04s04b00x00p04n02i00183arch OF c04s04b00x00p04n02i00183ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( c1 = 3 and fn1 = c1 and fn2 = c1+c1 )
report "***PASSED TEST: c04s04b00x00p04n02i00183"
severity NOTE;
assert ( c1 = 3 and fn1 = c1 and fn2 = c1+c1 )
report "***FAILED TEST: c04s04b00x00p04n02i00183 - Package attribute test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p04n02i00183arch;
|
gpl-2.0
|
1687334acd5667f45428ec41fb2d3137
| 0.682164 | 3.248698 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_12.vhd
| 4 | 2,544 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package fg_11_12 is
procedure init_synchronize ( signal synch : out std_logic );
procedure begin_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs );
procedure end_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs );
end package fg_11_12;
package body fg_11_12 is
-- code from book
procedure init_synchronize ( signal synch : out std_logic ) is
begin
synch <= '0';
end procedure init_synchronize;
procedure begin_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs ) is
begin
synch <= 'Z' after Tdelay;
wait until synch = 'H';
end procedure begin_synchronize;
procedure end_synchronize ( signal synch : inout std_logic;
Tdelay : in delay_length := 0 fs ) is
begin
synch <= '0' after Tdelay;
wait until synch = '0';
end procedure end_synchronize;
-- end code from book
end package body fg_11_12;
|
gpl-2.0
|
e1c2495f3d6f126617e35c4d49d950e8
| 0.516116 | 5.077844 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc414.vhd
| 4 | 2,997 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc414.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00414ent IS
END c03s02b01x01p19n01i00414ent;
ARCHITECTURE c03s02b01x01p19n01i00414arch OF c03s02b01x01p19n01i00414ent IS
constant C1 : positive := 1;
function complex_scalar(s : positive) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return positive is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : positive;
signal S2 : positive;
signal S3 : positive := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00414"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00414 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00414arch;
|
gpl-2.0
|
1d6580285a6082ece1340bb31b4a08ac
| 0.651985 | 3.7 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/bug18351/18351.vhd
| 3 | 1,419 |
entity PROBLEM is
end PROBLEM;
architecture BUG of PROBLEM is
-- original testcase used std_logic_vector but other types suffer too
type t_int_ptr is access integer;
function ISSUE_HERE return t_int_ptr is
begin
return new integer;
end ISSUE_HERE;
-- do functions with parameters work?
function ISSUE_2(I : Integer) return t_int_ptr is
variable Temp : t_int_ptr;
begin
Temp := new integer;
Temp.all := I;
return Temp;
end ISSUE_2;
function ISSUE_3 return t_int_ptr is
variable Temp : t_int_ptr;
begin
Temp := new integer;
Temp.all := 33;
return Temp;
end ISSUE_3;
-- original testcase passed the result as param to a procedure
-- so test passing parameters too
procedure ANY_STUFF(param: in integer) is
begin
report "Integer value " & integer'image(param) severity note;
end procedure;
begin
eval : process is
variable X : t_int_ptr;
variable Y : integer;
begin
X := ISSUE_HERE;
ANY_STUFF(X.all); -- Test case (1) : works
--Y := ISSUE_2(55).all; -- Test case (2) : used to fail; works with first patch
--ANY_STUFF(Y);
Y := ISSUE_HERE.all; -- Test case (3) : fails
ANY_STUFF(Y);
ANY_STUFF(ISSUE_HERE.all); -- Test case (4) : fails
Y := ISSUE_3.all; -- Test case (5) : fails
ANY_STUFF(Y);
ANY_STUFF(ISSUE_3.all); -- Test case (6) : fails
wait;
end process;
end BUG;
|
gpl-2.0
|
6e400e186146ae526150834dd5024dc5
| 0.634954 | 3.378571 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_05.vhd
| 4 | 5,541 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_05.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity master_slave_flipflop is
port ( phi1, phi2 : in std_logic;
d : in std_logic;
q : out std_logic );
end entity master_slave_flipflop;
architecture behavioral of master_slave_flipflop is
signal master_d : std_logic;
begin
master_d <= d when phi1 = '1';
q <= master_d when phi2 = '1';
end architecture behavioral;
-- code from book
library ieee; use ieee.std_logic_1164.all;
entity shift_reg is
port ( phi1, phi2 : in std_logic;
serial_data_in : in std_logic;
parallel_data : inout std_logic_vector );
end entity shift_reg;
--------------------------------------------------
architecture cell_level of shift_reg is
alias normalized_parallel_data :
std_logic_vector(0 to parallel_data'length - 1)
is parallel_data;
component master_slave_flipflop is
port ( phi1, phi2 : in std_logic;
d : in std_logic;
q : out std_logic );
end component master_slave_flipflop;
begin
reg_array : for index in normalized_parallel_data'range generate
begin
first_cell : if index = 0 generate
begin
cell : component master_slave_flipflop
port map ( phi1, phi2,
d => serial_data_in,
q => normalized_parallel_data(index) );
end generate first_cell;
other_cell : if index /= 0 generate
begin
cell : component master_slave_flipflop
port map ( phi1, phi2,
d => normalized_parallel_data(index - 1),
q => normalized_parallel_data(index) );
end generate other_cell;
end generate reg_array;
end architecture cell_level;
-- end code from book
library ieee; use ieee.std_logic_1164.all;
entity fg_14_05 is
end entity fg_14_05;
architecture test of fg_14_05 is
signal phi1, phi2, serial_data_in : std_logic := '0';
signal parallel_data : std_logic_vector(3 downto 0);
begin
dut : entity work.shift_reg(cell_level)
port map ( phi1 => phi1, phi2 => phi2,
serial_data_in => serial_data_in,
parallel_data => parallel_data );
clock_gen : process is
begin
phi1 <= '1', '0' after 4 ns;
phi2 <= '1' after 5 ns, '0' after 9 ns;
wait for 10 ns;
end process clock_gen;
stimulus : process is
begin
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0';
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
ad0a1ebfb5fde7ea4d96a13e22ea3a00
| 0.454972 | 4.672007 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd
| 4 | 1,769 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- code from book
entity battery is
port ( terminal plus, minus : electrical );
end entity battery;
architecture wrong of battery is
constant v_nominal : real := 9.0;
quantity v across plus to minus;
begin
v == v_nominal;
end architecture wrong;
--
architecture correct of battery is
constant v_nominal : real := 9.0;
quantity v across i through plus to minus;
begin
v == v_nominal;
end architecture correct;
-- end code from book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
signal clamp : bit;
quantity v1, v2 : real;
begin
-- code from book
if clamp = '1' use
v1 == 5.0;
v2 == 0.0;
else
v1 == v2;
end use;
-- end code from book
end architecture test;
|
gpl-2.0
|
f0b99cdf9a7659af0dd06be3ca4cd5a1
| 0.677219 | 3.975281 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug17309/polyamplib.vhdl
| 3 | 58,980 |
-----------------------------------------------------------------------------
-- Polyamp vhdl function library
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package polyamplib is
component interface_ads1271
port (
fastclk : in std_logic; -- Fast clock
adclk : in std_logic; -- A/D converter clock
resync : in std_logic; -- Clock change; resync
ser_data : in std_logic; -- Serial data in
n_drdy : in std_logic; -- Data is ready, active low
data_out : out std_logic_vector(23 downto 0); -- Parallell data out
nsync : out std_logic; -- Synchronize (restart) A/D conv.
busy : out std_logic; -- Busy reading serial data
g_sclk : out std_logic); -- Gated SPI clock, FOR SIMULATION ONLY
end component;
component priority_resolver2 is
port (
inp : in std_logic_vector(11 downto 0);
prio : out unsigned(3 downto 0); -- Output highest signal
active : out std_logic); -- High when any input is active
end component;
component one_of_n_encoder is
port (
number : in unsigned(3 downto 0);
enable : in std_logic;
single_out : out std_logic_vector(11 downto 0)); -- Only a single wire is active at a time
end component;
component active_input is
port (
fastclk : in std_logic; -- Main clock
enable : in std_logic; -- Enable signal
busy_n : in std_logic; -- Busy input signal, active low
clear : in std_logic; -- Clear the corresponding flip-flop
active_out : out std_logic); -- Active output
end component;
component master_state_machine is
port (
fastclk : in std_logic := '0'; -- Main clock
enable_lo8 : in std_logic; -- Enable the 8 low inputs
busy_n_vec : in std_logic_vector(11 downto 0); -- Busy inputs
id_code : inout unsigned(3 downto 0); -- Id code output
fifo_write : out std_logic); -- Save to fifo
end component;
component fifo_memory is
generic (
fifo_size : natural := 100);
port (
clock : in std_logic;
sclr : in std_logic;
datain : in std_logic_vector(31 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
dataout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
meter : out unsigned(7 downto 0));
end component;
component fifo_ft_memory is
generic (
fifo_size : natural := 100);
port (
clock : in std_logic;
sclr : in std_logic;
datain : in std_logic_vector(31 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
dataout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
meter : out unsigned(7 downto 0));
end component;
component ads1271_model is
port (
analog_in : in signed(23 downto 0); -- Analog input signal
clk : in std_logic; -- Conversion clock
sclk : in std_logic; -- SPI clock
n_sync : in std_logic; -- Input sync signal, active low
din : in std_logic; -- Serial data in
dout : out std_logic; -- Serial data out
n_drdy : out std_logic); -- Data ready, active low
end component;
component sr_sipo is
generic (
LENGTH : positive := 8; --! Shift register length
EDGE : natural := 1; --! Active edge; 1=positive, 0=negative
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
clk : in std_logic; --! Clock input
ser_in : in std_logic; --! Serial input data
par_out : out std_logic_vector(1 to LENGTH)); --! Parallel output data
end component;
component sr_piso is
generic (
LENGTH : positive := 8; --! Shift register length
EDGE : natural := 1; --! Active edge; 1=positive, 0=negative
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
clk : in std_logic; --! Clock input
load : in std_logic; --! Load on next clock
par_in : in std_logic_vector(1 to LENGTH); --! Parallel input data
ser_in : in std_logic; --! Serial input data
ser_out : out std_logic); --! Serial output data
end component;
component sr_piso_s is
generic (
LENGTH : positive := 8; --! Shift register length
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
fastclk : in std_logic; --! Synchronous clock
clk_en : in std_logic; --! Clock enable input
load_en : in std_logic; --! Load enable input
par_in : in std_logic_vector(1 to LENGTH); --! Parallel input data
ser_in : in std_logic; --! Serial input data
ser_out : out std_logic); --! Serial output data
end component;
component spi_slave is
port (
-- Main controls
fastclk : in std_logic;
spi_tx : in std_logic_vector(31 downto 0); -- Data to be sent
spi_rx : out std_logic_vector(31 downto 0); -- Data to be received
spi_op : out std_logic; -- Read/Write status/data/command
-- Slave port, connected to CPU
mosi : in std_logic;
miso : out std_logic;
sck : in std_logic; -- SPI clock
en_adc : in std_logic; -- Active low, enable ADC
en_incl : in std_logic; -- Active low, enable inclinometer
-- Master port, connected to inclinometer
incl_miso : in std_logic;
incl_mosi : out std_logic;
incl_sck : out std_logic;
incl_ena : out std_logic); -- Active low, enable inclinometer
end component;
component command_decoder is
port (
addr_data : in std_logic_vector(31 downto 0); -- Input address/data
decode : in std_logic; -- Single cycle decode pulse
fastclk : in std_logic; -- Master clock (not used for now)
sel_nulcmd : out std_logic; -- NULL command (no operation)
sel_adclk0 : out std_logic; -- Select sampling clock, ad0.
sel_adclk1 : out std_logic; -- Select sampling clock, ad1.
sel_adclk2 : out std_logic; -- Select sampling clock, ad2.
sel_adclk3 : out std_logic; -- Select sampling clock, ad3.
sel_adclk4 : out std_logic; -- Select sampling clock, ad4.
sel_adclk5 : out std_logic; -- Select sampling clock, ad5.
sel_adclk6 : out std_logic; -- Select sampling clock, ad6.
sel_adclk7 : out std_logic; -- Select sampling clock, ad7.
resync_adc : out std_logic; -- Resynchronize all ADC's
write_ctrl : out std_logic; -- Write to control-signal register
start_adcs : out std_logic; -- Start AD-conversion
stop_adcs : out std_logic); -- Stop AD-conversion
end component;
component clockmux is
port (
clk24M : in std_logic; -- Input clocks, 24 576 000
clk4M : in std_logic; -- 4 096 000
clk2M : in std_logic; -- 2 048 000
clk1M : in std_logic; -- 1 024 000
clk512k : in std_logic; -- 512 000
clk256k : in std_logic; -- 256 000
clk128k : in std_logic; -- 128 000
sel : in unsigned(2 downto 0); -- Mux select input
clkout : out std_logic); -- Output clock
end component;
component spi_master is
port (
-- Hardware ports
miso : in std_logic;
mosi : out std_logic;
sck : inout std_logic;
en_adval : out std_logic := '1';
en_incl : out std_logic := '1';
-- Simulation ports
data_to_spi : in std_logic_vector(31 downto 0);
data_from_spi : out std_logic_vector(31 downto 0);
start : in std_logic;
busy : out std_logic := '0';
running : in std_logic);
end component;
component spi_slave_burst is
port (
-- Main controls
fastclk : in std_logic;
spi_tx : in std_logic_vector(31 downto 0); -- Data to be sent
spi_rx : out std_logic_vector(31 downto 0); -- Data to be received
exec_cmd : out std_logic; -- Write command/data
fifo_read : out std_logic; -- Read status/data
-- Slave port, connected to CPU
mosi : in std_logic;
miso : out std_logic;
sck : in std_logic; -- SPI clock
en_adc : in std_logic; -- Active low, enable ADC
en_incl : in std_logic; -- Active low, enable inclinometer
-- Master port, connected to inclinometer
incl_miso : in std_logic;
incl_mosi : out std_logic;
incl_sck : out std_logic;
incl_ena : out std_logic); -- Active low, enable inclinometer
end component;
component sync_logic_2 is
port (
start_adcs : in std_logic; -- Start command
stop_adcs : in std_logic; -- Stop command
reset : in std_logic; -- Active high
hwsync : in std_logic; -- Hardware sync
fastclk : in std_logic; -- Master clock
enable_adcvalues : out std_logic); -- Enable reception of values
end component;
end polyamplib;
-----------------------------------------------------------------------------
-- Shift register for adc_interface, spi_interface etc.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! General serial input, parallell output shift register
--! The shift register length is generic, from 2 and up. It can trigger on
--! positive or negative edges, and the shift direction can be choosen as well.
entity sr_sipo is
generic (
LENGTH : positive := 8; --! Shift register length
EDGE : natural := 1; --! Active edge; 1=positive, 0=negative
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
clk : in std_logic; --! Clock input
ser_in : in std_logic; --! Serial input data
par_out : out std_logic_vector(1 to LENGTH)); --! Parallel output data
end sr_sipo;
architecture sr_arch of sr_sipo is
signal my_sr : std_logic_vector(1 to LENGTH);
begin -- sr_arch
posedge_right : if (EDGE = 1) and (DIR = 1) generate
shift : process(clk)
begin
if clk'event and clk = '1' then -- Positive clock edge
my_sr(1 to LENGTH) <= (my_sr(2 to LENGTH) & ser_in);
end if;
end process shift;
end generate posedge_right;
posedge_left : if (EDGE = 1) and (DIR /= 1) generate
shift : process(clk)
begin
if clk'event and clk = '1' then -- Positive clock edge
my_sr(1 to LENGTH) <= (ser_in & my_sr(1 to LENGTH-1));
end if;
end process shift;
end generate posedge_left;
negedge_right : if (EDGE /= 1) and (DIR = 1) generate
shift : process(clk)
begin
if clk'event and clk = '0' then -- Negative clock edge
my_sr(1 to LENGTH) <= (my_sr(2 to LENGTH) & ser_in);
end if;
end process shift;
end generate negedge_right;
negedge_left : if (EDGE /= 1) and (DIR /= 1) generate
shift : process(clk)
begin
if clk'event and clk = '0' then -- Negative clock edge
my_sr(1 to LENGTH) <= (ser_in & my_sr(1 to LENGTH-1));
end if;
end process shift;
end generate negedge_left;
par_out <= my_sr(1 to LENGTH) after 2 ns;
end sr_arch;
-----------------------------------------------------------------------------
-- Shift register for spi_interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! General parallell input, serial output shift register
--! The shift register length is generic, from 2 and up. It can trigger on
--! positive or negative edges, and the shift direction can be choosen as well.
entity sr_piso is
generic (
LENGTH : positive := 8; --! Shift register length
EDGE : natural := 1; --! Active edge; 1=positive, 0=negative
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
clk : in std_logic; --! Clock input
load : in std_logic; --! Load on next clock
par_in : in std_logic_vector(1 to LENGTH); --! Parallel input data
ser_in : in std_logic; --! Serial input data
ser_out : out std_logic); --! Serial output data
end sr_piso;
architecture sr_arch of sr_piso is
signal my_sr : std_logic_vector(1 to LENGTH);
begin -- sr_arch
shift_left : if DIR = 1 generate
ser_out <= my_sr(1) after 2 ns;
end generate shift_left;
shift_right : if DIR /= 1 generate
ser_out <= my_sr(LENGTH) after 2 ns;
end generate shift_right;
posedge_left : if (EDGE = 1) and (DIR = 1) generate
shift : process(clk)
begin
if clk'event and clk = '1' then -- Positive clock edge
if load = '1' then
my_sr <= par_in;
else
my_sr(1 to (LENGTH-1)) <= my_sr(2 to LENGTH);
my_sr(LENGTH) <= ser_in;
end if;
end if;
end process shift;
end generate posedge_left;
posedge_right : if (EDGE = 1) and (DIR /= 1) generate
shift : process(clk)
begin
if clk'event and clk = '1' then -- Positive clock edge
if load = '1' then
my_sr <= par_in;
else
my_sr(2 to LENGTH) <= my_sr(1 to LENGTH-1);
my_sr(1) <= ser_in;
end if;
end if;
end process shift;
end generate posedge_right;
negedge_left : if (EDGE /= 1) and (DIR = 1) generate
shift : process(clk)
begin
if clk'event and clk = '0' then -- Negative clock edge
if load = '1' then
my_sr <= par_in;
else
my_sr(1 to (LENGTH-1)) <= my_sr(2 to LENGTH);
my_sr(LENGTH) <= ser_in;
end if;
end if;
end process shift;
end generate negedge_left;
negedge_right : if (EDGE /= 1) and (DIR /= 1) generate
shift : process(clk)
begin
if clk'event and clk = '0' then -- Negative clock edge
if load = '1' then
my_sr <= par_in;
else
my_sr(2 to LENGTH) <= my_sr(1 to LENGTH-1);
my_sr(1) <= ser_in;
end if;
end if;
end process shift;
end generate negedge_right;
end sr_arch;
-----------------------------------------------------------------------------
-- Synchronously clocked shift register for spi_interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Synchronously clocked parallell input, serial output shift register
--! The shift register length is generic, from 2 and up.
--! The shift direction can be choosen.
entity sr_piso_s is
generic (
LENGTH : positive := 8; --! Shift register length
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
fastclk : in std_logic; --! Synchronous clock
clk_en : in std_logic; --! Clock enable input
load_en : in std_logic; --! Load enable input
par_in : in std_logic_vector(1 to LENGTH); --! Parallel input data
ser_in : in std_logic; --! Serial input data
ser_out : out std_logic); --! Serial output data
end sr_piso_s;
architecture ar_piso_s_arch of sr_piso_s is
signal my_sr : std_logic_vector(1 to LENGTH);
begin -- ar_piso_s_arch
shift_left_out : if DIR = 1 generate
ser_out <= my_sr(1) after 2 ns;
end generate shift_left_out;
shift_right_out : if DIR /= 1 generate
ser_out <= my_sr(LENGTH) after 2 ns;
end generate shift_right_out;
shift_left : if (DIR = 1) generate
shift : process(fastclk)
begin
if rising_edge(fastclk) then -- Positive clock edge
if load_en = '1' then
my_sr <= par_in;
elsif clk_en = '1' then
my_sr(1 to (LENGTH-1)) <= my_sr(2 to LENGTH);
my_sr(LENGTH) <= ser_in;
end if;
end if;
end process shift;
end generate shift_left;
shift_right : if (DIR /= 1) generate
shift : process(fastclk)
begin
if rising_edge(fastclk) then -- Positive clock edge
if load_en = '1' then
my_sr <= par_in;
elsif clk_en = '1' then
my_sr(2 to LENGTH) <= my_sr(1 to LENGTH-1);
my_sr(1) <= ser_in;
end if;
end if;
end process shift;
end generate shift_right;
end ar_piso_s_arch;
-----------------------------------------------------------------------------
-- The adc_interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity interface_ads1271 is
port (
fastclk : in std_logic; -- Fast clock
adclk : in std_logic; -- A/D converter clock
resync : in std_logic; -- Clock change; resync
ser_data : in std_logic; -- Serial data in
n_drdy : in std_logic; -- Data is ready, active low
data_out : out std_logic_vector(23 downto 0); -- Parallell data out
nsync : out std_logic := '1'; -- Synchronize (restart) A/D conv.
busy : out std_logic; -- Busy reading serial data
g_sclk : out std_logic); -- Gated SPI clock, FOR SIMULATION ONLY
end interface_ads1271;
architecture interface_ads1271_arch of interface_ads1271 is
type state_type is (idle, counting, freeze);
signal state : state_type := idle; -- Controlling state machine
signal unlatch_data : std_logic_vector(23 downto 0) := (others => '0'); -- From shift register
signal bitcounter : unsigned(4 downto 0) := to_unsigned(0, 5); -- Range 0..31
signal g_sclk_enable : std_logic := '0';
type rsync_sm_type is (rs_idle, rs_clo1, rs_chi, rs_clo2);
signal rsync_sm : rsync_sm_type := rs_idle;
component sr_sipo is
generic (
LENGTH : positive; --! Shift register length
EDGE : natural; --! Active edge; 1=positive, 0=negative
DIR : natural); --! Direction; 1=left, 0=right
port (
clk : in std_logic; --! Clock input
ser_in : in std_logic; --! Serial input data
par_out : out std_logic_vector(1 to LENGTH)); --! Parallel output data
end component;
begin -- interface_ads1271_arch
sr1 : sr_sipo generic map (
LENGTH => 24,
EDGE => 1,
DIR => 1)
port map (
clk => adclk,
ser_in => ser_data,
par_out => unlatch_data);
-- Static interconnects
g_sclk <= g_sclk_enable and adclk;
-- purpose: Freeze output data
-- type : sequential
-- inputs : adclk, n_drdy
freeze_proc : process (adclk)
begin -- process freeze_proc
if rising_edge(adclk) then -- rising clock edge
case state is
when idle => if n_drdy = '0' then
busy <= '1';
state <= counting;
bitcounter <= to_unsigned(23, 5);
g_sclk_enable <= '1';
else
busy <= '0';
end if;
when counting => busy <= '1';
if bitcounter > 0 then
bitcounter <= bitcounter - 1;
else
state <= freeze;
data_out <= unlatch_data;
g_sclk_enable <= '0';
end if;
when freeze => busy <= '0';
if n_drdy = '1' then
state <= idle;
end if;
when others => state <= idle; busy <= '0';
end case;
end if;
end process freeze_proc;
-- purpose: Handle resyncronization of A/D converters
-- Keep nsync low for at least one adclk cycle
-- type : sequential
-- inputs : fastclk, adclk, resync
-- outputs: nsync
resync_proc : process (fastclk)
begin -- process resync_proc
if rising_edge(fastclk) then -- rising clock edge
nsync <= '0';
case rsync_sm is
when rs_idle => if resync = '1' then
rsync_sm <= rs_clo1;
else
nsync <= '1';
end if;
when rs_clo1 => if adclk = '0' then
rsync_sm <= rs_chi;
end if;
when rs_chi => if adclk = '1' then
rsync_sm <= rs_clo2;
end if;
when rs_clo2 => if adclk = '0' then
rsync_sm <= rs_idle;
end if;
when others => rsync_sm <= rs_idle;
nsync <= '1';
end case;
end if;
end process resync_proc;
end interface_ads1271_arch;
-----------------------------------------------------------------------------
-- The priority_resolver2
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_resolver2 is
port (
inp : in std_logic_vector(11 downto 0); -- Active low inputs
prio : out unsigned(3 downto 0); -- Output highest signal
active : out std_logic); -- High when any input is active
end priority_resolver2;
architecture priority_resolver2_arch of priority_resolver2 is
begin -- priority_resolver2_arch
-- Any input active ???
active <= inp(0) or inp(1) or inp(2) or inp(3) or inp(4) or inp(5) or
inp(6) or inp(7) or inp(8) or inp(9) or inp(10) or inp(11) after 1 ns;
-- purpose: Priority resolver
-- type : combinational
-- inputs : inp
-- outputs: prio, active
mainloop : process (inp)
begin -- process mainloop
if inp(11) = '1' then
prio <= to_unsigned(11, 4) after 1 ns;
elsif inp(10) = '1' then
prio <= to_unsigned(10, 4) after 1 ns;
elsif inp(9) = '1' then
prio <= to_unsigned(9, 4) after 1 ns;
elsif inp(8) = '1' then
prio <= to_unsigned(8, 4) after 1 ns;
elsif inp(7) = '1' then
prio <= to_unsigned(7, 4) after 1 ns;
elsif inp(6) = '1' then
prio <= to_unsigned(6, 4) after 1 ns;
elsif inp(5) = '1' then
prio <= to_unsigned(5, 4) after 1 ns;
elsif inp(4) = '1' then
prio <= to_unsigned(4, 4) after 1 ns;
elsif inp(3) = '1' then
prio <= to_unsigned(3, 4) after 1 ns;
elsif inp(2) = '1' then
prio <= to_unsigned(2, 4) after 1 ns;
elsif inp(1) = '1' then
prio <= to_unsigned(1, 4) after 1 ns;
else
prio <= to_unsigned(0, 4) after 1 ns;
end if;
end process mainloop;
end priority_resolver2_arch;
-----------------------------------------------------------------------------
-- The active_input state machine
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity active_input is
port (
fastclk : in std_logic; -- Main clock
enable : in std_logic; -- Enable signal
busy_n : in std_logic; -- Busy input signal, active low
clear : in std_logic; -- Clear the corresponding flip-flop
active_out : out std_logic); -- Active output
end active_input;
architecture active_input_arch of active_input is
type input_state_type is (i_idle, i_active, i_decay);
signal i_state : input_state_type := i_idle;
signal temp_active_out : std_logic := '0'; -- Temporary signal'
begin -- active_input_arch
-- Static delayed connex
active_out <= temp_active_out after 1 ns;
-- purpose: Input state machine
-- type : sequential
-- inputs : fastclk, fastclk, busy_n, clear
-- outputs: temp_active_out
input_active : process (fastclk)
begin -- process input_active
if rising_edge(fastclk) then -- rising clock edge
temp_active_out <= '0';
case i_state is
when i_idle => if (busy_n = '0') and (enable = '1') then
temp_active_out <= '1';
i_state <= i_active;
end if;
when i_active => if clear = '0' then
temp_active_out <= '1';
else
i_state <= i_decay;
end if;
when i_decay => if busy_n = '1' then
i_state <= i_idle;
end if;
when others => i_state <= i_idle;
end case;
end if;
end process input_active;
end active_input_arch;
-----------------------------------------------------------------------------
-- The one_of_n_encoder
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity one_of_n_encoder is
port (
number : in unsigned(3 downto 0);
enable : in std_logic;
single_out : out std_logic_vector(11 downto 0)); -- Only a single wire is active at a time
end one_of_n_encoder;
architecture one_of_n_encoder_arch of one_of_n_encoder is
type out_table_type is array (0 to 15) of std_logic_vector(11 downto 0);
constant out_table : out_table_type :=
("000000000001",
"000000000010",
"000000000100",
"000000001000",
"000000010000",
"000000100000",
"000001000000",
"000010000000",
"000100000000",
"001000000000",
"010000000000",
"100000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000");
begin -- one_of_n_encoder_arch
-- purpose: Translate unsigned number into a signle output
-- type : sequential
-- inputs : number, number, enable
-- outputs: single_out
xlate : process (number, enable)
begin -- process xlate
if enable = '1' then
single_out <= out_table(to_integer(number)) after 1 ns;
else
single_out <= "000000000000" after 1 ns;
end if;
end process xlate;
end one_of_n_encoder_arch;
-----------------------------------------------------------------------------
-- The master_state_machine
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.polyamplib.all;
entity master_state_machine is
port (
fastclk : in std_logic := '0'; -- Main clock
enable_lo8 : in std_logic; -- Enable the 8 low inputs
busy_n_vec : in std_logic_vector(11 downto 0); -- Busy inputs
id_code : inout unsigned(3 downto 0); -- Id code output
fifo_write : out std_logic); -- Save to fifo
end master_state_machine;
architecture master_state_machine_arch of master_state_machine is
signal active_data : std_logic_vector(11 downto 0);
signal clear_vec : std_logic_vector(11 downto 0);
signal any_active : std_logic := '0'; -- Is any input active ???
signal clear_enable : std_logic := '0'; -- Clear the current active input flip-flop
signal temp_clear_en : std_logic := '0';
signal priority : unsigned(3 downto 0);
type master_state_type is (m_idle, m_latch, m_clear, m_decay);
signal m_state : master_state_type := m_idle;
begin -- master_state_machine_arch
-- The first 8 are controlled by the enable_lo8 signal
gen1 : for i in 0 to 7 generate
inp_sm : active_input port map (
fastclk => fastclk,
enable => enable_lo8,
busy_n => busy_n_vec(i),
clear => clear_vec(i),
active_out => active_data(i));
end generate gen1;
-- The other inputs are always enabled
gen2 : for i in 8 to 11 generate
inp_sm : active_input port map (
fastclk => fastclk,
enable => '1',
busy_n => busy_n_vec(i),
clear => clear_vec(i),
active_out => active_data(i));
end generate gen2;
resolve : priority_resolver2 port map (
inp => active_data,
prio => priority,
active => any_active);
encode : one_of_n_encoder port map (
number => id_code,
enable => clear_enable,
single_out => clear_vec);
clear_enable <= temp_clear_en after 1 ns; -- After some delay
fifo_write <= clear_enable; -- Same-same
-- purpose: Master state machine
-- type : sequential
-- inputs : fastclk, s0..s11,c0..c11
-- outputs: fifo_write, data_id
master_loop : process (fastclk)
begin -- process master_loop
if rising_edge(fastclk) then -- rising clock edge
temp_clear_en <= '0';
case m_state is
when m_idle => if any_active = '1' then
id_code <= priority after 1 ns;
m_state <= m_latch;
end if;
when m_latch =>
temp_clear_en <= '1';
m_state <= m_clear;
when m_clear =>
m_state <= m_decay;
when m_decay =>
if any_active = '1' then
id_code <= priority after 1 ns;
m_state <= m_latch;
else
m_state <= m_idle;
end if;
when others => m_state <= m_idle;
end case;
end if;
end process master_loop;
end master_state_machine_arch;
-----------------------------------------------------------------------------
-- The fifo_memory
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.polyamplib.all;
entity fifo_memory is
generic (
fifo_size : natural := 100);
port (
clock : in std_logic;
sclr : in std_logic;
datain : in std_logic_vector(31 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
dataout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
meter : out unsigned(7 downto 0));
end fifo_memory;
architecture fifo_memory_arch of fifo_memory is
begin -- fifo_memory_arch
-- purpose: Fifo memory simulator
-- type : sequential
-- inputs : clock, datain, wrreq, rdreq, clock
-- outputs: dataout, full, empty
fifo_mem : process (clock)
subtype word is std_logic_vector(31 downto 0);
type memory_area is array(0 to fifo_size) of word;
variable fifo : memory_area; -- The fifo memory area
variable head_ix : natural := 0; -- Write data to this address
variable tail_ix : natural := 0; -- Read data from this address
variable test_ix : natural := 0; -- Used for test of overflow/underflow
begin -- process fifo
if rising_edge(clock) then -- rising clock edge
-- Synchronous clear
if sclr = '1' then
head_ix := 0;
tail_ix := 0;
elsif wrreq = '1' then -- Fifo write op's
test_ix := head_ix + 1;
if test_ix > fifo_size then
test_ix := 0;
end if;
-- Writing to full fifo discards the last value
if test_ix /= tail_ix then -- NOT full
fifo(head_ix) := datain; -- Write data
head_ix := test_ix; -- And adjust the pointer
end if;
end if;
-- Reading empty fifo returns the last value
if (rdreq = '1') and (head_ix /= tail_ix) then
dataout <= fifo(tail_ix) after 1 ns;
tail_ix := tail_ix + 1;
if tail_ix > fifo_size then
tail_ix := 0;
end if;
end if;
-- Fifo empty signal
if head_ix = tail_ix then
empty <= '1' after 1 ns;
else
empty <= '0' after 1 ns;
end if;
-- Fifo full signal
if (tail_ix = (head_ix+1)) or ((tail_ix = 0) and (head_ix = fifo_size)) then
full <= '1' after 1 ns;
else
full <= '0' after 1 ns;
end if;
-- Fifo fill meter operations
if head_ix >= tail_ix then
meter <= to_unsigned(head_ix - tail_ix, 8);
else
meter <= to_unsigned(fifo_size + 1 + head_ix - tail_ix, 8);
end if;
end if;
end process fifo_mem;
end fifo_memory_arch;
-----------------------------------------------------------------------------
-- The fifo_ft_memory
-----------------------------------------------------------------------------
-- Fallthrough fifo memory model
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.polyamplib.all;
entity fifo_ft_memory is
generic (
fifo_size : natural := 100);
port (
clock : in std_logic;
sclr : in std_logic;
datain : in std_logic_vector(31 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
dataout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
meter : out unsigned(7 downto 0));
end fifo_ft_memory;
architecture fifo_ft_memory_arch of fifo_ft_memory is
begin -- fifo_ft_memory_arch
-- purpose: Fifo memory simulator
-- type : sequential
-- inputs : clock, datain, wrreq, rdreq, clock
-- outputs: dataout, full, empty
fifo_mem : process (clock)
subtype word is std_logic_vector(31 downto 0);
type memory_area is array(0 to fifo_size) of word;
variable fifo : memory_area; -- The fifo memory area
variable head_ix : natural := 0; -- Write data to this address
variable tail_ix : natural := 0; -- Read data from this address
variable test_ix : natural := 0; -- Used for test of overflow/underflow
begin -- process fifo
if rising_edge(clock) then -- rising clock edge
-- Synchronous clear
if sclr = '1' then
head_ix := 0;
tail_ix := 0;
else
-- Write to fifo
if wrreq = '1' then -- Fifo write op's
test_ix := head_ix + 1;
if test_ix > fifo_size then
test_ix := 0;
end if;
-- Fifo is empty
if head_ix = tail_ix then
dataout <= datain; -- Let data fall-through
fifo(head_ix) := datain; -- Write data
head_ix := test_ix; -- And adjust the pointer
elsif test_ix /= tail_ix then -- NOT full
fifo(head_ix) := datain; -- Write data
head_ix := test_ix; -- And adjust the pointer
end if;
end if;
-- Reading empty fifo returns the last value
if (rdreq = '1') and (head_ix /= tail_ix) then
tail_ix := tail_ix + 1;
if tail_ix > fifo_size then
tail_ix := 0;
end if;
if tail_ix /= head_ix then
dataout <= fifo(tail_ix) after 1 ns;
end if;
end if;
end if;
-- Fifo empty signal
if head_ix = tail_ix then
empty <= '1' after 1 ns;
else
empty <= '0' after 1 ns;
end if;
-- Fifo full signal
if (tail_ix = (head_ix+1)) or ((tail_ix = 0) and (head_ix = fifo_size)) then
full <= '1' after 1 ns;
else
full <= '0' after 1 ns;
end if;
-- Fifo fill meter operations
if head_ix >= tail_ix then
meter <= to_unsigned(head_ix - tail_ix, 8);
else
meter <= to_unsigned(fifo_size + 1 + head_ix - tail_ix, 8);
end if;
end if;
end process fifo_mem;
end fifo_ft_memory_arch;
-----------------------------------------------------------------------------
-- VHDL model of A/D-converter Texas ADS1271
-----------------------------------------------------------------------------
-- NOTE! This is a model for simulation only. It is not
-- coded to be synthezised.
-- SPI interface format, 512 clock cycles/conversion
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ads1271_model is
port (
analog_in : in signed(23 downto 0); -- Analog input signal
clk : in std_logic; -- Conversion clock
sclk : in std_logic; -- SPI clock
n_sync : in std_logic; -- Input sync signal, active low
din : in std_logic; -- Serial data in
dout : out std_logic; -- Serial data out
n_drdy : out std_logic := '1'); -- Data ready, active low
end ads1271_model;
architecture ads1271_model_arch of ads1271_model is
signal analog_data : signed(23 downto 0) := to_signed(0, 24);
shared variable conv_timer : integer := 2; -- Data conversion rate
shared variable sdata_counter : integer := -1; -- Controls dout bits
signal din_mem : std_logic := '0'; -- 'din' memory
signal drdy_ff : std_logic;
signal clk_del : std_logic := '0'; -- Delayed clk signal
signal sclk_del : std_logic := '0'; -- Delayed sclk signal
signal ct_is_one : std_logic; -- Locally generated sync
signal ct_is_zero : std_logic; -- Locally generated sync
begin -- ads1271_model_arch
n_drdy <= drdy_ff or ct_is_one after 8 ns;
sclk_del <= sclk after 2 ns;
clk_del <= clk after 1 ns;
-- purpose: Data conversion circuitry
-- type : sequential
-- inputs : clk_del
-- outputs: dout, ct_is_one
convert : process (clk_del)
begin -- process convert
if falling_edge(clk_del) then -- falling clock edge
ct_is_one <= '0';
ct_is_zero <= '0';
if n_sync = '0' then
conv_timer := (128*512); -- Reloading the FIR takes a while
ct_is_one <= '1';
else
conv_timer := conv_timer - 1;
if conv_timer <= 0 then -- Conversion rate number
conv_timer := 512;
sdata_counter := 23; -- MSBit comes first
ct_is_zero <= '1';
end if; -- conv_timer <= 0
if conv_timer = 1 then
ct_is_one <= '1';
end if; -- conv_timer = 1
if conv_timer = 512 then
analog_data <= analog_in; -- Data sampling, data av. after 512 clock's
end if; -- conv_timer = 512
end if; -- n_sync = '0'
end if; -- falling_edge(clk_del)
end process convert;
-- purpose: Serial data interface control
-- type : sequential
-- inputs : sclk_del
-- outputs: dout
dataout : process (sclk_del)
begin -- process dataout
if sclk_del'event then
if sclk_del = '0' then -- falling clock edge
if sdata_counter >= 0 then
dout <= 'X' after 5 ns;
dout <= analog_data(sdata_counter) after 12 ns;
sdata_counter := sdata_counter - 1;
else
dout <= 'X' after 5 ns;
dout <= din_mem after 12 ns;
end if;
else
-- rising clock edge samples din
din_mem <= din;
end if;
end if;
end process dataout;
-- purpose: Controls the drdy_ff signal
-- type : sequential
-- inputs : sclk_del, ct_is_zero
-- outputs: drdy_ff
readyctl : process (sclk_del, ct_is_zero)
begin -- process readyctl
if ct_is_zero = '1' then -- asynchronous reset (active high)
drdy_ff <= '0';
elsif falling_edge(sclk_del) then -- falling clock edge
drdy_ff <= '1';
end if;
end process readyctl;
end ads1271_model_arch;
-----------------------------------------------------------------------------
-- SPI slave with secondary spi master port
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.polyamplib.all;
entity spi_slave is
port (
-- Main controls
fastclk : in std_logic;
spi_tx : in std_logic_vector(31 downto 0); -- Data to be sent
spi_rx : out std_logic_vector(31 downto 0); -- Data to be received
spi_op : out std_logic; -- Read/Write status/data/command
-- Slave port, connected to CPU
mosi : in std_logic;
miso : out std_logic;
sck : in std_logic; -- SPI clock
en_adc : in std_logic; -- Active low, enable ADC
en_incl : in std_logic; -- Active low, enable inclinometer
-- Master port, connected to inclinometer
incl_miso : in std_logic;
incl_mosi : out std_logic;
incl_sck : out std_logic;
incl_ena : out std_logic); -- Active low, enable inclinometer
end spi_slave;
architecture spi_slave_arch of spi_slave is
type state_type is (idle, load, shift, relax);
signal state : state_type := idle; -- Controlling state machine
signal enable_inclinometer : std_logic := '0';
signal enable_adc : std_logic := '0';
signal adc_miso : std_logic;
signal adc_load : std_logic := '0';
-- signal g_miso : std_logic register := '0'; -- guarded miso signal
signal adc_sck : std_logic;
signal tx_sck : std_logic;
signal delayed_adc_sck : std_logic; -- Delayed, for edge detection
begin -- spi_slave_arch
-- Transmit shift register
tx_sr : sr_piso_s generic map (
LENGTH => 32,
DIR => 1) -- Shift left => MSB first
port map (
fastclk => fastclk,
clk_en => tx_sck,
load_en => adc_load,
par_in => spi_tx,
ser_in => '0',
ser_out => adc_miso);
-- Receive shift register
rx_sr : sr_sipo generic map (
LENGTH => 32,
EDGE => 1, -- Positive edge
DIR => 1) -- Shift left => MSB first
port map (
clk => adc_sck,
ser_in => mosi,
par_out => spi_rx);
-- Passthru signals
incl_sck <= sck after 1 ns;
incl_mosi <= mosi after 1 ns;
incl_ena <= not enable_inclinometer after 1 ns; -- Active low output
-- Enable and clock
enable_inclinometer <= not en_incl and en_adc after 1 ns;
enable_adc <= not en_adc after 1 ns;
adc_sck <= sck or en_adc after 1 ns; -- Clock is driven high at inactive state
tx_sck <= (not adc_sck) and delayed_adc_sck after 1 ns; -- sck negative edge trigger
-- Output data
-- miso <= g_miso;
-- purpose: ADC controls miso
-- talkto_adc : block (enable_adc = '1')
-- begin -- block talkto_adc
-- g_miso <= guarded adc_miso;
-- end block talkto_adc;
-- purpose: Inclinometer controls miso
-- talkto_incl : block (enable_inclinometer = '1')
-- begin -- block talkto_incl
-- g_miso <= guarded incl_miso;
-- end block talkto_incl;
-- Instead of the guarded assignments above
miso <= adc_miso when enable_inclinometer = '0' else incl_miso;
-- purpose: SPI slave controller state machine
-- type : sequential
-- inputs : fastclk, enable_adc
-- outputs: adc_load
input_active : process (fastclk)
begin -- process input_active
if rising_edge(fastclk) then -- rising clock edge
delayed_adc_sck <= adc_sck;
adc_load <= '1' after 1 ns;
spi_op <= '0' after 1 ns;
case state is
when idle => if enable_adc = '1' then
state <= load;
end if;
when load => state <= shift;
when shift => adc_load <= '0' after 1 ns;
if enable_adc = '0' then
state <= relax;
spi_op <= '1' after 1 ns;
end if;
when relax => state <= idle;
when others => state <= idle;
end case;
end if;
end process input_active;
end spi_slave_arch;
-----------------------------------------------------------------------------
-- SPI slave with burst capabilities and with secondary spi master port
-- NOTE! Spi mode 2
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.polyamplib.all;
entity spi_slave_burst is
port (
-- Main controls
fastclk : in std_logic;
spi_tx : in std_logic_vector(31 downto 0); -- Data to be sent
spi_rx : out std_logic_vector(31 downto 0); -- Data to be received
exec_cmd : out std_logic; -- Write command/data
fifo_read : out std_logic; -- Read status/data
-- Slave port, connected to CPU
mosi : in std_logic;
miso : out std_logic;
sck : in std_logic; -- SPI clock
en_adc : in std_logic; -- Active low, enable ADC
en_incl : in std_logic; -- Active low, enable inclinometer
-- Master port, connected to inclinometer
incl_miso : in std_logic;
incl_mosi : out std_logic;
incl_sck : out std_logic;
incl_ena : out std_logic); -- Active low, enable inclinometer
end spi_slave_burst;
architecture spi_slave_burst_arch of spi_slave_burst is
-- type state_type is (idle, load, shift, relax);
-- signal state : state_type := idle; -- Controlling state machine
signal bitcounter : unsigned(4 downto 0) := to_unsigned(0, 5); -- Range 0..31
signal enable_inclinometer : std_logic := '0';
signal enable_adc : std_logic := '0';
signal adc_miso : std_logic;
signal clk_tx_sr : std_logic := '0';
signal load_tx_sr : std_logic := '0';
signal sck_r1 : std_logic; -- Delayed, for edge detection
signal sck_r2 : std_logic; -- Delayed, for edge detection
signal sck_negedge : std_logic; -- Negative edge
signal sck_posedge : std_logic; -- Positive edge
signal enable_adc_r1 : std_logic; -- Delayed, for edge detection
signal enable_adc_r2 : std_logic; -- Delayed, for edge detection
signal enable_adc_negedge : std_logic; -- Negative edge
signal bitcounter_zero : std_logic;
signal bitcounter_one : std_logic;
signal exec_ff : std_logic := '0'; -- Enable the execute signal
signal load_ff : std_logic := '0'; -- Enable the load signal
begin -- spi_slave_burst_arch
-- Transmit shift register
tx_sr : sr_piso_s generic map (
LENGTH => 32,
DIR => 1) -- Shift left => MSB first
port map (
fastclk => fastclk,
clk_en => clk_tx_sr,
load_en => load_tx_sr,
par_in => spi_tx,
ser_in => '0',
ser_out => adc_miso);
-- Receive shift register
rx_sr : sr_sipo generic map (
LENGTH => 32,
EDGE => 1, -- Positive edge
DIR => 1) -- Shift left => MSB first
port map (
clk => sck_negedge,
ser_in => mosi,
par_out => spi_rx);
-- Passthru signals
incl_sck <= sck after 1 ns;
incl_mosi <= mosi after 1 ns;
incl_ena <= not enable_inclinometer after 1 ns; -- Active low output
-- Enable and clock
enable_inclinometer <= not en_incl and en_adc after 1 ns;
enable_adc <= not en_adc after 1 ns;
sck_posedge <= sck_r1 and (not sck_r2) after 1 ns; -- sck Positive edge
sck_negedge <= sck_r2 and (not sck_r1) after 1 ns; -- sck Negative edge
enable_adc_negedge <= enable_adc_r1 and (not enable_adc_r2) after 1 ns;
fifo_read <= sck_posedge and bitcounter_one after 1 ns;
load_tx_sr <= enable_adc_negedge or
(sck_negedge and bitcounter_zero and (not load_ff)) after 1 ns;
exec_cmd <= bitcounter_zero and exec_ff and sck_posedge after 1 ns;
clk_tx_sr <= sck_posedge or enable_adc_negedge after 1 ns;
-- Instead of the guarded assignments above
miso <= adc_miso when enable_inclinometer = '0' else incl_miso after 1 ns;
-- purpose: SPI slave controller state machine
-- type : sequential
-- inputs : fastclk, sck, enable_adc, bitcounter, load_tx_sr
-- outputs: sck_r1, sck_r2, enable_adc_r1, enable_adc_r2, bitcounter
input_active : process (fastclk)
begin -- process input_active
if rising_edge(fastclk) then -- rising clock edge
sck_r2 <= sck_r1 after 1 ns;
sck_r1 <= sck after 1 ns;
enable_adc_r2 <= enable_adc_r1 after 1 ns;
enable_adc_r1 <= enable_adc after 1 ns;
if enable_adc_negedge = '1' then
bitcounter <= to_unsigned(0, 5) after 1 ns;
else if sck_negedge = '1' then
bitcounter <= bitcounter + 1 after 1 ns;
end if;
end if;
if bitcounter = 0 then
bitcounter_zero <= '1' after 1 ns;
else
bitcounter_zero <= '0' after 1 ns;
end if;
if bitcounter = 1 then
bitcounter_one <= '1' after 1 ns;
else
bitcounter_one <= '0' after 1 ns;
end if;
if enable_adc = '0' then
exec_ff <= '0' after 1 ns;
elsif bitcounter = 2 then
exec_ff <= '1' after 1 ns;
end if;
if load_tx_sr = '1' then
load_ff <= '1' after 1 ns;
elsif bitcounter = 2 then
load_ff <= '0' after 1 ns;
end if;
end if;
end process input_active;
end spi_slave_burst_arch;
----------------------------------------------------------------------
-- Command decoder function
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity command_decoder is
port (
addr_data : in std_logic_vector(31 downto 0); -- Input address/data
decode : in std_logic; -- Single cycle decode pulse
fastclk : in std_logic; -- Master clock (not used for now)
sel_nulcmd : out std_logic; -- NULL command (no operation)
sel_adclk0 : out std_logic; -- Select sampling clock, ad0.
sel_adclk1 : out std_logic; -- Select sampling clock, ad1.
sel_adclk2 : out std_logic; -- Select sampling clock, ad2.
sel_adclk3 : out std_logic; -- Select sampling clock, ad3.
sel_adclk4 : out std_logic; -- Select sampling clock, ad4.
sel_adclk5 : out std_logic; -- Select sampling clock, ad5.
sel_adclk6 : out std_logic; -- Select sampling clock, ad6.
sel_adclk7 : out std_logic; -- Select sampling clock, ad7.
resync_adc : out std_logic; -- Resynchronize all ADC's
write_ctrl : out std_logic; -- Write to control-signal register
start_adcs : out std_logic; -- Start AD-conversion
stop_adcs : out std_logic); -- Stop AD-conversion
end command_decoder;
architecture command_decoder_arch of command_decoder is
begin -- command_decoder_arch
sel_nulcmd <= '1' when (addr_data(27 downto 24) = "0000") and decode = '1' else '0';
sel_adclk0 <= '1' when (addr_data(27 downto 24) = "0001") and decode = '1' else '0';
sel_adclk1 <= '1' when (addr_data(27 downto 24) = "0010") and decode = '1' else '0';
sel_adclk2 <= '1' when (addr_data(27 downto 24) = "0011") and decode = '1' else '0';
sel_adclk3 <= '1' when (addr_data(27 downto 24) = "0100") and decode = '1' else '0';
sel_adclk4 <= '1' when (addr_data(27 downto 24) = "0101") and decode = '1' else '0';
sel_adclk5 <= '1' when (addr_data(27 downto 24) = "0110") and decode = '1' else '0';
sel_adclk6 <= '1' when (addr_data(27 downto 24) = "0111") and decode = '1' else '0';
sel_adclk7 <= '1' when (addr_data(27 downto 24) = "1000") and decode = '1' else '0';
resync_adc <= '1' when (addr_data(27 downto 24) = "1001") and decode = '1' else '0';
write_ctrl <= '1' when (addr_data(27 downto 24) = "1010") and decode = '1' else '0';
start_adcs <= '1' when (addr_data(27 downto 24) = "1011") and decode = '1' else '0';
stop_adcs <= '1' when (addr_data(27 downto 24) = "1100") and decode = '1' else '0';
end command_decoder_arch;
----------------------------------------------------------------------
-- ADC clock multiplexer function
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clockmux is
port (
clk24M : in std_logic; -- Input clocks, 24 576 000
clk4M : in std_logic; -- 4 096 000
clk2M : in std_logic; -- 2 048 000
clk1M : in std_logic; -- 1 024 000
clk512k : in std_logic; -- 512 000
clk256k : in std_logic; -- 256 000
clk128k : in std_logic; -- 128 000
sel : in unsigned(2 downto 0); -- Mux select input
clkout : out std_logic); -- Output clock
end clockmux;
architecture clockmux_arch of clockmux is
begin -- clockmux_arch
with sel select
clkout <=
clk128k when "000",
clk256k when "001",
clk512k when "010",
clk1M when "011",
clk2M when "100",
clk4M when "101",
clk24M when "110",
clk24M when others;
end clockmux_arch;
-------------------------------------------------------------------------------
-- SPI master for simulation and test (no synth.)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
port (
-- Hardware ports
miso : in std_logic;
mosi : out std_logic;
sck : inout std_logic := '0';
en_adval : out std_logic := '1';
en_incl : out std_logic := '1';
-- Simulation ports
data_to_spi : in std_logic_vector(31 downto 0);
data_from_spi : out std_logic_vector(31 downto 0);
start : in std_logic;
busy : out std_logic := '0';
running : in std_logic);
end spi_master;
architecture spi_master_arch of spi_master is
type state_type is (idle, load, shift);
signal state : state_type := idle;
signal start_mem : std_logic := '0';
begin -- spi_master_arch
-----------------------------------------------------------------------------
-- Assume that data_to_spi is defined before this process is triggered
spi_rxtx : process (sck)
variable bit_index : integer := 0;
begin -- process spi_rxtx
if sck'event then
if sck = '1' then -- rising clock edge
start_mem <= start;
case state is
when idle => if start = '1' and start_mem = '0' then -- Start rising
-- edge
en_adval <= '0' after 15 ns;
busy <= '1' after 2 ns;
state <= load;
bit_index := 31;
end if;
when load => data_from_spi(bit_index) <= miso;
state <= shift;
when shift => bit_index := bit_index - 1;
if bit_index < 0 then
state <= idle;
en_adval <= '1' after 15 ns;
busy <= '0' after 2 ns;
else
data_from_spi(bit_index) <= miso;
end if;
when others => state <= idle;
end case;
end if; -- sck = '1' else ...
if sck = '0' and (state = load or state = shift) then
mosi <= data_to_spi(bit_index) after 1 ns;
end if;
end if; -- sck'event
end process spi_rxtx;
-----------------------------------------------------------------------------
spi_clk : process
begin -- process spi_clk
while running = '1' loop
sck <= not sck;
wait for 50 ns;
end loop;
sck <= not sck;
wait for 50 ns;
sck <= not sck;
wait for 50 ns;
sck <= not sck;
wait for 50 ns;
sck <= not sck;
wait for 50 ns;
wait;
end process spi_clk;
end spi_master_arch;
----------------------------------------------------------------------
-- Synchronization logic
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_logic_2 is
port (
start_adcs : in std_logic; -- Start command
stop_adcs : in std_logic; -- Stop command
reset : in std_logic; -- Active high
hwsync : in std_logic; -- Hardware sync
fastclk : in std_logic; -- Master clock
enable_adcvalues : out std_logic); -- Enable reception of values
end sync_logic_2;
architecture sync_logic_2_arch of sync_logic_2 is
signal del_sync_1 : std_logic; -- 1'st delay
signal del_sync_2 : std_logic; -- 2'nd delay
signal sr_set : std_logic; -- Set input to SR-latch
signal sr : std_logic := '0'; -- sr Q output, entity output
begin -- sync_logic_2_arch
enable_adcvalues <= sr;
sr_set <= (del_sync_1 and (not del_sync_2)) xor start_adcs;
-- purpose: Two D-latches and one SR-latch is controlled
-- type : sequential
-- inputs : fastclk, reset, start_adcs, stop_adcs, hwsync
-- outputs: sr
registered_logic : process (fastclk, reset)
begin -- process registered_logic
if reset = '1' then -- asynchronous reset
del_sync_1 <= '0' after 2 ns;
del_sync_2 <= '0' after 2 ns;
sr <= '0' after 2 ns;
elsif rising_edge(fastclk) then -- rising clock edge
del_sync_1 <= hwsync after 2 ns;
del_sync_2 <= del_sync_1 after 2 ns;
if stop_adcs = '1' then
sr <= '0' after 2 ns;
elsif sr_set = '1' then
sr <= '1' after 2 ns;
end if;
end if;
end process registered_logic;
end sync_logic_2_arch;
|
gpl-2.0
|
481eae3b7f7477fbf41d064448224b79
| 0.522431 | 3.788541 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt-b.vhd
| 4 | 1,763 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tofpt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of to_fp_test is
signal vec : std_ulogic_vector(15 downto 0);
signal r : real;
begin
dut : entity work.to_fp(behavioral)
port map (vec, r);
stimulus : process is
begin
vec <= X"0000"; wait for 10 ns;
vec <= X"8000"; wait for 10 ns;
vec <= X"7FFF"; wait for 10 ns;
vec <= X"4000"; wait for 10 ns;
vec <= X"C000"; wait for 10 ns;
wait;
end process stimulus;
end architecture bench;
|
gpl-2.0
|
bebd4ce52a955e8f38e84915b74dc0e9
| 0.537153 | 4.474619 | false | false | false | false |
mmoraless/ecc_vhdl
|
ecc_add/NewECCADD_163.vhd
| 1 | 6,089 |
------------------------------------------------------------------------
--Nueva implementacion ADD y Double en una misma arquitectura
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity ECC_add_serial_163 is
generic(
-- 163, 233, 277, 283, 409, 571
NUM_BITS : positive := 163
);
port(
xP: in std_logic_vector(NUM_BITS-1 downto 0);
yP: in std_logic_vector(NUM_BITS-1 downto 0);
xQ: in std_logic_vector(NUM_BITS-1 downto 0);
yQ: in std_logic_vector(NUM_BITS-1 downto 0);
---------------------------------------------
clk: in std_logic;
rst: in std_logic;
s0: in std_logic; -- 1 = Suma, 0 = Double
---------------------------------------------
X: out std_logic_vector(NUM_BITS-1 downto 0);
Y: out std_logic_vector(NUM_BITS-1 downto 0);
done: out std_logic
);
end;
------------------------------------------------------
architecture behave of ECC_add_serial_163 is
type CurrentState_type is (END_STATE, CHECK_INPUT, SPEND_CYCLE1, SPEND_CYCLE2,CALC_INV, CALC_MUL);
signal CurrentState : CurrentState_type;
constant cero : std_logic_vector(NUM_BITS-1 downto 0):= (others => '0');
--
signal S1 : std_logic_vector(NUM_BITS-1 downto 0);
signal not_s0 : std_logic;
-- 4 multiplexores
signal L3 : std_logic_vector(NUM_BITS-1 downto 0);
signal SQRin : std_logic_vector(NUM_BITS-1 downto 0);
signal Div1 : std_logic_vector(NUM_BITS-1 downto 0);
signal Div2 : std_logic_vector(NUM_BITS-1 downto 0);
--- interface con el inversor
signal rstInv : std_logic;
signal Division : std_logic_vector(NUM_BITS-1 downto 0);
signal doneInv : std_logic;
--- interface del multiplicador
signal rstMul : std_logic;
signal Multiplication : std_logic_vector(NUM_BITS-1 downto 0);
signal doneMul : std_logic;
--- interface del squarer
signal SQR : std_logic_vector(NUM_BITS-1 downto 0);
---------------------------------------------------------------
begin
---------------------------------------------------------------
-- Componentes
---------------------------------------------------------------
SQUARER_1 : entity squarer_163(behave)
--generic map (D, NUM2_BITS, NUM_BITS)
generic map (NUM_BITS)
port map(SQRin, SQR);
---------------------------------------------------------------
MUL_1: entity serial_multiplier_163(behave)
generic map (NUM_BITS)
port map(S1, SQRin, Multiplication,rstMul,clk,doneMul);
---------------------------------------------------------------
INV_1: entity f2m_divider_163(behave)
generic map (NUM_BITS)
port map(Div1, Div2, clk, rstInv, doneInv, Division);
---------------------------------------------------------------
---------------------------------------------------------------
LUT31: entity lut_3in(behave)
generic map (NUM_BITS)
port map(yQ, s0, yP, Div1);
---------------------------------------------------------------
---------------------------------------------------------------
LUT32: entity lut_3in(behave)
generic map (NUM_BITS)
port map(xQ, s0, xP, Div2);
---------------------------------------------------------------
---------------------------------------------------------------
LUT33: entity lut_3in(behave)
generic map (NUM_BITS)
port map(xP, not_s0, Division,SQRin);
---------------------------------------------------------------
---------------------------------------------------------------
LUT41: entity lut_3inadd(behave)
generic map (NUM_BITS)
port map(SQR, Division, Div2, L3);
---------------------------------------------------------------
-- Operaciones combinacionales (Sumas)
S1 <= L3 xor xP;
not_s0 <= not s0;
---------------------------------------------------------------
ADD_FSM: process (CLK)
Begin
if CLK'event and CLK = '1' then
-- Los datos de entrada deben estar presentes al llegar la señal de reset,
-- Si la señal Rst de entrada es síncrona con un reloj (i.e. es proporcionada
-- por un control en la subida del reloj), los datos a la entrada deben asignarse
-- junto con la señal de Rst o al momento de que Rst regrese a '0'
if Rst = '1' then
CurrentState <= CHECK_INPUT;
Done <= '0';
X <= (others =>'0');
Y <= (others =>'0');
rstInv <= '0';
rstMul <= '0';
else
case CurrentState is
when CHECK_INPUT =>
if (xP = cero) and (yP = cero) and s0 = '1' then -- add
X <= xQ;
Y <= yQ;
Done <= '1';
CurrentState <= END_STATE;
elsif (xQ = cero) and (yQ = cero) and s0 = '1' then -- Add
X <= xP;
Y <= yP;
Done <= '1';
CurrentState <= END_STATE;
elsif (xP = cero) and s0 = '0' then -- Double
Done <= '1';
CurrentState <= END_STATE;
else
rstInv <= '1'; -- calcular la division primero.
CurrentState <= SPEND_CYCLE1;
end if;
when SPEND_CYCLE1 => -- Provoca el pulso RST al modulo de inversion.
rstInv <= '0';
CurrentState <= CALC_INV;
when CALC_INV => -- Una vez que termina de calcular la division,
if doneInv = '1' then -- comienza con la multiplicación.
X <= L3;
rstMul <= '1';
CurrentState <= SPEND_CYCLE2;
end if;
when SPEND_CYCLE2 => -- Provoca el pulso RST en el multiplicador
rstMul <= '0';
CurrentState <= CALC_MUL;
when CALC_MUL => -- Espera que el multiplicador termine
if doneMul = '1' then
Y <= Multiplication xor L3 xor yP;
Done <= '1';
CurrentState <= END_STATE; -- Operación ADD terminada
end if;
when END_STATE =>
CurrentState <= END_STATE;
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
dcab79de4c2dadaf0974f582720642a5
| 0.46855 | 3.784338 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd
| 3 | 4,318 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_10a is
end entity inline_10a;
architecture test of inline_10a is
constant R : real := 10_000.0;
constant R1 : real := 10_000.0;
constant R2 : real := 10_000.0;
-- code from book
nature electrical_bus is
record
strobe: electrical;
databus : electrical_vector(0 to 7);
end record;
-- end code from book
begin
block_1 : block is
-- code from book
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
-- end code from book
begin
-- code from book
bus_v == bus_i * R;
-- end code from book
end block block_1;
block_2 : block is
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
begin
-- code from book
bus_v.strobe == bus_i.strobe * R;
bus_v.databus(0) == bus_i.databus(0) * R;
bus_v.databus(1) == bus_i.databus(1) * R;
-- ...
-- not in book
bus_v.databus(2) == bus_i.databus(2) * R;
bus_v.databus(3) == bus_i.databus(3) * R;
bus_v.databus(4) == bus_i.databus(4) * R;
bus_v.databus(5) == bus_i.databus(5) * R;
bus_v.databus(6) == bus_i.databus(6) * R;
-- end not in book
bus_v.databus(7) == bus_i.databus(7) * R;
-- end code from book
end block block_2;
block_3 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v == i * R;
-- end code from book
end block block_3;
block_4 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v / R == i;
-- end code from book
end block block_4;
block_5 : block is
terminal bus_end1, bus_end2 : electrical_bus;
quantity bus_v across bus_i through bus_end1 to bus_end2;
begin
-- code from book
bus_v.strobe == bus_i.strobe * R;
bus_v.databus(0) == bus_i.databus(0) * R;
-- end code from book
bus_v.databus(1) == bus_i.databus(1) * R;
bus_v.databus(2) == bus_i.databus(2) * R;
bus_v.databus(3) == bus_i.databus(3) * R;
bus_v.databus(4) == bus_i.databus(4) * R;
bus_v.databus(5) == bus_i.databus(5) * R;
bus_v.databus(6) == bus_i.databus(6) * R;
bus_v.databus(7) == bus_i.databus(7) * R;
end block block_5;
block_6 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2; -- illegal
-- end code from book
end block block_6;
block_7 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2 tolerance "current_tolerance";
-- end code from book
end block block_7;
block_8 : block is
terminal p1, m1, p2, m2 : electrical;
quantity v1 across i1 through p1 to m1;
quantity v2 across i2 through p2 to m2;
begin
-- code from book
i1 * R1 == i2 * R2 tolerance i2'tolerance;
-- end code from book
end block block_8;
block_9 : block is
terminal p, m : electrical;
quantity v across i through p to m;
begin
-- code from book
v == i * R tolerance i'tolerance;
-- end code from book
end block block_9;
begin
end architecture test;
|
gpl-2.0
|
10d19254f1ca7308d972bfcc95e71932
| 0.621121 | 3.232036 | false | false | false | false |
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