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stringlengths 137
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stringlengths 32
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float64 0.25
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class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_divider_GNKAPZN5MO.vhd
| 4 | 1,140 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_divider_GNKAPZN5MO is
generic ( Signed : natural := 0;
width : natural := 24;
pipeline : natural := 0);
port(
aclr : in std_logic;
clock : in std_logic;
denom : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
numer : in std_logic_vector((width)-1 downto 0);
quotient : out std_logic_vector((width)-1 downto 0);
remain : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_divider_GNKAPZN5MO is
Begin
-- Divide Operator - Simulink Block "alt_dspbuilder_divider"
Divideri : alt_dspbuilder_dividerAltr generic map (
widthin => 24,
isunsigned => 1,
pipeline => 0)
port map (
numer => numer,
denom => denom,
quotient => quotient,
remain => remain,
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr
);
end architecture;
|
mit
|
b64464f1165ed1d11dacea32f36212d6
| 0.655263 | 3 | false | false | false | false |
straywarrior/MadeCPUin21days
|
ForwardingUnit.vhd
| 1 | 3,218 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 23:26:40 11/19/2015
-- Design Name:
-- Module Name: ForwardingUnit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ForwardingUnit is
Port ( RegOpA : in STD_LOGIC_VECTOR (3 downto 0);
RegOpB : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_MEM: in STD_LOGIC;
RegDest_MEM : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_WB : in STD_LOGIC;
RegDest_WB : STD_LOGIC_VECTOR (3 downto 0);
MemRead_EXE : in STD_LOGIC;
MemRead_WB : in STD_LOGIC;
CReg : in STD_LOGIC;
CRegA : in STD_LOGIC_VECTOR (3 downto 0);
CRegB : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_EXE : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_MEM : in STD_LOGIC_VECTOR (3 downto 0);
RegAValSel : out STD_LOGIC;
RegBValSel : out STD_LOGIC;
RegRAValSel : out STD_LOGIC;
OperandASel : out STD_LOGIC_VECTOR (1 downto 0);
OperandBSel : out STD_LOGIC_VECTOR (1 downto 0);
MemDInSel_EXE : out STD_LOGIC_VECTOR (1 downto 0);
MemDInSel_MEM : out STD_LOGIC
);
end ForwardingUnit;
architecture Behavioral of ForwardingUnit is
begin
OperandASel <=
"01" when RegWE_MEM = '1' and RegDest_MEM /= "1111" and RegDest_MEM = RegOpA else
"10" when RegWE_WB = '1' and RegDest_WB /= "1111" and RegDest_WB = RegOpA and (RegDest_MEM /= RegOpA or MemRead_WB = '1') else
"00";
OperandBSel <=
"01" when RegWE_MEM = '1' and RegDest_MEM /= "1111" and RegDest_MEM = RegOpB else
"10" when RegWE_WB = '1' and RegDest_WB /= "1111" and RegDest_WB = RegOpB and (RegDest_MEM /= RegOpB or MemRead_WB = '1') else
"00";
MemDInSel_EXE <=
"01" when RegWE_MEM = '1' and RegDest_MEM /= "1111" and RegDest_MEM = RegMemDIn_EXE else
"10" when RegWE_WB = '1' and RegDest_WB /= "1111" and RegDest_WB = RegMemDIn_EXE and (RegDest_MEM /= RegMemDIn_EXE or MemRead_WB = '1') else
"00";
MemDInSel_MEM <=
'1' when RegWE_WB = '1' and RegDest_WB /= "1111" and RegDest_WB = RegMemDIn_MEM else
'0';
RegAValSel <=
'1' when RegWE_MEM = '1' and RegDest_MEM /= "1111" and RegDest_MEM = CRegA else
'0';
RegBValSel <=
'1' when RegWE_MEM = '1' and RegDest_MEM /= "1111" and RegDest_MEM = CRegB else
'0';
RegRAValSel <=
'1' when RegWE_MEM = '1' and RegDest_MEM = "1000" else
'0';
end Behavioral;
|
gpl-2.0
|
dda38a1a91d98891717b54a56a62c358
| 0.56619 | 3.781434 | false | false | false | false |
Caneda/Caneda
|
libraries/hdl/vhdl/asynchronous/mux4x1.vhd
| 1 | 545 |
-- a, b, c and d are the inputs
-- sel is the input selection
-- z is the output
ENTITY mux4x1 IS
PORT (a: IN std_logic;
b: IN std_logic;
c: IN std_logic;
d: IN std_logic;
z: OUT std_logic;
sel: IN std_logic_vector(1 DOWNTO 0));
END mux4x1;
ARCHITECTURE rtl of mux4x1 IS
BEGIN
process(a,b,c,d,sel) begin
case sel is
when "00" => z <= a;
when "01" => z <= b;
when "10" => z <= c;
when "11" => z <= d;
end case;
end process;
END rtl;
|
gpl-2.0
|
f82418fefb0c44f20f0fe074c67ee06e
| 0.506422 | 2.994505 | false | false | false | false |
Raane/Term-Assigment-TFE4140-mod-anal-dig-sys
|
Project/liaison/src/controller.vhd
| 1 | 5,216 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity controller is
port(
di_ready : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
do_ready : out STD_LOGIC;
control_signals : out STD_LOGIC_VECTOR(9 downto 0);
voted_data_selector : out STD_LOGIC_VECTOR(3 downto 0)
);
end controller;
architecture controller of controller is
-- Next-signals used for clock updates
signal next_control_signals: std_logic_vector(9 downto 0);
signal next_vdsi: std_logic_vector(3 downto 0);
signal next_do_ready: std_logic;
signal do_ready_internal: std_logic; -- For internal use of do_ready
signal control_signals_internal : STD_LOGIC_VECTOR(9 downto 0); -- For internal use of control_signals
signal vdsi : STD_LOGIC_VECTOR(3 downto 0); -- For internal use of voted_data_selector (shortened to vdsi, i for internal)
begin
-- Setting component output from internal output signals
do_ready <= do_ready_internal;
control_signals <= control_signals_internal;
voted_data_selector <= vdsi;
-- Setting current output
clock_tick : process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
control_signals_internal <= "0000000000";
vdsi <= "0111"; -- 0111 is the first output, from V7
do_ready_internal <= '0';
else
-- Updating the controller's output values
-- based on current selected next-values
control_signals_internal <= next_control_signals;
vdsi <= next_vdsi;
do_ready_internal <= next_do_ready;
end if;
end if;
end process;
-- Selects register for storing input among voted data, status data and ECC data,
-- and also activates do_ready after 8 cycles
handle_input : process(di_ready, control_signals_internal)
variable nd_variable : std_logic; -- Used to set next_do_ready
begin
nd_variable := '0';
case control_signals_internal is
when "0000000000" =>
if (di_ready = '1') then -- di_ready works only when system is idle, with value "0000000000"
next_control_signals <= "0010000000"; -- store as bit 7
else
next_control_signals <= "0000000000"; -- Stay idle, di_ready has not yet hit in
end if;
when "0010000000" =>
next_control_signals <= "0001000000"; -- store as bit 6
when "0001000000" =>
next_control_signals <= "0000100000"; -- store as bit 5
when "0000100000" =>
next_control_signals <= "0000010000"; -- store as bit 4
when "0000010000" =>
next_control_signals <= "0000001000"; -- store as bit 3
when "0000001000" =>
next_control_signals <= "0000000100"; -- store as bit 2
when "0000000100" =>
next_control_signals <= "0000000010"; -- store as bit 1
when "0000000010" =>
nd_variable := '1'; -- Setting do_ready 8 cycles after di_ready has initiated storing. Otherwise, keep do_ready at 0
next_control_signals <= "0000000001"; -- store as bit 0
when "0000000001" =>
next_control_signals <= "0100000000"; -- store status
when "0100000000" =>
next_control_signals <= "1000000000"; -- update ECC-registers
when others => -- Done running through register storing. Do nothing until di_ready has been set again.
next_control_signals <= "0000000000";
end case;
next_do_ready <= nd_variable;
end process;
-- Selects output from the different registers, one at a time
-- default when idle is register v7
handle_output : process (vdsi, do_ready_internal)
begin
case vdsi is
when "0111" =>
if (do_ready_internal = '1') then
next_vdsi <= "0110"; -- set output from liaison to voted data bit 6
else
next_vdsi <= "0111"; -- Idle, do_ready is not 1, keep output on voted data bit 7
end if;
when "0110" =>
next_vdsi <= "0101"; -- set output from liaison to voted data bit 5
when "0101" =>
next_vdsi <= "0100"; -- set output from liaison to voted data bit 4
when "0100" =>
next_vdsi <= "0011"; -- set output from liaison to voted data bit 3
when "0011" =>
next_vdsi <= "0010"; -- set output from liaison to voted data bit 2
when "0010" =>
next_vdsi <= "0001"; -- set output from liaison to voted data bit 1
when "0001" =>
next_vdsi <= "0000"; -- set output from liaison to voted data bit 0
when "0000" =>
next_vdsi <= "1010"; -- set output from liaison to status bit 2
when "1010" =>
next_vdsi <= "1001"; -- set output from liaison to status bit 1
when "1001" =>
next_vdsi <= "1000"; -- set output from liaison to status bit 0
when "1000" =>
next_vdsi <= "1110"; -- set output from liaison to ECC bit 3
when "1110" =>
next_vdsi <= "1101"; -- set output from liaison to ECC bit 2
when "1101" =>
next_vdsi <= "1100"; -- set output from liaison to ECC bit 1
when "1100" =>
next_vdsi <= "1011"; -- set output from liaison to ECC bit 0
when others =>
next_vdsi <= "0111";
-- Reached when vdsi = "01111". Cycle is at end, setting output at voted data bit 7.
-- Using "When others" in case of glitch as well, though other values should never be reached.
-- Ideally, do_ready should have been set to 1 at the same time for max throughput
end case;
end process;
end controller;
|
apache-2.0
|
c82466a8bdc909a515b05fba70b002ba
| 0.651265 | 3.543478 | false | false | false | false |
lelongdunet/dspunit
|
rtl/setmem.vhd
| 2 | 6,169 |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
-------------------------------------------------------------------------------
entity setmem is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
newval_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
--@outputs;
dsp_bus : out t_dsp_bus
);
end setmem;
--=----------------------------------------------------------------------------
architecture archi_setmem of setmem is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_setmem_state is (st_init, st_set);
signal s_state : t_setmem_state;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
signal s_length_moins : unsigned((cmdreg_width - 1) downto 0);
signal s_new_val : std_logic_vector((sig_width - 1) downto 0);
signal s_wr : std_logic;
begin -- archs_setmem
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_setmem : process (clk)
begin -- process p_setmem
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
--s_dsp_bus <= c_dsp_bus_init;
s_dsp_bus.op_done <= '0';
-- memory 0
-- s_dsp_bus.data_out_m0 <= (others => '0');
--s_dsp_bus.c_en_m0 <= '0';
-- memory 1
-- s_dsp_bus.data_out_m1 <= (others => '0');
--s_dsp_bus.c_en_m1 <= '0';
-- memory 2
-- s_dsp_bus.data_out_m2 <= (others => '0');
--s_dsp_bus.c_en_m2 <= '0';
-- alu
--s_dsp_bus.mul_in_a1 <= (others <= '0');
--s_dsp_bus.mul_in_b1 <= (others <= '0');
--s_dsp_bus.mul_in_a2 <= (others <= '0');
--s_dsp_bus.mul_in_b2 <= (others <= '0');
s_dsp_bus.addr_m1 <= (others => '0');
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
s_dsp_bus.alu_select <= alu_mul;
-- global counter
--s_dsp_bus.gcounter_reset <= '0';
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
s_dsp_bus.addr_m1 <= (others => '0');
s_wr <= '0';
if s_dsp_bus.op_done = '0' then
s_state <= st_set;
s_wr <= '1';
end if;
when st_set =>
s_wr <= '1';
if(s_dsp_bus.addr_m1 = s_length_moins) then
s_state <= st_init;
s_dsp_bus.op_done <= '1';
s_wr <= '0';
else
s_dsp_bus.addr_m1 <= s_dsp_bus.addr_m1 + 1;
end if;
when others => null;
end case;
end if;
end if;
end process p_setmem;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
dsp_bus <= s_dsp_bus;
s_dsp_bus.addr_w_m0 <= s_dsp_bus.addr_m1;
s_dsp_bus.data_out_m2 <= s_new_val;
s_dsp_bus.data_out_m0 <= s_new_val;
s_dsp_bus.data_out_m1 <= s_new_val;
-- s_dsp_bus.data_out_m1 <= s_dsp_bus.addr_m1;
s_dsp_bus.addr_w_m0 <= s_dsp_bus.addr_m1;
s_dsp_bus.addr_m2 <= s_dsp_bus.addr_m1;
-- write bit ctrl
s_dsp_bus.wr_en_m0 <= s_wr when opflag_select(opflagbit_m0) = '1' else '0';
s_dsp_bus.wr_en_m1 <= s_wr when opflag_select(opflagbit_m1) = '1' else '0';
s_dsp_bus.wr_en_m2 <= s_wr when opflag_select(opflagbit_m2) = '1' else '0';
-- chip enable
s_dsp_bus.c_en_m0 <= '1';
s_dsp_bus.c_en_m1 <= '1';
s_dsp_bus.c_en_m2 <= '1';
s_dsp_bus.gcounter_reset <= '1';
s_length <= unsigned(length_reg);
s_length_moins <= s_length - 1;
s_new_val <= newval_reg;
end archi_setmem;
|
gpl-3.0
|
aa4d034e86ef0026a18579caac52f6c0
| 0.411412 | 3.800986 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/ROUTE_SIGNAL.vhd
| 2 | 4,342 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ROUTE_SIGNAL is
PORT(
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
select_vector : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OUTPUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end;
architecture signal_routing of ROUTE_SIGNAL is
component tristate_32
PORT(
my_in : in std_logic_vector(31 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(31 downto 0)
);
end component;
component HAZARD_RESOLVE
PORT(
select_signal : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end component;
signal data : std_logic_vector(31 downto 0);
begin
a_0 : tristate_32 PORT MAP (
my_in => ram_0_out_a,
sel => select_vector(15),
my_out => data
);
b_0 : tristate_32 PORT MAP (
my_in => ram_0_out_b,
sel => select_vector(14),
my_out => data
);
a_1 : tristate_32 PORT MAP (
my_in => ram_1_out_a,
sel => select_vector(13),
my_out => data
);
b_1 : tristate_32 PORT MAP (
my_in => ram_1_out_b,
sel => select_vector(12),
my_out => data
);
a_2 : tristate_32 PORT MAP (
my_in => ram_2_out_a,
sel => select_vector(11),
my_out => data
);
b_2 : tristate_32 PORT MAP (
my_in => ram_2_out_b,
sel => select_vector(10),
my_out => data
);
a_3 : tristate_32 PORT MAP (
my_in => ram_3_out_a,
sel => select_vector(9),
my_out => data
);
b_3 : tristate_32 PORT MAP (
my_in => ram_3_out_b,
sel => select_vector(8),
my_out => data
);
a_4 : tristate_32 PORT MAP (
my_in => ram_4_out_a,
sel => select_vector(7),
my_out => data
);
b_4 : tristate_32 PORT MAP (
my_in => ram_4_out_b,
sel => select_vector(6),
my_out => data
);
a_5 : tristate_32 PORT MAP (
my_in => ram_5_out_a,
sel => select_vector(5),
my_out => data
);
b_5 : tristate_32 PORT MAP (
my_in => ram_5_out_b,
sel => select_vector(4),
my_out => data
);
a_6 : tristate_32 PORT MAP (
my_in => ram_6_out_a,
sel => select_vector(3),
my_out => data
);
b_6 : tristate_32 PORT MAP (
my_in => ram_6_out_b,
sel => select_vector(2),
my_out => data
);
a_7 : tristate_32 PORT MAP (
my_in => ram_7_out_a,
sel => select_vector(1),
my_out => data
);
b_7 : tristate_32 PORT MAP (
my_in => ram_7_out_b,
sel => select_vector(0),
my_out => data
);
resolve_hazard : HAZARD_RESOLVE PORT MAP (
select_signal => select_vector,
hazard => hazard,
data => data,
CLK => CLK,
RESET_n => RESET_n,
hazard_advanced => hazard_advanced,
data_out => OUTPUT
);
end;
|
gpl-2.0
|
4d934b9c36b5e42ae956bbc1ced97dd0
| 0.501612 | 2.961801 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_if_statement_GNIV4UP6ZO.vhd
| 4 | 1,401 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a=b";
number_inputs : integer := 2;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNIV4UP6ZO is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(a=b) ;
true <= result;
end architecture;
|
mit
|
759f170236f6b1b9296a06d4a083830e
| 0.622413 | 3.25814 | false | false | false | false |
adelapie/desl
|
f_fun.vhd
| 1 | 5,556 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity f_fun is
port(clk : in std_logic;
r_in : in std_logic_vector(31 downto 0);
k_in : in std_logic_vector(47 downto 0);
r_out : out std_logic_vector(31 downto 0));
end f_fun;
architecture Behavioral of f_fun is
component dsp_xor is
port (clk : in std_logic;
op_1 : in std_logic_vector(31 downto 0);
op_2 : in std_logic_vector(31 downto 0);
op_3 : out std_logic_vector(31 downto 0));
end component;
component dsp_xor_48 is
port (clk : in std_logic;
op_1 : in std_logic_vector(47 downto 0);
op_2 : in std_logic_vector(47 downto 0);
op_3 : out std_logic_vector(47 downto 0));
end component;
COMPONENT s_box_dram_1
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_2
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_3
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_4
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_5
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_6
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_7
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_8
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_l_dual_dram
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
signal blk_exp_s : std_logic_vector(47 downto 0);
signal post_exp_key_add_s : std_logic_vector(47 downto 0);
signal post_s_box_s : std_logic_vector(31 downto 0);
begin
-- E
blk_exp_s <= r_in(0) & r_in(31) & r_in(30) & r_in(29) & r_in(28) & r_in(27) &
r_in(28) & r_in(27) & r_in(26) & r_in(25) & r_in(24) & r_in(23) &
r_in(24) & r_in(23) & r_in(22) & r_in(21) & r_in(20) & r_in(19) &
r_in(20) & r_in(19) & r_in(18) & r_in(17) & r_in(16) & r_in(15) &
r_in(16) & r_in(15) & r_in(14) & r_in(13) & r_in(12) & r_in(11) &
r_in(12) & r_in(11) & r_in(10) & r_in(9) & r_in(8) & r_in(7) &
r_in(8) & r_in(7) & r_in(6) & r_in(5) & r_in(4) & r_in(3) &
r_in(4) & r_in(3) & r_in(2) & r_in(1) & r_in(0) & r_in(31);
post_exp_key_add_s <= blk_exp_s xor k_in;
S_BOX_0 : s_box_l_dual_dram port map (post_exp_key_add_s(47 downto 42),
(others => '0'),
post_exp_key_add_s(41 downto 36),
clk,
'0',
post_s_box_s(31 downto 28),
post_s_box_s(27 downto 24));
S_BOX_1 : s_box_l_dual_dram port map (post_exp_key_add_s(35 downto 30),
(others => '0'),
post_exp_key_add_s(29 downto 24),
clk,
'0',
post_s_box_s(23 downto 20),
post_s_box_s(19 downto 16));
S_BOX_2 : s_box_l_dual_dram port map (post_exp_key_add_s(23 downto 18),
(others => '0'),
post_exp_key_add_s(17 downto 12),
clk,
'0',
post_s_box_s(15 downto 12),
post_s_box_s(11 downto 8));
S_BOX_3 : s_box_l_dual_dram port map (post_exp_key_add_s(11 downto 6),
(others => '0'),
post_exp_key_add_s(5 downto 0),
clk,
'0',
post_s_box_s(7 downto 4),
post_s_box_s(3 downto 0));
r_out <= post_s_box_s(16) & post_s_box_s(25) & post_s_box_s(12) & post_s_box_s(11) & post_s_box_s(3) & post_s_box_s(20) & post_s_box_s(4) & post_s_box_s(15) &
post_s_box_s(31) & post_s_box_s(17) & post_s_box_s(9) & post_s_box_s(6) & post_s_box_s(27) & post_s_box_s(14) & post_s_box_s(1) & post_s_box_s(22) &
post_s_box_s(30) & post_s_box_s(24) & post_s_box_s(8) & post_s_box_s(18) & post_s_box_s(0) & post_s_box_s(5) & post_s_box_s(29) & post_s_box_s(23) &
post_s_box_s(13) & post_s_box_s(19) & post_s_box_s(2) & post_s_box_s(26) & post_s_box_s(10) & post_s_box_s(21) & post_s_box_s(28) & post_s_box_s(7);
end Behavioral;
|
gpl-3.0
|
6ae086d4591a69bc55212f646f4f3cb9
| 0.554356 | 2.576994 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNKIWLRTQI.vhd
| 4 | 879 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNKIWLRTQI is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(47 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNKIWLRTQI is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 48 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(47 downto 0) => input,
xin(48) => '0', yout => output
);
end architecture;
|
mit
|
64b6f7767a341c0bed303a6aab82ba6f
| 0.649602 | 3.139286 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_counter.vhd
| 2 | 3,487 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_counter is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "0";
USE_SSET : string := "false";
USE_SLOAD : string := "false";
USE_SCLR : string := "false";
USE_COUT : string := "false";
MODULUS : integer := 256;
USE_CNT_ENA : string := "false";
WIDTH : natural := 8;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
user_aclr : in std_logic;
clock : in std_logic;
q : out std_logic_vector(width-1 downto 0);
direction : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aset : in std_logic;
cout : out std_logic;
sset : in std_logic;
aclr : in std_logic;
cnt_ena : in std_logic;
cin : in std_logic;
ena : in std_logic;
aload : in std_logic;
sload : in std_logic
);
end entity alt_dspbuilder_counter;
architecture rtl of alt_dspbuilder_counter is
component alt_dspbuilder_counter_GNZKRIGTBB is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "1";
USE_SSET : string := "false";
USE_SLOAD : string := "true";
USE_SCLR : string := "false";
USE_COUT : string := "false";
MODULUS : integer := 65536;
USE_CNT_ENA : string := "true";
WIDTH : natural := 24;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
aclr : in std_logic;
clock : in std_logic;
cnt_ena : in std_logic;
cout : out std_logic;
data : in std_logic_vector(24-1 downto 0);
q : out std_logic_vector(24-1 downto 0);
sload : in std_logic
);
end component alt_dspbuilder_counter_GNZKRIGTBB;
begin
alt_dspbuilder_counter_GNZKRIGTBB_0: if ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SSET = "false") and (USE_SLOAD = "true") and (USE_SCLR = "false") and (USE_COUT = "false") and (MODULUS = 65536) and (USE_CNT_ENA = "true") and (WIDTH = 24) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) generate
inst_alt_dspbuilder_counter_GNZKRIGTBB_0: alt_dspbuilder_counter_GNZKRIGTBB
generic map(USE_USR_ACLR => "false", USE_ENA => "false", USE_CIN => "false", NDIRECTION => 1, SVALUE => "1", USE_SSET => "false", USE_SLOAD => "true", USE_SCLR => "false", USE_COUT => "false", MODULUS => 65536, USE_CNT_ENA => "true", WIDTH => 24, USE_ASET => "false", USE_ALOAD => "false", AVALUE => "0")
port map(aclr => aclr, clock => clock, cnt_ena => cnt_ena, cout => cout, data => data, q => q, sload => sload);
end generate;
assert not (((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SSET = "false") and (USE_SLOAD = "true") and (USE_SCLR = "false") and (USE_COUT = "false") and (MODULUS = 65536) and (USE_CNT_ENA = "true") and (WIDTH = 24) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
844342a158bf291d3392ba4331f13489
| 0.634069 | 3.003445 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_pipelined_adder_GNTWZRTG4I.vhd
| 6 | 1,300 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic ( width : natural := 0;
pipeline : integer := 0);
port(
aclr : in std_logic;
add_sub : in std_logic;
cin : in std_logic;
clock : in std_logic;
cout : out std_logic;
dataa : in std_logic_vector((width)-1 downto 0);
datab : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
result : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
signal cin_internal : std_logic;
Begin
cin_internal <= '0';
-- DSP Builder Block - Simulink Block "PipelinedAdder"
PipelinedAdderi : alt_dspbuilder_sLpmAddSub Generic map (
or_aclr_inputs => true,
width => width,
pipeline => pipeline,
IsUnsigned => 1 )
port map (
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr,
cin => cin_internal,
add_sub => '1' ,
dataa => dataa,
datab => datab,
cout => cout,
result => result);
end architecture;
|
mit
|
6ec7391a2f6a9a7487b47b52e310424d
| 0.636154 | 2.908277 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd
| 2 | 34,606 |
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
port (
data_en : in std_logic := '0'; -- data_en.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
ctrl_en : in std_logic := '0'; -- ctrl_en.wire
colorbar : out std_logic_vector(23 downto 0); -- colorbar.wire
counter : in std_logic_vector(23 downto 0) := (others => '0') -- counter.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_bus_build_GNI6E4JZ66 is
generic (
width : natural := 8
);
port (
output : out std_logic_vector(2 downto 0); -- wire
in0 : in std_logic := 'X'; -- wire
in1 : in std_logic := 'X'; -- wire
in2 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_bus_build_GNI6E4JZ66;
component alt_dspbuilder_divider_GNKAPZN5MO is
generic (
Signed : natural := 0;
width : natural := 8;
pipeline : natural := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
denom : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
numer : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
quotient : out std_logic_vector(width-1 downto 0); -- wire
remain : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_divider_GNKAPZN5MO;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNJ7D74ANQ;
component alt_dspbuilder_constant_GNKT7L5CDY is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNKT7L5CDY;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_if_statement_GNMQPB5LUF is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNMQPB5LUF;
component alt_dspbuilder_if_statement_GNZR777PB6 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNZR777PB6;
component alt_dspbuilder_constant_GNUWBUDS4L is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNUWBUDS4L;
component alt_dspbuilder_constant_GNJ2DIDH6N is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNJ2DIDH6N;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_constant_GNNCFWNIJI is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNCFWNIJI;
component alt_dspbuilder_if_statement_GNWHMBR6GA is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNWHMBR6GA;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component StateMachineEditor1 is
port (
clock : in std_logic := 'X'; -- clk
col_select : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
data : out std_logic_vector(23 downto 0); -- wire
data_en : in std_logic := 'X'; -- wire
reset : in std_logic := 'X' -- wire
);
end component StateMachineEditor1;
component alt_dspbuilder_counter_GNZKRIGTBB is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNZKRIGTBB;
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
Signed : natural := 0;
OutputMsb : integer := 8;
aWidth : natural := 8;
bWidth : natural := 8;
OutputLsb : integer := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
dataa : in std_logic_vector(aWidth-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(bWidth-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
component alt_dspbuilder_cast_GN7PRGDOVA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7PRGDOVA;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
component alt_dspbuilder_cast_GNLHWQIRQK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLHWQIRQK;
signal pipelined_adder3user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder3user_aclrGND:output -> Pipelined_Adder3:user_aclr
signal pipelined_adder3enavcc_output_wire : std_logic; -- Pipelined_Adder3enaVCC:output -> Pipelined_Adder3:ena
signal divideruser_aclrgnd_output_wire : std_logic; -- Divideruser_aclrGND:output -> Divider:user_aclr
signal dividerenavcc_output_wire : std_logic; -- DividerenaVCC:output -> Divider:ena
signal single_pulse1sclrgnd_output_wire : std_logic; -- Single_Pulse1sclrGND:output -> Single_Pulse1:sclr
signal single_pulse1enavcc_output_wire : std_logic; -- Single_Pulse1enaVCC:output -> Single_Pulse1:ena
signal multiplieruser_aclrgnd_output_wire : std_logic; -- Multiplieruser_aclrGND:output -> Multiplier:user_aclr
signal multiplierenavcc_output_wire : std_logic; -- MultiplierenaVCC:output -> Multiplier:ena
signal constant9_output_wire : std_logic_vector(23 downto 0); -- Constant9:output -> Counter1:data
signal constant8_output_wire : std_logic_vector(23 downto 0); -- Constant8:output -> Divider:denom
signal counter1_q_wire : std_logic_vector(23 downto 0); -- Counter1:q -> [If_Statement1:a, If_Statement2:a, If_Statement3:a, If_Statement:a]
signal divider_quotient_wire : std_logic_vector(23 downto 0); -- Divider:quotient -> [If_Statement1:b, If_Statement:b, Multiplier:dataa]
signal if_statement_true_wire : std_logic; -- If_Statement:true -> Bus_Builder:in0
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Bus_Builder:in1
signal if_statement2_true_wire : std_logic; -- If_Statement2:true -> Bus_Builder:in2
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> If_Statement5:a
signal if_statement3_true_wire : std_logic; -- If_Statement3:true -> Logical_Bit_Operator12:data0
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator12:data1, Logical_Bit_Operator8:data0, State_Machine_Editor1:data_en]
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> Logical_Bit_Operator7:data0
signal logical_bit_operator12_result_wire : std_logic; -- Logical_Bit_Operator12:result -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Counter1:sload
signal if_statement5_true_wire : std_logic; -- If_Statement5:true -> Logical_Bit_Operator8:data1
signal logical_bit_operator8_result_wire : std_logic; -- Logical_Bit_Operator8:result -> Counter1:cnt_ena
signal constant6_output_wire : std_logic_vector(23 downto 0); -- Constant6:output -> Multiplier:datab
signal constant13_output_wire : std_logic_vector(23 downto 0); -- Constant13:output -> Pipelined_Adder3:datab
signal pipelined_adder3_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder3:result -> If_Statement2:c
signal single_pulse1_result_wire : std_logic; -- Single_Pulse1:result -> State_Machine_Editor1:reset
signal state_machine_editor1_data_wire : std_logic_vector(23 downto 0); -- State_Machine_Editor1:data -> colorbar_0:input
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> [cast0:input, cast1:input, cast2:input, cast6:input]
signal cast0_output_wire : std_logic_vector(23 downto 0); -- cast0:output -> Divider:numer
signal cast1_output_wire : std_logic_vector(23 downto 0); -- cast1:output -> If_Statement:c
signal cast2_output_wire : std_logic_vector(23 downto 0); -- cast2:output -> If_Statement3:b
signal constant11_output_wire : std_logic_vector(15 downto 0); -- Constant11:output -> cast3:input
signal cast3_output_wire : std_logic_vector(23 downto 0); -- cast3:output -> If_Statement5:b
signal multiplier_result_wire : std_logic_vector(47 downto 0); -- Multiplier:result -> [cast4:input, cast5:input]
signal cast4_output_wire : std_logic_vector(23 downto 0); -- cast4:output -> If_Statement1:c
signal cast5_output_wire : std_logic_vector(23 downto 0); -- cast5:output -> If_Statement2:b
signal cast6_output_wire : std_logic_vector(23 downto 0); -- cast6:output -> Pipelined_Adder3:dataa
signal bus_builder_output_wire : std_logic_vector(2 downto 0); -- Bus_Builder:output -> cast7:input
signal cast7_output_wire : std_logic_vector(2 downto 0); -- cast7:output -> State_Machine_Editor1:col_select
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Counter1:aclr, Divider:aclr, Multiplier:aclr, Pipelined_Adder3:aclr, Single_Pulse1:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Counter1:clock, Divider:clock, Multiplier:clock, Pipelined_Adder3:clock, Single_Pulse1:clock, State_Machine_Editor1:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
pipelined_adder3 : component alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast6_output_wire, -- dataa.wire
datab => constant13_output_wire, -- datab.wire
result => pipelined_adder3_result_wire, -- result.wire
user_aclr => pipelined_adder3user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder3enavcc_output_wire -- ena.wire
);
pipelined_adder3user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder3user_aclrgnd_output_wire -- output.wire
);
pipelined_adder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder3enavcc_output_wire -- output.wire
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
bus_builder : component alt_dspbuilder_bus_build_GNI6E4JZ66
generic map (
width => 3
)
port map (
output => bus_builder_output_wire, -- output.wire
in0 => if_statement_true_wire, -- in0.wire
in1 => if_statement1_true_wire, -- in1.wire
in2 => if_statement2_true_wire -- in2.wire
);
divider : component alt_dspbuilder_divider_GNKAPZN5MO
generic map (
Signed => 0,
width => 24,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
numer => cast0_output_wire, -- numer.wire
denom => constant8_output_wire, -- denom.wire
quotient => divider_quotient_wire, -- quotient.wire
remain => open, -- remain.wire
user_aclr => divideruser_aclrgnd_output_wire, -- user_aclr.wire
ena => dividerenavcc_output_wire -- ena.wire
);
divideruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => divideruser_aclrgnd_output_wire -- output.wire
);
dividerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => dividerenavcc_output_wire -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => state_machine_editor1_data_wire, -- input.wire
output => colorbar -- output.wire
);
if_statement5 : component alt_dspbuilder_if_statement_GNJ7D74ANQ
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a>b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement5_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast3_output_wire -- b.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
constant6 : component alt_dspbuilder_constant_GNKT7L5CDY
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000010",
width => 24
)
port map (
output => constant6_output_wire -- output.wire
);
if_statement3 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement3_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast2_output_wire -- b.wire
);
logical_bit_operator12 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator12_result_wire, -- result.wire
data0 => if_statement3_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
if_statement2 : component alt_dspbuilder_if_statement_GNMQPB5LUF
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and ((a<c) or (a=c))",
number_inputs => 3,
width => 24
)
port map (
true => if_statement2_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast5_output_wire, -- b.wire
c => pipelined_adder3_result_wire -- c.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GNZR777PB6
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and (a<c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast4_output_wire -- c.wire
);
constant8 : component alt_dspbuilder_constant_GNUWBUDS4L
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000011",
width => 24
)
port map (
output => constant8_output_wire -- output.wire
);
constant9 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant9_output_wire -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => logical_bit_operator12_result_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
constant11 : component alt_dspbuilder_constant_GNNCFWNIJI
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000100",
width => 16
)
port map (
output => constant11_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNWHMBR6GA
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>zero) and (a<b)) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast1_output_wire -- c.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
constant13 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant13_output_wire -- output.wire
);
logical_bit_operator8 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator8_result_wire, -- result.wire
data0 => data_en_0_output_wire, -- data0.wire
data1 => if_statement5_true_wire -- data1.wire
);
single_pulse1 : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse1_result_wire, -- result.wire
sclr => single_pulse1sclrgnd_output_wire, -- sclr.wire
ena => single_pulse1enavcc_output_wire -- ena.wire
);
single_pulse1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulse1sclrgnd_output_wire -- output.wire
);
single_pulse1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulse1enavcc_output_wire -- output.wire
);
state_machine_editor1 : component StateMachineEditor1
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse1_result_wire, -- reset.wire
col_select => cast7_output_wire, -- col_select.wire
data_en => data_en_0_output_wire, -- data_en.wire
data => state_machine_editor1_data_wire -- data.wire
);
counter1 : component alt_dspbuilder_counter_GNZKRIGTBB
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "true",
use_sclr => "false",
use_cout => "false",
modulus => 65536,
use_cnt_ena => "true",
width => 24,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => constant9_output_wire, -- data.wire
cnt_ena => logical_bit_operator8_result_wire, -- cnt_ena.wire
sload => logical_bit_operator7_result_wire, -- sload.wire
q => counter1_q_wire, -- q.wire
cout => open -- cout.wire
);
multiplier : component alt_dspbuilder_multiplier_GNEIWYOKUR
generic map (
DEDICATED_MULTIPLIER_CIRCUITRY => "YES",
Signed => 0,
OutputMsb => 47,
aWidth => 24,
bWidth => 24,
OutputLsb => 0,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => divider_quotient_wire, -- dataa.wire
datab => constant6_output_wire, -- datab.wire
result => multiplier_result_wire, -- result.wire
user_aclr => multiplieruser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiplierenavcc_output_wire -- ena.wire
);
multiplieruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplieruser_aclrgnd_output_wire -- output.wire
);
multiplierenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplierenavcc_output_wire -- output.wire
);
cast0 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant11_output_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
cast4 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast4_output_wire -- output.wire
);
cast5 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast5_output_wire -- output.wire
);
cast6 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast6_output_wire -- output.wire
);
cast7 : component alt_dspbuilder_cast_GNLHWQIRQK
generic map (
round => 0,
saturate => 0
)
port map (
input => bus_builder_output_wire, -- input.wire
output => cast7_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE
|
mit
|
308ab5b4428194018e6b278396e54b50
| 0.54661 | 3.361438 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/generic_28nm_lc_mlab_cell_impl/_primary.vhd
| 5 | 2,780 |
library verilog;
use verilog.vl_types.all;
entity generic_28nm_lc_mlab_cell_impl is
generic(
logical_ram_name: string := "lutram";
logical_ram_depth: integer := 0;
logical_ram_width: integer := 0;
first_address : integer := 0;
last_address : integer := 0;
first_bit_number: integer := 0;
mixed_port_feed_through_mode: string := "new";
init_file : string := "NONE";
data_width : integer := 20;
address_width : integer := 6;
byte_enable_mask_width: integer := 1;
byte_size : integer := 1;
port_b_data_out_clock: string := "none";
port_b_data_out_clear: string := "none";
lpm_type : string := "common_28nm_mlab_cell";
lpm_hint : string := "true";
mem_init0 : string := ""
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portabyteenamasks: in vl_logic_vector;
portbaddr : in vl_logic_vector;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
clr : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
portbdataout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of first_address : constant is 1;
attribute mti_svvh_generic_type of last_address : constant is 1;
attribute mti_svvh_generic_type of first_bit_number : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of data_width : constant is 1;
attribute mti_svvh_generic_type of address_width : constant is 1;
attribute mti_svvh_generic_type of byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
end generic_28nm_lc_mlab_cell_impl;
|
mit
|
a5eadf37f4f6ed90e0f6478b98527a45
| 0.597122 | 3.624511 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_proc_sys_reset_0/sim/tutorial_proc_sys_reset_0.vhd
| 1 | 5,845 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY tutorial_proc_sys_reset_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_proc_sys_reset_0;
ARCHITECTURE tutorial_proc_sys_reset_0_arch OF tutorial_proc_sys_reset_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_proc_sys_reset_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END tutorial_proc_sys_reset_0_arch;
|
gpl-2.0
|
97e11427935b441bb6419dde63b6e6f7
| 0.707613 | 3.625931 | false | false | false | false |
Ttl/bf_cpu
|
datapath.vhd
| 1 | 2,389 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.bfconfig.all;
use ieee.numeric_std.all;
entity datapath is
Port ( clk, reset : in STD_LOGIC;
c_skip : in STD_LOGIC;
d_alutoreg : in STD_LOGIC;
d_alua : in STD_LOGIC_VECTOR(1 downto 0);
d_alub : in STD_LOGIC_VECTOR(1 downto 0);
readdata : in STD_LOGIC_VECTOR(7 downto 0);
writedata : out STD_LOGIC_VECTOR(7 downto 0);
alu_z : out STD_LOGIC);
end datapath;
architecture Behavioral of datapath is
signal alua_out : pointertype;
signal alu_result : pointertype;
-- Pointer to registers
signal pointer : pointertype := (others => '0');
-- Register output from address pointed by pointer
signal mem : std_logic_vector(7 downto 0);
signal reg_write : std_logic;
constant zeros : std_logic_vector(REG_SIZE-1 downto 8) := (others => '0');
begin
-- d_alua
-- 00 : mem(pointer)
-- 01 : pointer
-- 10 : read from input
-- 11 : illegal
-- First bit of d_alub is extended
-- extended to adder bits 2 ->
-- This allows to make three necessat constants-
-- with two bits and without multiplexer
-- d_alub
-- 00 : 0
-- 01 : 1
-- 10 : Illegal
-- 11 : -1
-- d_alutoreg
-- 0 : write alu result to mem(pointer)
-- 1 : write alu result to pointer
process(clk, reset)
begin
if reset = '1' then
pointer <= (others => '0');
elsif rising_edge(clk) then
if d_alutoreg = '1' and c_skip = '0' then
pointer <= alu_result;
else
pointer <= pointer;
end if;
end if;
end process;
alua_out <= zeros&mem when d_alua = "00" else
pointer when d_alua = "01" else
zeros&readdata when d_alua = "10" else
(others => '-');
reg_write <= (not d_alutoreg and not c_skip);
regs : entity work.reg_file
Port map( clk => clk,
a1 => pointer,
wd => alu_result(7 downto 0),
d1 => mem,
we => reg_write
);
-- Adder
process(alua_out, d_alub)
variable sign_ext : std_logic_vector(REG_SIZE-1 downto 2);
begin
-- Sign extend the B port input
sign_ext := (others => d_alub(1));
alu_result <= std_logic_vector(unsigned(alua_out)+unsigned(sign_ext&d_alub));
end process;
-- Zero flag calculation.
-- It is only checked after [ or ]
-- This allows one cycle delay
-- And we don't need to compare alu_result
alu_z <= '1' when mem = x"00" else '0';
writedata <= mem;
end Behavioral;
|
lgpl-3.0
|
79f9f45818e9623aca77e14caa8d27c5
| 0.622018 | 3.268126 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/twentynm_iopll_ip/_primary.vhd
| 5 | 30,798 |
library verilog;
use verilog.vl_types.all;
entity twentynm_iopll_ip is
generic(
number_of_counters: integer := 9;
number_of_extclks: integer := 2;
number_of_fine_delay_chains: integer := 4;
reference_clock_frequency: string := "100.0 MHz";
vco_frequency : string := "300.0 MHz";
output_clock_frequency_0: string := "100.0 MHz";
output_clock_frequency_1: string := "0 ps";
output_clock_frequency_2: string := "0 ps";
output_clock_frequency_3: string := "0 ps";
output_clock_frequency_4: string := "0 ps";
output_clock_frequency_5: string := "0 ps";
output_clock_frequency_6: string := "0 ps";
output_clock_frequency_7: string := "0 ps";
output_clock_frequency_8: string := "0 ps";
duty_cycle_0 : integer := 50;
duty_cycle_1 : integer := 50;
duty_cycle_2 : integer := 50;
duty_cycle_3 : integer := 50;
duty_cycle_4 : integer := 50;
duty_cycle_5 : integer := 50;
duty_cycle_6 : integer := 50;
duty_cycle_7 : integer := 50;
duty_cycle_8 : integer := 50;
phase_shift_0 : string := "0 ps";
phase_shift_1 : string := "0 ps";
phase_shift_2 : string := "0 ps";
phase_shift_3 : string := "0 ps";
phase_shift_4 : string := "0 ps";
phase_shift_5 : string := "0 ps";
phase_shift_6 : string := "0 ps";
phase_shift_7 : string := "0 ps";
phase_shift_8 : string := "0 ps";
compensation_mode: string := "normal";
bw_sel : string := "auto";
silicon_rev : string := "reve";
speed_grade : string := "2";
use_default_base_address: string := "true";
user_base_address: integer := 0;
is_cascaded_pll : string := "false";
pll_dprio_base_addr: integer := 0;
pll_dprio_broadcast_en: string := "false";
pll_dprio_cvp_inter_sel: string := "false";
pll_dprio_force_inter_sel: string := "false";
pll_dprio_power_iso_en: string := "false";
pll_c0_extclk_dllout_en: string := "true";
pll_c0_out_en : string := "false";
pll_c1_extclk_dllout_en: string := "true";
pll_c1_out_en : string := "false";
pll_c2_extclk_dllout_en: string := "true";
pll_c2_out_en : string := "false";
pll_c3_extclk_dllout_en: string := "true";
pll_c3_out_en : string := "false";
pll_c4_out_en : string := "false";
pll_c5_out_en : string := "false";
pll_c6_out_en : string := "false";
pll_c7_out_en : string := "false";
pll_c8_out_en : string := "false";
pll_dft_ppmclk : string := "c_cnt_out";
pll_powerdown_mode: string := "false";
pll_phyfb_mux : string := "m_cnt_phmux_out";
pll_c_counter_0_bypass_en: string := "false";
pll_c_counter_0_coarse_dly: string := "0 ps";
pll_c_counter_0_even_duty_en: string := "false";
pll_c_counter_0_fine_dly: string := "0 ps";
pll_c_counter_0_high: integer := 256;
pll_c_counter_0_in_src: string := "c_m_cnt_in_src_ph_mux_clk";
pll_c_counter_0_low: integer := 256;
pll_c_counter_0_ph_mux_prst: integer := 0;
pll_c_counter_0_prst: integer := 1;
pll_c_counter_1_bypass_en: string := "false";
pll_c_counter_1_coarse_dly: string := "0 ps";
pll_c_counter_1_even_duty_en: string := "false";
pll_c_counter_1_fine_dly: string := "0 ps";
pll_c_counter_1_high: integer := 256;
pll_c_counter_1_in_src: string := "c_m_cnt_in_src_ph_mux_clk";
pll_c_counter_1_low: integer := 256;
pll_c_counter_1_ph_mux_prst: integer := 0;
pll_c_counter_1_prst: integer := 1;
pll_c_counter_2_bypass_en: string := "false";
pll_c_counter_2_coarse_dly: string := "0 ps";
pll_c_counter_2_even_duty_en: string := "false";
pll_c_counter_2_fine_dly: string := "0 ps";
pll_c_counter_2_high: integer := 256;
pll_c_counter_2_in_src: string := "c_m_cnt_in_src_ph_mux_clk";
pll_c_counter_2_low: integer := 256;
pll_c_counter_2_ph_mux_prst: integer := 0;
pll_c_counter_2_prst: integer := 1;
pll_c_counter_3_bypass_en: string := "false";
pll_c_counter_3_coarse_dly: string := "0 ps";
pll_c_counter_3_even_duty_en: string := "false";
pll_c_counter_3_fine_dly: string := "0 ps";
pll_c_counter_3_high: integer := 256;
pll_c_counter_3_in_src: string := "c_m_cnt_in_src_ph_mux_clk";
pll_c_counter_3_low: integer := 256;
pll_c_counter_3_ph_mux_prst: integer := 0;
pll_c_counter_3_prst: integer := 1;
pll_c_counter_4_bypass_en: string := "false";
pll_c_counter_4_coarse_dly: string := "0 ps";
pll_c_counter_4_even_duty_en: string := "false";
pll_c_counter_4_fine_dly: string := "0 ps";
pll_c_counter_4_high: integer := 256;
pll_c_counter_4_in_src: string := "c_m_cnt_in_src_ph_mux_clk";
pll_c_counter_4_low: integer := 256;
pll_c_counter_4_ph_mux_prst: integer := 0;
pll_c_counter_4_prst: integer := 1;
pll_c_counter_5_bypass_en: string := "false";
pll_c_counter_5_coarse_dly: string := "0 ps";
pll_c_counter_5_even_duty_en: string := "false";
pll_c_counter_5_fine_dly: string := "0 ps";
pll_c_counter_5_high: integer := 256;
pll_c_counter_5_in_src: string := "c_m_cnt_in_src_ph_mux_clk";
pll_c_counter_5_low: integer := 256;
pll_c_counter_5_ph_mux_prst: integer := 0;
pll_c_counter_5_prst: integer := 1;
pll_c_counter_6_bypass_en: string := "false";
pll_c_counter_6_coarse_dly: string := "0 ps";
pll_c_counter_6_even_duty_en: string := "false";
pll_c_counter_6_fine_dly: string := "0 ps";
pll_c_counter_6_high: integer := 256;
pll_c_counter_6_in_src: string := "c_m_cnt_in_src_ph_mux_clk";
pll_c_counter_6_low: integer := 256;
pll_c_counter_6_ph_mux_prst: integer := 0;
pll_c_counter_6_prst: integer := 1;
pll_c_counter_7_bypass_en: string := "false";
pll_c_counter_7_coarse_dly: string := "0 ps";
pll_c_counter_7_even_duty_en: string := "false";
pll_c_counter_7_fine_dly: string := "0 ps";
pll_c_counter_7_high: integer := 256;
pll_c_counter_7_in_src: string := "c_m_cnt_in_src_ph_mux_clk";
pll_c_counter_7_low: integer := 256;
pll_c_counter_7_ph_mux_prst: integer := 0;
pll_c_counter_7_prst: integer := 1;
pll_c_counter_8_bypass_en: string := "false";
pll_c_counter_8_coarse_dly: string := "0 ps";
pll_c_counter_8_even_duty_en: string := "false";
pll_c_counter_8_fine_dly: string := "0 ps";
pll_c_counter_8_high: integer := 256;
pll_c_counter_8_in_src: string := "c_m_cnt_in_src_ph_mux_clk";
pll_c_counter_8_low: integer := 256;
pll_c_counter_8_ph_mux_prst: integer := 0;
pll_c_counter_8_prst: integer := 1;
pll_clkin_0_src : string := "pll_clkin_0_src_ioclkin_0";
pll_clkin_1_src : string := "pll_clkin_1_src_ioclkin_0";
pll_auto_clk_sw_en: string := "false";
pll_clk_loss_edge: string := "pll_clk_loss_both_edges";
pll_clk_loss_sw_en: string := "false";
pll_clk_sw_dly : integer := 0;
pll_manu_clk_sw_en: string := "false";
pll_sw_refclk_src: string := "pll_sw_refclk_src_clk_0";
pll_dll_src : string := "pll_dll_src_vss";
pll_extclk_0_cnt_src: string := "pll_extclk_cnt_src_vss";
pll_extclk_0_enable: string := "false";
pll_extclk_0_invert: string := "false";
pll_extclk_1_cnt_src: string := "pll_extclk_cnt_src_vss";
pll_extclk_1_enable: string := "false";
pll_extclk_1_invert: string := "false";
pll_coarse_dly_0: string := "0 ps";
pll_coarse_dly_1: string := "0 ps";
pll_coarse_dly_2: string := "0 ps";
pll_coarse_dly_3: string := "0 ps";
pll_dly_0_enable: string := "true";
pll_dly_1_enable: string := "true";
pll_dly_2_enable: string := "true";
pll_dly_3_enable: string := "true";
pll_fine_dly_0 : string := "0 ps";
pll_fine_dly_1 : string := "0 ps";
pll_fine_dly_2 : string := "0 ps";
pll_fine_dly_3 : string := "0 ps";
pll_nreset_invert: string := "false";
pll_ctrl_override_setting: string := "true";
pll_enable : string := "true";
pll_self_reset : string := "false";
pll_test_enable : string := "false";
pll_dft_plniotri_override: string := "false";
pll_vccr_pd_en : string := "false";
pll_atb : string := "atb_selectdisable";
pll_bwctrl : string := "pll_bw_res_setting4";
pll_cp_compensation: string := "true";
pll_cp_current_setting: string := "pll_cp_setting2";
pll_ripplecap_ctrl: string := "pll_ripplecap_setting0";
pll_testdn_enable: string := "false";
pll_testup_enable: string := "false";
pll_cmp_buf_dly : string := "0 ps";
pll_fbclk_mux_1 : string := "pll_fbclk_mux_1_glb";
pll_fbclk_mux_2 : string := "pll_fbclk_mux_2_fb_1";
pll_n_counter_coarse_dly: string := "0 ps";
pll_n_counter_fine_dly: string := "0 ps";
pll_lock_fltr_cfg: integer := 25;
pll_lock_fltr_test: string := "pll_lock_fltr_nrm";
pll_unlock_fltr_cfg: integer := 2;
pll_m_counter_bypass_en: string := "true";
pll_m_counter_coarse_dly: string := "0 ps";
pll_m_counter_even_duty_en: string := "false";
pll_m_counter_fine_dly: string := "0 ps";
pll_m_counter_high: integer := 256;
pll_m_counter_in_src: string := "c_m_cnt_in_src_ph_mux_clk";
pll_m_counter_low: integer := 256;
pll_m_counter_ph_mux_prst: integer := 0;
pll_m_counter_prst: integer := 1;
pll_n_counter_bypass_en: string := "true";
pll_n_counter_high: integer := 256;
pll_n_counter_low: integer := 256;
pll_n_counter_odd_div_duty_en: string := "false";
pll_ref_buf_dly : string := "0 ps";
pll_tclk_mux_en : string := "false";
pll_tclk_sel : string := "pll_tclk_m_src";
pll_dft_vco_ph0_en: string := "false";
pll_dft_vco_ph1_en: string := "false";
pll_dft_vco_ph2_en: string := "false";
pll_dft_vco_ph3_en: string := "false";
pll_dft_vco_ph4_en: string := "false";
pll_dft_vco_ph5_en: string := "false";
pll_dft_vco_ph6_en: string := "false";
pll_dft_vco_ph7_en: string := "false";
pll_vco_ph0_en : string := "true";
pll_vco_ph1_en : string := "true";
pll_vco_ph2_en : string := "true";
pll_vco_ph3_en : string := "true";
pll_vco_ph4_en : string := "true";
pll_vco_ph5_en : string := "true";
pll_vco_ph6_en : string := "true";
pll_vco_ph7_en : string := "true"
);
port(
clken : in vl_logic_vector(1 downto 0);
cnt_sel : in vl_logic_vector(3 downto 0);
core_refclk : in vl_logic;
csr_clk : in vl_logic;
csr_en : in vl_logic;
csr_in : in vl_logic;
dprio_address : in vl_logic_vector(8 downto 0);
dprio_clk : in vl_logic;
dprio_rst_n : in vl_logic;
dps_rst_n : in vl_logic;
extswitch : in vl_logic;
fbclk_in : in vl_logic;
fblvds_in : in vl_logic;
mdio_dis : in vl_logic;
num_phase_shifts: in vl_logic_vector(2 downto 0);
pfden : in vl_logic;
phase_en : in vl_logic;
pipeline_global_en_n: in vl_logic;
pll_cascade_in : in vl_logic;
pma_csr_test_dis: in vl_logic;
read : in vl_logic;
refclk : in vl_logic_vector(3 downto 0);
rst_n : in vl_logic;
scan_mode_n : in vl_logic;
scan_shift_n : in vl_logic;
up_dn : in vl_logic;
user_mode : in vl_logic;
write : in vl_logic;
writedata : in vl_logic_vector(7 downto 0);
zdb_in : in vl_logic;
block_select : out vl_logic;
clk0_bad : out vl_logic;
clk1_bad : out vl_logic;
clksel : out vl_logic;
csr_out : out vl_logic;
dll_output : out vl_logic;
extclk_dft : out vl_logic_vector(1 downto 0);
extclk_output : out vl_logic_vector(1 downto 0);
fbclk_out : out vl_logic;
fblvds_out : out vl_logic;
lf_reset : out vl_logic;
loaden : out vl_logic_vector(1 downto 0);
lock : out vl_logic;
lvds_clk : out vl_logic_vector(1 downto 0);
outclk : out vl_logic_vector(8 downto 0);
readdata : out vl_logic_vector(7 downto 0);
phase_done : out vl_logic;
pll_cascade_out : out vl_logic;
pll_pd : out vl_logic;
vcop_en : out vl_logic;
vcoph : out vl_logic_vector(7 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_counters : constant is 1;
attribute mti_svvh_generic_type of number_of_extclks : constant is 1;
attribute mti_svvh_generic_type of number_of_fine_delay_chains : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of vco_frequency : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_2 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_3 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_4 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_5 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_6 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_7 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_8 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_0 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_1 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_2 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_3 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_4 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_5 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_6 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_7 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_8 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_0 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_1 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_2 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_3 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_4 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_5 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_6 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_7 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_8 : constant is 1;
attribute mti_svvh_generic_type of compensation_mode : constant is 1;
attribute mti_svvh_generic_type of bw_sel : constant is 1;
attribute mti_svvh_generic_type of silicon_rev : constant is 1;
attribute mti_svvh_generic_type of speed_grade : constant is 1;
attribute mti_svvh_generic_type of use_default_base_address : constant is 1;
attribute mti_svvh_generic_type of user_base_address : constant is 1;
attribute mti_svvh_generic_type of is_cascaded_pll : constant is 1;
attribute mti_svvh_generic_type of pll_dprio_base_addr : constant is 1;
attribute mti_svvh_generic_type of pll_dprio_broadcast_en : constant is 1;
attribute mti_svvh_generic_type of pll_dprio_cvp_inter_sel : constant is 1;
attribute mti_svvh_generic_type of pll_dprio_force_inter_sel : constant is 1;
attribute mti_svvh_generic_type of pll_dprio_power_iso_en : constant is 1;
attribute mti_svvh_generic_type of pll_c0_extclk_dllout_en : constant is 1;
attribute mti_svvh_generic_type of pll_c0_out_en : constant is 1;
attribute mti_svvh_generic_type of pll_c1_extclk_dllout_en : constant is 1;
attribute mti_svvh_generic_type of pll_c1_out_en : constant is 1;
attribute mti_svvh_generic_type of pll_c2_extclk_dllout_en : constant is 1;
attribute mti_svvh_generic_type of pll_c2_out_en : constant is 1;
attribute mti_svvh_generic_type of pll_c3_extclk_dllout_en : constant is 1;
attribute mti_svvh_generic_type of pll_c3_out_en : constant is 1;
attribute mti_svvh_generic_type of pll_c4_out_en : constant is 1;
attribute mti_svvh_generic_type of pll_c5_out_en : constant is 1;
attribute mti_svvh_generic_type of pll_c6_out_en : constant is 1;
attribute mti_svvh_generic_type of pll_c7_out_en : constant is 1;
attribute mti_svvh_generic_type of pll_c8_out_en : constant is 1;
attribute mti_svvh_generic_type of pll_dft_ppmclk : constant is 1;
attribute mti_svvh_generic_type of pll_powerdown_mode : constant is 1;
attribute mti_svvh_generic_type of pll_phyfb_mux : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_0_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_0_coarse_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_0_even_duty_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_0_fine_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_0_high : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_0_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_0_low : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_0_ph_mux_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_0_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_1_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_1_coarse_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_1_even_duty_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_1_fine_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_1_high : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_1_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_1_low : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_1_ph_mux_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_1_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_2_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_2_coarse_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_2_even_duty_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_2_fine_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_2_high : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_2_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_2_low : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_2_ph_mux_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_2_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_3_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_3_coarse_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_3_even_duty_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_3_fine_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_3_high : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_3_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_3_low : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_3_ph_mux_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_3_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_4_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_4_coarse_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_4_even_duty_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_4_fine_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_4_high : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_4_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_4_low : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_4_ph_mux_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_4_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_5_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_5_coarse_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_5_even_duty_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_5_fine_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_5_high : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_5_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_5_low : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_5_ph_mux_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_5_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_6_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_6_coarse_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_6_even_duty_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_6_fine_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_6_high : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_6_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_6_low : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_6_ph_mux_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_6_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_7_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_7_coarse_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_7_even_duty_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_7_fine_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_7_high : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_7_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_7_low : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_7_ph_mux_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_7_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_8_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_8_coarse_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_8_even_duty_en : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_8_fine_dly : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_8_high : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_8_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_8_low : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_8_ph_mux_prst : constant is 1;
attribute mti_svvh_generic_type of pll_c_counter_8_prst : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_0_cnt_src : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_0_enable : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_0_invert : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_1_cnt_src : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_1_enable : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_1_invert : constant is 1;
attribute mti_svvh_generic_type of pll_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_dly_0_enable : constant is 1;
attribute mti_svvh_generic_type of pll_dly_1_enable : constant is 1;
attribute mti_svvh_generic_type of pll_dly_2_enable : constant is 1;
attribute mti_svvh_generic_type of pll_dly_3_enable : constant is 1;
attribute mti_svvh_generic_type of pll_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_nreset_invert : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting : constant is 1;
attribute mti_svvh_generic_type of pll_enable : constant is 1;
attribute mti_svvh_generic_type of pll_self_reset : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable : constant is 1;
attribute mti_svvh_generic_type of pll_dft_plniotri_override : constant is 1;
attribute mti_svvh_generic_type of pll_vccr_pd_en : constant is 1;
attribute mti_svvh_generic_type of pll_atb : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl : constant is 1;
attribute mti_svvh_generic_type of pll_cp_compensation : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_setting : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2 : constant is 1;
attribute mti_svvh_generic_type of pll_n_counter_coarse_dly : constant is 1;
attribute mti_svvh_generic_type of pll_n_counter_fine_dly : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg : constant is 1;
attribute mti_svvh_generic_type of pll_m_counter_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_m_counter_coarse_dly : constant is 1;
attribute mti_svvh_generic_type of pll_m_counter_even_duty_en : constant is 1;
attribute mti_svvh_generic_type of pll_m_counter_fine_dly : constant is 1;
attribute mti_svvh_generic_type of pll_m_counter_high : constant is 1;
attribute mti_svvh_generic_type of pll_m_counter_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_m_counter_low : constant is 1;
attribute mti_svvh_generic_type of pll_m_counter_ph_mux_prst : constant is 1;
attribute mti_svvh_generic_type of pll_m_counter_prst : constant is 1;
attribute mti_svvh_generic_type of pll_n_counter_bypass_en : constant is 1;
attribute mti_svvh_generic_type of pll_n_counter_high : constant is 1;
attribute mti_svvh_generic_type of pll_n_counter_low : constant is 1;
attribute mti_svvh_generic_type of pll_n_counter_odd_div_duty_en : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel : constant is 1;
attribute mti_svvh_generic_type of pll_dft_vco_ph0_en : constant is 1;
attribute mti_svvh_generic_type of pll_dft_vco_ph1_en : constant is 1;
attribute mti_svvh_generic_type of pll_dft_vco_ph2_en : constant is 1;
attribute mti_svvh_generic_type of pll_dft_vco_ph3_en : constant is 1;
attribute mti_svvh_generic_type of pll_dft_vco_ph4_en : constant is 1;
attribute mti_svvh_generic_type of pll_dft_vco_ph5_en : constant is 1;
attribute mti_svvh_generic_type of pll_dft_vco_ph6_en : constant is 1;
attribute mti_svvh_generic_type of pll_dft_vco_ph7_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en : constant is 1;
end twentynm_iopll_ip;
|
mit
|
6104de53a91c4d23d188891192b1ffc8
| 0.635269 | 3.130833 | false | false | false | false |
jandecaluwe/myhdl
|
example/manual/rom.vhd
| 13 | 663 |
-- File: rom.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:39 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity rom is
port (
dout: out unsigned(7 downto 0);
addr: in unsigned(3 downto 0)
);
end entity rom;
-- ROM model
architecture MyHDL of rom is
begin
ROM_READ: process (addr) is
begin
case to_integer(addr) is
when 0 => dout <= "00010001";
when 1 => dout <= "10000110";
when 2 => dout <= "00110100";
when others => dout <= "00001001";
end case;
end process ROM_READ;
end architecture MyHDL;
|
lgpl-2.1
|
e8a64ab5a857617b817ceb5557287730
| 0.61991 | 3.298507 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNCPEUNC4M.vhd
| 5 | 879 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCPEUNC4M is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCPEUNC4M is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 16 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(15 downto 0) => input,
xin(16) => '0', yout => output
);
end architecture;
|
mit
|
df1d80da5870ac0e4d0e9ab6644ae7f7
| 0.649602 | 3.09507 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNNZHXLS76.vhd
| 8 | 879 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNNZHXLS76 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNNZHXLS76 is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 16,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture;
|
mit
|
bf6ac4b400670b11eaa84c9f51175ca6
| 0.649602 | 3.117021 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_if_statement_GNMQPB5LUF.vhd
| 4 | 1,509 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNMQPB5LUF is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "((a>b) or (a=b)) and ((a<c) or (a=c))";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNMQPB5LUF is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(((a>b) or (a=b)) and ((a<c) or (a=c))) ;
true <= result;
end architecture;
|
mit
|
c2d8d5f0a56bc2f66def20b69dbf3f4d
| 0.612326 | 3.14375 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/Modules/Program Counter.vhd
| 1 | 907 |
--Author: Daniel Noyes
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.UMDRISC_pkg.ALL;
entity pcounter is
generic (regSize : integer:= BITREG_16);
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PC_En : in STD_LOGIC;
PROGRAM_COUNTER : out STD_LOGIC_VECTOR (regSize-1 downto 0)
);
end pcounter;
architecture Behavioral of pcounter is
signal PC : std_logic_vector(regSize-1 downto 0):= (others => '0'); --<= (others <= "0"); -- Program Counter
begin
process (CLK, RST)
begin
if (RST = '1') then
PC <= (OTHERS => '0');
elsif CLK = '0' and CLK'event then
if PC_En = '1' then
if PC = B"11111" then --MEM_LIMIT) then --going to need to change this line
PC <= (OTHERS => '0');
else
PC <= PC + 1;
end if;
end if;
end if;
end process;
PROGRAM_COUNTER <= PC;
end Behavioral;
|
mit
|
e5dfefb31a1bcef9f7f37088d972ac62
| 0.624035 | 2.790769 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/RAM_3.vhd
| 1 | 10,399 |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_3.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM_3 IS
PORT
(
aclr : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END RAM_3;
ARCHITECTURE SYN OF ram_3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "RAM_3.mif",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
aclr0 => aclr,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "RAM_3.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_3.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_3.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
85aa72d73862434f55d7fdc9630bafa6
| 0.666314 | 3.290823 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_if_statement_GNTVBNRAAT.vhd
| 4 | 1,463 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNTVBNRAAT is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a=b) or (a=c)";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNTVBNRAAT is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a=b) or (a=c)) ;
true <= result;
end architecture;
|
mit
|
34954e37492c57adbd7e132d790cff0f
| 0.619275 | 3.243902 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sImpulsen1Altr.vhd
| 8 | 3,102 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulsen1Altr is
generic (
Impulsedelay : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulsen1Altr ;
architecture syn of alt_dspbuilder_sImpulsen1Altr is
type States_ImpulseAltr is (sclear, slow, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsedelay)-1) downto 0);
begin
rp:process(clock,aclr)
begin
if aclr='1' then
count <= (others=>'0');
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
count <= (others=>'0');
current_state <= sclear;
elsif (ena='1') then
count <= count+int2ustd(1,nbitnecessary(Impulsedelay));
current_state <= next_state;
end if;
end if;
end process;
cp:process(count, current_state, sclr,ena)
begin
case current_state is
when sclear =>
q <= '0';
if (ena='1') and (sclr='0') then
next_state <= slow;
else
next_state <= sclear;
end if;
when slow =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsedelay-1,nbitnecessary(Impulsedelay))) and (ena='1') then
next_state <= shigh;
else
next_state <= slow ;
end if;
when shigh =>
q <= '1';
if (sclr='1') then
next_state <= sclear;
elsif (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
|
mit
|
b48345dbcf51eaecf4075e1309382f76
| 0.609607 | 3.755448 | false | false | false | false |
cathalmccabe/PYNQ
|
boards/ip/audio_codec_ctrl_v1.0/src/i2s_ctrl.vhd
| 4 | 16,925 |
------------------------------------------------------------------------------
-- i2s_ctrl.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: i2s_ctrl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Aug 15 18:20:40 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- Added CODEC_ADDRESS as output port driven by Generics. Value can be changed
-- by configuring the IP
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.common_types.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity i2s_ctrl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_CODEC_ADDRESS : std_logic_vector := B"11";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
codec_address : out std_logic_vector(1 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity i2s_ctrl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of i2s_ctrl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 5;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity work.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity work.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
BCLK => BCLK,
LRCLK => LRCLK,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
codec_address <= C_CODEC_ADDRESS;
end IMP;
|
bsd-3-clause
|
ebb13356a1e76de5660a8cfdfce6cff1
| 0.454121 | 4.232308 | false | false | false | false |
lelongdunet/dspunit
|
sim/bench_dspunit.vhd
| 2 | 12,003 |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity bench_dspunit is
end bench_dspunit;
--=----------------------------------------------------------------------------
architecture archi_bench_dspunit of bench_dspunit is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspunit
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
debug : out std_logic_vector(15 downto 0);
irq : out std_logic;
op_done : out std_logic
);
end component;
component gen_memoryf
generic (
addr_width : natural;
data_width : natural;
init_file : string
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component gen_memory
generic (
addr_width : natural;
data_width : natural
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data_in_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_r_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_addr_w_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m0 : std_logic;
signal s_c_en_m0 : std_logic;
signal s_data_in_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m1 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m1 : std_logic;
signal s_c_en_m1 : std_logic;
signal s_data_in_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m2 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m2 : std_logic;
signal s_c_en_m2 : std_logic;
signal s_addr_cmdreg : std_logic_vector((cmdreg_addr_width - 1) downto 0);
signal s_data_in_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_wr_en_cmdreg : std_logic;
signal s_data_out_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_op_done : std_logic;
signal s_debug_dsp : std_logic_vector(15 downto 0);
signal s_irq : std_logic;
begin -- archs_bench_dspunit
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspunit_1 : dspunit
port map (
clk => s_clk,
clk_cpu => s_clk,
reset => s_reset,
data_in_m0 => s_data_in_m0,
data_out_m0 => s_data_out_m0,
addr_r_m0 => s_addr_r_m0,
addr_w_m0 => s_addr_w_m0,
wr_en_m0 => s_wr_en_m0,
c_en_m0 => s_c_en_m0,
data_in_m1 => s_data_in_m1,
data_out_m1 => s_data_out_m1,
addr_m1 => s_addr_m1,
wr_en_m1 => s_wr_en_m1,
c_en_m1 => s_c_en_m1,
data_in_m2 => s_data_in_m2,
data_out_m2 => s_data_out_m2,
addr_m2 => s_addr_m2,
wr_en_m2 => s_wr_en_m2,
c_en_m2 => s_c_en_m2,
addr_cmdreg => s_addr_cmdreg,
data_in_cmdreg => s_data_in_cmdreg,
wr_en_cmdreg => s_wr_en_cmdreg,
data_out_cmdreg => s_data_out_cmdreg,
debug => s_debug_dsp,
irq => s_irq,
op_done => s_op_done);
gen_memory_1 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
-- init_file => "exsig.mif")
init_file => "exsig_fft.mif")
-- init_file => "Ones.mif")
port map (
address_a => s_addr_r_m0,
address_b => s_addr_w_m0,
clock_a => s_clk,
clock_b => s_clk,
data_a => (others => '0'),
data_b => s_data_out_m0,
wren_a => '0',
wren_b => s_wr_en_m0,
q_a => s_data_in_m0,
q_b => open);
gen_memory_2 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "exsig_fft.mif")
port map (
address_a => s_addr_m1,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m1,
data_b => (others => '0'),
wren_a => s_wr_en_m1,
wren_b => '0',
q_a => s_data_in_m1,
q_b => open);
gen_memory_3 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m2,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m2,
data_b => (others => '0'),
wren_a => s_wr_en_m2,
wren_b => '0',
q_a => s_data_in_m2,
q_b => open);
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_addr_cmdreg <= "0000", "0100" after 141 ns, "0010" after 151 ns, "0111" after 161 ns, "1000" after 171 ns,
-- "0010" after 8751 ns, "0111" after 8761 ns, "1000" after 8771 ns,
"0100" after 241 ns, "0010" after 251 ns, "0111" after 261 ns, "1000" after 271 ns,
"0001" after 321 ns,
"0010" after 341 ns, "0100" after 351 ns, "0111" after 361 ns, "1000" after 371 ns,
"0100" after 461 ns, "0010" after 471 ns, "0111" after 481 ns, "1000" after 491 ns,
"0010" after 541 ns, "0100" after 551 ns, "0111" after 561 ns, "1000" after 571 ns,
"0100" after 661 ns, "0010" after 671 ns, "0111" after 681 ns, "1000" after 691 ns;
s_data_in_cmdreg <= x"0000", x"003F" after 141 ns, x"0040" after 151 ns, x"003C" after 161 ns, x"0002" after 171 ns, -- ifft bitrev
-- x"003F" after 8751 ns, x"002D" after 8761 ns, x"0002" after 8771 ns, -- dotcmul bitrev
-- sigshift is not available any more
-- x"0072" after 241 ns, x"0080" after 251 ns, x"0026" after 261 ns, x"0002" after 271 ns, -- sigshift bitrev
x"0080" after 321 ns,
x"0040" after 341 ns, x"000F" after 351 ns, x"000C" after 361 ns, x"0002" after 371 ns, -- fft
x"0040" after 461 ns, x"0040" after 471 ns, x"000D" after 481 ns, x"000A" after 491 ns, -- dotcmul
x"0040" after 541 ns, x"000A" after 551 ns, x"003C" after 561 ns, x"0002" after 571 ns, -- ifft bitrev
x"0040" after 661 ns, x"0040" after 671 ns, x"002D" after 681 ns, x"0002" after 691 ns; -- dotcmul bitrev
s_wr_en_cmdreg <= '0', '1' after 141 ns, '0' after 181 ns,
'1' after 241 ns, '0' after 281 ns,
'1' after 321 ns, '0' after 331 ns,
'1' after 341 ns, '0' after 381 ns,
'1' after 461 ns, '0' after 501 ns,
'1' after 541 ns, '0' after 581 ns,
'1' after 661 ns, '0' after 701 ns;
end archi_bench_dspunit;
-------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=35000ns
-->SIMSAVFILE=debugfft.sav
-------------------------------------------------------------------------------
|
gpl-3.0
|
cb3bb028eab57d3c1365e1ea1aa44239
| 0.475215 | 3.432371 | false | false | false | false |
nulldozer/purisc
|
Global_memory/MAGIC_global/FLOW_global.vhd
| 2 | 4,527 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FLOW_global is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ROW_A : IN STD_LOGIC_VECTOR(11 downto 0);
ROW_B : IN STD_LOGIC_VECTOR(11 downto 0);
ROW_C : IN STD_LOGIC_VECTOR(11 downto 0);
ROW_D : IN STD_LOGIC_VECTOR(11 downto 0);
ROW_E : IN STD_LOGIC_VECTOR(11 downto 0);
ROW_W : IN STD_LOGIC_VECTOR(11 downto 0);
HAZARD : IN STD_LOGIC;
EQUALITY : OUT STD_LOGIC;
ADDRESS_A : OUT STD_LOGIC_VECTOR(11 downto 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR(11 downto 0);
SEL_VECTOR : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
WREN_A : OUT STD_LOGIC;
WREN_B : OUT STD_LOGIC
);
end;
architecture flow of FLOW_global is
component SELECTOR_global
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
EQUALITY : OUT STD_LOGIC;
sel_A_0 : OUT STD_LOGIC;
sel_B_0 : OUT STD_LOGIC;
sel_C_0 : OUT STD_LOGIC;
sel_D_0 : OUT STD_LOGIC;
sel_E_0 : OUT STD_LOGIC;
sel_W_0 : OUT STD_LOGIC;
sel_A_1 : OUT STD_LOGIC;
sel_B_1 : OUT STD_LOGIC;
sel_C_1 : OUT STD_LOGIC;
sel_D_1 : OUT STD_LOGIC;
sel_E_1 : OUT STD_LOGIC;
sel_W_1 : OUT STD_LOGIC
);
end component;
component tristate_global
PORT(
my_in : in std_logic_vector(11 downto 0);
sel : in std_logic;
my_out : out std_logic_vector(11 downto 0)
);
end component;
signal sel_a0 : std_logic;
signal sel_b0 : std_logic;
signal sel_c0 : std_logic;
signal sel_d0 : std_logic;
signal sel_e0 : std_logic;
signal sel_w0 : std_logic;
signal sel_a1 : std_logic;
signal sel_b1 : std_logic;
signal sel_c1 : std_logic;
signal sel_d1 : std_logic;
signal sel_e1 : std_logic;
signal sel_w1 : std_logic;
begin
select_address : SELECTOR_global PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE,
EQUALITY => EQUALITY,
SEL_A_0 => sel_a0,
SEL_B_0 => sel_b0,
SEL_C_0 => sel_c0,
SEL_D_0 => sel_d0,
SEL_E_0 => sel_e0,
SEL_W_0 => sel_w0,
SEL_A_1 => sel_a1,
SEL_B_1 => sel_b1,
SEL_C_1 => sel_c1,
SEL_D_1 => sel_d1,
SEL_E_1 => sel_e1,
SEL_W_1 => sel_w1
);
TRI_0_PORT_A : tristate_global PORT MAP (
my_in => ROW_A,
sel => sel_a0,
my_out => ADDRESS_A
);
TRI_1_PORT_A : tristate_global PORT MAP (
my_in => ROW_B,
sel => sel_b0,
my_out => ADDRESS_A
);
TRI_2_PORT_A : tristate_global PORT MAP (
my_in => ROW_C,
sel => sel_c0,
my_out => ADDRESS_A
);
TRI_3_PORT_A : tristate_global PORT MAP (
my_in => ROW_D,
sel => sel_d0,
my_out => ADDRESS_A
);
TRI_4_PORT_A : tristate_global PORT MAP (
my_in => ROW_E,
sel => sel_e0,
my_out => ADDRESS_A
);
TRI_5_PORT_A : tristate_global PORT MAP (
my_in => ROW_W,
sel => sel_w0,
my_out => ADDRESS_A
);
TRI_0_PORT_B : tristate_global PORT MAP (
my_in => ROW_A,
sel => sel_a1,
my_out => ADDRESS_B
);
TRI_1_PORT_B : tristate_global PORT MAP (
my_in => ROW_B,
sel => sel_b1,
my_out => ADDRESS_B
);
TRI_2_PORT_B : tristate_global PORT MAP (
my_in => ROW_C,
sel => sel_c1,
my_out => ADDRESS_B
);
TRI_3_PORT_B : tristate_global PORT MAP (
my_in => ROW_D,
sel => sel_d1,
my_out => ADDRESS_B
);
TRI_4_PORT_B : tristate_global PORT MAP (
my_in => ROW_E,
sel => sel_e1,
my_out => ADDRESS_B
);
TRI_5_PORT_B : tristate_global PORT MAP (
my_in => ROW_W,
sel => sel_w1,
my_out => ADDRESS_B
);
WREN_A <= '0';
process (HAZARD, OPCODE) begin --addred this if block
if (HAZARD = '1') then
WREN_B <= '0';
else
WREN_B <= OPCODE(0); --used to be just this line
end if;
end process;
SEL_VECTOR <= sel_a0 & sel_a1 & sel_b0 & sel_b1 & sel_c0 & sel_c1 & sel_d0 & sel_d1 & sel_e0 & sel_e1;
end;
|
gpl-2.0
|
7018de8d96338700279ffff32605e8c7
| 0.497239 | 2.820561 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/altera_arriavgz_pll/_primary.vhd
| 5 | 70,300 |
library verilog;
use verilog.vl_types.all;
entity altera_arriavgz_pll is
generic(
number_of_counters: integer := 18;
number_of_fplls : integer := 1;
number_of_extclks: integer := 4;
number_of_dlls : integer := 2;
number_of_lvds : integer := 4;
pll_auto_clk_sw_en_0: string := "false";
pll_clk_loss_edge_0: string := "both_edges";
pll_clk_loss_sw_en_0: string := "false";
pll_clk_sw_dly_0: integer := 0;
pll_clkin_0_src_0: string := "clk_0";
pll_clkin_1_src_0: string := "clk_0";
pll_manu_clk_sw_en_0: string := "false";
pll_sw_refclk_src_0: string := "clk_0";
pll_auto_clk_sw_en_1: string := "false";
pll_clk_loss_edge_1: string := "both_edges";
pll_clk_loss_sw_en_1: string := "false";
pll_clk_sw_dly_1: integer := 0;
pll_clkin_0_src_1: string := "clk_1";
pll_clkin_1_src_1: string := "clk_1";
pll_manu_clk_sw_en_1: string := "false";
pll_sw_refclk_src_1: string := "clk_1";
pll_output_clock_frequency_0: string := "700.0 MHz";
reference_clock_frequency_0: string := "700.0 MHz";
mimic_fbclk_type_0: string := "gclk";
dsm_accumulator_reset_value_0: integer := 0;
forcelock_0 : string := "false";
nreset_invert_0 : string := "false";
pll_atb_0 : integer := 0;
pll_bwctrl_0 : integer := 1000;
pll_cmp_buf_dly_0: string := "0 ps";
pll_cp_comp_0 : string := "true";
pll_cp_current_0: integer := 20;
pll_ctrl_override_setting_0: string := "true";
pll_dsm_dither_0: string := "disable";
pll_dsm_out_sel_0: string := "disable";
pll_dsm_reset_0 : string := "false";
pll_ecn_bypass_0: string := "false";
pll_ecn_test_en_0: string := "false";
pll_enable_0 : string := "true";
pll_fbclk_mux_1_0: string := "fb";
pll_fbclk_mux_2_0: string := "m_cnt";
pll_fractional_carry_out_0: integer := 24;
pll_fractional_division_0: integer := 1;
pll_fractional_value_ready_0: string := "true";
pll_lf_testen_0 : string := "false";
pll_lock_fltr_cfg_0: integer := 25;
pll_lock_fltr_test_0: string := "false";
pll_m_cnt_bypass_en_0: string := "false";
pll_m_cnt_coarse_dly_0: string := "0 ps";
pll_m_cnt_fine_dly_0: string := "0 ps";
pll_m_cnt_hi_div_0: integer := 3;
pll_m_cnt_in_src_0: string := "ph_mux_clk";
pll_m_cnt_lo_div_0: integer := 3;
pll_m_cnt_odd_div_duty_en_0: string := "false";
pll_m_cnt_ph_mux_prst_0: integer := 0;
pll_m_cnt_prst_0: integer := 256;
pll_n_cnt_bypass_en_0: string := "true";
pll_n_cnt_coarse_dly_0: string := "0 ps";
pll_n_cnt_fine_dly_0: string := "0 ps";
pll_n_cnt_hi_div_0: integer := 1;
pll_n_cnt_lo_div_0: integer := 1;
pll_n_cnt_odd_div_duty_en_0: string := "false";
pll_ref_buf_dly_0: string := "0 ps";
pll_reg_boost_0 : integer := 0;
pll_regulator_bypass_0: string := "false";
pll_ripplecap_ctrl_0: integer := 0;
pll_slf_rst_0 : string := "false";
pll_tclk_mux_en_0: string := "false";
pll_tclk_sel_0 : string := "n_src";
pll_test_enable_0: string := "false";
pll_testdn_enable_0: string := "false";
pll_testup_enable_0: string := "false";
pll_unlock_fltr_cfg_0: integer := 1;
pll_vco_div_0 : integer := 0;
pll_vco_ph0_en_0: string := "true";
pll_vco_ph1_en_0: string := "true";
pll_vco_ph2_en_0: string := "true";
pll_vco_ph3_en_0: string := "true";
pll_vco_ph4_en_0: string := "true";
pll_vco_ph5_en_0: string := "true";
pll_vco_ph6_en_0: string := "true";
pll_vco_ph7_en_0: string := "true";
pll_vctrl_test_voltage_0: integer := 750;
vccd0g_atb_0 : string := "disable";
vccd0g_output_0 : integer := 0;
vccd1g_atb_0 : string := "disable";
vccd1g_output_0 : integer := 0;
vccm1g_tap_0 : integer := 2;
vccr_pd_0 : string := "false";
vcodiv_override_0: string := "false";
sim_use_fast_model_0: string := "false";
pll_output_clock_frequency_1: string := "300.0 MHz";
reference_clock_frequency_1: string := "100.0 MHz";
mimic_fbclk_type_1: string := "gclk";
dsm_accumulator_reset_value_1: integer := 0;
forcelock_1 : string := "false";
nreset_invert_1 : string := "false";
pll_atb_1 : integer := 0;
pll_bwctrl_1 : integer := 1000;
pll_cmp_buf_dly_1: string := "0 ps";
pll_cp_comp_1 : string := "true";
pll_cp_current_1: integer := 30;
pll_ctrl_override_setting_1: string := "false";
pll_dsm_dither_1: string := "disable";
pll_dsm_out_sel_1: string := "disable";
pll_dsm_reset_1 : string := "false";
pll_ecn_bypass_1: string := "false";
pll_ecn_test_en_1: string := "false";
pll_enable_1 : string := "false";
pll_fbclk_mux_1_1: string := "glb";
pll_fbclk_mux_2_1: string := "fb_1";
pll_fractional_carry_out_1: integer := 24;
pll_fractional_division_1: integer := 1;
pll_fractional_value_ready_1: string := "true";
pll_lf_testen_1 : string := "false";
pll_lock_fltr_cfg_1: integer := 25;
pll_lock_fltr_test_1: string := "false";
pll_m_cnt_bypass_en_1: string := "false";
pll_m_cnt_coarse_dly_1: string := "0 ps";
pll_m_cnt_fine_dly_1: string := "0 ps";
pll_m_cnt_hi_div_1: integer := 2;
pll_m_cnt_in_src_1: string := "ph_mux_clk";
pll_m_cnt_lo_div_1: integer := 1;
pll_m_cnt_odd_div_duty_en_1: string := "true";
pll_m_cnt_ph_mux_prst_1: integer := 0;
pll_m_cnt_prst_1: integer := 256;
pll_n_cnt_bypass_en_1: string := "true";
pll_n_cnt_coarse_dly_1: string := "0 ps";
pll_n_cnt_fine_dly_1: string := "0 ps";
pll_n_cnt_hi_div_1: integer := 256;
pll_n_cnt_lo_div_1: integer := 256;
pll_n_cnt_odd_div_duty_en_1: string := "false";
pll_ref_buf_dly_1: string := "0 ps";
pll_reg_boost_1 : integer := 0;
pll_regulator_bypass_1: string := "false";
pll_ripplecap_ctrl_1: integer := 0;
pll_slf_rst_1 : string := "false";
pll_tclk_mux_en_1: string := "false";
pll_tclk_sel_1 : string := "n_src";
pll_test_enable_1: string := "false";
pll_testdn_enable_1: string := "false";
pll_testup_enable_1: string := "false";
pll_unlock_fltr_cfg_1: integer := 2;
pll_vco_div_1 : integer := 1;
pll_vco_ph0_en_1: string := "true";
pll_vco_ph1_en_1: string := "true";
pll_vco_ph2_en_1: string := "true";
pll_vco_ph3_en_1: string := "true";
pll_vco_ph4_en_1: string := "true";
pll_vco_ph5_en_1: string := "true";
pll_vco_ph6_en_1: string := "true";
pll_vco_ph7_en_1: string := "true";
pll_vctrl_test_voltage_1: integer := 750;
vccd0g_atb_1 : string := "disable";
vccd0g_output_1 : integer := 0;
vccd1g_atb_1 : string := "disable";
vccd1g_output_1 : integer := 0;
vccm1g_tap_1 : integer := 2;
vccr_pd_1 : string := "false";
vcodiv_override_1: string := "false";
sim_use_fast_model_1: string := "false";
output_clock_frequency_0: string := "100.0 MHz";
enable_output_counter_0: string := "true";
phase_shift_0 : string := "0 ps";
duty_cycle_0 : integer := 50;
c_cnt_coarse_dly_0: string := "0 ps";
c_cnt_fine_dly_0: string := "0 ps";
c_cnt_in_src_0 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_0: integer := 0;
c_cnt_prst_0 : integer := 1;
cnt_fpll_src_0 : string := "fpll_0";
dprio0_cnt_bypass_en_0: string := "true";
dprio0_cnt_hi_div_0: integer := 3;
dprio0_cnt_lo_div_0: integer := 3;
dprio0_cnt_odd_div_even_duty_en_0: string := "false";
dprio1_cnt_bypass_en_0: vl_notype;
dprio1_cnt_hi_div_0: vl_notype;
dprio1_cnt_lo_div_0: vl_notype;
dprio1_cnt_odd_div_even_duty_en_0: vl_notype;
output_clock_frequency_1: string := "0 ps";
enable_output_counter_1: string := "true";
phase_shift_1 : string := "0 ps";
duty_cycle_1 : integer := 50;
c_cnt_coarse_dly_1: string := "0 ps";
c_cnt_fine_dly_1: string := "0 ps";
c_cnt_in_src_1 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_1: integer := 0;
c_cnt_prst_1 : integer := 1;
cnt_fpll_src_1 : string := "fpll_0";
dprio0_cnt_bypass_en_1: string := "true";
dprio0_cnt_hi_div_1: integer := 2;
dprio0_cnt_lo_div_1: integer := 1;
dprio0_cnt_odd_div_even_duty_en_1: string := "true";
dprio1_cnt_bypass_en_1: vl_notype;
dprio1_cnt_hi_div_1: vl_notype;
dprio1_cnt_lo_div_1: vl_notype;
dprio1_cnt_odd_div_even_duty_en_1: vl_notype;
output_clock_frequency_2: string := "0 ps";
enable_output_counter_2: string := "true";
phase_shift_2 : string := "0 ps";
duty_cycle_2 : integer := 50;
c_cnt_coarse_dly_2: string := "0 ps";
c_cnt_fine_dly_2: string := "0 ps";
c_cnt_in_src_2 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_2: integer := 0;
c_cnt_prst_2 : integer := 1;
cnt_fpll_src_2 : string := "fpll_0";
dprio0_cnt_bypass_en_2: string := "true";
dprio0_cnt_hi_div_2: integer := 1;
dprio0_cnt_lo_div_2: integer := 1;
dprio0_cnt_odd_div_even_duty_en_2: string := "false";
dprio1_cnt_bypass_en_2: vl_notype;
dprio1_cnt_hi_div_2: vl_notype;
dprio1_cnt_lo_div_2: vl_notype;
dprio1_cnt_odd_div_even_duty_en_2: vl_notype;
output_clock_frequency_3: string := "0 ps";
enable_output_counter_3: string := "true";
phase_shift_3 : string := "0 ps";
duty_cycle_3 : integer := 50;
c_cnt_coarse_dly_3: string := "0 ps";
c_cnt_fine_dly_3: string := "0 ps";
c_cnt_in_src_3 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_3: integer := 0;
c_cnt_prst_3 : integer := 1;
cnt_fpll_src_3 : string := "fpll_0";
dprio0_cnt_bypass_en_3: string := "false";
dprio0_cnt_hi_div_3: integer := 1;
dprio0_cnt_lo_div_3: integer := 1;
dprio0_cnt_odd_div_even_duty_en_3: string := "false";
dprio1_cnt_bypass_en_3: vl_notype;
dprio1_cnt_hi_div_3: vl_notype;
dprio1_cnt_lo_div_3: vl_notype;
dprio1_cnt_odd_div_even_duty_en_3: vl_notype;
output_clock_frequency_4: string := "0 ps";
enable_output_counter_4: string := "true";
phase_shift_4 : string := "0 ps";
duty_cycle_4 : integer := 50;
c_cnt_coarse_dly_4: string := "0 ps";
c_cnt_fine_dly_4: string := "0 ps";
c_cnt_in_src_4 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_4: integer := 0;
c_cnt_prst_4 : integer := 1;
cnt_fpll_src_4 : string := "fpll_0";
dprio0_cnt_bypass_en_4: string := "false";
dprio0_cnt_hi_div_4: integer := 1;
dprio0_cnt_lo_div_4: integer := 1;
dprio0_cnt_odd_div_even_duty_en_4: string := "false";
dprio1_cnt_bypass_en_4: vl_notype;
dprio1_cnt_hi_div_4: vl_notype;
dprio1_cnt_lo_div_4: vl_notype;
dprio1_cnt_odd_div_even_duty_en_4: vl_notype;
output_clock_frequency_5: string := "0 ps";
enable_output_counter_5: string := "true";
phase_shift_5 : string := "0 ps";
duty_cycle_5 : integer := 50;
c_cnt_coarse_dly_5: string := "0 ps";
c_cnt_fine_dly_5: string := "0 ps";
c_cnt_in_src_5 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_5: integer := 0;
c_cnt_prst_5 : integer := 1;
cnt_fpll_src_5 : string := "fpll_0";
dprio0_cnt_bypass_en_5: string := "false";
dprio0_cnt_hi_div_5: integer := 1;
dprio0_cnt_lo_div_5: integer := 1;
dprio0_cnt_odd_div_even_duty_en_5: string := "false";
dprio1_cnt_bypass_en_5: vl_notype;
dprio1_cnt_hi_div_5: vl_notype;
dprio1_cnt_lo_div_5: vl_notype;
dprio1_cnt_odd_div_even_duty_en_5: vl_notype;
output_clock_frequency_6: string := "0 ps";
enable_output_counter_6: string := "true";
phase_shift_6 : string := "0 ps";
duty_cycle_6 : integer := 50;
c_cnt_coarse_dly_6: string := "0 ps";
c_cnt_fine_dly_6: string := "0 ps";
c_cnt_in_src_6 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_6: integer := 0;
c_cnt_prst_6 : integer := 1;
cnt_fpll_src_6 : string := "fpll_0";
dprio0_cnt_bypass_en_6: string := "false";
dprio0_cnt_hi_div_6: integer := 1;
dprio0_cnt_lo_div_6: integer := 1;
dprio0_cnt_odd_div_even_duty_en_6: string := "false";
dprio1_cnt_bypass_en_6: vl_notype;
dprio1_cnt_hi_div_6: vl_notype;
dprio1_cnt_lo_div_6: vl_notype;
dprio1_cnt_odd_div_even_duty_en_6: vl_notype;
output_clock_frequency_7: string := "0 ps";
enable_output_counter_7: string := "true";
phase_shift_7 : string := "0 ps";
duty_cycle_7 : integer := 50;
c_cnt_coarse_dly_7: string := "0 ps";
c_cnt_fine_dly_7: string := "0 ps";
c_cnt_in_src_7 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_7: integer := 0;
c_cnt_prst_7 : integer := 1;
cnt_fpll_src_7 : string := "fpll_0";
dprio0_cnt_bypass_en_7: string := "false";
dprio0_cnt_hi_div_7: integer := 1;
dprio0_cnt_lo_div_7: integer := 1;
dprio0_cnt_odd_div_even_duty_en_7: string := "false";
dprio1_cnt_bypass_en_7: vl_notype;
dprio1_cnt_hi_div_7: vl_notype;
dprio1_cnt_lo_div_7: vl_notype;
dprio1_cnt_odd_div_even_duty_en_7: vl_notype;
output_clock_frequency_8: string := "0 ps";
enable_output_counter_8: string := "true";
phase_shift_8 : string := "0 ps";
duty_cycle_8 : integer := 50;
c_cnt_coarse_dly_8: string := "0 ps";
c_cnt_fine_dly_8: string := "0 ps";
c_cnt_in_src_8 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_8: integer := 0;
c_cnt_prst_8 : integer := 1;
cnt_fpll_src_8 : string := "fpll_0";
dprio0_cnt_bypass_en_8: string := "false";
dprio0_cnt_hi_div_8: integer := 1;
dprio0_cnt_lo_div_8: integer := 1;
dprio0_cnt_odd_div_even_duty_en_8: string := "false";
dprio1_cnt_bypass_en_8: vl_notype;
dprio1_cnt_hi_div_8: vl_notype;
dprio1_cnt_lo_div_8: vl_notype;
dprio1_cnt_odd_div_even_duty_en_8: vl_notype;
output_clock_frequency_9: string := "0 ps";
enable_output_counter_9: string := "true";
phase_shift_9 : string := "0 ps";
duty_cycle_9 : integer := 50;
c_cnt_coarse_dly_9: string := "0 ps";
c_cnt_fine_dly_9: string := "0 ps";
c_cnt_in_src_9 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_9: integer := 0;
c_cnt_prst_9 : integer := 1;
cnt_fpll_src_9 : string := "fpll_0";
dprio0_cnt_bypass_en_9: string := "false";
dprio0_cnt_hi_div_9: integer := 1;
dprio0_cnt_lo_div_9: integer := 1;
dprio0_cnt_odd_div_even_duty_en_9: string := "false";
dprio1_cnt_bypass_en_9: vl_notype;
dprio1_cnt_hi_div_9: vl_notype;
dprio1_cnt_lo_div_9: vl_notype;
dprio1_cnt_odd_div_even_duty_en_9: vl_notype;
output_clock_frequency_10: string := "0 ps";
enable_output_counter_10: string := "true";
phase_shift_10 : string := "0 ps";
duty_cycle_10 : integer := 50;
c_cnt_coarse_dly_10: string := "0 ps";
c_cnt_fine_dly_10: string := "0 ps";
c_cnt_in_src_10 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_10: integer := 0;
c_cnt_prst_10 : integer := 1;
cnt_fpll_src_10 : string := "fpll_0";
dprio0_cnt_bypass_en_10: string := "false";
dprio0_cnt_hi_div_10: integer := 1;
dprio0_cnt_lo_div_10: integer := 1;
dprio0_cnt_odd_div_even_duty_en_10: string := "false";
dprio1_cnt_bypass_en_10: vl_notype;
dprio1_cnt_hi_div_10: vl_notype;
dprio1_cnt_lo_div_10: vl_notype;
dprio1_cnt_odd_div_even_duty_en_10: vl_notype;
output_clock_frequency_11: string := "0 ps";
enable_output_counter_11: string := "true";
phase_shift_11 : string := "0 ps";
duty_cycle_11 : integer := 50;
c_cnt_coarse_dly_11: string := "0 ps";
c_cnt_fine_dly_11: string := "0 ps";
c_cnt_in_src_11 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_11: integer := 0;
c_cnt_prst_11 : integer := 1;
cnt_fpll_src_11 : string := "fpll_0";
dprio0_cnt_bypass_en_11: string := "false";
dprio0_cnt_hi_div_11: integer := 1;
dprio0_cnt_lo_div_11: integer := 1;
dprio0_cnt_odd_div_even_duty_en_11: string := "false";
dprio1_cnt_bypass_en_11: vl_notype;
dprio1_cnt_hi_div_11: vl_notype;
dprio1_cnt_lo_div_11: vl_notype;
dprio1_cnt_odd_div_even_duty_en_11: vl_notype;
output_clock_frequency_12: string := "0 ps";
enable_output_counter_12: string := "true";
phase_shift_12 : string := "0 ps";
duty_cycle_12 : integer := 50;
c_cnt_coarse_dly_12: string := "0 ps";
c_cnt_fine_dly_12: string := "0 ps";
c_cnt_in_src_12 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_12: integer := 0;
c_cnt_prst_12 : integer := 1;
cnt_fpll_src_12 : string := "fpll_0";
dprio0_cnt_bypass_en_12: string := "false";
dprio0_cnt_hi_div_12: integer := 1;
dprio0_cnt_lo_div_12: integer := 1;
dprio0_cnt_odd_div_even_duty_en_12: string := "false";
dprio1_cnt_bypass_en_12: vl_notype;
dprio1_cnt_hi_div_12: vl_notype;
dprio1_cnt_lo_div_12: vl_notype;
dprio1_cnt_odd_div_even_duty_en_12: vl_notype;
output_clock_frequency_13: string := "0 ps";
enable_output_counter_13: string := "true";
phase_shift_13 : string := "0 ps";
duty_cycle_13 : integer := 50;
c_cnt_coarse_dly_13: string := "0 ps";
c_cnt_fine_dly_13: string := "0 ps";
c_cnt_in_src_13 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_13: integer := 0;
c_cnt_prst_13 : integer := 1;
cnt_fpll_src_13 : string := "fpll_0";
dprio0_cnt_bypass_en_13: string := "false";
dprio0_cnt_hi_div_13: integer := 1;
dprio0_cnt_lo_div_13: integer := 1;
dprio0_cnt_odd_div_even_duty_en_13: string := "false";
dprio1_cnt_bypass_en_13: vl_notype;
dprio1_cnt_hi_div_13: vl_notype;
dprio1_cnt_lo_div_13: vl_notype;
dprio1_cnt_odd_div_even_duty_en_13: vl_notype;
output_clock_frequency_14: string := "0 ps";
enable_output_counter_14: string := "true";
phase_shift_14 : string := "0 ps";
duty_cycle_14 : integer := 50;
c_cnt_coarse_dly_14: string := "0 ps";
c_cnt_fine_dly_14: string := "0 ps";
c_cnt_in_src_14 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_14: integer := 0;
c_cnt_prst_14 : integer := 1;
cnt_fpll_src_14 : string := "fpll_0";
dprio0_cnt_bypass_en_14: string := "false";
dprio0_cnt_hi_div_14: integer := 1;
dprio0_cnt_lo_div_14: integer := 1;
dprio0_cnt_odd_div_even_duty_en_14: string := "false";
dprio1_cnt_bypass_en_14: vl_notype;
dprio1_cnt_hi_div_14: vl_notype;
dprio1_cnt_lo_div_14: vl_notype;
dprio1_cnt_odd_div_even_duty_en_14: vl_notype;
output_clock_frequency_15: string := "0 ps";
enable_output_counter_15: string := "true";
phase_shift_15 : string := "0 ps";
duty_cycle_15 : integer := 50;
c_cnt_coarse_dly_15: string := "0 ps";
c_cnt_fine_dly_15: string := "0 ps";
c_cnt_in_src_15 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_15: integer := 0;
c_cnt_prst_15 : integer := 1;
cnt_fpll_src_15 : string := "fpll_0";
dprio0_cnt_bypass_en_15: string := "false";
dprio0_cnt_hi_div_15: integer := 1;
dprio0_cnt_lo_div_15: integer := 1;
dprio0_cnt_odd_div_even_duty_en_15: string := "false";
dprio1_cnt_bypass_en_15: vl_notype;
dprio1_cnt_hi_div_15: vl_notype;
dprio1_cnt_lo_div_15: vl_notype;
dprio1_cnt_odd_div_even_duty_en_15: vl_notype;
output_clock_frequency_16: string := "0 ps";
enable_output_counter_16: string := "true";
phase_shift_16 : string := "0 ps";
duty_cycle_16 : integer := 50;
c_cnt_coarse_dly_16: string := "0 ps";
c_cnt_fine_dly_16: string := "0 ps";
c_cnt_in_src_16 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_16: integer := 0;
c_cnt_prst_16 : integer := 1;
cnt_fpll_src_16 : string := "fpll_0";
dprio0_cnt_bypass_en_16: string := "false";
dprio0_cnt_hi_div_16: integer := 1;
dprio0_cnt_lo_div_16: integer := 1;
dprio0_cnt_odd_div_even_duty_en_16: string := "false";
dprio1_cnt_bypass_en_16: vl_notype;
dprio1_cnt_hi_div_16: vl_notype;
dprio1_cnt_lo_div_16: vl_notype;
dprio1_cnt_odd_div_even_duty_en_16: vl_notype;
output_clock_frequency_17: string := "0 ps";
enable_output_counter_17: string := "true";
phase_shift_17 : string := "0 ps";
duty_cycle_17 : integer := 50;
c_cnt_coarse_dly_17: string := "0 ps";
c_cnt_fine_dly_17: string := "0 ps";
c_cnt_in_src_17 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_17: integer := 0;
c_cnt_prst_17 : integer := 1;
cnt_fpll_src_17 : string := "fpll_0";
dprio0_cnt_bypass_en_17: string := "false";
dprio0_cnt_hi_div_17: integer := 1;
dprio0_cnt_lo_div_17: integer := 1;
dprio0_cnt_odd_div_even_duty_en_17: string := "false";
dprio1_cnt_bypass_en_17: vl_notype;
dprio1_cnt_hi_div_17: vl_notype;
dprio1_cnt_lo_div_17: vl_notype;
dprio1_cnt_odd_div_even_duty_en_17: vl_notype;
dpa_output_clock_frequency_0: string := "0 ps";
pll_vcoph_div_0 : integer := 1;
dpa_output_clock_frequency_1: string := "0 ps";
pll_vcoph_div_1 : integer := 1;
enable_extclk_output_0: string := "false";
pll_extclk_cnt_src_0: string := "m0_cnt";
pll_extclk_enable_0: string := "true";
pll_extclk_invert_0: string := "false";
enable_extclk_output_1: string := "false";
pll_extclk_cnt_src_1: string := "vss";
pll_extclk_enable_1: string := "true";
pll_extclk_invert_1: string := "false";
enable_extclk_output_2: string := "false";
pll_extclk_cnt_src_2: string := "vss";
pll_extclk_enable_2: string := "true";
pll_extclk_invert_2: string := "false";
enable_extclk_output_3: string := "false";
pll_extclk_cnt_src_3: string := "vss";
pll_extclk_enable_3: string := "true";
pll_extclk_invert_3: string := "false";
enable_dll_output_0: string := "false";
pll_dll_src_value_0: string := "vss";
enable_dll_output_1: string := "false";
pll_dll_src_value_1: string := "vss";
enable_lvds_output_0: string := "false";
pll_loaden_coarse_dly_0: string := "0 ps";
pll_loaden_enable_disable_0: string := "true";
pll_loaden_fine_dly_0: string := "0 ps";
pll_lvdsclk_coarse_dly_0: string := "0 ps";
pll_lvdsclk_enable_disable_0: string := "true";
pll_lvdsclk_fine_dly_0: string := "0 ps";
enable_lvds_output_1: string := "false";
pll_loaden_coarse_dly_1: string := "0 ps";
pll_loaden_enable_disable_1: string := "true";
pll_loaden_fine_dly_1: string := "0 ps";
pll_lvdsclk_coarse_dly_1: string := "0 ps";
pll_lvdsclk_enable_disable_1: string := "true";
pll_lvdsclk_fine_dly_1: string := "0 ps";
enable_lvds_output_2: string := "false";
pll_loaden_coarse_dly_2: string := "0 ps";
pll_loaden_enable_disable_2: string := "true";
pll_loaden_fine_dly_2: string := "0 ps";
pll_lvdsclk_coarse_dly_2: string := "0 ps";
pll_lvdsclk_enable_disable_2: string := "true";
pll_lvdsclk_fine_dly_2: string := "0 ps";
enable_lvds_output_3: string := "false";
pll_loaden_coarse_dly_3: string := "0 ps";
pll_loaden_enable_disable_3: string := "true";
pll_loaden_fine_dly_3: string := "0 ps";
pll_lvdsclk_coarse_dly_3: string := "0 ps";
pll_lvdsclk_enable_disable_3: string := "true";
pll_lvdsclk_fine_dly_3: string := "0 ps"
);
port(
phout_0 : out vl_logic_vector(7 downto 0);
phout_1 : out vl_logic_vector(7 downto 0);
adjpllin : in vl_logic_vector;
cclk : in vl_logic_vector;
coreclkin : in vl_logic_vector;
extswitch : in vl_logic_vector;
iqtxrxclkin : in vl_logic_vector;
plliqclkin : in vl_logic_vector;
rxiqclkin : in vl_logic_vector;
clkin : in vl_logic_vector(3 downto 0);
refiqclk_0 : in vl_logic_vector(1 downto 0);
refiqclk_1 : in vl_logic_vector(1 downto 0);
clk0bad : out vl_logic_vector;
clk1bad : out vl_logic_vector;
pllclksel : out vl_logic_vector;
atpgmode : in vl_logic_vector;
clk : in vl_logic_vector;
fpllcsrtest : in vl_logic_vector;
iocsrclkin : in vl_logic_vector;
iocsrdatain : in vl_logic_vector;
iocsren : in vl_logic_vector;
iocsrrstn : in vl_logic_vector;
mdiodis : in vl_logic_vector;
phaseen : in vl_logic_vector;
read : in vl_logic_vector;
rstn : in vl_logic_vector;
scanen : in vl_logic_vector;
sershiftload : in vl_logic_vector;
shiftdonei : in vl_logic_vector;
updn : in vl_logic_vector;
write : in vl_logic_vector;
addr_0 : in vl_logic_vector(5 downto 0);
addr_1 : in vl_logic_vector(5 downto 0);
byteen_0 : in vl_logic_vector(1 downto 0);
byteen_1 : in vl_logic_vector(1 downto 0);
cntsel_0 : in vl_logic_vector(4 downto 0);
cntsel_1 : in vl_logic_vector(4 downto 0);
din_0 : in vl_logic_vector(15 downto 0);
din_1 : in vl_logic_vector(15 downto 0);
blockselect : out vl_logic_vector;
iocsrdataout : out vl_logic_vector;
iocsrenbuf : out vl_logic_vector;
iocsrrstnbuf : out vl_logic_vector;
phasedone : out vl_logic_vector;
dout_0 : out vl_logic_vector(15 downto 0);
dout_1 : out vl_logic_vector(15 downto 0);
dprioout_0 : out vl_logic_vector(815 downto 0);
dprioout_1 : out vl_logic_vector(815 downto 0);
fbclkfpll : in vl_logic_vector;
lvdfbin : in vl_logic_vector;
nresync : in vl_logic_vector;
pfden : in vl_logic_vector;
shiften_fpll : in vl_logic_vector;
zdb : in vl_logic_vector;
fblvdsout : out vl_logic_vector;
lock : out vl_logic_vector;
mcntout : out vl_logic_vector;
plniotribuf : out vl_logic_vector;
clken : in vl_logic_vector;
extclk : out vl_logic_vector;
dll_clkin : in vl_logic_vector;
clkout : out vl_logic_vector;
loaden : out vl_logic_vector;
lvdsclk : out vl_logic_vector;
divclk : out vl_logic_vector;
cascade_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_counters : constant is 1;
attribute mti_svvh_generic_type of number_of_fplls : constant is 1;
attribute mti_svvh_generic_type of number_of_extclks : constant is 1;
attribute mti_svvh_generic_type of number_of_dlls : constant is 1;
attribute mti_svvh_generic_type of number_of_lvds : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_0 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_0 : constant is 1;
attribute mti_svvh_generic_type of forcelock_0 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_0 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_0 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_0 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_0 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_0 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_0 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_0 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_1 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_1 : constant is 1;
attribute mti_svvh_generic_type of forcelock_1 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_1 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_1 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_1 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_1 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_1 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_1 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_1 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_0 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_0 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_0 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_1 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_1 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_1 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_2 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_2 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_2 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_2 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_2 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_3 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_3 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_3 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_3 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_3 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_4 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_4 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_4 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_4 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_4 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_5 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_5 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_5 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_5 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_5 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_6 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_6 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_6 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_6 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_6 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_7 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_7 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_7 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_7 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_7 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_8 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_8 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_8 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_8 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_8 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_9 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_9 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_9 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_9 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_9 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_10 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_10 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_10 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_10 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_10 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_11 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_11 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_11 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_11 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_11 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_12 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_12 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_12 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_12 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_12 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_13 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_13 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_13 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_13 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_13 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_14 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_14 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_14 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_14 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_14 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_15 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_15 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_15 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_15 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_15 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_16 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_16 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_16 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_16 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_16 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_17 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_17 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_17 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_17 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_17 : constant is 3;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_0 : constant is 1;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_0 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_2 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_3 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_0 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_3 : constant is 1;
end altera_arriavgz_pll;
|
mit
|
69e028c7b2c7eef7e47daa0b0ea76ddf
| 0.64377 | 3.061713 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/terminal_pkg.vhd
| 1 | 305,110 |
---------------------------------------------------------------
-- Title : Package for simulation terminal
-- Project : -
---------------------------------------------------------------
-- File : terminal_pkg.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 22/09/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- Revision 1.4 2017/06/13 07:00:00 mmiehling
-- reworked comments in vme_dma_sram2a32d64
--
-- Revision 1.3 2013/07/15 13:14:22 mmiehling
-- adopted testcases
--
-- Revision 1.2 2013/04/18 15:11:10 MMiehling
-- rework
--
-- Revision 1.1 2012/03/29 10:28:45 MMiehling
-- Initial Revision
--
-- Revision 1.9 2010/08/16 12:57:16 FLenhardt
-- Added an overloaded MTEST which accepts a seed number as an input
--
-- Revision 1.8 2009/01/13 10:57:52 FLenhardt
-- Defined that TGA=2 means configuration access
--
-- Revision 1.7 2008/09/10 17:26:45 MSchindler
-- added flash_mtest_indirect procedure
--
-- Revision 1.6 2007/07/26 07:48:15 FLenhardt
-- Defined usage of TGA
--
-- Revision 1.5 2007/07/18 10:53:34 FLenhardt
-- Fixed bug regarding MTEST printout
--
-- Revision 1.4 2007/07/18 10:28:35 mernst
-- - Changed err to sum up errors instead of setting a specific value
-- - Added dat vector to terminal_in record
--
-- Revision 1.3 2006/08/24 08:52:02 mmiehling
-- changed txt_out to integer
--
-- Revision 1.1 2006/06/23 16:33:04 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/05/12 10:49:17 MMiehling
-- initialization of iram now with mem_init (back)
-- added testcase 14
--
-- Revision 1.1 2006/05/09 16:51:16 MMiehling
-- Initial Revision
--
-- Revision 1.2 2005/10/27 08:35:35 flenhardt
-- Added IRQ to TERMINAL_IN_TYPE record
--
-- Revision 1.1 2005/08/23 15:21:07 MMiehling
-- Initial Revision
--
-- Revision 1.1 2005/07/01 15:47:38 MMiehling
-- Initial Revision
--
-- Revision 1.2 2005/01/31 16:28:59 mmiehling
-- updated
--
-- Revision 1.1 2004/11/16 12:09:07 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
USE work.print_pkg.all;
USE work.vme_sim_pack.all;
USE work.iram32_pkg.all;
USE work.pcie_sim_pkg.ALL;
LIBRARY modelsim_lib;
USE modelsim_lib.util.all;
USE std.textio.all;
PACKAGE terminal_pkg IS
CONSTANT SIM_BAR0 : std_logic_vector(31 DOWNTO 0):= x"0000_0000";
CONSTANT BAR0 : std_logic_vector(31 DOWNTO 0):=x"8000_0000";
CONSTANT BAR1 : std_logic_vector(31 DOWNTO 0):=x"9000_0000";
CONSTANT BAR2 : std_logic_vector(31 DOWNTO 0):= x"a000_0000";
CONSTANT BAR3 : std_logic_vector(31 DOWNTO 0):= x"e000_0000";
CONSTANT BAR4 : std_logic_vector(31 DOWNTO 0):= x"0000_0000";
CONSTANT BAR5 : std_logic_vector(31 DOWNTO 0):= x"0000_0000";
-- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
-- | Chameleon Table | 0 | 0 | 200 | 0 |
-- | 16Z126_SERFLASH | 1 | 200 | 20 | 0 |
-- | 16z002-01 VME | 2 | 10000 | 10000 | 0 |
-- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
-- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
-- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
-- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
-- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
-- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
-- +--------------------------+-----+----------+----------+-----+
CONSTANT VME_REGS : std_logic_vector(31 DOWNTO 0):=x"0001_0000" + BAR0;
CONSTANT VME_IACK : std_logic_vector(31 DOWNTO 0):=x"0001_0100" + BAR0;
CONSTANT VME_A16D16 : std_logic_vector(31 DOWNTO 0):=x"0002_0000" + BAR0;
CONSTANT VME_A16D32 : std_logic_vector(31 DOWNTO 0):=x"0003_0000" + BAR0;
CONSTANT VME_A24D16 : std_logic_vector(31 DOWNTO 0):=x"0000_0000" + BAR2;
CONSTANT VME_A24D32 : std_logic_vector(31 DOWNTO 0):=x"0100_0000" + BAR2;
CONSTANT VME_CRCSR : std_logic_vector(31 DOWNTO 0):=x"0000_0000" + BAR4;
CONSTANT VME_A32D32 : std_logic_vector(31 DOWNTO 0):=x"0000_0000" + BAR3;
CONSTANT SRAM : std_logic_vector(31 DOWNTO 0):=x"0000_0000" + BAR1;
CONSTANT DMA_VME_AM_A16D16_non : std_logic_vector(4 downto 0):="00001";
CONSTANT DMA_VME_AM_A16D16_priv : std_logic_vector(4 downto 0):="10001";
CONSTANT DMA_VME_AM_A16D32_non : std_logic_vector(4 downto 0):="00101";
CONSTANT DMA_VME_AM_A16D32_priv : std_logic_vector(4 downto 0):="10101";
CONSTANT DMA_VME_AM_A24D16_non : std_logic_vector(4 downto 0):="00000";
CONSTANT DMA_VME_AM_A24D16_priv : std_logic_vector(4 downto 0):="10000";
CONSTANT DMA_VME_AM_A24D32_non : std_logic_vector(4 downto 0):="00100";
CONSTANT DMA_VME_AM_A24D32_priv : std_logic_vector(4 downto 0):="10100";
CONSTANT DMA_VME_AM_A24D64_non : std_logic_vector(4 downto 0):="01100";
CONSTANT DMA_VME_AM_A24D64_priv : std_logic_vector(4 downto 0):="11100";
CONSTANT DMA_VME_AM_A32D32_non : std_logic_vector(4 downto 0):="00110";
CONSTANT DMA_VME_AM_A32D32_priv : std_logic_vector(4 downto 0):="10110";
CONSTANT DMA_VME_AM_A32D64_non : std_logic_vector(4 downto 0):="01110";
CONSTANT DMA_VME_AM_A32D64_priv : std_logic_vector(4 downto 0):="11110";
CONSTANT DMA_BLK : std_logic:='0';
CONSTANT DMA_SGL : std_logic:='1';
CONSTANT DMA_DEVICE_SRAM : std_logic_vector(2 downto 0):="001";
CONSTANT DMA_DEVICE_VME : std_logic_vector(2 downto 0):="010";
CONSTANT DMA_DEVICE_PCI : std_logic_vector(2 downto 0):="100";
TYPE terminal_in_type IS record
done : boolean; -- edge indicates end of transfer
busy : std_logic; -- indicates status of master
err : natural; -- number of errors occured
irq : std_logic; -- interrupt request
dat : std_logic_vector(31 DOWNTO 0); -- Input data
END record;
TYPE terminal_out_type IS record
adr : std_logic_vector(31 DOWNTO 0); -- address
tga : std_logic_vector(5 DOWNTO 0); --
dat : std_logic_vector(31 DOWNTO 0); -- write data
wr : natural; -- 0=read, 1=write, 2=wait for numb cycles
typ : natural; -- 0=b, w=1, l=2, dl=3
numb : natural; -- number of transactions (1=single, >1=burst)
start : boolean; -- edge starts transfer
txt : integer; -- enables info messages -- 0=quiet, 1=only errors, 2=all
END record;
-- Bus Accesses
PROCEDURE init( SIGNAL terminal_out : OUT terminal_out_type);
PROCEDURE wait_for( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
numb : natural;
woe : boolean
);
PROCEDURE rd32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd64( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd8_iack( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE wr32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr64( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
err : INOUT natural
) ;
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
seed : natural;
err : INOUT natural
) ;
PROCEDURE vme_ga_test(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL vme_ga : OUT std_logic_vector(4 DOWNTO 0);
SIGNAL vme_gap : OUT std_logic;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_sram2a24d32(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_am(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_boundaries(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_fifo(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
size : integer; -- number of longwords to be transmitted by DMA
src_adr : std_logic_vector(31 downto 0); -- DMA source address
dest_adr : std_logic_vector(31 downto 0); -- DMA destination address
vme_am : std_logic_vector(4 downto 0); -- address modifier bits of buffer descriptor
src_dev : std_logic_vector(2 downto 0); -- source device bits of buffer descriptor
dest_dev : std_logic_vector(2 downto 0); -- destination device bits of buffer descriptor
blk : std_logic; -- block or single access
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_slave_a242sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_slave_a242pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_reset(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL slot1 : OUT boolean;
SIGNAL hreset_n : OUT std_logic;
SIGNAL v2p_rstn : IN std_logic;
SIGNAL vb_sysresn : IN std_logic;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_slave_a322sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_slave_a322pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE cham_test(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_slave_a162regs(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_sram2sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_sram2pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_sram2a32d32(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_dma_sram2a32d64(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_buserror(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_master_windows(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_arbitration(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL hreset_n : OUT std_logic;
SIGNAL slot1 : OUT boolean;
SIGNAL en_clk : OUT boolean;
en_msg_0 : integer;
err : OUT natural
) ;
PROCEDURE vme_arbiter(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_irq_rcv(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE vme_irq_trans(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
en_msg_0 : integer;
err : OUT natural
);
PROCEDURE rd_iram_bfm(
adr : std_logic_vector(31 DOWNTO 0); -- address
exp_dat : std_logic_vector(31 DOWNTO 0); -- expected data
txt_out : integer; -- 0= no message, 1=only errors, 2=all
err : OUT integer -- 1 if exp_dat /= read data
);
PROCEDURE wr_iram_bfm(
adr : std_logic_vector(31 DOWNTO 0); -- address
dat : std_logic_vector(31 DOWNTO 0); -- data
txt_out : integer; -- 0= no message, 1=only errors, 2=all
err : OUT integer
);
PROCEDURE print_err(s: in string; err: in integer);
procedure configure_bfm(
signal terminal_in : in terminal_in_type;
signal terminal_out : out terminal_out_type;
bar0_addr : std_logic_vector(31 downto 0);
bar1_addr : std_logic_vector(31 downto 0);
bar2_addr : std_logic_vector(31 downto 0);
bar3_addr : std_logic_vector(31 downto 0);
bar4_addr : std_logic_vector(31 downto 0);
bar5_addr : std_logic_vector(31 downto 0);
txt_out : integer
);
END terminal_pkg;
PACKAGE BODY terminal_pkg IS
----------------------------------------------------------------------------------------------------------
PROCEDURE print_err(s: in string; err: in integer) is
variable l: line;
BEGIN
write(l, ' ');
WRITELINE(output,l);
WRITE(l, string'(" Testcase: "));
write(l, s);
WRITE(l, string'(" Error Sum: "));
write(l, err);
writeline(output,l);
write(l, ' ');
WRITELINE(output,l);
END print_err;
PROCEDURE wr_iram_bfm(
adr : std_logic_vector(31 DOWNTO 0); -- address
dat : std_logic_vector(31 DOWNTO 0); -- data
txt_out : integer; -- 0= no message, 1=only errors, 2=all
err : OUT integer
) IS
BEGIN
--! procedure to write values to the BFM internal memory
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param nbr_of_dw number of DWORDS that will be written
--! @param io_space set to true is I/O space is targeted
--! @param mem32 set to true is MEM32 space is targeted, otherwise MEM64 space is used
--! @param mem_addr offset for internal memory space, start at x"0000_0000"
--! @param start_data_val first data value to write, other values are defined by data_inc
--! @param data_inc defines the data increment added to start_data_val for DW 2 to nbr_of_dw
--set_bfm_memory(0, 1, FALSE, TRUE, adr, dat, 1);
set_bfm_memory(nbr_of_dw => 1, mem_addr => adr, start_data_val => dat, data_inc => 1);
IF txt_out > 1 THEN
print_cycle("BFM SET: ", adr, dat, "1111", "");
END IF;
err := 0;
END PROCEDURE;
PROCEDURE rd_iram_bfm(
adr : std_logic_vector(31 DOWNTO 0); -- address
exp_dat : std_logic_vector(31 DOWNTO 0); -- expected data
txt_out : integer; -- 0= no message, 1=only errors, 2=all
err : OUT integer -- 1 if exp_dat /= read data
) IS
VARIABLE databuf_out : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
BEGIN
--! procedure to read from BFM internal memory
--! @param bfm_inst_nbr number of the BFM instance that will be used
--! @param nbr_of_dw number of DWORDS that will be written
--! @param io_space set to true is I/O space is targeted
--! @param mem32 set to true is MEM32 space is targeted, otherwise MEM64 space is used
--! @param mem_addr offset for internal memory space, start at x"0000_0000"
--! @return databuf_out returns a dword_vector that contains all data read from BFM internal memory
--get_bfm_memory(0, 1, FALSE, TRUE, adr, databuf_out);
get_bfm_memory(nbr_of_dw => 1, mem_addr => adr, databuf_out => databuf_out);
IF databuf_out(0) /= exp_dat THEN
IF txt_out > 0 THEN
print_mtest("ERROR: ", adr, databuf_out(0), exp_dat, FALSE);
END IF;
err := 1;
ELSIF txt_out > 1 THEN
print_mtest("RD_IRAM_BFM: ", adr, databuf_out(0), exp_dat, TRUE);
err := 0;
END IF;
END PROCEDURE;
PROCEDURE init( SIGNAL terminal_out : OUT terminal_out_type) IS
BEGIN
terminal_out.adr <= (OTHERS => '0');
terminal_out.tga <= (OTHERS => '0');
terminal_out.dat <= (OTHERS => '0');
terminal_out.wr <= 0;
terminal_out.typ <= 0;
terminal_out.numb <= 0;
terminal_out.txt <= 0;
terminal_out.start <= TRUE;
END PROCEDURE init;
PROCEDURE wait_for( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
numb : natural;
woe : boolean
) IS
BEGIN
terminal_out.wr <= 2;
terminal_out.numb <= numb;
terminal_out.txt <= 0;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE rd32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 2;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd64( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 3;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 1;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 0;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd8_iack(
SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 4; -- indicate iack
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE wr32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 2;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr64( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 3;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 0;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 1;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
-- This is the legacy MTEST (without seed)
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
mtest(terminal_in, terminal_out, adr, adr_end, typ, numb, txt_out, tga, 0, err);
END PROCEDURE;
-- This is an overloaded MTEST which accepts a seed number as an input,
-- which can be used to generate the pseudo-random data in different ways
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
seed : natural;
err : INOUT natural
) IS
VARIABLE loc_err : natural;
VARIABLE loc_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE loc_dat : std_logic_vector(31 DOWNTO 0);
VARIABLE numb_cnt : natural;
BEGIN
loc_adr := adr;
numb_cnt := 0;
loc_err := 0;
loc_dat := adr;
while NOT(numb_cnt = numb) LOOP
CASE typ IS
WHEN 0 => -- long
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr32(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"4";
END LOOP;
WHEN 1 => -- word
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr16(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd16(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"2";
END LOOP;
WHEN 2 => -- byte
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr8(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd8(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"1";
END LOOP;
WHEN OTHERS =>
print("ERROR terminal_pkg: typ IS NOT defined!");
END CASE;
numb_cnt := numb_cnt + 1;
END LOOP;
IF loc_err > 0 THEN
print_s_i(" mtest FAIL errors: ", loc_err);
ELSE
print(" mtest PASS");
END IF;
err := err + loc_err;
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_ga_test(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL vme_ga : OUT std_logic_vector(4 DOWNTO 0);
SIGNAL vme_gap : OUT std_logic;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE vme_ga_int : std_logic_vector(4 DOWNTO 0);
VARIABLE vme_gap_int : std_logic;
BEGIN
print("Test vme_ga_test: VME graphical address test");
-- reset value shall be 0x0
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0050", x"0000_1e00", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print_time("Check Slot Number detection by using corresponding VME_GA/VME_GAP settings");
FOR i IN 1 TO 21 LOOP
print_s_i("Slot Number ",i);
vme_ga_int := NOT (conv_std_logic_vector(i,5)); -- inverted number
vme_gap_int := NOT (vme_ga_int(4) XOR vme_ga_int(3) XOR vme_ga_int(2) XOR vme_ga_int(1) XOR vme_ga_int(0));
vme_ga <= vme_ga_int;
vme_gap <= vme_gap_int;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0050", x"0000" & conv_std_logic_vector(i,8) & "00" & vme_gap_int & vme_ga_int, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
WAIT FOR 1 us;
print_time("Check Slot Number detection by using incorrect VME_GAP settings => Slot Number shall be always 30");
FOR i IN 1 TO 21 LOOP
print_s_i("Slot Number ",i);
vme_ga_int := NOT (conv_std_logic_vector(i,5)); -- inverted number
vme_gap_int := (vme_ga_int(4) XOR vme_ga_int(3) XOR vme_ga_int(2) XOR vme_ga_int(1) XOR vme_ga_int(0));
vme_ga <= vme_ga_int;
vme_gap <= vme_gap_int;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0050", x"0000" & x"1e" & "00" & vme_gap_int & vme_ga_int, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
WAIT FOR 1 us;
print_time("Check Slot Number detection by using incorrect VME_GA/VME_GAP settings => Slot Number shall be always 30");
FOR i IN 22 TO 31 LOOP
vme_ga_int := NOT (conv_std_logic_vector(i,5)); -- inverted number
vme_gap_int := NOT (vme_ga_int(4) XOR vme_ga_int(3) XOR vme_ga_int(2) XOR vme_ga_int(1) XOR vme_ga_int(0));
print_s_std("VME_GAP & VME_GA setting = ", "00" & vme_gap_int & vme_ga_int);
vme_ga <= vme_ga_int;
vme_gap <= vme_gap_int;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0050", x"0000" & x"1e" & "00" & vme_gap_int & vme_ga_int, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
err := err_sum;
print_err("vme_ga_test", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_sram2a24d32(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0110: VME DMA: SRAM TO VME A24D32 AND back");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2a24d32): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- test data in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"1111_1111", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"1111_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_000c", x"2222_2222", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_000c", x"2222_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0010", x"3333_3333", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0010", x"3333_3333", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0014", x"4444_4444", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0014", x"4444_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- clear destination in VME_A24D32
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0004", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0010", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0014", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001");
-- clear destination in SRAM
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0100", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_010c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0110", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0114", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_00fc", x"0000_0000", 1, en_msg_0, TRUE, "000001");
-- config buffer descriptor #1 SRAM => VME_A24D32
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0020_0004", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0020_0004", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0008", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_2040", 1, en_msg_0, TRUE, "000001"); -- source=sram dest=A24D32 inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_2040", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- config buffer descriptor #2 VME_A24D32 => SRAM
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0100", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0100", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"0020_0004", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"0020_0004", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_1041", 1, en_msg_0, TRUE, "000001"); -- source=A24D32 dest=sram inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_1041", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- start transfer
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2a24d32): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2a24d32: dma irq NOT asserted");
END IF;
-- check control reg for irq asserted
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0006", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0004", x"1111_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"2222_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000c", x"3333_3333", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0010", x"4444_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0014", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check destination SRAM
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_00fc", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0100", x"1111_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"2222_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"3333_3333", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_010c", x"4444_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0110", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check irq
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2a24d32: dma irq NOT asserted");
END IF;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma_sram2a24d32: dma irq asserted");
END IF;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
WAIT FOR 500 ns;
err := err_sum;
print_err("vme_dma_sram2a24d32", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_am(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable offset : std_logic_vector(11 downto 0);
variable size : integer; -- number of longwords to be transmitted by DMA
variable am : std_logic_vector(5 downto 0);
BEGIN
-- checks all address modifiers possible by DMA transfer: A16, A24, A32, D16, D32, D64, supervisory, non-privilegded
size := 4;
-- set longadd
-- wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001"); -- if generic USE_LONGADD=false
-- rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001", loc_err);
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- test data in sram
FOR i IN 0 TO size*4+1 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001");
END LOOP;
print_time("Test vme_dma_am: A24 Accesses");
-- A24_D16 supervisory BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D16 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0000", -- destination address
DMA_VME_AM_A24D16_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D16 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0000", -- source address
x"0000_2000", -- destination address
DMA_VME_AM_A24D16_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D32 supervisory BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D32 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0100", -- destination address
DMA_VME_AM_A24D32_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0100", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D16 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0100", -- source address
x"0000_2100", -- destination address
DMA_VME_AM_A24D32_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2100", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D16 supervisory
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D16 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0200", -- destination address
DMA_VME_AM_A24D16_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0200", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D16 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0200", -- source address
x"0000_2200", -- destination address
DMA_VME_AM_A24D16_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2200", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D32 supervisory
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0300", -- destination address
DMA_VME_AM_A24D32_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0300", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0300", -- source address
x"0000_2300", -- destination address
DMA_VME_AM_A24D32_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2300", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D64 supervisory MBLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D64 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0400", -- destination address
DMA_VME_AM_A24D64_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0400", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D64 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0400", -- source address
x"0000_2400", -- destination address
DMA_VME_AM_A24D64_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_SUPER_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2400", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D16 non-priviledged BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D64 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0500", -- destination address
DMA_VME_AM_A24D16_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0500", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D64 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0500", -- source address
x"0000_2500", -- destination address
DMA_VME_AM_A24D16_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2500", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D32 non-priviledged BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D32 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0600", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0600", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D32 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0600", -- source address
x"0000_2600", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2600", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D16 non-priviledged
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D16 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0700", -- destination address
DMA_VME_AM_A24D16_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0700", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D16 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0700", -- source address
x"0000_2700", -- destination address
DMA_VME_AM_A24D16_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2700", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D32 non-priviledged
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D32 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0800", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0800", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D32 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0800", -- source address
x"0000_2800", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2800", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A24_D64 non-priviledged MBLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A24D64 non-privileged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0900", -- destination address
DMA_VME_AM_A24D64_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0900", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A24D32 non-privileged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0020_0900", -- source address
x"0000_2900", -- destination address
DMA_VME_AM_A24D64_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A24_NONPRIV_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2900", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print_time("Test vme_dma_am: A16 Accesses");
-- A16_D16 supervisory
print("Test vme_dma_am: VME DMA: SRAM TO VME A16D16 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0000_1000", -- destination address
DMA_VME_AM_A16D16_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_SUPER THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A16D16 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_1000", -- source address
x"0000_2a00", -- destination address
DMA_VME_AM_A16D16_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_SUPER THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2a00", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A16_D32 supervisory
print("Test vme_dma_am: VME DMA: SRAM TO VME A16D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0000_1100", -- destination address
DMA_VME_AM_A16D32_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_SUPER THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1100", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A16D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_1100", -- source address
x"0000_2b00", -- destination address
DMA_VME_AM_A16D32_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_SUPER THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2b00", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A16_D16 non-priviledged
print("Test vme_dma_am: VME DMA: SRAM TO VME A16D16 non-priviledged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0000_1200", -- destination address
DMA_VME_AM_A16D16_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_NONPRIV THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1200", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A16D16 non-priviledged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_1200", -- source address
x"0000_2c00", -- destination address
DMA_VME_AM_A16D16_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_NONPRIV THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2c00", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A16_D32 non-priviledged
print("Test vme_dma_am: VME DMA: SRAM TO VME A16D32 non-priviledged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"0000_1300", -- destination address
DMA_VME_AM_A16D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_NONPRIV THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1300", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A16D32 non-priviledged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_1300", -- source address
x"0000_2d00", -- destination address
DMA_VME_AM_A16D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A16_NONPRIV THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2d00", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print_time("Test vme_dma_am: A32 Accesses");
-- A32_D32 supervisory BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D32 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0000", -- destination address
DMA_VME_AM_A32D32_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D32 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0000", -- source address
x"0000_3000", -- destination address
DMA_VME_AM_A32D32_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A32_D32 supervisory
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0100", -- destination address
DMA_VME_AM_A32D32_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0100", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D32 supervisory with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0100", -- source address
x"0000_3100", -- destination address
DMA_VME_AM_A32D32_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3100", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A32_D64 supervisory MBLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D64 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0200", -- destination address
DMA_VME_AM_A32D64_priv, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0200", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D64 supervisory with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0200", -- source address
x"0000_3200", -- destination address
DMA_VME_AM_A32D64_priv, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_SUPER_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3200", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A32_D32 non-priviledged BLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D32 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0300", -- destination address
DMA_VME_AM_A32D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0300", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D32 non-priviledged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0300", -- source address
x"0000_3300", -- destination address
DMA_VME_AM_A32D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_BLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3300", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A32_D32 non-priviledged
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D32 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0400", -- destination address
DMA_VME_AM_A32D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0400", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D32 non-privileged with single transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0400", -- source address
x"0000_3400", -- destination address
DMA_VME_AM_A32D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_SGL, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_DAT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3400", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A32_D64 non-priviledged MBLT
print("Test vme_dma_am: VME DMA: SRAM TO VME A32D64 non-privileged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"0000_0000", -- source address
x"3000_0600", -- destination address
DMA_VME_AM_A32D64_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0600", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_am: VME DMA: VME to SRAM A32D32 non-privileged with block transfers");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size = 1 longword
x"3000_0600", -- source address
x"0000_3600", -- destination address
DMA_VME_AM_A32D64_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- access type
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check vme address modifier used
am_vme_slv(vme_slv_in, vme_slv_out, am);
IF am /= AM_A32_NONPRIV_MBLT THEN
print_now_s_hb ("ERROR vme_dma_am: wrong address modifier used! am = ", ("00" & am));
err_sum := err_sum + 1;
else
print_time("vme_dma_am: Checked AM => OK");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3600", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_dma_am", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_boundaries(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable offset : std_logic_vector(11 downto 0);
variable size : integer; -- number of longwords to be transmitted by DMA
BEGIN
size := 64; --257
-- test data in sram
FOR i IN 0 TO size*4+1 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001");
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME with size of 4 bytes ");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
1, -- data block size = 1 longword
x"0000_0000", -- source address
x"0020_0000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
print("Test vme_dma_boundaries: VME DMA: VME to SRAM with size of 4 bytes ");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
1, -- data block size = 1 longword
x"0020_0000", -- source address
x"0000_2000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
-- check destination
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2000", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_000c", 1, en_msg_0, TRUE, "000001"); -- clear dma err
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME with size of 0x404 longwords at offset 0x4");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0000", -- source address
x"0020_0004", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_0004", -- source address
x"0000_1000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0004" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0004" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with size of 256 bytes (exactly as large as boundary)");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0000", -- source address
x"0020_0000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_0000", -- source address
x"0000_1000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing boundary by one access");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0e0";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_1" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_1" & offset, -- source address
x"0000_2" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_1" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_1" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_2" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_2" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing boundary by two access");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0e4";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_2" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_2" & offset, -- source address
x"0000_3" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_2" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_2" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_3" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_3" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing boundary by three access");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0e8";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_3" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_3" & offset, -- source address
x"0000_4" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_3" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_3" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_4" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_4" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing after one access");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0fc";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_4" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_4" & offset, -- source address
x"0000_5" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_4" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_4" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_5" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_5" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing after two accesses");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0f8";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_5" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_5" & offset, -- source address
x"0000_6" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_5" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_5" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_6" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_6" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_boundaries: VME DMA: SRAM TO VME AND back with crossing after three accesses");
size := 9;
print_s_i ("Size in byte = ", size*4);
offset := x"0f4";
print_s_std ("Offset address = 0x", offset);
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0" & offset, -- source address
x"0020_6" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_6" & offset, -- source address
x"0000_7" & offset, -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_6" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + (x"0020_6" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_7" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + (x"0000_7" & offset) + (4*i), (x"00000" & offset) + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
err := err_sum;
print_err("vme_dma_boundaries", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma_fifo(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable offset : std_logic_vector(11 downto 0);
variable size : integer; -- number of longwords to be transmitted by DMA
constant CONST_FIFO_SIZE : integer := 256;
BEGIN
size := CONST_FIFO_SIZE;
-- test data in sram
FOR i IN 0 TO size*4+1 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001");
END LOOP;
print("Test vme_dma_fifo: SRAM TO VME AND back with size of fifo depth");
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0000", -- source address
x"0020_0000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_0000", -- source address
x"0000_1000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_fifo: SRAM TO VME AND back with size of fifo depth +1");
size := CONST_FIFO_SIZE+1;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0000", -- source address
x"0020_1000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_1000", -- source address
x"0000_2000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_1000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_2000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
print("Test vme_dma_fifo: SRAM TO VME AND back with size of fifo depth +2");
size := CONST_FIFO_SIZE+2;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0000_0000", -- source address
x"0020_2000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_SRAM, -- source device
DMA_DEVICE_VME, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
vme_dma(terminal_in_0, terminal_out_0, irq_req,
size, -- data block size in longword -1
x"0020_2000", -- source address
x"0000_3000", -- destination address
DMA_VME_AM_A24D32_non, -- vme address modifier
DMA_DEVICE_VME, -- source device
DMA_DEVICE_SRAM, -- destination device
DMA_BLK, -- block access
en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_2000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_2000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
-- check destination SRAM
FOR i IN 0 TO 2 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
FOR i IN size-2 TO size-1 LOOP
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_3000" + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
END LOOP;
err := err_sum;
print_err("vme_dma_fifo", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_dma (
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
size : integer; -- number of longwords to be transmitted by DMA
src_adr : std_logic_vector(31 downto 0); -- DMA source address
dest_adr : std_logic_vector(31 downto 0); -- DMA destination address
vme_am : std_logic_vector(4 downto 0); -- address modifier bits of buffer descriptor
src_dev : std_logic_vector(2 downto 0); -- source device bits of buffer descriptor
dest_dev : std_logic_vector(2 downto 0); -- destination device bits of buffer descriptor
blk : std_logic; -- block(0) or single(1) access
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable bd_0xc : std_logic_vector(31 downto 0);
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2a24d32): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
if en_msg_0 > 0 then
print_now ("VME DMA access");
print_s_std(" Source Address = ", src_adr);
if src_dev = "001" then
print (" Source Device = SRAM");
elsif src_dev = "010" then
print (" Source Device = VME");
elsif src_dev = "100" then
print (" Source Device = PCI");
else
print (" Source Device = unknown");
end if;
print_s_std(" Destination Address = ", dest_adr);
if dest_dev = "001" then
print (" Destination Device = SRAM");
elsif dest_dev = "010" then
print (" Destination Device = VME");
elsif dest_dev = "100" then
print (" Destination Device = PCI");
else
print (" Destination Device = unknown");
end if;
print_s_i (" Size in Byte = ", (size-1)*4);
end if;
bd_0xc := "0000000000000" & src_dev & '0' & dest_dev & "000" & vme_am & blk & "001";
-- config buffer descriptor
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", dest_adr, 1, 0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", dest_adr, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", src_adr, 1, 0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", src_adr, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0000" + size-1, 1, 0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0000" + size-1, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", bd_0xc, 1, 0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", bd_0xc, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, 0, TRUE, "000001"); -- start transfer
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2a24d32): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma: dma irq NOT asserted");
END IF;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, 0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma: dma irq asserted");
END IF;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
WAIT FOR 500 ns;
err := err_sum;
print_err("vme_dma", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_reset(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL slot1 : OUT boolean;
SIGNAL hreset_n : OUT std_logic;
SIGNAL v2p_rstn : IN std_logic;
SIGNAL vb_sysresn : IN std_logic;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
BEGIN
print("Test MEN_01A021_00_IT_0010: VME Reset (there might be WBB bus errors indicated");
print("NOT Slot1");
-- powerup board
-- shorten reset time on vme bus
hreset_n <= '0';
signal_force("/a25_tb/a25/pll/areset", "1", 0 ns, freeze, 100 ns, 1);
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/pre_cnt_max_sig", "0000001000", 0 ns, freeze, -1 ns, 1);
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/main_cnt_max_sig", "000000000000011", 0 ns, freeze, -1 ns, 1);
-- signal_force("/a25_tb/a25/pcie/test_pcie_core", "0000000000000001", 0 ns, freeze, -1 ns, 1);
-- signal_force("/a25_tb/a25/pcie/test_rs_serdes", "1", 0 ns, freeze, -1 ns, 1);
slot1 <= FALSE;
WAIT FOR 100 ns;
IF vb_sysresn /= '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be active");
err_sum := err_sum + 1;
END IF;
hreset_n <= '1';
WAIT FOR 1 us;
IF vb_sysresn = '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be inactive");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
print_time("check result of slot1 detection");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0018", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print_time(" vb_sysresn inactive?");
IF vb_sysresn = '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be inactive");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
print_time(" force vb_sysresn TO 0");
signal_force("/a25_tb/vb_sysresn", "0", 0 ns, freeze, 1000 ns, 1);
WAIT FOR 200 ns;
print_time(" v2p_rstn active?");
IF v2p_rstn /= '0' THEN
print_time(" ERROR: SIGNAL v2p_rstn should be active");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
print_time(" v2p_rstn inactive?");
IF v2p_rstn = '0' THEN
print_time(" ERROR: SIGNAL v2p_rstn should be inactive");
err_sum := err_sum + 1;
END IF;
hreset_n <= '1';
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0018", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
----------------------------
print("Slot1");
-- powerup board
-- shorten reset time on vme bus
hreset_n <= '0';
signal_force("/a25_tb/a25/pll/areset", "1", 0 ns, freeze, 100 ns, 1);
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/pre_cnt_max_sig", "0000001000", 0 ns, freeze, -1 ns, 1);
signal_force("/a25_tb/a25/vme/vmectrl/bustimer/main_cnt_max_sig", "000000000000011", 0 ns, freeze, -1 ns, 1);
-- signal_force("/a25_tb/a25/pcie/test_pcie_core", "0000000000000001", 0 ns, freeze, -1 ns, 1);
-- signal_force("/a25_tb/a25/pcie/test_rs_serdes", "1", 0 ns, freeze, -1 ns, 1);
slot1 <= TRUE;
WAIT FOR 100 ns;
IF vb_sysresn /= '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be active");
err_sum := err_sum + 1;
END IF;
hreset_n <= '1';
WAIT FOR 1 us;
IF vb_sysresn = '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be inactive");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
print_time("check result of slot1 detection");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0018", x"00000001", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print_time(" vb_sysresn inactive?");
IF vb_sysresn = '0' THEN
print_time(" ERROR: SIGNAL vb_sysresn should be inactive");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
print_time(" force vb_sysresn TO 0");
signal_force("/a25_tb/vb_sysresn", "0", 0 ns, freeze, 1000 ns, 1);
WAIT FOR 200 ns;
print_time(" v2p_rstn active?");
IF v2p_rstn /= '0' THEN
print_time(" ERROR: SIGNAL v2p_rstn should be active");
err_sum := err_sum + 1;
END IF;
WAIT FOR 1 us;
print_time(" v2p_rstn inactive?");
IF v2p_rstn = '0' THEN
print_time(" ERROR: SIGNAL v2p_rstn should be inactive");
err_sum := err_sum + 1;
END IF;
hreset_n <= '1';
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0018", x"00000001", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_reset", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_slave_a242sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
BEGIN
print("Test MEN_01A021_00_IT_0030: VME A24 TO SRAM WRITE");
-- write to a24 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0013", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0030_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0030_0104", x"cafe_affe", 1, en_msg_0, TRUE, "111101");
wr32(terminal_in_1, terminal_out_1, x"0030_0108", x"1111_2222", 1, en_msg_0, TRUE, "111101");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"0030_0130", x"1112_1314", 1, en_msg_0, TRUE, "111101");
wr16(terminal_in_1, terminal_out_1, x"0030_0132", x"1516_1718", 1, en_msg_0, TRUE, "111101");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"0030_0140", x"1111_11aa", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0141", x"1111_bb11", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0142", x"11cc_1111", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0143", x"dd11_1111", 1, en_msg_0, TRUE, "111101");
-- write to a24 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0014", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0040_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0040_0304", x"cafe_affe", 1, en_msg_0, TRUE, "111001");
wr32(terminal_in_1, terminal_out_1, x"0040_0308", x"1111_2222", 1, en_msg_0, TRUE, "111001");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"0040_0330", x"1112_1314", 1, en_msg_0, TRUE, "111001");
wr16(terminal_in_1, terminal_out_1, x"0040_0332", x"1516_1718", 1, en_msg_0, TRUE, "111001");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"0040_0340", x"1111_11aa", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0341", x"1111_bb11", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0342", x"11cc_1111", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0343", x"dd11_1111", 1, en_msg_0, TRUE, "111001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0050_0000
WAIT FOR 1 us;
-- non privileged block transfer
wr32(terminal_in_1, terminal_out_1, x"0050_0410", x"3333_4444", 2, en_msg_0, TRUE, "111011");
WAIT FOR 100 ns;
-- supervisory block transfer
wr32(terminal_in_1, terminal_out_1, x"0050_0420", x"5555_5555", 3, en_msg_0, TRUE, "111111");
WAIT FOR 100 ns;
-- non privileged 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"0050_0450", x"1234_5678", 2, en_msg_0, TRUE, "111000");
WAIT FOR 100 ns;
-- supervisory 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"0050_0470", x"cafe_affe", 3, en_msg_0, TRUE, "111100");
WAIT FOR 100 ns;
-- read from sram
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"1111_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0132", x"1516_1314", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0140", x"ddcc_bbaa", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"1111_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0332", x"1516_1314", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0340", x"ddcc_bbaa", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0410", x"3333_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0414", x"3433_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0420", x"5555_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0424", x"5655_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0428", x"5755_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := x"1234_5678";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0454", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0450", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_045c", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0458", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := x"cafe_affe";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0474", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0470", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_047c", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0478", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0484", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0480", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test: VME A24 TO SRAM READ");
-- prepare data in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"1111_2222", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0030", x"1516_1314", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0034", x"1234_5678", 1, en_msg_0, TRUE, "000001");
dat := x"1234_5678";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0044", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0040", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_004c", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0048", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0054", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0050", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_005c", dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0080", x"abcd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0084", x"accd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0088", x"adcd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_008c", x"aecd_ef01", 1, en_msg_0, TRUE, "000001");
-- read from a24 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0017", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0070_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0070_0008", x"1111_2222", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"0070_0030", x"1112_1314", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"0070_0032", x"1516_1718", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"0070_0034", x"1111_1178", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0035", x"1111_5611", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0036", x"1134_1111", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0037", x"1211_1111", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0070_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0050_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0050_0008", x"1111_2222", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"0050_0030", x"1112_1314", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"0050_0032", x"1516_1718", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"0050_0034", x"1111_1178", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0035", x"1111_5611", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0036", x"1134_1111", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0037", x"1211_1111", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0050_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0018", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0080_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0080_0080", x"abcd_ef01", 2, en_msg_0, TRUE, "111111", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (non privileged block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_0019", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0090_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0090_0080", x"abcd_ef01", 3, en_msg_0, TRUE, "111011", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_001a", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x00a0_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"00a0_0040", x"1234_5678", 2, en_msg_0, TRUE, "111100", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_001b", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x00b0_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"00b0_0040", x"1234_5678", 3, en_msg_0, TRUE, "111000", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_slave_a242sram", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_slave_a242pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
VARIABLE ex_dat : std_logic_vector(31 DOWNTO 0);
CONSTANT OFFSET : std_logic_vector(31 DOWNTO 0):=x"1000_0000";
BEGIN
print("Test MEN_01A021_00_IT_0040: VME A24 TO PCI WRITE");
-- set pci offset
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0028", x"0000_0100", 1, en_msg_0, TRUE, "000001"); -- set pci offset to 0x1000_0000
-- write to a24 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0013", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0030_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0030_0104", x"cafe_affe", 1, en_msg_0, TRUE, "111101");
wr32(terminal_in_1, terminal_out_1, x"0030_0108", x"1111_2222", 1, en_msg_0, TRUE, "111101");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"0030_0130", x"1112_1314", 1, en_msg_0, TRUE, "111101");
wr16(terminal_in_1, terminal_out_1, x"0030_0132", x"1516_1718", 1, en_msg_0, TRUE, "111101");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"0030_0140", x"1111_11aa", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0141", x"1111_bb11", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0142", x"11cc_1111", 1, en_msg_0, TRUE, "111101");
wr8(terminal_in_1, terminal_out_1, x"0030_0143", x"dd11_1111", 1, en_msg_0, TRUE, "111101");
-- write to a24 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0014", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0040_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0040_0304", x"cafe_affe", 1, en_msg_0, TRUE, "111001");
wr32(terminal_in_1, terminal_out_1, x"0040_0308", x"1111_2222", 1, en_msg_0, TRUE, "111001");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"0040_0330", x"1112_1314", 1, en_msg_0, TRUE, "111001");
wr16(terminal_in_1, terminal_out_1, x"0040_0332", x"1516_1718", 1, en_msg_0, TRUE, "111001");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"0040_0340", x"1111_11aa", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0341", x"1111_bb11", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0342", x"11cc_1111", 1, en_msg_0, TRUE, "111001");
wr8(terminal_in_1, terminal_out_1, x"0040_0343", x"dd11_1111", 1, en_msg_0, TRUE, "111001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0050_0000
WAIT FOR 1 us;
-- non privileged block transfer
wr32(terminal_in_1, terminal_out_1, x"0050_0410", x"3333_4444", 2, en_msg_0, TRUE, "111011");
WAIT FOR 100 ns;
-- supervisory block transfer
wr32(terminal_in_1, terminal_out_1, x"0050_0420", x"5555_5555", 3, en_msg_0, TRUE, "111111");
WAIT FOR 100 ns;
-- non privileged 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"0050_0450", x"1234_5678", 2, en_msg_0, TRUE, "111000");
WAIT FOR 100 ns;
-- supervisory 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"0050_0470", x"cafe_affe", 3, en_msg_0, TRUE, "111100");
WAIT FOR 2 us;
-- read from sram
rd_iram_bfm(x"0000_0104", x"cafe_affe", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0108", x"1111_2222", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0130", x"1516_1314", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0140", x"ddcc_bbaa", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0304", x"cafe_affe", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0308", x"1111_2222", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0330", x"1516_1314", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0340", x"ddcc_bbaa", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0410", x"3333_4444", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0414", x"3433_4444", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0420", x"5555_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0424", x"5655_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0428", x"5755_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := x"1234_5678";
rd_iram_bfm(x"0000_0454", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0450", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_045c", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0458", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := x"cafe_affe";
rd_iram_bfm(x"0000_0474", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0470", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_047c", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0478", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_0484", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0480", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
print("Test: VME A24 TO PCI READ");
-- prepare data in sram
wr_iram_bfm(x"0000_0004", x"cafe_affe", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0008", x"1111_2222", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0030", x"1516_1314", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0034", x"1234_5678", en_msg_0, loc_err);
dat := x"1234_5678";
wr_iram_bfm(x"0000_0044", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0040", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_004c", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0048", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_0054", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0050", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_005c", dat, en_msg_0, loc_err);
wr_iram_bfm(x"0000_0080", x"abcd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0084", x"accd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0088", x"adcd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_008c", x"aecd_ef01", en_msg_0, loc_err);
-- read from a24 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0017", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0070_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0070_0008", x"1111_2222", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"0070_0030", x"1112_1314", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"0070_0032", x"1516_1718", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"0070_0034", x"1111_1178", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0035", x"1111_5611", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0036", x"1134_1111", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0070_0037", x"1211_1111", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0070_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111101", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0050_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0050_0008", x"1111_2222", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"0050_0030", x"1112_1314", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"0050_0032", x"1516_1718", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"0050_0034", x"1111_1178", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0035", x"1111_5611", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0036", x"1134_1111", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"0050_0037", x"1211_1111", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0050_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111001", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0018", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0080_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0080_0080", x"abcd_ef01", 2, en_msg_0, TRUE, "111111", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (non privileged block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_0019", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0090_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"0090_0080", x"abcd_ef01", 3, en_msg_0, TRUE, "111011", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_001a", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x00a0_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"00a0_0040", x"1234_5678", 2, en_msg_0, TRUE, "111100", loc_err);
err_sum := err_sum + loc_err;
-- read from a24 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_001b", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x00b0_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"00b0_0040", x"1234_5678", 3, en_msg_0, TRUE, "111000", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_slave_a242pci", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE cham_test(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
BEGIN
print("Test MEN_01A021_00_IT_0210: Chameleon Table");
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0000", x"00014103", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0004", x"0000abce", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0008", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_000c", x"32304100", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0010", x"30302d35", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0014", x"006013ff", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0018", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_001c", x"00000000", 1, en_msg_0, TRUE, "000001", loc_err);
rd32(terminal_in_0, terminal_out_0, BAR0 + x"0000_0020", x"00000200", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("cham_test", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_slave_a322sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
BEGIN
print("Test MEN_01A021_00_IT_0020: VME A32 TO SRAM WRITE");
-- write to a32 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0012", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x2000_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"2000_0104", x"cafe_affe", 1, en_msg_0, TRUE, "001101");
wr32(terminal_in_1, terminal_out_1, x"2000_0108", x"1111_2222", 1, en_msg_0, TRUE, "001101");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"2000_0130", x"1112_1314", 1, en_msg_0, TRUE, "001101");
wr16(terminal_in_1, terminal_out_1, x"2000_0132", x"1516_1718", 1, en_msg_0, TRUE, "001101");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"2000_0140", x"1111_11aa", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0141", x"1111_bb11", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0142", x"11cc_1111", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0143", x"dd11_1111", 1, en_msg_0, TRUE, "001101");
-- write to a32 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0014", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x4000_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"4000_0304", x"cafe_affe", 1, en_msg_0, TRUE, "001001");
wr32(terminal_in_1, terminal_out_1, x"4000_0308", x"1111_2222", 1, en_msg_0, TRUE, "001001");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"4000_0330", x"1112_1314", 1, en_msg_0, TRUE, "001001");
wr16(terminal_in_1, terminal_out_1, x"4000_0332", x"1516_1718", 1, en_msg_0, TRUE, "001001");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"4000_0340", x"1111_11aa", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0341", x"1111_bb11", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0342", x"11cc_1111", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0343", x"dd11_1111", 1, en_msg_0, TRUE, "001001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x5000_0000
WAIT FOR 1 us;
-- non privileged block transfer
wr32(terminal_in_1, terminal_out_1, x"5000_0410", x"3333_4444", 2, en_msg_0, TRUE, "001011");
WAIT FOR 100 ns;
-- supervisory block transfer
wr32(terminal_in_1, terminal_out_1, x"5000_0420", x"5555_5555", 3, en_msg_0, TRUE, "001111");
WAIT FOR 100 ns;
-- non privileged 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"5000_0450", x"1234_5678", 2, en_msg_0, TRUE, "001000");
WAIT FOR 100 ns;
-- supervisory 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"5000_0470", x"cafe_affe", 3, en_msg_0, TRUE, "001100");
WAIT FOR 100 ns;
-- read from sram
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"1111_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0132", x"1516_1314", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0140", x"ddcc_bbaa", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"1111_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0332", x"1516_1314", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0340", x"ddcc_bbaa", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0410", x"3333_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0414", x"3433_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0420", x"5555_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0424", x"5655_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0428", x"5755_5555", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := x"1234_5678";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0454", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0450", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_045c", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0458", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := x"cafe_affe";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0474", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0470", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_047c", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0478", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := (NOT dat) + x"10_00000";
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0484", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
dat := NOT dat;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0480", dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print("Test: VME A32 TO SRAM READ");
-- prepare data in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"1111_2222", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0030", x"1516_1314", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0034", x"1234_5678", 1, en_msg_0, TRUE, "000001");
dat := x"1234_5678";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0044", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0040", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_004c", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0048", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0054", dat, 1, en_msg_0, TRUE, "000001");
dat := NOT dat;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0050", dat, 1, en_msg_0, TRUE, "000001");
dat := (NOT dat) + x"10_00000";
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_005c", dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0080", x"abcd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0084", x"accd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0088", x"adcd_ef01", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_008c", x"aecd_ef01", 1, en_msg_0, TRUE, "000001");
-- read from a32 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0017", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x7000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"7000_0008", x"1111_2222", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"7000_0030", x"1112_1314", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"7000_0032", x"1516_1718", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"7000_0034", x"1111_1178", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0035", x"1111_5611", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0036", x"1134_1111", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0037", x"1211_1111", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"7000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x5000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"5000_0008", x"1111_2222", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"5000_0030", x"1112_1314", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"5000_0032", x"1516_1718", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"5000_0034", x"1111_1178", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0035", x"1111_5611", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0036", x"1134_1111", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0037", x"1211_1111", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"5000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0018", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x8000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"8000_0080", x"abcd_ef01", 2, en_msg_0, TRUE, "001111", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (non privileged block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_0019", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x9000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"9000_0080", x"abcd_ef01", 3, en_msg_0, TRUE, "001011", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_001a", 1, en_msg_0, TRUE, "000001"); -- set base address to 0xa000_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"a000_0040", x"1234_5678", 2, en_msg_0, TRUE, "001100", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"0000_001b", 1, en_msg_0, TRUE, "000001"); -- set base address to 0xb000_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"b000_0040", x"1234_5678", 3, en_msg_0, TRUE, "001000", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_slave_a322sram", err_sum);
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE vme_slave_a322pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
VARIABLE ex_dat : std_logic_vector(31 DOWNTO 0);
CONSTANT OFFSET : std_logic_vector(31 DOWNTO 0):=x"2000_0000";
BEGIN
print("Test MEN_01A021_00_IT_0050: VME A32 TO PCI WRITE");
-- set bar0 offset of bfm to 0x2000_0000
init_bfm(0, x"0000_0000", x"0000_0000", x"0000_0000_0000_0000", x"0000", 256);
-- set pci offset
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0028", x"0000_0000", 1, en_msg_0, TRUE, "000001"); -- set pci offset to 0x0000_0000
-- write to a32 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0012", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x2000_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"2000_0104", x"cafe_affe", 1, en_msg_0, TRUE, "001101");
wr32(terminal_in_1, terminal_out_1, x"2000_0108", x"1111_2222", 1, en_msg_0, TRUE, "001101");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"2000_0130", x"1112_1314", 1, en_msg_0, TRUE, "001101");
wr16(terminal_in_1, terminal_out_1, x"2000_0132", x"1516_1718", 1, en_msg_0, TRUE, "001101");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"2000_0140", x"1111_11aa", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0141", x"1111_bb11", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0142", x"11cc_1111", 1, en_msg_0, TRUE, "001101");
wr8(terminal_in_1, terminal_out_1, x"2000_0143", x"dd11_1111", 1, en_msg_0, TRUE, "001101");
-- write to a32 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0014", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x4000_0000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"4000_0304", x"cafe_affe", 1, en_msg_0, TRUE, "001001");
wr32(terminal_in_1, terminal_out_1, x"4000_0308", x"1111_2222", 1, en_msg_0, TRUE, "001001");
WAIT FOR 100 ns;
wr16(terminal_in_1, terminal_out_1, x"4000_0330", x"1112_1314", 1, en_msg_0, TRUE, "001001");
wr16(terminal_in_1, terminal_out_1, x"4000_0332", x"1516_1718", 1, en_msg_0, TRUE, "001001");
WAIT FOR 100 ns;
wr8(terminal_in_1, terminal_out_1, x"4000_0340", x"1111_11aa", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0341", x"1111_bb11", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0342", x"11cc_1111", 1, en_msg_0, TRUE, "001001");
wr8(terminal_in_1, terminal_out_1, x"4000_0343", x"dd11_1111", 1, en_msg_0, TRUE, "001001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x5000_0000
WAIT FOR 1 us;
-- non privileged block transfer
wr32(terminal_in_1, terminal_out_1, x"5000_0410", x"3333_4444", 2, en_msg_0, TRUE, "001011");
WAIT FOR 100 ns;
-- supervisory block transfer
wr32(terminal_in_1, terminal_out_1, x"5000_0420", x"5555_5555", 3, en_msg_0, TRUE, "001111");
WAIT FOR 100 ns;
-- non privileged 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"5000_0450", x"1234_5678", 2, en_msg_0, TRUE, "001000");
WAIT FOR 100 ns;
-- supervisory 64-bit block transfer
wr64(terminal_in_1, terminal_out_1, x"5000_0470", x"cafe_affe", 3, en_msg_0, TRUE, "001100");
WAIT FOR 1 us;
-- read from sram
rd_iram_bfm(x"0000_0104", x"cafe_affe", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0108", x"1111_2222", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
--rd_iram_bfm(x"0000_0132", x"1516_1314", en_msg_0, loc_err);
rd_iram_bfm(x"0000_0130", x"1516_1314", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0140", x"ddcc_bbaa", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0304", x"cafe_affe", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0308", x"1111_2222", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
--rd_iram_bfm(x"0000_0332", x"1516_1314", en_msg_0, loc_err);
rd_iram_bfm(x"0000_0330", x"1516_1314", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0340", x"ddcc_bbaa", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0410", x"3333_4444", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0414", x"3433_4444", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0420", x"5555_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0424", x"5655_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
rd_iram_bfm(x"0000_0428", x"5755_5555", en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := x"1234_5678";
rd_iram_bfm(x"0000_0454", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0450", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_045c", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0458", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := x"cafe_affe";
rd_iram_bfm(x"0000_0474", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0470", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_047c", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0478", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := (NOT ex_dat) + x"10_00000";
rd_iram_bfm(x"0000_0484", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
ex_dat := NOT ex_dat;
rd_iram_bfm(x"0000_0480", ex_dat, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
print("Test: VME A32 TO PCI READ");
-- prepare data in sram
wr_iram_bfm(x"0000_0004", x"cafe_affe", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0008", x"1111_2222", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0030", x"1516_1314", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0034", x"1234_5678", en_msg_0, loc_err);
dat := x"1234_5678";
wr_iram_bfm(x"0000_0044", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0040", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_004c", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0048", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_0054", dat, en_msg_0, loc_err);
dat := NOT dat;
wr_iram_bfm(x"0000_0050", dat, en_msg_0, loc_err);
dat := (NOT dat) + x"10_00000";
wr_iram_bfm(x"0000_005c", dat, en_msg_0, loc_err);
wr_iram_bfm(x"0000_0080", x"abcd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0084", x"accd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_0088", x"adcd_ef01", en_msg_0, loc_err);
wr_iram_bfm(x"0000_008c", x"aecd_ef01", en_msg_0, loc_err);
-- read from a32 vme slave (supervisory data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0017", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x7000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"7000_0008", x"1111_2222", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"7000_0030", x"1112_1314", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"7000_0032", x"1516_1718", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"7000_0034", x"1111_1178", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0035", x"1111_5611", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0036", x"1134_1111", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"7000_0037", x"1211_1111", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"7000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "001101", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (non privileged data access)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x5000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"5000_0008", x"1111_2222", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd16(terminal_in_1, terminal_out_1, x"5000_0030", x"1112_1314", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_1, terminal_out_1, x"5000_0032", x"1516_1718", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
rd8(terminal_in_1, terminal_out_1, x"5000_0034", x"1111_1178", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0035", x"1111_5611", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0036", x"1134_1111", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_1, terminal_out_1, x"5000_0037", x"1211_1111", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"5000_0004", x"cafe_affe", 1, en_msg_0, TRUE, "001001", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0018", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x8000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"8000_0080", x"abcd_ef01", 2, en_msg_0, TRUE, "001111", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (non privileged block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_0019", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x9000_0000
WAIT FOR 1 us;
rd32(terminal_in_1, terminal_out_1, x"9000_0080", x"abcd_ef01", 3, en_msg_0, TRUE, "001011", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_001a", 1, en_msg_0, TRUE, "000001"); -- set base address to 0xa000_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"a000_0040", x"1234_5678", 2, en_msg_0, TRUE, "001100", loc_err);
err_sum := err_sum + loc_err;
-- read from a32 vme slave (supervisory 64-bit block transfer)
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_004c", x"0000_001b", 1, en_msg_0, TRUE, "000001"); -- set base address to 0xb000_0000
WAIT FOR 1 us;
rd64(terminal_in_1, terminal_out_1, x"b000_0040", x"1234_5678", 3, en_msg_0, TRUE, "001000", loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_slave_a322pcie", err_sum);
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE vme_slave_a162regs(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
VARIABLE am : std_logic_vector(5 DOWNTO 0);
BEGIN
print("Test MEN_01A021_00_IT_0060: VME A16 TO REGS");
-- A16 supervisory access
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0012", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_2000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_2014", x"0000_3412", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0013", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_3000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_3034", x"00ab_cd1f", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0014", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_4000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_4048", x"0000_7914", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0015", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_5000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_500c", x"0000_005a", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0016", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_6000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_6004", x"0000_00ab", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0017", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_7000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_701c", x"0000_0007", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0018", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_8000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_8028", x"ffff_f000", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0019", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_9000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_9000", x"0000_0007", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001a", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_a000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_a020", x"0000_0056", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001b", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_b000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_b038", x"0000_0037", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001c", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_c000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_c03c", x"0000_0037", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001d", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_d000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_d040", x"1234_5678", 1, en_msg_0, TRUE, "101101");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001e", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_e000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_e044", x"9abc_def0", 1, en_msg_0, TRUE, "101101");
-- read back
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001e", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_3412", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"00ab_cd1f", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_7914", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_005a", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0004", x"0000_00ab", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0007", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0028", x"ffff_f000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0000", x"0000_0007", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0020", x"0000_0056", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0038", x"0000_0037", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_003c", x"0000_0037", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0040", x"1234_5678", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0044", x"9abc_def0", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A16 non-privileged access
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_001f", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_f000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_f014", x"0000_1214", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_f030", x"0000_0010", 1, en_msg_0, TRUE, "101001");-- set base address to 0x0000_0000
wr32(terminal_in_1, terminal_out_1, x"0000_0034", x"00ab_ab0d", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0048", x"0000_6508", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_000c", x"0000_004b", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0004", x"0000_003c", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_001c", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0028", x"5678_9000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0000", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0020", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0038", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_003c", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0040", x"8765_4321", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_0044", x"0fed_cba9", 1, en_msg_0, TRUE, "101001");
-- read back
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0010", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_1214", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0034", x"00ab_ab0d", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0048", x"0000_6508", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_004b", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0004", x"0000_003c", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0028", x"5678_9000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0020", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0038", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_003c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0040", x"8765_4321", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0044", x"0fed_cba9", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- A16 non-privileged access
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0030", x"0000_0012", 1, en_msg_0, TRUE, "000001"); -- set base address to 0x0000_2000
WAIT FOR 1 us;
wr32(terminal_in_1, terminal_out_1, x"0000_2014", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2034", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2048", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_200c", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2004", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_201c", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2028", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2000", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2020", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2038", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_203c", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2040", x"0000_0000", 1, en_msg_0, TRUE, "101001");
wr32(terminal_in_1, terminal_out_1, x"0000_2044", x"0000_0000", 1, en_msg_0, TRUE, "101001");
err := err_sum;
print_err("vme_slave_a162regs", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_dma_sram2sram(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0140: VME DMA: SRAM TO SRAM ");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2sram): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- test data in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0004", x"1111_1111", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0004", x"1111_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"2222_2222", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0008", x"2222_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_000c", x"3333_3333", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_000c", x"3333_3333", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0010", x"4444_4444", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0010", x"4444_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- clear destination in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0100", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_010c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0110", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0114", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0118", x"0000_0000", 1, en_msg_0, TRUE, "000001");
-- config buffer descriptor
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0000_0108", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0000_0108", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0004", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0004", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_1001", 1, en_msg_0, TRUE, "000001"); -- source=sram dest=sram inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_1001", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- start transfer
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2sram): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2sram: dma irq NOT asserted");
END IF;
-- check destination
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0100", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0104", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0108", x"1111_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_010c", x"2222_2222", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0110", x"3333_3333", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0114", x"4444_4444", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0118", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check control reg for irq asserted
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0006", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma_sram2sram: dma irq asserted");
END IF;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
WAIT FOR 500 ns;
err := err_sum;
print_err("vme_dma_sram2sram", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_dma_sram2pci(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE adr : std_logic_vector(31 DOWNTO 0);
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0150: DMA: SRAM TO PCIe AND back");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2pci): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- test data in sram
FOR i IN 0 TO 255 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + (4*i), x"00000000" + (4*i), 1, en_msg_0, TRUE, "000001");
END LOOP;
-- program dma: sram2pci
adr := x"000f_f900";
dat := x"00000000";
FOR i IN 0 TO 15 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"0", dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"4", dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"8", x"0000000f", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"00014000", 1, en_msg_0, TRUE, "000001");
dat := dat + x"40";
adr := adr + x"10";
END LOOP;
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"00014001", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"2c", x"00000003", 1, en_msg_0, TRUE, "000001");
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2pci): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-----------------------------------------------------
-- program dma: sram2pci
adr := x"000f_f900";
dat := x"00000000";
FOR i IN 0 TO 15 LOOP
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"0", x"0000_0100" + dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"4", dat, 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"8", x"0000000f", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + adr+ x"c", x"00041000", 1, en_msg_0, TRUE, "000001");
dat := dat + x"40";
adr := adr + x"10";
END LOOP;
wr32(terminal_in_0, terminal_out_0, SRAM + adr - x"10" + x"c", x"00041001", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"2c", x"00000003", 1, en_msg_0, TRUE, "000001");
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2pci): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
err := err_sum;
print_err("vme_dma_sram2pci", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_dma_sram2a32d32(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0120: VME DMA: SRAM TO VME A32D32 AND back");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2a32d32): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- test data in sram
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0208", x"3121_1101", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0208", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_020c", x"3222_1202", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_020c", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0210", x"3323_1303", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0210", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0214", x"3424_1404", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0214", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- set A32 address extension
-- wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001"); -- if generic USE_LONGADD=false
-- rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001", loc_err);
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- clear destination in VME_A24D32
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0004", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0010", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0014", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001");
-- clear destination in SRAM
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0300", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_030c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0310", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0314", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_02fc", x"0000_0000", 1, en_msg_0, TRUE, "000001");
-- config buffer descriptor #1 SRAM => VME_A24D32
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"3000_0004", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"3000_0004", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0208", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0208", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_2060", 1, en_msg_0, TRUE, "000001"); -- source=sram dest=A24D32 inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_2060", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- config buffer descriptor #2 VME_A24D32 => SRAM
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0300", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0300", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"3000_0004", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"3000_0004", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_1061", 1, en_msg_0, TRUE, "000001"); -- source=A24D32 dest=sram inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_1061", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- start transfer
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2a32d32): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2a32d32: dma irq NOT asserted");
END IF;
-- check control reg for irq asserted
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0006", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check destination VME_A24D32
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0004", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000c", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0010", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0014", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- check destination SRAM
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_02fc", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0300", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_030c", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0310", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
-- clear irq request
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '1' THEN
print_time("ERROR vme_dma_sram2a32d32: dma irq asserted");
END IF;
-- check control reg for end of dma
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
WAIT FOR 500 ns;
err := err_sum;
print_err("vme_dma_sram2a32d32", err_sum);
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE vme_dma_sram2a32d64(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
variable var_check_msi_nbr : natural := 0;
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0130: VME DMA: SRAM TO VME A32D64 AND back");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_dma_sram2a32d64): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
print(" test data in sram");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0208", x"3121_1101", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0208", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_020c", x"3222_1202", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_020c", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0210", x"3323_1303", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0210", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0214", x"3424_1404", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0214", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" set A32 address extension");
-- wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001"); -- if generic USE_LONGADD=false
-- rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001", loc_err);
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" clear destination in VME_A32D32");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0004", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0010", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0014", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001");
print(" clear destination in SRAM");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0300", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_030c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0310", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_0314", x"0000_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, SRAM + x"0000_02fc", x"0000_0000", 1, en_msg_0, TRUE, "000001");
print(" config buffer descriptor #1 SRAM => VME_A32D64");
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"3000_0008", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"3000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0208", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0208", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_20e0", 1, en_msg_0, TRUE, "000001"); -- source=sram dest=A32D64 inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0001_20e0", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" config buffer descriptor #2 VME_A32D64 => SRAM");
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0300", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F910", x"0000_0300", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"3000_0008", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F914", x"3000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F918", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_10e1", 1, en_msg_0, TRUE, "000001"); -- source=A32D64 dest=sram inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F91c", x"0002_10e1", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" start DMA transfer");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- start transfer
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
--wait_on_irq_assert(0);
var_check_msi_nbr := 9;
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => var_check_msi_nbr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_dma_sram2a32d64): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2a32d64: dma irq NOT asserted");
END IF;
print(" check control reg for irq asserted");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0006", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" check destination VME_A32D32");
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0000", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0004", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000c", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0010", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0014", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0018", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" check destination SRAM");
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_02fc", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0300", x"3121_1101", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0304", x"3222_1202", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0308", x"3323_1303", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_030c", x"3424_1404", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, SRAM + x"0000_0310", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" clear irq request");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0004", 1, en_msg_0, TRUE, "000001");
IF irq_req(13) = '0' THEN
print_time("ERROR vme_dma_sram2a32d64: dma irq asserted");
END IF;
print(" check control reg for end of dma");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
WAIT FOR 500 ns;
err := err_sum;
print_err("vme_dma_sram2a32d64", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_buserror(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE irq_req_berr : integer;
VARIABLE irq_req_dma : integer;
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0160: VME Bus Error");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_buserror): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
--irq_req_berr := 12;
irq_req_berr := 8;
--irq_req_dma := 13;
irq_req_dma := 9;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print (" VME A16/D16 single read access");
rd32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_0000", x"0000_ffff", 1, en_msg_0, FALSE, "000001", loc_err);
--wait_on_irq_assert(0);
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => irq_req_berr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_buserror): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(irq_req_berr) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001");
--wait_on_irq_deassert(0);
IF irq_req(irq_req_berr) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print (" VME A24/D16 single read access");
rd32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0000_0000", x"0000_ffff", 1, en_msg_0, FALSE, "000001", loc_err);
--wait_on_irq_assert(0);
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => irq_req_berr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_buserror): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(irq_req_berr) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001");
--wait_on_irq_deassert(0);
IF irq_req(irq_req_berr) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print (" VME A32/D32 single read access");
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"0000_0000", x"ffff_ffff", 1, en_msg_0, FALSE, "000001", loc_err);
--wait_on_irq_assert(0);
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => irq_req_berr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_buserror): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(irq_req_berr) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001");
--wait_on_irq_deassert(0);
IF irq_req(irq_req_berr) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print (" VME DMA A24/D32 read access");
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0000_0000", 1, en_msg_0, TRUE, "000001"); -- dest adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F900", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0000", 1, en_msg_0, TRUE, "000001"); -- source adr
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F904", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- size
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F908", x"0000_0003", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0002_10e1", 1, en_msg_0, TRUE, "000001"); -- source=A24D32 dest=sram inc
rd32(terminal_in_0, terminal_out_0, SRAM + x"000F_F90c", x"0002_10e1", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
print(" start DMA transfer");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0003", 1, en_msg_0, TRUE, "000001"); -- start transfer
-- check for buserror interrupt
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => irq_req_berr,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_buserror): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(irq_req_berr) = '0' THEN
print_time("ERROR vme_dma_sram2pci: buserror irq NOT asserted");
END IF;
-- check for DMA interrupt
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => irq_req_dma,
msi_expected => var_msi_expected
);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_buserror): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(irq_req_dma) = '0' THEN
print_time("ERROR vme_dma_sram2pci: dma irq NOT asserted");
END IF;
WAIT FOR 1 us;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_001e", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_000c", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_000c", 1, en_msg_0, TRUE, "000001");
--wait_on_irq_deassert(0);
IF irq_req(irq_req_dma) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
IF irq_req(irq_req_berr) = '1' THEN
print_time("ERROR vme_dma_sram2pci: dma irq asserted");
END IF;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0008", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_002c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
err := err_sum;
print_err("vme_buserror", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_master_windows(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
BEGIN
print("Test MEN_01A021_00_IT_0070: VME A16D16");
wr16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1000", x"0000_1111", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1002", x"2222_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1010", x"aa88_11ff", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1100", x"1234_5678", 10, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1010", x"aa88_11ff", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1100", x"1234_5678", 10, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1002", x"2222_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1000", x"0000_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A16D32");
wr16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1004", x"0000_1131", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1006", x"2232_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1020", x"cafe_affe", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1020", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1200", x"cafe_affe", 12, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1200", x"cafe_affe", 12, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1006", x"2232_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1004", x"0000_1131", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A24D16");
wr16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0008", x"0000_4455", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_000a", x"6677_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0030", x"1234_5678", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0030", x"1234_5678", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0040", x"1234_5678", 14, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0040", x"1234_5678", 14, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_000a", x"6677_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0008", x"0000_4455", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A24D32");
wr16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A32D32");
-- access to vme slave simmodel offset 0x3000_0000
-- depending on the generic settings, register LONGADD will be used differently:
-- -- Generic USE_LONGADD=false
-- wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0001", 1, en_msg_0, TRUE, "000001");
-- Generic USE_LONGADD=true and LONGADD_SIZE=3
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_001c", x"0000_0020", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A32D32 + x"1000_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME CR/CSR");
wr16(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001");
wr8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0100", x"4433_2211", 1, en_msg_0, TRUE, "000001");
wr8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0101", x"0000_2200", 1, en_msg_0, TRUE, "000001");
wr8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0102", x"0033_0000", 1, en_msg_0, TRUE, "000001");
wr8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0103", x"4400_0000", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0300", x"cafe_affe", 8, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0100", x"0000_0011", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0101", x"0000_2200", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0102", x"0033_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd8(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0103", x"4400_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_CRCSR + x"0040_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
err := err_sum;
print_err("vme_master_windows", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_arbitration(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL hreset_n : OUT std_logic;
SIGNAL slot1 : OUT boolean;
SIGNAL en_clk : OUT boolean;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
BEGIN
print("Test MEN_01A021_00_IT_0100: VME vme_arbitration ");
-- VME Arbitration:
-- powerup board
slot1 <= TRUE;
hreset_n <= '0';
en_clk <= FALSE; -- switch off clk in order to let the PLL relock => startup reset will be generated which clears sysc bit
WAIT FOR 500 ns;
en_clk <= TRUE;
WAIT FOR 50 ns;
hreset_n <= '1';
WAIT FOR 2 us;
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0002", 1, en_msg_0, TRUE, "000001"); -- set RWD
vme_arbiter(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- powerup board
slot1 <= FALSE;
hreset_n <= '0';
en_clk <= FALSE; -- switch off clk in order to let the PLL relock => startup reset will be generated which clears sysc bit
WAIT FOR 500 ns;
en_clk <= TRUE;
WAIT FOR 50 ns;
hreset_n <= '1';
WAIT FOR 2 us;
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0002", 1, en_msg_0, TRUE, "000001"); -- set RWD
vme_arbiter(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
--
-- VME Arbitration:
-- powerup board
slot1 <= TRUE;
hreset_n <= '0';
en_clk <= FALSE; -- switch off clk in order to let the PLL relock => startup reset will be generated which clears sysc bit
WAIT FOR 500 ns;
en_clk <= TRUE;
WAIT FOR 50 ns;
hreset_n <= '1';
WAIT FOR 2 us;
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0000", 1, en_msg_0, TRUE, "000001"); -- clear RWD
vme_arbiter(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
-- powerup board
slot1 <= FALSE;
hreset_n <= '0';
en_clk <= FALSE; -- switch off clk in order to let the PLL relock => startup reset will be generated which clears sysc bit
WAIT FOR 500 ns;
en_clk <= TRUE;
WAIT FOR 50 ns;
hreset_n <= '1';
WAIT FOR 2 us;
--! procedure to initialize the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be initialized
--! @param io_add start address for the BFM internal I/O space
--! @param mem32_addr start address for the BFM internal MEM32 space
--! @param mem64_addr start address for the BFM internal MEM64 space
--! @param requester_id defines the requester ID that is used for every BFM transfer
--! @param max_payloadsize defines the maximum payload size for every write request
init_bfm(0, x"0000_0000", SIM_BAR0, x"0000_0000_0000_0000", x"0000", 256);
--! procedure to configure the BFM
--! @param bfm_inst_nbr number of the BFM instance that will be configured
--! @param max_payload_size maximum payload size for write requests
--! @param max_read_size maximum payload size for read requests
--! @param bar0 BAR0 settings
--! @param bar1 BAR1 settings
--! @param bar2 BAR2 settings
--! @param bar3 BAR3 settings
--! @param bar4 BAR4 settings
--! @param bar5 BAR5 settings
--! @param cmd_status_reg settings for the command status register
--! @param ctrl_status_reg settings for the control status register
configure_bfm(terminal_in => terminal_in_0, terminal_out => terminal_out_0, bar0_addr => BAR0, bar1_addr => BAR1, bar2_addr => BAR2, bar3_addr => BAR3, bar4_addr => BAR4, bar5_addr => BAR5, txt_out => en_msg_0);
WAIT FOR 3 us;
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0010", x"0000_0000", 1, en_msg_0, TRUE, "000001"); -- set RWD
vme_arbiter(terminal_in_0, terminal_out_0, terminal_in_1, terminal_out_1, en_msg_0, loc_err);
err_sum := err_sum + loc_err;
err := err_sum;
print_err("vme_arbitration", err_sum);
END PROCEDURE;
----------------------------------------------------------------------------------------------
PROCEDURE vme_arbiter(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
BEGIN
print("Test MEN_01A021_00_IT_0100: VME Arbitration ");
wr32(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0014", x"0000_1010", 1, en_msg_0, TRUE, "000001"); -- activate A24 vme slave
WAIT FOR 1 us;
print("Test: VME A16D16");
wr16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1000", x"0000_1111", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_1, terminal_out_1, x"0100_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wr16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1002", x"2222_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_1, terminal_out_1, x"0100_0008", x"1111_1111", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wr32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1010", x"aa88_11ff", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_1, terminal_out_1, x"0100_0004", x"cafe_affe", 1, en_msg_0, TRUE, "111001", loc_err); -- read from a24 vme slave
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1010", x"aa88_11ff", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1002", x"2222_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0100_0008", x"1111_1111", 1, en_msg_0, TRUE, "111001", loc_err); -- read from a24 vme slave
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A16D16 + x"0000_1000", x"0000_1111", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A16D32");
wr16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1004", x"0000_1131", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_1, terminal_out_1, x"0100_0014", x"2222_2222", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wr16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1006", x"2232_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_1, terminal_out_1, x"0100_0018", x"3333_3333", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wr32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1020", x"cafe_affe", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1020", x"cafe_affe", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_1, terminal_out_1, x"0100_001c", x"4444_4444", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
rd16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1006", x"2232_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_1, terminal_out_1, x"0100_0020", x"5555_5555", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
rd16(terminal_in_0, terminal_out_0, VME_A16D32 + x"0000_1004", x"0000_1131", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wr32(terminal_in_1, terminal_out_1, x"0100_0024", x"6666_6666", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wr32(terminal_in_1, terminal_out_1, x"0100_0028", x"7777_7777", 1, en_msg_0, TRUE, "111001"); -- write to a24 vme slave
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A24D16");
wr16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0008", x"0000_4455", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_1, terminal_out_1, x"0100_0014", x"2222_2222", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
wr16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_000a", x"6677_0000", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_1, terminal_out_1, x"0100_0018", x"3333_3333", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
wr32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0030", x"1234_5678", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_1, terminal_out_1, x"0100_001c", x"4444_4444", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
rd32(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0030", x"1234_5678", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0100_0020", x"5555_5555", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_000a", x"6677_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0100_0024", x"6666_6666", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D16 + x"0020_0008", x"0000_4455", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd32(terminal_in_1, terminal_out_1, x"0100_0028", x"7777_7777", 1, en_msg_0, TRUE, "111001", loc_err); -- write to a24 vme slave
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
print("Test: VME A24D32");
wr16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001");
wr16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001");
wr32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001");
rd32(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0030", x"5555_6666", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_000a", x"3434_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
rd16(terminal_in_0, terminal_out_0, VME_A24D32 + x"0020_0008", x"0000_7878", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
wait_for(terminal_in_1, terminal_out_1, 10, TRUE);
err := err_sum;
print_err("vme_arbiter", err_sum);
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE vme_irq_rcv(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
SIGNAL irq_req : IN std_logic_vector(16 DOWNTO 0);
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
variable var_msi_expected : std_logic_vector(31 downto 0) := (others => '0');
variable var_success : boolean := false;
variable var_msi_allocated : std_logic_vector(2 downto 0) := (others => '0');
constant MSI_SHMEM_ADDR : natural := 2096896; -- := x"1FFF00" at upper end of shared memory
constant MSI_DATA_VAL : std_logic_vector(15 downto 0) := x"3210";
BEGIN
print("Test MEN_01A021_00_IT_0090: Interrupt Handler");
var_success := false;
bfm_configure_msi(
msi_addr => MSI_SHMEM_ADDR,
msi_data => MSI_DATA_VAL,
msi_allocated => var_msi_allocated,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then
print_now("ERROR(vme_irq_rcv): error while executing bfm_configure_msi() - MSI NOT configured, MSI behavior is UNDEFINED!");
print(" ---> test case skipped");
end if;
else
-- enable receiving interrupts
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_00ff", 1, en_msg_0, TRUE, "000001");
rd8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_00ff", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 150 ns;
FOR i IN 1 TO 7 LOOP
bfm_calc_msi_expected(
msi_allocated => var_msi_allocated,
msi_data => MSI_DATA_VAL,
msi_nbr => i,
msi_expected => var_msi_expected
);
irq_vme_slv (vme_slv_in, vme_slv_out, i, x"00"+i);
var_success := false;
bfm_poll_msi(
track_msi => 1,
msi_addr => MSI_SHMEM_ADDR,
msi_expected => var_msi_expected,
txt_out => en_msg_0,
success => var_success
);
if not var_success then
err_sum := err_sum +1;
if en_msg_0 >= 1 then print_now("ERROR(vme_irq_rcv): error while executing bfm_poll_msi()"); end if;
end if;
IF irq_req(i+4) = '0' THEN -- acfail + vme_irq is irq_req(11:5)
print_time("ERROR vme_irq_rcv: wrong irq asserted");
END IF;
dat:=x"00"+i & x"00"+i & x"00"+i & x"00"+i;
rd8(terminal_in_0, terminal_out_0, VME_IACK + (2*i) + 1, dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 300 ns;
END LOOP;
-- disable receiving interrupts
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_0000", 1, en_msg_0, TRUE, "000001");
rd8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_000c", x"0000_0000", 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
end if;
err := err_sum;
print_err("vme_irq_rcv", err_sum);
END PROCEDURE;
------------------------------------------------------------------------------------------
PROCEDURE vme_irq_trans(
SIGNAL terminal_in_0 : IN terminal_in_type;
SIGNAL terminal_out_0 : OUT terminal_out_type;
SIGNAL terminal_in_1 : IN terminal_in_type;
SIGNAL terminal_out_1 : OUT terminal_out_type;
SIGNAL vme_slv_in : OUT vme_slv_in_type;
SIGNAL vme_slv_out : IN vme_slv_out_type;
en_msg_0 : integer;
err : OUT natural
) IS
VARIABLE loc_err : integer:=0;
VARIABLE err_sum : integer:=0;
VARIABLE dat : std_logic_vector(31 DOWNTO 0);
BEGIN
print("Test MEN_01A021_00_IT_0080: Interrupter");
FOR i IN 1 TO 7 LOOP
IF vme_slv_out.irq(i) = '0' THEN
print_time("ERROR: VME irqs should NOT be active!");
END IF;
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0000", x"0000_0008" + i, 1, en_msg_0, TRUE, "000001"); -- set interrupt request on line x
wr8(terminal_in_0, terminal_out_0, VME_REGS + x"0000_0004", x"0000_0000" + i, 1, en_msg_0, TRUE, "000001"); -- set interrupt id
wl: FOR j IN 0 TO 1000 LOOP
IF vme_slv_out.irq(i) = '0' THEN
print_time("exit");
exit wl;
END IF;
WAIT FOR 10 ns;
END LOOP;
dat:=x"00"+i & x"00"+i & x"00"+i & x"00"+i;
rd8_iack(terminal_in_1, terminal_out_1, VME_IACK + (2*i), dat, 1, en_msg_0, TRUE, "000001", loc_err);
err_sum := err_sum + loc_err;
WAIT FOR 100 ns;
END LOOP;
err := err_sum;
print_err("vme_irq_trans", err_sum);
END PROCEDURE;
procedure configure_bfm(
signal terminal_in : in terminal_in_type;
signal terminal_out : out terminal_out_type;
bar0_addr : std_logic_vector(31 downto 0);
bar1_addr : std_logic_vector(31 downto 0);
bar2_addr : std_logic_vector(31 downto 0);
bar3_addr : std_logic_vector(31 downto 0);
bar4_addr : std_logic_vector(31 downto 0);
bar5_addr : std_logic_vector(31 downto 0);
txt_out : integer
) is
begin
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR0");
end if;
wr32(terminal_in, terminal_out, x"0000_0000", bar0_addr, 1, txt_out, TRUE, "000011");
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR1");
end if;
wr32(terminal_in, terminal_out, x"0000_0001", bar1_addr, 1, txt_out, TRUE, "000011");
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR2");
end if;
wr32(terminal_in, terminal_out, x"0000_0002", bar2_addr, 1, txt_out, TRUE, "000011");
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR3");
end if;
wr32(terminal_in, terminal_out, x"0000_0003", bar3_addr, 1, txt_out, TRUE, "000011");
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR4");
end if;
wr32(terminal_in, terminal_out, x"0000_0004", bar4_addr, 1, txt_out, TRUE, "000011");
if txt_out >= 2 then -- print info
print("terminal_pkg->configure_bfm(): set address for BAR5");
end if;
wr32(terminal_in, terminal_out, x"0000_0005", bar5_addr, 1, txt_out, TRUE, "000011");
end procedure configure_bfm;
END;
|
gpl-3.0
|
80315c2462a18b73193c0311b725eb8a
| 0.522828 | 3.271782 | false | false | false | false |
Ttl/bf_cpu
|
testbenches/cpu_branchtest_tb.vhd
| 1 | 3,030 |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.all;
ENTITY cpu_branchtest_tb IS
END cpu_branchtest_tb;
ARCHITECTURE behavior OF cpu_branchtest_tb IS
signal clk, reset, tx, rx : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
signal uart_tx_req, uart_tx_end, uart_rx_ready : std_logic;
signal uart_tx_data, uart_rx_data : std_logic_vector(7 downto 0);
BEGIN
-- Component Instantiation
uut: entity work.cpu
Generic map ( INSTRUCTIONS => "scripts/branch.mif"
)
Port map(clk => clk,
reset => reset,
tx => rx,
rx => tx
);
uart1 : entity work.uart
Generic map(
CLK_FREQ => 100,
SER_FREQ => 1000000,
PARITY_BIT => false
)
Port map (
clk => clk,
rst => reset,
rx => rx,
tx => tx,
tx_req => uart_tx_req,
tx_end => uart_tx_end,
tx_data => uart_tx_data,
rx_ready => uart_rx_ready,
rx_data => uart_rx_data
);
-- Print received bytes
uart_process : process
begin
wait until uart_rx_ready = '1';
wait for clk_period;
if to_integer(unsigned(uart_rx_data)) > 31 and to_integer(unsigned(uart_rx_data)) < 127 then
report "Received ASCII: "&character'image(character'val(to_integer(unsigned(uart_rx_data))));
else
report "Received Dec: "&integer'image(to_integer(unsigned(uart_rx_data)));
end if;
end process;
-- Test received bytes
test_process : process
begin
wait until uart_rx_ready = '1';
wait for clk_period;
assert to_integer(unsigned(uart_rx_data)) = 255 report "First msg incorrect" severity failure;
wait until uart_rx_ready = '1';
wait for clk_period;
assert to_integer(unsigned(uart_rx_data)) = 0 report "Second msg incorrect" severity failure;
wait until uart_rx_ready = '1';
wait for clk_period;
assert to_integer(unsigned(uart_rx_data)) = 0 report "Third msg incorrect" severity failure;
wait until uart_rx_ready = '1';
assert false report "Received too many messages" severity failure;
end process;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Test Bench Statements
tb : PROCESS
BEGIN
reset <= '1';
uart_tx_req <= '0';
wait for 100 ns; -- wait until global set/reset completes
reset <= '0';
uart_tx_req <= '1';
uart_tx_data <= x"50"; -- P
wait for clk_period;
uart_tx_req <= '0';
wait until uart_tx_end = '1';
wait for clk_period;
uart_tx_req <= '1';
uart_tx_data <= x"00";
wait for clk_period;
uart_tx_req <= '0';
wait for 19us;
assert false report "Completed succesfully" severity failure;
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
|
lgpl-3.0
|
84f2089b450c8de4388563d472dbb978
| 0.59505 | 3.53972 | false | true | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/SELECTOR.vhd
| 2 | 4,519 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SELECTOR is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
EQUALITY : OUT STD_LOGIC;
sel_A_0 : OUT STD_LOGIC;
sel_B_0 : OUT STD_LOGIC;
sel_C_0 : OUT STD_LOGIC;
sel_D_0 : OUT STD_LOGIC;
sel_E_0 : OUT STD_LOGIC;
sel_W_0 : OUT STD_LOGIC;
sel_A_1 : OUT STD_LOGIC;
sel_B_1 : OUT STD_LOGIC;
sel_C_1 : OUT STD_LOGIC;
sel_D_1 : OUT STD_LOGIC;
sel_E_1 : OUT STD_LOGIC;
sel_W_1 : OUT STD_LOGIC
);
end;
architecture input_select of SELECTOR is
signal opcode_sig : std_logic_vector (5 downto 0) := "000000";
signal serviced_vector : std_logic_vector (5 downto 0) := "000000";
signal equality_vector : std_logic_vector (5 downto 0) := "111111";
signal equality_extend : std_logic_vector (5 downto 0) := "111111";
signal equality_signal : std_logic := '1';
signal equality_buff : std_logic;
signal to_service_next : std_logic_vector (5 downto 0) := "000000";
signal hazard_to_mask : std_logic_vector (5 downto 0) := "111111";
signal hazard_mask : std_logic_vector (5 downto 0) := "111111";
signal SEL_A_0_sig : std_logic;
signal SEL_B_0_sig : std_logic;
signal SEL_C_0_sig : std_logic;
signal SEL_D_0_sig : std_logic;
signal SEL_E_0_sig : std_logic;
signal SEL_W_0_sig : std_logic;
signal SEL_A_1_sig : std_logic;
signal SEL_B_1_sig : std_logic;
signal SEL_C_1_sig : std_logic;
signal SEL_D_1_sig : std_logic;
signal SEL_E_1_sig : std_logic;
signal SEL_W_1_sig : std_logic;
begin
sel_A_0_sig <= opcode_sig(5) and RESET_n;
sel_B_0_sig <= opcode_sig(4) and (not opcode_sig(5)) and RESET_n;
sel_C_0_sig <= opcode_sig(3) and (not (opcode_sig(5) or opcode_sig(4))) and RESET_n;
sel_D_0_sig <= opcode_sig(2) and (not (opcode_sig(5) or opcode_sig(4) or opcode_sig(3))) and RESET_n;
sel_E_0_sig <= opcode_sig(1) and (not (opcode_sig(5) or opcode_sig(4) or opcode_sig(3) or opcode_sig(2))) and RESET_n;
sel_W_0_sig <= opcode_sig(0) and (not (opcode_sig(5) or opcode_sig(4) or opcode_sig(3) or opcode_sig(2) or opcode_sig(1))) and RESET_n;
sel_W_1_sig <= opcode_sig(0) and RESET_n;
sel_E_1_sig <= opcode_sig(1) and (not opcode_sig(0)) and RESET_n;
sel_D_1_sig <= opcode_sig(2) and (not (opcode_sig(1) or opcode_sig(0))) and RESET_n;
sel_C_1_sig <= opcode_sig(3) and (not (opcode_sig(2) or opcode_sig(1) or opcode_sig(0))) and RESET_n;
sel_B_1_sig <= opcode_sig(4) and (not (opcode_sig(3) or opcode_sig(2) or opcode_sig(1) or opcode_sig(0))) and RESET_n;
sel_A_1_sig <= opcode_sig(5) and (not (opcode_sig(4) or opcode_sig(3) or opcode_sig(2) or opcode_sig(1) or opcode_sig(0))) and RESET_n;
-- opcode_sig <= OPCODE and hazard_mask;
-- opcode_sig <= OPCODE;
opcode_sig <= (OPCODE(5) and hazard_mask(5)) & (OPCODE(4) and hazard_mask(4)) & (OPCODE(3) and hazard_mask(3)) &
(OPCODE(2) and hazard_mask(2)) & (OPCODE(1) and hazard_mask(1)) & (OPCODE(0) and hazard_mask(0));
serviced_vector <= (sel_A_0_sig or sel_A_1_sig ) &
(sel_B_0_sig or sel_B_1_sig ) &
(sel_C_0_sig or sel_C_1_sig ) &
(sel_D_0_sig or sel_D_1_sig ) &
(sel_E_0_sig or sel_E_1_sig ) &
(sel_W_0_sig or sel_W_1_sig );
to_service_next <= serviced_vector xor opcode_sig;
equality_vector <= opcode_sig xor (not serviced_vector);
hazard_to_mask <= to_service_next xor equality_extend;
hazard_latching : process (CLK, RESET_n) begin
if (RESET_n = '0') then
hazard_mask <= "111111";
elsif (rising_edge(CLK)) then
hazard_mask <= hazard_to_mask;
end if;
end process;
equality_extend <= equality_signal & equality_signal & equality_signal & equality_signal & equality_signal & equality_signal;
equality_signal <= equality_vector(5) and equality_vector(4) and equality_vector(3) and equality_vector(2) and equality_vector(1) and equality_vector(0);
-- derp : process (CLK) begin
-- if (falling_edge(CLK)) then
-- equality_buff <= equality_signal;
-- end if;
-- end process;
EQUALITY <= equality_signal; --used to be equality_signal
SEL_A_0 <= SEL_A_0_sig;
SEL_B_0 <= SEL_B_0_sig;
SEL_C_0 <= SEL_C_0_sig;
SEL_D_0 <= SEL_D_0_sig;
SEL_E_0 <= SEL_E_0_sig;
SEL_W_0 <= SEL_W_0_sig;
SEL_A_1 <= SEL_A_1_sig;
SEL_B_1 <= SEL_B_1_sig;
SEL_C_1 <= SEL_C_1_sig;
SEL_D_1 <= SEL_D_1_sig;
SEL_E_1 <= SEL_E_1_sig;
SEL_W_1 <= SEL_W_1_sig;
end;
|
gpl-2.0
|
eebb3cfa828ab3f1d03b9490d5ee0e61
| 0.619606 | 2.488436 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNLWRZWTQF.vhd
| 8 | 852 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNLWRZWTQF is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNLWRZWTQF is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 3 ,
width_inr=> 0,
width_outl=> 3,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(2 downto 0) => input,
yout => output
);
end architecture;
|
mit
|
50881730b54f8cf4afd07f5b4945f746
| 0.656103 | 3.179104 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_delay.vhd
| 2 | 1,948 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNVJUPFOX3 is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "000000000000000000000000";
WIDTH : positive := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector(24-1 downto 0);
output : out std_logic_vector(24-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_delay_GNVJUPFOX3;
begin
alt_dspbuilder_delay_GNVJUPFOX3_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000000000") and (WIDTH = 24)) generate
inst_alt_dspbuilder_delay_GNVJUPFOX3_0: alt_dspbuilder_delay_GNVJUPFOX3
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "000000000000000000000000", WIDTH => 24)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000000000") and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
0b7723df678ff87d7271e776a59c301c
| 0.691992 | 3.370242 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_testbench_salt_GNDBMPYDND.vhd
| 20 | 1,717 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNDBMPYDND is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 1) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= '0';
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic(s(1));
end if ;
end if ;
end process ;
end architecture;
|
mit
|
5440c1e50856d78b9ef962995a5e8702
| 0.626674 | 3.033569 | false | false | false | false |
piliguori/Linear-Regression
|
Src/GenericBuffer.vhd
| 1 | 2,708 |
--! @file GenericBuffer.vhd
--! @author Salvatore Barone <[email protected]>
--! Alfonso Di Martino <[email protected]>
--! Pietro Liguori <[email protected]>
--! @date 17-04-2017
--!
--! Copyright 2017 Salvatore Barone <[email protected]> <br>
--! Alfonso Di Martino <[email protected]> <br>
--! Pietro Liguori <[email protected]> <br>
--!
--! This file is part of Linear-Regression.
--!
--! Linear-Regression is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Linear-Regression is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--! @addtogroup GenericBuffer
--! @{
-- Changelog
-- 17-04-2017: creazione del file e prima implementazione
-- 27-4-2017: Implementazione di architettura Falling Edge su clock
-- 09-05-2017: Unione delle architetture in una sola
-- - Aggiunto parametro di configurazione "edge", che permette di scegliere quale sia il fronte attivo del clock
library ieee;
use ieee.std_logic_1164.all;
--! @brief Registro di dimensione generica
entity GenericBuffer is
Generic ( width : natural := 8; --! numero di bit del registro
edge : std_logic := '1'); --! fronte di attivo del clock:
--! - '1': fronte di salita
--! - '0': fronte di discesa
Port ( clock : in std_logic; --! segnale di clock
reset_n : in std_logic; --! reset asincrono, attivo basso
load : in std_logic; --! segnale di load, quando '1' l'uscita (data_out) segue l'ingresso (data_in)
data_in : in std_logic_vector(width-1 downto 0); --! ingresso del registro
data_out : out std_logic_vector(width-1 downto 0)); --! uscita del registro
end GenericBuffer;
--! Implementazione behavioral di GenericBuffer
architecture Behavioral of GenericBuffer is
signal tmp : std_logic_vector(width-1 downto 0) := (others => '0');
begin
data_out <= tmp;
process(clock, reset_n, load, data_in)
begin
if reset_n = '0' then
tmp <= (others => '0');
elsif clock'event and clock = edge then
if (load = '1') then
tmp <= data_in;
end if;
end if;
end process;
end Behavioral;
--! @}
|
gpl-3.0
|
832f35ea218524a1ed7a1c8eb5afb1fe
| 0.689069 | 3.359801 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNMYKU6OLE.vhd
| 4 | 877 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNMYKU6OLE is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNMYKU6OLE is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 4 + 1 ,
width_inr=> 12,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(15 downto 0) => input,
xin(16) => '0', yout => output
);
end architecture;
|
mit
|
60f4b76ad9c1b8fc93a5a24133e52298
| 0.648803 | 3.088028 | false | false | false | false |
freecores/t48
|
rtl/vhdl/system/t8039_notri.vhd
| 1 | 7,191 |
-------------------------------------------------------------------------------
--
-- T8039 Microcontroller System
-- 8039 toplevel without tri-states
--
-- $Id: t8039_notri.vhd,v 1.5 2006-07-14 01:13:32 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8039_notri is
generic (
gate_port_input_g : integer := 1
);
port (
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_n_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic
);
end t8039_notri;
library ieee;
use ieee.numeric_std.all;
use work.t48_core_comp_pack.t48_core;
use work.t48_core_comp_pack.generic_ram_ena;
architecture struct of t8039_notri is
signal xtal3_s : std_logic;
signal dmem_addr_s : std_logic_vector( 7 downto 0);
signal dmem_we_s : std_logic;
signal dmem_data_from_s : std_logic_vector( 7 downto 0);
signal dmem_data_to_s : std_logic_vector( 7 downto 0);
signal pmem_data_s : std_logic_vector( 7 downto 0);
signal p1_in_s,
p1_out_s : std_logic_vector( 7 downto 0);
signal p2_in_s,
p2_out_s : std_logic_vector( 7 downto 0);
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- Check generics for valid values.
-----------------------------------------------------------------------------
-- pragma translate_off
assert gate_port_input_g = 0 or gate_port_input_g = 1
report "gate_port_input_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
-- no Program memory available
pmem_data_s <= (others => '0');
t48_core_b : t48_core
generic map (
xtal_div_3_g => 1,
register_mnemonic_g => 1,
include_port1_g => 1,
include_port2_g => 1,
include_bus_g => 1,
include_timer_g => 1,
sample_t1_state_g => 4
)
port map (
xtal_i => xtal_i,
xtal_en_i => xtal_en_i,
reset_i => reset_n_i,
t0_i => t0_i,
t0_o => t0_o,
t0_dir_o => t0_dir_o,
int_n_i => int_n_i,
ea_i => ea_i,
rd_n_o => rd_n_o,
psen_n_o => psen_n_o,
wr_n_o => wr_n_o,
ale_o => ale_o,
db_i => db_i,
db_o => db_o,
db_dir_o => db_dir_o,
t1_i => t1_i,
p2_i => p2_in_s,
p2_o => p2_out_s,
p2l_low_imp_o => p2l_low_imp_o,
p2h_low_imp_o => p2h_low_imp_o,
p1_i => p1_in_s,
p1_o => p1_out_s,
p1_low_imp_o => p1_low_imp_o,
prog_n_o => prog_n_o,
clk_i => xtal_i,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => dmem_addr_s,
dmem_we_o => dmem_we_s,
dmem_data_i => dmem_data_from_s,
dmem_data_o => dmem_data_to_s,
pmem_addr_o => open,
pmem_data_i => pmem_data_s
);
-----------------------------------------------------------------------------
-- Gate port 1 and 2 input bus with respetive output value
-----------------------------------------------------------------------------
gate_ports: if gate_port_input_g = 1 generate
p1_in_s <= p1_i and p1_out_s;
p2_in_s <= p2_i and p2_out_s;
end generate;
pass_ports: if gate_port_input_g = 0 generate
p1_in_s <= p1_i;
p2_in_s <= p2_i;
end generate;
p1_o <= p1_out_s;
p2_o <= p2_out_s;
ram_128_b : generic_ram_ena
generic map (
addr_width_g => 7,
data_width_g => 8
)
port map (
clk_i => xtal_i,
a_i => dmem_addr_s(6 downto 0),
we_i => dmem_we_s,
ena_i => vdd_s,
d_i => dmem_data_to_s,
d_o => dmem_data_from_s
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2006/06/21 01:02:35 arniml
-- replaced syn_ram with generic_ram_ena
--
-- Revision 1.3 2006/06/20 00:47:08 arniml
-- new input xtal_en_i
--
-- Revision 1.2 2005/11/01 21:38:10 arniml
-- wire signals for P2 low impedance marker issue
--
-- Revision 1.1 2004/12/03 19:42:34 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
fdddf9fbc24a2319fe8f3c2137a83c68
| 0.531776 | 3.323013 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_logical_bit_op_GNA5ZFEL7V.vhd
| 20 | 806 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic ( LogicalOp : string := "AltAND";
number_inputs : positive := 2);
port(
result : out std_logic;
data0 : in std_logic;
data1 : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
Begin
-- Logical Bit Operation - Simulink Block "LogicalBitOperator"
LogicalBitOperatori : alt_dspbuilder_SBitLogical generic map (
LPM_WIDTH => 2,
LOP => AltAND)
port map (
dataa(0) => data0,
dataa(1) => data1,
result => result);
end architecture;
|
mit
|
790d383db9f2922fb9f6e6d815b8abb1
| 0.67866 | 3.124031 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_if_statement_GNWHMBR6GA.vhd
| 4 | 1,493 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNWHMBR6GA is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "((a>zero) and (a<b)) or (a=c)";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNWHMBR6GA is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(((a>zero) and (a<b)) or (a=c)) ;
true <= result;
end architecture;
|
mit
|
945a7e5dba90bb9281e29f69714a59c3
| 0.617549 | 3.197002 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNKDE2NVCC.vhd
| 4 | 877 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNKDE2NVCC is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNKDE2NVCC is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 25,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture;
|
mit
|
13034b26bbc8683ec5c3717b4d6221e5
| 0.648803 | 3.077193 | false | false | false | false |
cathalmccabe/PYNQ
|
boards/ip/audio_codec_ctrl_v1.0/src/pselect_f.vhd
| 4 | 12,490 |
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.common_types.all;
use work.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
bsd-3-clause
|
a22cdb5d0b3c825870e65d4a021b8792
| 0.406245 | 5.404587 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/RAM_1.vhd
| 1 | 10,399 |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_1.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM_1 IS
PORT
(
aclr : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END RAM_1;
ARCHITECTURE SYN OF ram_1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "RAM_1.mif",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
aclr0 => aclr,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "RAM_1.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_1.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
bc792b6e7e36968f67fa7697c9059e09
| 0.666314 | 3.290823 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_bus_concat.vhd
| 2 | 4,553 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_bus_concat is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
b : in std_logic_vector(widthB-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
a : in std_logic_vector(widthA-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
output : out std_logic_vector(widthA+widthB-1 downto 0)
);
end entity alt_dspbuilder_bus_concat;
architecture rtl of alt_dspbuilder_bus_concat is
component alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic (
WIDTHB : natural := 4;
WIDTHA : natural := 4
);
port (
a : in std_logic_vector(4-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(4-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(8-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNAUBM7IRL;
component alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 16
);
port (
a : in std_logic_vector(16-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(8-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(24-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNWZPLIVXS;
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
a : in std_logic_vector(8-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(8-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(16-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
component alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic (
WIDTHB : natural := 16;
WIDTHA : natural := 8
);
port (
a : in std_logic_vector(8-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(16-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(24-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GN55ETJ4VI;
component alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic (
WIDTHB : natural := 1;
WIDTHA : natural := 1
);
port (
a : in std_logic_vector(1-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(1-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(2-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GN6E6AAQPZ;
begin
alt_dspbuilder_bus_concat_GNAUBM7IRL_0: if ((WIDTHB = 4) and (WIDTHA = 4)) generate
inst_alt_dspbuilder_bus_concat_GNAUBM7IRL_0: alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map(WIDTHB => 4, WIDTHA => 4)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
alt_dspbuilder_bus_concat_GNWZPLIVXS_1: if ((WIDTHB = 8) and (WIDTHA = 16)) generate
inst_alt_dspbuilder_bus_concat_GNWZPLIVXS_1: alt_dspbuilder_bus_concat_GNWZPLIVXS
generic map(WIDTHB => 8, WIDTHA => 16)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
alt_dspbuilder_bus_concat_GNIIOZRPJD_2: if ((WIDTHB = 8) and (WIDTHA = 8)) generate
inst_alt_dspbuilder_bus_concat_GNIIOZRPJD_2: alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map(WIDTHB => 8, WIDTHA => 8)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
alt_dspbuilder_bus_concat_GN55ETJ4VI_3: if ((WIDTHB = 16) and (WIDTHA = 8)) generate
inst_alt_dspbuilder_bus_concat_GN55ETJ4VI_3: alt_dspbuilder_bus_concat_GN55ETJ4VI
generic map(WIDTHB => 16, WIDTHA => 8)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
alt_dspbuilder_bus_concat_GN6E6AAQPZ_4: if ((WIDTHB = 1) and (WIDTHA = 1)) generate
inst_alt_dspbuilder_bus_concat_GN6E6AAQPZ_4: alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map(WIDTHB => 1, WIDTHA => 1)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
assert not (((WIDTHB = 4) and (WIDTHA = 4)) or ((WIDTHB = 8) and (WIDTHA = 16)) or ((WIDTHB = 8) and (WIDTHA = 8)) or ((WIDTHB = 16) and (WIDTHA = 8)) or ((WIDTHB = 1) and (WIDTHA = 1)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
a2f93515f774f51848fe782398ec214a
| 0.663079 | 2.939316 | false | false | false | false |
dominiklohmann/mikrorechner
|
vhdl/procIdea.vhd
| 1 | 10,236 |
-- pipeProc.vhd
--
-- entity pipeProc -pipeline processor datapath
-- architecture noIO -register-transfer model
-- synthesizable
------------------------------------------------------------------------------
library ieee; -- packages:
use ieee.std_logic_1164.all; -- std_logic
use ieee.numeric_std.all; -- (un)signed
use work.procPkg.all; -- procPkg (=>opcode)
-- entity --------------------------------------------------------------
------------------------------------------------------------------------------
entity procIdea is
port( clk : in std_logic; -- clock
nRst : in std_logic; -- not reset
iAddr : out std_logic_vector(31 downto 0); -- instMem address
iData : in std_logic_vector(31 downto 0); -- instMem data
dnWE : out std_logic; -- dataMem write-ena
dnOE : out std_logic; -- dataMem output-ena
dAddr : out std_logic_vector(31 downto 0); -- dataMem address
dData : inout std_logic_vector(31 downto 0)); -- dataMem data
end entity procIdea;
-- architecture --------------------------------------------------------------
------------------------------------------------------------------------------
architecture noIO of procIdea is
type regBankTy is array (0 to 31) of std_logic_vector(31 downto 0);
signal regBank : regBankTy;
signal instIF : std_logic_vector(31 downto 0);
signal instID : std_logic_vector(31 downto 0);
signal instEX : std_logic_vector(31 downto 0);
signal instMEM : std_logic_vector(31 downto 0);
signal aluOpc : std_logic_vector(3 downto 0);
signal akku, opA : std_logic_vector(31 downto 0);
signal akkuEX : std_logic_vector(31 downto 0);
signal akkuMEM : std_logic_vector(31 downto 0);
signal achtungFlag : std_logic;
signal alu : signed(31 downto 0);
signal aluEX : std_logic_vector(31 downto 0);
signal regMEM : std_logic_vector(31 downto 0);
signal dDataEna : std_logic;
signal dDataReg : std_logic_vector(31 downto 0);
signal instCntIF : std_logic_vector(31 downto 0);
signal eqzFlag : std_logic;
begin
-- iAddr <= std_logic_vector(instCnt);
iAddr <= regBank(2);
-- IF ------------------------------------------------------
----------------------------------------------------------------------------
pipeIFreg_P: process(nRst, clk) is -- process: register + input-logic
begin --------------------------------------
if nRst = '0' then -- async. reset
instIF <= (others =>'1'); -- no-operation
elsif rising_edge(clk) then
instIF <= iData;
instCntIF <= regBank(2);
end if;
end process pipeIFreg_P;
-- ID / OF ------------------------------------------------------
-- -delayed regBank read in EX and MEM
----------------------------------------------------------------------------
pipeIDreg_P: process(nRst, clk) is -- process: register + input-logic
begin --------------------------------------
if nRst = '0' then -- async. reset
instID <= (others =>'1');
achtungFlag <= '0'; -- no-operation
elsif rising_edge(clk) then
instID <= instIF;
achtungFlag <= '0';
case instIF(31 downto 27) is -- decode instIF.opc --------------
when opcAdd | opcSub | -- 2-operand
opcAnd | opcOr | opcXor | opcShl | opcShr | opcNot =>
if achtungFlag = '0' then -- ALU command
akku <= regBank(0); --Der Akku
opA <= regBank(to_integer(unsigned(instIF(4 downto 0))));
achtungFlag <= '1';
elsif achtungFlag = '1' then
opA <= regBank(to_integer(unsigned(instIF(4 downto 0))));
achtungFlag <= '1';
end if;
-- 23 Bit Verschwendung, yay!
when opcMove =>
akku <= regBank(4);
opA <= "00000" & instIF(26 downto 0); -- Das ist eine Sign-Extention. (27 -> 32 Bit)
achtungFlag <= '1';
when opcAkkuLoad =>
akku <= regBank(4);
opA <= "00000000000000000000000000000000";
achtungFlag <= '1';
when opcAkkuStore =>
if achtungFlag = '0' then
akku <= regBank(4);
opA <= "00000000000000000000000000000000";
achtungFlag <= '0';
elsif achtungFlag = '1' then
opA <= "00000000000000000000000000000000";
achtungFlag <= '0';
end if;
when opcLoadMemory =>
achtungFlag <= '0';
when opcNoOP =>
achtungFlag <= '1';
when opcStoreMemory =>
if achtungFlag = '0' then
akku <= regBank(4);
opA <= "00000" & instIF(26 downto 0);
achtungFlag <= '0';
elsif achtungFlag = '1' then
opA <= "00000" & instIF(26 downto 0);
achtungFlag <= '0';
end if;
when opciStore =>
if achtungFlag = '0' then
akku <= regBank(4);
opA <= "00000" & instIF(26 downto 0);
achtungFlag <= '0';
elsif achtungFlag = '1' then
opA <= "00000" & instIF(26 downto 0);
achtungFlag <= '0';
end if;
when opciLoad =>
achtungFlag <= '0';
when opcJmp =>
akku <= regBank(4);
opA <= regBank(to_integer(unsigned(instIF(4 downto 0))));
achtungFlag <= '0';
when others => null;
end case; -- decode opcode
end if;
end process pipeIDreg_P;
-- EX ------------------------------------------------------
----------------------------------------------------------------------------
-- ALU opcode --------------
-- mode may require addition in ALU
aluOpc <= aluAdd when ((instID(31 downto 27) = opcJmp) or
(instID(31 downto 27) = opcMove) or
(instID(31 downto 27) = opcAkkuLoad) or
(instID(31 downto 27) = opcAkkuStore))
else instID(30 downto 27); -- ALU command
with aluOpc select -- ALU ------------------------------
alu <= signed(akku)+signed(opA) when aluAdd,
signed(akku)-signed(opA) when aluSub,
signed(akku and opA) when aluAnd,
signed(akku or opA) when aluOr,
signed(akku xor opA) when aluXor,
signed(shift_left(unsigned(akku),to_integer(unsigned(opA)))) when aluShl,
signed(shift_right(unsigned(akku),to_integer(unsigned(opA)))) when aluShr,
signed(not(opA)) when aluNot,
(others => '-') when others;
pipeEXreg_P: process(nRst, clk) is -- process: register + input-logic
begin --------------------------------------
if nRst = '0' then -- async. reset
instEx <= (others =>'1'); -- no-operation
dAddr <= (others =>'0'); -- data address
dnWE <= '1'; -- data readopA <= regBank(toInteger(unsigned(instIF(27 downto 0))));
dnOE <= '1'; -- data disabled
dDataEna <= '0'; -- own bus-driver disabled
elsif rising_edge(clk) then
instEX <= instID;
dnWE <= '1';
dnOE <= '1';
dDataEna <= '0';
case instID(31 downto 27) is -- decode instID.opc --------------
when opcAnd | opcOr | opcXor | opcShl | opcShr | opcNot | opcMove | opcJmp =>
-- ALU command
aluEX <= std_logic_vector(alu);
akkuEX <= std_logic_vector(alu);
if alu = 0 then eqzFlag <= '1';
else eqzFlag <= '0';
end if;
when opcAdd | opcSub =>
aluEX <= std_logic_vector(alu);
akkuEX <= std_logic_vector(alu);
if alu = 0 then eqzFlag <= '1';
else eqzFlag <= '0';
end if;
when opcLoadMemory => -- Load
dnOE <= '0'; -- + absolute
dAddr <= "00000" & instID(26 downto 0);
when opcStoreMemory => -- Store
dnWE <= '0';
dDataEna<= '1';
dDataReg<= regBank(0); -- + absolute
dAddr <= "00000" & instID(26 downto 0);
when opcAkkuStore =>
aluEX <= regBank(0);
when opcAkkuLoad =>
aluEX <= regBank(to_integer(unsigned(instID(4 downto 0))));
when opciStore =>
dnWE <= '0';
dDataEna<= '1';
dDataReg<= regBank(0); -- + absolute
dAddr <= regBank(to_integer(unsigned(instID(4 downto 0))));
when opciLoad =>
dnOE <= '0';
dAddr <= regBank(to_integer(unsigned(instID(4 downto 0))));
when others => null;
end case; -- decode opcode
end if;
end process pipeEXreg_P;
-- tristate bus driver --------------
dData <= dDataReg when dDataEna = '1' else -- enabled
(others => 'Z'); -- tristate
-- MEM ------------------------------------------------------
----------------sim:/procsim/procIdeaI/regMEM(3)
------------------------------------------------------------
pipeMEMreg_P: process(nRst, clk) is -- process: register + input-logic
begin --------------------------------------
if nRst = '0' then -- async. reset
instMEM <= (others =>'1'); -- no-operation
elsif rising_edge(clk) then
instMEM <= instEX;
case instEX(31 downto 27) is -- decode instEX.opc --------------
when opcAdd | opcSub |
opcAnd | opcOr | opcXor | opcShl | opcShr | opcNot | opcMove | opcAkkuStore | opcJmp => -- ALU command
regMEM <= aluEX;
when opcLoadMemory | opciLoad => -- Load
regMEM <= dData;
when others => null;
end case; -- decode opcode
end if;
end process pipeMEMreg_P;
-- WB / regBank ------------------------------------------------------
----------------------------------------------------------------------------
pipeWBreg_P: process(nRst,clk) is -- process: register + input-logic
begin
if nRst = '0' then
regBank(0) <= (others => '0');
regBank(1) <= "00000000000000000111111111111111"
regBank(2) <= (others => '0');
regBank(4) <= (others => '0');
--------------------------------------
elsif rising_edge(clk) then
regBank(2) <= std_logic_vector(unsigned(regBank(2)) + 1);
case instMEM(31 downto 27) is -- decode instMEM.opc --------------
when opcAdd | opcSub |
opcAnd | opcOr | opcXor | opcShl | opcShr | opcNot | -- ALU command
opcLoadMemory | opcMove | opcAkkuLoad | opciLoad => -- Load
regBank(0) <= regMEM;
when opcAkkuStore =>
regBank(to_integer(unsigned(instMEM(4 downto 0)))) <= regMEM;
when opcJmp =>
-- Jump =0
if eqzFlag = '1' then -- if=0
regBank(2) <= regMEM; -- absolute
end if; -- condition
when others => null;
end case;
if (iData(31 downto 27) = opcHALTSTOP) or
(instIF(31 downto 27) = opcHALTSTOP) or
(instID(31 downto 27) = opcHALTSTOP) then -- stop
regBank(2) <= regBank(2);
end if; -- decode opcode
end if;
end process pipeWBreg_P;
end architecture noIO;
------------------------------------------------------------------------------
-- pipeProc.vhd - end
|
mit
|
a9e8fc605f8fd918bf16056ce4633f9f
| 0.524033 | 3.616961 | false | false | false | false |
lelongdunet/dspunit
|
sim/gen_memoryf.vhd
| 2 | 6,490 |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2006-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL ;
-------------------------------------------------------------------------------
entity gen_memoryf is
generic (
addr_width : natural := 11;
data_width : natural := 8;
init_file : STRING
);
port (
--@inputs
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
--@outputs;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end gen_memoryf;
--=----------------------------------------------------------------------------
architecture archi_gen_memoryf of gen_memoryf is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
type memType is array((2**addr_width - 1) downto 0) of std_logic_vector((data_width - 1) downto 0);
-- Fonction d'initialisation du programme
function initialize_ram
return memType is
variable result : memType;
file data : TEXT IS init_file;
variable lineStr, msg : line;
variable i : natural := 0;
variable rom_buf : std_logic_vector((data_width - 1) downto 0);
variable ok : boolean;
begin
for i in 0 to (2**addr_width - 1) loop
if not endfile(data) then
readline(data, lineStr);
hread(lineStr, rom_buf, ok);
if ok then
result(i) := rom_buf;
-- result(i)((data_width - 2) downto 0) := rom_buf((data_width - 1) downto 1);
-- result(i)(data_width - 1) := rom_buf(data_width - 1);
else
write(msg, String'(" !!! FORMAT !!! : "));
-- write(msg, String'(line.all));
write(msg, String'(" @ line : "));
write(msg, i);
report msg.all;
end if;
else
result(i) := (others => '0');
end if;
end loop;
return result;
end initialize_ram;
signal s_ram_block : memType := initialize_ram;
signal s_address_a : std_logic_vector((addr_width - 1) downto 0);
signal s_address_b : std_logic_vector((addr_width - 1) downto 0);
signal s_w_clk : std_logic;
begin -- archs_gen_memoryf
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
ramProc_a : process (clock_a)
begin -- process ramProc
if rising_edge(clock_a) then -- rising clock edge
s_address_a <= address_a;
q_a <= s_ram_block(to_integer(unsigned(s_address_a)));
end if;
end process ramProc_a;
ramProc_b : process (clock_b)
begin -- process ramProc
if rising_edge(clock_b) then -- rising clock edge
s_address_b <= address_b;
q_b <= s_ram_block(to_integer(unsigned(s_address_b)));
end if;
end process ramProc_b;
-- -- Read initial content of the ram from file
-- file_read : process
-- file data : TEXT IS init_file;
-- variable lineStr, msg : line;
-- variable i : natural := 0;
-- variable rom_buf : std_logic_vector((data_width - 1) downto 0);
-- variable ok : boolean;
-- begin -- process file_read
-- while not endfile(data) loop
-- readline(data, lineStr);
-- hread(lineStr, rom_buf, ok);
-- if ok then
-- s_ram_block(i) <= rom_buf; -- no conversion
-- else
-- write(msg, String'(" !!! FORMAT !!! : "));
---- write(msg, String'(line.all));
-- write(msg, String'(" @ line : "));
-- write(msg, i);
-- report msg.all;
-- end if;
--
-- if i < (2**addr_width - 1) then
-- i := i + 1;
-- else
-- report "ram full";
-- exit;
-- end if;
-- end loop;
-- wait;
-- end process file_read;
--
ramWrite : process (clock_a)
begin -- process ramWrite
-- if rising_edge(s_w_clk) then -- rising clock edge
if falling_edge(clock_a) then -- rising clock edge
if wren_a = '1' then
s_ram_block(to_integer(unsigned(address_a))) <= data_a;
elsif wren_b = '1' then
s_ram_block(to_integer(unsigned(address_b))) <= data_b;
end if;
end if;
end process ramWrite;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_w_clk <= (clock_a and wren_a) or (clock_b and wren_b);
end archi_gen_memoryf;
-------------------------------------------------------------------------------
|
gpl-3.0
|
40b53bcc1962f034574a5cc210bb5591
| 0.478737 | 4.038581 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_AltMultConst.vhd
| 12 | 10,967 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
library LPM;
use LPM.LPM_COMPONENTS.all;
entity alt_dspbuilder_AltMultConst is
generic (
CA : std_logic_vector :="10";
CB : std_logic_vector :="0010";
CC : std_logic_vector :="10010";
CD : std_logic_vector :="1000001011111111111111";
width_a : positive :=8;
width_r : positive :=17;
regstruct : registerstructure :=NoRegister;
data_signed : boolean := true
);
port (
datain : in std_logic_vector (width_a-1 downto 0);
datbin : in std_logic_vector (width_a-1 downto 0);
datcin : in std_logic_vector (width_a-1 downto 0);
datdin : in std_logic_vector (width_a-1 downto 0);
dataout : out std_logic_vector (width_r-1 downto 0);
clock : in std_logic := '1';
ena : in std_logic := '1';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
user_aclr : in std_logic
);
end alt_dspbuilder_AltMultConst;
architecture AltMultConst_synth of alt_dspbuilder_AltMultConst is
function MaxInt(a:integer ; b:integer) return integer is
variable i : integer;
begin
if (a>b) then
i := a;
else
i := b;
end if ;
return i;
end MaxInt;
constant wadda : integer := MaxInt(datain'high+CA'high+1,datbin'high+CB'high+1)+1;
constant waddb : integer := MaxInt(datcin'high+CC'high+1,datdin'high+CD'high+1)+1;
constant wres : integer := MaxInt(wadda,waddb)+1;
signal C0 : std_logic_vector(CA'high downto 0) := CA(0 to CA'high);
signal C1 : std_logic_vector(CB'high downto 0) := CB(0 to CB'high);
signal C2 : std_logic_vector(CC'high downto 0) := CC(0 to CC'high);
signal C3 : std_logic_vector(CD'high downto 0) := CD(0 to CD'high);
signal dataint : std_logic_vector (datain'high downto 0);
signal datbint : std_logic_vector (datbin'high downto 0);
signal datcint : std_logic_vector (datcin'high downto 0);
signal datdint : std_logic_vector (datdin'high downto 0);
signal AC0 : std_logic_vector(datain'high+CA'high+1 downto 0) ;
signal BC1 : std_logic_vector(datbin'high+CB'high+1 downto 0) ;
signal CC2 : std_logic_vector(datcin'high+CC'high+1 downto 0) ;
signal DC3 : std_logic_vector(datdin'high+CD'high+1 downto 0) ;
signal AC0EXT : std_logic_vector(wadda downto 0) ;
signal BC1EXT : std_logic_vector(wadda downto 0) ;
signal CC2EXT : std_logic_vector(waddb downto 0) ;
signal DC3EXT : std_logic_vector(waddb downto 0) ;
signal adda : std_logic_vector(wadda downto 0) ;
signal addb : std_logic_vector(waddb downto 0) ;
signal addaEXT : std_logic_vector(wres downto 0) ;
signal addbEXT : std_logic_vector(wres downto 0) ;
signal result : std_logic_vector(wres downto 0) ;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
C0 <= CA(0 to CA'high);
C1 <= CB(0 to CB'high);
C2 <= CC(0 to CC'high);
C3 <= CD(0 to CD'high);
AC0EXT(datain'high+CA'high+1 downto 0) <= AC0(datain'high+CA'high+1 downto 0);
gAC0EXT:for i in datain'high+CA'high+2 to wadda generate
gAC0EXT_s: if (data_signed) generate
AC0EXT(i) <= AC0EXT(datain'high+CA'high+1);
end generate;
gAC0EXT_u: if not(data_signed) generate
AC0EXT(i) <= '0';
end generate;
end generate ;
BC1EXT(datbin'high+CB'high+1 downto 0) <= BC1(datbin'high+CB'high+1 downto 0);
gBC1EXT:for i in datbin'high+CB'high+2 to wadda generate
gBC1EXT_s: if (data_signed) generate
BC1EXT(i) <= BC1EXT(datbin'high+CB'high+1);
end generate;
gBC1EXT_u: if not(data_signed) generate
BC1EXT(i) <= '0';
end generate;
end generate ;
CC2EXT(datcin'high+CC'high+1 downto 0) <= CC2(datcin'high+CC'high+1 downto 0);
gCC2EXT:for i in datcin'high+CC'high+2 to waddb generate
gCC2EXT_s: if (data_signed) generate
CC2EXT(i) <= CC2EXT(datcin'high+CC'high+1);
end generate;
gCC2EXT_u: if not(data_signed) generate
CC2EXT(i) <= '0';
end generate;
end generate ;
DC3EXT(datcin'high+CD'high+1 downto 0) <= DC3(datcin'high+CD'high+1 downto 0);
gDC3EXT:for i in datcin'high+CD'high+2 to waddb generate
gDC3EXT_s: if (data_signed) generate
DC3EXT(i) <= DC3EXT(datcin'high+CD'high+1);
end generate;
gDC3EXT_u: if not(data_signed) generate
DC3EXT(i) <= '0';
end generate;
end generate ;
addaEXT(wadda downto 0) <= adda(wadda downto 0);
gaddaEXT:for i in wadda+1 to wres generate
gaddaEXT_s: if (data_signed) generate
addaEXT(i) <= adda(wadda);
end generate;
gaddaEXT_u: if not(data_signed) generate
addaEXT(i) <= '0';
end generate;
end generate ;
addbEXT(waddb downto 0) <= addb(waddb downto 0);
gaddbEXT:for i in waddb+1 to wres generate
gaddbEXT_s: if (data_signed) generate
addbEXT(i) <= addb(waddb);
end generate;
gaddbEXT_u: if not(data_signed) generate
addbEXT(i) <= '0';
end generate;
end generate ;
gr:if (wres<dataout'high) generate
dataout(wres downto 0) <= result(wres downto 0);
grr: for i in wres+1 to dataout'high generate
grr_s: if (data_signed) generate
dataout(i) <= result(wres);
end generate grr_s;
grr_u: if not(data_signed) generate
dataout(i) <= '0';
end generate grr_u;
end generate grr;
end generate gr;
gnr:if not(wres<dataout'high) generate
dataout(dataout'high downto 0) <= result(dataout'high downto 0);
end generate gnr;
gnr1: if ((regstruct=NoRegister)or (regstruct=MultiplierOnly) or (regstruct=AdderOnly) or (regstruct=MultiplierandAdder)) generate
dataint <= datain;
datbint <= datbin;
datcint <= datcin;
datdint <= datdin;
end generate gnr1;
gr1: if ((regstruct=InputsOnly)or (regstruct=InputsandMultiplier) or (regstruct=InputsandAdder) or (regstruct=InputsMultiplierandAdder)) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dataint <= (others=>'0');
datbint <= (others=>'0');
datcint <= (others=>'0');
datdint <= (others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
dataint <= (others=>'0');
datbint <= (others=>'0');
datcint <= (others=>'0');
datdint <= (others=>'0');
elsif (ena='1') then
dataint <= datain;
datbint <= datbin;
datcint <= datcin;
datdint <= datdin;
end if ;
end if ;
end process ;
end generate gr1;
gnr2: if ((regstruct=NoRegister)or (regstruct=InputsOnly) or (regstruct=AdderOnly) or (regstruct=InputsandAdder)) generate
gnr2_s: if (data_signed) generate
AC0 <= C0*dataint;
BC1 <= C1*datbint;
CC2 <= C2*datcint;
DC3 <= C3*datdint;
end generate gnr2_s;
gnr2_u: if not(data_signed) generate
AC0 <= unsigned(C0)*unsigned(dataint);
BC1 <= unsigned(C1)*unsigned(datbint);
CC2 <= unsigned(C2)*unsigned(datcint);
DC3 <= unsigned(C3)*unsigned(datdint);
end generate gnr2_u;
end generate gnr2;
gr2: if ((regstruct=MultiplierOnly)or (regstruct=InputsandMultiplier) or (regstruct=MultiplierandAdder) or (regstruct=InputsMultiplierandAdder)) generate
gr2_s: if (data_signed) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AC0 <= (others=>'0');
BC1 <= (others=>'0');
CC2 <= (others=>'0');
DC3 <=(others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
AC0 <= (others=>'0');
BC1 <= (others=>'0');
CC2 <= (others=>'0');
DC3 <=(others=>'0');
elsif (ena='1') then
AC0 <= C0*dataint;
BC1 <= C1*datbint;
CC2 <= C2*datcint;
DC3 <= C3*datdint;
end if ;
end if ;
end process ;
end generate gr2_s;
gr2_u: if not(data_signed) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AC0 <= (others=>'0');
BC1 <= (others=>'0');
CC2 <= (others=>'0');
DC3 <=(others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
AC0 <= (others=>'0');
BC1 <= (others=>'0');
CC2 <= (others=>'0');
DC3 <=(others=>'0');
elsif (ena='1') then
AC0 <= unsigned(C0)*unsigned(dataint);
BC1 <= unsigned(C1)*unsigned(datbint);
CC2 <= unsigned(C2)*unsigned(datcint);
DC3 <= unsigned(C3)*unsigned(datdint);
end if ;
end if ;
end process ;
end generate gr2_u;
end generate gr2;
adda <= AC0EXT+BC1EXT;
addb <= CC2EXT+DC3EXT;
gnr3: if ((regstruct=NoRegister)or (regstruct=InputsOnly) or (regstruct=MultiplierOnly) or (regstruct=InputsandMultiplier)) generate
result <= addaEXT+addbEXT;
end generate gnr3;
gr3: if ((regstruct=AdderOnly)or (regstruct=InputsandAdder) or (regstruct=MultiplierandAdder) or (regstruct=InputsMultiplierandAdder)) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
result <= (others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
result <= (others=>'0');
elsif (ena='1') then
result <= addaEXT+addbEXT;
end if ;
end if ;
end process ;
end generate gr3;
end AltMultConst_synth;
|
mit
|
29562f2ea766fa8953b19e7774551331
| 0.590955 | 3.248519 | false | false | false | false |
lelongdunet/dspunit
|
rtl/dspalu_pac.vhd
| 2 | 4,546 |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
package dspalu_pac is
function zeros(size : natural) return unsigned;
function zeros(size : natural) return std_logic_vector;
function sig_one(size : natural) return signed;
function sig_one(size : natural) return std_logic_vector;
-- type t_acc_mode is (acc_store, acc_sumstore, acc_diff, acc_add, acc_sub, acc_back_add, acc_minback_sub);
constant acc_mode_width : natural := 4;
-- alias t_acc_mode is std_logic_vector(3 downto 0);
constant acc_none : std_logic_vector((acc_mode_width - 1) downto 0) := x"0";
constant acc_store : std_logic_vector((acc_mode_width - 1) downto 0) := x"1";
constant acc_sumstore : std_logic_vector((acc_mode_width - 1) downto 0) := x"2";
constant acc_diff : std_logic_vector((acc_mode_width - 1) downto 0) := x"3";
constant acc_add : std_logic_vector((acc_mode_width - 1) downto 0) := x"4";
constant acc_sub : std_logic_vector((acc_mode_width - 1) downto 0) := x"5";
constant acc_back_add : std_logic_vector((acc_mode_width - 1) downto 0) := x"6";
constant acc_abs : std_logic_vector((acc_mode_width - 1) downto 0) := x"7";
constant acc_minback_sub : std_logic_vector((acc_mode_width - 1) downto 0) := x"8";
constant acc_reset : std_logic_vector((acc_mode_width - 1) downto 0) := x"F";
-- type t_alu_select is (alu_add, alu_muladd, alu_mul, alu_cmul, alu_cmul_conj);
-- alias t_alu_select is std_logic_vector(3 downto 0);
constant alu_select_width : natural := 4;
-- constant alu_add : std_logic_vector(3 downto 0) := "0000";
constant alu_none : std_logic_vector((alu_select_width - 1) downto 0) := "0000";
constant alu_muladd : std_logic_vector((alu_select_width - 1) downto 0) := "0001";
constant alu_mul : std_logic_vector((alu_select_width - 1) downto 0) := "0010";
constant alu_cmul : std_logic_vector((alu_select_width - 1) downto 0) := "0100";
constant alu_cmul_conj : std_logic_vector((alu_select_width - 1) downto 0) := "1000";
-- type t_cmp_mode is (cmp_acc1, cmp_acc2);
constant cmp_mode_width : natural := 2;
-- alias t_cmp_mode is std_logic_vector(1 downto 0);
constant cmp_none : std_logic_vector((cmp_mode_width - 1) downto 0) := "00";
constant cmp_acc1 : std_logic_vector((cmp_mode_width - 1) downto 0) := "01";
constant cmp_acc2 : std_logic_vector((cmp_mode_width - 1) downto 0) := "10";
end dspalu_pac;
package body dspalu_pac is
function zeros(size : natural) return unsigned
is
variable vect_zeros : unsigned((size - 1) downto 0);
begin
vect_zeros := (others => '0');
return vect_zeros;
end zeros;
function zeros(size : natural) return std_logic_vector
is
variable vect_zeros : std_logic_vector((size - 1) downto 0);
begin
vect_zeros := (others => '0');
return vect_zeros;
end zeros;
function sig_one(size : natural) return signed
is
variable vect_one : signed((size - 1) downto 0);
begin
vect_one(size - 1) := '0';
vect_one((size - 2) downto 0) := (others => '1');
return vect_one;
end sig_one;
function sig_one(size : natural) return std_logic_vector
is
variable vect_one : std_logic_vector((size - 1) downto 0);
begin
vect_one(size - 1) := '0';
vect_one((size - 2) downto 0) := (others => '1');
return vect_one;
end sig_one;
end dspalu_pac;
|
gpl-3.0
|
baba478bffcd463cb69924203782bdb7
| 0.618126 | 3.369904 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/M25P32/M25P32.vhd
| 1 | 9,636 |
-------------------------------------------------------
-- Author: Hugues CREUSY
--February 2004
-- VHDL model
-- project: M25P32 50 MHz,
-- release: 1.0
-----------------------------------------------------
-- Unit : Top hierarchy
-----------------------------------------------------
-------------------------------------------------------------
-- These VHDL models are provided "as is" without warranty
-- of any kind, included but not limited to, implied warranty
-- of merchantability and fitness for a particular purpose.
-------------------------------------------------------------
---------------------------------------------------------
--
-- m25p32 SERIAL FLASH MEMORY
--
---------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY WORK;
USE WORK.MEM_UTIL_PKG.ALL;
-----------------------------------------------------
-- ENTITY
-----------------------------------------------------
ENTITY m25p32 IS
GENERIC ( init_file: string := string'("initm25p32.txt"); -- Init file name
SIZE : positive := 1048576*32; -- 16Mbit
Plength : positive := 256; -- Page length (in Byte)
SSIZE : positive := 524288; -- Sector size (in # of bits)
NB_BPi: positive := 3; -- Number of BPi bits
signature : STD_LOGIC_VECTOR (7 downto 0):="00010101"; -- Electronic signature
manufacturerID : STD_LOGIC_VECTOR (7 downto 0):="00100000"; -- Manufacturer ID
memtype : STD_LOGIC_VECTOR (7 downto 0):="00100000"; -- Memory Type
density : STD_LOGIC_VECTOR (7 downto 0):="00010110"; -- Density
Tc: TIME := 20 ns; -- Minimum Clock period
Tr: TIME := 50 ns; -- Minimum Clock period for read instruction
tSLCH: TIME:= 5 ns; -- notS active setup time (relative to C)
tCHSL: TIME:= 5 ns; -- notS not active hold time
tCH : TIME := 9 ns; -- Clock high time
tCL : TIME := 9 ns; -- Clock low time
tDVCH: TIME:= 2 ns; -- Data in Setup Time
tCHDX: TIME:= 5 ns; -- Data in Hold Time
tCHSH : TIME := 5 ns; -- notS active hold time (relative to C)
tSHCH: TIME := 5 ns; -- notS not active setup time (relative to C)
tSHSL: TIME := 100 ns; -- /S deselect time
tSHQZ: TIME := 8 ns; -- Output disable Time
tCLQV: TIME := 8 ns; -- clock low to output valid
tHLCH: TIME := 5 ns; -- NotHold active setup time
tCHHH: TIME := 5 ns; -- NotHold not active hold time
tHHCH: TIME := 5 ns; -- NotHold not active setup time
tCHHL: TIME := 5 ns; -- NotHold active hold time
tHHQX: TIME := 8 ns; -- NotHold high to Output Low-Z
tHLQZ: TIME := 8 ns; -- NotHold low to Output High-Z
tWHSL: TIME := 20 ns; -- Write protect setup time (SRWD=1)
tSHWL: TIME := 100 ns; -- Write protect hold time (SRWD=1)
tDP: TIME := 3 us; -- notS high to deep power down mode
tRES1: TIME := 30 us; -- notS high to stand-by power mode
tRES2: TIME := 30 us; --
tW: TIME := 15 ms; -- write status register cycle time
tPP: TIME := 5 ms; -- page program cycle time
tSE: TIME := 3 sec; -- sector erase cycle time
tBE: TIME := 80 sec; -- bulk erase cycle time
tVSL: TIME := 10 us; -- Vcc(min) to /S low
tPUW: TIME := 10 ms; -- Time delay to write instruction
Vwi: REAL := 2.5 ; -- Write inhibit voltage (unit: V)
Vccmin: REAL := 2.7 ; -- Minimum supply voltage
Vccmax: REAL := 3.6 -- Maximum supply voltage
);
PORT( VCC: IN REAL;
C, D, S, W, HOLD : IN std_logic ;
Q : OUT std_logic);
BEGIN
END m25p32;
---------------------------------------------------------------------
-- ARCHITECTURE
---------------------------------------------------------------------
-- This part implements three components: one of type Internal Logic,
-- one of type Memory Access and one of type ACDC check
---------------------------------------------------------------------
ARCHITECTURE structure OF m25p32 IS
COMPONENT Internal_Logic
GENERIC ( SIZE : positive;
Plength : positive;
SSIZE : positive;
Nb_BPi: positive;
signature : STD_LOGIC_VECTOR (7 downto 0);
manufacturerID : STD_LOGIC_VECTOR (7 downto 0);
memtype : STD_LOGIC_VECTOR (7 downto 0);
density : STD_LOGIC_VECTOR (7 downto 0);
NB_BIT_DATA: positive;
NB_BIT_ADD: positive;
NB_BIT_ADD_MEM: positive;
Tc: TIME;
tSLCH: TIME;
tCHSL: TIME;
tCH: TIME;
tCL: TIME;
tDVCH: TIME;
tCHDX: TIME;
tCHSH: TIME;
tSHCH: TIME;
tSHSL: TIME;
tSHQZ: TIME;
tCLQV: TIME;
tHLCH: TIME;
tCHHH: TIME;
tHHCH: TIME;
tCHHL: TIME;
tHHQX: TIME;
tHLQZ: TIME;
tWHSL: TIME;
tSHWL: TIME;
tDP:TIME;
tRES1:TIME;
tRES2:TIME;
tW: TIME;
tPP:TIME;
tSE:TIME;
tBE:TIME );
PORT ( C, D, HOLD,W,S: IN std_logic;
data_to_read: IN std_logic_vector (NB_BIT_DATA-1 downto 0);
Power_up: IN boolean;
Q: OUT std_logic;
p_prog: OUT page (0 TO (Plength-1));
add_mem: OUT std_logic_vector(NB_BIT_ADD_MEM-1 downto 0);
write_op,read_op,BE_enable,SE_enable,add_pp_enable,PP_enable:OUT boolean;
read_enable,data_request: OUT boolean;
wrsr, srwd_wrsr,write_protect: INOUT boolean
);
END COMPONENT;
COMPONENT Memory_Access
GENERIC( init_file: string;
SIZE : positive;
Plength : positive;
SSIZE : positive;
NB_BIT_DATA: positive;
NB_BIT_ADD: positive;
NB_BIT_ADD_MEM: positive);
PORT( add_mem: IN std_logic_vector(NB_BIT_ADD_MEM-1 downto 0);
BE_enable,SE_enable,add_pp_enable,PP_enable: IN boolean;
read_enable,data_request: IN boolean;
p_prog: IN page (0 TO (Plength-1));
data_to_read: OUT std_logic_vector (NB_BIT_DATA-1 downto 0));
END COMPONENT;
COMPONENT ACDC_check
GENERIC ( Tc: TIME;
Tr: TIME;
tSLCH: TIME;
tCHSL: TIME;
tCH : TIME;
tCL : TIME;
tDVCH: TIME;
tCHDX: TIME;
tCHSH : TIME;
tSHCH: TIME;
tSHSL: TIME;
tHLCH: TIME;
tCHHH: TIME;
tHHCH: TIME;
tCHHL: TIME;
tVSL: TIME ;
tPUW: TIME ;
tWHSL: TIME;
tSHWL: TIME;
Vwi: REAL;
Vccmin: REAL;
Vccmax: REAL);
PORT ( VCC: IN REAL;
C, D, S, HOLD : IN std_logic;
write_op,read_op: IN boolean;
wrsr: IN boolean;
srwd_wrsr: IN boolean;
write_protect: IN boolean;
Power_up: OUT boolean);
END COMPONENT;
CONSTANT NOMBRE_BIT_ADRESSE_TOTAL: positive:= 24;
CONSTANT NOMBRE_BIT_ADRESSE_SPI: positive := 8;
CONSTANT NOMBRE_BIT_DONNEE_SPI: positive :=8;
SIGNAL adresse: std_logic_vector(NOMBRE_BIT_ADRESSE_TOTAL-1 DOWNTO 0) ;
SIGNAL dtr: std_logic_vector(NOMBRE_BIT_DONNEE_SPI-1 DOWNTO 0);
SIGNAL page_prog:page (0 TO (Plength-1));
SIGNAL wr_op,rd_op,s_en,b_en,add_pp_en,pp_en,r_en,d_req,wrsr, srwd_wrsr,write_protect,p_up : boolean;
SIGNAL clck : std_logic;
BEGIN
clck<=C;
SPI_decoder:Internal_Logic
GENERIC MAP(
SIZE=>SIZE,
Plength => Plength,
SSIZE => SSIZE,
NB_BPi => NB_BPi,
signature => signature,
manufacturerID => manufacturerID,
memtype => memtype,
density => density,
NB_BIT_DATA => NOMBRE_BIT_DONNEE_SPI,
NB_BIT_ADD => NOMBRE_BIT_ADRESSE_SPI,
NB_BIT_ADD_MEM => NOMBRE_BIT_ADRESSE_TOTAL,
Tc=>Tc,
tSLCH => tSLCH,
tCHSL => tCHSL,
tCH => tCH,
tCL => tCL,
tDVCH => tDVCH,
tCHDX => tCHDX,
tCHSH => tCHSH,
tSHCH => tSHCH,
tSHSL => tSHSL,
tSHQZ =>tSHQZ,
tCLQV => tCLQV,
tHLCH => tHLCH,
tCHHH => tCHHH,
tHHCH => tHHCH,
tCHHL => tCHHL,
tHHQX => tHHQX,
tHLQZ => tHLQZ,
tWHSL => tWHSL,
tSHWL => tSHWL,
tDP => tDP,
tRES1 => tRES1,
tRES2 => tRES2,
tW => tW,
tPP => tPP,
tSE => tSE,
tBE => tBE )
PORT MAP( clck, D,HOLD,W,S,dtr,p_up,Q,page_prog,adresse,wr_op,rd_op,b_en,s_en,add_pp_en,pp_en,r_en,d_req, wrsr, srwd_wrsr,write_protect);
Mem_access:Memory_Access
GENERIC MAP( init_file => init_file,
SIZE => SIZE,
Plength => Plength,
SSIZE => SSIZE,
NB_BIT_DATA => NOMBRE_BIT_DONNEE_SPI,
NB_BIT_ADD => NOMBRE_BIT_ADRESSE_SPI,
NB_BIT_ADD_MEM => NOMBRE_BIT_ADRESSE_TOTAL)
PORT MAP( adresse,
b_en,
s_en,
add_pp_en,
pp_en,
r_en,
d_req,
page_prog,
dtr);
ACDC_watch:ACDC_check
GENERIC MAP( Tc => Tc,
Tr => Tr,
tSLCH => tSLCH,
tCHSL => tCHSL,
tCH => tCH,
tCL => tCL,
tDVCH => tDVCH,
tCHDX => tCHDX,
tCHSH => tCHSH,
tSHCH => tSHCH,
tSHSL => tSHSL,
tHLCH => tHLCH,
tCHHH => tCHHH,
tHHCH => tHHCH,
tCHHL => tCHHL,
tVSL => tVSL,
tPUW => tPUW,
tWHSL => tWHSL,
tSHWL => tSHWL,
Vwi => Vwi,
Vccmin => Vccmin,
Vccmax => Vccmax )
PORT MAP( VCC,clck,D,S,HOLD,wr_op,rd_op,wrsr, srwd_wrsr, write_protect,p_up);
END structure;
|
gpl-3.0
|
e089a0aa08e6a9b6de91e99c9dfbc6b3
| 0.50768 | 3.426743 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_pipelined_adder.vhd
| 3 | 3,938 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_pipelined_adder is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 1;
USE_CARRY_OUT_PORT : natural := 1;
USE_CARRY_PORT : natural := 1;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
user_aclr : in std_logic := '0';
result : out std_logic_vector(width-1 downto 0);
clock : in std_logic := '0';
dataa : in std_logic_vector(width-1 downto 0) := (others=>'0');
datab : in std_logic_vector(width-1 downto 0) := (others=>'0');
cout : out std_logic;
add_sub : in std_logic := '0';
aclr : in std_logic := '0';
cin : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_pipelined_adder;
architecture rtl of alt_dspbuilder_pipelined_adder is
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 0;
USE_CARRY_OUT_PORT : natural := 0;
USE_CARRY_PORT : natural := 0;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
dataa : in std_logic_vector(0-1 downto 0) := (others=>'0');
datab : in std_logic_vector(0-1 downto 0) := (others=>'0');
ena : in std_logic := '0';
result : out std_logic_vector(0-1 downto 0);
user_aclr : in std_logic := '0'
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
OR_ACLR_INPUTS : natural := 1;
SIGNED : integer := 0;
NDIRECTION : integer := 1;
USE_CARRY_OUT_PORT : natural := 0;
USE_CARRY_PORT : natural := 0;
WIDTH : natural := 0;
PIPELINE : integer := 0
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
dataa : in std_logic_vector(0-1 downto 0) := (others=>'0');
datab : in std_logic_vector(0-1 downto 0) := (others=>'0');
ena : in std_logic := '0';
result : out std_logic_vector(0-1 downto 0);
user_aclr : in std_logic := '0'
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
begin
alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: if ((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_pipelined_adder_GNWEIMU3MK_0: alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map(OR_ACLR_INPUTS => 1, SIGNED => 0, NDIRECTION => 0, USE_CARRY_OUT_PORT => 0, USE_CARRY_PORT => 0, WIDTH => 0, PIPELINE => 0)
port map(aclr => aclr, clock => clock, dataa => dataa, datab => datab, ena => ena, result => result, user_aclr => user_aclr);
end generate;
alt_dspbuilder_pipelined_adder_GNTWZRTG4I_1: if ((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 1) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_pipelined_adder_GNTWZRTG4I_1: alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map(OR_ACLR_INPUTS => 1, SIGNED => 0, NDIRECTION => 1, USE_CARRY_OUT_PORT => 0, USE_CARRY_PORT => 0, WIDTH => 0, PIPELINE => 0)
port map(aclr => aclr, clock => clock, dataa => dataa, datab => datab, ena => ena, result => result, user_aclr => user_aclr);
end generate;
assert not (((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 0) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)) or ((OR_ACLR_INPUTS = 1) and (SIGNED = 0) and (NDIRECTION = 1) and (USE_CARRY_OUT_PORT = 0) and (USE_CARRY_PORT = 0) and (WIDTH = 0) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
b300a8f0f68784a1bb1a904836789845
| 0.656171 | 2.992401 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/LOAD_BALANCER.vhd
| 2 | 3,462 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LOAD_BALANCER is
PORT (
CORE_ID : IN STD_LOGIC;
ADDRESS_A_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C0 : IN STD_LOGIC;
ADDRESS_A_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_C1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_C1 : IN STD_LOGIC;
ADDRESS_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_IO : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
IO_ENABLE : IN STD_LOGIC;
global_enable : IN STD_LOGIC_VECTOR (5 downto 0);
ADDRESS_A_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W_MAG : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN_MAG : OUT STD_LOGIC
);
end;
architecture balancer of LOAD_BALANCER is
begin
process (CORE_ID, ADDRESS_A_C0, ADDRESS_B_C0, ADDRESS_C_C0, ADDRESS_0_C0, ADDRESS_1_C0, ADDRESS_W_C0,
ADDRESS_A_C1, ADDRESS_B_C1, ADDRESS_C_C1, ADDRESS_0_C1, ADDRESS_1_C1, ADDRESS_W_C1,
DATA_TO_W_C0, DATA_TO_W_C1, W_EN_C0, W_EN_C1, IO_ENABLE, ADDRESS_IO, DATA_IO, global_enable) begin
if (CORE_ID = '0') then
if (IO_ENABLE = '1') then
ADDRESS_A_MAG <= "00000000000000000000000000000000";
ADDRESS_B_MAG <= "00000000000000000000000000000001";
ADDRESS_C_MAG <= "00000000000000000000000000000010";
ADDRESS_0_MAG <= "00000000000000000000000000000011";
ADDRESS_1_MAG <= "00000000000000000000000000000100";
DATA_TO_W_MAG <= DATA_IO;
ADDRESS_W_MAG <= ADDRESS_IO;
W_EN_MAG <= '1';
else
ADDRESS_A_MAG <= ADDRESS_A_C0;
ADDRESS_B_MAG <= ADDRESS_B_C0;
ADDRESS_C_MAG <= ADDRESS_C_C0;
ADDRESS_0_MAG <= ADDRESS_0_C0;
ADDRESS_1_MAG <= ADDRESS_1_C0;
ADDRESS_W_MAG <= ADDRESS_W_C0;
DATA_TO_W_MAG <= DATA_TO_W_C0;
W_EN_MAG <= W_EN_C0;
end if;
else
if (IO_ENABLE = '1') then
ADDRESS_A_MAG <= "00000000000000000000000000000000";
ADDRESS_B_MAG <= "00000000000000000000000000000001";
ADDRESS_C_MAG <= "00000000000000000000000000000010";
ADDRESS_0_MAG <= "00000000000000000000000000000011";
ADDRESS_1_MAG <= "00000000000000000000000000000100";
DATA_TO_W_MAG <= DATA_IO;
ADDRESS_W_MAG <= ADDRESS_IO;
W_EN_MAG <= '1';
else
ADDRESS_A_MAG <= ADDRESS_A_C1;
ADDRESS_B_MAG <= ADDRESS_B_C1;
ADDRESS_C_MAG <= ADDRESS_C_C1;
ADDRESS_0_MAG <= ADDRESS_0_C1;
ADDRESS_1_MAG <= ADDRESS_1_C1;
ADDRESS_W_MAG <= ADDRESS_W_C1;
DATA_TO_W_MAG <= DATA_TO_W_C1;
W_EN_MAG <= W_EN_C1;
end if;
end if;
end process;
end;
|
gpl-2.0
|
0cf903783baf86decc64d8a8f4a091b8
| 0.624206 | 2.715294 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/ipcore_dir/tmp/_cg/Instruct_Memory/simulation/Instruct_Memory_tb.vhd
| 2 | 4,559 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Instruct_Memory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Instruct_Memory_tb IS
END ENTITY;
ARCHITECTURE Instruct_Memory_tb_ARCH OF Instruct_Memory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Instruct_Memory_synth_inst:ENTITY work.Instruct_Memory_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
mit
|
e047106a0b14e23ea0e5793c1955bc2f
| 0.618776 | 4.623732 | false | false | false | false |
bobxiv/DispositivosLogicosProgramables-FICH
|
Practica/Contador binario vhdl/clock.vhd
| 1 | 1,985 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:06:03 10/20/11
-- Design Name:
-- Module Name: Binary Counter. 8 bits. Reset asinc. Clock enable.
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Entidad de un contador binario de 8 bits con reset asincronico
--linea de clock enable, y flanco decreciente de reloj
entity ContadorBinario is
port( clock : in std_logic;
clock_enable : in std_logic;
reset : in std_logic;
count_direction : in std_logic;
count : out std_logic_vector(7 downto 0) );
end ContadorBinario;
--Contador binario con:
--clock_enable(CE) -> habilita o desabilita
--reset -> ante un 1 asincronicamente(es como el clock) pone todo a 0
--count_direction(Up/Down) -> Si es 1 aumenta el contador, si es 0 disminuye el clock
architecture ContadorBinarioArchitecture of ContadorBinario is
--la señal temporal es para llevar el conteo, si usaria count
--como lo tengo que leer para incrementarlo deberia ser de inout
--en vez de solo out
signal count_temp : std_logic_vector(7 downto 0);
begin
process (clock, reset)--el proceso se activa al modificar el clock o reset
begin
if reset='1' then
count_temp <= (others => '0');--resetea todo
elsif clock='1' and clock'event then--osea rising_edge(clock) flanco...
if clock_enable='1' then
if count_direction='1' then
count_temp <= count_temp + 1;--incremento
else
count_temp <= count_temp - 1;--decremento
end if;
end if;
end if;
count <= count_temp;
end process;
end ContadorBinarioArchitecture;
|
gpl-3.0
|
71417c7cc0e3ed7fd53d6d5559e4d3b5
| 0.620655 | 3.675926 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/common_28nm_mlab_cell_core/_primary.vhd
| 5 | 1,641 |
library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_core is
generic(
first_address : integer := 0;
last_address : integer := 0;
data_width : integer := 20;
address_width : integer := 6;
byte_enable_mask_width: integer := 1;
mem_init0 : string := "";
MEM_INIT_STRING_LENGTH: integer := 160;
port_byte_size : vl_notype;
num_rows : vl_notype;
num_cols : integer := 1
);
port(
datain_a_reg : in vl_logic_vector;
addr_a_reg : in vl_logic_vector;
byteena_a_reg : in vl_logic_vector;
portbaddr : in vl_logic_vector;
clk_a_in : in vl_logic;
ena0 : in vl_logic;
dataout_b : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of first_address : constant is 1;
attribute mti_svvh_generic_type of last_address : constant is 1;
attribute mti_svvh_generic_type of data_width : constant is 1;
attribute mti_svvh_generic_type of address_width : constant is 1;
attribute mti_svvh_generic_type of byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of MEM_INIT_STRING_LENGTH : constant is 1;
attribute mti_svvh_generic_type of port_byte_size : constant is 3;
attribute mti_svvh_generic_type of num_rows : constant is 3;
attribute mti_svvh_generic_type of num_cols : constant is 1;
end common_28nm_mlab_cell_core;
|
mit
|
8a7b5d694c0a2a78b8ee2b0e31bd50f7
| 0.607556 | 3.575163 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/ama_preadder_function/_primary.vhd
| 5 | 5,462 |
library verilog;
use verilog.vl_types.all;
entity ama_preadder_function is
generic(
preadder_mode : string := "SIMPLE";
width_in_a : integer := 1;
width_in_b : integer := 1;
width_in_c : integer := 1;
width_in_coef : integer := 1;
width_result_a : integer := 1;
width_result_b : integer := 1;
preadder_direction_0: string := "ADD";
preadder_direction_1: string := "ADD";
preadder_direction_2: string := "ADD";
preadder_direction_3: string := "ADD";
representation_preadder_adder: string := "UNSIGNED";
width_in_a_msb : vl_notype;
width_in_b_msb : vl_notype;
width_in_c_msb : vl_notype;
width_in_coef_msb: vl_notype;
width_result_a_msb: vl_notype;
width_result_b_msb: vl_notype;
width_preadder_adder_input: vl_notype;
width_preadder_adder_input_msb: vl_notype;
width_preadder_adder_result: vl_notype;
width_preadder_adder_result_msb: vl_notype;
width_preadder_adder_input_wire: vl_notype;
width_preadder_adder_input_wire_msb: vl_notype;
width_in_a_ext : vl_notype;
width_in_b_ext : vl_notype;
width_output_preadder: vl_notype;
width_output_preadder_msb: vl_notype;
width_output_coef: vl_notype;
width_output_coef_msb: vl_notype;
width_output_datab: vl_notype;
width_output_datab_msb: vl_notype;
width_output_datac: vl_notype;
width_output_datac_msb: vl_notype
);
port(
dataa_in_0 : in vl_logic_vector;
dataa_in_1 : in vl_logic_vector;
dataa_in_2 : in vl_logic_vector;
dataa_in_3 : in vl_logic_vector;
datab_in_0 : in vl_logic_vector;
datab_in_1 : in vl_logic_vector;
datab_in_2 : in vl_logic_vector;
datab_in_3 : in vl_logic_vector;
datac_in_0 : in vl_logic_vector;
datac_in_1 : in vl_logic_vector;
datac_in_2 : in vl_logic_vector;
datac_in_3 : in vl_logic_vector;
coef0 : in vl_logic_vector;
coef1 : in vl_logic_vector;
coef2 : in vl_logic_vector;
coef3 : in vl_logic_vector;
result_a0 : out vl_logic_vector;
result_a1 : out vl_logic_vector;
result_a2 : out vl_logic_vector;
result_a3 : out vl_logic_vector;
result_b0 : out vl_logic_vector;
result_b1 : out vl_logic_vector;
result_b2 : out vl_logic_vector;
result_b3 : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of preadder_mode : constant is 1;
attribute mti_svvh_generic_type of width_in_a : constant is 1;
attribute mti_svvh_generic_type of width_in_b : constant is 1;
attribute mti_svvh_generic_type of width_in_c : constant is 1;
attribute mti_svvh_generic_type of width_in_coef : constant is 1;
attribute mti_svvh_generic_type of width_result_a : constant is 1;
attribute mti_svvh_generic_type of width_result_b : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1;
attribute mti_svvh_generic_type of representation_preadder_adder : constant is 1;
attribute mti_svvh_generic_type of width_in_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_in_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_in_c_msb : constant is 3;
attribute mti_svvh_generic_type of width_in_coef_msb : constant is 3;
attribute mti_svvh_generic_type of width_result_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_result_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_input : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_input_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_result_msb : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_input_wire : constant is 3;
attribute mti_svvh_generic_type of width_preadder_adder_input_wire_msb : constant is 3;
attribute mti_svvh_generic_type of width_in_a_ext : constant is 3;
attribute mti_svvh_generic_type of width_in_b_ext : constant is 3;
attribute mti_svvh_generic_type of width_output_preadder : constant is 3;
attribute mti_svvh_generic_type of width_output_preadder_msb : constant is 3;
attribute mti_svvh_generic_type of width_output_coef : constant is 3;
attribute mti_svvh_generic_type of width_output_coef_msb : constant is 3;
attribute mti_svvh_generic_type of width_output_datab : constant is 3;
attribute mti_svvh_generic_type of width_output_datab_msb : constant is 3;
attribute mti_svvh_generic_type of width_output_datac : constant is 3;
attribute mti_svvh_generic_type of width_output_datac_msb : constant is 3;
end ama_preadder_function;
|
mit
|
325858ba7a68f829844d1a89e786ef9e
| 0.633834 | 3.456962 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_clock.vhd
| 8 | 2,153 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_clock is
generic (
RESET : string := "ACTIVE_HIGH";
DOMAIN : string := "default"
);
port (
clock_out : out std_logic;
clock : in std_logic := '0';
aclr_out : out std_logic;
aclr : in std_logic := '0';
aclr_n : in std_logic := '0'
);
end entity alt_dspbuilder_clock;
architecture rtl of alt_dspbuilder_clock is
component alt_dspbuilder_clock_GNF343OQUJ is
generic (
RESET : string := "ACTIVE_LOW";
DOMAIN : string := "default"
);
port (
aclr_n : in std_logic := '0';
aclr_out : out std_logic;
clock : in std_logic := '0';
clock_out : out std_logic
);
end component alt_dspbuilder_clock_GNF343OQUJ;
component alt_dspbuilder_clock_GNQFU4PUDH is
generic (
RESET : string := "ACTIVE_HIGH";
DOMAIN : string := "default"
);
port (
aclr : in std_logic := '0';
aclr_out : out std_logic;
clock : in std_logic := '0';
clock_out : out std_logic
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
begin
alt_dspbuilder_clock_GNF343OQUJ_0: if ((RESET = "ACTIVE_LOW") and (DOMAIN = "default")) generate
inst_alt_dspbuilder_clock_GNF343OQUJ_0: alt_dspbuilder_clock_GNF343OQUJ
generic map(RESET => "ACTIVE_LOW", DOMAIN => "default")
port map(aclr_n => aclr_n, aclr_out => aclr_out, clock => clock, clock_out => clock_out);
end generate;
alt_dspbuilder_clock_GNQFU4PUDH_1: if ((RESET = "ACTIVE_HIGH") and (DOMAIN = "default")) generate
inst_alt_dspbuilder_clock_GNQFU4PUDH_1: alt_dspbuilder_clock_GNQFU4PUDH
generic map(RESET => "ACTIVE_HIGH", DOMAIN => "default")
port map(aclr => aclr, aclr_out => aclr_out, clock => clock, clock_out => clock_out);
end generate;
assert not (((RESET = "ACTIVE_LOW") and (DOMAIN = "default")) or ((RESET = "ACTIVE_HIGH") and (DOMAIN = "default")))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
caa6879d0f1e8ef92b84a5aecd45cc91
| 0.685555 | 3.124819 | false | false | false | false |
straywarrior/MadeCPUin21days
|
ClockDiv.vhd
| 1 | 2,457 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 23:19:33 11/16/2015
-- Design Name:
-- Module Name: ClockDiv - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ClockDiv is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_2t : out STD_LOGIC;
clk_4t : out STD_LOGIC;
clk_16t : out STD_LOGIC
);
end ClockDiv;
architecture Behavioral of ClockDiv is
signal clk_2t_q : STD_LOGIC := '0';
signal div_4t : STD_LOGIC := '0';
signal clk_4t_q : STD_LOGIC := '0';
signal div_16t : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal clk_16t_q : STD_LOGIC := '0';
begin
process (clk, reset)
begin
if (reset = '0') then
div_4t <= '0';
elsif (clk'event and clk = '1') then
div_4t <= not div_4t;
end if;
end process;
process (clk, reset)
begin
if (reset = '0') then
div_16t <= (others => '0');
elsif (clk'event and clk = '1') then
div_16t <= div_16t + '1';
end if;
end process;
process (clk, reset)
begin
if (reset = '0') then
clk_2t_q <= '0';
clk_4t_q <= '0';
clk_16t_q <= '0';
elsif (clk'event and clk = '1') then
clk_2t_q <= not clk_2t_q;
if (div_4t = '0') then
clk_4t_q <= not clk_4t_q;
else
clk_4t_q <= clk_4t_q;
end if;
if (div_16t = "0000") then
clk_16t_q <= not clk_16t_q;
else
clk_16t_q <= clk_16t_q;
end if;
end if;
end process;
clk_2t <= clk_2t_q;
clk_4t <= clk_4t_q;
clk_16t <= clk_16t_q;
end Behavioral;
|
gpl-2.0
|
c5e57af534c09d789bebe50fca66facf
| 0.488807 | 3.485106 | false | false | false | false |
straywarrior/MadeCPUin21days
|
InstDecoder_simplify.vhd
| 1 | 26,914 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 15:16:45 11/14/2015
-- Design Name:
-- Module Name: InstDecoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstDecoder is
Port ( pc : in STD_LOGIC_VECTOR (15 downto 0);
inst : in STD_LOGIC_VECTOR (15 downto 0);
RegAVal : in STD_LOGIC_VECTOR (15 downto 0);
RegBVal : in STD_LOGIC_VECTOR (15 downto 0);
RAVal : in STD_LOGIC_VECTOR (15 downto 0);
SPVal : in STD_LOGIC_VECTOR (15 downto 0);
IHVal : in STD_LOGIC_VECTOR (15 downto 0);
T_in : in STD_LOGIC;
T_out : out STD_LOGIC;
pc_imm : out STD_LOGIC_VECTOR (15 downto 0);
pc_sel : out STD_LOGIC_VECTOR (1 downto 0);
RegWE : out STD_LOGIC;
RegDest : out STD_LOGIC_VECTOR (3 downto 0);
MemRd : out STD_LOGIC;
MemDIn : out STD_LOGIC_VECTOR (15 downto 0);
MemWE : out STD_LOGIC;
opcode : out STD_LOGIC_VECTOR (3 downto 0);
RegOpA : out STD_LOGIC_VECTOR (3 downto 0);
RegOpB : out STD_LOGIC_VECTOR (3 downto 0);
CReg : out STD_LOGIC;
CRegA : out STD_LOGIC_VECTOR (3 downto 0);
CRegB : out STD_LOGIC_VECTOR (3 downto 0);
operandA : out STD_LOGIC_VECTOR (15 downto 0);
operandB : out STD_LOGIC_VECTOR (15 downto 0)
);
end InstDecoder;
architecture Behavioral of InstDecoder is
begin
operandA <=
RegAVal when (inst(15 downto 11) = "11100" or (inst(15 downto 11) = "11101" and inst(4 downto 2) = "011")) else
pc when (inst(15 downto 11) = "11101" and inst(4 downto 0) = "00000") else
RegBVal when (inst(15 downto 11) = "11101" and inst(4 downto 2) = "001") else
(others => '0') when (inst(15 downto 11) = "11101" and inst(4 downto 0) = "01011") else
RegAVal when (inst(15 downto 11) = "11110" and inst(1 downto 0) = "01") or (inst(15 downto 11) = "01000") or (inst(15 downto 11) = "01001") else
IHVal when (inst(15 downto 11) = "11110" and inst(1 downto 0) = "00") else
RegBVal when (inst(15 downto 11) = "00110" or inst(15 downto 11) = "01111" or (inst(15 dowto 11) = "01100" and inst(10 downto 8) = "100")) else
SPVal when ((inst(15 downto 11) = "01100" and (inst(10 downo 8) = "010" or inst(10 downto 8) = "011")) or inst(15 downto 11) = "00000") else
-- Use Process firt. TODO: Rewrite to combinational logic circuit
process (inst, pc, RegAVal, RegBVal, T_in, IHVal, RAVal, SPVal)
begin
case inst(15 downto 11) is
-- R type instruction
when "11100" =>
case inst(1 downto 0) is
when "01" => opcode <= "0000";
when "11" => opcode <= "0001";
when others => opcode <= "1111"; -- 1111 means doing nothing
end case;
operandA <= RegAVal;
operandB <= RegBVal;
RegDest(2 downto 0) <= inst(4 downto 2);
RegDest(3) <= '0';
RegWE <= '1';
MemWE <= '0';
MemRd <= '0';
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB(2 downto 0) <= inst(7 downto 5);
RegOpB(3) <= '0';
pc_sel <= "00";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
-- R type instruction & J type instruction (excpet INT & NOP)
when "11101" =>
case inst(4 downto 2) is
when "000" => -- SLT SLTU & MFPC JR JRRA JALR
RegOpA <= "1111";
RegOpB <= "1111";
case inst(1 downto 0) is
when "10" => -- SLT
if (signed(RegAVal) < signed(RegBVal)) then
T_out <= '1';
else
T_out <= '0';
end if;
RegDest <= "1111"; -- dummy number
pc_sel <= "00";
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB(2 downto 0) <= inst(7 downto 5); CRegB(3) <= '0';
when "11" => -- SLTU
if (unsigned(RegAVal) < unsigned(RegBVal)) then
T_out <= '1';
else
T_out <= '0';
end if;
RegDest <= "1111"; -- dummy number
pc_sel <= "00";
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB(2 downto 0) <= inst(7 downto 5); CRegB(3) <= '0';
when "00" => -- MFPC JR JRRA JALR
opcode <= "1111";
T_out <= T_in;
case inst(7 downto 5) is
when "010" => -- MFPC
operandA <= pc;
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
pc_sel <= "00";
CReg <= '0';
when "000" => -- JR TODO: PC Select!!!
pc_sel <= "10";
RegDest <= "1111"; -- dummy number
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB <= "1111";
when "001" => -- JRRA
pc_sel <= "01";
RegDest <= "1111"; -- dummy number
CReg <= '1';
CRegA <= "1000";
CRegB <= "1111";
null;
when "110" => -- JALR
pc_sel <= "10";
operandA <= pc;
RegDest <= "1000";
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB <= "1111";
when others => null;
end case;
when others => null;
end case;
when "001" => -- SLLV SRLV SRAV
case inst(1 downto 0) is
when "00" => opcode <= "1000";
when "10" => opcode <= "1010";
when "11" => opcode <= "1011";
when others => null;
end case;
operandA <= RegBVal;
operandB <= RegAVal;
-- RegDest is ry
RegDest(2 downto 0) <= inst(7 downto 5);
RegDest(3) <= '0';
RegOpA(2 downto 0) <= inst(7 downto 5);
RegOpA(3) <= '0';
RegOpB(2 downto 0) <= inst(10 downto 8);
RegOpB(3) <= '0';
pc_sel <= "00";
CReg <= '0';
T_out <= T_in;
when "010" => -- CMP NEG
case inst(1 downto 0) is
when "10" => -- CMP
if (RegAVal = RegBVal) then
T_out <= '0';
else
T_out <= '1';
end if;
RegDest <= "1111";
RegOpA <= "1111";
RegOpB <= "1111";
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB(2 downto 0) <= inst(7 downto 5); CRegB(3) <= '0';
when "11" => -- NEG
opcode <= "0001";
operandA <= (others => '0');
operandB <= RegBVal;
RegDest(2 downto 0) <= inst(10 downto 8); RegDest(3) <= '0';
RegOpA <= "1111";
RegOpB(2 downto 0) <= inst(7 downto 5); RegOpB(3) <= '0';
CReg <= '0';
T_out <= T_in;
when others => null;
end case;
pc_sel <= "00";
when "011" => -- AND OR XOR NOT
case inst(1 downto 0) is
when "00" => opcode <= "0100";
when "01" => opcode <= "0101";
when "10" => opcode <= "0110";
when "11" => opcode <= "0111";
when others => null;
end case;
operandA <= RegAVal;
operandB <= RegBVal;
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB(2 downto 0) <= inst(7 downto 5);
RegOpB(3) <= '0';
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
pc_sel <= "00";
CReg <= '0';
T_out <= T_in;
when others =>
pc_sel <= "00";
opcode <= "1111"; -- 1111 means doing nothing
RegOpA <= "1111";
RegOpA <= "1111";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
end case;
RegWE <= '1';
MemWE <= '0';
MemRd <= '0';
-- prefix "11101" ended
when "11110" => -- MFIH MTIH
case inst(1 downto 0) is
when "00" => --MFIH
operandA <= IHVal;
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
RegOpA <= "1010";
when "01" => --MTIH
operandA <= RegAVal;
RegDest <= "1010";
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
when others => null;
end case;
opcode <= "1111";
RegWE <= '1';
MemWE <= '0';
MemRd <= '0';
RegOpB <= "1111";
pc_sel <= "00";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "00110" => -- SRL SRA SLL
case inst(1 downto 0) is
when "00" => -- SLL
opcode <= "1000";
when "10" => -- SRL
opcode <= "1010";
when "11" => -- SRA
opcode <= "1011";
when others => null;
end case;
RegWE <= '1';
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
operandA <= RegBVal;
if (inst(4 downto 2) = "000") then
operandB(3) <= '1';
else
operandB(3) <= '0';
end if;
operandB(2 downto 0) <= inst(4 downto 2);
operandB(15 downto 4) <= (others => '0');
MemWE <= '0';
MemRd <= '0';
RegOpA(2 downto 0) <= inst(7 downto 5);
RegOpA(3) <= '0';
RegOpB <= "1111";
pc_sel <= "00";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01111" => -- MOVE
opcode <= "1111";
operandA <= RegBVal;
RegWE <= '1';
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
MemWE <= '0';
MemRd <= '0';
RegOpA(2 downto 0) <= inst(7 downto 5);
RegOpA(3) <= '0';
RegOpB <= "1111";
pc_sel <= "00";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01100" => -- MTSP SW_RS ADDSP BTEQZ BTNEZ
case inst(10 downto 8) is
when "100" => -- MTSP
opcode <= "1111";
operandA <= RegBVal; -- NOTE: ry here is "rx"
RegWE <= '1';
RegDest <= "1001";
MemWE <= '0';
RegOpA(2 downto 0) <= inst(7 downto 5); RegOpA(3) <= '0';
RegOpB <= "1111";
pc_sel <= "00";
when "010" => -- SW_RS
RegWE <= '0';
MemDIn <= RAVal;
MemWE <= '1';
opcode <= "0000";
operandA <= SPVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7)); -- FIXME? S_EXT OR Z_EXT?
RegOpA <= "1001";
RegOpB <= "1111";
pc_sel <= "00";
when "011" => -- ADDSP
RegWE <= '1';
MemWE <= '0';
RegDest <= "1001";
opcode <= "0000";
operandA <= SPVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7)); -- FIXME? S_EXT OR Z_EXT?
RegOpA <= "1001";
RegOpB <= "1111";
pc_sel <= "00";
when "000" => -- BTEQZ
RegWE <= '0';
MemWE <= '0';
if (T_in = '0') then
pc_sel <= "11";
else
pc_sel <= "00";
end if;
RegOpA <= "1111";
RegOpB <= "1111";
when "001" => -- BTNEZ
RegWE <= '0';
MemWE <= '0';
if (T_in /= '0') then
pc_sel <= "11";
else
pc_sel <= "00";
end if;
RegOpA <= "1111";
RegOpB <= "1111";
when others => null;
end case;
MemRd <= '0';
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "11111" => -- INT TODO!
-- FIXME!!!
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
pc_sel <= "00";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "00001" => -- NOP
pc_sel <= "00";
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "00000" => -- ADDSP3
pc_sel <= "00";
RegWE <= '1';
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
MemWE <= '0';
MemRd <= '0';
opcode <= "0000";
operandA <= SPVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7));
RegOpA <= "1001";
RegOpB <= "1111";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01000" => -- ADDIU3
pc_sel <= "00";
RegWE <= '1';
-- RegDest is ry
RegDest(2 downto 0) <= inst(7 downto 5);
RegDest(3) <= '0';
MemWE <= '0';
MemRd <= '0';
opcode <= "0000";
operandA <= RegAVal;
operandB(3 downto 0) <= inst(3 downto 0);
operandB(15 downto 4) <= (others => inst(3));
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB <= "1111";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01001" => -- ADDIU
pc_sel <= "00";
RegWE <= '1';
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
opcode <= "0000";
MemWE <= '0';
MemRd <= '0';
operandA <= RegAVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7));
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB <= "1111";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01010" => -- SLTI
pc_sel <= "00";
RegWE <= '1';
MemWE <= '0';
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
CReg <= '1';
CRegA <= "1111";
CRegB <= "1111";
if (signed(RegAVal) < signed(inst(7 downto 0))) then
T_out <= '1';
else
T_out <= '0';
end if;
when "01011" => -- SLTUI
pc_sel <= "00";
RegWE <= '1';
MemWE <= '0';
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
CReg <= '1';
CRegA <= "1111";
CRegB <= "1111";
if (unsigned(RegAVal) < unsigned(inst(7 downto 0))) then -- FIXME?
T_out <= '1';
else
T_out <= '0';
end if;
when "01101" => -- LI
pc_sel <= "00";
RegWE <= '1';
MemWE <= '0';
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
opcode <= "1111";
operandA(7 downto 0) <= inst(7 downto 0);
operandA(15 downto 8) <= (others => '0');
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "01110" => -- CMPI
pc_sel <= "00";
RegWE <= '1';
RegDest <= "1111";
MemWE <= '0';
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB <= "1111";
if (signed(RegAVal) = signed(inst(7 downto 0))) then -- FIXME?
T_out <= '0';
else
T_out <= '1';
end if;
when "10010" => -- LW_SP
pc_sel <= "00";
RegWE <= '1';
MemWE <= '0';
MemRd <= '1';
RegOpA <= "1001";
RegOpB <= "1111";
-- RegDest is rx
RegDest(2 downto 0) <= inst(10 downto 8);
RegDest(3) <= '0';
opcode <= "0000";
operandA <= SPVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7));
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "10011" => -- LW
pc_sel <= "00";
RegWE <= '1';
MemWE <= '0';
MemRd <= '1';
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB <= "1111";
-- RegDest is ry
RegDest(2 downto 0) <= inst(7 downto 5);
RegDest(3) <= '0';
opcode <= "0000";
operandA <= RegAVal;
operandB(4 downto 0) <= inst(4 downto 0);
operandB(15 downto 5) <= (others => inst(4));
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "11010" => -- SW_SP
pc_sel <= "00";
RegWE <= '0';
MemWE <= '1';
MemDIn <= RegAVal;
MemRd <= '0';
RegOpA <= "1001";
RegOpB <= "1111";
opcode <= "0000";
operandA <= SPVal;
operandB(7 downto 0) <= inst(7 downto 0);
operandB(15 downto 8) <= (others => inst(7));
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "11011" => -- SW
pc_sel <= "00";
RegWE <= '0';
MemWE <= '1';
MemDIn <= RegBVal;
MemRd <= '0';
RegOpA(2 downto 0) <= inst(10 downto 8);
RegOpA(3) <= '0';
RegOpB <= "1111";
opcode <= "0000";
operandA <= RegAVal;
operandB(4 downto 0) <= inst(4 downto 0);
operandB(15 downto 5) <= (others => inst(4));
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
when "00010" => -- B
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
pc_imm(10 downto 0) <= inst(10 downto 0);
pc_imm(15 downto 11) <= (others => '0');
pc_sel <= "11";
T_out <= T_in;
when "00100" => -- BEQZ
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
pc_imm(7 downto 0) <= inst(7 downto 0);
pc_imm(15 downto 8) <= (others => '0');
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB <= "1111";
T_out <= T_in;
if (RegAVal = "0000000000000000") then
pc_sel <= "11";
else
pc_sel <= "00";
end if;
when "00101" => -- BNEZ
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
pc_imm(7 downto 0) <= inst(7 downto 0);
pc_imm(15 downto 8) <= (others => '0');
CReg <= '1';
CRegA(2 downto 0) <= inst(10 downto 8); CRegA(3) <= '0';
CRegB <= "1111";
T_out <= T_in;
if (RegAVal /= "0000000000000000") then
pc_sel <= "11";
else
pc_sel <= "00";
end if;
when others =>
RegWE <= '0';
MemWE <= '0';
MemRd <= '0';
RegOpA <= "1111";
RegOpB <= "1111";
pc_sel <= "00";
CReg <= '0';
CRegA <= "1111";
CRegB <= "1111";
T_out <= T_in;
end case;
end process;
end Behavioral;
|
gpl-2.0
|
13677a5bb7076bdfbe6a2a12efe09d78
| 0.32537 | 4.858123 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_decoder.vhd
| 2 | 1,567 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
DECODE : string := "01";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(2-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
begin
alt_dspbuilder_decoder_GNM4LOIHXZ_0: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNM4LOIHXZ_0: alt_dspbuilder_decoder_GNM4LOIHXZ
generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
81e7dc5642a483e9d42c7d3287fdb79b
| 0.687939 | 3.211066 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/ip_16z091_01_top_sim.vhd
| 1 | 71,192 |
--------------------------------------------------------------------------------
-- Title : top level module for 16z091-01 design
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : ip_16z091_01_top
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 23.02.2011
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a
-- Synthesis : Quartus II 10.0
--------------------------------------------------------------------------------
-- Description :
-- Toplevel module that combines the 16z091-01 IP core with the Altera hard
-- makro PCIe IP core
--------------------------------------------------------------------------------
-- Hierarchy :
-- * ip_16z091_01_top_core
-- ip_16z091_01
-- Hard_IP
-- z091_01_wb_adr_dec
-- pcie_msi
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.fpga_pkg_2.all;
entity ip_16z091_01_top is
generic(
SIMULATION : std_logic := '0'; -- =1 simulation,=0 synthesis
FPGA_FAMILY : family_type := NONE;
IRQ_WIDTH : integer range 32 downto 1 := 1;
-- only use one of the following 3:
-- 001 := 1 lane, 010 := 2 lanes, 100 := 4 lanes
USE_LANES : std_logic_vector(2 downto 0) := "001";
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
NR_OF_BARS_USED : natural range 6 downto 1 := 5;
VENDOR_ID : natural := 16#1A88#;
DEVICE_ID : natural := 16#4D45#;
REVISION_ID : natural := 16#0#;
CLASS_CODE : natural := 16#068000#;
SUBSYSTEM_VENDOR_ID : natural := 16#9B#;
SUBSYSTEM_DEVICE_ID : natural := 16#5A91#;
BAR_MASK_0 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_1 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_2 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_3 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_4 : std_logic_vector(31 downto 0) := x"FF000001";
BAR_MASK_5 : std_logic_vector(31 downto 0) := x"FF000001";
ROM_MASK : std_logic_vector(31 downto 0) := x"FFFF0000";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000010000"; -- 16DW = 64Byte
RX_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
TX_HEADER_LPM_WIDTHU : integer range 10 DOWNTO 5 := 5;
TX_DATA_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
BFM_LANE_WIDTH : integer range 8 downto 0 := 1; -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
GP_DEBUG_PORT_WIDTH : positive := 1
);
port(
-- Hard IP ports:
clk_50 : in std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
clk_125 : in std_logic; -- 125 MHz clock for fixed_clk, CycloneIV only
ref_clk : in std_logic; -- 100 MHz reference clock
clk_500 : in std_logic; -- 500 Hz clock
ext_rst_n : in std_logic; -- for CycloneV this MUST be connected to
-- nPERSTL0 for top left HardIP
-- nPERSTL1 for bottom left Hard IP <- use this one first (recommended by Altera)
rx_0 : in std_logic;
rx_1 : in std_logic;
rx_2 : in std_logic;
rx_3 : in std_logic;
tx_0 : out std_logic;
tx_1 : out std_logic;
tx_2 : out std_logic;
tx_3 : out std_logic;
-- Wishbone ports:
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
irq_req_i : in std_logic_vector(IRQ_WIDTH -1 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- Hard IP BFM connections
ep_rxvalid_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_i : in std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_clk250_o : out std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_o : out std_logic; -- endpoint SERDES 500MHz clk output
ep_rate_ext_o : out std_logic; -- endpoint rate_ext
ep_powerdown_ext_o : out std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_o : out std_logic_vector(4 downto 0);
-- debug port
gp_debug_port : out std_logic_vector(GP_DEBUG_PORT_WIDTH -1 downto 0); -- general purpose debug port
link_train_active : out std_logic
);
end entity ip_16z091_01_top;
-- ****************************************************************************
-- +----------------------------------------------------------------------------
-- | Architecture for Cyclone IV
-- +----------------------------------------------------------------------------
architecture ip_16z091_01_top_arch of ip_16z091_01_top is
constant MAX_ADDR_VAL : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- := 2^32 - 1
function conv_std_to_string(
in_bit : std_logic
) return string is
begin
if(in_bit = '0') then
return "false";
else
return "true";
end if;
end function conv_std_to_string;
function calc_mask_size(
in_BAR_mask : std_logic_vector;
BAR_No : integer range 5 downto 0
) return integer is
variable in_val : std_logic_vector(31 downto 0) := (others => '0');
variable int_temp : integer := 0;
variable addr_line : integer range 32 downto 1 := 1;
begin
if(BAR_No > NR_OF_BARS_USED - 1) then
return 0;
else
---------------------------------------------------------
-- memory thus unmask I/O, type and prefetch bit values
---------------------------------------------------------
if(in_BAR_mask(0) = '0') then
in_val := in_BAR_mask(31 downto 4) & "0000";
-----------------------------------------
-- I/O thus unmask I/O and reserved bit
-----------------------------------------
else
in_val := in_BAR_mask(31 downto 2) & "00";
end if;
in_val := MAX_ADDR_VAL - in_val;
int_temp := conv_integer(unsigned(in_val));
while int_temp >= 2 loop
addr_line := addr_line + 1;
int_temp := int_temp / 2;
end loop;
return addr_line;
end if;
end function calc_mask_size;
constant IO_SPACE_0 : string := conv_std_to_string(BAR_MASK_0(0));
constant PREFETCH_0 : string := conv_std_to_string(BAR_MASK_0(3));
constant SIZE_MASK_0 : integer := calc_mask_size(BAR_MASK_0, 0);
constant IO_SPACE_1 : string := conv_std_to_string(BAR_MASK_1(0));
constant PREFETCH_1 : string := conv_std_to_string(BAR_MASK_1(3));
constant SIZE_MASK_1 : integer := calc_mask_size(BAR_MASK_1, 1);
constant IO_SPACE_2 : string := conv_std_to_string(BAR_MASK_2(0));
constant PREFETCH_2 : string := conv_std_to_string(BAR_MASK_2(3));
constant SIZE_MASK_2 : integer := calc_mask_size(BAR_MASK_2, 2);
constant IO_SPACE_3 : string := conv_std_to_string(BAR_MASK_3(0));
constant PREFETCH_3 : string := conv_std_to_string(BAR_MASK_3(3));
constant SIZE_MASK_3 : integer := calc_mask_size(BAR_MASK_3, 3);
constant IO_SPACE_4 : string := conv_std_to_string(BAR_MASK_4(0));
constant PREFETCH_4 : string := conv_std_to_string(BAR_MASK_4(3));
constant SIZE_MASK_4 : integer := calc_mask_size(BAR_MASK_4, 4);
constant IO_SPACE_5 : string := conv_std_to_string(BAR_MASK_5(0));
constant PREFETCH_5 : string := conv_std_to_string(BAR_MASK_5(3));
constant SIZE_MASK_5 : integer := calc_mask_size(BAR_MASK_5, 5);
--TODO_ITEM FIX THIS!
--constant SIZE_MASK_ROM : integer := calc_mask_size(ROM_MASK, 6);
constant SIZE_MASK_ROM : integer := calc_mask_size(ROM_MASK, 5);
constant SUPPORTED_DEVICES : supported_family_types := (CYCLONE4, ARRIA2_GX);
-- internal signals -----------------------------------------------------------
signal rst_int : std_logic;
signal core_clk_int : std_logic;
signal crst_int : std_logic;
signal srst_int : std_logic;
signal srstn_int : std_logic;
signal npor_int : std_logic;
signal clk250_int : std_logic;
signal clk250_int_1delta_delay : std_logic;
signal clk250_int_2delta_delay : std_logic;
signal clk250_int_3delta_delay : std_logic;
signal rx_st_data0_int : std_logic_vector(63 downto 0);
signal rx_st_err0_int : std_logic;
signal rx_st_valid0_int : std_logic;
signal rx_st_sop0_int : std_logic;
signal rx_st_eop0_int : std_logic;
signal rx_st_be0_int : std_logic_vector(7 downto 0);
signal rx_st_bardec0_int : std_logic_vector(7 downto 0);
signal tx_st_ready0_int : std_logic;
signal tx_fifo_full0_int : std_logic;
signal tx_fifo_empty0_int : std_logic;
signal tx_fifo_rdptr0_int : std_logic_vector(3 downto 0);
signal tx_fifo_wrptr0_int : std_logic_vector(3 downto 0);
signal pme_to_sr_int : std_logic;
signal tl_cfg_add_int : std_logic_vector(3 downto 0);
signal tl_cfg_ctl_int : std_logic_vector(31 downto 0);
signal tl_cfg_ctl_wr_int : std_logic;
signal tl_cfg_sts_int : std_logic_vector(52 downto 0);
signal tl_cfg_sts_wr_int : std_logic;
signal app_int_ack_int : std_logic;
signal app_msi_ack_int : std_logic;
signal rx_st_mask0_int : std_logic;
signal rx_st_ready0_int : std_logic;
signal tx_st_err0_int : std_logic;
signal tx_st_valid0_int : std_logic;
signal tx_st_sop0_int : std_logic;
signal tx_st_eop0_int : std_logic;
signal tx_st_data0_int : std_logic_vector(63 downto 0);
signal pme_to_cr_int : std_logic;
signal app_int_sts_int : std_logic;
signal app_msi_req_int : std_logic;
signal app_msi_tc_int : std_logic_vector(2 downto 0);
signal app_msi_num_int : std_logic_vector(4 downto 0);
signal pex_msi_num_int : std_logic_vector(4 downto 0);
signal derr_cor_ext_rcv_int : std_logic_vector(1 downto 0) := "00";
signal derr_cor_ext_rpl_int : std_logic;
signal derr_rpl_int : std_logic;
signal r2c_err0_int : std_logic;
signal cpl_err_int : std_logic_vector(6 downto 0);
signal cpl_pending_int : std_logic;
--signal int_bar_hit : std_logic_vector(6 downto 0);
--signal wbm_adr_int : std_logic_vector(31 downto 0);
signal reconfig_fromgxb_int : std_logic_vector (4 downto 0);
signal reconfig_togxb_int : std_logic_vector (3 downto 0);
SIGNAL reconf_busy : std_logic;
signal pll_powerdown_int : std_logic;
signal l2_exit : std_logic;
signal hotrst_exit : std_logic;
signal dlup_exit : std_logic;
signal rst_cwh : std_logic;
signal rst_cwh_cnt : std_logic_vector (1 downto 0);
--signal wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
--signal wbm_cyc_o_int_d : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0); --mwawrik: delayed cycle causes problems
signal test_in_int : std_logic_vector(39 downto 0);
signal pipe_mode_int : std_logic;
signal txdetectrx_int : std_logic;
signal powerdown_int : std_logic_vector(1 downto 0);
-- signals to connect pcie_msi
signal int_wb_int : std_logic;
signal int_wb_pwr_enable : std_logic;
signal int_wb_int_num : std_logic_vector(4 downto 0);
signal int_wb_int_ack : std_logic;
signal int_wb_int_num_allowed : std_logic_vector(5 downto 0);
signal int_ltssm : std_logic_vector(4 downto 0);
signal reconfig_clk_locked_int : std_logic;
signal reconfig_clk_int : std_logic;
signal fixedclk_serdes_int : std_logic;
-------------------------------------------------------------------------------
-- components -----------------------------------------------------------------
component ip_16z091_01
generic(
FPGA_FAMILY : family_type := NONE;
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
READY_LATENCY : natural := 2;
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001";
WBM_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011";
WBM_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111";
WBS_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111100";
WBS_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000";
RX_FIFO_DEPTH : natural := 1024;
RX_LPM_WIDTHU : natural := 10;
TX_HEADER_FIFO_DEPTH : natural := 32;
TX_HEADER_LPM_WIDTHU : natural := 5;
TX_DATA_FIFO_DEPTH : natural := 1024;
TX_DATA_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
wb_clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
wb_rst : in std_logic;
-- IP Core
core_clk : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tl_cfg_add : in std_logic_vector(3 downto 0);
tl_cfg_ctl : in std_logic_vector(31 downto 0);
tl_cfg_ctl_wr : in std_logic;
tl_cfg_sts : in std_logic_vector(52 downto 0);
tl_cfg_sts_wr : in std_logic;
app_int_ack : in std_logic;
app_msi_ack : in std_logic;
rx_st_mask0 : out std_logic;
rx_st_ready0 : out std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
tx_st_data0 : out std_logic_vector(63 downto 0);
pme_to_cr : out std_logic;
app_int_sts : out std_logic;
app_msi_req : out std_logic;
app_msi_tc : out std_logic_vector(2 downto 0);
app_msi_num : out std_logic_vector(4 downto 0);
pex_msi_num : out std_logic_vector(4 downto 0);
derr_cor_ext_rcv : in std_logic_vector(1 downto 0);
derr_cor_ext_rpl : in std_logic;
derr_rpl : in std_logic;
r2c_err0 : in std_logic;
cpl_err : out std_logic_vector(6 downto 0);
cpl_pending : out std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
--wb_bar_dec : out std_logic_vector(6 downto 0);
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
wb_int : in std_logic;
wb_pwr_enable : in std_logic;
wb_int_num : in std_logic_vector(4 downto 0);
wb_int_ack : out std_logic;
wb_int_num_allowed : out std_logic_vector(5 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- debug port
rx_debug_out : out std_logic_vector(3 downto 0)
);
end component;
component Hard_IP_x1
port (
-- inputs:
signal app_int_sts : IN STD_LOGIC;
signal app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal app_msi_req : IN STD_LOGIC;
signal app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal busy_altgxb_reconfig : IN STD_LOGIC;
signal cal_blk_clk : IN STD_LOGIC;
signal cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal cpl_pending : IN STD_LOGIC;
signal crst : IN STD_LOGIC;
signal fixedclk_serdes : IN STD_LOGIC;
signal gxb_powerdown : IN STD_LOGIC;
signal hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal lmi_rden : IN STD_LOGIC;
signal lmi_wren : IN STD_LOGIC;
signal npor : IN STD_LOGIC;
signal pclk_in : IN STD_LOGIC;
signal pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal phystatus_ext : IN STD_LOGIC;
signal pipe_mode : IN STD_LOGIC;
signal pld_clk : IN STD_LOGIC;
signal pll_powerdown : IN STD_LOGIC;
signal pm_auxpwr : IN STD_LOGIC;
signal pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pm_event : IN STD_LOGIC;
signal pme_to_cr : IN STD_LOGIC;
signal reconfig_clk : IN STD_LOGIC;
signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk : IN STD_LOGIC;
signal rx_in0 : IN STD_LOGIC;
signal rx_st_mask0 : IN STD_LOGIC;
signal rx_st_ready0 : IN STD_LOGIC;
signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext : IN STD_LOGIC;
signal rxelecidle0_ext : IN STD_LOGIC;
signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext : IN STD_LOGIC;
signal srst : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_st_eop0 : IN STD_LOGIC;
signal tx_st_err0 : IN STD_LOGIC;
signal tx_st_sop0 : IN STD_LOGIC;
signal tx_st_valid0 : IN STD_LOGIC;
-- outputs:
signal app_clk : OUT STD_LOGIC;
signal app_int_ack : OUT STD_LOGIC;
signal app_msi_ack : OUT STD_LOGIC;
signal clk250_out : OUT STD_LOGIC;
signal clk500_out : OUT STD_LOGIC;
signal core_clk_out : OUT STD_LOGIC;
signal derr_cor_ext_rcv0 : OUT STD_LOGIC;
signal derr_cor_ext_rpl : OUT STD_LOGIC;
signal derr_rpl : OUT STD_LOGIC;
signal dlup_exit : OUT STD_LOGIC;
signal hotrst_exit : OUT STD_LOGIC;
signal ko_cpl_spc_vc0 : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal l2_exit : OUT STD_LOGIC;
signal lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal lmi_ack : OUT STD_LOGIC;
signal lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal pme_to_sr : OUT STD_LOGIC;
signal powerdown_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal r2c_err0 : OUT STD_LOGIC;
signal rate_ext : OUT STD_LOGIC;
signal rc_pll_locked : OUT STD_LOGIC;
signal rc_rx_digitalreset : OUT STD_LOGIC;
signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reset_status : OUT STD_LOGIC;
signal rx_fifo_empty0 : OUT STD_LOGIC;
signal rx_fifo_full0 : OUT STD_LOGIC;
signal rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal rx_st_eop0 : OUT STD_LOGIC;
signal rx_st_err0 : OUT STD_LOGIC;
signal rx_st_sop0 : OUT STD_LOGIC;
signal rx_st_valid0 : OUT STD_LOGIC;
signal rxpolarity0_ext : OUT STD_LOGIC;
signal suc_spd_neg : OUT STD_LOGIC;
signal test_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal tl_cfg_ctl_wr : OUT STD_LOGIC;
signal tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
signal tl_cfg_sts_wr : OUT STD_LOGIC;
signal tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tx_fifo_empty0 : OUT STD_LOGIC;
signal tx_fifo_full0 : OUT STD_LOGIC;
signal tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_out0 : OUT STD_LOGIC;
signal tx_st_ready0 : OUT STD_LOGIC;
signal txcompl0_ext : OUT STD_LOGIC;
signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext : OUT STD_LOGIC;
signal txdetectrx_ext : OUT STD_LOGIC;
signal txelecidle0_ext : OUT STD_LOGIC
);
end component;
COMPONENT Hard_IP_x4 is
port (
-- inputs:
signal app_int_sts : IN STD_LOGIC;
signal app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal app_msi_req : IN STD_LOGIC;
signal app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal busy_altgxb_reconfig : IN STD_LOGIC;
signal cal_blk_clk : IN STD_LOGIC;
signal cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal cpl_pending : IN STD_LOGIC;
signal crst : IN STD_LOGIC;
signal fixedclk_serdes : IN STD_LOGIC;
signal gxb_powerdown : IN STD_LOGIC;
signal hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal lmi_rden : IN STD_LOGIC;
signal lmi_wren : IN STD_LOGIC;
signal npor : IN STD_LOGIC;
signal pclk_in : IN STD_LOGIC;
signal pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal phystatus_ext : IN STD_LOGIC;
signal pipe_mode : IN STD_LOGIC;
signal pld_clk : IN STD_LOGIC;
signal pll_powerdown : IN STD_LOGIC;
signal pm_auxpwr : IN STD_LOGIC;
signal pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pm_event : IN STD_LOGIC;
signal pme_to_cr : IN STD_LOGIC;
signal reconfig_clk : IN STD_LOGIC;
signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk : IN STD_LOGIC;
signal rx_in0 : IN STD_LOGIC;
signal rx_in1 : IN STD_LOGIC;
signal rx_in2 : IN STD_LOGIC;
signal rx_in3 : IN STD_LOGIC;
signal rx_st_mask0 : IN STD_LOGIC;
signal rx_st_ready0 : IN STD_LOGIC;
signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata1_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata2_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata3_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext : IN STD_LOGIC;
signal rxdatak1_ext : IN STD_LOGIC;
signal rxdatak2_ext : IN STD_LOGIC;
signal rxdatak3_ext : IN STD_LOGIC;
signal rxelecidle0_ext : IN STD_LOGIC;
signal rxelecidle1_ext : IN STD_LOGIC;
signal rxelecidle2_ext : IN STD_LOGIC;
signal rxelecidle3_ext : IN STD_LOGIC;
signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus1_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus2_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus3_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext : IN STD_LOGIC;
signal rxvalid1_ext : IN STD_LOGIC;
signal rxvalid2_ext : IN STD_LOGIC;
signal rxvalid3_ext : IN STD_LOGIC;
signal srst : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_st_eop0 : IN STD_LOGIC;
signal tx_st_err0 : IN STD_LOGIC;
signal tx_st_sop0 : IN STD_LOGIC;
signal tx_st_valid0 : IN STD_LOGIC;
-- outputs:
signal app_int_ack : OUT STD_LOGIC;
signal app_msi_ack : OUT STD_LOGIC;
signal clk250_out : OUT STD_LOGIC;
signal clk500_out : OUT STD_LOGIC;
signal core_clk_out : OUT STD_LOGIC;
signal derr_cor_ext_rcv0 : OUT STD_LOGIC;
signal derr_cor_ext_rpl : OUT STD_LOGIC;
signal derr_rpl : OUT STD_LOGIC;
signal dlup_exit : OUT STD_LOGIC;
signal hotrst_exit : OUT STD_LOGIC;
signal ko_cpl_spc_vc0 : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal l2_exit : OUT STD_LOGIC;
signal lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal lmi_ack : OUT STD_LOGIC;
signal lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal pme_to_sr : OUT STD_LOGIC;
signal powerdown_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal r2c_err0 : OUT STD_LOGIC;
signal rate_ext : OUT STD_LOGIC;
signal rc_pll_locked : OUT STD_LOGIC;
signal rc_rx_digitalreset : OUT STD_LOGIC;
signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reset_status : OUT STD_LOGIC;
signal rx_fifo_empty0 : OUT STD_LOGIC;
signal rx_fifo_full0 : OUT STD_LOGIC;
signal rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal rx_st_eop0 : OUT STD_LOGIC;
signal rx_st_err0 : OUT STD_LOGIC;
signal rx_st_sop0 : OUT STD_LOGIC;
signal rx_st_valid0 : OUT STD_LOGIC;
signal rxpolarity0_ext : OUT STD_LOGIC;
signal rxpolarity1_ext : OUT STD_LOGIC;
signal rxpolarity2_ext : OUT STD_LOGIC;
signal rxpolarity3_ext : OUT STD_LOGIC;
signal suc_spd_neg : OUT STD_LOGIC;
signal test_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal tl_cfg_ctl_wr : OUT STD_LOGIC;
signal tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
signal tl_cfg_sts_wr : OUT STD_LOGIC;
signal tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tx_fifo_empty0 : OUT STD_LOGIC;
signal tx_fifo_full0 : OUT STD_LOGIC;
signal tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_out0 : OUT STD_LOGIC;
signal tx_out1 : OUT STD_LOGIC;
signal tx_out2 : OUT STD_LOGIC;
signal tx_out3 : OUT STD_LOGIC;
signal tx_st_ready0 : OUT STD_LOGIC;
signal txcompl0_ext : OUT STD_LOGIC;
signal txcompl1_ext : OUT STD_LOGIC;
signal txcompl2_ext : OUT STD_LOGIC;
signal txcompl3_ext : OUT STD_LOGIC;
signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata1_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata2_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata3_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext : OUT STD_LOGIC;
signal txdatak1_ext : OUT STD_LOGIC;
signal txdatak2_ext : OUT STD_LOGIC;
signal txdatak3_ext : OUT STD_LOGIC;
signal txdetectrx_ext : OUT STD_LOGIC;
signal txelecidle0_ext : OUT STD_LOGIC;
signal txelecidle1_ext : OUT STD_LOGIC;
signal txelecidle2_ext : OUT STD_LOGIC;
signal txelecidle3_ext : OUT STD_LOGIC
);
end component hard_ip_x4;
component Hard_IP_x1_plus is
port (
-- inputs:
signal app_int_sts : in std_logic;
signal app_msi_num : in std_logic_vector (4 downto 0);
signal app_msi_req : in std_logic;
signal app_msi_tc : in std_logic_vector (2 downto 0);
signal cpl_err : in std_logic_vector (6 downto 0);
signal cpl_pending : in std_logic;
signal fixedclk_serdes : in std_logic;
signal lmi_addr : in std_logic_vector (11 downto 0);
signal lmi_din : in std_logic_vector (31 downto 0);
signal lmi_rden : in std_logic;
signal lmi_wren : in std_logic;
signal local_rstn : in std_logic;
signal pcie_rstn : in std_logic;
signal pclk_in : in std_logic;
signal pex_msi_num : in std_logic_vector (4 downto 0);
signal phystatus_ext : in std_logic;
signal pipe_mode : in std_logic := std_logic'('0');
signal pld_clk : in std_logic;
signal pm_auxpwr : in std_logic;
signal pm_data : in std_logic_vector (9 downto 0);
signal pm_event : in std_logic;
signal pme_to_cr : in std_logic;
signal reconfig_clk : in std_logic;
signal reconfig_clk_locked : in std_logic;
signal refclk : in std_logic;
signal rx_in0 : in std_logic := std_logic'('0');
signal rx_st_mask0 : in std_logic;
signal rx_st_ready0 : in std_logic;
signal rxdata0_ext : in std_logic_vector (7 downto 0);
signal rxdatak0_ext : in std_logic;
signal rxelecidle0_ext : in std_logic;
signal rxstatus0_ext : in std_logic_vector (2 downto 0);
signal rxvalid0_ext : in std_logic;
signal test_in : in std_logic_vector (39 downto 0);
signal tx_st_data0 : in std_logic_vector (63 downto 0);
signal tx_st_eop0 : in std_logic;
signal tx_st_err0 : in std_logic;
signal tx_st_sop0 : in std_logic;
signal tx_st_valid0 : in std_logic;
-- outputs:
signal app_clk : out std_logic;
signal app_int_ack : out std_logic;
signal app_msi_ack : out std_logic;
signal clk250_out : out std_logic;
signal clk500_out : out std_logic;
signal core_clk_out : out std_logic;
signal lane_act : out std_logic_vector (3 downto 0);
signal lmi_ack : out std_logic;
signal lmi_dout : out std_logic_vector (31 downto 0);
signal ltssm : out std_logic_vector (4 downto 0);
signal pme_to_sr : out std_logic;
signal powerdown_ext : out std_logic_vector (1 downto 0);
signal rate_ext : out std_logic;
signal rc_pll_locked : out std_logic;
signal rx_st_bardec0 : out std_logic_vector (7 downto 0);
signal rx_st_be0 : out std_logic_vector (7 downto 0);
signal rx_st_data0 : out std_logic_vector (63 downto 0);
signal rx_st_eop0 : out std_logic;
signal rx_st_err0 : out std_logic;
signal rx_st_sop0 : out std_logic;
signal rx_st_valid0 : out std_logic;
signal rxpolarity0_ext : out std_logic;
signal srstn : out std_logic;
signal test_out : out std_logic_vector (8 downto 0);
signal tl_cfg_add : out std_logic_vector (3 downto 0);
signal tl_cfg_ctl : out std_logic_vector (31 downto 0);
signal tl_cfg_ctl_wr : out std_logic;
signal tl_cfg_sts : out std_logic_vector (52 downto 0);
signal tl_cfg_sts_wr : out std_logic;
signal tx_cred0 : out std_logic_vector (35 downto 0);
signal tx_fifo_empty0 : out std_logic;
signal tx_out0 : out std_logic;
signal tx_st_ready0 : out std_logic;
signal txcompl0_ext : out std_logic;
signal txdata0_ext : out std_logic_vector (7 downto 0);
signal txdatak0_ext : out std_logic;
signal txdetectrx_ext : out std_logic;
signal txelecidle0_ext : OUT STD_LOGIC
);
end component Hard_IP_x1_plus;
component altpcierd_reconfig_clk_pll is
port (
signal inclk0 : in std_logic;
signal locked : out std_logic;
signal c0 : out std_logic;
signal c1 : out std_logic
);
end component altpcierd_reconfig_clk_pll;
--component z091_01_wb_adr_dec
-- generic(
-- NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
-- );
-- port (
-- pci_cyc_i : in std_logic_vector(6 downto 0);
-- wbm_adr_o_q : in std_logic_vector(31 downto 2);
--
-- wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
-- );
--end component;
component alt_reconf
port(
reconfig_clk : in std_logic;
reconfig_fromgxb : in std_logic_vector (4 downto 0);
busy : out std_logic;
reconfig_togxb : out std_logic_vector (3 downto 0)
);
end component;
---------------------------------------
-- module to convert irq_req_i vector
-- to 16z091-01 irq behavior
---------------------------------------
component pcie_msi
generic (
WIDTH : integer range 32 downto 1
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
irq_req_i : in std_logic_vector(WIDTH -1 downto 0);
wb_int_o : out std_logic;
wb_pwr_enable_o : out std_logic;
wb_int_num_o : OUT std_logic_vector(4 downto 0);
wb_int_ack_i : in std_logic;
wb_int_num_allowed_i : in std_logic_vector(5 downto 0)
);
end component;
-------------------------------------------------------------------------------
begin
-- coverage off
assert not no_valid_device(supported_devices => SUPPORTED_DEVICES, device => FPGA_FAMILY) report "16z091-01: no valid FPGA device selected" severity failure;
-- coverage on
--wbm_cyc_o <= wbm_cyc_o_int;
npor_int <= ext_rst_n and '1';
pll_powerdown_int <= not npor_int;
--core_clk_int <= clk250_int;
ep_clk250_o <= clk250_int;
clk250_int_1delta_delay <= clk250_int;
clk250_int_2delta_delay <= clk250_int_1delta_delay;
clk250_int_3delta_delay <= clk250_int_2delta_delay;
----------------------------------
-- assign debug port if ltssm is
-- in link training mode
----------------------------------
link_train_active <= '0' when int_ltssm = "01111" else
'1';
ep_ltssm_o <= int_ltssm;
-- -------------------------------------------------
-- -- work around for Altera receiver detect issue
-- -------------------------------------------------
-- --pipe_mode_int <= '0'; -- use serial mode
-- test_in_int(39 downto 4) <= (others => '0');
-- test_in_int(3) <= not pipe_mode_int;
-- test_in_int(2 downto 1) <= (others => '0');
-- --------------------------------------------
-- -- speed up initialization for simulation:
-- --------------------------------------------
-- test_in_int(0) <= SIMULATION;
pipe_mode_int <= '1';
test_in_int(39 downto 10) <= (others => '0');
test_in_int(9) <= '1'; -- disable polling.compliance
test_in_int(8 downto 4) <= (others => '0');
test_in_int(3) <= not pipe_mode_int; -- forces all lanes to detect the receiver
test_in_int(2 downto 1) <= (others => '0');
test_in_int(0) <= '1'; -- speed up simulation by making counters faster than normal
-- instanciate components
ip_16z091_01_comp : ip_16z091_01
generic map(
FPGA_FAMILY => FPGA_FAMILY,
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
READY_LATENCY => 2,
FIFO_MAX_USEDW => conv_std_logic_vector((2**RX_LPM_WIDTHU - 8),10),
WBM_SUSPEND_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 5),10),
WBM_RESUME_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 9),10),
WBS_SUSPEND_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 4),10),
WBS_RESUME_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 9),10),
PCIE_REQUEST_LENGTH => PCIE_REQUEST_LENGTH,
RX_FIFO_DEPTH => 2**RX_LPM_WIDTHU,
RX_LPM_WIDTHU => RX_LPM_WIDTHU,
TX_HEADER_FIFO_DEPTH => 2**TX_HEADER_LPM_WIDTHU,
TX_HEADER_LPM_WIDTHU => TX_HEADER_LPM_WIDTHU,
TX_DATA_FIFO_DEPTH => 2**TX_DATA_LPM_WIDTHU,
TX_DATA_LPM_WIDTHU => TX_DATA_LPM_WIDTHU
)
port map(
clk => core_clk_int,
rst => srst_int, --rst_int,
clk_500 => clk_500,
wb_clk => wb_clk,
wb_rst => wb_rst,
-- IP Core
core_clk => core_clk_int,
rx_st_data0 => rx_st_data0_int,
rx_st_err0 => rx_st_err0_int,
rx_st_valid0 => rx_st_valid0_int,
rx_st_sop0 => rx_st_sop0_int,
rx_st_eop0 => rx_st_eop0_int,
rx_st_be0 => rx_st_be0_int,
rx_st_bardec0 => rx_st_bardec0_int,
tx_st_ready0 => tx_st_ready0_int,
tx_fifo_full0 => tx_fifo_full0_int,
tx_fifo_empty0 => tx_fifo_empty0_int,
tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
pme_to_sr => pme_to_sr_int,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
app_int_ack => app_int_ack_int,
app_msi_ack => app_msi_ack_int,
rx_st_mask0 => rx_st_mask0_int,
rx_st_ready0 => rx_st_ready0_int,
tx_st_err0 => tx_st_err0_int,
tx_st_valid0 => tx_st_valid0_int,
tx_st_sop0 => tx_st_sop0_int,
tx_st_eop0 => tx_st_eop0_int,
tx_st_data0 => tx_st_data0_int,
pme_to_cr => pme_to_cr_int,
app_int_sts => app_int_sts_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
app_msi_num => app_msi_num_int,
pex_msi_num => pex_msi_num_int,
derr_cor_ext_rcv => derr_cor_ext_rcv_int,
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
r2c_err0 => r2c_err0_int,
cpl_err => cpl_err_int,
cpl_pending => cpl_pending_int,
-- Wishbone master
wbm_ack => wbm_ack,
wbm_dat_i => wbm_dat_i,
wbm_stb => wbm_stb,
--wbm_cyc => OPEN,
wbm_cyc_o => wbm_cyc_o,
wbm_we => wbm_we,
wbm_sel => wbm_sel,
wbm_adr => wbm_adr,
wbm_dat_o => wbm_dat_o,
wbm_cti => wbm_cti,
wbm_tga => wbm_tga,
--wb_bar_dec => int_bar_hit,
-- Wishbone slave
wbs_cyc => wbs_cyc,
wbs_stb => wbs_stb,
wbs_we => wbs_we,
wbs_sel => wbs_sel,
wbs_adr => wbs_adr,
wbs_dat_i => wbs_dat_i,
wbs_cti => wbs_cti,
wbs_tga => wbs_tga,
wbs_ack => wbs_ack,
wbs_err => wbs_err,
wbs_dat_o => wbs_dat_o,
-- interrupt
wb_int => int_wb_int,
wb_pwr_enable => int_wb_pwr_enable,
wb_int_num => int_wb_int_num,
wb_int_ack => int_wb_int_ack,
wb_int_num_allowed => int_wb_int_num_allowed,
-- error
error_timeout => error_timeout,
error_cor_ext_rcv => error_cor_ext_rcv,
error_cor_ext_rpl => error_cor_ext_rpl,
error_rpl => error_rpl,
error_r2c0 => error_r2c0,
error_msi_num => error_msi_num,
-- debug port
rx_debug_out => open
);
-- gen_x4: if USE_LANES = "100" generate
-- Hard_IP_x4_comp : entity work.Hard_IP_x4
-- port map(
-- -- inputs:
-- app_int_sts => app_int_sts_int,
-- app_msi_num => app_msi_num_int,
-- app_msi_req => app_msi_req_int,
-- app_msi_tc => app_msi_tc_int,
-- busy_altgxb_reconfig => reconf_busy,
-- cal_blk_clk => clk_50,
-- cpl_err => cpl_err_int,
-- cpl_pending => cpl_pending_int,
-- crst => crst_int,
-- fixedclk_serdes => clk_125,
-- gxb_powerdown => '0',
-- hpg_ctrler => (others => '0'),
-- lmi_addr => (others => '0'),
-- lmi_din => (others => '0'),
-- lmi_rden => '0',
-- lmi_wren => '0',
-- npor => npor_int,
-- pclk_in => core_clk_int,
-- pex_msi_num => pex_msi_num_int,
-- phystatus_ext => ep_phystatus_i(0),
-- pipe_mode => pipe_mode_int,
-- pld_clk => core_clk_int,
-- pll_powerdown => pll_powerdown_int,
-- pm_auxpwr => '0',
-- pm_data => (others => '0'),
-- pm_event => '0',
-- pme_to_cr => pme_to_cr_int,
-- reconfig_clk => clk_50,
-- reconfig_togxb => reconfig_togxb_int,
-- refclk => ref_clk,
-- rx_in0 => rx_0,
-- rx_in1 => rx_1,
-- rx_in2 => rx_2,
-- rx_in3 => rx_3,
-- rx_st_mask0 => rx_st_mask0_int,
-- rx_st_ready0 => rx_st_ready0_int,
-- rxdata0_ext => ep_rxdata_i(7 downto 0),
-- rxdata1_ext => ep_rxdata_i(15 downto 8),
-- rxdata2_ext => ep_rxdata_i(23 downto 16),
-- rxdata3_ext => ep_rxdata_i(31 downto 24),
-- rxdatak0_ext => ep_rxdatak_i(0),
-- rxdatak1_ext => ep_rxdatak_i(1),
-- rxdatak2_ext => ep_rxdatak_i(2),
-- rxdatak3_ext => ep_rxdatak_i(3),
-- rxelecidle0_ext => ep_rxelecidle_i(0),
-- rxelecidle1_ext => ep_rxelecidle_i(1),
-- rxelecidle2_ext => ep_rxelecidle_i(2),
-- rxelecidle3_ext => ep_rxelecidle_i(3),
-- rxstatus0_ext => ep_rxstatus_i(2 downto 0),
-- rxstatus1_ext => ep_rxstatus_i(5 downto 3),
-- rxstatus2_ext => ep_rxstatus_i(8 downto 6),
-- rxstatus3_ext => ep_rxstatus_i(11 downto 9),
-- rxvalid0_ext => ep_rxvalid_i(0),
-- rxvalid1_ext => ep_rxvalid_i(1),
-- rxvalid2_ext => ep_rxvalid_i(2),
-- rxvalid3_ext => ep_rxvalid_i(3),
-- srst => srst_int,
-- test_in => test_in_int,
-- tx_st_data0 => tx_st_data0_int,
-- tx_st_eop0 => tx_st_eop0_int,
-- tx_st_err0 => tx_st_err0_int,
-- tx_st_sop0 => tx_st_sop0_int,
-- tx_st_valid0 => tx_st_valid0_int,
--
-- -- outputs:
-- app_int_ack => app_int_ack_int,
-- app_msi_ack => app_msi_ack_int,
-- clk250_out => ep_clk250_o,
-- clk500_out => ep_clk500_o,
-- core_clk_out => core_clk_int,
-- derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
-- derr_cor_ext_rpl => derr_cor_ext_rpl_int,
-- derr_rpl => derr_rpl_int,
-- dlup_exit => dlup_exit,
-- hotrst_exit => hotrst_exit,
-- ko_cpl_spc_vc0 => open,
-- l2_exit => l2_exit,
-- lane_act => open,
-- lmi_ack => open,
-- lmi_dout => open,
-- ltssm => int_ltssm,
-- pme_to_sr => pme_to_sr_int,
-- powerdown_ext => powerdown_int, --ep_powerdown_ext_o,
-- r2c_err0 => r2c_err0_int,
-- rate_ext => ep_rate_ext_o,
-- rc_pll_locked => open,
-- reconfig_fromgxb => reconfig_fromgxb_int,
-- reset_status => open,
-- rx_fifo_empty0 => open,
-- rx_fifo_full0 => open,
-- rx_st_bardec0 => rx_st_bardec0_int,
-- rx_st_be0 => rx_st_be0_int,
-- rx_st_data0 => rx_st_data0_int,
-- rx_st_eop0 => rx_st_eop0_int,
-- rx_st_err0 => rx_st_err0_int,
-- rx_st_sop0 => rx_st_sop0_int,
-- rx_st_valid0 => rx_st_valid0_int,
-- rxpolarity0_ext => ep_rxpolarity_o(0),
-- rxpolarity1_ext => ep_rxpolarity_o(1),
-- rxpolarity2_ext => ep_rxpolarity_o(2),
-- rxpolarity3_ext => ep_rxpolarity_o(3),
-- suc_spd_neg => open,
-- test_out => open,
-- tl_cfg_add => tl_cfg_add_int,
-- tl_cfg_ctl => tl_cfg_ctl_int,
-- tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
-- tl_cfg_sts => tl_cfg_sts_int,
-- tl_cfg_sts_wr => tl_cfg_sts_wr_int,
-- tx_cred0 => open,
-- tx_fifo_empty0 => tx_fifo_empty0_int,
-- tx_fifo_full0 => tx_fifo_full0_int,
-- tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
-- tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
-- tx_out0 => tx_0,
-- tx_out1 => tx_1,
-- tx_out2 => tx_2,
-- tx_out3 => tx_3,
-- tx_st_ready0 => tx_st_ready0_int,
-- txcompl0_ext => ep_txcompl_o(0),
-- txcompl1_ext => ep_txcompl_o(1),
-- txcompl2_ext => ep_txcompl_o(2),
-- txcompl3_ext => ep_txcompl_o(3),
-- txdata0_ext => ep_txdata_o(7 downto 0),
-- txdata1_ext => ep_txdata_o(15 downto 8),
-- txdata2_ext => ep_txdata_o(23 downto 16),
-- txdata3_ext => ep_txdata_o(31 downto 24),
-- txdatak0_ext => ep_txdatak_o(0),
-- txdatak1_ext => ep_txdatak_o(1),
-- txdatak2_ext => ep_txdatak_o(2),
-- txdatak3_ext => ep_txdatak_o(3),
-- txdetectrx_ext => txdetectrx_int, --ep_txdetectrx_o(0),
-- txelecidle0_ext => ep_txelecidle_o(0),
-- txelecidle1_ext => ep_txelecidle_o(1),
-- txelecidle2_ext => ep_txelecidle_o(2),
-- txelecidle3_ext => ep_txelecidle_o(3)
-- );
--
-----------------------------------------------------------------------
-- Hard IP has only one bit for txdetectrx and 2 bits for powerdown
-- thus map these to the other ports
-----------------------------------------------------------------------
-- ep_txdetectrx_o(0) <= txdetectrx_int;
-- ep_txdetectrx_o(1) <= txdetectrx_int;
-- ep_txdetectrx_o(2) <= txdetectrx_int;
-- ep_txdetectrx_o(3) <= txdetectrx_int;
-- ep_powerdown_ext_o(1 downto 0) <= powerdown_int;
-- ep_powerdown_ext_o(3 downto 2) <= powerdown_int;
-- ep_powerdown_ext_o(5 downto 4) <= powerdown_int;
-- ep_powerdown_ext_o(7 downto 6) <= powerdown_int;
-- end generate gen_x4;
-- gen_x2: if USE_LANES = "010" generate
-- Hard_IP_x2_comp : entity work.Hard_IP_x2
-- generic map(
-- VENDOR_ID => VENDOR_ID,
-- DEVICE_ID => DEVICE_ID,
-- REVISION_ID => REVISION_ID,
-- CLASS_CODE => CLASS_CODE,
-- SUBSYSTEM_VENDOR_ID => SUBSYSTEM_VENDOR_ID,
-- SUBSYSTEM_DEVICE_ID => SUBSYSTEM_DEVICE_ID,
--
-- IO_SPACE_BAR_0 => IO_SPACE_0, -- IO_SPACE_BAR_0,
-- PREFETCH_BAR_0 => PREFETCH_0, -- PREFETCH_BAR_0,
-- SIZE_MASK_BAR_0 => SIZE_MASK_0, -- SIZE_MASK_BAR_0,
--
-- IO_SPACE_BAR_1 => IO_SPACE_1, -- IO_SPACE_BAR_1,
-- PREFETCH_BAR_1 => PREFETCH_1, -- PREFETCH_BAR_1,
-- SIZE_MASK_BAR_1 => SIZE_MASK_1, -- SIZE_MASK_BAR_1,
--
-- IO_SPACE_BAR_2 => IO_SPACE_2, -- IO_SPACE_BAR_2,
-- PREFETCH_BAR_2 => PREFETCH_2, -- PREFETCH_BAR_2,
-- SIZE_MASK_BAR_2 => SIZE_MASK_2, -- SIZE_MASK_BAR_2,
--
-- IO_SPACE_BAR_3 => IO_SPACE_3, -- IO_SPACE_BAR_3,
-- PREFETCH_BAR_3 => PREFETCH_3, -- PREFETCH_BAR_3,
-- SIZE_MASK_BAR_3 => SIZE_MASK_3, -- SIZE_MASK_BAR_3,
--
-- IO_SPACE_BAR_4 => IO_SPACE_4, -- IO_SPACE_BAR_4,
-- PREFETCH_BAR_4 => PREFETCH_4, -- PREFETCH_BAR_4,
-- SIZE_MASK_BAR_4 => SIZE_MASK_4, -- SIZE_MASK_BAR_4,
--
-- IO_SPACE_BAR_5 => IO_SPACE_5, -- IO_SPACE_BAR_5,
-- PREFETCH_BAR_5 => PREFETCH_5, -- PREFETCH_BAR_5,
-- SIZE_MASK_BAR_5 => SIZE_MASK_5 -- SIZE_MASK_BAR_5
-- )
-- port map(
-- -- inputs:
-- app_int_sts => app_int_sts_int,
-- app_msi_num => app_msi_num_int,
-- app_msi_req => app_msi_req_int,
-- app_msi_tc => app_msi_tc_int,
-- cal_blk_clk => clk_50,
-- cpl_err => cpl_err_int,
-- cpl_pending => cpl_pending_int,
-- crst => crst_int,
-- gxb_powerdown => '0',
-- hpg_ctrler => (others => '0'),
-- lmi_addr => (others => '0'),
-- lmi_din => (others => '0'),
-- lmi_rden => '0',
-- lmi_wren => '0',
-- npor => '1', --ext_rst_n, --'0',
-- pclk_in => core_clk_int,
-- pex_msi_num => pex_msi_num_int,
-- phystatus_ext => '0',
-- pipe_mode => '0',
-- pld_clk => core_clk_int,
-- pll_powerdown => '0',
-- pm_auxpwr => '0',
-- pm_data => (others => '0'),
-- pm_event => '0',
-- pme_to_cr => pme_to_cr_int,
-- reconfig_clk => clk_50,
-- reconfig_togxb => reconfig_togxb_int,
-- refclk => ref_clk,
-- rx_in0 => rx_0,
-- rx_in1 => rx_1,
-- rx_st_mask0 => rx_st_mask0_int,
-- rx_st_ready0 => rx_st_ready0_int,
-- rxdata0_ext => (others => '0'),
-- rxdata1_ext => (others => '0'),
-- rxdatak0_ext => '0',
-- rxdatak1_ext => '0',
-- rxelecidle0_ext => '0',
-- rxelecidle1_ext => '0',
-- rxstatus0_ext => (others => '0'),
-- rxstatus1_ext => (others => '0'),
-- rxvalid0_ext => '0',
-- rxvalid1_ext => '0',
-- srst => srst_int,
-- test_in => (others => '0'),
-- tx_st_data0 => tx_st_data0_int,
-- tx_st_eop0 => tx_st_eop0_int,
-- tx_st_err0 => tx_st_err0_int,
-- tx_st_sop0 => tx_st_sop0_int,
-- tx_st_valid0 => tx_st_valid0_int,
--
-- -- outputs:
-- app_int_ack => app_int_ack_int,
-- app_msi_ack => app_msi_ack_int,
-- clk250_out => open,
-- clk500_out => open,
-- core_clk_out => core_clk_int,
-- derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
-- derr_cor_ext_rpl => derr_cor_ext_rpl_int,
-- derr_rpl => derr_rpl_int,
-- dlup_exit => open,
-- hotrst_exit => open,
-- ko_cpl_spc_vc0 => open,
-- l2_exit => open,
-- lane_act => open,
-- lmi_ack => open,
-- lmi_dout => open,
-- ltssm => open,
-- pme_to_sr => pme_to_sr_int,
-- powerdown_ext => open,
-- r2c_err0 => r2c_err0_int,
-- rate_ext => open,
-- rc_pll_locked => open,
-- reconfig_fromgxb => reconfig_fromgxb_int,
-- reset_status => open,
-- rx_fifo_empty0 => open,
-- rx_fifo_full0 => open,
-- rx_st_bardec0 => rx_st_bardec0_int,
-- rx_st_be0 => rx_st_be0_int,
-- rx_st_data0 => rx_st_data0_int,
-- rx_st_eop0 => rx_st_eop0_int,
-- rx_st_err0 => rx_st_err0_int,
-- rx_st_sop0 => rx_st_sop0_int,
-- rx_st_valid0 => rx_st_valid0_int,
-- rxpolarity0_ext => open,
-- rxpolarity1_ext => open,
-- suc_spd_neg => open,
-- test_out => open,
-- tl_cfg_add => tl_cfg_add_int,
-- tl_cfg_ctl => tl_cfg_ctl_int,
-- tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
-- tl_cfg_sts => tl_cfg_sts_int,
-- tl_cfg_sts_wr => tl_cfg_sts_wr_int,
-- tx_cred0 => open,
-- tx_fifo_empty0 => tx_fifo_empty0_int,
-- tx_fifo_full0 => tx_fifo_full0_int,
-- tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
-- tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
-- tx_out0 => tx_0,
-- tx_out1 => tx_1,
-- tx_st_ready0 => tx_st_ready0_int,
-- txcompl0_ext => open,
-- txcompl1_ext => open,
-- txdata0_ext => open,
-- txdata1_ext => open,
-- txdatak0_ext => open,
-- txdatak1_ext => open,
-- txdetectrx_ext => open,
-- txelecidle0_ext => open,
-- txelecidle1_ext => open
-- );
-- tx_2 <= '1';
-- tx_3 <= '1';
-- end generate gen_x2;
gen_x1: if USE_LANES = "001" generate
Hard_IP_x1_comp : Hard_IP_x1_plus
port map(
app_int_sts => app_int_sts_int,
app_msi_num => app_msi_num_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
--busy_altgxb_reconfig => reconf_busy,
--cal_blk_clk => clk_50,
cpl_err => cpl_err_int,
cpl_pending => cpl_pending_int,
--crst => crst_int,
fixedclk_serdes => clk_125, --fixedclk_serdes_int, --clk_125,
--gxb_powerdown => '0',
--hpg_ctrler => (others => '0'),
lmi_addr => (others => '0'),
lmi_din => (others => '0'),
lmi_rden => '0',
lmi_wren => '0',
local_rstn => '1',
--npor => npor_int,
pcie_rstn => ext_rst_n,
pclk_in => clk250_int, --clk250_int_3delta_delay, --clk250_int, --core_clk_int,
pex_msi_num => pex_msi_num_int,
phystatus_ext => ep_phystatus_i(0),
pipe_mode => pipe_mode_int,
pld_clk => core_clk_int,
--pll_powerdown => pll_powerdown_int,
pm_auxpwr => '0',
pm_data => (others => '0'),
pm_event => '0',
pme_to_cr => pme_to_cr_int,
reconfig_clk => reconfig_clk_int, --clk_50,
reconfig_clk_locked => reconfig_clk_locked_int,
--reconfig_togxb => reconfig_togxb_int,
refclk => ref_clk,
rx_in0 => rx_0,
rx_st_mask0 => rx_st_mask0_int,
rx_st_ready0 => rx_st_ready0_int,
rxdata0_ext => ep_rxdata_i(7 downto 0),
rxdatak0_ext => ep_rxdatak_i(0),
rxelecidle0_ext => ep_rxelecidle_i(0),
rxstatus0_ext => ep_rxstatus_i(2 downto 0),
rxvalid0_ext => ep_rxvalid_i(0),
--srst => srst_int,
test_in => test_in_int,
tx_st_data0 => tx_st_data0_int,
tx_st_eop0 => tx_st_eop0_int,
tx_st_err0 => tx_st_err0_int,
tx_st_sop0 => tx_st_sop0_int,
tx_st_valid0 => tx_st_valid0_int,
-- outputs:
app_clk => open,
app_int_ack => app_int_ack_int,
app_msi_ack => app_msi_ack_int,
clk250_out => clk250_int, --ep_clk250_o,
clk500_out => ep_clk500_o,
core_clk_out => core_clk_int,
--derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
--derr_cor_ext_rpl => derr_cor_ext_rpl_int,
--derr_rpl => derr_rpl_int,
--dlup_exit => dlup_exit,
--hotrst_exit => hotrst_exit,
--ko_cpl_spc_vc0 => open,
--l2_exit => l2_exit,
lane_act => open,
lmi_ack => open,
lmi_dout => open,
ltssm => int_ltssm,
pme_to_sr => pme_to_sr_int,
powerdown_ext => powerdown_int, --ep_powerdown_ext_o(1 downto 0),
--r2c_err0 => r2c_err0_int,
rate_ext => ep_rate_ext_o,
rc_pll_locked => open,
--rc_rx_digitalreset => open,
--reconfig_fromgxb => reconfig_fromgxb_int,
--reset_status => open,
--rx_fifo_empty0 => open,
--rx_fifo_full0 => open,
rx_st_bardec0 => rx_st_bardec0_int,
rx_st_be0 => rx_st_be0_int,
rx_st_data0 => rx_st_data0_int,
rx_st_eop0 => rx_st_eop0_int,
rx_st_err0 => rx_st_err0_int,
rx_st_sop0 => rx_st_sop0_int,
rx_st_valid0 => rx_st_valid0_int,
rxpolarity0_ext => ep_rxpolarity_o(0),
srstn => srstn_int,
--suc_spd_neg => open,
test_out => open,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
tx_cred0 => open,
tx_fifo_empty0 => tx_fifo_empty0_int,
--tx_fifo_full0 => tx_fifo_full0_int,
--tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
--tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
tx_out0 => tx_0,
tx_st_ready0 => tx_st_ready0_int,
txcompl0_ext => ep_txcompl_o(0),
txdata0_ext => ep_txdata_o(7 downto 0),
txdatak0_ext => ep_txdatak_o(0),
txdetectrx_ext => txdetectrx_int, --ep_txdetectrx_o(0),
txelecidle0_ext => ep_txelecidle_o(0)
);
ep_txdetectrx_o(0) <= txdetectrx_int;
ep_powerdown_ext_o(1 downto 0) <= powerdown_int;
-- manage removed signals
tx_fifo_full0_int <= '0';
tx_fifo_rdptr0_int <= (others => '0');
tx_fifo_wrptr0_int <= (others => '0');
r2c_err0_int <= '0';
derr_cor_ext_rcv_int(0) <= '0';
derr_cor_ext_rpl_int <= '0';
derr_rpl_int <= '0';
dlup_exit <= '0';
hotrst_exit <= '0';
l2_exit <= '0';
tx_1 <= '1';
tx_2 <= '1';
tx_3 <= '1';
end generate gen_x1;
reconfig_pll : altpcierd_reconfig_clk_pll
port map(
inclk0 => ref_clk,
locked => reconfig_clk_locked_int,
c0 => reconfig_clk_int,
c1 => fixedclk_serdes_int
);
--z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
-- generic map(
-- NR_OF_WB_SLAVES => NR_OF_WB_SLAVES
-- )
-- port map(
-- pci_cyc_i => int_bar_hit,
-- wbm_adr_o_q => wbm_adr_int(31 downto 2),
--
-- wbm_cyc_o => wbm_cyc_o_int
-- );
--mwawrik: this process is responsible for the problem, that the cycle is longer active than acknowledge
--cyc_o : process(wb_rst, wb_clk)
--begin
-- if wb_rst = '1' then
-- wbm_cyc_o_int_d <= (others => '0');
-- elsif wb_clk'event and wb_clk = '1' then
-- if wbm_ack = '1' then
-- wbm_cyc_o_int_d <= (others=>'0');
-- else
-- wbm_cyc_o_int_d <= wbm_cyc_o_int;
-- end if;
-- end if;
--end process cyc_o;
------------------------------------------------------------------------------
alt_reconf_comp : alt_reconf
port map(
reconfig_clk => clk_50,
reconfig_fromgxb => reconfig_fromgxb_int,
busy => reconf_busy,
reconfig_togxb => reconfig_togxb_int
);
gen_srst_crst_for_cold_warm_hot: process(rst_int,core_clk_int)
begin
if(rst_int = '1') then -- deactivate rst_cwh during ext_rst
rst_cwh <= '0';
rst_cwh_cnt <= (others => '0');
elsif(core_clk_int'event and core_clk_int = '1') then
if(l2_exit = '0' or hotrst_exit = '0' or dlup_exit = '0') then -- start reset
rst_cwh_cnt <= (others => '1');
elsif(rst_cwh_cnt > 0) then -- count condition
rst_cwh_cnt <= rst_cwh_cnt - 1;
else -- stop condition
rst_cwh_cnt <= (others => '0');
end if;
if(rst_cwh_cnt = 0) then -- reset if cnt > 0
rst_cwh <= '0';
else
rst_cwh <= '1';
end if;
end if;
end process;
---------------------------------------
-- module to convert irq_req_i vector
-- to 16z091-01 irq behavior
---------------------------------------
pcie_msi_i0 : pcie_msi
generic map(
WIDTH => IRQ_WIDTH
)
port map(
clk_i => wb_clk,
rst_i => wb_rst,
irq_req_i => irq_req_i,
wb_int_o => int_wb_int,
wb_pwr_enable_o => int_wb_pwr_enable,
wb_int_num_o => int_wb_int_num,
wb_int_ack_i => int_wb_int_ack,
wb_int_num_allowed_i => int_wb_int_num_allowed
);
-------------------------------------------------------------------------------
-- port assignement
--wbm_adr <= wbm_adr_int;
-- reset and clock logic
rst_int <= not ext_rst_n;
crst_int <= rst_int or rst_cwh;
--srst_int <= rst_int or rst_cwh;
srst_int <= not srstn_int;
-------------------------------------------------------------------------------
end architecture ip_16z091_01_top_arch;
|
gpl-3.0
|
800732944a8cf0df7abbead13695c445
| 0.478059 | 3.454246 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc576.vhd
| 4 | 2,652 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc576.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:35 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:35 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:07 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00576ent IS
END c03s04b01x00p01n01i00576ent;
ARCHITECTURE c03s04b01x00p01n01i00576arch OF c03s04b01x00p01n01i00576ent IS
type natural_file is file of natural;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : natural_file open read_mode is "iofile.18";
variable v : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3 ) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00576"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00576 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00576arch;
|
gpl-2.0
|
e22b290906c6cbabdfc294aac82fbdd7
| 0.551282 | 3.976012 | false | true | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/ram_image.vhd
| 2 | 181,522 |
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafaf2708000c4034241400ac373c343c343c373c00100010",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f000cafafafafafafafafafafafafafafafaf",
INIT_02 => X"008faf03afaf270003278f0303af2740034034278f8f8f8f8f8f8f8f8f8f8f8f",
INIT_03 => X"08000caf24008faf240008af2400080010008f240010008f24af008f000caf24",
INIT_04 => X"008f8f0008af00008f8f00080010008f240010008f24af008faf24af03af2700",
INIT_05 => X"00000000000000000000000000000000000000000000000003278f0324af0000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"aaa9a8a7a6a5a4a3a2a1bd000000880884608580bd1da50584049c1c00000000",
INIT_01 => X"aeadacabaaa9a8a7a6a5a4a3a2a10000bfb9b8b7b6b5b4b3b2b1b0afaeadacab",
INIT_02 => X"00c2c0a0bebfbd00e0bdbec0a0bebd9a601b1abdbfb9b8b7b6b5b4b3b2b1b0af",
INIT_03 => X"000000824200828202000082020000006200c302006200c302c2008200008242",
INIT_04 => X"00c3c20000824300c3820000006200c302006200c302c200c2c202c4a0bebd00",
INIT_05 => X"000000000000000000000000000000000000000000000000e0bdbec002820043",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000ff000000600000ff18001f0018001800180000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"000000f00000ff00000000e8f000ff6000700000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"00000000000010000000000000000000000000000000000000000000f000ff00",
INIT_05 => X"000000000000000000000000000000000000000000000000000000e8ff001000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"2c2824201c181410040090140059000104fd2a00f80004000000000000120003",
INIT_01 => X"3c3a34302c2824201c181410040000516c6864605c5854504c4844403c3a3430",
INIT_02 => X"001010212024d80008100c21210cf000080001706c6864605c5854504c484440",
INIT_03 => X"7f00810002000000050079000100790007001803000800180218000000810001",
INIT_04 => X"00180000a3002100000000a3000a00080200080008010800180001182114e800",
INIT_05 => X"00000000000000000000000000000000000000000000000008181421ff001218",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
mit
|
1f70394d708a3f3619fc3de8ff79cdfa
| 0.842906 | 6.881046 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/mb_lite/execute.vhd
| 3 | 10,181 |
----------------------------------------------------------------------------------------------
--
-- Input file : execute.vhd
-- Design name : execute
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The Execution Unit performs all arithmetic operations and makes
-- the branch decision. Furthermore the forwarding logic is located
-- here. Everything is computed within a single clock-cycle
--
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.core_Pkg.ALL;
USE work.std_Pkg.ALL;
ENTITY execute IS GENERIC
(
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
PORT
(
exec_o : OUT execute_out_type;
exec_i : IN execute_in_type;
ena_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END execute;
ARCHITECTURE arch OF execute IS
TYPE execute_reg_type IS RECORD
carry : std_ulogic;
flush_ex : std_ulogic;
END RECORD;
SIGNAL r, rin : execute_out_type;
SIGNAL reg, regin : execute_reg_type;
BEGIN
exec_o <= r;
execute_comb: PROCESS(exec_i,exec_i.fwd_mem,exec_i.ctrl_ex,
exec_i.ctrl_wb,exec_i.ctrl_mem,
exec_i.ctrl_mem.transfer_size,
exec_i.ctrl_mem_wb,exec_i.fwd_dec,
r,r.ctrl_mem,r.ctrl_mem.transfer_size,
r.ctrl_wb,reg)
VARIABLE v : execute_out_type;
VARIABLE v_reg : execute_reg_type;
VARIABLE alu_src_a : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
VARIABLE alu_src_b : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
VARIABLE carry : std_ulogic;
VARIABLE result : std_ulogic_vector(CFG_DMEM_WIDTH DOWNTO 0);
VARIABLE result_add : std_ulogic_vector(CFG_DMEM_WIDTH DOWNTO 0);
VARIABLE zero : std_ulogic;
VARIABLE dat_a, dat_b : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
VARIABLE sel_dat_a, sel_dat_b, sel_dat_d : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
VARIABLE mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
v := r;
sel_dat_a := select_register_data(exec_i.dat_a, exec_i.reg_a, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_a));
sel_dat_b := select_register_data(exec_i.dat_b, exec_i.reg_b, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_b));
sel_dat_d := select_register_data(exec_i.dat_d, exec_i.ctrl_wb.reg_d, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.ctrl_wb.reg_d));
IF reg.flush_ex = '1' THEN
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '0';
v.ctrl_wb.reg_write := '0';
v.ctrl_wb.reg_d := (OTHERS => '0');
ELSE
v.ctrl_mem := exec_i.ctrl_mem;
v.ctrl_wb := exec_i.ctrl_wb;
END IF;
IF exec_i.ctrl_mem_wb.mem_read = '1' THEN
mem_result := align_mem_load(exec_i.mem_result, exec_i.ctrl_mem_wb.transfer_size, exec_i.alu_result(1 DOWNTO 0));
ELSE
mem_result := exec_i.alu_result;
END IF;
IF forward_condition(r.ctrl_wb.reg_write, r.ctrl_wb.reg_d, exec_i.reg_a) = '1' THEN
-- Forward Execution Result to REG a
dat_a := r.alu_result;
ELSIF forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_a) = '1' THEN
-- Forward Memory Result to REG a
dat_a := mem_result;
ELSE
-- DEFAULT: value of REG a
dat_a := sel_dat_a;
END IF;
IF forward_condition(r.ctrl_wb.reg_write, r.ctrl_wb.reg_d, exec_i.reg_b) = '1' THEN
-- Forward (latched) Execution Result to REG b
dat_b := r.alu_result;
ELSIF forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_b) = '1' THEN
-- Forward Memory Result to REG b
dat_b := mem_result;
ELSE
-- DEFAULT: value of REG b
dat_b := sel_dat_b;
END IF;
IF forward_condition(r.ctrl_wb.reg_write, r.ctrl_wb.reg_d, exec_i.ctrl_wb.reg_d) = '1' THEN
-- Forward Execution Result to REG d
v.dat_d := align_mem_store(r.alu_result, exec_i.ctrl_mem.transfer_size);
ELSIF forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.ctrl_wb.reg_d) = '1' THEN
-- Forward Memory Result to REG d
v.dat_d := align_mem_store(mem_result, exec_i.ctrl_mem.transfer_size);
ELSE
-- DEFAULT: value of REG d
v.dat_d := align_mem_store(sel_dat_d, exec_i.ctrl_mem.transfer_size);
END IF;
-- Set the first operand of the ALU
CASE exec_i.ctrl_ex.alu_src_a IS
WHEN ALU_SRC_PC => alu_src_a := sign_extend(exec_i.program_counter, '0', 32);
WHEN ALU_SRC_NOT_REGA => alu_src_a := NOT dat_a;
WHEN ALU_SRC_ZERO => alu_src_a := (OTHERS => '0');
WHEN OTHERS => alu_src_a := dat_a;
END CASE;
-- Set the second operand of the ALU
CASE exec_i.ctrl_ex.alu_src_b IS
WHEN ALU_SRC_IMM => alu_src_b := exec_i.imm;
WHEN ALU_SRC_NOT_IMM => alu_src_b := NOT exec_i.imm;
WHEN ALU_SRC_NOT_REGB => alu_src_b := NOT dat_b;
WHEN OTHERS => alu_src_b := dat_b;
END CASE;
-- Determine value of carry in
CASE exec_i.ctrl_ex.carry IS
WHEN CARRY_ALU => carry := reg.carry;
WHEN CARRY_ONE => carry := '1';
WHEN CARRY_ARITH => carry := alu_src_a(CFG_DMEM_WIDTH - 1);
WHEN OTHERS => carry := '0';
END CASE;
result_add := add(alu_src_a, alu_src_b, carry);
CASE exec_i.ctrl_ex.alu_op IS
WHEN ALU_ADD => result := result_add;
WHEN ALU_OR => result := '0' & (alu_src_a OR alu_src_b);
WHEN ALU_AND => result := '0' & (alu_src_a AND alu_src_b);
WHEN ALU_XOR => result := '0' & (alu_src_a XOR alu_src_b);
WHEN ALU_SHIFT => result := alu_src_a(0) & carry & alu_src_a(CFG_DMEM_WIDTH - 1 DOWNTO 1);
WHEN ALU_SEXT8 => result := '0' & sign_extend(alu_src_a(7 DOWNTO 0), alu_src_a(7), 32);
WHEN ALU_SEXT16 => result := '0' & sign_extend(alu_src_a(15 DOWNTO 0), alu_src_a(15), 32);
WHEN ALU_MUL =>
IF G_USE_HW_MUL = true THEN
result := '0' & multiply(alu_src_a, alu_src_b);
ELSE
result := (OTHERS => '0');
END IF;
WHEN ALU_BS =>
IF G_USE_BARREL = true THEN
result := '0' & shift(alu_src_a, alu_src_b(4 DOWNTO 0), exec_i.imm(10), exec_i.imm(9));
ELSE
result := (OTHERS => '0');
END IF;
WHEN OTHERS =>
result := (OTHERS => '0');
REPORT "Invalid ALU operation" SEVERITY FAILURE;
END CASE;
-- Set carry register
IF exec_i.ctrl_ex.carry_keep = CARRY_KEEP THEN
v_reg.carry := reg.carry;
ELSE
v_reg.carry := result(CFG_DMEM_WIDTH);
END IF;
zero := is_zero(dat_a);
-- Overwrite branch condition
IF reg.flush_ex = '1' THEN
v.branch := '0';
ELSE
-- Determine branch condition
CASE exec_i.ctrl_ex.branch_cond IS
WHEN BNC => v.branch := '1';
WHEN BEQ => v.branch := zero;
WHEN BNE => v.branch := NOT zero;
WHEN BLT => v.branch := dat_a(CFG_DMEM_WIDTH - 1);
WHEN BLE => v.branch := dat_a(CFG_DMEM_WIDTH - 1) OR zero;
WHEN BGT => v.branch := NOT dat_a(CFG_DMEM_WIDTH - 1);
WHEN BGE => v.branch := NOT dat_a(CFG_DMEM_WIDTH - 1) OR zero;
WHEN OTHERS => v.branch := '0';
END CASE;
END IF;
-- Handle CMPU
IF ( exec_i.ctrl_ex.operation AND NOT (alu_src_a(CFG_DMEM_WIDTH - 1) XOR alu_src_b(CFG_DMEM_WIDTH - 1))) = '1' THEN
-- Set MSB
v.alu_result(CFG_DMEM_WIDTH - 1 DOWNTO 0) := (NOT result(CFG_DMEM_WIDTH - 1)) & result(CFG_DMEM_WIDTH - 2 DOWNTO 0);
ELSE
-- Use ALU result
v.alu_result := result(CFG_DMEM_WIDTH - 1 DOWNTO 0);
END IF;
v.program_counter := exec_i.program_counter;
-- Determine flush signals
v.flush_id := v.branch;
v_reg.flush_ex := v.branch AND NOT exec_i.ctrl_ex.delay;
rin <= v;
regin <= v_reg;
END PROCESS;
execute_seq: PROCESS(clk_i)
PROCEDURE proc_execute_reset IS
BEGIN
r.alu_result <= (OTHERS => '0');
r.dat_d <= (OTHERS => '0');
r.branch <= '0';
r.program_counter <= (OTHERS => '0');
r.flush_id <= '0';
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.mem_read <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_wb.reg_d <= (OTHERS => '0');
r.ctrl_wb.reg_write <= '0';
reg.carry <= '0';
reg.flush_ex <= '0';
END PROCEDURE proc_execute_reset;
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
proc_execute_reset;
ELSIF ena_i = '1' THEN
r <= rin;
reg <= regin;
END IF;
END IF;
END PROCESS;
END arch;
|
mit
|
38863ab310f296daaa567e9e65d4cd7d
| 0.508791 | 3.391406 | false | false | false | false |
tristanseifert/68komputer
|
sdr_command.vhd
| 1 | 16,774 |
--#############################################################################
--
-- LOGIC CORE: Command module
-- MODULE NAME: command()
-- COMPANY: Altera Corporation
-- www.altera.com
--
-- REVISION HISTORY:
--
-- Revision 1.1 06/06/2000 Description: Initial Release.
--
-- FUNCTIONAL DESCRIPTION:
--
-- This module is the command processor module for the SDR SDRAM controller.
--
--
-- Copyright (C) 1991-2000 Altera Corporation
--#############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sdr_command is
generic (
ASIZE : integer := 23;
DSIZE : integer := 32;
ROWSIZE : integer := 12;
COLSIZE : integer := 9;
BANKSIZE : integer := 2;
ROWSTART : integer := 9; -- Starting position of the row address within ADDR
COLSTART : integer := 0; -- Starting position of the column address within ADDR
BANKSTART : integer := 20 -- Starting position of the bank address within ADDR
);
port (
CLK : in std_logic; -- System Clock
RESET_N : in std_logic; -- System Reset
SADDR : in std_logic_vector(ASIZE-1 downto 0); -- Address
NOP : in std_logic; -- Decoded NOP command
READA : in std_logic; -- Decoded READA command
WRITEA : in std_logic; -- Decoded WRITEA command
REFRESH : in std_logic; -- Decoded REFRESH command
PRECHARGE : in std_logic; -- Decoded PRECHARGE command
LOAD_MODE : in std_logic; -- Decoded LOAD_MODE command
SC_CL : in std_logic_vector(1 downto 0); -- Programmed CAS latency
SC_RC : in std_logic_vector(1 downto 0); -- Programmed RC delay
SC_RRD : in std_logic_vector(3 downto 0); -- Programmed RRD delay
SC_PM : in std_logic; -- programmed Page Mode
SC_BL : in std_logic_vector(3 downto 0); -- Programmed burst length
REF_REQ : in std_logic; -- Hidden refresh request
REF_ACK : out std_logic; -- Refresh request acknowledge
CM_ACK : out std_logic; -- Command acknowledge
OE : out std_logic; -- OE signal for data path module
SA : out std_logic_vector(11 downto 0); -- SDRAM address
BA : out std_logic_vector(1 downto 0); -- SDRAM bank address
CS_N : out std_logic_vector(1 downto 0); -- SDRAM chip selects
CKE : out std_logic; -- SDRAM clock enable
RAS_N : out std_logic; -- SDRAM RAS
CAS_N : out std_logic; -- SDRAM CAS
WE_N : out std_logic -- SDRAM WE_N
);
end sdr_command;
architecture RTL of sdr_command is
-- signal declarations
signal do_nop : std_logic;
signal do_reada : std_logic;
signal do_writea : std_logic;
signal do_writea1 : std_logic;
signal do_refresh : std_logic;
signal do_precharge : std_logic;
signal do_load_mode : std_logic;
signal command_done : std_logic;
signal command_delay : std_logic_vector(7 downto 0);
signal rw_shift : std_logic_vector(3 downto 0);
signal do_act : std_logic;
signal rw_flag : std_logic;
signal do_rw : std_logic;
signal oe_shift : std_logic_vector(7 downto 0);
signal oe1 : std_logic;
signal oe2 : std_logic;
signal oe3 : std_logic;
signal oe4 : std_logic;
signal rp_shift : std_logic_vector(3 downto 0);
signal rp_done : std_logic;
signal rowaddr : std_logic_vector(ROWSIZE-1 downto 0);
signal coladdr : std_logic_vector(COLSIZE-1 downto 0);
signal bankaddr : std_logic_vector(BANKSIZE-1 downto 0);
signal REF_REQ_int : std_logic;
begin
rowaddr <= SADDR(ROWSTART + ROWSIZE - 1 downto ROWSTART); -- assignment of the row address bits from SADDR
coladdr <= SADDR(COLSTART + COLSIZE - 1 downto COLSTART); -- assignment of the column address bits
bankaddr <= SADDR(BANKSTART + BANKSIZE - 1 downto BANKSTART); -- assignment of the bank address bits
-- This process monitors the individual command lines and issues a command
-- to the next stage if there currently another command already running.
--
process(CLK, RESET_N)
begin
if (RESET_N = '0') then
do_nop <= '0';
do_reada <= '0';
do_writea <= '0';
do_refresh <= '0';
do_precharge <= '0';
do_load_mode <= '0';
command_done <= '0';
command_delay <= (others => '0');
rw_flag <= '0';
rp_shift <= (others => '0');
rp_done <= '0';
do_writea1 <= '0';
elsif rising_edge(CLK) then
-- Issue the appropriate command if the sdram is not currently busy
if ((REF_REQ = '1' or REFRESH = '1') and command_done = '0' and do_refresh = '0' and rp_done = '0' -- Refresh
and do_reada = '0' and do_writea = '0') then
do_refresh <= '1';
else
do_refresh <= '0';
end if;
if ((READA = '1') and (command_done = '0') and (do_reada = '0') and (rp_done = '0') and (REF_REQ = '0')) then -- READA
do_reada <= '1';
else
do_reada <= '0';
end if;
if ((WRITEA = '1') and (command_done = '0') and (do_writea = '0') and (rp_done = '0') and (REF_REQ = '0')) then -- WRITEA
do_writea <= '1';
do_writea1 <= '1';
else
do_writea <= '0';
do_writea1 <= '0';
end if;
if ((PRECHARGE = '1') and (command_done = '0') and (do_precharge = '0')) then -- PRECHARGE
do_precharge <= '1';
else
do_precharge <= '0';
end if;
if ((LOAD_MODE = '1') and (command_done = '0') and (do_load_mode = '0')) then -- LOADMODE
do_load_mode <= '1';
else
do_load_mode <= '0';
end if;
-- set command_delay shift register and command_done flag
-- The command delay shift register is a timer that is used to ensure that
-- the SDRAM devices have had sufficient time to finish the last command.
if ((do_refresh = '1') or (do_reada = '1') or (do_writea = '1') or (do_precharge = '1') or (do_load_mode = '1')) then
command_delay <= "11111111";
command_done <= '1';
rw_flag <= do_reada;
else
command_done <= command_delay(0); -- the command_delay shift operation
command_delay(6 downto 0) <= command_delay(7 downto 1);
command_delay(7) <= '0';
end if;
-- start additional timer that is used for the refresh, writea, reada commands
if (command_delay(0) = '0' and command_done = '1') then
rp_shift <= "1111";
rp_done <= '1';
else
rp_done <= rp_shift(0);
rp_shift(2 downto 0) <= rp_shift(3 downto 1);
rp_shift(3) <= '0';
end if;
end if;
end process;
-- logic that generates the OE signal for the data path module
-- For normal burst write he duration of OE is dependent on the configured burst length.
-- For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command
-- and is left on until a PRECHARGE(page burst terminate) is detected.
--
process(CLK, RESET_N)
begin
if (RESET_N = '0') then
oe_shift <= (others => '0');
oe1 <= '0';
oe2 <= '0';
oe3 <= '0';
oe4 <= '0';
OE <= '0';
elsif rising_edge(CLK) then
if (SC_PM = '0') then
if (do_writea1 = '1') then
if (SC_BL = "0001") then -- Set the shift register to the appropriate
oe_shift <= (others => '0'); -- value based on burst length.
elsif (SC_BL = "0010") then
oe_shift <= "00000001";
elsif (SC_BL = "0100") then
oe_shift <= "00000111";
elsif (SC_BL = "1000") then
oe_shift <= "01111111";
end if;
oe1 <= '1';
else
oe_shift(6 downto 0) <= oe_shift(7 downto 1); -- Do the shift operation
oe_shift(7) <= '0';
oe1 <= oe_shift(0);
oe2 <= oe1;
oe3 <= oe2;
oe4 <= oe3;
if (SC_RC = "10") then
OE <= oe3;
else
OE <= oe4;
end if;
end if;
else
if (do_writea1 = '1') then -- OE generation for page mode accesses
oe4 <= '1';
elsif (do_precharge = '1' or do_reada = '1' or do_refresh = '1') then
oe4 <= '0';
end if;
OE <= oe4;
end if;
end if;
end process;
-- This process tracks the time between the activate command and the
-- subsequent WRITEA or READA command, RC. The shift register is set using
-- the configuration register setting SC_RC. The shift register is loaded with
-- a single '1' with the position within the register dependent on SC_RC.
-- When the '1' is shifted out of the register it sets so_rw which triggers
-- a writea or reada command
--
process(CLK, RESET_N)
begin
if (RESET_N = '0') then
rw_shift <= (others => '0');
do_rw <= '0';
elsif rising_edge(CLK) then
if ((do_reada = '1') or (do_writea = '1')) then
if (SC_RC = "01") then -- Set the shift register
do_rw <= '1';
elsif (SC_RC = "10") then
rw_shift <= "0001";
elsif (SC_RC = "11") then
rw_shift <= "0010";
end if;
else
rw_shift(2 downto 0) <= rw_shift(3 downto 1); -- perform the shift operation
rw_shift(3) <= '0';
do_rw <= rw_shift(0);
end if;
end if;
end process;
-- This process generates the command acknowledge, CM_ACK, signal.
-- It also generates the acknowledge signal, REF_ACK, that acknowledges
-- a refresh request that was generated by the internal refresh timer circuit.
process(CLK, RESET_N)
begin
if (RESET_N = '0') then
CM_ACK <= '0';
REF_ACK <= '0';
elsif rising_edge(CLK) then
if (do_refresh = '1' and REF_REQ = '1') then -- Internal refresh timer refresh request
REF_ACK <= '1';
elsif ((do_refresh = '1') or (do_reada = '1') or (do_writea = '1') or (do_precharge = '1') -- externa commands
or (do_load_mode = '1')) then
CM_ACK <= '1';
else
REF_ACK <= '0';
CM_ACK <= '0';
end if;
end if;
end process;
-- This process generates the address, cs, cke, and command signals(ras,cas,wen)
--
process(CLK, RESET_N)
begin
if (RESET_N = '0') then
SA <= (others => '0');
BA <= (others => '0');
CS_N <= "01";
RAS_N <= '1';
CAS_N <= '1';
WE_N <= '1';
CKE <= '0';
elsif rising_edge(CLK) then
CKE <= '1';
-- Generate SA
if (do_writea = '1' or do_reada = '1') then -- ACTIVATE command is being issued, so present the row address
SA(ROWSIZE-1 downto 0) <= rowaddr;
else
SA(COLSIZE-1 downto 0) <= coladdr; -- else alway present column address
end if;
if ((do_rw='1') or (do_precharge='1')) then
SA(10) <= not(SC_PM); -- set SA(10) for autoprecharge read/write or for a precharge all command
end if;
-- don't set it if the controller is in page mode.
if (do_precharge='1' or do_load_mode='1') then
BA <= "00"; -- Set BA=0 if performing a precharge or load_mode command
else
BA <= bankaddr(1 downto 0); -- else set it with the appropriate address bits
end if;
if (do_refresh='1' or do_precharge='1' or do_load_mode='1') then
CS_N <= "00"; -- Select both chip selects if performing
else -- refresh, precharge(all) or load_mode
CS_N(0) <= SADDR(ASIZE-1); -- else set the chip selects based off of the
CS_N(1) <= not(SADDR(ASIZE-1)); -- msb address bit
end if;
--Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N
--depending on the issued command.
--
if (do_refresh='1') then -- Refresh: S=00, RAS=0, CAS=0, WE=1
RAS_N <= '0';
CAS_N <= '0';
WE_N <= '1';
elsif ((do_precharge='1') and ((oe4 = '1') or (rw_flag = '1'))) then -- burst terminate if write is active
RAS_N <= '1';
CAS_N <= '1';
WE_N <= '0';
elsif ((do_precharge='1')) then -- precharge
RAS_N <= '0';
CAS_N <= '1';
WE_N <= '0';
elsif (do_load_mode='1') then -- Mode Write: S=00, RAS=0, CAS=0, WE=0
RAS_N <= '0';
CAS_N <= '0';
WE_N <= '0';
elsif (do_reada = '1' or do_writea = '1') then -- Activate: S=01 or 10, RAS=0, CAS=1, WE=1
RAS_N <= '0';
CAS_N <= '1';
WE_N <= '1';
elsif (do_rw = '1') then -- Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1
RAS_N <= '1';
CAS_N <= '0';
WE_N <= rw_flag;
else
RAS_N <= '1';
CAS_N <= '1';
WE_N <= '1';
end if;
end if;
end process;
end RTL;
|
bsd-2-clause
|
f3d11b2e96433aaa10ee16edd277928a
| 0.415882 | 4.096215 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1871.vhd
| 4 | 1,955 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1871.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01871ent IS
END c07s01b00x00p08n01i01871ent;
ARCHITECTURE c07s01b00x00p08n01i01871arch OF c07s01b00x00p08n01i01871ent IS
type small_int is range 0 to 7;
function value return small_int is
variable tmp : small_int := 0;
begin
case tmp is
when 0 => tmp := 0;
when others => tmp := 1;
end case;
return c07s01b00x00p08n01i01871arch; -- architecture body name illegal here
end value;
BEGIN
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01871 - Architecture body names are not permitted as primaries in a function return expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01871arch;
|
gpl-2.0
|
7d8106df0d7d688cc76174fbb941748f
| 0.66445 | 3.774131 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd
| 4 | 1,437 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.resolve.all;
-- code from book (in text)
entity tri_state_reg is
port ( d : in resolved_byte;
q : out resolved_byte bus;
clock, out_enable : in bit );
end entity tri_state_reg;
-- end code from book
-- code from book
architecture behavioral of tri_state_reg is
begin
reg_behavior : process (d, clock, out_enable) is
variable stored_byte : byte;
begin
if clock'event and clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
end process reg_behavior;
end architecture behavioral;
-- end code from book
|
gpl-2.0
|
ab5ed6d4b8ac71b0e0dbf77fc16c6246
| 0.693111 | 3.842246 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc148.vhd
| 4 | 2,229 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc148.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p14n01i00148ent IS
END c04s03b02x02p14n01i00148ent;
ARCHITECTURE c04s03b02x02p14n01i00148arch OF c04s03b02x02p14n01i00148ent IS
FUNCTION FLOAT ( ival : in integer) return real is
VARIABLE v1 : real := 543.0;
begin
RETURN v1;
end FLOAT;
FUNCTION ROUND ( rval : in real) return integer is
VARIABLE v1 : integer := 543;
begin
RETURN v1;
end ROUND;
PROCEDURE test_bed
( in1 : in integer;
out1 : out real ) is
begin
out1 := FLOAT (in1);
end test_bed;
BEGIN
TESTING: PROCESS
VARIABLE var1 : real;
VARIABLE var2 : real := 543.2;
BEGIN
test_bed ( in1 => ROUND (var2),
out1 => var1 );
assert NOT( var1 = 543.0 )
report "***PASSED TEST: c04s03b02x02p14n01i00148"
severity NOTE;
assert ( var1 = 543.0 )
report "***FAILED TEST: c04s03b02x02p14n01i00148 - The actual part of a named element association may be in the form of a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p14n01i00148arch;
|
gpl-2.0
|
f95c5ba4985c792280f812ee94ba896c
| 0.651413 | 3.654098 | false | true | false | false |
herenvarno/dlx
|
dlx_vhd/tb/a-tbDlx.vhd
| 1 | 4,092 |
--------------------------------------------------------------------------------
-- FILE: tbDlx
-- DESC: Testbench for DLX
--
-- Author:
-- Create: 2015-05-24
-- Update: 2015-05-24
-- Status: UNTESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity tbDlx is
end tbDlx;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture tb_dlx_arch of tbDlx is
signal clk: std_logic := '0';
signal rst: std_logic := '0';
component Dlx
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
DRCW_SIZE : integer := C_CTR_DRCW_SIZE
);
port (
clk : in std_logic := '0';
rst : in std_logic := '0'; -- Active Low
en_iram: out std_logic:='1';
pc_bus : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
ir_bus : in std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
en_dram : out std_logic:='1';
addr_bus : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
di_bus : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
do_bus : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
dr_cw : out std_logic_vector(DRCW_SIZE-1 downto 0):=(others=>'0')
);
end component;
-- Instruction RAM
component InstructionRam is
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE
);
port (
rst : in std_logic;
clk : in std_logic;
en : in std_logic;
addr : in std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
iout : out std_logic_vector(ISTR_SIZE-1 downto 0)
);
end component;
-- Data RAM
component DataRam is
generic (
DRCW_SIZE : integer := C_CTR_DRCW_SIZE; -- Data RAM Control Word: R/W
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
rst : in std_logic;
clk : in std_logic;
en : in std_logic;
addr : in std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
din : in std_logic_vector(DATA_SIZE-1 downto 0);
dout : out std_logic_vector(DATA_SIZE-1 downto 0);
dr_cw : in std_logic_vector(DRCW_SIZE-1 downto 0)
);
end component;
constant ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
constant DATA_SIZE : integer := C_SYS_DATA_SIZE;
constant ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
constant DRCW_SIZE : integer := C_CTR_DRCW_SIZE;
signal ir_bus : std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
signal pc_bus : std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
signal di_bus : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal do_bus : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal addr_bus : std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
signal dr_cw : std_logic_vector(DRCW_SIZE-1 downto 0):=(others=>'0');
signal en_iram : std_logic:='1';
signal en_dram : std_logic:='1';
begin
-- DLX Processor
DLX0: Dlx
generic map(ADDR_SIZE,DATA_SIZE,ISTR_SIZE,DRCW_SIZE)
port map (clk, rst, en_iram, pc_bus, ir_bus, en_dram, addr_bus, di_bus, do_bus, dr_cw);
-- Clock generator
PCLOCK : process(clk)
begin
clk <= not(clk) after 0.5 ns;
end process;
-- Reset test
rst <= '0', '1' after 2 ns;
IR0: InstructionRam
generic map(ADDR_SIZE, ISTR_SIZE)
port map(rst, clk, en_iram, pc_bus, ir_bus);
DR0: DataRam
generic map(DRCW_SIZE, ADDR_SIZE, DATA_SIZE)
port map(rst, clk, en_dram, addr_bus, di_bus, do_bus, dr_cw);
end tb_dlx_arch;
--------------------------------------------------------------------------------
-- CONFIGURATION
--------------------------------------------------------------------------------
configuration tb_dlx_cfg of tbDlx is
for tb_dlx_arch
end for;
end tb_dlx_cfg;
|
mit
|
0a33e843d0f42ce5c33757bd5fec5ace
| 0.538856 | 3.162287 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc644.vhd
| 4 | 3,413 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc644.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:52 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:16 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:30 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00644ent IS
END c03s04b01x00p01n01i00644ent;
ARCHITECTURE c03s04b01x00p01n01i00644arch OF c03s04b01x00p01n01i00644ent IS
type four_value is ('Z','0','1','X');
subtype binary is four_value range '0' to '1';
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array(0 to size) of word;
type primary_memory_module is
record
enable : binary;
memory_number : primary_memory;
end record;
type whole_memory is array (0 to size) of primary_memory_module;
type whole_memory_file is file of whole_memory;
constant C38 : word := (others => '1');
constant C44 : primary_memory := (others => C38);
constant C45 : primary_memory_module := ('1',C44);
constant C46 : whole_memory := (others => C45);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : whole_memory_file open read_mode is "iofile.44";
variable v : whole_memory;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C46) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00644"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00644 - File reading operation (whole_memory_file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00644arch;
|
gpl-2.0
|
b61a7bc6d37e42cd72355ceac2fdf262
| 0.551421 | 3.909507 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1368.vhd
| 4 | 6,488 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1368.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01368ent IS
END c08s05b00x00p03n01i01368ent;
ARCHITECTURE c08s05b00x00p03n01i01368arch OF c08s05b00x00p03n01i01368ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
--
BEGIN
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01368"
severity NOTE;
assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01368 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01368arch;
|
gpl-2.0
|
b517b93353fa82d4bfc8b42107ee28d3
| 0.582922 | 2.957156 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2072.vhd
| 4 | 2,500 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2072.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02072ent IS
END c07s02b04x00p01n02i02072ent;
ARCHITECTURE c07s02b04x00p01n02i02072arch OF c07s02b04x00p01n02i02072ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- Local declarations.
variable DISTV : DISTANCE := 1 A;
variable TIMEV : TIME := 1 ns;
BEGIN
DISTV := DISTV + TIMEV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02072 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02072arch;
|
gpl-2.0
|
2badaf777054ff0ec21632ffc74c6234
| 0.5776 | 4.012841 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Gura/Modular/gura_modular_113.vhd
| 1 | 5,422 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_113 is
generic(
NUM_BITS : positive := 113
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_113 is
----------------------------------------------------------------------------------------------------
-- m = 113, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000001";
-- control signals
signal CASO: std_logic_vector(1 downto 0);
signal c_4, c_5,c_6,a_greater_b,a_eq_b: std_logic;
signal CA, CB : STD_LOGIC_VECTOR(7 downto 0);
signal U, A, V, B,X2, Y2, temp1, toA, toB, toU, toV: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
X2 <= x & '0';
Y2 <= y & '0';
caso <= "01" when (A(0) = '1' and B(0) = '0') or CurrentState = LOAD1 else
"10" when A(0) = '0' else
"11";
c_5 <= '0' when rst = '1' or currentState = LOAD1 else
'1';
c_6 <= '1' when CurrentState = LOAD1 else
'0';
a_greater_b <= '1' when CA > CB else
'0';
a_eq_b <= '1' when A = B else
'0';
--a_eq_b <= '1' when CA = "00000000" else
-- '0';
c_4 <= '0' when CurrentState = Load1 or temp1(0) = '0' else
'1';
celda_reg_A: entity celda_a(behave)
generic map (NUM_BITS)
port map( A, B,caso(1), caso(0), toA);
celda_reg_U: entity celda_U(behave)
generic map (NUM_BITS)
port map(U, V, caso(1), caso(0), temp1);
celda_reg_mod_P: entity mod_P(behave)
generic map (NUM_BITS)
port map(temp1, P, c_4, toU);
celda_reg_B: entity celda_B(behave)
generic map (NUM_BITS)
port map(toA,P,Y2,c_5,c_6, toB);
celda_reg_V: entity celda_v(behave)
generic map (NUM_BITS)
port map(toU,X2,c_5,c_6,toV);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= (others => '0');
U <= (others => '0');
B <= toB;
V <= toV;
CA <= "01110000" ;
CB <= "01101111" ;
x_div_y <= (others => '0');
done <= '0';
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
A <= toA;
U <= toU;
B <= toB;
V <= toV;
currentState <= Cycle;
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
elsif CASO = "10" then
A <= toA;
CA <= CA-1;
U <= toU;
elsif CASO = "01" then
B <= toB;
CB <= CB -1;
V <= toV;
elsif a_greater_b = '1' then
A <= toA;
CA <= CA-1;
U <= toU;
else
B <= toB;
CB <= CB-1;
V <= toV;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
bbc0290a8f08a0c92829c1bdea1fd274
| 0.396717 | 3.960555 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_06.vhd
| 4 | 3,229 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package counter_types is
-- code from book (in text)
subtype digit is bit_vector(3 downto 0);
-- end code from book
end package counter_types;
use work.counter_types.digit;
entity add_1 is
port ( d : in digit; y : out digit );
end entity add_1;
architecture boolean_eqn of add_1 is
begin
y(0) <= not d(0) after 4 ns;
y(1) <= (not d(1) and d(0))
or (d(1) and not d(0)) after 4 ns;
y(2) <= (not d(2) and d(1) and d(0))
or (d(2) and not (d(1) and d(0))) after 4 ns;
y(3) <= (not d(3) and d(2) and d(1) and d(0))
or (d(3) and not (d(2) and d(1) and d(0))) after 4 ns;
end architecture boolean_eqn;
use work.counter_types.digit;
entity buf4 is
port ( a : in digit; y : out digit );
end entity buf4;
architecture basic of buf4 is
begin
y(0) <= a(0) after 2 ns;
y(1) <= a(1) after 2 ns;
y(2) <= a(2) after 2 ns;
y(3) <= a(3) after 2 ns;
end architecture basic;
-- code from book
use work.counter_types.digit;
entity counter is
port ( clk, clr : in bit;
q0, q1 : out digit );
end entity counter;
--------------------------------------------------
architecture registered of counter is
component digit_register is
port ( clk, clr : in bit;
d : in digit;
q : out digit );
end component digit_register;
signal current_val0, current_val1, next_val0, next_val1 : digit;
begin
val0_reg : component digit_register
port map ( clk => clk, clr => clr, d => next_val0,
q => current_val0 );
val1_reg : component digit_register
port map ( clk => clk, clr => clr, d => next_val1,
q => current_val1 );
-- other component instances
-- . . .
-- not in book
incr0 : entity work.add_1(boolean_eqn)
port map ( d => current_val0, y => next_val0 );
incr1 : entity work.add_1(boolean_eqn)
port map ( d => current_val1, y => next_val1 );
buf0 : entity work.buf4(basic)
port map ( a => current_val0, y => q0 );
buf1 : entity work.buf4(basic)
port map ( a => current_val1, y => q1 );
-- end not in book
end architecture registered;
-- end code from book
|
gpl-2.0
|
abfbcf01dfc65e51066a940f3f533e65
| 0.580056 | 3.406118 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_03.vhd
| 4 | 2,710 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_fg_09_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 32;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
end package cpu_types;
package bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
end package bit_vector_unsigned_arithmetic;
package body bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
alias norm1 : bit_vector(1 to bv1'length) is bv1;
alias norm2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "arguments of different length" severity failure;
else
for index in norm1'reverse_range loop
result(index) := norm1(index) xor norm2(index) xor carry;
carry := ( norm1(index) and norm2(index) )
or ( carry and ( norm1(index) or norm2(index) ) );
end loop;
end if;
return result;
end function "+";
end package body bit_vector_unsigned_arithmetic;
-- code from book
package DMA_controller_types_and_utilities is
alias word is work.cpu_types.word;
alias address is work.cpu_types.address;
alias status_value is work.cpu_types.status_value;
alias "+" is work.bit_vector_unsigned_arithmetic."+"
[ bit_vector, bit_vector return bit_vector ];
-- . . .
end package DMA_controller_types_and_utilities;
-- end code from book
|
gpl-2.0
|
06e62a6d10dc7e56801d3d64abff85f7
| 0.649077 | 3.795518 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug21078/foo.vhdl
| 3 | 1,356 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity foo is
end entity;
architecture fum of foo is
signal ia: std_logic_vector(15 downto 0);
signal clock: std_logic:='0';
signal cw: unsigned(15 downto 0):=(others => '0');
begin
-- counter and cw are converted to UNSIGNED to use numeric_std "+"
CTR: process (clock)
variable counter : unsigned (15 downto 0) := x"0000";
variable op : std_logic_vector (7 downto 0);
begin
if clock'event and clock='1' then
op := std_logic_vector(cw (15 downto 8));
-- This if statement is misbehaving
if (op = x"20") then
counter := counter + cw (7 downto 0);
end if;
counter := counter + 2;
ia <= std_logic_vector(counter);
end if;
end process;
CLK: process
begin
if Now <= 200 ns then
wait for 10 ns;
clock <= not clock;
else
wait;
end if;
end process;
STIMULUS:
process (clock)
begin
if clk'event and clock = '1' then
if Now = 110 ns then
cw <= X"200F";
else
cw <= (others => '0');
end if;
end if;
end process;
end architecture;
|
gpl-2.0
|
40a6b113b22cc404a4f46d3e53b54c32
| 0.506637 | 4.023739 | false | false | false | false |
peteut/ghdl
|
libraries/ieee/math_complex-body.vhdl
| 4 | 52,423 |
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_COMPLEX)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package body is a nonnormative implementation of the
-- functionality defined in the MATH_COMPLEX package declaration.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076
-- -1993.
--
-- Notes:
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_COMPLEX.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_COMPLEX package declaration. The purpose of the
-- MATH_COMPLEX package body is to clarify such semantics and
-- provide a guideline for implementations to verify their
-- implementation of MATH_COMPLEX. Tool developers may choose to
-- implement the package body in the most efficient manner
-- available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
use WORK.MATH_REAL.all;
package body MATH_COMPLEX is
--
-- Equality and Inequality Operators for COMPLEX_POLAR
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return TRUE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return TRUE;
end if;
return FALSE;
end "=";
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return FALSE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return FALSE;
end if;
return TRUE;
end "/=";
--
-- Other Functions Start Here
--
function CMPLX(X: in REAL; Y: in REAL := 0.0 ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(X, Y);
end CMPLX;
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Check if already a principal value
if ( X > -MATH_PI and X <= MATH_PI ) then
return PRINCIPAL_VALUE'(X);
end if;
-- Get principal value
TEMP := X;
while ( TEMP <= -MATH_PI ) loop
TEMP := TEMP + MATH_2_PI;
end loop;
while (TEMP > MATH_PI ) loop
TEMP := TEMP - MATH_2_PI;
end loop;
return PRINCIPAL_VALUE'(TEMP);
end GET_PRINCIPAL_VALUE;
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.IM > 0.0 ) then
return COMPLEX_POLAR'(Z.IM, MATH_PI_OVER_2);
else
return COMPLEX_POLAR'(-Z.IM, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.RE > 0.0 ) then
return COMPLEX_POLAR'(Z.RE, 0.0);
else
return COMPLEX_POLAR'(-Z.RE, MATH_PI);
end if;
end if;
-- Get principal value for general case
TEMP := ARCTAN(Z.IM, Z.RE);
return COMPLEX_POLAR'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM),
GET_PRINCIPAL_VALUE(TEMP));
end COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns MATH_CZERO on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in POLAR_TO_COMPLEX(Z)"
severity ERROR;
return MATH_CZERO;
end if;
-- Get value for general case
return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
end POLAR_TO_COMPLEX;
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
begin
-- Get value for general case
return POSITIVE_REAL'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM));
end "ABS";
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = Z.MAG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ABS(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.MAG;
end "ABS";
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = ARCTAN(Z.IM, Z.RE)
variable ZTEMP : COMPLEX_POLAR;
begin
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
return ZTEMP.ARG;
end ARG;
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = Z.ARG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ARG(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.ARG;
end ARG;
function "-" (Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns -x -jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(-Z.RE, -Z.IM);
end "-";
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (Z.MAG, Z.ARG + MATH_PI)
-- b) Returns Z on error
variable TEMP: REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in -(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
TEMP := REAL'(Z.ARG) + MATH_PI;
return COMPLEX_POLAR'(Z.MAG, GET_PRINCIPAL_VALUE(TEMP));
end "-";
function CONJ (Z: in COMPLEX) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns x - jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(Z.RE, -Z.IM);
end CONJ;
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX conjugate (Z.MAG, -Z.ARG)
-- b) Returns Z on error
--
variable TEMP: PRINCIPAL_VALUE;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in CONJ(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
if ( Z.ARG = MATH_PI or Z.ARG = 0.0 ) then
TEMP := Z.ARG;
else
TEMP := -Z.ARG;
end if;
return COMPLEX_POLAR'(Z.MAG, TEMP);
end CONJ;
function SQRT(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable ZTEMP : COMPLEX_POLAR;
variable ZOUT : COMPLEX;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CZERO;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TMAG := SQRT(ZTEMP.MAG);
TARG := 0.5*ZTEMP.ARG;
if ( COS(TARG) > 0.0 ) then
ZOUT.RE := TMAG*COS(TARG);
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
if ( COS(TARG) < 0.0 ) then
ZOUT.RE := TMAG*COS(TARG + MATH_PI);
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end if;
if ( SIN(TARG) > 0.0 ) then
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end SQRT;
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZOUT : COMPLEX_POLAR;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SQRT(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return Z;
end if;
-- Get principal value for general case
TMAG := SQRT(Z.MAG);
TARG := 0.5*Z.ARG;
ZOUT.MAG := POSITIVE_REAL'(TMAG);
if ( COS(TARG) < 0.0 ) then
TARG := TARG + MATH_PI;
end if;
if ( (COS(TARG) = 0.0) and (SIN(TARG) < 0.0) ) then
TARG := TARG + MATH_PI;
end if;
ZOUT.ARG := GET_PRINCIPAL_VALUE(TARG);
return ZOUT;
end SQRT;
function EXP(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 0.0 ) then
if ( Z.IM = MATH_PI or Z.IM = -MATH_PI ) then
return COMPLEX'(-1.0, 0.0);
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return COMPLEX'(0.0, -1.0);
end if;
end if;
-- Get value for general case
TEMP := EXP(Z.RE);
return COMPLEX'(TEMP*COS(Z.IM), TEMP*SIN(Z.IM));
end EXP;
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZTEMP : COMPLEX;
variable temp: REAL;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in EXP(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and (Z.ARG = MATH_PI_OVER_2 or
Z.ARG = -MATH_PI_OVER_2 )) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 ) then
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get principal value for general case
ZTEMP := POLAR_TO_COMPLEX(Z);
ZOUT.MAG := POSITIVE_REAL'(EXP(ZTEMP.RE));
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZTEMP.IM);
return ZOUT;
end EXP;
function LOG(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = -1.0 ) then
return COMPLEX'(0.0, MATH_PI);
end if;
if ( Z.RE = MATH_E ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
if ( Z.RE = 0.0 ) then
if (Z.IM = 1.0) then
return COMPLEX'(0.0, MATH_PI_OVER_2);
end if;
if (Z.IM = -1.0) then
return COMPLEX'(0.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, ZTEMP.ARG);
end LOG;
function LOG2(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 2.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG2_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG2_OF_E*ZTEMP.ARG);
end LOG2;
function LOG10(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 10.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG10_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG10_OF_E*ZTEMP.ARG);
end LOG10;
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 ) then
if ( Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2);
end if;
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.MAG = MATH_E and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG);
ZTEMP.IM := Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG;
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 2.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG2_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG2_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG2;
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 10.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG10_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG10_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG10;
function LOG(Z: in COMPLEX; BASE: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMPRE : REAL;
variable TEMPIM : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = BASE ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMPRE := LOG(ZTEMP.MAG, BASE);
TEMPIM := ZTEMP.ARG/LOG(BASE);
return COMPLEX'(TEMPRE, TEMPIM);
end LOG;
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = BASE and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG, BASE);
ZTEMP.IM := Z.ARG/LOG(BASE);
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end LOG;
function SIN(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 or Z.RE = MATH_PI) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(SIN(Z.RE)*COSH(Z.IM), COS(Z.RE)*SINH(Z.IM));
end SIN;
function SIN(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SIN(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SIN(Z1.RE)*COSH(Z1.IM), COS(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end SIN;
function COS(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = MATH_PI_OVER_2 or Z.RE = -MATH_PI_OVER_2) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COS(Z.RE)*COSH(Z.IM), -SIN(Z.RE)*SINH(Z.IM));
end COS;
function COS(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COS(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COS(Z1.RE)*COSH(Z1.IM), -SIN(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end COS;
function SINH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 or Z.IM = MATH_PI ) then
return MATH_CZERO;
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return -MATH_CBASE_J;
end if;
end if;
-- Get value for general case
return COMPLEX'(SINH(Z.RE)*COS(Z.IM), COSH(Z.RE)*SIN(Z.IM));
end SINH;
function SINH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SINH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SINH(Z1.RE)*COS(Z1.IM), COSH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end SINH;
function COSH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI ) then
return -MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI_OVER_2 or Z.IM = -MATH_PI_OVER_2 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COSH(Z.RE)*COS(Z.IM), SINH(Z.RE)*SIN(Z.IM));
end COSH;
function COSH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COSH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COSH(Z1.RE)*COS(Z1.IM), SINH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end COSH;
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R.RE, L.IM + R.IM);
end "+";
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L + R.RE, R.IM);
end "+";
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R, L.IM);
end "+";
function "+" (L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + ZR.RE, ZL.IM +ZR.IM));
return ZOUT;
end "+";
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L + ZR.RE, ZR.IM));
return ZOUT;
end "+";
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + R, ZL.IM));
return ZOUT;
end "+";
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R.RE, L.IM - R.IM);
end "-";
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L - R.RE, -1.0 * R.IM);
end "-";
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R, L.IM);
end "-";
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - ZR.RE, ZL.IM -ZR.IM));
return ZOUT;
end "-";
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L - ZR.RE, -1.0*ZR.IM));
return ZOUT;
end "-";
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - R, ZL.IM));
return ZOUT;
end "-";
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R.RE - L.IM * R.IM, L.RE * R.IM + L.IM * R.RE);
end "*";
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L * R.RE, L * R.IM);
end "*";
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R, L.IM * R);
end "*";
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + R.ARG);
return ZOUT;
end "*";
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if ( L < 0.0 ) then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG + R.ARG);
return ZOUT;
end "*";
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if ( R < 0.0 ) then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG * ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + ZR.ARG);
return ZOUT;
end "*";
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'( (L.RE * R.RE + L.IM * R.IM) / TEMP,
(L.IM * R.RE - L.RE * R.IM) / TEMP);
end "/";
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
TEMP := L / TEMP;
return COMPLEX'( TEMP * R.RE, -TEMP * R.IM );
end "/";
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by 0.0"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'(L.RE / R, L.IM / R);
end "/";
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - R.ARG);
return ZOUT;
end "/";
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by 0.0"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if R < 0.0 then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG/ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - ZR.ARG);
return ZOUT;
end "/";
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_P in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if L < 0.0 then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG - R.ARG);
return ZOUT;
end "/";
end MATH_COMPLEX;
|
gpl-2.0
|
3bb036520d6650e6091c48e3b441c430
| 0.474372 | 4.138876 | false | false | false | false |
mmoraless/ecc_vhdl
|
scalar_mul_serial/binaryMethod_serial_131.vhd
| 1 | 11,970 |
----------------------------------------------------------------------------|
-- Author : Miguel Morales-Sandoval Copyrights (R) |
-- Project : " Reconfigurable ECC" |
-- Organization : INAOE, Computer Science Department |
-- Date : Originally created March, 2007. |
----------------------------------------------------------------------------|
-- / o o \ This the binary method to compute |
-- / - o o - \ scalar multiplication in affine |
-- / --- o o --- \ coordinates. It uses a module that |
-- / ---- o o ---- \ implements the ECC-ADD and ECC-DOUBLE |
-- /------ o o ----- \ at the same time. The operations are |
-- / ----- o o ----- \ performed serially. This is a 163 bit |
-- / o o o o o o \ implementation. |
-- x x x |
-- x ----- x |
-- x ------- x |
-- x --------- x |
-- x --------- x |
-- ------------- |
-- _ _ _ _ ___ ___ |
-- | || \ | | / _ \ | _ || __| |
-- | || \| || |_| ||| ||||__ |
-- | || \ | || _ |||_||||__ |
-- |_||_|\__||_| |_||___||___| |
----------------------------------------------------------------------------|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity binaryMethod is
generic(
--------------------------------------------------------------
-- para la entrada y salida
CW : positive := 29; -- 15 29 29, 23, 11, 5, 7, 5 :- bits que "faltan" para ser multiplo de 32
WORD : positive := 32; -- 32 32 32, 32, 32, 32, 32, 32 :- Numero de palabra de entrada
ITR : positive := 5; -- 4 5 6, 8, 9, 9, 13, 18 :- No. de iteraciones en la máquina de estados
--------------------------------------------------------------
-- 113 131 163, 233, 277, 283, 409, 571
-- para el squarer
--------------------------------------------------------------
-- D : positive := 10; -- 11 10 9, 76, 14, 14, 89, 12 -- el "grado mas grande" para el polinomio en el campo m + 2
-- NUM2_BITS: positive := 261; --225 261 325, 465, 553, 565, 817, 1141 -- 2*NUMBITS -1
--------------------------------------------------------------
--113 131 163, 233, 277, 283, 409, 571
-- El nivel de seguridad
NUM_BITS: positive := 131
);
port(
valid_data_in :in std_logic;
valid_data_out :out std_logic;
ack_master :in std_logic;
ack_slave :out std_logic;
data_in : in std_logic_vector(WORD-1 downto 0);
data_out : out std_logic_vector(WORD-1 downto 0);
op : in std_logic; -- 0 -> Scalar multiplication, 1 -> SUM of points
clk : in std_logic;
rst : in std_logic
);
end;
------------------------------------------------------------------
architecture behave of BinaryMethod is
------------------------------------------------------------------
-- se agregaron mas estados para controlar la carga de los
-- operadores de la multiplicación escalar o de la suma
type CurrentState_type is (END_STATE, WAIT_DATA, WAIT_MORE, SEND_MORE, SEND_DATA, MODE0, WAIT_FINISH);
signal CurrentState: CurrentState_type;
------------------------------------------------------------------
signal Q_X: std_logic_vector(NUM_BITS-1 downto 0); -- Registros para manterner las operaciones ADD y Double
signal Q_Y: std_logic_vector(NUM_BITS-1 downto 0);
signal P_X: std_logic_vector(NUM_BITS-1 downto 0);
signal P_Y: std_logic_vector(NUM_BITS-1 downto 0);
signal counter: std_logic_vector(7 downto 0); -- Counter, indicates the number of iterations (m)
------------------------------------------------------------------
signal RstADD : std_logic; -- Interface signals for the ADD-Double module
signal ADD_X : std_logic_vector(NUM_BITS-1 downto 0);
signal ADD_Y : std_logic_vector(NUM_BITS-1 downto 0);
signal DoneADD: std_logic;
signal op_ADD: std_logic;
------------------------------------------------------------------
signal internal_regk : std_logic_vector(NUM_BITS-1 downto 0); -- Register to keep the shifth value of the scalar
signal K_SHIFT : std_logic_vector(NUM_BITS-1 downto 0); -- The combinatorial shifter for the scalar
------------------------------------------------------------------
-- Estas señales se agregaron para controlar y carga y salida de
-- valores desde/hacia el modulo KP
signal B_x_in : std_logic_vector((NUM_BITS+CW)-1 downto 0); -- 1 Registros de NUM_BITS bits para el siguiente corrimiento
signal B_X_shift : std_logic_vector((NUM_BITS+CW)-1 downto 0); -- Corrimiento combinacional
signal counter_word : std_logic_vector(4 downto 0); -- Contador para la carga del dato
signal mux_input : std_logic_vector(WORD-1 downto 0); -- Contador para la carga del dato
------------------------------------------------------------------
begin
------------------------------------------------------------------
-- The ADD module
ECC_ADD: entity ECC_add_serial_131(behave)
--Generic Map (D, NUM2_BITS, NUM_BITS)
Generic Map (NUM_BITS)
Port Map(Q_X, Q_Y, P_X, P_Y, clk, RstADD, op_ADD, ADD_X, ADD_Y, DoneADD);
k_shift <= internal_regk(NUM_BITS-2 downto 0) & '0'; -- Shift the scalar every time
mux_input <= data_in when currentState = WAIT_DATA else
(others => '0');
B_x_shift <= B_x_in((NUM_BITS+CW)-WORD-1 downto 0) & mux_input;
data_out <= B_x_in(NUM_BITS+CW-1 downto NUM_BITS+CW-WORD);
------------------------------------------------------------------
-- Finite state machine that implements the LEFT-TO-RIGTH
-- binary method, ADD and DOUBLING are performed serially
------------------------------------------------------------------
SCALAR_MUL_FSM: process (CLK)
Begin -- Inferencias de 6 registros de m y m+CW bits
if CLK'event and CLK = '1' then
if Rst = '1' then -- synchronous reset
Q_X <= (others => '0'); -- registros internos
Q_Y <= (others => '0'); -- para suma y double
P_X <= (others => '0');
P_Y <= (others => '0');
B_x_in <= (others => '0');
internal_regk <= (others => '0'); -- registro de corrimiento del escalar k
RstADD <= '0'; -- Señales de control para los bloques ADD y DOUBLE
counter_word <= (others => '0'); -- contador para capturar las palabras de entrada
counter <= (others => '0'); -- contador para la multiplicación escalar
CurrentState <= WAIT_DATA; -- El estado para esperar la primera secuencia de WORDS
ack_slave <= '0';
valid_data_out <= '0'; -- Señal de salida que habilida WORDs validos a la salida
else
case CurrentState is
----------------------------------------------------
when WAIT_DATA =>
if valid_data_in = '1' then
B_X_in <= B_x_shift;
ack_slave <= '1';
if counter_word = "00101" then -- ITR
P_X <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
elsif counter_word = "01010" then -- 2*ITR
P_Y <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
elsif counter_word = "01111" then -- 3*ITR
if op = '0' then -- multiplicación escalar
internal_regk <= B_x_in(NUM_BITS-1 downto 0); -- Lo que se leyo es el escalar, comenzar a ejecutar kP
op_ADD <= '0'; --Double
RstADD <= '1';
CurrentState <= MODE0;
else
Q_x <= B_X_in(NUM_BITS-1 downto 0);
CurrentState <= WAIT_MORE;
end if;
elsif counter_word = "10100" then --4*ITR
Q_Y <= B_X_in(NUM_BITS-1 downto 0); -- Ya tenemos los dos puntos, hacemos la suma
op_ADD <= '1'; --ADD
RstADD <= '1';
CurrentState <= MODE0;
else
CurrentState <= WAIT_MORE;
end if;
end if;
----------------------------------------------------
when WAIT_MORE => -- Espera a que el host regrese subtype señal de dato valido a cero
if valid_data_in = '0' then
ack_slave <= '0';
CurrentState <= WAIT_DATA;
Counter_word <= Counter_word + "00001";
end if;
----------------------------------------------------
when MODE0 =>
RstADD <= '0'; -- Emite el pulso al Modulo de suma y espera a que termine la operacion
CurrentState <= WAIT_FINISH;
----------------------------------------------------
when WAIT_FINISH =>
if DoneADD = '1' then -- Espera hasta que la operacion ADD termina
if op = '1' then -- solo esta suma, terminar
B_x_in <= "00000000000000000000000000000" & ADD_X;
counter_word <= (others => '0');
CurrentState <= SEND_DATA;
valid_data_out <= '1';
else
Q_X <= ADD_X; -- Almacenar el resultado actual
Q_Y <= ADD_Y;
if internal_regk(NUM_BITS-1) = '1' and op_ADD = '0' then-- se comienza una nueva operacion si es qu es necesario realizar una suma
op_ADD <= '1'; -- add
RSTADD <= '1';
CurrentState <= MODE0;
else
counter <= counter + 1; -- incrementa el counter para indicar que ya se consumio un bit del escalar
if counter = "10000010" then --130 = NUM_BITS-1, if all iterations has been performed, then the operation is compleated
B_x_in <= "00000000000000000000000000000" & ADD_X;
counter_word <= (others => '0');
valid_data_out <= '1';
CurrentState <= SEND_DATA;
else -- if not all iterations have been performed, do the following
internal_regk <= k_shift; -- update the scalar shifted
op_ADD <= '0'; -- operacion double
RstADD <= '1';
CurrentState <= MODE0;
end if;
end if;
end if;
end if;
----------------------------------------------------
when SEND_DATA => -- ya hay una palabra valida a la salida, esperar a que el host la lea
--espera el ack del receptor
if ack_master = '1' then
Counter_word <= Counter_word + "00001";
valid_data_out <= '0';
CurrentState <= SEND_MORE;
end if;
----------------------------------------------------
when SEND_MORE => -- pone una palabra valida mas
if ack_master = '0' then
if counter_word = "00101" then -- ITR = 5
B_x_in <= "00000000000000000000000000000" & ADD_Y;
valid_data_out <= '1';
CurrentState <= SEND_DATA;
elsif counter_word = "01010" then -- 2*ITR = 10
CurrentState <= END_STATE;
else
B_x_in <= B_x_shift;
valid_data_out <= '1';
CurrentState <= SEND_DATA;
end if;
end if;
when END_STATE => -- do nothing, wait until the reset signal goes to '1'
valid_data_out <= '0';
----------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
e2e8f655f13f77f4a1f9c50824991f54
| 0.447368 | 3.780796 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/memory/mem_hub.vhd
| 1 | 2,948 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: MEM_HUB
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MEM_HUB is
Port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
-- Port A
EN_A : in std_logic; -- Povoleni prace s portem A
WE_A : in std_logic; -- Povoleni zapisu
ADDR_A : in std_logic_vector(7 downto 0); -- Adresa
DIN_A : in std_logic_vector(31 downto 0); -- Vstupni data
DOUT_A : out std_logic_vector(31 downto 0); -- Vystupni data
ACK_A : out std_logic; -- Potvrzeni prace s portem A
-- Port B
EN_B : in std_logic; -- Povoleni prace s portem B
WE_B : in std_logic; -- Povoleni zapisu
ADDR_B : in std_logic_vector(7 downto 0); -- Adresa
DIN_B : in std_logic_vector(31 downto 0); -- Vstupni data
DOUT_B : out std_logic_vector(31 downto 0); -- Vystupni data
ACK_B : out std_logic; -- Potvrzeni prace s portem B
-- Output port
WE : out std_logic; -- Povoleni zapisu
ADDR : out std_logic_vector(7 downto 0); -- Adresa
DIN : out std_logic_vector(31 downto 0); -- Vstupni data
DOUT : in std_logic_vector(31 downto 0) -- Vystupni data
);
end MEM_HUB;
architecture FULL of MEM_HUB is
signal sig_ack_a : std_logic;
signal sig_ack_b : std_logic;
signal last_ack_a : std_logic;
signal last_ack_b : std_logic;
begin
ctrl_mux_p : process (WE_A, WE_B, EN_A, EN_B, ADDR_A, ADDR_B, DIN_A, DIN_B)
begin
if (EN_A = '1') then
WE <= WE_A;
ADDR <= ADDR_A;
DIN <= DIN_A;
sig_ack_a <= '1';
sig_ack_b <= '0';
elsif (EN_B = '1') then
WE <= WE_B;
ADDR <= ADDR_B;
DIN <= DIN_B;
sig_ack_a <= '0';
sig_ack_b <= '1';
else
WE <= '0';
ADDR <= (others => '0');
DIN <= (others => '0');
sig_ack_a <= '0';
sig_ack_b <= '0';
end if;
end process;
ACK_A <= sig_ack_a;
ACK_B <= sig_ack_b;
DOUT_A <= DOUT;
DOUT_B <= DOUT;
ack_reg : process (CLK, RST)
begin
if (RST = '1') then
last_ack_a <= '0';
last_ack_b <= '0';
elsif (rising_edge(CLK)) then
last_ack_a <= sig_ack_a;
last_ack_b <= sig_ack_b;
end if;
end process;
end FULL;
|
mit
|
0fa576789e05c28976c766c2fe2471d0
| 0.456581 | 3.396313 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-v.vhd
| 4 | 5,491 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxtst-v.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture verifier of dlx_test is
use work.dlx_types.all;
component clock_gen is
port ( phi1, phi2 : out std_logic;
reset : out std_logic );
end component clock_gen;
component memory is
port ( phi1, phi2 : in std_logic;
a : in dlx_address;
d : inout dlx_word;
width : in dlx_mem_width;
write_enable : in std_logic;
burst : in std_logic := '0';
mem_enable : in std_logic;
ready : out std_logic );
end component memory;
component dlx is
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
a : out dlx_address;
d : inout dlx_word;
width : out dlx_mem_width;
write_enable : out std_logic;
ifetch : out std_logic;
mem_enable : out std_logic;
ready : in std_logic );
end component dlx;
signal phi1, phi2, reset : std_logic;
signal a_behav : dlx_address;
signal d_behav : dlx_word;
signal halt_behav : std_logic;
signal width_behav : dlx_mem_width;
signal write_enable_behav, mem_enable_behav, ifetch_behav : std_logic;
signal a_rtl : dlx_address;
signal d_rtl : dlx_word;
signal halt_rtl : std_logic;
signal width_rtl : dlx_mem_width;
signal write_enable_rtl, mem_enable_rtl, ifetch_rtl : std_logic;
signal ready_mem : std_logic;
begin
cg : component clock_gen
port map ( phi1 => phi1, phi2 => phi2, reset => reset );
mem : component memory
port map ( phi1 => phi1, phi2 => phi2,
a => a_behav, d => d_behav,
width => width_behav, write_enable => write_enable_behav,
burst => open,
mem_enable => mem_enable_behav, ready => ready_mem );
proc_behav : component dlx
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_behav,
a => a_behav, d => d_behav,
width => width_behav, write_enable => write_enable_behav,
ifetch => ifetch_behav,
mem_enable => mem_enable_behav, ready => ready_mem );
proc_rtl : component dlx
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_rtl,
a => a_rtl, d => d_rtl,
width => width_rtl, write_enable => write_enable_rtl,
ifetch => ifetch_rtl,
mem_enable => mem_enable_rtl, ready => ready_mem );
verification_section : block is
begin
fwd_data_from_mem_to_rtl :
d_rtl <= d_behav when mem_enable_rtl = '1'
and write_enable_rtl = '0' else
disabled_dlx_word;
monitor : process
variable write_command_behav : boolean;
variable write_command_rtl : boolean;
begin
monitor_loop : loop
-- wait for a command, valid on leading edge of phi2
wait until rising_edge(phi2)
and mem_enable_behav = '1' and mem_enable_rtl = '1';
--
-- capture the command information
write_command_behav := write_enable_behav = '1';
write_command_rtl := write_enable_rtl = '1';
assert a_behav = a_rtl
report "addresses differ";
assert write_enable_behav = write_enable_rtl
report "write enable states differ";
assert ifetch_behav = ifetch_rtl
report "instruction fetch states differ";
assert width_behav = width_rtl
report "widths differ";
if write_command_behav and write_command_rtl then
assert d_behav = d_rtl
report "write data differs";
end if;
--
-- wait for the response from memory
ready_loop : loop
wait until falling_edge(phi2);
exit monitor_loop when reset = '1';
exit ready_loop when ready_mem = '1';
end loop ready_loop;
end loop monitor_loop;
--
-- get here when reset is asserted
wait until reset = '0';
--
-- process monitor now starts again from beginning
end process monitor;
end block verification_section;
end architecture verifier;
|
gpl-2.0
|
e4d340b4b99f56cddcaa785090095be5
| 0.550173 | 4.169324 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_14.vhd
| 4 | 2,251 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_14.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_14 is
end entity ch_05_14;
----------------------------------------------------------------
architecture test of ch_05_14 is
signal PC, functional_next_PC, equivalent_next_PC : integer := 0;
begin
block_05_3_p : block is
port ( next_PC : out integer );
port map ( next_PC => functional_next_PC );
begin
-- code from book:
PC_incr : next_PC <= PC + 4 after 5 ns;
-- end of code from book
end block block_05_3_p;
----------------
block_05_3_q : block is
port ( next_PC : out integer );
port map ( next_PC => equivalent_next_PC );
begin
-- code from book:
PC_incr : process is
begin
next_PC <= PC + 4 after 5 ns;
wait on PC;
end process PC_incr;
-- end of code from book
end block block_05_3_q;
----------------
stimulus : process is
begin
for i in 1 to 10 loop
PC <= i after 20 ns;
wait for 20 ns;
end loop;
wait;
end process stimulus;
verifier :
assert functional_next_PC = equivalent_next_PC
report "Functional and equivalent models give different results";
end architecture test;
|
gpl-2.0
|
63229df4dbeda3f9e556c9901ee7f9de
| 0.565082 | 4.137868 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/pwl_functions.vhd
| 4 | 3,147 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
package pwl_functions is
function pwl_dim1_extrap ( x : in real; xdata, ydata : in real_vector )
return real;
function interpolate (x,y2,y1,x2,x1 : in real)
return real;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real;
end package pwl_functions;
package body pwl_functions is
-- code from book
function pwl_dim1_extrap ( x : in real; xdata, ydata : in real_vector )
return real is
variable xvalue, yvalue, m : real;
variable start, fin, mid: integer;
begin
if x <= xdata(0) then
yvalue := extrapolate ( x, ydata(1), ydata(0), xdata(1), xdata(0) );
return yvalue;
end if;
if x >= xdata(xdata'right) then
yvalue := extrapolate( x, ydata(ydata'right), ydata(ydata'right - 1),
xdata(xdata'right), xdata(xdata'right - 1) );
return yvalue;
end if;
start := 0;
fin := xdata'right;
while start <= fin loop
mid := (start + fin) / 2;
if xdata(mid) < x then
start := mid + 1;
else
fin := mid - 1;
end if;
end loop;
if xdata(mid) > x then
mid := mid - 1;
end if;
yvalue := interpolate( x, ydata(mid + 1), ydata(mid),
xdata(mid + 1), xdata(mid) );
return yvalue;
end function pwl_dim1_extrap;
-- end code from book
function interpolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "interpolate: x1 cannot be equal to x2"
severity error;
assert (x >= x1) and (x <= x2)
report "interpolate: x must be between x1 and x2, inclusively "
severity error;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function interpolate;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "extrapolate: x1 cannot be equal to x2"
severity error;
assert (x <= x1) or (x >= x2)
report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
severity warning;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function extrapolate;
end package body pwl_functions;
|
gpl-2.0
|
13c243c463cf436531590853270088b6
| 0.618367 | 3.596571 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_13.vhd
| 4 | 2,251 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_13.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_13 is
end entity fg_07_13;
architecture test of fg_07_13 is
-- code from book
procedure bv_lt ( bv1, bv2 : in bit_vector; result : out boolean ) is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
result := tmp1 < tmp2;
end procedure bv_lt;
-- end code from book
begin
stimulus : process is
subtype byte is bit_vector(0 to 7);
variable result : boolean;
begin
bv_lt( byte'(X"02"), byte'(X"04"), result );
assert result;
bv_lt( byte'(X"02"), byte'(X"02"), result );
assert not result;
bv_lt( byte'(X"02"), byte'(X"02"), result );
assert not result;
bv_lt( byte'(X"FC"), byte'(X"04"), result );
assert result;
bv_lt( byte'(X"04"), byte'(X"FC"), result );
assert not result;
bv_lt( byte'(X"FC"), byte'(X"FC"), result );
assert not result;
bv_lt( byte'(X"FC"), byte'(X"FE"), result );
assert result;
bv_lt( byte'(X"FE"), byte'(X"FC"), result );
assert not result;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
f46fc6e445b88ba88dddd57df2d407ff
| 0.595291 | 3.590112 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jn.vhd
| 4 | 3,781 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-jn.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
architecture join of test_bench is
use qsim.qsim_types.all;
use random.random.all;
constant num_outputs : positive := 4;
constant probabilities : probability_vector(1 to num_outputs - 1)
:= ( 0.2, 0.4, 0.1 );
signal source_arc, join_arc : arc_type;
signal fork_arc : arc_vector(1 to num_outputs);
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(1),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => source_arc,
info_detail => info_detail );
fork1 : entity qsim.fork(behavior)
generic map ( name => "fork1",
probabilities => probabilities,
seed => sample_seeds(2),
time_unit => ns,
info_file_name => "fork1.dat" )
port map ( in_arc => source_arc,
out_arc => fork_arc,
info_detail => info_detail );
join1 : entity qsim.join(behavior)
generic map ( name => "join1",
time_unit => ns,
info_file_name => "join1.dat" )
port map ( in_arc => fork_arc,
out_arc => join_arc,
info_detail => info_detail );
sink1 : entity qsim.sink(behavior)
generic map ( name => "sink1",
time_unit => ns,
info_file_name => "sink1.dat" )
port map ( in_arc => join_arc,
info_detail => info_detail );
source_monitor : process is
variable L : line;
begin
wait on source_arc;
write(L, string'("source_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, source_arc.token, ns);
writeline(output, L);
end process source_monitor;
forks : for index in 1 to num_outputs generate
constant index_string : string := integer'image(index);
begin
fork_monitor : process
variable L : line;
begin
wait on fork_arc(index);
write(L, string'("fork_monitor(" & index_string & "): at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, fork_arc(index).token, ns);
writeline(output, L);
end process fork_monitor;
end generate forks;
sink_monitor : process
variable L : line;
begin
wait on join_arc;
write(L, string'("sink_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, join_arc.token, ns);
writeline(output, L);
end process sink_monitor;
end architecture join;
|
gpl-2.0
|
fe312d02284c0ced80a2050b7310f2cf
| 0.569955 | 3.889918 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/mb_lite/core.vhd
| 3 | 4,764 |
----------------------------------------------------------------------------------------------
--
-- Input file : core.vhd
-- Design name : core
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Top level entity of the integer unit
--
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.core_Pkg.ALL;
ENTITY core IS
PORT
(
imem_adr_o : OUT std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
imem_ena_o : OUT std_ulogic;
dmem_dat_o : OUT std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dmem_adr_o : OUT std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0);
dmem_sel_o : OUT std_ulogic_vector(3 DOWNTO 0);
dmem_we_o : OUT std_ulogic;
dmem_ena_o : OUT std_ulogic;
imem_dat_i : IN std_ulogic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
dmem_dat_i : IN std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dmem_ena_i : IN std_ulogic;
int_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END core;
ARCHITECTURE arch OF core IS
SIGNAL fetch_i : fetch_in_type;
SIGNAL fetch_o : fetch_out_type;
SIGNAL decode_i : decode_in_type;
SIGNAL decode_o : decode_out_type;
SIGNAL gprf_o : gprf_out_type;
SIGNAL exec_i : execute_in_type;
SIGNAL exec_o : execute_out_type;
SIGNAL mem_i : mem_in_type;
SIGNAL mem_o : mem_out_type;
SIGNAL ena_i : std_ulogic;
BEGIN
ena_i <= dmem_ena_i;
fetch_i.hazard <= decode_o.hazard;
fetch_i.branch <= exec_o.branch;
fetch_i.branch_target <= exec_o.alu_result(CFG_IMEM_SIZE - 1 DOWNTO 0);
fetch0 : fetch PORT MAP
(
fetch_o => fetch_o,
imem_adr_o => imem_adr_o,
imem_ena_o => imem_ena_o,
fetch_i => fetch_i,
rst_i => rst_i,
ena_i => ena_i,
clk_i => clk_i
);
decode_i.program_counter <= fetch_o.program_counter;
decode_i.instruction <= imem_dat_i;
decode_i.ctrl_wb <= mem_o.ctrl_wb;
decode_i.ctrl_mem_wb <= mem_o.ctrl_mem_wb;
decode_i.mem_result <= dmem_dat_i;
decode_i.alu_result <= mem_o.alu_result;
decode_i.interrupt <= int_i;
decode_i.flush_id <= exec_o.flush_id;
decode0: decode GENERIC MAP
(
G_INTERRUPT => CFG_INTERRUPT,
G_USE_HW_MUL => CFG_USE_HW_MUL,
G_USE_BARREL => CFG_USE_BARREL,
G_DEBUG => CFG_DEBUG
)
PORT MAP
(
decode_o => decode_o,
decode_i => decode_i,
gprf_o => gprf_o,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
exec_i.fwd_dec <= decode_o.fwd_dec;
exec_i.fwd_dec_result <= decode_o.fwd_dec_result;
exec_i.dat_a <= gprf_o.dat_a_o;
exec_i.dat_b <= gprf_o.dat_b_o;
exec_i.dat_d <= gprf_o.dat_d_o;
exec_i.reg_a <= decode_o.reg_a;
exec_i.reg_b <= decode_o.reg_b;
exec_i.imm <= decode_o.imm;
exec_i.program_counter <= decode_o.program_counter;
exec_i.ctrl_wb <= decode_o.ctrl_wb;
exec_i.ctrl_mem <= decode_o.ctrl_mem;
exec_i.ctrl_ex <= decode_o.ctrl_ex;
exec_i.fwd_mem <= mem_o.ctrl_wb;
exec_i.mem_result <= dmem_dat_i;
exec_i.alu_result <= mem_o.alu_result;
exec_i.ctrl_mem_wb <= mem_o.ctrl_mem_wb;
execute0 : execute GENERIC MAP
(
G_USE_HW_MUL => CFG_USE_HW_MUL,
G_USE_BARREL => CFG_USE_BARREL
)
PORT MAP
(
exec_o => exec_o,
exec_i => exec_i,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
mem_i.alu_result <= exec_o.alu_result;
mem_i.program_counter <= exec_o.program_counter;
mem_i.branch <= exec_o.branch;
mem_i.dat_d <= exec_o.dat_d;
mem_i.ctrl_wb <= exec_o.ctrl_wb;
mem_i.ctrl_mem <= exec_o.ctrl_mem;
mem_i.mem_result <= dmem_dat_i;
mem0 : mem PORT MAP
(
mem_o => mem_o,
dmem_dat_o => dmem_dat_o,
dmem_adr_o => dmem_adr_o,
dmem_sel_o => dmem_sel_o,
dmem_we_o => dmem_we_o,
dmem_ena_o => dmem_ena_o,
mem_i => mem_i,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
END arch;
|
mit
|
c73cef03270f6eb8f734f57052b39494
| 0.493283 | 3.071567 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_07.vhd
| 4 | 2,188 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_07 is
end entity ch_03_07;
architecture test of ch_03_07 is
begin
process_03_2_b : process is
-- code from book:
subtype index_mode is integer range 0 to 3;
variable instruction_register : integer range 0 to 2**16 - 1;
-- end of code from book
variable index_value : integer;
constant accumulator_A : integer := 1;
constant accumulator_B : integer := 2;
constant index_register : integer := 3;
begin
for i in index_mode loop
instruction_register := i * 2**12;
-- code from book:
case index_mode'((instruction_register / 2**12) rem 2**2) is
when 0 =>
index_value := 0;
when 1 =>
index_value := accumulator_A;
when 2 =>
index_value := accumulator_B;
when 3 =>
index_value := index_register;
end case;
-- end of code from book
end loop;
wait;
end process process_03_2_b;
end architecture test;
|
gpl-2.0
|
cfb0f9ddac274732ec7367a9bd89ee10
| 0.553931 | 4.447154 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/sr2940/Prim.vhd
| 3 | 2,219 |
-- Types and functions for Haskell Primitives
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package \Prim\ is
subtype \Int#\ is signed(31 downto 0);
subtype \GHC.Types.Int\ is signed(31 downto 0);
subtype \GHC.Types.Bool\ is std_logic;
-- Primitive arithmetic operations
function \GHC.Prim.==#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\;
function \GHC.Prim.<#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\;
function \GHC.Prim.-#\ ( a, b : \Int#\ ) return \Int#\;
-- Data Constructor predicates: each takes a object and returns
-- a boolean (i.e., tested with VHDL's if) that indicates whether the
-- object was constructed with the given constructor
function \is_GHC.Types.False\ (a : \GHC.Types.Bool\) return boolean;
function \is_GHC.Types.True\ (a : \GHC.Types.Bool\) return boolean;
function \is_GHC.Types.I#\ (a : \GHC.Types.Int\) return boolean;
-- Data "deconstructor" procedures: split apart an algebraic data type
-- into fields
procedure \expand_GHC.Types.I#\ ( input : in \GHC.Types.Int\;
field1 : out \Int#\);
end \Prim\;
package body \Prim\ is
function \GHC.Prim.==#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\ is
begin
if a = b then
return '1';
else
return '0';
end if;
end \GHC.Prim.==#\;
function \GHC.Prim.<#\ ( a, b : \Int#\ ) return \GHC.Types.Bool\ is
begin
if a < b then
return '1';
else
return '0';
end if;
end \GHC.Prim.<#\;
function \GHC.Prim.-#\ ( a, b : \Int#\ ) return \Int#\ is
begin
return a - b;
end \GHC.Prim.-#\;
function \is_GHC.Types.False\ (a : \GHC.Types.Bool\) return boolean is
begin
return a = '0';
end \is_GHC.Types.False\;
function \is_GHC.Types.True\ (a : \GHC.Types.Bool\) return boolean is
begin
return a = '1';
end \is_GHC.Types.True\;
function \is_GHC.Types.I#\ (a : \GHC.Types.Int\) return boolean is
begin
return true; -- Trivial: there's only one constructor
end \is_GHC.Types.I#\;
procedure \expand_GHC.Types.I#\ (
input : in \GHC.Types.Int\;
field1 : out \Int#\) is
begin
field1 := input;
end \expand_GHC.Types.I#\;
end \Prim\;
|
gpl-2.0
|
f9d01a9e2b070a013e4eb6c2fe3a3bb8
| 0.607481 | 3.156472 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3182.vhd
| 4 | 2,302 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3182.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p116n01i03182ent IS
END c14s01b00x00p116n01i03182ent;
ARCHITECTURE c14s01b00x00p116n01i03182arch OF c14s01b00x00p116n01i03182ent IS
constant C : INTEGER := 1;
--
type t2 is array(c to c + c, 1 to 10) of integer;
-- transitive cases
type t3 is array(t2'range(1), t2'reverse_range(2)) of integer;
-- 'Range (of two-dimensional array type)
type rt311 is range t3'range(1);
type rt312 is range t3'range(2);
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( rt311'LEFT = rt311(c) and
rt311'RIGHT= rt311(c+c) and
rt312'LEFT = rt312(10) and
rt312'RIGHT= rt312(1) )
report "***PASSED TEST: c14s01b00x00p116n01i03182"
severity NOTE;
assert ( rt311'LEFT = rt311(c) and
rt311'RIGHT= rt311(c+c) and
rt312'LEFT = rt312(10) and
rt312'RIGHT= rt312(1) )
report "***FAILED TEST: c14s01b00x00p116n01i03182 - Predefined attribute range test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p116n01i03182arch;
|
gpl-2.0
|
9b59e02efc2b6112de19f54b0b32b7b5
| 0.637272 | 3.487879 | false | true | false | false |
123gmax/Digital-Lab
|
AES128/Architecture1_Pipeline/decryptionLoopCore_V1.vhd
| 1 | 7,667 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 02:47:07 PM
-- Design Name:
-- Module Name: decryptionLoopCore_V1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decryptionLoopCore_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
memorySourceSelector : in STD_LOGIC;
keySelector : in STD_LOGIC_VECTOR (1 downto 0);
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end decryptionLoopCore_V1;
architecture Behavioral of decryptionLoopCore_V1 is
component addRoundKey is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
keyIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component memoryUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SELB : in STD_LOGIC;
wordAIn : in STD_LOGIC_VECTOR (31 downto 0);
wordBin : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component invShiftRows is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
blockIn : in STD_LOGIC_VECTOR (127 downto 0);
blockOut : out STD_LOGIC_VECTOR (127 downto 0));
end component;
component invSubByte is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component invMixColumn is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal mu0_Out, mu1_Out, mu2_Out, mu3_Out, mu4_Out, mu5_Out : STD_LOGIC_VECTOR(31 downto 0);
signal invSubBytes_In, invSubBytes_Out, addRoundKey_KeyIn, addRoundKey_Out : STD_LOGIC_VECTOR(31 downto 0);
signal invShiftRows_In, invShiftRows_Out : STD_LOGIC_VECTOR(127 downto 0);
signal ZERO_BIT : STD_LOGIC := '0';
signal ZERO_WORD : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
ZERO_BIT <= '0';
ZERO_WORD <= (others => '0');
mu0: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO_BIT,
wordAIn => WORD_IN,
wordBIn => ZERO_WORD,
wordOut => mu0_Out);
mu1: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO_BIT,
wordAIn => mu0_Out,
wordBIn => ZERO_WORD,
wordOut => mu1_Out);
mu2: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO_BIT,
wordAIn => mu1_Out,
wordBIn => ZERO_WORD,
wordOut => mu2_Out);
invShiftRows_In <= mu2_Out & mu1_Out & mu0_Out & WORD_IN;
invShiftRows0: invShiftRows port map( CLK => CLK,
RESET => RESET,
blockIn => invShiftRows_In,
blockOut => invShiftRows_Out);
mu3: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => memorySourceSelector,
wordAIn => invShiftRows_Out(31 downto 0),
wordBIn => invShiftRows_Out(31 downto 0),
wordOut => mu3_Out);
mu4: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => memorySourceSelector,
wordAIn => mu3_Out,
wordBIn => invShiftRows_Out(63 downto 32),
wordOut => mu4_Out);
mu5: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => memorySourceSelector,
wordAIn => mu4_Out,
wordBIn => invShiftRows_Out(95 downto 64),
wordOut => mu5_Out);
invSubBytes_In <= invShiftRows_Out(127 downto 96) when (memorySourceSelector = '1')
else mu5_Out;
invSubBytes0: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(7 downto 0),
byteOut => invSubBytes_Out(7 downto 0));
invSubBytes1: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(15 downto 8),
byteOut => invSubBytes_Out(15 downto 8));
invSubBytes2: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(23 downto 16),
byteOut => invSubBytes_Out(23 downto 16));
invSubBytes3: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => invSubBytes_In(31 downto 24),
byteOut => invSubBytes_Out(31 downto 24));
addRoundKeySelector: process(cipherKey, keySelector)
begin
case keySelector is
when "11" => addRoundKey_KeyIn <= cipherKey(127 downto 96);
when "10" => addRoundKey_KeyIn <= cipherKey(95 downto 64);
when "01" => addRoundKey_KeyIn <= cipherKey(63 downto 32);
when "00" => addRoundKey_KeyIn <= cipherKey(31 downto 0);
when others => addRoundKey_KeyIn <= (others => '0');
end case;
end process;
addRoundKey0: addRoundKey port map( CLK => CLK,
RESET => RESET,
wordIn => invSubBytes_Out,
keyIn => addRoundKey_KeyIn,
wordOut => addRoundKey_Out);
invMixColumn0: invMixColumn port map( CLK => CLK,
RESET => RESET,
wordIn => addRoundKey_Out,
wordOut => WORD_OUT);
end Behavioral;
|
gpl-2.0
|
ff11cc9136eb00b32fd5190237955224
| 0.429764 | 5.480343 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_08.vhd
| 4 | 1,886 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_08.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_08 is
end entity fg_07_08;
architecture test of fg_07_08 is
subtype word32 is bit_vector(31 downto 0);
-- code in book
procedure negate ( a : inout word32 ) is
variable carry_in : bit := '1';
variable carry_out : bit;
begin
a := not a;
for index in a'reverse_range loop
carry_out := a(index) and carry_in;
a(index) := a(index) xor carry_in;
carry_in := carry_out;
end loop;
end procedure negate;
-- end code in book
begin
stimulus : process is
-- code in book (in text)
variable op1 : word32;
-- . . .
-- end code in book
begin
op1 := X"0000_0002";
-- code in book (in text)
negate ( op1 );
-- end code in book
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
22ee175745f8a1fab6d6617844e3f1da
| 0.585366 | 4.004246 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3048.vhd
| 4 | 2,233 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3048.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03048ent IS
END c12s02b04x00p03n01i03048ent;
ARCHITECTURE c12s02b04x00p03n01i03048arch OF c12s02b04x00p03n01i03048ent IS
signal si:integer := 14;
signal sr:real := 1.4;
signal sb:bit := '0';
BEGIN
-- test for first port associated
bl2: block
port (i:integer:=4;r:real:=6.4;b:bit:='1');
port map (i=>si);
begin
assert (r=6.4)
report "Default expression for unassociated real port R incorrect"
severity failure;
assert (b='1')
report "Default expression for unassociated bit port B incorrect"
severity failure;
TESTING: PROCESS
BEGIN
assert NOT( i=14 and r=6.4 and b='1' )
report "***PASSED TEST: c12s02b04x00p03n01i03048"
severity NOTE;
assert ( i=14 and r=6.4 and b='1' )
report "***FAILED TEST: c12s02b04x00p03n01i03048 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b04x00p03n01i03048arch;
|
gpl-2.0
|
a1c755bcfe021855640fac34fd2cb191
| 0.656516 | 3.654664 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd
| 4 | 1,363 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity analog_switch is
port ( terminal n1, n2 : electrical;
signal control : in std_ulogic );
end entity analog_switch;
----------------------------------------------------------------
architecture ideal of analog_switch is
quantity v across i through n1 to n2;
begin
if control = '1' or control = 'H' use
v == 0.0;
else
i == 0.0;
end use;
break on control;
end architecture ideal;
|
gpl-2.0
|
f5f0725fc87a41b076a053015ede362a
| 0.666911 | 4.180982 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/perf02/sub_147.vhd
| 3 | 1,745 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_147 is
port (
output : out std_logic_vector(63 downto 0);
sign : in std_logic;
ge : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end sub_147;
architecture augh of sub_147 is
signal carry_inA : std_logic_vector(65 downto 0);
signal carry_inB : std_logic_vector(65 downto 0);
signal carry_res : std_logic_vector(65 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(64 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(63) & in_b(63) & carry_res(64);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "001" or msb_abr = "111") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011" or msb_abr = "111") else
'0';
ge <= tmp_ge;
end architecture;
|
gpl-2.0
|
0f45ce02c1ed8e742620298c2ea25c30
| 0.623496 | 2.573746 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_05.vhd
| 4 | 2,951 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_18_05_a is
end entity fg_18_05_a;
architecture writer of fg_18_05_a is
begin
process is
type integer_file is file of integer;
file data_file : integer_file open write_mode is "coeff-data";
begin
write(data_file, 0);
write(data_file, 1);
write(data_file, 2);
write(data_file, 3);
write(data_file, 4);
write(data_file, 5);
write(data_file, 6);
write(data_file, 7);
write(data_file, 8);
write(data_file, 9);
write(data_file, 10);
write(data_file, 11);
write(data_file, 12);
write(data_file, 13);
write(data_file, 14);
write(data_file, 15);
write(data_file, 16);
write(data_file, 17);
write(data_file, 18);
wait;
end process;
end architecture writer;
entity fg_18_05 is
end entity fg_18_05;
architecture test of fg_18_05 is
begin
process is
-- code from book (in text)
type integer_vector is array (integer range <>) of integer;
-- end code from book
-- code from book (Figure 18-5)
impure function read_array ( file_name : string; array_length : natural )
return integer_vector is
type integer_file is file of integer;
file data_file : integer_file open read_mode is file_name;
variable result : integer_vector(1 to array_length) := (others => 0);
variable index : integer := 1;
begin
while not endfile(data_file) and index <= array_length loop
read(data_file, result(index));
index := index + 1;
end loop;
return result;
end function read_array;
-- end code from book
-- code from book (in text)
constant coeffs : integer_vector := read_array("coeff-data", 16);
-- end code from book
begin
wait;
end process;
end architecture test;
|
gpl-2.0
|
1047934c7219a5922193b10c8f1db5e1
| 0.593019 | 3.908609 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1946.vhd
| 4 | 16,412 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1946.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01946pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- -----------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01946pkg.all;
ENTITY c07s02b01x00p01n02i01946ent IS
END c07s02b01x00p01n02i01946ent;
ARCHITECTURE c07s02b01x00p01n02i01946arch OF c07s02b01x00p01n02i01946ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT OR_C_csa1_1 : t_csa1_1 := ( '1', '1', '1', '0' );
CONSTANT OR_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '1', '0' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT OR_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, TRUE, FALSE );
CONSTANT OR_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, TRUE, FALSE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT OR_C_csa1_3 : t_csa1_3 := ( '1', '1', '1', '0' );
CONSTANT OR_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '1', '0' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT OR_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, TRUE, FALSE );
CONSTANT OR_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, TRUE, FALSE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL OR_S_csa1_1 : t_csa1_1 := ( '1', '1', '1', '0' );
SIGNAL OR_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '1', '0' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL OR_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, TRUE, FALSE );
SIGNAL OR_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, TRUE, FALSE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL OR_S_csa1_3 : t_csa1_3 := ( '1', '1', '1', '0' );
SIGNAL OR_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '1', '0' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL OR_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, TRUE, FALSE );
SIGNAL OR_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, TRUE, FALSE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE OR_V_csa1_1 : t_csa1_1 := ( '1', '1', '1', '0' );
VARIABLE OR_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '1', '0' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE OR_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, TRUE, FALSE );
VARIABLE OR_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, TRUE, FALSE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE OR_V_csa1_3 : t_csa1_3 := ( '1', '1', '1', '0' );
VARIABLE OR_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '1', '0' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE OR_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, TRUE, FALSE );
VARIABLE OR_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, TRUE, FALSE );
BEGIN
--
-- Test OR operator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 OR ARGB_C_csa1_1 ) = OR_C_csa1_1
REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 OR ARGB_C_csa1_2 ) = OR_C_csa1_2
REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 OR ARGB_C_csa1_3 ) = OR_C_csa1_3
REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 OR ARGB_C_csa1_4 ) = OR_C_csa1_4
REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 OR ARGB_C_usa1_1 ) = OR_C_usa1_1
REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 OR ARGB_C_usa1_2 ) = OR_C_usa1_2
REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 OR ARGB_C_usa1_3 ) = OR_C_usa1_3
REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 OR ARGB_C_usa1_4 ) = OR_C_usa1_4
REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test OR operator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 OR ARGB_S_csa1_1 ) = OR_S_csa1_1
REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 OR ARGB_S_csa1_2 ) = OR_S_csa1_2
REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 OR ARGB_S_csa1_3 ) = OR_S_csa1_3
REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 OR ARGB_S_csa1_4 ) = OR_S_csa1_4
REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 OR ARGB_S_usa1_1 ) = OR_S_usa1_1
REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 OR ARGB_S_usa1_2 ) = OR_S_usa1_2
REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 OR ARGB_S_usa1_3 ) = OR_S_usa1_3
REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 OR ARGB_S_usa1_4 ) = OR_S_usa1_4
REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test OR operator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 OR ARGB_V_csa1_1 ) = OR_V_csa1_1
REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 OR ARGB_V_csa1_2 ) = OR_V_csa1_2
REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 OR ARGB_V_csa1_3 ) = OR_V_csa1_3
REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 OR ARGB_V_csa1_4 ) = OR_V_csa1_4
REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 OR ARGB_V_usa1_1 ) = OR_V_usa1_1
REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 OR ARGB_V_usa1_2 ) = OR_V_usa1_2
REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 OR ARGB_V_usa1_3 ) = OR_V_usa1_3
REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 OR ARGB_V_usa1_4 ) = OR_V_usa1_4
REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 OR ARGB_C_csa1_1 ) = OR_C_csa1_1 and
( ARGA_C_csa1_2 OR ARGB_C_csa1_2 ) = OR_C_csa1_2 and
( ARGA_C_csa1_3 OR ARGB_C_csa1_3 ) = OR_C_csa1_3 and
( ARGA_C_csa1_4 OR ARGB_C_csa1_4 ) = OR_C_csa1_4 and
( ARGA_C_usa1_1 OR ARGB_C_usa1_1 ) = OR_C_usa1_1 and
( ARGA_C_usa1_2 OR ARGB_C_usa1_2 ) = OR_C_usa1_2 and
( ARGA_C_usa1_3 OR ARGB_C_usa1_3 ) = OR_C_usa1_3 and
( ARGA_C_usa1_4 OR ARGB_C_usa1_4 ) = OR_C_usa1_4 and
( ARGA_S_csa1_1 OR ARGB_S_csa1_1 ) = OR_S_csa1_1 and
( ARGA_S_csa1_2 OR ARGB_S_csa1_2 ) = OR_S_csa1_2 and
( ARGA_S_csa1_3 OR ARGB_S_csa1_3 ) = OR_S_csa1_3 and
( ARGA_S_csa1_4 OR ARGB_S_csa1_4 ) = OR_S_csa1_4 and
( ARGA_S_usa1_1 OR ARGB_S_usa1_1 ) = OR_S_usa1_1 and
( ARGA_S_usa1_2 OR ARGB_S_usa1_2 ) = OR_S_usa1_2 and
( ARGA_S_usa1_3 OR ARGB_S_usa1_3 ) = OR_S_usa1_3 and
( ARGA_S_usa1_4 OR ARGB_S_usa1_4 ) = OR_S_usa1_4 and
( ARGA_V_csa1_1 OR ARGB_V_csa1_1 ) = OR_V_csa1_1 and
( ARGA_V_csa1_2 OR ARGB_V_csa1_2 ) = OR_V_csa1_2 and
( ARGA_V_csa1_3 OR ARGB_V_csa1_3 ) = OR_V_csa1_3 and
( ARGA_V_csa1_4 OR ARGB_V_csa1_4 ) = OR_V_csa1_4 and
( ARGA_V_usa1_1 OR ARGB_V_usa1_1 ) = OR_V_usa1_1 and
( ARGA_V_usa1_2 OR ARGB_V_usa1_2 ) = OR_V_usa1_2 and
( ARGA_V_usa1_3 OR ARGB_V_usa1_3 ) = OR_V_usa1_3 and
( ARGA_V_usa1_4 OR ARGB_V_usa1_4 ) = OR_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01946"
severity NOTE;
assert ( ( ARGA_C_csa1_1 OR ARGB_C_csa1_1 ) = OR_C_csa1_1 and
( ARGA_C_csa1_2 OR ARGB_C_csa1_2 ) = OR_C_csa1_2 and
( ARGA_C_csa1_3 OR ARGB_C_csa1_3 ) = OR_C_csa1_3 and
( ARGA_C_csa1_4 OR ARGB_C_csa1_4 ) = OR_C_csa1_4 and
( ARGA_C_usa1_1 OR ARGB_C_usa1_1 ) = OR_C_usa1_1 and
( ARGA_C_usa1_2 OR ARGB_C_usa1_2 ) = OR_C_usa1_2 and
( ARGA_C_usa1_3 OR ARGB_C_usa1_3 ) = OR_C_usa1_3 and
( ARGA_C_usa1_4 OR ARGB_C_usa1_4 ) = OR_C_usa1_4 and
( ARGA_S_csa1_1 OR ARGB_S_csa1_1 ) = OR_S_csa1_1 and
( ARGA_S_csa1_2 OR ARGB_S_csa1_2 ) = OR_S_csa1_2 and
( ARGA_S_csa1_3 OR ARGB_S_csa1_3 ) = OR_S_csa1_3 and
( ARGA_S_csa1_4 OR ARGB_S_csa1_4 ) = OR_S_csa1_4 and
( ARGA_S_usa1_1 OR ARGB_S_usa1_1 ) = OR_S_usa1_1 and
( ARGA_S_usa1_2 OR ARGB_S_usa1_2 ) = OR_S_usa1_2 and
( ARGA_S_usa1_3 OR ARGB_S_usa1_3 ) = OR_S_usa1_3 and
( ARGA_S_usa1_4 OR ARGB_S_usa1_4 ) = OR_S_usa1_4 and
( ARGA_V_csa1_1 OR ARGB_V_csa1_1 ) = OR_V_csa1_1 and
( ARGA_V_csa1_2 OR ARGB_V_csa1_2 ) = OR_V_csa1_2 and
( ARGA_V_csa1_3 OR ARGB_V_csa1_3 ) = OR_V_csa1_3 and
( ARGA_V_csa1_4 OR ARGB_V_csa1_4 ) = OR_V_csa1_4 and
( ARGA_V_usa1_1 OR ARGB_V_usa1_1 ) = OR_V_usa1_1 and
( ARGA_V_usa1_2 OR ARGB_V_usa1_2 ) = OR_V_usa1_2 and
( ARGA_V_usa1_3 OR ARGB_V_usa1_3 ) = OR_V_usa1_3 and
( ARGA_V_usa1_4 OR ARGB_V_usa1_4 ) = OR_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01946 - Logical operator OR for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01946arch;
|
gpl-2.0
|
54c5e160cfb630863bc08ee0b3d6b147
| 0.537412 | 2.580097 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1359.vhd
| 4 | 6,568 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1359.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01359ent IS
END c08s05b00x00p03n01i01359ent;
ARCHITECTURE c08s05b00x00p03n01i01359arch OF c08s05b00x00p03n01i01359ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_rec3 : st_rec3 := c_st_rec3_1 ;
--
BEGIN
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01359"
severity NOTE;
assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01359 - Target of a variable assignment is not a variable."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01359arch;
|
gpl-2.0
|
f667b87439425a7e19a6ba000ea6dd39
| 0.582826 | 2.921708 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_10.vhd
| 4 | 2,002 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_08_10 is
end entity fg_08_10;
architecture test of fg_08_10 is
-- code from book
function "<" ( a, b : bit_vector ) return boolean is
variable tmp1 : bit_vector(a'range) := a;
variable tmp2 : bit_vector(b'range) := b;
begin
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
return std.standard."<" ( tmp1, tmp2 );
end function "<";
-- end code from book
signal a, b : bit_vector(7 downto 0);
signal result : boolean;
begin
dut : result <= a < b;
stimulus : process is
begin
wait for 10 ns;
a <= X"02"; b <= X"04"; wait for 10 ns;
a <= X"02"; b <= X"02"; wait for 10 ns;
a <= X"02"; b <= X"01"; wait for 10 ns;
a <= X"02"; b <= X"FE"; wait for 10 ns;
a <= X"FE"; b <= X"02"; wait for 10 ns;
a <= X"FE"; b <= X"FE"; wait for 10 ns;
a <= X"FE"; b <= X"FC"; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
df168ed7a22751d2c9ece1a9d9744d3a
| 0.587912 | 3.387479 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1369.vhd
| 4 | 6,565 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1369.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01369ent IS
END c08s05b00x00p03n01i01369ent;
ARCHITECTURE c08s05b00x00p03n01i01369arch OF c08s05b00x00p03n01i01369ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
--
BEGIN
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01369"
severity NOTE;
assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01369 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01369arch;
|
gpl-2.0
|
298cbac47028c8568eb42bfb0a870469
| 0.583549 | 2.934734 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_08.vhd
| 4 | 1,531 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_fg_01_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behav of reg4 is
begin
storage : process is
variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
begin
if en = '1' and clk = '1' then
stored_d0 := d0;
stored_d1 := d1;
stored_d2 := d2;
stored_d3 := d3;
end if;
q0 <= stored_d0 after 5 ns;
q1 <= stored_d1 after 5 ns;
q2 <= stored_d2 after 5 ns;
q3 <= stored_d3 after 5 ns;
wait on d0, d1, d2, d3, en, clk;
end process storage;
end architecture behav;
|
gpl-2.0
|
9fa655e5ca102a7479e210c5feda6c41
| 0.602221 | 3.716019 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc465.vhd
| 4 | 3,468 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc465.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00465ent IS
END c03s02b01x01p19n01i00465ent;
ARCHITECTURE c03s02b01x01p19n01i00465arch OF c03s02b01x01p19n01i00465ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type severity_level_vector is array (natural range <>) of severity_level;
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
constant C66: severity_level_vector_range := (others => note);
function complex_scalar(s : severity_level_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return severity_level_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : severity_level_vector_range;
signal S2 : severity_level_vector_range;
signal S3 : severity_level_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00465"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00465 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00465arch;
|
gpl-2.0
|
cb5b7be79a64f360b4474708b0b8cb7d
| 0.659746 | 3.685441 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2260.vhd
| 4 | 6,740 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2260.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p05n01i02260ent IS
END c07s02b06x00p05n01i02260ent;
ARCHITECTURE c07s02b06x00p05n01i02260arch OF c07s02b06x00p05n01i02260ent IS
BEGIN
TESTING: PROCESS
constant rem11 : integer := (1 - 4) rem (1 - 4);
constant rem12 : integer := (1 - 4) rem (2 - 4);
constant rem13 : integer := (1 - 4) rem (3 - 4);
constant rem15 : integer := (1 - 4) rem (5 - 4);
constant rem16 : integer := (1 - 4) rem (6 - 4);
constant rem17 : integer := (1 - 4) rem (7 - 4);
constant rem18 : integer := (1 - 4) rem (8 - 4);
constant rem19 : integer := (1 - 4) rem (9 - 4);
constant rem41 : integer := (4 - 4) rem (1 - 4);
constant rem42 : integer := (4 - 4) rem (2 - 4);
constant rem43 : integer := (4 - 4) rem (3 - 4);
constant rem45 : integer := (4 - 4) rem (5 - 4);
constant rem46 : integer := (4 - 4) rem (6 - 4);
constant rem47 : integer := (4 - 4) rem (7 - 4);
constant rem48 : integer := (4 - 4) rem (8 - 4);
constant rem49 : integer := (4 - 4) rem (9 - 4);
constant rem61 : integer := (6 - 4) rem (1 - 4);
constant rem62 : integer := (6 - 4) rem (2 - 4);
constant rem63 : integer := (6 - 4) rem (3 - 4);
constant rem65 : integer := (6 - 4) rem (5 - 4);
constant rem66 : integer := (6 - 4) rem (6 - 4);
constant rem67 : integer := (6 - 4) rem (7 - 4);
constant rem68 : integer := (6 - 4) rem (8 - 4);
constant rem69 : integer := (6 - 4) rem (9 - 4);
variable four : integer := 4;
BEGIN
assert rem11 = (1 - four) rem (1 - four);
assert rem12 = (1 - four) rem (2 - four);
assert rem13 = (1 - four) rem (3 - four);
assert rem15 = (1 - four) rem (5 - four);
assert rem16 = (1 - four) rem (6 - four);
assert rem17 = (1 - four) rem (7 - four);
assert rem18 = (1 - four) rem (8 - four);
assert rem19 = (1 - four) rem (9 - four);
assert rem41 = (4 - four) rem (1 - four);
assert rem42 = (4 - four) rem (2 - four);
assert rem43 = (4 - four) rem (3 - four);
assert rem45 = (4 - four) rem (5 - four);
assert rem46 = (4 - four) rem (6 - four);
assert rem47 = (4 - four) rem (7 - four);
assert rem48 = (4 - four) rem (8 - four);
assert rem49 = (4 - four) rem (9 - four);
assert rem61 = (6 - four) rem (1 - four);
assert rem62 = (6 - four) rem (2 - four);
assert rem63 = (6 - four) rem (3 - four);
assert rem65 = (6 - four) rem (5 - four);
assert rem66 = (6 - four) rem (6 - four);
assert rem67 = (6 - four) rem (7 - four);
assert rem68 = (6 - four) rem (8 - four);
assert rem69 = (6 - four) rem (9 - four);
assert NOT((rem11 = (1 - four) rem (1 - four)) and
( rem12 = (1 - four) rem (2 - four)) and
( rem13 = (1 - four) rem (3 - four)) and
( rem15 = (1 - four) rem (5 - four)) and
( rem16 = (1 - four) rem (6 - four)) and
( rem17 = (1 - four) rem (7 - four)) and
( rem18 = (1 - four) rem (8 - four)) and
( rem19 = (1 - four) rem (9 - four)) and
( rem41 = (4 - four) rem (1 - four)) and
( rem42 = (4 - four) rem (2 - four)) and
( rem43 = (4 - four) rem (3 - four)) and
( rem45 = (4 - four) rem (5 - four)) and
( rem46 = (4 - four) rem (6 - four)) and
( rem47 = (4 - four) rem (7 - four)) and
( rem48 = (4 - four) rem (8 - four)) and
( rem49 = (4 - four) rem (9 - four)) and
( rem61 = (6 - four) rem (1 - four)) and
( rem62 = (6 - four) rem (2 - four)) and
( rem63 = (6 - four) rem (3 - four)) and
( rem65 = (6 - four) rem (5 - four)) and
( rem66 = (6 - four) rem (6 - four)) and
( rem67 = (6 - four) rem (7 - four)) and
( rem68 = (6 - four) rem (8 - four)) and
( rem69 = (6 - four) rem (9 - four)) )
report "***PASSED TEST: c07s02b06x00p05n01i02260"
severity NOTE;
assert (( rem11 = (1 - four) rem (1 - four)) and
( rem12 = (1 - four) rem (2 - four)) and
( rem13 = (1 - four) rem (3 - four)) and
( rem15 = (1 - four) rem (5 - four)) and
( rem16 = (1 - four) rem (6 - four)) and
( rem17 = (1 - four) rem (7 - four)) and
( rem18 = (1 - four) rem (8 - four)) and
( rem19 = (1 - four) rem (9 - four)) and
( rem41 = (4 - four) rem (1 - four)) and
( rem42 = (4 - four) rem (2 - four)) and
( rem43 = (4 - four) rem (3 - four)) and
( rem45 = (4 - four) rem (5 - four)) and
( rem46 = (4 - four) rem (6 - four)) and
( rem47 = (4 - four) rem (7 - four)) and
( rem48 = (4 - four) rem (8 - four)) and
( rem49 = (4 - four) rem (9 - four)) and
( rem61 = (6 - four) rem (1 - four)) and
( rem62 = (6 - four) rem (2 - four)) and
( rem63 = (6 - four) rem (3 - four)) and
( rem65 = (6 - four) rem (5 - four)) and
( rem66 = (6 - four) rem (6 - four)) and
( rem67 = (6 - four) rem (7 - four)) and
( rem68 = (6 - four) rem (8 - four)) and
( rem69 = (6 - four) rem (9 - four)) )
report "***FAILED TEST: c07s02b06x00p05n01i02260 - Constant integer type rem test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p05n01i02260arch;
|
gpl-2.0
|
562a803997709c14455ec93fa4733ba3
| 0.498516 | 3.164319 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1606.vhd
| 4 | 2,391 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1606.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01606ent IS
END c08s11b00x00p04n01i01606ent;
ARCHITECTURE c08s11b00x00p04n01i01606arch OF c08s11b00x00p04n01i01606ent IS
BEGIN
TESTING: PROCESS
-- local variables
variable GONE_THROUGH_ONCE : BOOLEAN := FALSE;
variable k : integer := 0;
BEGIN
for I in 0 to 10 loop
-- Check to see if we have gone through this more than once.
if (not(GONE_THROUGH_ONCE)) then
GONE_THROUGH_ONCE := TRUE;
else
assert (FALSE)
report "Going through loop more than once.";
end if;
-- Exit the loop.
exit when TRUE;
k := 1;
-- The following should never be executed.
assert (FALSE)
report "This statement should NEVER be executed.";
end loop;
-- Verify that we went through at least once.
assert( GONE_THROUGH_ONCE )
report "Did not go through the loop at all.";
assert NOT(k=0)
report "***PASSED TEST: c08s11b00x00p04n01i01606"
severity NOTE;
assert (k=0)
report "***FAILED TEST: c08s11b00x00p04n01i01606 - The loop should terminate when the condition is TRUE."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01606arch;
|
gpl-2.0
|
1176744baee3987c8e9644c4351bd320
| 0.651192 | 3.856452 | false | true | false | false |
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